| created | 2024-04-12T11:12:10Z |
|---|---|
| begin | 2024-04-07T00:00:00Z |
| end | 2024-04-08T00:00:00Z |
| path | src/sys |
| commits | 4 |
| date | 2024-04-07T00:58:57Z | |||
|---|---|---|---|---|
| author | jsg | |||
| files | src/sys/dev/pci/pcidevs | log | diff | annotate |
| message |
another two Alder Lake-N DesignWare I2C ids Not in the Intel datasheet but are matched by their Windows driver. Seen on Surface Go 4. ok mglocker@ |
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| date | 2024-04-07T00:59:23Z | |||
|---|---|---|---|---|
| author | jsg | |||
| files | src/sys/dev/pci/pcidevs.h | log | diff | annotate |
| src/sys/dev/pci/pcidevs_data.h | log | diff | annotate | |
| message | regen | |||
| date | 2024-04-07T01:04:58Z | |||
|---|---|---|---|---|
| author | jsg | |||
| files | src/sys/dev/pci/dwiic_pci.c | log | diff | annotate |
| message |
match another two Alder Lake-N DesignWare I2C ids Not in the Intel datasheet but are matched by their Windows driver. ok mglocker@ who tested on Surface Go 4. |
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| date | 2024-04-07T21:08:59Z | |||
|---|---|---|---|---|
| author | kettenis | |||
| files | src/sys/arch/riscv64/dev/mainbus.c | log | diff | annotate |
| src/sys/arch/riscv64/dev/simplebus.c | log | diff | annotate | |
| message |
The RISC-V architecture has cache-coherent DMA... until it doesn't. This is indicated by a "dma-noncoherent" property on the bus or device nodes in the device tree. Set the BUS_DMA_COHERENT flag on the DMA tag for mainbus(4) and modify the flags based on the presence of "dma-coherent" and "dma-noncoherent" properties where appropriate. ok patrick@ |
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