| created | 2024-03-24T00:26:54Z |
|---|---|
| begin | 2024-03-18T00:00:00Z |
| end | 2024-03-19T00:00:00Z |
| path | src/sys |
| commits | 6 |
| date | 2024-03-18T06:05:23Z | |||
|---|---|---|---|---|
| author | dlg | |||
| files | src/sys/net/if_aggr.c | log | diff | annotate |
| message |
use high bits from the mbuf flowid to pick a port to transmit on. a port here is a physical interface used by an aggr. this leaves the low bits for a physical interface to use to pick a tx ring. without this, aggr used low bits for port selection, which takes bits away from the ring selection, which can lead to uneven distribution of packets over tx rings. ive been running this in production for well over a year now. |
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| date | 2024-03-18T06:14:50Z | |||
|---|---|---|---|---|
| author | dlg | |||
| files | src/sys/net/if_aggr.c | log | diff | annotate |
| message |
expose per port information via kstats. the most interesting information exposed here is the number of times a port changes state according to the lacp state machine. if a port is flapping, it's hard to see if you only look at the current state. getting a count of changes over time makes problems a lot more visible and therefore fixable. this also exposes counters around how the lacp protocol packets. all of these can be useful when trying to line up behaviors with another system (eg, a switch). ok jmatthew@ |
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| date | 2024-03-18T18:35:21Z | |||
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| author | kettenis | |||
| files | src/sys/arch/arm64/arm64/cpu.c | log | diff | annotate |
| src/sys/arch/arm64/include/armreg.h | log | diff | annotate | |
| message |
Add support for the new layout of the CCSIDR_EL1 register that was introduced in Armv8.3 when the CCIDX feature is advertised. This makes us properly detect the cache size on newer CPU cores like Neoverse N2, at least when emulated by QEMU. ok jsg@ |
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| date | 2024-03-18T21:20:46Z | |||
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| author | kettenis | |||
| files | src/sys/dev/pci/pci.c | log | diff | annotate |
| message |
Reduce dmesg spam and only print about resource conflicts for resources that are actually enabled. ok dlg@, deraadt@ |
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| date | 2024-03-18T21:37:44Z | |||
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| author | patrick | |||
| files | src/sys/dev/fdt/if_mvpp.c | log | diff | annotate |
| message | Pass PHY OF node to the MII layer for use by PHY drivers. | |||
| date | 2024-03-18T21:57:22Z | |||
|---|---|---|---|---|
| author | kettenis | |||
| files | src/sys/arch/arm64/arm64/cpu.c | log | diff | annotate |
| src/sys/dev/fdt/psci.c | log | diff | annotate | |
| src/sys/dev/fdt/pscivar.h | log | diff | annotate | |
| message |
Implement Spectre-V4 mitigations. The only real effect of this change is that we now make a firmware call to enable the mitigations if the firmware tells us mitigations are implemented and needed. But according to the specification these mitigations should be enabled by default. The open source TF-A implementation only implements mitigations for older Cortex-A76 cores. Newer Cortex-A76 revisions are not vulnerable and as far as I can tell we only support SoCs with the newer cores. ok patrick@ |
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