| created | 2024-02-18T02:44:07Z |
|---|---|
| begin | 2024-02-12T00:00:00Z |
| end | 2024-02-13T00:00:00Z |
| path | src/sys |
| commits | 5 |
| date | 2024-02-12T01:18:17Z | |||
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| author | guenther | |||
| files | src/sys/arch/amd64/amd64/cpu.c | log | diff | annotate |
| src/sys/arch/amd64/amd64/genassym.cf | log | diff | annotate | |
| src/sys/arch/amd64/amd64/locore.S | log | diff | annotate | |
| src/sys/arch/amd64/amd64/vector.S | log | diff | annotate | |
| src/sys/arch/amd64/amd64/vmm_machdep.c | log | diff | annotate | |
| src/sys/arch/amd64/include/codepatch.h | log | diff | annotate | |
| src/sys/arch/amd64/include/cpu.h | log | diff | annotate | |
| message |
Retpolines are an anti-pattern for IBT, so we need to shift protecting userspace from cross-process BTI to the kernel. Have each CPU track the last pmap run on in userspace and the last vmm VCPU in guest-mode and use the IBPB msr to flush predictors right before running in userspace on a different pmap or entering guest-mode on a different VCPU. Codepatch-nop the userspace bits and conditionalize the vmm bits to keep working if IBPB isn't supported. ok deraadt@ kettenis@ |
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| date | 2024-02-12T02:57:14Z | |||
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| author | jsg | |||
| files | src/sys/arch/amd64/amd64/cpu.c | log | diff | annotate |
| src/sys/arch/amd64/amd64/vmm_machdep.c | log | diff | annotate | |
| message |
Intel and AMD use different cpuid bits for MSR_PRED_CMD IBPB ok guenther@ |
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| date | 2024-02-12T21:37:25Z | |||
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| author | uaa | |||
| files | src/sys/dev/fdt/ehci_fdt.c | log | diff | annotate |
| message |
add Allwinner H616 support (and errata fix) ok kettenis@ |
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| date | 2024-02-12T22:07:33Z | |||
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| author | cheloha | |||
| files | src/sys/kern/kern_clock.c | log | diff | annotate |
| src/sys/kern/kern_clockintr.c | log | diff | annotate | |
| message |
kernel: disable hardclock() on secondary CPUs There is no useful work left for secondary CPUs to do in hardclock(). Disable cq_hardclock on secondary CPUs and remove the now-unnecessary early-return from hardclock(). This change reduces every system's normal clock interrupt rate by (HZ - HZ/10) per secondary CPU. For example, an 8-core machine with a HZ=100 kernel should see its clock interrupt rate drop from ~1600 to ~960. Thread: https://marc.info/?l=openbsd-tech&m=170750140915898&w=2 ok kettenis@ |
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| date | 2024-02-12T22:48:27Z | |||
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| author | mvs | |||
| files | src/sys/kern/uipc_socket.c | log | diff | annotate |
| src/sys/kern/uipc_socket2.c | log | diff | annotate | |
| src/sys/sys/socketvar.h | log | diff | annotate | |
| message |
Pass protosw instead of domain structure to soalloc() to get real `pr_type'. The corresponding domain is referenced as `pr_domain'. Otherwise dp->dom_protosw->pr_type of inet sockets always points to inetsw[0]. ok bluhm |
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