created | 2023-07-15T20:16:42Z |
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begin | 2023-07-09T00:00:00Z |
end | 2023-07-10T00:00:00Z |
path | src/sys |
commits | 7 |
date | 2023-07-09T08:02:13Z | |||
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author | tobhe | |||
files | src/sys/dev/hid/hidkbd.c | log | diff | annotate |
src/sys/dev/usb/makemap.awk | log | diff | annotate | |
message |
Add suspend key support in wskbd and make it work on Apple ARM laptops. feedback and ok miod@ |
date | 2023-07-09T08:02:14Z | |||
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author | tobhe | |||
files | src/sys/dev/wscons/wskbd.c | log | diff | annotate |
src/sys/dev/wscons/wsksymdef.h | log | diff | annotate | |
message |
Add suspend key support in wskbd and make it work on Apple ARM laptops. feedback and ok miod@ |
date | 2023-07-09T08:04:09Z | |||
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author | tobhe | |||
files | src/sys/dev/usb/ukbdmap.c | log | diff | annotate |
message | regen |
date | 2023-07-09T12:32:22Z | |||
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author | kettenis | |||
files | src/sys/dev/fdt/sncodec.c | log | diff | annotate |
message |
Add mute control. This makes the mute button on laptops that use sncodec(4) work. ok tobhe@ |
date | 2023-07-09T16:33:49Z | |||
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author | patrick | |||
files | src/sys/dev/fdt/rkclock.c | log | diff | annotate |
src/sys/dev/fdt/rkclock_clocks.h | log | diff | annotate | |
message |
Add some more RK3588 PCIe clocks and resets. ok kettenis@ |
date | 2023-07-09T19:06:48Z | |||
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author | bluhm | |||
files | src/sys/netinet6/in6_ifattach.c | log | diff | annotate |
message |
Fix route entry leak. In in6_ifdetach() two struct rtentry were leaked. This was triggered by regress/sbin/route and detected with btrace(8) refcnt. The reference returned by rtalloc() must be freed with rtfree() in all cases. OK phessler@ mvs@ |
date | 2023-07-09T19:11:30Z | |||
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author | patrick | |||
files | src/sys/dev/fdt/rkpciephy.c | log | diff | annotate |
message |
It turns out that there are seperate pins for the PCIe Gen 2 and 3, which means that the x4 PCIe controller can get all PCIe Gen 3 lines, while the others then only get PCIe Gen 2 lines. Therefore the decision on how to configure the mux needs to be adjusted so that the PCIe Gen 3 lines are only routed to other PCIe controllers when they are explicitly configured for them. While there, fix an obvious typo. ok kettenis@ |