| created | 2022-03-13T19:42:32Z |
|---|---|
| begin | 2022-03-11T00:00:00Z |
| end | 2022-03-11T06:45:22Z |
| path | src/sys |
| commits | 1 |
| date | 2022-03-11T06:45:22Z | |||
|---|---|---|---|---|
| author | anton | |||
| files | src/sys/dev/acpi/pluart_acpi.c | log | diff | annotate |
| src/sys/dev/fdt/pluart_fdt.c | log | diff | annotate | |
| src/sys/dev/ic/pluart.c | log | diff | annotate | |
| src/sys/dev/ic/pluartvar.h | log | diff | annotate | |
| message |
Enable PL011 UART FIF0 support in pluart(4). The FIFO depth depends on the revision and ranges from 16 to 32 bytes. Special treatment of Server Base System Architecture (SBSA) generic UART devices is required as presence of the interrupt trigger level register is not guaranteed. Therefore treat such devices of having a 1-byte FIFO. With help from kettenis@ and ok visa@ |
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