OpenBSD cvs log

created 2021-11-06T23:47:18Z
begin 2021-10-31T00:00:00Z
end 2021-11-01T00:00:00Z
path src/sys
commits 12

date 2021-10-31T12:17:54Z
author stsp
files src/sys/dev/usb/if_run.c log diff annotate
message Raise SPL to IPL_NET in run_next_scan() to avoid splassert failures.

Problem found and fix tested by krw@.
ok krw@

date 2021-10-31T12:22:48Z
author stsp
files src/sys/dev/usb/usbdevs log diff annotate
message Add USB device ID for the Sony UWA-BR100. Patch by martingot@protonmail

date 2021-10-31T12:23:17Z
author stsp
files src/sys/dev/usb/usbdevs.h log diff annotate
src/sys/dev/usb/usbdevs_data.h log diff annotate
message regen

date 2021-10-31T12:24:02Z
author stsp
files src/sys/dev/usb/if_athn_usb.c log diff annotate
message Make athn(4) attach to the Sony UWA-BR100. Patch by martingot@protonmail

date 2021-10-31T14:41:00Z
author patrick
files src/sys/dev/pci/pcidevs log diff annotate
message Add another PCI id for Intel 2.5Gb adapters.

date 2021-10-31T14:41:53Z
author patrick
files src/sys/dev/pci/pcidevs.h log diff annotate
src/sys/dev/pci/pcidevs_data.h log diff annotate
message regen

date 2021-10-31T14:52:57Z
author patrick
files src/sys/dev/pci/files.pci log diff annotate
src/sys/dev/pci/if_igc.c log diff annotate
src/sys/dev/pci/if_igc.h log diff annotate
src/sys/dev/pci/igc_api.c log diff annotate
src/sys/dev/pci/igc_api.h log diff annotate
src/sys/dev/pci/igc_base.c log diff annotate
src/sys/dev/pci/igc_base.h log diff annotate
src/sys/dev/pci/igc_defines.h log diff annotate
src/sys/dev/pci/igc_hw.h log diff annotate
src/sys/dev/pci/igc_i225.c log diff annotate
src/sys/dev/pci/igc_i225.h log diff annotate
src/sys/dev/pci/igc_mac.c log diff annotate
src/sys/dev/pci/igc_mac.h log diff annotate
src/sys/dev/pci/igc_nvm.c log diff annotate
src/sys/dev/pci/igc_nvm.h log diff annotate
src/sys/dev/pci/igc_phy.c log diff annotate
src/sys/dev/pci/igc_phy.h log diff annotate
src/sys/dev/pci/igc_regs.h log diff annotate
message Add igc(4), a driver for the Intel 2.5Gb Ethernet controllers.

Ported by kevlo@
ok jmatthew@

date 2021-10-31T15:02:25Z
author patrick
files src/sys/dev/pci/if_igc.c log diff annotate
message Move the fill and the tail pointer change to a later point, to make sure
that the RDT is written, and that it is written not too early. Doing it
before writing IGC_RXDCTL definitely doesn't work.

The tail pointer needs to be set to the next empty slot, so it has to be
"last desc filled + 1".

Make sure sure that the rss mapping does not happen in the middle of the
RX checksum block, and that it happens only if nqueues > 1. Also disable
storing bad packets.

With this, igc(4) receives packets just fine.

ok kevlo@

date 2021-10-31T15:12:00Z
author kettenis
files src/sys/dev/fdt/imxspi.c log diff annotate
src/sys/dev/fdt/mvspi.c log diff annotate
src/sys/dev/spi/spivar.h log diff annotate
message Extend the SPI bus API a bit. The config structure gets an sc_cs_delay
member to allow us to specify a delay between assert the CS# signal and
starting the clock. And the transfer function gains a flags argument,
which can be used to specify a new SPI_KEEP_CS flag to keep CS# asserted
after the transfer. This allows us to do another transfer immediately
afterwards without de-asserting CS# which is necessary for sending
commands to the upcoming Apple M1 keyboard/touchpad driver.

ok patrick@

date 2021-10-31T15:22:40Z
author patrick
files src/sys/dev/pci/if_igc.c log diff annotate
message Implement transmit and transmit completion path.

date 2021-10-31T15:25:10Z
author patrick
files src/sys/dev/pci/if_igc.c log diff annotate
message Disable both TCP/UDP checksum offloading and VLAN HW tag offloading for now,
as we currently configure neither in the transmit code path.

Found by sf@

date 2021-10-31T16:38:12Z
author kettenis
files src/sys/arch/arm64/conf/GENERIC log diff annotate
src/sys/arch/arm64/conf/RAMDISK log diff annotate
src/sys/arch/arm64/conf/files.arm64 log diff annotate
src/sys/arch/arm64/dev/aplspi.c log diff annotate
message Add aplspi(4), a driver for the SPI controller found on the Apple M1 SoC.

ok patrick@