| created | 2021-09-13T16:17:16Z |
|---|---|
| begin | 2021-09-04T00:00:00Z |
| end | 2021-09-05T00:00:00Z |
| path | src/sys |
| commits | 4 |
| date | 2021-09-04T07:13:14Z | |||
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| author | jasper | |||
| files | src/sys/arch/amd64/amd64/db_trace.c | log | diff | annotate |
| message |
in backtraces, print as many arguments as the function actually has since amd64 is compiled with -msave-args we have all arguments available to print and there's no reason to limit this to six. discussed with kettenis@ |
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| date | 2021-09-04T10:19:28Z | |||
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| author | mglocker | |||
| files | src/sys/dev/usb/dwc2/dwc2_hcd.c | log | diff | annotate |
| src/sys/dev/usb/dwc2/dwc2_hcdddma.c | log | diff | annotate | |
| src/sys/dev/usb/dwc2/dwc2_hcdintr.c | log | diff | annotate | |
| src/sys/dev/usb/dwc2/dwc2_hcdqueue.c | log | diff | annotate | |
| message |
Revert list_move() to list_move_tail() change from last commit since it turned out that it has a negative impact to isoc transfers timing with our driver implementation. |
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| date | 2021-09-04T12:11:45Z | |||
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| author | jmatthew | |||
| files | src/sys/dev/usb/files.usb | log | diff | annotate |
| src/sys/dev/usb/if_uaq.c | log | diff | annotate | |
| message |
Add uaq(4), a driver for Aquantia AQC111U/AQC112U USB ethernet devices. hardware provided by Brad tested with modest success by mlarkin@, kevlo@ and Brad ok kevlo@ |
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| date | 2021-09-04T22:15:33Z | |||
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| author | bluhm | |||
| files | src/sys/arch/amd64/amd64/acpi_wakecode.S | log | diff | annotate |
| src/sys/arch/amd64/amd64/aes_intel.S | log | diff | annotate | |
| src/sys/arch/amd64/amd64/copy.S | log | diff | annotate | |
| src/sys/arch/amd64/amd64/locore.S | log | diff | annotate | |
| src/sys/arch/amd64/amd64/mds.S | log | diff | annotate | |
| src/sys/arch/amd64/amd64/spl.S | log | diff | annotate | |
| src/sys/arch/amd64/amd64/vector.S | log | diff | annotate | |
| src/sys/arch/amd64/amd64/vmm_support.S | log | diff | annotate | |
| src/sys/arch/amd64/include/asm.h | log | diff | annotate | |
| src/sys/arch/amd64/include/profile.h | log | diff | annotate | |
| message |
To mitigate against spectre attacks, AMD processors without the IBRS feature need an lfence instruction after every near ret. Place them after all functions in the kernel which are implemented in assembler. Change the retguard macro so that the end of the lfence instruction is 16-byte aligned now. This prevents that the ret instruction is at the end of a 32-byte boundary. The latter would cause a performance impact on certain Intel processors which have a microcode update to mitigate the jump conditional code erratum. See software techniques for managing speculation on AMD processors revision 9.17.20 mitigation G-5. See Intel mitigations for jump conditional code erratum revision 1.0 november 2019 2.4 software guidance and optimization methods. OK deraadt@ mortimer@ |
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