| created | 2021-06-20T10:35:18Z |
|---|---|
| begin | 2021-06-18T00:00:00Z |
| end | 2021-06-18T06:17:28Z |
| path | src/sys |
| commits | 1 |
| date | 2021-06-18T06:17:28Z | |||
|---|---|---|---|---|
| author | guenther | |||
| files | src/sys/arch/amd64/amd64/genassym.cf | log | diff | annotate |
| src/sys/arch/amd64/amd64/locore.S | log | diff | annotate | |
| src/sys/arch/amd64/amd64/pmap.c | log | diff | annotate | |
| src/sys/arch/amd64/include/cpu.h | log | diff | annotate | |
| src/sys/arch/amd64/include/pmap.h | log | diff | annotate | |
| message |
The pmap needs to know which CPUs to send IPIs when TLB entries need to be invalidated. Instead of keeping a bitset of CPUs in each pmap, have each cpu_info track which pmap it has loaded: replace pmap->pm_cpus with cpu_info->ci_proc_pmap. This reduces the atomic operations (and cache thrashing) and simplifies cpu_switchto() Also, fix a defect in cpu_switchto()'s "am I loading the same cr3?" test: ignore the CR3_REUSE_PCID bit when checking that. This makes switching between kernel threads slightly less costly. over a week in snaps with no complaints looks ok to mlarkin@ kettenis@ mpi@ |
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