| created | 2021-05-23T13:35:21Z |
|---|---|
| begin | 2021-05-20T00:00:00Z |
| end | 2021-05-21T00:00:00Z |
| path | src/sys |
| commits | 6 |
| date | 2021-05-20T04:22:33Z | |||
|---|---|---|---|---|
| author | drahn | |||
| files | src/sys/arch/riscv64/riscv64/cpuswitch.S | log | diff | annotate |
| src/sys/arch/riscv64/riscv64/exception.S | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/fpu.c | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/machdep.c | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/process_machdep.c | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/sig_machdep.c | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/syscall.c | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/trap.c | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/vm_machdep.c | log | diff | annotate | |
| message |
Significant overhaul of the floating point save/restore code. At this point the mechanism should closely resemble the powerpc64 save/restore points with one difference. (reload avoidance) The previous 'aggressive' fpu save code that was (mostly) implemented before and is present on arm32 and arm64. There is one piece from that other design that remains, if pcb->pcb_fpcpu == ci && ci->ci_fpuproc == p after sleep, this will automatically re-activate the FPU state without needing to reload it. To enable this, the pointer pair is not changed on FPU context save to indicate that the CPU still holds the valid content as long as both of those pointers are pointing to each other. Note that if another core steals the FPU conxtex (when we get to SMP) the pcb->pcb_fpcpu will be another cpu, and from that it will know to reload the FPU context. Also optimistically enabling this only makes sense on riscv64 because there is the notion of FPU on and clean. Other implimentations would need to 'fault on' the FPU enable, but could avoid the FPU context load if no other processor has run this FPU context and no other process has use FPU on this core. ok kettenis@ deraadt@ Prior to a couple of fixes. |
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| date | 2021-05-20T08:03:35Z | |||
|---|---|---|---|---|
| author | mpi | |||
| files | src/sys/uvm/uvm_aobj.c | log | diff | annotate |
| message |
Make use of uao_dropswap_range() in uao_free() instead of re-rolling it. ok kettenis@ |
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| date | 2021-05-20T12:34:35Z | |||
|---|---|---|---|---|
| author | bluhm | |||
| files | src/sys/arch/powerpc/powerpc/trap.c | log | diff | annotate |
| message |
We changed powerpc64 to allow write access to write only mappings. Although the page table cannot prevent reads on write only pages, the first access in trap() knows what is is. This should be passed to uvm_fault(). Then regress/sys/kern/fork-exit passes. Copy the new powerpc64 logic to powerpc. OK tobhe@ kettenis@ deraadt@ |
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| date | 2021-05-20T15:14:30Z | |||
|---|---|---|---|---|
| author | drahn | |||
| files | src/sys/arch/riscv64/include/signal.h | log | diff | annotate |
| message |
Significant overhaul of the floating point save/restore code. At this point the mechanism should closely resemble the powerpc64 save/restore points with one difference. (reload avoidance) The previous 'aggressive' fpu save code that was (mostly) implemented before and is present on arm32 and arm64. There is one piece from that other design that remains, if pcb->pcb_fpcpu == ci && ci->ci_fpuproc == p after sleep, this will automatically re-activate the FPU state without needing to reload it. To enable this, the pointer pair is not changed on FPU context save to indicate that the CPU still holds the valid content as long as both of those pointers are pointing to each other. Note that if another core steals the FPU conxtex (when we get to SMP) the pcb->pcb_fpcpu will be another cpu, and from that it will know to reload the FPU context. Also optimistically enabling this only makes sense on riscv64 because there is the notion of FPU on and clean. Other implimentations would need to 'fault on' the FPU enable, but could avoid the FPU context load if no other processor has run this FPU context and no other process has use FPU on this core. ok kettenis@ deraadt@ Prior to a couple of fixes. (this file was missing from original commit) |
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| date | 2021-05-20T17:33:44Z | |||
|---|---|---|---|---|
| author | dv | |||
| files | src/sys/arch/amd64/include/vmmvar.h | log | diff | annotate |
| message |
vmm(4): don't advertise cpu support for TSC_ADJUST msr We don't emulate it, so guests that attempt to read it just get #GP injected anyways. OK mlarkin@ |
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| date | 2021-05-20T18:28:15Z | |||
|---|---|---|---|---|
| author | kettenis | |||
| files | src/sys/arch/riscv64/riscv64/cpu.c | log | diff | annotate |
| message |
Print cache information based on device tree properties like we do on powerpc64. ok deraadt@ |
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