created | 2021-05-23T13:33:11Z |
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begin | 2021-05-19T00:00:00Z |
end | 2021-05-20T00:00:00Z |
path | src/sys |
commits | 17 |
date | 2021-05-19T02:14:11Z | |||
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author | jsg | |||
files | src/sys/dev/pci/pcidevs | log | diff | annotate |
message | add more inteldrm and amdgpu ids |
date | 2021-05-19T02:14:52Z | |||
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author | jsg | |||
files | src/sys/dev/pci/pcidevs.h | log | diff | annotate |
src/sys/dev/pci/pcidevs_data.h | log | diff | annotate | |
message | regen |
date | 2021-05-19T05:20:48Z | |||
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author | jsg | |||
files | src/sys/dev/pci/pcidevs | log | diff | annotate |
message | add Intel 500 Series PCH ids |
date | 2021-05-19T05:21:24Z | |||
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author | jsg | |||
files | src/sys/dev/pci/pcidevs.h | log | diff | annotate |
src/sys/dev/pci/pcidevs_data.h | log | diff | annotate | |
message | regen |
date | 2021-05-19T05:28:09Z | |||
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author | jsg | |||
files | src/sys/dev/pci/azalia.c | log | diff | annotate |
src/sys/dev/pci/dwiic_pci.c | log | diff | annotate | |
src/sys/dev/pci/ichiic.c | log | diff | annotate | |
src/sys/dev/pci/pucdata.c | log | diff | annotate | |
message | match on Intel 500 Series PCH ids |
date | 2021-05-19T16:57:04Z | |||
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author | deraadt | |||
files | src/sys/arch/armv7/conf/RAMDISK | log | diff | annotate |
message | Please sir, I want some more (ramdisk miniroot space) |
date | 2021-05-19T17:39:49Z | |||
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author | kettenis | |||
files | src/sys/arch/riscv64/dev/plic.c | log | diff | annotate |
message |
Bring riscv64 intr.c code in sync with arm64. This brings us: - MSI support - Interfaces to route interrupts to specific CPUs - Proper interrupt barriers - s/riscv_intr_handler/machine_intr_handler/ ok mlarkin@ |
date | 2021-05-19T17:39:50Z | |||
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author | kettenis | |||
files | src/sys/arch/riscv64/include/fdt.h | log | diff | annotate |
src/sys/arch/riscv64/include/intr.h | log | diff | annotate | |
src/sys/arch/riscv64/riscv64/intr.c | log | diff | annotate | |
message |
Bring riscv64 intr.c code in sync with arm64. This brings us: - MSI support - Interfaces to route interrupts to specific CPUs - Proper interrupt barriers - s/riscv_intr_handler/machine_intr_handler/ ok mlarkin@ |
date | 2021-05-19T17:46:36Z | |||
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author | patrick | |||
files | src/sys/arch/amd64/amd64/pmap.c | log | diff | annotate |
message |
Disable global mappings when using PCID. Page table mappings are frequently created and destroyed in the kernel address space. Traditionally, these mappings have been marked as "global" mappings which means that a TLB flush via %cr3 load does not invalidate them. This is ok as these mappings are the same for all processes. With the advent of MELTDOWN, global mappings were disabled for CPUs that are affected by rogue data cache load (RDCL aka MELTDOWN). To compensate for this we started using PCID and the kernel got its own process context identifier. Thus the hardware is allowed to cache kernel mappings again. However, a CPU that supports PCID but is _not_ affected by MELTDOWN (i.e. ARCH_CAPABILTIES.RDCL_NO=1) will now use both: global PTE mappings and PCID. This is a problem if range based TLB invalidations are used to update/ flush cached TLBs after a change to the kernel page tables. The reason is that the invpcid instruction (function 0) that is used to remove the cached TLBs will not remove global mappings. In the non-PCID case invlpg is used instead which does remove global mappings. In the MELTDOWN case, global mappings are not used at all. The solution is to not use global mappings if PCID is active, as the latter should already by enough to let the hardware cache kernel address translations across address space switches and the global flag is not required. From Christian Ehrhardt ok bluhm@ guenther@ mlarkin@ |
date | 2021-05-19T18:10:45Z | |||
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author | kettenis | |||
files | src/sys/kern/tty.c | log | diff | annotate |
message |
In ttyinfo() check that ps_vmspace isn't NULL before calculating the resident set size. This replicates what the sysctl code does and fixes a kernel crash reported by robert@ ok deraadt@ |
date | 2021-05-19T18:42:59Z | |||
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author | bluhm | |||
files | src/sys/arch/powerpc64/include/vmparam.h | log | diff | annotate |
message |
Double the maximum data size limit on powerpc64. Now it is 32 GB and the same as amd64. The machines have large amounts of memory. discussed with kettenis@ |
date | 2021-05-19T19:32:25Z | |||
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author | kettenis | |||
files | src/sys/arch/riscv64/conf/GENERIC | log | diff | annotate |
src/sys/arch/riscv64/conf/files.riscv64 | log | diff | annotate | |
src/sys/arch/riscv64/dev/pci_machdep.c | log | diff | annotate | |
src/sys/arch/riscv64/include/pci_machdep.h | log | diff | annotate | |
message |
Add PCI support. ok deraadt@ |
date | 2021-05-19T20:10:38Z | |||
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author | kettenis | |||
files | src/sys/dev/fdt/pciecam.c | log | diff | annotate |
message |
Only advertise MSI support if there is an MSI controller of some sort. ok patrick@ |
date | 2021-05-19T20:35:02Z | |||
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author | deraadt | |||
files | src/sys/arch/riscv64/riscv64/mem.c | log | diff | annotate |
message | delete useless XXX |
date | 2021-05-19T20:37:16Z | |||
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author | deraadt | |||
files | src/sys/arch/riscv64/riscv64/conf.c | log | diff | annotate |
message | delete useless XXX |
date | 2021-05-19T21:23:20Z | |||
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author | kettenis | |||
files | src/sys/arch/riscv64/riscv64/machdep.c | log | diff | annotate |
message |
Get rid of the do-nothing cache setup code. The RISC-V architecture has no architecturally defined caches (yet) so there is nothing to set up here. Gets rid of some more useless XXX. |
date | 2021-05-19T23:29:42Z | |||
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author | jsg | |||
files | src/sys/arch/riscv64/conf/RAMDISK | log | diff | annotate |
message | add pci to RAMDISK as well |