| created | 2021-05-16T07:46:05Z |
|---|---|
| begin | 2021-05-14T00:00:00Z |
| end | 2021-05-15T00:00:00Z |
| path | src/sys |
| commits | 7 |
| date | 2021-05-14T03:01:24Z | |||
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| author | drahn | |||
| files | src/sys/arch/riscv64/conf/Makefile.riscv64 | log | diff | annotate |
| message |
Enable riscv64 native kernel builds. remove extra targets |
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| date | 2021-05-14T06:48:52Z | |||
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| author | jsg | |||
| files | src/sys/arch/riscv64/dev/mainbus.c | log | diff | annotate |
| src/sys/arch/riscv64/dev/riscv_cpu_intc.c | log | diff | annotate | |
| src/sys/arch/riscv64/dev/simplebus.c | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/ast.c | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/autoconf.c | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/bus_dma.c | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/conf.c | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/cpu.c | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/intr.c | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/machdep.c | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/mem.c | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/pmap.c | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/process_machdep.c | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/sig_machdep.c | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/syscall.c | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/trap.c | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/vm_machdep.c | log | diff | annotate | |
| message | remove uneeded includes | |||
| date | 2021-05-14T06:55:19Z | |||
|---|---|---|---|---|
| author | jsg | |||
| files | src/sys/arch/riscv64/conf/RAMDISK | log | diff | annotate |
| message | add dwge(4) to RAMDISK as well | |||
| date | 2021-05-14T08:10:39Z | |||
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| author | jsg | |||
| files | src/sys/arch/arm64/conf/RAMDISK | log | diff | annotate |
| src/sys/arch/riscv64/conf/RAMDISK | log | diff | annotate | |
| message | remove comment describing GENERIC | |||
| date | 2021-05-14T15:31:01Z | |||
|---|---|---|---|---|
| author | krw | |||
| files | src/sys/kern/subr_disk.c | log | diff | annotate |
| message |
Tweak the two copies of gpt_chk_mbr() to return the index of the MBR 0xEE (DOSPTYP_EFI) partition, or -1 no usable such partition is found. Adopt a consistent idiom to capture the index for future use. Clean up the gpt_chk_mbr() logic to make it clearer what constraints are being applied when looking for the DOSTYP_EFI partition. No intentional functional change. |
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| date | 2021-05-14T16:44:38Z | |||
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| author | cheloha | |||
| files | src/sys/arch/amd64/include/specialreg.h | log | diff | annotate |
| message |
amd64: specialreg.h: add MSR_TSC_ADJUST Where available, the IA32_TSC_ADJUST MSR may be used to make race-free relative adjustments to a logical CPU's TSC. The value in the register is interpreted as a signed 64-bit offset and added to the "real" value of the TSC whenever the TSC MSR is read. That is: RDTSC = REAL_TSC + TSC_ADJUST and: RDMSR TSC = REAL_TSC + TSC_ADJUST For example, if REAL_TSC=1 and TSC_ADJUST=1, then RDTSC would yield 2. Or if REAL_TSC=10 and TSC_ADJUST=-5, then RDTSC would yield 5. Writing TSC_ADJUST does not change the "real" underlying value of the TSC. Said another way setting TSC_ADJUST to zero will always undo any prior adjustment. This property may be useful in fixing desynchronized TSCs. In particular, buggy firmware may erroneously desynchronize a normally synchronized TSC. If this happens, in theory we can do: wrmsr(MSR_TSC_ADJUST, 0); and fix any desynchronization during boot/resume with no fuss. ok mlarkin@ |
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| date | 2021-05-14T21:11:15Z | |||
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| author | krw | |||
| files | src/sys/kern/subr_disk.c | log | diff | annotate |
| message |
Whitespace tweaks and a couple of stray u_int* in gpt_chk_mbr(). No intentional functional change. |
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