| created | 2021-05-12T19:06:11Z |
|---|---|
| begin | 2021-05-05T15:29:19Z |
| end | 2021-05-05T19:26:51Z |
| path | src/sys |
| commits | 1 |
| date | 2021-05-05T19:26:51Z | |||
|---|---|---|---|---|
| author | kettenis | |||
| files | src/sys/arch/riscv64/conf/GENERIC | log | diff | annotate |
| src/sys/arch/riscv64/conf/RAMDISK | log | diff | annotate | |
| src/sys/arch/riscv64/conf/files.riscv64 | log | diff | annotate | |
| src/sys/arch/riscv64/dev/sfcc.c | log | diff | annotate | |
| src/sys/arch/riscv64/include/cpufunc.h | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/bus_dma.c | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/cpu.c | log | diff | annotate | |
| message |
The StarFive JH7100 SoC found on the BeagleV beta boards has most of its peripherals hooked up through a bus that doesn't maintain cache coherency. So in order to use DMA we will need to flush the L2 caches before/after a DMA tranfer. Add a driver for the L2 cache controller for these SoCs and infrastructure to do the necessary cache maintenance. Since this particular L2 cache controller needs physical addresses, this makes the bus_dma(4) code deviate from its arm64 counterpart. ok drahn@ |
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