| created | 2021-05-09T03:56:01Z |
|---|---|
| begin | 2021-05-05T00:00:00Z |
| end | 2021-05-06T00:00:00Z |
| path | src/sys |
| commits | 13 |
| date | 2021-05-05T00:53:08Z | |||
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| author | jsg | |||
| files | src/sys/arch/riscv64/conf/Makefile.riscv64 | log | diff | annotate |
| src/sys/arch/riscv64/conf/files.riscv64 | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/exception.S | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/Attic/trap.S | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/trap.c | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/Attic/trap_machdep.c | log | diff | annotate | |
| message |
rename trap.S exception.S and trap_machdep.c trap.c to match other archs ok kettenis@ |
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| date | 2021-05-05T01:24:57Z | |||
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| author | jsg | |||
| files | src/sys/arch/riscv64/riscv64/exception.S | log | diff | annotate |
| message |
riscv: Clear SUM in SSTATUS for supervisor mode exceptions. From John Baldwin 753bcca440a4d2c95f48536b586131b84c0bb87e in FreeBSD ok kettenis@ mlarkin@ |
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| date | 2021-05-05T01:28:38Z | |||
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| author | jsg | |||
| files | src/sys/arch/riscv64/riscv64/trap.c | log | diff | annotate |
| message |
riscv: Assert that SUM is not set in SSTATUS for exceptions. From John Baldwin 6a3a6fe34bf36b6e745b3e9ad1a991de057729c7 in FreeBSD ok kettenis@ mlarkin@ |
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| date | 2021-05-05T05:47:11Z | |||
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| author | stsp | |||
| files | src/sys/dev/pci/if_iwm.c | log | diff | annotate |
| message |
Enable detailed reports about firmware errors in iwm(4) for the time being. I am getting reports about firmware errors which may be related to Tx agg. |
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| date | 2021-05-05T07:29:00Z | |||
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| author | mpi | |||
| files | src/sys/arch/amd64/amd64/trap.c | log | diff | annotate |
| src/sys/arch/arm64/arm64/trap.c | log | diff | annotate | |
| message |
Unlock top part of the fault handler. ok kettenis@ |
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| date | 2021-05-05T07:29:01Z | |||
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| author | mpi | |||
| files | src/sys/arch/i386/i386/trap.c | log | diff | annotate |
| src/sys/arch/powerpc/powerpc/trap.c | log | diff | annotate | |
| src/sys/arch/powerpc64/powerpc64/trap.c | log | diff | annotate | |
| src/sys/arch/sparc64/sparc64/trap.c | log | diff | annotate | |
| message |
Unlock top part of the fault handler. ok kettenis@ |
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| date | 2021-05-05T09:17:19Z | |||
|---|---|---|---|---|
| author | jsg | |||
| files | src/sys/dev/fdt/dwmmc.c | log | diff | annotate |
| message |
Match on snps,dw-mshc in dwmmc(4) and use clock-frequency for clkbase if the "ciu" clock is missing as mentioned in the devicetree binding. ok kettenis@ |
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| date | 2021-05-05T12:02:21Z | |||
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| author | kettenis | |||
| files | src/sys/arch/arm64/dev/agintc.c | log | diff | annotate |
| message |
Fix definition of GICD_TYPER_LPIS. ok patrick@ |
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| date | 2021-05-05T13:12:26Z | |||
|---|---|---|---|---|
| author | kettenis | |||
| files | src/sys/arch/riscv64/riscv64/bus_dma.c | log | diff | annotate |
| message |
Sync with arm64 version. ok jsg@ |
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| date | 2021-05-05T13:28:56Z | |||
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| author | jsg | |||
| files | src/sys/arch/riscv64/include/bus.h | log | diff | annotate |
| message |
use fence iorw,iorw for bus_space_barrier() ok kettenis@ |
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| date | 2021-05-05T14:13:57Z | |||
|---|---|---|---|---|
| author | kettenis | |||
| files | src/sys/arch/arm64/dev/mainbus.c | log | diff | annotate |
| message | whitespace | |||
| date | 2021-05-05T15:29:19Z | |||
|---|---|---|---|---|
| author | visa | |||
| files | src/sys/arch/mips64/include/cpu.h | log | diff | annotate |
| src/sys/arch/mips64/mips64/pmap.c | log | diff | annotate | |
| src/sys/arch/mips64/mips64/tlbhandler.S | log | diff | annotate | |
| message |
Remove unneeded tlb_set_gbase() that was used with R8000. Pointed out by miod@ |
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| date | 2021-05-05T19:26:51Z | |||
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| author | kettenis | |||
| files | src/sys/arch/riscv64/conf/GENERIC | log | diff | annotate |
| src/sys/arch/riscv64/conf/RAMDISK | log | diff | annotate | |
| src/sys/arch/riscv64/conf/files.riscv64 | log | diff | annotate | |
| src/sys/arch/riscv64/dev/sfcc.c | log | diff | annotate | |
| src/sys/arch/riscv64/include/cpufunc.h | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/bus_dma.c | log | diff | annotate | |
| src/sys/arch/riscv64/riscv64/cpu.c | log | diff | annotate | |
| message |
The StarFive JH7100 SoC found on the BeagleV beta boards has most of its peripherals hooked up through a bus that doesn't maintain cache coherency. So in order to use DMA we will need to flush the L2 caches before/after a DMA tranfer. Add a driver for the L2 cache controller for these SoCs and infrastructure to do the necessary cache maintenance. Since this particular L2 cache controller needs physical addresses, this makes the bus_dma(4) code deviate from its arm64 counterpart. ok drahn@ |
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