| created | 2021-04-04T01:41:03Z |
|---|---|
| begin | 2021-03-29T00:00:00Z |
| end | 2021-03-30T00:00:00Z |
| path | src/sys |
| commits | 3 |
| date | 2021-03-29T12:39:02Z | |||
|---|---|---|---|---|
| author | dv | |||
| files | src/sys/arch/amd64/include/specialreg.h | log | diff | annotate |
| message |
Fix IA32_EPT_VPID_CAP_XO_TRANSLATIONS specification Per Intel SDM (Vol 3D, App. A.10) bit 0 should be read as a 1 if enabled. From Adam Steen. ok mlarkin@ |
|||
| date | 2021-03-29T13:38:01Z | |||
|---|---|---|---|---|
| author | sthen | |||
| files | src/sys/dev/usb/if_umb.c | log | diff | annotate |
| message |
combine umb_products and umb_fccauth_devs into one umb_quirks table ok gerhard@ |
|||
| date | 2021-03-29T17:04:00Z | |||
|---|---|---|---|---|
| author | kettenis | |||
| files | src/sys/arch/arm64/dev/apldart.c | log | diff | annotate |
| message |
Turns out the PCIe DARTs support a full 32-bit device virtual address space. Adjust the region managed by the extend accordingly but avoid the first and last page. The last page collides with the MSI address used by the PCIe controller and not using the first page helps finding bugs. ok patrick@ |
|||