| created | 2021-03-28T04:08:36Z |
|---|---|
| begin | 2021-03-22T00:00:00Z |
| end | 2021-03-23T00:00:00Z |
| path | src/sys |
| commits | 4 |
| date | 2021-03-22T09:52:49Z | |||
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| author | stsp | |||
| files | src/sys/dev/pci/if_iwn.c | log | diff | annotate |
| message |
Let iwn(4) simply clear frames before the firmware's BA window, instead of trying to be smart and clearing already acknowledged frames which are still within the firmware's BA window. This matches what the Linux driver does and makes our driver code simpler. Also, Tx rate control code relies on sequence numbers falling into the BA window so let's skip Tx rate control for frames before this window. Tested by: myself on 6205 and 6300 afresh1, bluhm, and paco on 6300 jmatthew on 5100 Balder Oddson on 6205 |
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| date | 2021-03-22T18:37:26Z | |||
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| author | kn | |||
| files | src/sys/dev/fdt/cwfg.c | log | diff | annotate |
| message |
Update device-tree bindings Using the DTB from our dtb package this driver no longer attaches (on a Pinebook Pro)due to renamed bindings: https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/power/supply/cw2015_battery.yaml Thanks to kettenis and patrick for pointing this out. Follow upstream's rename and acccount for the monitor interval now being milliseconds not seconds anymore. This makes cwfg(4) export values under hw.sensors as expected when using /usr/local/share/dtb/arm64/rockchip/rk3399-pinebook-pro.dtb . Input patrick kettenis OK kettenis |
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| date | 2021-03-22T20:30:21Z | |||
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| author | patrick | |||
| files | src/sys/arch/arm64/dev/acpipci.c | log | diff | annotate |
| src/sys/arch/arm64/dev/pci_machdep.c | log | diff | annotate | |
| src/sys/arch/arm64/dev/pciecam.c | log | diff | annotate | |
| src/sys/arch/arm64/include/pci_machdep.h | log | diff | annotate | |
| src/sys/dev/fdt/dwpcie.c | log | diff | annotate | |
| message |
Load MSI pages through bus_dma(9). Our interrupt controllers for MSIs typically pass the physical address, however retrieved, to our PCIe controller code. This physical address can in practise be directly given to the PCIe, but it is not a given that the CPU and the PCIe controller are able to use the same physical addresses. This is even more obvious with an smmu(4) inbetween, which can change the world view by introducing I/O virtual addresses. Hence for this it is indeed necessary to map those pages, which thanks to integration with bus_dma(9) works easily. For this we remember the PCI devices' DMA tag in the interrupt handle during the MSI map, so that we can use the smmu(4)-hooked DMA tag to load the physical address. While some systems might prefer to implement "trapping" pages for MSIs, to make sure devices cannot trigger other devices' interrupts, we only make sure the whole page is mapped. Having the IOMMU create a mapping for each MSI is a bit wasteful, but for now it's the simplest way to implement it. Discussed with and ok kettenis@ |
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| date | 2021-03-22T20:34:45Z | |||
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| author | patrick | |||
| files | src/sys/arch/arm64/dev/smmu.c | log | diff | annotate |
| message |
Now that MSI pages are properly mapped, all that debug code in smmu(4) can be removed. The only thing left to implement for smmu(4) to work out of the box with PCIe devices is to reserve the PCIe MMIO windows. Let's see how we can do this properly. |
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