| created | 2020-12-27T22:39:41Z |
|---|---|
| begin | 2020-12-24T00:00:00Z |
| end | 2020-12-25T00:00:00Z |
| path | src/sys |
| commits | 10 |
| date | 2020-12-24T01:00:00Z | |||
|---|---|---|---|---|
| author | kevlo | |||
| files | src/sys/dev/pci/if_rge.c | log | diff | annotate |
| src/sys/dev/pci/if_rgereg.h | log | diff | annotate | |
| message |
Add Wake on LAN support to rge(4). Tested by otto@ and myself. |
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| date | 2020-12-24T01:16:14Z | |||
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| author | cheloha | |||
| files | src/sys/kern/kern_synch.c | log | diff | annotate |
| src/sys/sys/systm.h | log | diff | annotate | |
| message |
tsleep(9): add global "nowake" channel for threads avoiding wakeup(9) It would be convenient if there were a channel a thread could sleep on to indicate they do not want any wakeup(9) broadcasts. The easiest way to do this is to add an "int nowake" to kern_synch.c and extern it in sys/systm.h. You use it like this: #include <sys/systm.h> tsleep_nsec(&nowait, ...); There is now no need to handroll a local dead channel, e.g. int chan; tsleep_nsec(&chan, ...); which expands the stack. Local dead channels will be replaced with &nowake in later patches. One possible problem with this "one global channel" approach is sleep queue congestion. If you have lots of threads sleeping on &nowake you might slow down a wakeup(9) on a different channel that hashes into the same queue. Unsure how much of problem this actually is, if at all. NetBSD and FreeBSD have a "pause" interface in the kernel that chooses a suitable channel automatically. To keep things simple and avoid adding a new interface we will start with this global channel. Discussed with mpi@, claudio@, kettenis@, and deraadt@. Basically designed by kettenis@, who vetoed my other proposals. Bugs caught by deraadt@, tb@, and patrick@. |
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| date | 2020-12-24T04:20:48Z | |||
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| author | jsg | |||
| files | src/sys/arch/amd64/amd64/tsc.c | log | diff | annotate |
| message |
handle reported core clock frequency of 0 on newer Intel Comet Lake The 'nominal core crystal clock frequency' from cpuid 0x15 is 0 on Intel model 0xa5 (CML-H CML-S62 CML-S102) and 0xa6 (CML-U62). So act as if 24 MHz was reported like we do on other Skylake/Kaby Lake variants. Comet Lake processors with model 0x8e (CML-U42 CML-Y42) use the same model number used by Kaby Lake and many other parts which was already handled. While we could approximate the crystal frequency with 'Processor Base Frequency' from cpuid 0x16 eax like FreeBSD and Linux do, kettenis@ couldn't get ntpd to sync a clock on a Skylake machine with: CPUID 0x15: eax=2, ebx=134, khz=0 CPUID 0x16: eax=1600, ebx=1600, ecx=100, edx=0 with reported crystal frequency changing from 24000 kHz to 23880 kHz (cpuid 0x16 eax * 1000 * cpuid 0x15 eax / cpuid 0x15 ebx) and TSC frequency changing from 1608000000 to 1599960000. Cannon Lake, Ice Lake, and Tiger Lake are known to return non-zero frequency in cpuid 0x15 so hopefully no other model ids have to be added. James Cook reported hangs on bsd.rd with i7-10710U 06-a6-00 (CML-U62) (which does not have acpihpet) but not with bsd.mp (which does) and has confirmed that both approaches fixed the problem. |
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| date | 2020-12-24T06:34:03Z | |||
|---|---|---|---|---|
| author | deraadt | |||
| files | src/sys/dev/pci/if_rge.c | log | diff | annotate |
| message | ramdisks do not contain WOL | |||
| date | 2020-12-24T10:10:49Z | |||
|---|---|---|---|---|
| author | visa | |||
| files | src/sys/arch/mips64/mips64/pmap.c | log | diff | annotate |
| message |
Initialize mips64 pmap pool using IPL_VM. This moves the pmap closer to MP-safety. A similar change has already been made on some other architectures. |
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| date | 2020-12-24T12:02:21Z | |||
|---|---|---|---|---|
| author | jsg | |||
| files | src/sys/dev/pci/pcidevs | log | diff | annotate |
| message | add some NVMe devices and Intel Comet Lake host bridges | |||
| date | 2020-12-24T12:02:54Z | |||
|---|---|---|---|---|
| author | jsg | |||
| files | src/sys/dev/pci/pcidevs.h | log | diff | annotate |
| src/sys/dev/pci/pcidevs_data.h | log | diff | annotate | |
| message | regen | |||
| date | 2020-12-24T12:47:17Z | |||
|---|---|---|---|---|
| author | kettenis | |||
| files | src/sys/dev/acpi/sdhc_acpi.c | log | diff | annotate |
| message |
Implement capability register overrides based on _DSD properties. ok patrick@ |
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| date | 2020-12-24T14:09:38Z | |||
|---|---|---|---|---|
| author | patrick | |||
| files | src/sys/dev/acpi/sdhc_acpi.c | log | diff | annotate |
| message |
Extract clock frequency from _DSD properties. ok kettenis@ |
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| date | 2020-12-24T14:11:38Z | |||
|---|---|---|---|---|
| author | mglocker | |||
| files | src/sys/dev/usb/xhci.c | log | diff | annotate |
| src/sys/dev/usb/xhcivar.h | log | diff | annotate | |
| message |
Do proper accounting of zero length TDs. Currently a specific number of zero length TDs can cause our free TRBs to run out, causing xhci(4) to return USBD_NOMEM to the USB stack. The issue was reported by Jonathon Fletcher <jonathon.fletcher () gmail ! com> -- Thanks! Reviewed/suggestions by patrick@. ok mpi@ |
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