| created | 2020-12-27T22:17:06Z |
|---|---|
| begin | 2020-12-22T00:00:00Z |
| end | 2020-12-23T00:00:00Z |
| path | src/sys |
| commits | 10 |
| date | 2020-12-22T03:42:03Z | |||
|---|---|---|---|---|
| author | jsg | |||
| files | src/sys/arch/amd64/amd64/cacheinfo.c | log | diff | annotate |
| src/sys/arch/amd64/include/cacheinfo.h | log | diff | annotate | |
| message |
stop showing amd l3 cache information >= zen 2 based amd processors return a value of 9 for l3 cache assoc via cpuid 0x80000006. As that is a reserved value we end up incorrectly claiming the l3 cache is disabled. While it is possible to get l3 cache information via cpuid 0x8000001d when TOPEXT is advertised that will instead give information about the l3 cache available to the core complex (CCX) that the cpu belongs to where previously the amount of l3 available to all core complexes was shown. As we don't detail topology in dmesg or show the mapping of cores to core complexes just stop displaying l3 information. It already isn't shown on intel. ok gkoehler@ |
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| date | 2020-12-22T04:32:08Z | |||
|---|---|---|---|---|
| author | visa | |||
| files | src/sys/arch/loongson/conf/Makefile.loongson | log | diff | annotate |
| message |
Make clang the default compiler on loongson. OK deraadt@ |
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| date | 2020-12-22T06:55:16Z | |||
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| author | dlg | |||
| files | src/sys/dev/pci/if_ixl.c | log | diff | annotate |
| message | name the rx rings like ix does for systat mb | |||
| date | 2020-12-22T11:55:44Z | |||
|---|---|---|---|---|
| author | kettenis | |||
| files | src/sys/arch/powerpc64/include/cpufunc.h | log | diff | annotate |
| src/sys/arch/powerpc64/powerpc64/cpu.c | log | diff | annotate | |
| message |
Clear FSCR register. This gives us a sane default state where all facilities are disabled by default on all CPUs. |
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| date | 2020-12-22T12:59:05Z | |||
|---|---|---|---|---|
| author | kettenis | |||
| files | src/sys/dev/fdt/dwpcie.c | log | diff | annotate |
| message |
Defer hardware initialization in order to give things like PCIe PHYs a chance to attach. Needed for future support of PCIe on Amlogic SoCs. ok patrick@ |
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| date | 2020-12-22T13:24:45Z | |||
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| author | mpi | |||
| files | src/sys/kern/sys_generic.c | log | diff | annotate |
| message |
Implement select(2) and pselect(2) on top of kqueue. The given set of fds are converted to equivalent kevents using EV_SET(2) and passed to the scanning internals of kevent(2): kqueue_scan(). ktrace(1) will now output the converted kevents on top of the usuals set bits to be able to find possible error in the convertion. This switch implies that select(2) and pselect(2) will now query the underlying kqfilters instead of the *_poll() routines. Based on similar work done on DragonFlyBSD with inputs from from visa@, millert@, anton@, cheloha@, thanks! ok visa@ |
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| date | 2020-12-22T13:37:48Z | |||
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| author | bluhm | |||
| files | src/sys/netinet6/ip6_output.c | log | diff | annotate |
| message |
For a while the kerrnel reports EACCES to userland if pf blocks a packet. IPv6 still had the old EHOSTUNREACH code. Use the same errno for dropped IPv6 packets as in IPv4. OK kn@ phessler@ claudio@ florian@ sashan@ |
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| date | 2020-12-22T15:23:51Z | |||
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| author | kettenis | |||
| files | src/sys/dev/fdt/amlclock.c | log | diff | annotate |
| message | Add PCIe clocks. | |||
| date | 2020-12-22T18:17:28Z | |||
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| author | gkoehler | |||
| files | src/sys/arch/powerpc64/powerpc64/trap.c | log | diff | annotate |
| message |
Use SIGILL for the Facility Unavailable Interrupt in usermode. ok kettenis@ |
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| date | 2020-12-22T23:25:37Z | |||
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| author | dlg | |||
| files | src/sys/dev/pci/if_ix.c | log | diff | annotate |
| message |
have the ifrxr info stuff report the buffer size the hw handles. this makes it more consistent with other drivers. |
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