| created | 2021-01-02T19:01:29Z |
|---|---|
| begin | 2020-11-22T00:00:00Z |
| end | 2020-11-23T00:00:00Z |
| path | src/sys |
| commits | 2 |
| date | 2020-11-22T14:06:22Z | |||
|---|---|---|---|---|
| author | otto | |||
| files | src/sys/dev/pci/if_rgereg.h | log | diff | annotate |
| message |
Enabling RGE_ISR_RX_DESC_UNAVAIL causes an interrupt storm, so disable until the root cause is found. ok kevlo@ kettenis@ |
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| date | 2020-11-22T15:18:35Z | |||
|---|---|---|---|---|
| author | patrick | |||
| files | src/sys/arch/arm64/arm64/bus_dma.c | log | diff | annotate |
| message |
ARM64's bus dma coalesces segments when they are physically contiguous, to optimize the amount of segments given to hardware for DMA. The cache maintenance code uses the virtual addresses stored in the segments for flushing, since we have to flush by VA. Unfortunately the coalescing only checks if the physical blocks are contiguous. Thus it is possible that phys-contig but virt-non-contig blocks are coalesced. The cache flush operations are then not aware of this, and will flush the vaddr with the length of the whole physical block, thus running long and then flushing vaddrs that do not belong to the segments. Fix this by making sure the coalescing only occurs if the bus space is coherent, which means we do not do any flushing, or if the vaddrs are contiguous as well. An alternative fix would have been to keep a copy of the mbuf/uio pointers and flush vaddrs extracted from those objects. This fixes a panic seen with mbuf chains, where the physical data was surpisingly contiguous, but the mbufs' data pointers were not. ok drahn@ kettenis@ |
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