created | 2020-11-21T19:49:00Z |
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begin | 2020-07-14T00:00:00Z |
end | 2020-07-15T00:00:00Z |
path | src/sys |
commits | 21 |
date | 2020-07-14T00:43:29Z | |||
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author | krw | |||
files | src/sys/dev/ic/qlw.c | log | diff | annotate |
message |
Set SDEV_NOWIDE and SDEV_NOSYNC on the 'real' link (xs->sc_link) when negotiations fail. |
date | 2020-07-14T04:10:18Z | |||
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author | jmatthew | |||
files | src/sys/dev/pci/files.pci | log | diff | annotate |
src/sys/dev/pci/if_mcx.c | log | diff | annotate | |
message |
Set up a second level flow table for RSS and switch the root flow table entries to forwarding packets to it. The RSS flow table contains flow table entries that match specific types of traffic and send them to TIRs set up to hash on the appropriate fields, then deliver packets through an RQT to all our rx queues. We still only have one queue, but now all we need to do is plug in an intrmap to add more. ok dlg@ |
date | 2020-07-14T06:02:50Z | |||
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author | beck | |||
files | src/sys/kern/vfs_bio.c | log | diff | annotate |
message |
Do not convert the NOCACHE buffers that come from a vnd strategy routine into more delayed writes if the vnd is mounted from a file on an MNT_ASYNC filesystem. This prevents a situaiton where the cleaner can not clean delayed writes out without making more delayed writes, and we end up waiting for the syncer to spit things occasionaly when it runs. noticed and reported by sven falempin <[email protected]> on tech, who validated this fixes his issue. ok krw@ |
date | 2020-07-14T09:41:30Z | |||
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author | kettenis | |||
files | src/sys/arch/powerpc64/include/reg.h | log | diff | annotate |
src/sys/arch/powerpc64/powerpc64/process_machdep.c | log | diff | annotate | |
message | Implement ptrace(2) bits. Still largely untested. |
date | 2020-07-14T09:42:33Z | |||
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author | kettenis | |||
files | src/sys/arch/powerpc64/powerpc64/syscall.c | log | diff | annotate |
message | Remove commented out debug printfs. |
date | 2020-07-14T11:22:11Z | |||
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author | jsg | |||
files | src/sys/dev/pci/drm/ttm/ttm_bo_vm.c | log | diff | annotate |
message |
reduce the diff to linux in local versions of functions brings in changes from 'drm/ttm: stop always moving BOs on the LRU on page fault' 5d50fcbda7b0acd301bb1fc3d828df0aa29237b8 and some other minor changes ok kettenis@ |
date | 2020-07-14T14:33:03Z | |||
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author | deraadt | |||
files | src/sys/kern/tty.c | log | diff | annotate |
src/sys/kern/tty_pty.c | log | diff | annotate | |
message |
A pty write containing VDISCARD, VREPRINT, or various retyping cases of VERASE would perform (sometimes irrelevant) compute in the kernel which can be heavy (especially with our insufficient tty subsystem locking). Use tsleep_nsec for 1 tick in such circumstances to yield cpu, and also bring interruptability to ptcwrite() https://syzkaller.appspot.com/bug?extid=462539bc18fef8fc26cc ok kettenis millert, discussions with greg and anton |
date | 2020-07-14T14:33:06Z | |||
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author | deraadt | |||
files | src/sys/sys/tty.h | log | diff | annotate |
message |
A pty write containing VDISCARD, VREPRINT, or various retyping cases of VERASE would perform (sometimes irrelevant) compute in the kernel which can be heavy (especially with our insufficient tty subsystem locking). Use tsleep_nsec for 1 tick in such circumstances to yield cpu, and also bring interruptability to ptcwrite() https://syzkaller.appspot.com/bug?extid=462539bc18fef8fc26cc ok kettenis millert, discussions with greg and anton |
date | 2020-07-14T15:34:14Z | |||
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author | patrick | |||
files | src/sys/arch/arm/cortex/ampintc.c | log | diff | annotate |
src/sys/arch/arm/cortex/amptimer.c | log | diff | annotate | |
src/sys/arch/arm/include/fdt.h | log | diff | annotate | |
src/sys/arch/arm64/arm64/acpi_machdep.c | log | diff | annotate | |
src/sys/arch/arm64/arm64/intr.c | log | diff | annotate | |
src/sys/arch/arm64/dev/acpipci.c | log | diff | annotate | |
src/sys/arch/arm64/dev/agintc.c | log | diff | annotate | |
src/sys/arch/arm64/dev/ampintc.c | log | diff | annotate | |
src/sys/arch/arm64/dev/bcm2836_intr.c | log | diff | annotate | |
src/sys/arch/arm64/include/fdt.h | log | diff | annotate | |
src/sys/arch/arm64/include/intr.h | log | diff | annotate | |
src/sys/arch/armv7/armv7/intr.c | log | diff | annotate | |
message |
Extend the interrupt API on arm64 and armv7 to be able to pass around a struct cpu_info *. From a driver point of view the fdt_intr_establish_* API now also exist same functions with a *_cpu suffix. Internally the "old" functions now call their *_cpu counterparts, passing NULL as ci. NULL will be interpreted as primary CPU in the interrupt controller code. The internal framework for interrupt controllers has been changed so that the establish methods provided by an interrupt controller function always takes a struct cpu_info *. Some drivers, like imxgpio(4) and rkgpio(4), only have a single interrupt line for multiple pins. On those we simply disallow trying to establish an interrupt on a non-primary CPU, returning NULL. Since we do not have MP yet on armv7, all armv7 interrupt controllers do return NULL if an attempt is made to establish an interrupt on a different CPU. That said, so far there's no way this can happen. If we ever gain MP support, this is a reminder that the interrupt controller drivers have to be adjusted. Prompted by dlg@ ok kettenis@ |
date | 2020-07-14T15:34:15Z | |||
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author | patrick | |||
files | src/sys/arch/armv7/broadcom/bcm2836_intr.c | log | diff | annotate |
src/sys/arch/armv7/include/intr.h | log | diff | annotate | |
src/sys/arch/armv7/marvell/mvmpic.c | log | diff | annotate | |
src/sys/arch/armv7/omap/intc.c | log | diff | annotate | |
src/sys/arch/armv7/omap/intc.h | log | diff | annotate | |
src/sys/arch/armv7/sunxi/sxiintc.c | log | diff | annotate | |
src/sys/arch/armv7/sunxi/sxiintc.h | log | diff | annotate | |
src/sys/dev/fdt/bcm2835_aux.c | log | diff | annotate | |
src/sys/dev/fdt/imxgpio.c | log | diff | annotate | |
src/sys/dev/fdt/mvgicp.c | log | diff | annotate | |
src/sys/dev/fdt/mvicu.c | log | diff | annotate | |
src/sys/dev/fdt/mvkpcie.c | log | diff | annotate | |
src/sys/dev/fdt/rkgpio.c | log | diff | annotate | |
message |
Extend the interrupt API on arm64 and armv7 to be able to pass around a struct cpu_info *. From a driver point of view the fdt_intr_establish_* API now also exist same functions with a *_cpu suffix. Internally the "old" functions now call their *_cpu counterparts, passing NULL as ci. NULL will be interpreted as primary CPU in the interrupt controller code. The internal framework for interrupt controllers has been changed so that the establish methods provided by an interrupt controller function always takes a struct cpu_info *. Some drivers, like imxgpio(4) and rkgpio(4), only have a single interrupt line for multiple pins. On those we simply disallow trying to establish an interrupt on a non-primary CPU, returning NULL. Since we do not have MP yet on armv7, all armv7 interrupt controllers do return NULL if an attempt is made to establish an interrupt on a different CPU. That said, so far there's no way this can happen. If we ever gain MP support, this is a reminder that the interrupt controller drivers have to be adjusted. Prompted by dlg@ ok kettenis@ |
date | 2020-07-14T15:42:19Z | |||
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author | patrick | |||
files | src/sys/arch/arm/include/pci_machdep.h | log | diff | annotate |
src/sys/arch/arm64/dev/acpipci.c | log | diff | annotate | |
src/sys/arch/arm64/dev/pciecam.c | log | diff | annotate | |
src/sys/arch/arm64/include/pci_machdep.h | log | diff | annotate | |
src/sys/arch/armv7/marvell/mvpcie.c | log | diff | annotate | |
src/sys/arch/armv7/vexpress/pciecam.c | log | diff | annotate | |
src/sys/dev/fdt/bcm2711_pcie.c | log | diff | annotate | |
src/sys/dev/fdt/dwpcie.c | log | diff | annotate | |
src/sys/dev/fdt/mvkpcie.c | log | diff | annotate | |
src/sys/dev/fdt/rkpcie.c | log | diff | annotate | |
message |
Implement pci_intr_establish_cpu() on arm64 and armv7. The function pointer in the chipset tag for establishing interrupts now takes a struct cpu_info *. The normal pci_intr_establish() macro passes NULL as ci, which indicates that the primary CPU is to be used. The PCI controller drivers can then simply pass the ci on to our arm64/armv7 interrupt establish "framework". Prompted by dlg@ ok kettenis@ |
date | 2020-07-14T15:52:20Z | |||
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author | patrick | |||
files | src/sys/arch/arm64/dev/ampintc.c | log | diff | annotate |
message |
Add support for routing interrupts to other CPUs in ampintc(4). Most of the supporting code was already there. The driver supports establishing multiple handlers on the same pin. Make sure that a single pin can only be established on a specific core by recording the struct cpu_info * of the first establish, and returning NULL if someone tries to share the pin with a different core. Since the array of CPU masks, used for enabling/disabling interrupt routing to specific cores, is only populated during cpu_boot_secondary_processors(), each core will re-route the interrupts once a core read its mask. Until then, the core will not receive interrupts for that pin. While there, remove a call to ampintc_setipl(), which seems to be a no-op. It tries to set the same value that's already set. Since the function that calls it is supposed to calculate a pin's mask and do the routing, this doesn't seem to be the correct place for such a call. agintc(4) doesn't have it either. Prompted by dlg@ ok kettenis@ |
date | 2020-07-14T16:01:08Z | |||
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author | patrick | |||
files | src/sys/arch/arm64/dev/agintc.c | log | diff | annotate |
message |
Add support for routing interrupts to other CPUs in agintc(4). Most of the supporting code was already there. The driver supports establishing multiple handlers on the same pin. Make sure that a single pin can only be established on a specific core by recording the struct cpu_info * of the first establish, and returning NULL if someone tries to share the pin with a different core. For LPIs, typically used for MSIs, the routing is done by targetting an LPI to a specific "collection". We create a collection per core, indexing it by cpu_number(). For this we need to know a CPU's "processor number", unless GITS_TYPER_PTA is set. Since we now attach CPUs early, and the redistributors are not banked, we can retrieve that information early on. It's important to move this as far up as possible, as it's not as easy as on ampintc(4) to re-route LPIs. To establish an LPI on a different core, we now only have the pass the CPU's number as part of the map command which is sent to the hardware. Prompted by dlg@ ok kettenis@ |
date | 2020-07-14T16:48:13Z | |||
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author | kettenis | |||
files | src/sys/arch/powerpc64/include/tcb.h | log | diff | annotate |
message |
Fix TIB/TCB on powerpc64. Some bright sould decided that the TCB should be 8 bytes in the 64-bit ABI just like in the 32-bit ABI. But that means there is no "spare" word in the TCB that we can use to store a pointer to our struct pthread. So we have to treat powerpc64 special. Also recognize that the thread pointer points 0x7000 bytes after the TCB. Since the TCB is 8 bytes this means that TCB_OFFSET should be 0x7008. Pointed out by guenther@; ok deraadt@ |
date | 2020-07-14T16:54:46Z | |||
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author | kettenis | |||
files | src/sys/arch/powerpc64/powerpc64/trap.c | log | diff | annotate |
message | Put some debug code behin #ifdef TRAP_DEBUG. |
date | 2020-07-14T17:03:13Z | |||
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author | kettenis | |||
files | src/sys/arch/powerpc64/include/pte.h | log | diff | annotate |
src/sys/arch/powerpc64/powerpc64/pmap.c | log | diff | annotate | |
message |
Mark unmanaged kernel mappings as wired and skip them if we need to evict a mapping from the page tables. |
date | 2020-07-14T18:25:22Z | |||
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author | deraadt | |||
files | src/sys/kern/tty.c | log | diff | annotate |
message |
Use a rwlock to protect the ttylist, rather than having ttymalloc/ttyfree callers use spltty. ok kettenis |
date | 2020-07-14T20:37:18Z | |||
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author | kettenis | |||
files | src/sys/arch/powerpc64/include/intr.h | log | diff | annotate |
src/sys/arch/powerpc64/powerpc64/intr.c | log | diff | annotate | |
message | Add FDT interrupt support. |
date | 2020-07-14T20:39:40Z | |||
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author | kettenis | |||
files | src/sys/arch/powerpc64/conf/GENERIC | log | diff | annotate |
src/sys/arch/powerpc64/conf/RAMDISK | log | diff | annotate | |
src/sys/arch/powerpc64/conf/files.powerpc64 | log | diff | annotate | |
src/sys/arch/powerpc64/dev/xics.c | log | diff | annotate | |
message | Add xics(4), a driver for the OPAL virtual ICS. |
date | 2020-07-14T20:40:48Z | |||
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author | kettenis | |||
files | src/sys/arch/powerpc64/dev/phb.c | log | diff | annotate |
message | Make INTx interupts work. |
date | 2020-07-14T20:52:44Z | |||
---|---|---|---|---|
author | kettenis | |||
files | src/sys/arch/powerpc64/powerpc64/machdep.c | log | diff | annotate |
message | Print real/avail mem like we do on all other architectures. |