| created | 2019-12-25T09:49:11Z |
|---|---|
| begin | 2019-12-20T00:00:00Z |
| end | 2019-12-21T00:00:00Z |
| path | src/sys |
| commits | 10 |
| date | 2019-12-20T07:49:31Z | |||
|---|---|---|---|---|
| author | jsg | |||
| files | src/sys/arch/amd64/amd64/acpi_machdep.c | log | diff | annotate |
| src/sys/arch/amd64/amd64/cpu.c | log | diff | annotate | |
| src/sys/arch/amd64/amd64/machdep.c | log | diff | annotate | |
| src/sys/arch/amd64/include/cpu.h | log | diff | annotate | |
| src/sys/arch/amd64/include/specialreg.h | log | diff | annotate | |
| message |
Disable TSX when MSR_ARCH_CAPABILITIES sets TSX_CTRL. Even with the latest microcode this is not set on all CPUs with TSX, but is set on CPUs which don't need MDS mitigations. MDS mitigations also mitigate TSX Asynchronous Abort (TAA) but aren't done if the CPU claims to not be affected by MDS (MDS_NO). According to "Deep Dive: Intel Transactional Synchronization Extensions (Intel TSX) Asynchronous Abort" CPUs requiring additional mitigations for this are: 06-8e-0c Whiskey Lake (ULT refresh) 06-55-0{6,7} 2nd Gen Xeon Scalable Processors based on Cascade Lake 06-9e-0d Coffee Lake R Currently TSX is disabled unconditionally when possible even if TAA_NO is set. ok bluhm@ guenther@ deraadt@ tested by bluhm@ on i5-8365U (06-8e-0c). |
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| date | 2019-12-20T07:55:30Z | |||
|---|---|---|---|---|
| author | jsg | |||
| files | src/sys/arch/i386/i386/acpi_machdep.c | log | diff | annotate |
| src/sys/arch/i386/i386/cpu.c | log | diff | annotate | |
| src/sys/arch/i386/include/cpu.h | log | diff | annotate | |
| src/sys/arch/i386/include/specialreg.h | log | diff | annotate | |
| message |
Disable TSX when MSR_ARCH_CAPABILITIES sets TSX_CTRL. Even with the latest microcode this is not set on all CPUs with TSX, but is set on CPUs which don't need MDS mitigations. MDS mitigations also mitigate TSX Asynchronous Abort (TAA) but aren't done if the CPU claims to not be affected by MDS (MDS_NO). According to "Deep Dive: Intel Transactional Synchronization Extensions (Intel TSX) Asynchronous Abort" CPUs requiring additional mitigations for this are: 06-8e-0c Whiskey Lake (ULT refresh) 06-55-0{6,7} 2nd Gen Xeon Scalable Processors based on Cascade Lake 06-9e-0d Coffee Lake R Currently TSX is disabled unconditionally when possible even if TAA_NO is set. We don't currently do MDS mitigations on i386. Attempt to disable TSX regardless to match amd64. |
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| date | 2019-12-20T09:27:00Z | |||
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| author | stsp | |||
| files | src/sys/net80211/ieee80211_input.c | log | diff | annotate |
| message |
Have net80211 actually update the Rx block ack sequence number window, as well as pulling frames off the Rx block ack reordering queue, when an incoming frame above the current seqnum window forces us to slide the window forward, potentially losing frames within the old window. Leaving the seqnum window out of sync with the queue would cause needlessly long stalls in traffic until the window moved again for some other reason. Problem observed on lossy wifi whenever netstat -W indicated an increasing "input block ack window slides" counter. With this fix, stalled frames can be observed only for a relatively short amount of time whenever one or more frames in the current window are lost. ok mpi@ |
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| date | 2019-12-20T09:28:06Z | |||
|---|---|---|---|---|
| author | stsp | |||
| files | src/sys/net80211/ieee80211_input.c | log | diff | annotate |
| message |
Ignore new Rx block ack agreements until the WPA handshake is done. Some peers will eagerly try to negotiate block ack (asking us to reserve buffer space) before they are done authenticating themselves. No thanks. Just let them try again later. ok mpi@ |
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| date | 2019-12-20T10:16:23Z | |||
|---|---|---|---|---|
| author | stsp | |||
| files | src/sys/dev/ic/ar5008.c | log | diff | annotate |
| message |
Make athn(4) use a constant Tx retry rate while MiRA is probing. Matches what iwm(4) has been doing for a long time to ensure that a good initial Tx rate will be chosen. Tested by Tracey Emery on AR9281. |
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| date | 2019-12-20T10:23:27Z | |||
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| author | stsp | |||
| files | src/sys/dev/pci/if_iwm.c | log | diff | annotate |
| message |
Make iwm(4) clear/set selected bits in the HW_IF_CONFIG register, rather than writing a hard-coded bit pattern to this register. Matches what Intel's Linux driver does, so it should be the right thing to do. Tested on 8265 by Tracey Emery and myself. |
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| date | 2019-12-20T13:25:02Z | |||
|---|---|---|---|---|
| author | visa | |||
| files | src/sys/arch/loongson/loongson/conf.c | log | diff | annotate |
| message | Fix build. | |||
| date | 2019-12-20T13:27:41Z | |||
|---|---|---|---|---|
| author | visa | |||
| files | src/sys/arch/mips64/mips64/pmap.c | log | diff | annotate |
| message |
Convert boolean_t/TRUE/FALSE to int/1/0 in mips64 pmap. Rename variables for clarity while here. OK mpi@ |
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| date | 2019-12-20T13:29:23Z | |||
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| author | visa | |||
| files | src/sys/arch/sgi/sgi/ip27_machdep.c | log | diff | annotate |
| message |
Replace a lonely TRUE. OK mpi@ |
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| date | 2019-12-20T13:34:41Z | |||
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| author | visa | |||
| files | src/sys/arch/loongson/loongson/bus_dma.c | log | diff | annotate |
| src/sys/arch/loongson/loongson/loongson2_machdep.c | log | diff | annotate | |
| src/sys/arch/mips64/mips64/mem.c | log | diff | annotate | |
| src/sys/arch/mips64/mips64/sys_machdep.c | log | diff | annotate | |
| src/sys/arch/mips64/mips64/vm_machdep.c | log | diff | annotate | |
| src/sys/arch/octeon/octeon/bus_dma.c | log | diff | annotate | |
| src/sys/arch/octeon/octeon/machdep.c | log | diff | annotate | |
| src/sys/arch/sgi/sgi/bus_dma.c | log | diff | annotate | |
| src/sys/arch/sgi/sgi/machdep.c | log | diff | annotate | |
| message |
Convert various boolean_t/TRUE/FALSE to int/1/0 in mips64 memory code. OK mpi@ |
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