created | 2019-11-30T15:54:22Z |
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begin | 2019-11-20T00:00:00Z |
end | 2019-11-21T00:00:00Z |
path | src/sys |
commits | 6 |
date | 2019-11-20T14:07:25Z | |||
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author | visa | |||
files | src/sys/arch/mips64/mips64/vm_machdep.c | log | diff | annotate |
message |
Ensure that the kernel stack is properly aligned on mips64. This fixes a panic related to vararg function sppp_auth_send(). The vararg code generated by clang assumes 16-byte stack alignment. pppoe(4)-induced panic seen by many on octeon Fix from miod@ |
date | 2019-11-20T16:14:51Z | |||
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author | patrick | |||
files | src/sys/dev/pci/if_iwm.c | log | diff | annotate |
message |
Correctly match another 9560-based device. From Bryan Vyhmeister |
date | 2019-11-20T16:33:00Z | |||
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author | patrick | |||
files | src/sys/dev/pci/pcidevs | log | diff | annotate |
message | Add PCI IDs for Gemini Lake SD/MMC controllers |
date | 2019-11-20T16:33:30Z | |||
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author | patrick | |||
files | src/sys/dev/pci/pcidevs.h | log | diff | annotate |
src/sys/dev/pci/pcidevs_data.h | log | diff | annotate | |
message | regen |
date | 2019-11-20T16:34:58Z | |||
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author | patrick | |||
files | src/sys/dev/pci/sdhc_pci.c | log | diff | annotate |
message |
Some Intel SD/MMC controllers do not like the voltage being set to 0V, so add a quirk for Apollo Lake, Gemini Lake and 100 Series. Tested by and ok bmercer@ and mlarkin@ for 100 Series Tested by and diff from James Hastings for Apollo and Gemini Lake |
date | 2019-11-20T20:44:22Z | |||
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author | brynet | |||
files | src/sys/dev/pci/ksmn.c | log | diff | annotate |
message |
ksmn(4): Improve the precision of the fractional part of temperatures. Before we were losing some precision in the raw value sensor conversion. raw: 478 before: 59.70 after: 59.75 real: 59.750 raw: 479 before: 59.80 after: 59.88 real: 59.875 raw: 480 before: 60.00 after: 60.00 real: 60.000 Tested on Ryzen 7 2700X, Ryzen 5 2500U, and Zen2 by nte. Diff and feedback from nte |