| created | 2018-11-30T02:08:55Z |
|---|---|
| begin | 2018-08-18T00:00:00Z |
| end | 2018-08-19T00:00:00Z |
| path | src/sys |
| commits | 3 |
| date | 2018-08-18T10:10:19Z | |||
|---|---|---|---|---|
| author | kettenis | |||
| files | src/sys/arch/arm64/dev/agintc.c | log | diff | annotate |
| message |
Support arbitrary number of redistributors. Inspired by an earlier diff from drahn@ ok patrick@, jsg@ |
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| date | 2018-08-18T11:34:08Z | |||
|---|---|---|---|---|
| author | kettenis | |||
| files | src/sys/arch/arm64/arm64/cpu.c | log | diff | annotate |
| message |
Make sure we don't match (and attach) more than the maximum number of supported CPUs. ok deraadt@, patrick@, visa@ |
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| date | 2018-08-18T15:42:19Z | |||
|---|---|---|---|---|
| author | kettenis | |||
| files | src/sys/arch/arm64/arm64/pmap.c | log | diff | annotate |
| message |
Add support for flushing the instruction cache of other processes. This is needed for inserting and removing breakpoints through ptrace(2). The approach here only works for CPUs that have a PIPT instruction cache as we use aliased mappings to invalidate the instruction cache. That doesn't work on CPUs that have a virtually indexed instruction cache. ok deraadt@, visa@ |
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