created | 2018-11-30T01:42:48Z |
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begin | 2018-08-11T00:00:00Z |
end | 2018-08-12T00:00:00Z |
path | src/sys |
commits | 10 |
date | 2018-08-11T10:41:08Z | |||
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author | kettenis | |||
files | src/sys/arch/arm64/dev/agtimer.c | log | diff | annotate |
message |
Use MAXCPUS as the number of elements for the array of per-cpu data. Fixes machines with more than 8 cores. ok jsg@, patrick@ |
date | 2018-08-11T10:42:42Z | |||
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author | kettenis | |||
files | src/sys/arch/arm/cortex/agtimer.c | log | diff | annotate |
message |
Use MAXCPUS as the number of elements for the array of per-cpu data. ok jsg@, patrick@ |
date | 2018-08-11T10:58:39Z | |||
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author | stsp | |||
files | src/sys/net80211/ieee80211_node.c | log | diff | annotate |
message |
Add comment explaining why we read basic MCS set only from beacon/probereq. requested by mpi@ |
date | 2018-08-11T11:16:43Z | |||
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author | kettenis | |||
files | src/sys/arch/arm64/dev/agintc.c | log | diff | annotate |
message |
Fix a couple of bugs in the ITS support code: - Don't dereference sc_prop if we're not handling an LPI. Fixes a crash on qemu when emulating a GICv3 without ITS (and therefore no LPIs(. - Use the true IPL when calculating the priority of an LPI. The old code used a variable that still had the IPL_MPSAFE flag in it. - Write to the right GITS_BASERn instead of ialways writing to GITS_BASER0. - Flush the cache after initializing/modifying the in-memory tables. The GICv3 on the SynQuacer isn't fully coherent and only supports the "non-shareable" attribute for its in-memory tables. So we have to flush the cache to the point of coherency to guarentee that the GIC sees our changes to those tables. Throw in a full memory barrier for good measure. Also add support for the SynQuacer pre-ITS. ok jsg@, patrick@ |
date | 2018-08-11T14:00:33Z | |||
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author | kettenis | |||
files | src/sys/arch/arm64/include/cpu.h | log | diff | annotate |
message |
Bump MAXCPUS from 8 to 24. ok jsg@ |
date | 2018-08-11T16:02:33Z | |||
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author | kettenis | |||
files | src/sys/arch/arm64/stand/efiboot/efiacpi.c | log | diff | annotate |
message | Make GICv3 redistributor support actually work and add ITS support. |
date | 2018-08-11T16:04:49Z | |||
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author | kettenis | |||
files | src/sys/dev/acpi/pluart_acpi.c | log | diff | annotate |
message | Match "ARMH0011". |
date | 2018-08-11T16:16:07Z | |||
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author | beck | |||
files | src/sys/kern/kern_pledge.c | log | diff | annotate |
src/sys/kern/kern_unveil.c | log | diff | annotate | |
src/sys/kern/vfs_syscalls.c | log | diff | annotate | |
src/sys/sys/namei.h | log | diff | annotate | |
src/sys/sys/pledge.h | log | diff | annotate | |
message |
Get rid of PLEDGE_STAT, which was a hack used for unveil. We use UNVEIL_INSPECT instead in the unveil flags for the same purpose, and now add traversed vnodes of a path with UNVEIL_INSPECT instead of with 0 flags and voodoo in unveil_flagmatch. This allows us to uncontort the logic of unveil_flagmatch a bunch. helpful review and ok from semarie@ |
date | 2018-08-11T20:46:48Z | |||
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author | kettenis | |||
files | src/sys/arch/arm64/dev/acpipci.c | log | diff | annotate |
message | Use IORT table to map requester ID into MSI sideband data. |
date | 2018-08-11T22:47:27Z | |||
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author | kettenis | |||
files | src/sys/arch/arm64/dev/acpipci.c | log | diff | annotate |
message | Make legacy interrupts work in more cases. |