| created | 2018-11-29T21:30:21Z |
|---|---|
| begin | 2018-06-05T00:00:00Z |
| end | 2018-06-06T00:00:00Z |
| path | src/sys |
| commits | 7 |
| date | 2018-06-05T05:04:31Z | |||
|---|---|---|---|---|
| author | guenther | |||
| files | src/sys/arch/amd64/amd64/locore.S | log | diff | annotate |
| src/sys/arch/amd64/amd64/spl.S | log | diff | annotate | |
| src/sys/arch/amd64/amd64/vector.S | log | diff | annotate | |
| message |
Split "return to userspace via iretq" from intr_fast_exit into intr_user_exit. Move AST handling from the bottom of alltraps and Xdoreti to the top of the new routine. syscall-return-via-iretq and the FPU #DNA trap jump into intr_user_exit after the AST check (already performed for the former, skipped for the latter) Delete a couple debugging hooks mlarkin@ and I used during Meltdown work tested by many in snaps; thanks to brynet@ for spurious interrrupt testing earlier reviews and comments kettenis@ mlarkin@; prodding from deraadt@ |
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| date | 2018-06-05T06:39:10Z | |||
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| author | guenther | |||
| files | src/sys/arch/amd64/amd64/acpi_machdep.c | log | diff | annotate |
| src/sys/arch/amd64/amd64/cpu.c | log | diff | annotate | |
| src/sys/arch/amd64/amd64/fpu.c | log | diff | annotate | |
| src/sys/arch/amd64/amd64/genassym.cf | log | diff | annotate | |
| src/sys/arch/amd64/amd64/ipifuncs.c | log | diff | annotate | |
| src/sys/arch/amd64/amd64/locore.S | log | diff | annotate | |
| src/sys/arch/amd64/amd64/machdep.c | log | diff | annotate | |
| src/sys/arch/amd64/amd64/mptramp.S | log | diff | annotate | |
| src/sys/arch/amd64/amd64/process_machdep.c | log | diff | annotate | |
| src/sys/arch/amd64/amd64/trap.c | log | diff | annotate | |
| src/sys/arch/amd64/amd64/vector.S | log | diff | annotate | |
| src/sys/arch/amd64/amd64/via.c | log | diff | annotate | |
| src/sys/arch/amd64/amd64/vm_machdep.c | log | diff | annotate | |
| src/sys/arch/amd64/amd64/vmm.c | log | diff | annotate | |
| message |
Switch from lazy FPU switching to semi-eager FPU switching: track whether curproc's xstate ("extended state") is loaded in the CPU or not. - context switch, sendsig(), vmm, and doing CPU crypto in the kernel all check the flag and, if set, save the old thread's state to the PCB, clear the flag, and then load the _blank_ state - when returning to userspace, if the flag is clear then set it and restore the thread's state This simpler tracking also fixes the restoring of FPU state after nested signal handlers. With this, %cr0's TS flag is never set, the FPU #DNA trap can no longer happen, and IPIs are no longer necessary for flushing or syncing FPU state; on the other hand, restoring xstate while returning to userspace means we have to handle xrstor faulting if we could be loading an altered state. If that happens, reset the state, fake a #GP fault (SIGBUS), and recheck for ASTs. While here, regularize fxsave/fxrstor vs xsave/xrstor handling, by using codepatching to switch to xsave/xrstor when present in the CPU. In addition, code patch in use of xsaveopt in most places when the CPU supports that. Use the 64bit-wide variants of the instructions in all cases so that x87 instruction fault IPs are reported correctly. This change has three motivations: 1) with modern clang, SSE registers are used even in rcrt0.o, making lazy FPU switching a smaller benefit vs trap costs 2) the Intel SDM warns that lazy FPU switching may increase power costs 3) post-Spectre rumors suggest that the %cr0 TS flag might not block speculation, permitting leaking of information about FPU state (AES keys?) across protection boundaries. tested by many in snaps; prodding from deraadt@ |
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| date | 2018-06-05T06:39:11Z | |||
|---|---|---|---|---|
| author | guenther | |||
| files | src/sys/arch/amd64/include/codepatch.h | log | diff | annotate |
| src/sys/arch/amd64/include/cpu.h | log | diff | annotate | |
| src/sys/arch/amd64/include/fpu.h | log | diff | annotate | |
| src/sys/arch/amd64/include/intrdefs.h | log | diff | annotate | |
| src/sys/arch/amd64/include/pcb.h | log | diff | annotate | |
| src/sys/arch/amd64/include/proc.h | log | diff | annotate | |
| src/sys/arch/amd64/include/specialreg.h | log | diff | annotate | |
| message |
Switch from lazy FPU switching to semi-eager FPU switching: track whether curproc's xstate ("extended state") is loaded in the CPU or not. - context switch, sendsig(), vmm, and doing CPU crypto in the kernel all check the flag and, if set, save the old thread's state to the PCB, clear the flag, and then load the _blank_ state - when returning to userspace, if the flag is clear then set it and restore the thread's state This simpler tracking also fixes the restoring of FPU state after nested signal handlers. With this, %cr0's TS flag is never set, the FPU #DNA trap can no longer happen, and IPIs are no longer necessary for flushing or syncing FPU state; on the other hand, restoring xstate while returning to userspace means we have to handle xrstor faulting if we could be loading an altered state. If that happens, reset the state, fake a #GP fault (SIGBUS), and recheck for ASTs. While here, regularize fxsave/fxrstor vs xsave/xrstor handling, by using codepatching to switch to xsave/xrstor when present in the CPU. In addition, code patch in use of xsaveopt in most places when the CPU supports that. Use the 64bit-wide variants of the instructions in all cases so that x87 instruction fault IPs are reported correctly. This change has three motivations: 1) with modern clang, SSE registers are used even in rcrt0.o, making lazy FPU switching a smaller benefit vs trap costs 2) the Intel SDM warns that lazy FPU switching may increase power costs 3) post-Spectre rumors suggest that the %cr0 TS flag might not block speculation, permitting leaking of information about FPU state (AES keys?) across protection boundaries. tested by many in snaps; prodding from deraadt@ |
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| date | 2018-06-05T09:29:05Z | |||
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| author | mpi | |||
| files | src/sys/kern/exec_script.c | log | diff | annotate |
| src/sys/kern/kern_descrip.c | log | diff | annotate | |
| src/sys/kern/kern_event.c | log | diff | annotate | |
| src/sys/kern/kern_exec.c | log | diff | annotate | |
| src/sys/kern/sys_pipe.c | log | diff | annotate | |
| src/sys/kern/tty_pty.c | log | diff | annotate | |
| src/sys/kern/uipc_syscalls.c | log | diff | annotate | |
| src/sys/kern/vfs_syscalls.c | log | diff | annotate | |
| src/sys/sys/file.h | log | diff | annotate | |
| src/sys/sys/filedesc.h | log | diff | annotate | |
| message |
Revert introduction of fdinsert(), a sanitify check triggers when closing a LARVAL file. Found the hardway by sthen@. |
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| date | 2018-06-05T09:45:08Z | |||
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| author | jsg | |||
| files | src/sys/arch/arm64/arm64/cpu.c | log | diff | annotate |
| message |
Recognise Cortex A76. Only adding to arm64 as it only supports aarch32 for EL0/userland. MIDR value from ATF. ok kettenis@ |
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| date | 2018-06-05T19:23:01Z | |||
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| author | kettenis | |||
| files | src/sys/arch/arm64/dev/Attic/pluart.c | log | diff | annotate |
| src/sys/arch/armv7/dev/Attic/pluart.c | log | diff | annotate | |
| message |
Unify arm64 and armv7 pluart(4) implementations. ok jsg@ |
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| date | 2018-06-05T20:41:19Z | |||
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| author | kettenis | |||
| files | src/sys/arch/arm64/conf/files.arm64 | log | diff | annotate |
| src/sys/arch/arm64/dev/Attic/pluart.c | log | diff | annotate | |
| src/sys/arch/armv7/conf/files.armv7 | log | diff | annotate | |
| src/sys/arch/armv7/dev/Attic/pluart.c | log | diff | annotate | |
| src/sys/dev/fdt/files.fdt | log | diff | annotate | |
| src/sys/dev/fdt/Attic/pluart.c | log | diff | annotate | |
| message |
Move pluart(4) to dev/fdt. ok jsg@ |
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