--- 7.6/2024-12-05T13:22:15Z/2024-11-25T00:00:00Z/nm-bsd-ot14.txt	Sun Dec  8 08:29:01 2024
+++ 7.6/2024-12-05T13:22:15Z/2024-11-26T00:00:00Z/nm-bsd-ot14.txt	Sun Dec  8 11:09:53 2024
@@ -11520,21 +11520,21 @@ ffffffff815d07e0 T uvm_pagermapin
 ffffffff815d09d0 T uvm_pagermapout
 ffffffff815d0a40 T uvm_mk_pcluster
 ffffffff815d0d10 T uvm_pager_put
-ffffffff815d1000 T uvm_pager_dropcluster
-ffffffff815d1220 T uvm_aio_biodone
-ffffffff815d12c0 T uvm_aio_aiodone
-ffffffff815d14b0 T uvm_aio_aiodone_pages
+ffffffff815d0fa0 T uvm_pager_dropcluster
+ffffffff815d11c0 T uvm_aio_biodone
+ffffffff815d1260 T uvm_aio_aiodone
+ffffffff815d1450 T uvm_aio_aiodone_pages
 ffffffff815d2000 T uvm_wait
 ffffffff815d2140 T uvmpd_tune
 ffffffff815d2200 T uvm_pageout
-ffffffff815d2680 T uvmpd_scan_active
-ffffffff815d28c0 T uvmpd_scan
-ffffffff815d29a0 T uvm_aiodone_daemon
-ffffffff815d2b40 T uvmpd_trylockowner
-ffffffff815d2bd0 T uvmpd_dropswap
-ffffffff815d2c80 T uvmpd_scan_inactive
-ffffffff815d3530 T uvmpd_drop
-ffffffff815d3620 T uvmpd_hibernate
+ffffffff815d2690 T uvmpd_scan_active
+ffffffff815d28d0 T uvmpd_scan
+ffffffff815d29b0 T uvm_aiodone_daemon
+ffffffff815d2b80 T uvmpd_trylockowner
+ffffffff815d2c10 T uvmpd_dropswap
+ffffffff815d2cc0 T uvmpd_scan_inactive
+ffffffff815d3570 T uvmpd_drop
+ffffffff815d3660 T uvmpd_hibernate
 ffffffff815d4000 T uvm_pmr_pg_to_memtype
 ffffffff815d4030 T pow2divide
 ffffffff815d4080 T uvm_pmemrange_addr_cmp
@@ -14272,42 +14272,43 @@ ffffffff81759b70 T virtio_stop_vq_intr
 ffffffff81759c50 T virtio_start_vq_intr
 ffffffff8175a000 T vio_match
 ffffffff8175a030 T vio_attach
-ffffffff8175a8f0 T vio_alloc_dmamem
-ffffffff8175aaa0 T vio_free_dmamem
-ffffffff8175ab40 T vio_alloc_mem
-ffffffff8175b0d0 T vio_get_lladdr
-ffffffff8175b1f0 T vio_put_lladdr
-ffffffff8175b2e0 T vio_rx_intr
-ffffffff8175b3a0 T vio_tx_intr
-ffffffff8175b410 T vio_ctrleof
-ffffffff8175b4e0 T vio_start
-ffffffff8175b9f0 T vio_ioctl
-ffffffff8175bbe0 T vio_media_change
-ffffffff8175bc10 T vio_media_status
-ffffffff8175bce0 T vio_config_change
-ffffffff8175bdd0 T vio_txtick
-ffffffff8175be20 T vio_rxtick
-ffffffff8175beb0 T vio_link_state
-ffffffff8175bf50 T vio_init
-ffffffff8175c0f0 T vio_stop
-ffffffff8175c490 T vio_populate_rx_mbufs
-ffffffff8175c7e0 T vio_iff
-ffffffff8175c9d0 T vio_ctrl_guest_offloads
-ffffffff8175cb60 T vio_rxeof
-ffffffff8175ce20 T vio_ctrl_wakeup
-ffffffff8175ce40 T vio_tx_drain
-ffffffff8175cf60 T vio_rx_drain
-ffffffff8175d070 T vio_tx_offload
-ffffffff8175d240 T vio_txeof
-ffffffff8175d490 T vio_encap
-ffffffff8175d570 T vio_add_rx_mbuf
-ffffffff8175d660 T vio_free_rx_mbuf
-ffffffff8175d6f0 T vio_rx_offload
-ffffffff8175d8a0 T vio_ctrl_start
-ffffffff8175dae0 T vio_ctrl_submit
-ffffffff8175dd10 T vio_ctrl_finish
-ffffffff8175dd60 T vio_ctrl_rx
-ffffffff8175def0 T vio_set_rx_filter
+ffffffff8175aa20 T vio_alloc_dmamem
+ffffffff8175abd0 T vio_free_dmamem
+ffffffff8175ac70 T vio_alloc_mem
+ffffffff8175b210 T vio_get_lladdr
+ffffffff8175b330 T vio_put_lladdr
+ffffffff8175b420 T vio_rx_intr
+ffffffff8175b530 T vio_tx_intr
+ffffffff8175b5c0 T vio_ctrleof
+ffffffff8175b6d0 T vio_start
+ffffffff8175bd60 T vio_ioctl
+ffffffff8175bf50 T vio_media_change
+ffffffff8175bf80 T vio_media_status
+ffffffff8175c050 T vio_config_change
+ffffffff8175c150 T vio_txtick
+ffffffff8175c1e0 T vio_rxtick
+ffffffff8175c2a0 T vio_link_state
+ffffffff8175c340 T vio_init
+ffffffff8175c520 T vio_stop
+ffffffff8175c840 T vio_populate_rx_mbufs
+ffffffff8175cbe0 T vio_iff
+ffffffff8175cdd0 T vio_ctrl_guest_offloads
+ffffffff8175cf60 T vio_rxeof
+ffffffff8175d260 T vio_ctrl_wakeup
+ffffffff8175d280 T vio_tx_drain
+ffffffff8175d420 T vio_rx_drain
+ffffffff8175d530 T vio_tx_offload
+ffffffff8175d700 T vio_tx_dequeue
+ffffffff8175d970 T vio_encap
+ffffffff8175da50 T vio_add_rx_mbuf
+ffffffff8175db40 T vio_free_rx_mbuf
+ffffffff8175dbd0 T vio_rx_offload
+ffffffff8175dd80 T vio_txeof
+ffffffff8175df00 T vio_ctrl_start
+ffffffff8175e140 T vio_ctrl_submit
+ffffffff8175e370 T vio_ctrl_finish
+ffffffff8175e3c0 T vio_ctrl_rx
+ffffffff8175e550 T vio_set_rx_filter
 ffffffff8175f000 T vioblk_match
 ffffffff8175f030 T vioblk_attach
 ffffffff8175f370 T vioblk_scsi_cmd
@@ -18783,21 +18784,22 @@ ffffffff819d5eb0 T virtio_pci_get_status
 ffffffff819d5f20 T virtio_pci_set_status
 ffffffff819d6090 T virtio_pci_negotiate_features
 ffffffff819d61f0 T virtio_pci_poll_intr
-ffffffff819d6270 T virtio_pci_set_msix_queue_vector
-ffffffff819d62f0 T virtio_pci_set_msix_config_vector
-ffffffff819d6330 T virtio_pci_find_cap
-ffffffff819d6500 T virtio_pci_attach_10
-ffffffff819d69d0 T virtio_pci_attach_09
-ffffffff819d6b40 T virtio_pci_adjust_config_region
-ffffffff819d6bf0 T virtio_pci_setup_msix
-ffffffff819d6e00 T virtio_pci_legacy_intr
-ffffffff819d6ed0 T virtio_pci_legacy_intr_mpsafe
-ffffffff819d6f80 T virtio_pci_free_irqs
-ffffffff819d7140 T virtio_pci_negotiate_features_10
-ffffffff819d73f0 T virtio_pci_msix_establish
-ffffffff819d7570 T virtio_pci_config_intr
-ffffffff819d75b0 T virtio_pci_shared_queue_intr
-ffffffff819d75c0 T virtio_pci_queue_intr
+ffffffff819d6270 T virtio_pci_intr_barrier
+ffffffff819d6300 T virtio_pci_set_msix_queue_vector
+ffffffff819d6380 T virtio_pci_set_msix_config_vector
+ffffffff819d63c0 T virtio_pci_find_cap
+ffffffff819d6590 T virtio_pci_attach_10
+ffffffff819d6a60 T virtio_pci_attach_09
+ffffffff819d6bd0 T virtio_pci_adjust_config_region
+ffffffff819d6c80 T virtio_pci_setup_msix
+ffffffff819d6e90 T virtio_pci_legacy_intr
+ffffffff819d6f60 T virtio_pci_legacy_intr_mpsafe
+ffffffff819d7010 T virtio_pci_free_irqs
+ffffffff819d71d0 T virtio_pci_negotiate_features_10
+ffffffff819d7480 T virtio_pci_msix_establish
+ffffffff819d7600 T virtio_pci_config_intr
+ffffffff819d7640 T virtio_pci_shared_queue_intr
+ffffffff819d7650 T virtio_pci_queue_intr
 ffffffff819d8000 T dwiic_pci_match
 ffffffff819d8030 T dwiic_pci_attach
 ffffffff819d8410 T dwiic_pci_activate
@@ -30375,7 +30377,7 @@ ffffffff82094950 t nbio_v7_7_update_medium_grain_light
 ffffffff82094b80 t nbio_v7_7_get_clockgating_state
 ffffffff82094cc0 t nbio_v7_7_ih_control
 ffffffff82094e30 t nbio_v7_7_init_registers
-ffffffff82094f50 t nbio_v7_7_remap_hdp_registers
+ffffffff82095040 t nbio_v7_7_remap_hdp_registers
 ffffffff82096000 t nbio_v7_9_get_hdp_flush_req_offset
 ffffffff82096040 t nbio_v7_9_get_hdp_flush_done_offset
 ffffffff82096080 t nbio_v7_9_get_pcie_index_offset
@@ -36820,20 +36822,20 @@ ffffffff825a4400 t vangogh_get_power_limit
 ffffffff825a4580 t vangogh_get_ppt_limit
 ffffffff825a45f0 t vangogh_get_dpm_clock_table
 ffffffff825a4760 t vangogh_init_smc_tables
-ffffffff825a49e0 t vangogh_system_features_control
-ffffffff825a4a30 t vangogh_set_power_limit
-ffffffff825a4bc0 t vangogh_get_gfxoff_status
-ffffffff825a4c50 t vangogh_get_gfxoff_entrycount
-ffffffff825a4cd0 t vangogh_set_gfxoff_residency
-ffffffff825a4d50 t vangogh_get_gfxoff_residency
-ffffffff825a4d90 t vangogh_mode2_reset
-ffffffff825a4f50 t vangogh_common_get_gpu_metrics
-ffffffff825a5770 t vangogh_post_smu_init
-ffffffff825a5930 t vangogh_set_fine_grain_gfx_freq_parameters
-ffffffff825a59a0 t vangogh_force_dpm_limit_value
-ffffffff825a5b20 t vangogh_get_dpm_ultimate_freq
-ffffffff825a5e50 t vangogh_set_soft_freq_limited_range
-ffffffff825a6010 t vangogh_get_gpu_metrics_v2_3
+ffffffff825a49d0 t vangogh_system_features_control
+ffffffff825a4a20 t vangogh_set_power_limit
+ffffffff825a4bb0 t vangogh_get_gfxoff_status
+ffffffff825a4c40 t vangogh_get_gfxoff_entrycount
+ffffffff825a4cc0 t vangogh_set_gfxoff_residency
+ffffffff825a4d40 t vangogh_get_gfxoff_residency
+ffffffff825a4d80 t vangogh_mode2_reset
+ffffffff825a4f40 t vangogh_common_get_gpu_metrics
+ffffffff825a5760 t vangogh_post_smu_init
+ffffffff825a5920 t vangogh_set_fine_grain_gfx_freq_parameters
+ffffffff825a5990 t vangogh_force_dpm_limit_value
+ffffffff825a5b10 t vangogh_get_dpm_ultimate_freq
+ffffffff825a5e40 t vangogh_set_soft_freq_limited_range
+ffffffff825a6000 t vangogh_get_gpu_metrics_v2_3
 ffffffff825a7000 T renoir_set_ppt_funcs
 ffffffff825a70a0 t renoir_get_current_power_state
 ffffffff825a7120 t renoir_print_clk_levels
@@ -42284,19 +42286,19 @@ ffffffff8284612c r dg2_g12_revid_step_tbl
 ffffffff82847000 r isomappings
 ffffffff82847080 r unimappings
 ffffffff82847230 r replacements
-ffffffff8284aab4 r apollo_pio_rec
-ffffffff82898d01 r apollo_udma33_tim
-ffffffff828ae497 r pp_r600_decoded_lanes
-ffffffff828e5806 r cmd680_setup_channel.udma_tbl
-ffffffff828edda3 r apollo_udma100_tim
-ffffffff828edda9 r cmd0646_9_tim_udma
-ffffffff828fc757 r substchar
-ffffffff82954266 r apollo_udma133_tim
-ffffffff8295426d r apollo_udma66_tim
-ffffffff82954297 r cy_pio_rec
-ffffffff82959ad8 R drm_ca
-ffffffff82959b00 R drm_filtops
-ffffffff82959b30 R drmread_filtops
+ffffffff8284aada r apollo_pio_rec
+ffffffff82898d5f r apollo_udma33_tim
+ffffffff828ae516 r pp_r600_decoded_lanes
+ffffffff828e58c9 r cmd680_setup_channel.udma_tbl
+ffffffff828ede66 r apollo_udma100_tim
+ffffffff828ede6c r cmd0646_9_tim_udma
+ffffffff828fc81a r substchar
+ffffffff82954345 r apollo_udma133_tim
+ffffffff8295434c r apollo_udma66_tim
+ffffffff82954376 r cy_pio_rec
+ffffffff82959bb8 R drm_ca
+ffffffff82959be0 R drm_filtops
+ffffffff82959c10 R drmread_filtops
 ffffffff8295a000 r vga_emulops
 ffffffff8295a048 R vga_stdscreen
 ffffffff8295a078 R vga_stdscreen_mono