--- 7.6/2024-11-01T07:17:09Z/2024-10-11T00:00:00Z/nm-bsd-ot14.txt	Sat Nov  2 12:15:39 2024
+++ 7.6/2024-11-01T07:17:09Z/2024-10-12T00:00:00Z/nm-bsd-ot14.txt	Sat Nov  2 14:53:21 2024
@@ -4260,11 +4260,11 @@ ffffffff812256e0 T ehci_device_bulk_close
 ffffffff812256f0 T ehci_device_bulk_done
 ffffffff812257c0 T ehci_device_isoc_transfer
 ffffffff81225820 T ehci_device_isoc_start
-ffffffff81225b20 T ehci_device_isoc_abort
-ffffffff81225b70 T ehci_device_isoc_close
-ffffffff81225ba0 T ehci_device_isoc_done
-ffffffff81225c20 T ehci_reverse_bits
-ffffffff81225c80 T ehci_init
+ffffffff81225b30 T ehci_device_isoc_abort
+ffffffff81225b80 T ehci_device_isoc_close
+ffffffff81225bb0 T ehci_device_isoc_done
+ffffffff81225c30 T ehci_reverse_bits
+ffffffff81225c90 T ehci_init
 ffffffff81226420 T ehci_reset
 ffffffff81226600 T ehci_alloc_sqh
 ffffffff812267b0 T ehci_intrlist_timeout
@@ -20465,20 +20465,20 @@ ffffffff81aa9cd0 T drm_prime_sg_to_page_array
 ffffffff81aa9d30 T drm_prime_sg_to_dma_addr_array
 ffffffff81aa9d90 T drm_prime_gem_destroy
 ffffffff81aaa000 T __drm_puts_coredump
-ffffffff81aaa100 T __drm_printfn_coredump
-ffffffff81aaa320 T __drm_puts_seq_file
-ffffffff81aaa350 T __drm_printfn_seq_file
-ffffffff81aaa380 T __drm_printfn_info
-ffffffff81aaa3b0 T __drm_printfn_debug
-ffffffff81aaa3e0 T __drm_printfn_err
-ffffffff81aaa420 T drm_puts
-ffffffff81aaa450 T drm_printf
-ffffffff81aaa4e0 T drm_print_bits
-ffffffff81aaa740 T drm_dev_printk
-ffffffff81aaa7e0 T __drm_dev_dbg
-ffffffff81aaa880 T ___drm_dbg
-ffffffff81aaa920 T __drm_err
-ffffffff81aaa9c0 T drm_print_regset32
+ffffffff81aaa110 T __drm_printfn_coredump
+ffffffff81aaa340 T __drm_puts_seq_file
+ffffffff81aaa370 T __drm_printfn_seq_file
+ffffffff81aaa3a0 T __drm_printfn_info
+ffffffff81aaa3d0 T __drm_printfn_debug
+ffffffff81aaa400 T __drm_printfn_err
+ffffffff81aaa440 T drm_puts
+ffffffff81aaa470 T drm_printf
+ffffffff81aaa500 T drm_print_bits
+ffffffff81aaa760 T drm_dev_printk
+ffffffff81aaa800 T __drm_dev_dbg
+ffffffff81aaa8a0 T ___drm_dbg
+ffffffff81aaa940 T __drm_err
+ffffffff81aaa9e0 T drm_print_regset32
 ffffffff81aab000 T drm_crtc_mode_valid
 ffffffff81aab050 T drm_encoder_mode_valid
 ffffffff81aab090 T drm_connector_mode_valid
@@ -26087,53 +26087,53 @@ ffffffff81de2670 T r100_gfx_get_rptr
 ffffffff81de26d0 T r100_gfx_get_wptr
 ffffffff81de2710 T r100_gfx_set_wptr
 ffffffff81de2750 T r100_cp_init
-ffffffff81de2d40 T r100_debugfs_cp_init
-ffffffff81de2d70 T r100_cp_fini
-ffffffff81de2e40 T r100_cp_disable
-ffffffff81de2fa0 T r100_gui_wait_for_idle
-ffffffff81de3090 T r100_reloc_pitch_offset
-ffffffff81de3200 T r100_packet3_load_vbpntr
-ffffffff81de34f0 T r100_cs_parse_packet0
-ffffffff81de3600 T r100_cs_packet_parse_vline
-ffffffff81de3830 T r100_cs_track_check_pkt3_indx_buffer
-ffffffff81de38b0 T r100_cs_parse
-ffffffff81de4ba0 T r100_cs_track_clear
-ffffffff81de4f30 T r100_cs_track_check
-ffffffff81de57f0 T r100_mc_wait_for_idle
-ffffffff81de5890 T r100_gpu_is_lockup
-ffffffff81de5900 T r100_enable_bm
-ffffffff81de5950 T r100_bm_disable
-ffffffff81de5a10 T r100_asic_reset
-ffffffff81de5da0 T r100_mc_stop
-ffffffff81de5f60 T r100_mc_resume
-ffffffff81de6020 T r100_set_common_regs
-ffffffff81de61d0 T r100_vram_init_sizes
-ffffffff81de63e0 T r100_vga_set_state
-ffffffff81de6440 T r100_pll_errata_after_index
-ffffffff81de6480 T r100_pll_rreg
-ffffffff81de65f0 T r100_pll_wreg
-ffffffff81de6740 T r100_debugfs_rbbm_init
-ffffffff81de6770 T r100_debugfs_mc_info_init
-ffffffff81de67a0 T r100_set_surface_reg
-ffffffff81de69f0 T r100_clear_surface_reg
-ffffffff81de6ab0 T r100_bandwidth_update
-ffffffff81de7520 T r100_ring_test
-ffffffff81de7850 T r100_ring_ib_execute
-ffffffff81de7ad0 T r100_ib_test
-ffffffff81de7e90 T r100_vga_render_disable
-ffffffff81de7ef0 T r100_resume
-ffffffff81de8130 t r100_startup
-ffffffff81de86f0 T r100_suspend
-ffffffff81de87f0 T r100_fini
-ffffffff81de8960 T r100_restore_sanity
-ffffffff81de8a00 T r100_init
-ffffffff81de8f40 t r100_set_safe_registers
-ffffffff81de8fc0 T r100_mm_rreg_slow
-ffffffff81de9050 T r100_mm_wreg_slow
-ffffffff81de90c0 T r100_io_rreg
-ffffffff81de9170 T r100_io_wreg
-ffffffff81de91f0 t r100_get_vtx_size
-ffffffff81de92e0 t r100_cs_track_texture_print
+ffffffff81de2d70 T r100_debugfs_cp_init
+ffffffff81de2da0 T r100_cp_fini
+ffffffff81de2e70 T r100_cp_disable
+ffffffff81de2fd0 T r100_gui_wait_for_idle
+ffffffff81de30c0 T r100_reloc_pitch_offset
+ffffffff81de3230 T r100_packet3_load_vbpntr
+ffffffff81de3520 T r100_cs_parse_packet0
+ffffffff81de3630 T r100_cs_packet_parse_vline
+ffffffff81de3860 T r100_cs_track_check_pkt3_indx_buffer
+ffffffff81de38e0 T r100_cs_parse
+ffffffff81de4bd0 T r100_cs_track_clear
+ffffffff81de4f60 T r100_cs_track_check
+ffffffff81de5820 T r100_mc_wait_for_idle
+ffffffff81de58c0 T r100_gpu_is_lockup
+ffffffff81de5930 T r100_enable_bm
+ffffffff81de5980 T r100_bm_disable
+ffffffff81de5a40 T r100_asic_reset
+ffffffff81de5dd0 T r100_mc_stop
+ffffffff81de5f90 T r100_mc_resume
+ffffffff81de6050 T r100_set_common_regs
+ffffffff81de6200 T r100_vram_init_sizes
+ffffffff81de6410 T r100_vga_set_state
+ffffffff81de6470 T r100_pll_errata_after_index
+ffffffff81de64b0 T r100_pll_rreg
+ffffffff81de6620 T r100_pll_wreg
+ffffffff81de6770 T r100_debugfs_rbbm_init
+ffffffff81de67a0 T r100_debugfs_mc_info_init
+ffffffff81de67d0 T r100_set_surface_reg
+ffffffff81de6a20 T r100_clear_surface_reg
+ffffffff81de6ae0 T r100_bandwidth_update
+ffffffff81de7550 T r100_ring_test
+ffffffff81de7880 T r100_ring_ib_execute
+ffffffff81de7b00 T r100_ib_test
+ffffffff81de7ec0 T r100_vga_render_disable
+ffffffff81de7f20 T r100_resume
+ffffffff81de8160 t r100_startup
+ffffffff81de8720 T r100_suspend
+ffffffff81de8820 T r100_fini
+ffffffff81de8990 T r100_restore_sanity
+ffffffff81de8a30 T r100_init
+ffffffff81de8f70 t r100_set_safe_registers
+ffffffff81de8ff0 T r100_mm_rreg_slow
+ffffffff81de9080 T r100_mm_wreg_slow
+ffffffff81de90f0 T r100_io_rreg
+ffffffff81de91a0 T r100_io_wreg
+ffffffff81de9220 t r100_get_vtx_size
+ffffffff81de9310 t r100_cs_track_texture_print
 ffffffff81dea000 T r200_copy_dma
 ffffffff81dea4e0 T r200_packet0_check
 ffffffff81deb340 t r200_get_vtx_size_0
@@ -27515,31 +27515,31 @@ ffffffff81ece4a0 T amdgpu_amdkfd_alloc_gtt_mem
 ffffffff81ece7c0 t amdgpu_bo_reserve
 ffffffff81ece950 t amdgpu_bo_unreserve
 ffffffff81ecea60 T amdgpu_amdkfd_free_gtt_mem
-ffffffff81eceb00 T amdgpu_amdkfd_alloc_gws
-ffffffff81ecec00 T amdgpu_amdkfd_free_gws
-ffffffff81ecec50 T amdgpu_amdkfd_get_fw_version
-ffffffff81eced00 T amdgpu_amdkfd_get_local_mem_info
-ffffffff81eceeb0 T amdgpu_amdkfd_xcp_memory_size
-ffffffff81ecef50 T amdgpu_amdkfd_get_gpu_clock_counter
-ffffffff81ecef90 T amdgpu_amdkfd_get_max_engine_clock_in_mhz
-ffffffff81ecf000 T amdgpu_amdkfd_get_cu_info
-ffffffff81ecf120 T amdgpu_amdkfd_get_dmabuf_info
-ffffffff81ecf270 T amdgpu_amdkfd_get_xgmi_hops_count
-ffffffff81ecf2f0 T amdgpu_amdkfd_get_xgmi_bandwidth_mbytes
-ffffffff81ecf390 T amdgpu_amdkfd_get_pcie_bandwidth_mbytes
-ffffffff81ecf510 T amdgpu_amdkfd_submit_ib
-ffffffff81ecf6b0 T amdgpu_amdkfd_set_compute_idle
-ffffffff81ecf700 T amdgpu_amdkfd_is_kfd_vmid
-ffffffff81ecf740 T amdgpu_amdkfd_flush_gpu_tlb_vmid
-ffffffff81ecf880 T amdgpu_amdkfd_flush_gpu_tlb_pasid
-ffffffff81ecf8c0 T amdgpu_amdkfd_have_atomics_support
-ffffffff81ecf8f0 T amdgpu_amdkfd_debug_mem_fence
-ffffffff81ecf910 T amdgpu_amdkfd_ras_poison_consumption_handler
-ffffffff81ecf920 T amdgpu_amdkfd_send_close_event_drain_irq
-ffffffff81ecf940 T amdgpu_amdkfd_ras_query_utcl2_poison_status
-ffffffff81ecf990 T amdgpu_amdkfd_check_and_lock_kfd
-ffffffff81ecf9c0 T amdgpu_amdkfd_unlock_kfd
-ffffffff81ecf9f0 T amdgpu_amdkfd_unmap_hiq
+ffffffff81ecead0 T amdgpu_amdkfd_alloc_gws
+ffffffff81ecebd0 T amdgpu_amdkfd_free_gws
+ffffffff81ecec20 T amdgpu_amdkfd_get_fw_version
+ffffffff81ececd0 T amdgpu_amdkfd_get_local_mem_info
+ffffffff81ecee80 T amdgpu_amdkfd_xcp_memory_size
+ffffffff81ecef20 T amdgpu_amdkfd_get_gpu_clock_counter
+ffffffff81ecef60 T amdgpu_amdkfd_get_max_engine_clock_in_mhz
+ffffffff81ecefd0 T amdgpu_amdkfd_get_cu_info
+ffffffff81ecf0f0 T amdgpu_amdkfd_get_dmabuf_info
+ffffffff81ecf240 T amdgpu_amdkfd_get_xgmi_hops_count
+ffffffff81ecf2c0 T amdgpu_amdkfd_get_xgmi_bandwidth_mbytes
+ffffffff81ecf360 T amdgpu_amdkfd_get_pcie_bandwidth_mbytes
+ffffffff81ecf4e0 T amdgpu_amdkfd_submit_ib
+ffffffff81ecf680 T amdgpu_amdkfd_set_compute_idle
+ffffffff81ecf6d0 T amdgpu_amdkfd_is_kfd_vmid
+ffffffff81ecf710 T amdgpu_amdkfd_flush_gpu_tlb_vmid
+ffffffff81ecf850 T amdgpu_amdkfd_flush_gpu_tlb_pasid
+ffffffff81ecf890 T amdgpu_amdkfd_have_atomics_support
+ffffffff81ecf8c0 T amdgpu_amdkfd_debug_mem_fence
+ffffffff81ecf8e0 T amdgpu_amdkfd_ras_poison_consumption_handler
+ffffffff81ecf8f0 T amdgpu_amdkfd_send_close_event_drain_irq
+ffffffff81ecf910 T amdgpu_amdkfd_ras_query_utcl2_poison_status
+ffffffff81ecf960 T amdgpu_amdkfd_check_and_lock_kfd
+ffffffff81ecf990 T amdgpu_amdkfd_unlock_kfd
+ffffffff81ecf9c0 T amdgpu_amdkfd_unmap_hiq
 ffffffff81ed0000 T amdgpu_atom_execute_table
 ffffffff81ed00c0 t amdgpu_atom_execute_table_locked
 ffffffff81ed0470 T amdgpu_atom_parse
@@ -28048,13 +28048,13 @@ ffffffff81f17e60 T amdgpu_get_gfx_off_residency
 ffffffff81f17ee0 T amdgpu_get_gfx_off_entrycount
 ffffffff81f17f60 T amdgpu_get_gfx_off_status
 ffffffff81f17fe0 T amdgpu_gfx_ras_late_init
-ffffffff81f180f0 T amdgpu_gfx_ras_sw_init
-ffffffff81f18210 T amdgpu_gfx_process_ras_data_cb
-ffffffff81f182a0 T amdgpu_gfx_poison_consumption_handler
-ffffffff81f182f0 T amdgpu_gfx_cp_ecc_error_irq
-ffffffff81f183a0 T amdgpu_gfx_ras_error_func
-ffffffff81f184d0 T amdgpu_kiq_rreg
-ffffffff81f18820 T amdgpu_kiq_wreg
+ffffffff81f18100 T amdgpu_gfx_ras_sw_init
+ffffffff81f18220 T amdgpu_gfx_process_ras_data_cb
+ffffffff81f182b0 T amdgpu_gfx_poison_consumption_handler
+ffffffff81f18300 T amdgpu_gfx_cp_ecc_error_irq
+ffffffff81f183b0 T amdgpu_gfx_ras_error_func
+ffffffff81f184e0 T amdgpu_kiq_rreg
+ffffffff81f18830 T amdgpu_kiq_wreg
 ffffffff81f18b10 T amdgpu_gfx_get_num_kcq
 ffffffff81f18b90 T amdgpu_gfx_cp_init_microcode
 ffffffff81f18e70 T amdgpu_gfx_sysfs_init
@@ -28192,16 +28192,16 @@ ffffffff81f260b0 T amdgpu_driver_unload_kms
 ffffffff81f261e0 T amdgpu_register_gpu_instance
 ffffffff81f26270 T amdgpu_driver_load_kms
 ffffffff81f26410 T amdgpu_info_ioctl
-ffffffff81f27cc0 t amdgpu_hw_ip_info
-ffffffff81f28820 t amdgpu_firmware_info
-ffffffff81f28c00 T amdgpu_driver_lastclose_kms
-ffffffff81f28c10 T amdgpu_driver_open_kms
-ffffffff81f28f00 T amdgpu_driver_postclose_kms
-ffffffff81f293d0 T amdgpu_driver_release_kms
-ffffffff81f29410 T amdgpu_get_vblank_counter_kms
-ffffffff81f295e0 T amdgpu_enable_vblank_kms
-ffffffff81f29630 T amdgpu_disable_vblank_kms
-ffffffff81f29680 T amdgpu_debugfs_firmware_init
+ffffffff81f27c00 t amdgpu_hw_ip_info
+ffffffff81f28760 t amdgpu_firmware_info
+ffffffff81f28b40 T amdgpu_driver_lastclose_kms
+ffffffff81f28b50 T amdgpu_driver_open_kms
+ffffffff81f28e40 T amdgpu_driver_postclose_kms
+ffffffff81f29310 T amdgpu_driver_release_kms
+ffffffff81f29350 T amdgpu_get_vblank_counter_kms
+ffffffff81f29520 T amdgpu_enable_vblank_kms
+ffffffff81f29570 T amdgpu_disable_vblank_kms
+ffffffff81f295c0 T amdgpu_debugfs_firmware_init
 ffffffff81f2a000 T amdgpu_lsdma_wait_for
 ffffffff81f2a0b0 T amdgpu_lsdma_copy_mem
 ffffffff81f2a160 T amdgpu_lsdma_fill_mem
@@ -29044,60 +29044,60 @@ ffffffff81fa2d60 t gfx_v10_0_ring_emit_sb
 ffffffff81fa2e50 t gfx_v10_0_ring_emit_cntxcntl
 ffffffff81fa3380 t gfx_v10_0_ring_emit_frame_cntl
 ffffffff81fa3490 t gfx_v10_0_ring_soft_recovery
-ffffffff81fa3500 t gfx_v10_0_ring_preempt_ib
-ffffffff81fa36b0 t gfx_v10_0_emit_mem_sync
-ffffffff81fa3a20 t gfx_v10_0_write_data_to_reg
-ffffffff81fa3c50 t gfx_v10_0_set_eop_interrupt_state
-ffffffff81fa3d50 t gfx_v10_0_eop_irq
-ffffffff81fa3f30 t gfx_v10_0_set_gfx_eop_interrupt_state
-ffffffff81fa40f0 t gfx_v10_0_set_compute_eop_interrupt_state
-ffffffff81fa42d0 t gfx_v10_0_kiq_set_interrupt_state
-ffffffff81fa4640 t gfx_v10_0_kiq_irq
-ffffffff81fa46d0 t gfx_v10_0_set_priv_reg_fault_state
-ffffffff81fa4820 t gfx_v10_0_priv_reg_irq
-ffffffff81fa4890 t gfx_v10_0_handle_priv_fault
-ffffffff81fa4a00 t gfx_v10_0_set_priv_inst_fault_state
-ffffffff81fa4b50 t gfx_v10_0_priv_inst_irq
-ffffffff81fa4bc0 t gfx_v10_0_is_rlc_enabled
-ffffffff81fa4c60 t gfx_v10_0_set_safe_mode
-ffffffff81fa4f60 t gfx_v10_0_unset_safe_mode
-ffffffff81fa5010 t gfx_v10_0_rlc_init
-ffffffff81fa5030 t gfx_v10_0_get_csb_size
-ffffffff81fa5060 t gfx_v10_0_get_csb_buffer
-ffffffff81fa51d0 t gfx_v10_0_rlc_resume
-ffffffff81fa5d90 t gfx_v10_0_rlc_stop
-ffffffff81fa5e70 t gfx_v10_0_rlc_reset
-ffffffff81fa6060 t gfx_v10_0_rlc_start
-ffffffff81fa6250 t gfx_v10_0_update_spm_vmid
-ffffffff81fa62a0 t gfx_v10_0_wait_for_rlc_autoload_complete
-ffffffff81fa6ce0 t gfx_v10_0_init_csb
-ffffffff81fa7000 t gfx_v10_0_update_spm_vmid_internal
-ffffffff81fa70f0 t gfx_v10_0_rlc_backdoor_autoload_config_mec_cache
-ffffffff81fa7410 t gfx_v10_0_is_rlcg_access_range
-ffffffff81fa7440 t gfx_v10_0_gfx_mqd_init
-ffffffff81fa7880 t gfx_v10_0_compute_mqd_init
-ffffffff81fa7d90 t gfx_v10_0_mec_init
-ffffffff81fa8020 t gfx_v10_0_compute_ring_init
-ffffffff81fa8180 t gfx_v10_0_rlc_backdoor_autoload_buffer_init
-ffffffff81fa8420 t gfx_v10_0_gpu_early_init
-ffffffff81fa8690 t amdgpu_bo_unreserve
-ffffffff81fa87a0 t gfx_v10_0_cp_resume
-ffffffff81fab760 t gfx_v10_3_get_disabled_sa
-ffffffff81fab890 t gfx_v10_0_get_rb_active_bitmap
-ffffffff81fab9d0 t gfx_v10_0_get_wgp_active_bitmap_per_sh
-ffffffff81fabaf0 t gfx_v10_0_enable_gui_idle_interrupt
-ffffffff81fabc00 t gfx_v10_0_cp_gfx_enable
-ffffffff81fabea0 t gfx_v10_0_cp_compute_enable
-ffffffff81fac060 t amdgpu_bo_reserve
-ffffffff81fac200 t gfx_v10_0_kiq_init_register
-ffffffff81fad2f0 t gfx_v10_0_cp_gfx_switch_pipe
-ffffffff81fad3f0 t gfx_v10_0_cp_gfx_set_doorbell
-ffffffff81fad720 t gfx_v10_0_cp_gfx_start
-ffffffff81fae210 t gfx_v10_0_update_fine_grain_clock_gating
-ffffffff81fae5a0 t gfx_v10_0_update_medium_grain_clock_gating
-ffffffff81faeda0 t gfx_v10_0_update_3d_clock_gating
-ffffffff81faf1d0 t gfx_v10_0_update_coarse_grain_clock_gating
-ffffffff81faf600 t gfx_v10_cntl_pg
+ffffffff81fa3540 t gfx_v10_0_ring_preempt_ib
+ffffffff81fa36f0 t gfx_v10_0_emit_mem_sync
+ffffffff81fa3a60 t gfx_v10_0_write_data_to_reg
+ffffffff81fa3c90 t gfx_v10_0_set_eop_interrupt_state
+ffffffff81fa3d90 t gfx_v10_0_eop_irq
+ffffffff81fa3f70 t gfx_v10_0_set_gfx_eop_interrupt_state
+ffffffff81fa4130 t gfx_v10_0_set_compute_eop_interrupt_state
+ffffffff81fa4310 t gfx_v10_0_kiq_set_interrupt_state
+ffffffff81fa4680 t gfx_v10_0_kiq_irq
+ffffffff81fa4710 t gfx_v10_0_set_priv_reg_fault_state
+ffffffff81fa4860 t gfx_v10_0_priv_reg_irq
+ffffffff81fa48d0 t gfx_v10_0_handle_priv_fault
+ffffffff81fa4a40 t gfx_v10_0_set_priv_inst_fault_state
+ffffffff81fa4b90 t gfx_v10_0_priv_inst_irq
+ffffffff81fa4c00 t gfx_v10_0_is_rlc_enabled
+ffffffff81fa4ca0 t gfx_v10_0_set_safe_mode
+ffffffff81fa4fa0 t gfx_v10_0_unset_safe_mode
+ffffffff81fa5050 t gfx_v10_0_rlc_init
+ffffffff81fa5070 t gfx_v10_0_get_csb_size
+ffffffff81fa50a0 t gfx_v10_0_get_csb_buffer
+ffffffff81fa5210 t gfx_v10_0_rlc_resume
+ffffffff81fa5dd0 t gfx_v10_0_rlc_stop
+ffffffff81fa5eb0 t gfx_v10_0_rlc_reset
+ffffffff81fa60a0 t gfx_v10_0_rlc_start
+ffffffff81fa6290 t gfx_v10_0_update_spm_vmid
+ffffffff81fa62e0 t gfx_v10_0_wait_for_rlc_autoload_complete
+ffffffff81fa6d20 t gfx_v10_0_init_csb
+ffffffff81fa7040 t gfx_v10_0_update_spm_vmid_internal
+ffffffff81fa7130 t gfx_v10_0_rlc_backdoor_autoload_config_mec_cache
+ffffffff81fa7450 t gfx_v10_0_is_rlcg_access_range
+ffffffff81fa7480 t gfx_v10_0_gfx_mqd_init
+ffffffff81fa78c0 t gfx_v10_0_compute_mqd_init
+ffffffff81fa7dd0 t gfx_v10_0_mec_init
+ffffffff81fa8060 t gfx_v10_0_compute_ring_init
+ffffffff81fa81c0 t gfx_v10_0_rlc_backdoor_autoload_buffer_init
+ffffffff81fa8460 t gfx_v10_0_gpu_early_init
+ffffffff81fa86d0 t amdgpu_bo_unreserve
+ffffffff81fa87e0 t gfx_v10_0_cp_resume
+ffffffff81fab7a0 t gfx_v10_3_get_disabled_sa
+ffffffff81fab8d0 t gfx_v10_0_get_rb_active_bitmap
+ffffffff81faba10 t gfx_v10_0_get_wgp_active_bitmap_per_sh
+ffffffff81fabb30 t gfx_v10_0_enable_gui_idle_interrupt
+ffffffff81fabc40 t gfx_v10_0_cp_gfx_enable
+ffffffff81fabee0 t gfx_v10_0_cp_compute_enable
+ffffffff81fac0a0 t amdgpu_bo_reserve
+ffffffff81fac240 t gfx_v10_0_kiq_init_register
+ffffffff81fad330 t gfx_v10_0_cp_gfx_switch_pipe
+ffffffff81fad430 t gfx_v10_0_cp_gfx_set_doorbell
+ffffffff81fad760 t gfx_v10_0_cp_gfx_start
+ffffffff81fae250 t gfx_v10_0_update_fine_grain_clock_gating
+ffffffff81fae5e0 t gfx_v10_0_update_medium_grain_clock_gating
+ffffffff81faede0 t gfx_v10_0_update_3d_clock_gating
+ffffffff81faf210 t gfx_v10_0_update_coarse_grain_clock_gating
+ffffffff81faf640 t gfx_v10_cntl_pg
 ffffffff81fb0000 t gfx_v11_0_early_init
 ffffffff81fb0870 t gfx_v11_0_late_init
 ffffffff81fb08e0 t gfx_v11_0_sw_init
@@ -29156,53 +29156,53 @@ ffffffff81fbcbf0 t gfx_v11_0_ring_emit_cntxcntl
 ffffffff81fbcd70 t gfx_v11_0_ring_emit_gfx_shadow
 ffffffff81fbd180 t gfx_v11_0_ring_emit_frame_cntl
 ffffffff81fbd290 t gfx_v11_0_ring_soft_recovery
-ffffffff81fbd300 t gfx_v11_0_ring_preempt_ib
-ffffffff81fbd4b0 t gfx_v11_0_emit_mem_sync
-ffffffff81fbd820 t gfx_v11_0_write_data_to_reg
-ffffffff81fbda50 t gfx_v11_0_set_eop_interrupt_state
-ffffffff81fbdaf0 t gfx_v11_0_eop_irq
-ffffffff81fbdcd0 t gfx_v11_0_set_gfx_eop_interrupt_state
-ffffffff81fbde90 t gfx_v11_0_set_compute_eop_interrupt_state
-ffffffff81fbe040 t gfx_v11_0_set_priv_reg_fault_state
-ffffffff81fbe190 t gfx_v11_0_priv_reg_irq
-ffffffff81fbe200 t gfx_v11_0_handle_priv_fault
-ffffffff81fbe370 t gfx_v11_0_set_priv_inst_fault_state
-ffffffff81fbe4c0 t gfx_v11_0_priv_inst_irq
-ffffffff81fbe530 t gfx_v11_0_rlc_gc_fed_irq
-ffffffff81fbe580 t gfx_v11_0_is_rlc_enabled
-ffffffff81fbe620 t gfx_v11_0_set_safe_mode
-ffffffff81fbe7a0 t gfx_v11_0_unset_safe_mode
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-ffffffff81fbe890 t gfx_v11_0_get_csb_size
-ffffffff81fbe8c0 t gfx_v11_0_get_csb_buffer
-ffffffff81fbea30 t gfx_v11_0_rlc_resume
-ffffffff81fbf8e0 t gfx_v11_0_rlc_stop
-ffffffff81fbf9c0 t gfx_v11_0_rlc_reset
-ffffffff81fbfbb0 t gfx_v11_0_rlc_start
-ffffffff81fbfda0 t gfx_v11_0_update_spm_vmid
-ffffffff81fbfec0 t gfx_v11_0_init_csb
-ffffffff81fc0080 t gfx_v11_0_gfx_mqd_init
-ffffffff81fc04b0 t gfx_v11_0_compute_mqd_init
-ffffffff81fc0a50 t gfx_v11_0_mec_init
-ffffffff81fc0be0 t gfx_v11_0_compute_ring_init
-ffffffff81fc0d40 t gfx_v11_0_rlc_autoload_buffer_init
-ffffffff81fc0f40 t gfx_v11_0_gpu_early_init
-ffffffff81fc1010 t amdgpu_bo_unreserve
-ffffffff81fc1120 t gfx_v11_0_disable_gpa_mode
-ffffffff81fc12e0 t gfx_v11_0_cp_resume
-ffffffff81fc5a40 t gfx_v11_0_config_me_cache
-ffffffff81fc5e60 t gfx_v11_0_config_pfp_cache
-ffffffff81fc6280 t gfx_v11_0_config_mec_cache
-ffffffff81fc66a0 t gfx_v11_0_get_sa_active_bitmap
-ffffffff81fc67d0 t gfx_v11_0_enable_gui_idle_interrupt
-ffffffff81fc68e0 t gfx_v11_0_cp_compute_enable
-ffffffff81fc6ae0 t gfx_v11_0_cp_gfx_enable
-ffffffff81fc6d10 t amdgpu_bo_reserve
-ffffffff81fc6eb0 t gfx_v11_0_kiq_init_register
-ffffffff81fc7fb0 t gfx_v11_0_cp_gfx_switch_pipe
-ffffffff81fc80a0 t gfx_v11_0_cp_gfx_set_doorbell
-ffffffff81fc82b0 t gfx_v11_0_cp_gfx_start
-ffffffff81fc8c00 t gfx_v11_cntl_pg
+ffffffff81fbd340 t gfx_v11_0_ring_preempt_ib
+ffffffff81fbd4f0 t gfx_v11_0_emit_mem_sync
+ffffffff81fbd860 t gfx_v11_0_write_data_to_reg
+ffffffff81fbda90 t gfx_v11_0_set_eop_interrupt_state
+ffffffff81fbdb30 t gfx_v11_0_eop_irq
+ffffffff81fbdd10 t gfx_v11_0_set_gfx_eop_interrupt_state
+ffffffff81fbded0 t gfx_v11_0_set_compute_eop_interrupt_state
+ffffffff81fbe080 t gfx_v11_0_set_priv_reg_fault_state
+ffffffff81fbe1d0 t gfx_v11_0_priv_reg_irq
+ffffffff81fbe240 t gfx_v11_0_handle_priv_fault
+ffffffff81fbe3b0 t gfx_v11_0_set_priv_inst_fault_state
+ffffffff81fbe500 t gfx_v11_0_priv_inst_irq
+ffffffff81fbe570 t gfx_v11_0_rlc_gc_fed_irq
+ffffffff81fbe5c0 t gfx_v11_0_is_rlc_enabled
+ffffffff81fbe660 t gfx_v11_0_set_safe_mode
+ffffffff81fbe7e0 t gfx_v11_0_unset_safe_mode
+ffffffff81fbe850 t gfx_v11_0_rlc_init
+ffffffff81fbe8d0 t gfx_v11_0_get_csb_size
+ffffffff81fbe900 t gfx_v11_0_get_csb_buffer
+ffffffff81fbea70 t gfx_v11_0_rlc_resume
+ffffffff81fbf920 t gfx_v11_0_rlc_stop
+ffffffff81fbfa00 t gfx_v11_0_rlc_reset
+ffffffff81fbfbf0 t gfx_v11_0_rlc_start
+ffffffff81fbfde0 t gfx_v11_0_update_spm_vmid
+ffffffff81fbff00 t gfx_v11_0_init_csb
+ffffffff81fc00c0 t gfx_v11_0_gfx_mqd_init
+ffffffff81fc04f0 t gfx_v11_0_compute_mqd_init
+ffffffff81fc0a90 t gfx_v11_0_mec_init
+ffffffff81fc0c20 t gfx_v11_0_compute_ring_init
+ffffffff81fc0d80 t gfx_v11_0_rlc_autoload_buffer_init
+ffffffff81fc0f80 t gfx_v11_0_gpu_early_init
+ffffffff81fc1050 t amdgpu_bo_unreserve
+ffffffff81fc1160 t gfx_v11_0_disable_gpa_mode
+ffffffff81fc1320 t gfx_v11_0_cp_resume
+ffffffff81fc5a80 t gfx_v11_0_config_me_cache
+ffffffff81fc5ea0 t gfx_v11_0_config_pfp_cache
+ffffffff81fc62c0 t gfx_v11_0_config_mec_cache
+ffffffff81fc66e0 t gfx_v11_0_get_sa_active_bitmap
+ffffffff81fc6810 t gfx_v11_0_enable_gui_idle_interrupt
+ffffffff81fc6920 t gfx_v11_0_cp_compute_enable
+ffffffff81fc6b20 t gfx_v11_0_cp_gfx_enable
+ffffffff81fc6d50 t amdgpu_bo_reserve
+ffffffff81fc6ef0 t gfx_v11_0_kiq_init_register
+ffffffff81fc7ff0 t gfx_v11_0_cp_gfx_switch_pipe
+ffffffff81fc80e0 t gfx_v11_0_cp_gfx_set_doorbell
+ffffffff81fc82f0 t gfx_v11_0_cp_gfx_start
+ffffffff81fc8c40 t gfx_v11_cntl_pg
 ffffffff81fc9000 t gfx_v11_0_3_rlc_gc_fed_irq
 ffffffff81fc9240 t gfx_v11_0_3_poison_consumption_handler
 ffffffff81fca000 t gfx_v8_0_early_init
@@ -29298,56 +29298,56 @@ ffffffff81fda1e0 t gfx_v9_0_query_ras_error_count
 ffffffff81fdaf10 t gfx_v9_0_reset_ras_error_count
 ffffffff81fdbab0 T gfx_v9_0_select_se_sh
 ffffffff81fdbb50 t gfx_v9_0_early_init
-ffffffff81fdc790 t gfx_v9_0_late_init
-ffffffff81fdd770 t gfx_v9_0_sw_init
-ffffffff81fddf50 t gfx_v9_0_sw_fini
-ffffffff81fde1b0 t gfx_v9_0_hw_init
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-ffffffff81fe1fe0 t gfx_v9_0_suspend
-ffffffff81fe2020 t gfx_v9_0_resume
-ffffffff81fe2030 t gfx_v9_0_is_idle
-ffffffff81fe20d0 t gfx_v9_0_wait_for_idle
-ffffffff81fe21d0 t gfx_v9_0_soft_reset
-ffffffff81fe25e0 t gfx_v9_0_set_clockgating_state
-ffffffff81fe26e0 t gfx_v9_0_set_powergating_state
-ffffffff81fe2b40 t gfx_v9_0_get_clockgating_state
-ffffffff81fe2c80 t gfx_v9_0_get_gpu_clock_counter
-ffffffff81fe3560 t gfx_v9_0_read_wave_data
-ffffffff81fe3830 t gfx_v9_0_read_wave_vgprs
-ffffffff81fe38a0 t gfx_v9_0_read_wave_sgprs
-ffffffff81fe38d0 t gfx_v9_0_select_me_pipe_q
-ffffffff81fe38f0 t wave_read_ind
-ffffffff81fe3a00 t wave_read_regs
-ffffffff81fe3b70 t gfx_v9_0_kiq_set_resources
-ffffffff81fe3ed0 t gfx_v9_0_kiq_map_queues
-ffffffff81fe4250 t gfx_v9_0_kiq_unmap_queues
-ffffffff81fe45c0 t gfx_v9_0_kiq_query_status
-ffffffff81fe48e0 t gfx_v9_0_kiq_invalidate_tlbs
-ffffffff81fe4a10 t gfx_v9_0_ring_get_rptr_compute
-ffffffff81fe4a40 t gfx_v9_0_ring_get_wptr_compute
-ffffffff81fe4ab0 t gfx_v9_0_ring_set_wptr_compute
-ffffffff81fe4b10 t gfx_v9_0_ring_emit_fence_kiq
-ffffffff81fe4f90 t gfx_v9_0_ring_test_ring
-ffffffff81fe5200 t gfx_v9_0_ring_emit_rreg
-ffffffff81fe54c0 t gfx_v9_0_ring_emit_wreg
-ffffffff81fe5720 t gfx_v9_0_ring_emit_reg_wait
-ffffffff81fe5780 t gfx_v9_0_ring_emit_reg_write_reg_wait
-ffffffff81fe5820 t gfx_v9_0_wait_reg_mem
-ffffffff81fe5b80 t gfx_v9_0_ring_get_rptr_gfx
-ffffffff81fe5bb0 t gfx_v9_0_ring_get_wptr_gfx
-ffffffff81fe5cd0 t gfx_v9_0_ring_set_wptr_gfx
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-ffffffff81fe6900 t gfx_v9_0_ring_emit_pipeline_sync
-ffffffff81fe6970 t gfx_v9_0_ring_emit_vm_flush
-ffffffff81fe6a90 t gfx_v9_0_ring_emit_hdp_flush
-ffffffff81fe6b80 t gfx_v9_0_ring_emit_gds_switch
-ffffffff81fe6c80 t gfx_v9_0_ring_emit_init_cond_exec
-ffffffff81fe6ed0 t gfx_v9_0_ring_emit_patch_cond_exec
-ffffffff81fe6f90 t gfx_v9_ring_emit_sb
-ffffffff81fe7080 t gfx_v9_ring_emit_cntxcntl
-ffffffff81fe75c0 t gfx_v9_0_ring_emit_frame_cntl
-ffffffff81fe76d0 t gfx_v9_0_ring_soft_recovery
+ffffffff81fdc740 t gfx_v9_0_late_init
+ffffffff81fdd720 t gfx_v9_0_sw_init
+ffffffff81fddf00 t gfx_v9_0_sw_fini
+ffffffff81fde160 t gfx_v9_0_hw_init
+ffffffff81fe16d0 t gfx_v9_0_hw_fini
+ffffffff81fe1f90 t gfx_v9_0_suspend
+ffffffff81fe1fd0 t gfx_v9_0_resume
+ffffffff81fe1fe0 t gfx_v9_0_is_idle
+ffffffff81fe2080 t gfx_v9_0_wait_for_idle
+ffffffff81fe2180 t gfx_v9_0_soft_reset
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+ffffffff81fe2690 t gfx_v9_0_set_powergating_state
+ffffffff81fe2af0 t gfx_v9_0_get_clockgating_state
+ffffffff81fe2c30 t gfx_v9_0_get_gpu_clock_counter
+ffffffff81fe3510 t gfx_v9_0_read_wave_data
+ffffffff81fe37e0 t gfx_v9_0_read_wave_vgprs
+ffffffff81fe3850 t gfx_v9_0_read_wave_sgprs
+ffffffff81fe3880 t gfx_v9_0_select_me_pipe_q
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+ffffffff81fe4200 t gfx_v9_0_kiq_unmap_queues
+ffffffff81fe4570 t gfx_v9_0_kiq_query_status
+ffffffff81fe4890 t gfx_v9_0_kiq_invalidate_tlbs
+ffffffff81fe49c0 t gfx_v9_0_ring_get_rptr_compute
+ffffffff81fe49f0 t gfx_v9_0_ring_get_wptr_compute
+ffffffff81fe4a60 t gfx_v9_0_ring_set_wptr_compute
+ffffffff81fe4ac0 t gfx_v9_0_ring_emit_fence_kiq
+ffffffff81fe4f40 t gfx_v9_0_ring_test_ring
+ffffffff81fe51b0 t gfx_v9_0_ring_emit_rreg
+ffffffff81fe5470 t gfx_v9_0_ring_emit_wreg
+ffffffff81fe56d0 t gfx_v9_0_ring_emit_reg_wait
+ffffffff81fe5730 t gfx_v9_0_ring_emit_reg_write_reg_wait
+ffffffff81fe57d0 t gfx_v9_0_wait_reg_mem
+ffffffff81fe5b30 t gfx_v9_0_ring_get_rptr_gfx
+ffffffff81fe5b60 t gfx_v9_0_ring_get_wptr_gfx
+ffffffff81fe5c80 t gfx_v9_0_ring_set_wptr_gfx
+ffffffff81fe5dc0 t gfx_v9_0_ring_emit_ib_gfx
+ffffffff81fe64b0 t gfx_v9_0_ring_emit_fence
+ffffffff81fe68c0 t gfx_v9_0_ring_emit_pipeline_sync
+ffffffff81fe6930 t gfx_v9_0_ring_emit_vm_flush
+ffffffff81fe6a50 t gfx_v9_0_ring_emit_hdp_flush
+ffffffff81fe6b40 t gfx_v9_0_ring_emit_gds_switch
+ffffffff81fe6c40 t gfx_v9_0_ring_emit_init_cond_exec
+ffffffff81fe6e90 t gfx_v9_0_ring_emit_patch_cond_exec
+ffffffff81fe6f50 t gfx_v9_ring_emit_sb
+ffffffff81fe7040 t gfx_v9_ring_emit_cntxcntl
+ffffffff81fe7580 t gfx_v9_0_ring_emit_frame_cntl
+ffffffff81fe7690 t gfx_v9_0_ring_soft_recovery
 ffffffff81fe7740 t gfx_v9_0_ring_preempt_ib
 ffffffff81fe7970 t gfx_v9_0_emit_mem_sync
 ffffffff81fe7c60 t gfx_v9_0_write_data_to_reg
@@ -31376,94 +31376,94 @@ ffffffff82157d70 T amdgpu_dm_connector_atomic_get_prop
 ffffffff82157e10 T amdgpu_dm_connector_funcs_reset
 ffffffff82157f10 T amdgpu_dm_connector_atomic_duplicate_state
 ffffffff82158020 T create_validate_stream_for_sink
-ffffffff82159950 T amdgpu_dm_connector_mode_valid
-ffffffff82159b50 T convert_dc_color_depth_into_bpc
-ffffffff82159b90 t dm_encoder_helper_disable
-ffffffff82159bc0 t dm_encoder_helper_atomic_check
-ffffffff82159dd0 T amdgpu_dm_connector_init_helper
-ffffffff8215a1c0 T amdgpu_dm_get_encoder_crtc_mask
-ffffffff8215a210 T dm_restore_drm_connector_state
-ffffffff8215a3a0 t parse_hdmi_amd_vsdb
-ffffffff8215a750 T amdgpu_dm_trigger_timing_sync
-ffffffff8215a930 T dm_write_reg_func
-ffffffff8215a950 T dm_read_reg_func
-ffffffff8215aa00 T amdgpu_dm_process_dmub_aux_transfer_sync
-ffffffff8215ac70 T amdgpu_dm_process_dmub_set_config_sync
-ffffffff8215ae10 T check_seamless_boot_capability
-ffffffff8215ae60 T dm_execute_dmub_cmd
-ffffffff8215ae80 T dm_execute_dmub_cmd_list
-ffffffff8215aea0 t dm_early_init
-ffffffff8215b270 t dm_late_init
-ffffffff8215b570 t dm_sw_init
-ffffffff8215bb90 t dm_sw_fini
-ffffffff8215bc60 t amdgpu_dm_early_fini
-ffffffff8215bcc0 t dm_hw_init
-ffffffff8215dcf0 t dm_hw_fini
-ffffffff8215dd60 t dm_suspend
-ffffffff8215e1a0 t dm_resume
-ffffffff8215ec00 t dm_is_idle
-ffffffff8215ec30 t dm_wait_for_idle
-ffffffff8215ec60 t dm_check_soft_reset
-ffffffff8215ec90 t dm_soft_reset
-ffffffff8215ecc0 t dm_set_clockgating_state
-ffffffff8215ecf0 t dm_set_powergating_state
-ffffffff8215ed20 t dm_bandwidth_update
-ffffffff8215ed50 t dm_vblank_get_counter
-ffffffff8215edd0 t dm_crtc_get_scanoutpos
-ffffffff8215eec0 t amdgpu_dm_dmub_reg_read
-ffffffff8215ef70 t amdgpu_dm_dmub_reg_write
-ffffffff8215efa0 t dm_dmub_hw_init
-ffffffff8215f400 t dmub_aux_setconfig_callback
-ffffffff8215f4b0 t amdgpu_dm_fini
-ffffffff8215f700 t emulated_link_detect
-ffffffff8215f810 t amdgpu_dm_atomic_check
-ffffffff82160700 t dm_update_plane_state
-ffffffff82160db0 t dm_update_crtc_state
-ffffffff821618a0 t dm_check_crtc_cursor
-ffffffff82161c20 t is_scaling_state_different
-ffffffff82161cc0 t do_aquire_global_lock
-ffffffff82161f90 t dm_update_mst_vcpi_slots_for_dsc
-ffffffff821621a0 t dm_atomic_destroy_state
-ffffffff821621e0 t dm_check_cursor_fb
-ffffffff82162390 t fill_dc_plane_attributes
-ffffffff82162640 t fill_dc_plane_info_and_addr
-ffffffff82162990 t fill_hdr_info_packet
-ffffffff82162b00 t is_timing_unchanged_for_freesync
-ffffffff82162c30 t get_highest_refresh_rate_mode
-ffffffff82162d90 t update_stream_scaling_settings
-ffffffff82162ee0 t amdgpu_dm_atomic_commit_tail
-ffffffff821660a0 t amdgpu_dm_backlight_set_level
-ffffffff821662f0 t dm_atomic_duplicate_state
-ffffffff821663b0 t amdgpu_dm_audio_component_bind
-ffffffff82166420 t amdgpu_dm_audio_component_unbind
-ffffffff82166480 t amdgpu_dm_audio_component_get_eld
-ffffffff821665e0 t dm_dmub_outbox1_low_irq
-ffffffff82166920 t dm_handle_hpd_work
-ffffffff821669b0 t amdgpu_dm_encoder_destroy
-ffffffff821669f0 t amdgpu_dm_i2c_xfer
-ffffffff82166b50 t amdgpu_dm_i2c_func
-ffffffff82166b80 t amdgpu_dm_connector_detect
-ffffffff82166c40 t amdgpu_dm_connector_funcs_force
-ffffffff82166d30 t amdgpu_dm_connector_late_register
-ffffffff82166eb0 t amdgpu_dm_connector_unregister
-ffffffff82166ed0 t amdgpu_dm_connector_destroy
-ffffffff82166fe0 t amdgpu_dm_backlight_update_status
-ffffffff82167070 t amdgpu_dm_backlight_get_brightness
-ffffffff821672a0 t get_modes
-ffffffff821672b0 t amdgpu_dm_connector_atomic_check
-ffffffff82167410 t amdgpu_dm_connector_get_modes
-ffffffff82167a90 t dm_crtc_high_irq
-ffffffff82167c50 t dm_vupdate_high_irq
-ffffffff82167e00 t dm_pflip_high_irq
-ffffffff82168050 t register_hpd_handlers
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-ffffffff82168330 t handle_hpd_irq
-ffffffff82168340 t handle_hpd_rx_irq
-ffffffff821686f0 t handle_hpd_irq_helper
-ffffffff821688b0 t schedule_hpd_rx_offload_work
-ffffffff82168980 t dm_handle_hpd_rx_offload_work
-ffffffff82168d60 t dm_gpureset_toggle_interrupts
-ffffffff82168fa0 t s3_handle_mst
+ffffffff821599b0 T amdgpu_dm_connector_mode_valid
+ffffffff82159bb0 T convert_dc_color_depth_into_bpc
+ffffffff82159bf0 t dm_encoder_helper_disable
+ffffffff82159c20 t dm_encoder_helper_atomic_check
+ffffffff82159e30 T amdgpu_dm_connector_init_helper
+ffffffff8215a220 T amdgpu_dm_get_encoder_crtc_mask
+ffffffff8215a270 T dm_restore_drm_connector_state
+ffffffff8215a400 t parse_hdmi_amd_vsdb
+ffffffff8215a7b0 T amdgpu_dm_trigger_timing_sync
+ffffffff8215a990 T dm_write_reg_func
+ffffffff8215a9b0 T dm_read_reg_func
+ffffffff8215aa60 T amdgpu_dm_process_dmub_aux_transfer_sync
+ffffffff8215acd0 T amdgpu_dm_process_dmub_set_config_sync
+ffffffff8215ae70 T check_seamless_boot_capability
+ffffffff8215aec0 T dm_execute_dmub_cmd
+ffffffff8215aee0 T dm_execute_dmub_cmd_list
+ffffffff8215af00 t dm_early_init
+ffffffff8215b2d0 t dm_late_init
+ffffffff8215b5d0 t dm_sw_init
+ffffffff8215bbf0 t dm_sw_fini
+ffffffff8215bcc0 t amdgpu_dm_early_fini
+ffffffff8215bd20 t dm_hw_init
+ffffffff8215dd50 t dm_hw_fini
+ffffffff8215ddc0 t dm_suspend
+ffffffff8215e200 t dm_resume
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+ffffffff8215ecc0 t dm_check_soft_reset
+ffffffff8215ecf0 t dm_soft_reset
+ffffffff8215ed20 t dm_set_clockgating_state
+ffffffff8215ed50 t dm_set_powergating_state
+ffffffff8215ed80 t dm_bandwidth_update
+ffffffff8215edb0 t dm_vblank_get_counter
+ffffffff8215ee30 t dm_crtc_get_scanoutpos
+ffffffff8215ef20 t amdgpu_dm_dmub_reg_read
+ffffffff8215efd0 t amdgpu_dm_dmub_reg_write
+ffffffff8215f000 t dm_dmub_hw_init
+ffffffff8215f460 t dmub_aux_setconfig_callback
+ffffffff8215f510 t amdgpu_dm_fini
+ffffffff8215f760 t emulated_link_detect
+ffffffff8215f870 t amdgpu_dm_atomic_check
+ffffffff82160760 t dm_update_plane_state
+ffffffff82160e10 t dm_update_crtc_state
+ffffffff82161900 t dm_check_crtc_cursor
+ffffffff82161c80 t is_scaling_state_different
+ffffffff82161d20 t do_aquire_global_lock
+ffffffff82161ff0 t dm_update_mst_vcpi_slots_for_dsc
+ffffffff82162200 t dm_atomic_destroy_state
+ffffffff82162240 t dm_check_cursor_fb
+ffffffff821623f0 t fill_dc_plane_attributes
+ffffffff821626a0 t fill_dc_plane_info_and_addr
+ffffffff821629f0 t fill_hdr_info_packet
+ffffffff82162b60 t is_timing_unchanged_for_freesync
+ffffffff82162c90 t get_highest_refresh_rate_mode
+ffffffff82162df0 t update_stream_scaling_settings
+ffffffff82162f40 t amdgpu_dm_atomic_commit_tail
+ffffffff82166100 t amdgpu_dm_backlight_set_level
+ffffffff82166350 t dm_atomic_duplicate_state
+ffffffff82166410 t amdgpu_dm_audio_component_bind
+ffffffff82166480 t amdgpu_dm_audio_component_unbind
+ffffffff821664e0 t amdgpu_dm_audio_component_get_eld
+ffffffff82166640 t dm_dmub_outbox1_low_irq
+ffffffff82166980 t dm_handle_hpd_work
+ffffffff82166a10 t amdgpu_dm_encoder_destroy
+ffffffff82166a50 t amdgpu_dm_i2c_xfer
+ffffffff82166bb0 t amdgpu_dm_i2c_func
+ffffffff82166be0 t amdgpu_dm_connector_detect
+ffffffff82166ca0 t amdgpu_dm_connector_funcs_force
+ffffffff82166d90 t amdgpu_dm_connector_late_register
+ffffffff82166f10 t amdgpu_dm_connector_unregister
+ffffffff82166f30 t amdgpu_dm_connector_destroy
+ffffffff82167040 t amdgpu_dm_backlight_update_status
+ffffffff821670d0 t amdgpu_dm_backlight_get_brightness
+ffffffff82167300 t get_modes
+ffffffff82167310 t amdgpu_dm_connector_atomic_check
+ffffffff82167470 t amdgpu_dm_connector_get_modes
+ffffffff82167af0 t dm_crtc_high_irq
+ffffffff82167cb0 t dm_vupdate_high_irq
+ffffffff82167e60 t dm_pflip_high_irq
+ffffffff821680b0 t register_hpd_handlers
+ffffffff821681d0 t dmub_hpd_callback
+ffffffff821683c0 t handle_hpd_irq
+ffffffff821683d0 t handle_hpd_rx_irq
+ffffffff82168780 t handle_hpd_irq_helper
+ffffffff82168940 t schedule_hpd_rx_offload_work
+ffffffff82168a10 t dm_handle_hpd_rx_offload_work
+ffffffff82168df0 t dm_gpureset_toggle_interrupts
+ffffffff82169030 t s3_handle_mst
 ffffffff8216a000 T amdgpu_dm_init_color_mod
 ffffffff8216a010 T amdgpu_dm_verify_lut_sizes
 ffffffff8216a0f0 T amdgpu_dm_update_crtc_color_mgmt
@@ -31504,39 +31504,39 @@ ffffffff8216d320 t update_config
 ffffffff8216d6d0 t enable_assr
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-ffffffff8216e7b0 T dm_helpers_dp_mst_send_payload_allocation
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-ffffffff8216eb90 T dm_helpers_dp_mst_stop_top_mgr
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-ffffffff8216f6b0 T dm_helpers_read_local_edid
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-ffffffff8216f9d0 T dm_set_dcn_clocks
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-ffffffff8216fa30 T dm_helpers_init_panel_settings
-ffffffff8216faa0 T dm_helpers_override_panel_settings
-ffffffff8216fae0 T dm_helpers_allocate_gpu_mem
-ffffffff8216fbf0 T dm_helpers_free_gpu_mem
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-ffffffff821701e0 T dm_helpers_enable_periodic_detection
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-ffffffff82170240 T dm_get_adaptive_sync_support_type
-ffffffff821702b0 t execute_synaptics_rc_command
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+ffffffff8216e770 T dm_helpers_dp_mst_poll_for_allocation_change_trigger
+ffffffff8216e7f0 T dm_helpers_dp_mst_send_payload_allocation
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+ffffffff8216ed20 T dm_helpers_dp_write_dpcd
+ffffffff8216edb0 T dm_helpers_submit_i2c
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+ffffffff8216f640 T dm_helpers_is_dp_sink_present
+ffffffff8216f6f0 T dm_helpers_read_local_edid
+ffffffff8216f9a0 T dm_helper_dmub_aux_transfer_sync
+ffffffff8216f9f0 T dm_helpers_dmub_set_config_sync
+ffffffff8216fa10 T dm_set_dcn_clocks
+ffffffff8216fa40 T dm_helpers_smu_timeout
+ffffffff8216fa70 T dm_helpers_init_panel_settings
+ffffffff8216fae0 T dm_helpers_override_panel_settings
+ffffffff8216fb20 T dm_helpers_allocate_gpu_mem
+ffffffff8216fc30 T dm_helpers_free_gpu_mem
+ffffffff8216fcd0 T dm_helpers_dmub_outbox_interrupt_control
+ffffffff8216fd70 T dm_helpers_mst_enable_stream_features
+ffffffff8216fea0 T dm_helpers_dp_handle_test_pattern_request
+ffffffff821701f0 T dm_set_phyd32clk
+ffffffff82170220 T dm_helpers_enable_periodic_detection
+ffffffff82170250 T dm_helpers_dp_mst_update_branch_bandwidth
+ffffffff82170280 T dm_get_adaptive_sync_support_type
+ffffffff821702f0 t execute_synaptics_rc_command
 ffffffff82171000 T amdgpu_dm_irq_register_interrupt
 ffffffff821711d0 t dm_irq_work_func
 ffffffff821711f0 T amdgpu_dm_irq_unregister_interrupt
@@ -31588,19 +31588,19 @@ ffffffff82177120 T amdgpu_dm_plane_fill_plane_buffer_a
 ffffffff821776a0 T amdgpu_dm_plane_helper_check_state
 ffffffff821778c0 T amdgpu_dm_plane_fill_dc_scaling_info
 ffffffff82177b20 T amdgpu_dm_plane_handle_cursor_update
-ffffffff82177df0 T amdgpu_dm_plane_init
-ffffffff82178da0 T is_video_format
-ffffffff82178df0 t dm_drm_plane_reset
-ffffffff82178e90 t dm_drm_plane_duplicate_state
-ffffffff82178f30 t dm_drm_plane_destroy_state
-ffffffff82178f70 t dm_plane_format_mod_supported
-ffffffff821790a0 t dm_plane_helper_prepare_fb
-ffffffff82179420 t dm_plane_helper_cleanup_fb
-ffffffff821794d0 t dm_plane_atomic_check
-ffffffff821795c0 t dm_plane_atomic_async_check
-ffffffff82179600 t dm_plane_atomic_async_update
-ffffffff821796b0 t amdgpu_bo_reserve
-ffffffff821798f0 t amdgpu_bo_unreserve
+ffffffff82177e00 T amdgpu_dm_plane_init
+ffffffff82178db0 T is_video_format
+ffffffff82178e00 t dm_drm_plane_reset
+ffffffff82178ea0 t dm_drm_plane_duplicate_state
+ffffffff82178f40 t dm_drm_plane_destroy_state
+ffffffff82178f80 t dm_plane_format_mod_supported
+ffffffff821790b0 t dm_plane_helper_prepare_fb
+ffffffff82179430 t dm_plane_helper_cleanup_fb
+ffffffff821794e0 t dm_plane_atomic_check
+ffffffff821795d0 t dm_plane_atomic_async_check
+ffffffff82179610 t dm_plane_atomic_async_update
+ffffffff821796c0 t amdgpu_bo_reserve
+ffffffff82179900 t amdgpu_bo_unreserve
 ffffffff8217a000 T dm_pp_apply_display_requirements
 ffffffff8217a1f0 T dm_pp_get_clock_levels_by_type
 ffffffff8217a5b0 T dm_pp_get_clock_levels_by_type_with_latency
@@ -31878,8 +31878,8 @@ ffffffff8219ea70 t dce_update_clocks
 ffffffff8219f000 T dce110_get_min_vblank_time_us
 ffffffff8219f090 T dce110_fill_display_configs
 ffffffff8219f310 T dce11_pplib_apply_display_requirements
-ffffffff8219f620 T dce110_clk_mgr_construct
-ffffffff8219f6d0 t dce11_update_clocks
+ffffffff8219f630 T dce110_clk_mgr_construct
+ffffffff8219f6e0 t dce11_update_clocks
 ffffffff821a0000 T dce112_set_clock
 ffffffff821a01a0 T dce112_set_dispclk
 ffffffff821a02d0 T dce112_set_dprefclk
@@ -32105,81 +32105,81 @@ ffffffff821c1000 T dc_stream_adjust_vmin_vmax
 ffffffff821c1170 T dc_stream_get_last_used_drr_vtotal
 ffffffff821c12e0 T dc_stream_get_crtc_position
 ffffffff821c1540 T dc_stream_configure_crc
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-ffffffff821c17b0 T dc_stream_set_dyn_expansion
-ffffffff821c1a40 T dc_stream_set_dither_option
-ffffffff821c1be0 T dc_stream_set_gamut_remap
-ffffffff821c1d90 T dc_stream_program_csc_matrix
-ffffffff821c1ff0 T dc_stream_set_static_screen_params
-ffffffff821c2180 T dc_create
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-ffffffff821c2970 t dc_destruct
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-ffffffff821c2da0 T dc_init_callbacks
-ffffffff821c2df0 T dc_deinit_callbacks
-ffffffff821c2e40 T dc_destroy
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-ffffffff821c32c0 T dc_enable_stereo
-ffffffff821c33d0 T dc_trigger_sync
-ffffffff821c3a30 T dc_z10_restore
-ffffffff821c3a70 T dc_z10_save_init
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-ffffffff821c4000 t commit_minimal_transition_state
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-ffffffff821c5ec0 T dc_acquire_release_mpc_3dlut
-ffffffff821c5f90 T dc_post_update_surfaces_to_stream
-ffffffff821c6410 T dc_copy_state
-ffffffff821c6600 T dc_retain_state
-ffffffff821c6630 T dc_set_generic_gpio_for_stereo
-ffffffff821c6790 T dc_check_update_surfaces_for_stream
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-ffffffff821caa60 t copy_stream_update_to_stream
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-ffffffff821cb1f0 T dc_interrupt_to_irq_source
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-ffffffff821cb2d0 T dc_set_power_state
-ffffffff821cb500 T dc_resume
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-ffffffff821cb5d0 T get_clock_requirements_for_state
-ffffffff821cb650 T dc_set_clock
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-ffffffff821cb6d0 T dc_set_psr_allow_active
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-ffffffff821cbdb0 T dc_is_plane_eligible_for_idle_optimizations
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-ffffffff821cbea0 T dc_is_dmub_outbox_supported
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-ffffffff821cbfd0 T dc_process_dmub_aux_transfer_async
-ffffffff821cc160 T get_link_index_from_dpia_port_index
-ffffffff821cc220 T dc_process_dmub_set_config_async
-ffffffff821cc300 T dc_process_dmub_set_mst_slots
-ffffffff821cc3f0 T dc_process_dmub_dpia_hpd_int_enable
-ffffffff821cc4c0 T dc_print_dmub_diagnostic_data
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-ffffffff821cc990 T dc_set_edp_power
-ffffffff821cca00 t create_links
-ffffffff821cceb0 t create_link_encoders
-ffffffff821ccfa0 t dc_update_viusal_confirm_color
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+ffffffff821c1a50 T dc_stream_set_dither_option
+ffffffff821c1bf0 T dc_stream_set_gamut_remap
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+ffffffff821c32d0 T dc_enable_stereo
+ffffffff821c33e0 T dc_trigger_sync
+ffffffff821c3a40 T dc_z10_restore
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+ffffffff821c5ee0 T dc_acquire_release_mpc_3dlut
+ffffffff821c5fb0 T dc_post_update_surfaces_to_stream
+ffffffff821c6430 T dc_copy_state
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+ffffffff821c6650 T dc_set_generic_gpio_for_stereo
+ffffffff821c67b0 T dc_check_update_surfaces_for_stream
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+ffffffff821c8820 t commit_planes_for_stream
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+ffffffff821caa90 t copy_stream_update_to_stream
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+ffffffff821cb240 T dc_interrupt_set
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+ffffffff821cb530 T dc_resume
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+ffffffff821cb680 T dc_set_clock
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+ffffffff821cb950 T dc_lock_memory_clock_frequency
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+ffffffff821cbbc0 t blank_and_force_memclk
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+ffffffff821cbee0 T dc_is_dmub_outbox_supported
+ffffffff821cbf50 T dc_enable_dmub_notifications
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+ffffffff821cc010 T dc_process_dmub_aux_transfer_async
+ffffffff821cc1a0 T get_link_index_from_dpia_port_index
+ffffffff821cc260 T dc_process_dmub_set_config_async
+ffffffff821cc340 T dc_process_dmub_set_mst_slots
+ffffffff821cc430 T dc_process_dmub_dpia_hpd_int_enable
+ffffffff821cc500 T dc_print_dmub_diagnostic_data
+ffffffff821cc520 T dc_disable_accelerated_mode
+ffffffff821cc540 T dc_notify_vsync_int_state
+ffffffff821cc770 T dc_abm_save_restore
+ffffffff821cc960 T dc_query_current_properties
+ffffffff821cc9d0 T dc_set_edp_power
+ffffffff821cca40 t create_links
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+ffffffff821ccfe0 t dc_update_viusal_confirm_color
 ffffffff821ce000 T pre_surface_trace
 ffffffff821ce030 T update_surface_trace
 ffffffff821ce060 T post_surface_trace
@@ -32293,65 +32293,65 @@ ffffffff821d5c70 T resource_unreference_clock_source
 ffffffff821d5cf0 T resource_reference_clock_source
 ffffffff821d5d70 T resource_get_clock_source_reference
 ffffffff821d5df0 T resource_are_vblanks_synchronizable
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-ffffffff821d75f0 T resource_find_free_secondary_pipe_legacy
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-ffffffff821d7700 T resource_is_pipe_type
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-ffffffff821d7800 T resource_find_free_pipe_used_as_cur_sec_dpp_in_mpcc_combine
-ffffffff821d7920 T resource_is_for_mpcc_combine
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-ffffffff821d7b50 T resource_get_opp_head
-ffffffff821d7bf0 T dc_add_plane_to_context
-ffffffff821d7ef0 T dc_remove_plane_from_context
-ffffffff821d80f0 T dc_rem_all_planes_for_stream
-ffffffff821d82b0 T dc_add_all_planes_for_stream
-ffffffff821d8430 T dc_is_timing_changed
-ffffffff821d84a0 T dc_is_stream_unchanged
-ffffffff821d8590 T dc_is_stream_scaling_unchanged
-ffffffff821d8640 T update_audio_usage
-ffffffff821d86b0 T dc_add_stream_to_ctx
-ffffffff821d87a0 T dc_remove_stream_from_ctx
-ffffffff821d8bf0 T resource_map_pool_resources
-ffffffff821d96e0 t acquire_first_split_pipe
-ffffffff821d9860 t add_hpo_dp_link_enc_to_ctx
-ffffffff821d9930 t find_first_free_audio
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-ffffffff821d9be0 T dc_resource_state_construct
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-ffffffff821daaa0 T dc_validate_global_state
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-ffffffff821daf40 T dc_resource_find_first_free_pll
-ffffffff821dafb0 T resource_build_info_frame
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-ffffffff821db890 T pipe_need_reprogram
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-ffffffff821dbc40 T dc_validate_stream
-ffffffff821dbe50 T dc_validate_plane
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-ffffffff821dbf60 T get_audio_check
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-ffffffff821dc190 T reset_syncd_pipes_from_disabled_pipes
-ffffffff821dc2e0 T check_syncd_pipes_for_disabled_master_pipe
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-ffffffff821dc550 T get_link_hwss
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-ffffffff821dc670 T dc_resource_acquire_secondary_pipe_for_mpc_odm
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-ffffffff821dcb60 t calculate_plane_rec_in_timing_active
-ffffffff821dce80 t calculate_init_and_vp
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+ffffffff821d62e0 T resource_get_num_odm_splits
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+ffffffff821dbc80 T dc_validate_stream
+ffffffff821dbe90 T dc_validate_plane
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+ffffffff821dbfa0 T get_audio_check
+ffffffff821dc0c0 T get_temp_dp_link_res
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+ffffffff821dc8e0 T update_dp_encoder_resources_for_test_harness
+ffffffff821dcba0 t calculate_plane_rec_in_timing_active
+ffffffff821dcec0 t calculate_init_and_vp
 ffffffff821de000 T dc_sink_retain
 ffffffff821de030 T dc_sink_release
 ffffffff821de0b0 T dc_sink_create
@@ -32361,25 +32361,25 @@ ffffffff821e0000 T update_stream_signal
 ffffffff821e0080 T dc_stream_retain
 ffffffff821e00b0 T dc_stream_release
 ffffffff821e0150 T dc_create_stream_for_sink
-ffffffff821e04b0 T dc_copy_stream
-ffffffff821e0590 T dc_stream_get_status_from_state
-ffffffff821e05f0 T dc_stream_get_status
-ffffffff821e0660 T dc_optimize_timing_for_fsft
-ffffffff821e06b0 T dc_stream_set_cursor_attributes
-ffffffff821e08f0 t program_cursor_attributes
-ffffffff821e0a80 T dc_stream_set_cursor_position
-ffffffff821e0be0 t program_cursor_position
-ffffffff821e0d40 T dc_stream_add_writeback
-ffffffff821e0f60 T dc_stream_remove_writeback
-ffffffff821e10a0 T dc_stream_warmup_writeback
-ffffffff821e10e0 T dc_stream_get_vblank_counter
-ffffffff821e11b0 T dc_stream_send_dp_sdp
-ffffffff821e14c0 T dc_stream_get_scanoutpos
-ffffffff821e15a0 T dc_stream_dmdata_status_done
-ffffffff821e1660 T dc_stream_set_dynamic_metadata
-ffffffff821e17d0 T dc_stream_add_dsc_to_resource
-ffffffff821e1820 T dc_stream_get_pipe_ctx
-ffffffff821e18d0 T dc_stream_log
+ffffffff821e04c0 T dc_copy_stream
+ffffffff821e05a0 T dc_stream_get_status_from_state
+ffffffff821e0600 T dc_stream_get_status
+ffffffff821e0670 T dc_optimize_timing_for_fsft
+ffffffff821e06c0 T dc_stream_set_cursor_attributes
+ffffffff821e0900 t program_cursor_attributes
+ffffffff821e0a90 T dc_stream_set_cursor_position
+ffffffff821e0bf0 t program_cursor_position
+ffffffff821e0d50 T dc_stream_add_writeback
+ffffffff821e0f70 T dc_stream_remove_writeback
+ffffffff821e10b0 T dc_stream_warmup_writeback
+ffffffff821e10f0 T dc_stream_get_vblank_counter
+ffffffff821e11c0 T dc_stream_send_dp_sdp
+ffffffff821e14d0 T dc_stream_get_scanoutpos
+ffffffff821e15b0 T dc_stream_dmdata_status_done
+ffffffff821e1670 T dc_stream_set_dynamic_metadata
+ffffffff821e17e0 T dc_stream_add_dsc_to_resource
+ffffffff821e1830 T dc_stream_get_pipe_ctx
+ffffffff821e18e0 T dc_stream_log
 ffffffff821e2000 T enable_surface_flip_reporting
 ffffffff821e2030 T dc_create_plane_state
 ffffffff821e2200 T dc_plane_get_status
@@ -32419,10 +32419,10 @@ ffffffff821e4e50 T dc_dmub_srv_p_state_delegate
 ffffffff821e5200 T dc_dmub_srv_query_caps_cmd
 ffffffff821e52c0 T dc_dmub_srv_get_visual_confirm_color_cmd
 ffffffff821e53b0 T dc_dmub_setup_subvp_dmub_command
-ffffffff821e5e30 T dc_dmub_srv_get_diagnostic_data
-ffffffff821e5e70 T dc_send_update_cursor_info_to_dmu
-ffffffff821e61e0 T dc_dmub_check_min_version
-ffffffff821e6220 T dc_dmub_srv_enable_dpia_trace
+ffffffff821e5e60 T dc_dmub_srv_get_diagnostic_data
+ffffffff821e5ea0 T dc_send_update_cursor_info_to_dmu
+ffffffff821e6210 T dc_dmub_check_min_version
+ffffffff821e6250 T dc_dmub_srv_enable_dpia_trace
 ffffffff821e7000 T dc_edid_parser_send_cea
 ffffffff821e70b0 T dc_edid_parser_recv_cea_ack
 ffffffff821e7140 T dc_edid_parser_recv_amd_vsdb
@@ -32752,28 +32752,28 @@ ffffffff822194e0 T dce110_disable_link_output
 ffffffff822195f0 T dce110_hw_sequencer_construct
 ffffffff82219650 t enable_display_pipe_clock_gating
 ffffffff82219680 t build_audio_output
-ffffffff822197e0 t init_hw
-ffffffff82219b00 t dce110_power_down_fe
-ffffffff82219be0 t dce110_apply_ctx_for_surface
-ffffffff8221a3b0 t dce110_post_unlock_program_front_end
-ffffffff8221a3e0 t update_plane_addr
-ffffffff8221a450 t dce110_wait_for_mpcc_disconnect
-ffffffff8221a480 t dce110_update_pending_status
-ffffffff8221a570 t get_position
-ffffffff8221a600 t dce110_enable_per_frame_crtc_position_reset
-ffffffff8221a910 t dce110_enable_timing_synchronization
-ffffffff8221ac80 t set_drr
-ffffffff8221ad80 t set_static_screen_control
-ffffffff8221ae60 t dce110_set_cursor_position
-ffffffff8221afb0 t dce110_set_cursor_attribute
-ffffffff8221b070 t program_gamut_remap
-ffffffff8221b1d0 t program_output_csc
-ffffffff8221b2d0 t init_pipes
-ffffffff8221b300 t dce110_reset_hw_ctx_wrap
-ffffffff8221b5d0 t dce110_set_input_transfer_func
-ffffffff8221b780 t dce110_set_output_transfer_func
-ffffffff8221c1b0 t dce110_enable_display_power_gating
-ffffffff8221c330 t dce110_enable_stream_timing
+ffffffff822197f0 t init_hw
+ffffffff82219b10 t dce110_power_down_fe
+ffffffff82219bf0 t dce110_apply_ctx_for_surface
+ffffffff8221a3c0 t dce110_post_unlock_program_front_end
+ffffffff8221a3f0 t update_plane_addr
+ffffffff8221a460 t dce110_wait_for_mpcc_disconnect
+ffffffff8221a490 t dce110_update_pending_status
+ffffffff8221a580 t get_position
+ffffffff8221a610 t dce110_enable_per_frame_crtc_position_reset
+ffffffff8221a920 t dce110_enable_timing_synchronization
+ffffffff8221ac90 t set_drr
+ffffffff8221ad90 t set_static_screen_control
+ffffffff8221ae70 t dce110_set_cursor_position
+ffffffff8221afc0 t dce110_set_cursor_attribute
+ffffffff8221b080 t program_gamut_remap
+ffffffff8221b1e0 t program_output_csc
+ffffffff8221b2e0 t init_pipes
+ffffffff8221b310 t dce110_reset_hw_ctx_wrap
+ffffffff8221b5e0 t dce110_set_input_transfer_func
+ffffffff8221b790 t dce110_set_output_transfer_func
+ffffffff8221c1c0 t dce110_enable_display_power_gating
+ffffffff8221c340 t dce110_enable_stream_timing
 ffffffff8221d000 T dce110_mem_input_v_construct
 ffffffff8221d040 t dce_mem_input_v_program_display_marks
 ffffffff8221d0d0 t dce_mem_input_program_chroma_display_marks
@@ -33109,14 +33109,14 @@ ffffffff82257560 T dcn10_set_cursor_position
 ffffffff82257ab0 T dcn10_set_cursor_attribute
 ffffffff82257b10 T dcn10_set_cursor_sdr_white_level
 ffffffff82257be0 T dcn10_get_vupdate_offset_from_vsync
-ffffffff82257c70 T dcn10_calc_vupdate_position
-ffffffff82257d10 T dcn10_setup_periodic_interrupt
-ffffffff82257e30 T dcn10_setup_vupdate_interrupt
-ffffffff82257f00 T dcn10_unblank_stream
-ffffffff82258020 T dcn10_send_immediate_sdp_message
-ffffffff82258080 T dcn10_set_clock
-ffffffff82258190 T dcn10_get_clock
-ffffffff822581f0 T dcn10_get_dcc_en_bits
+ffffffff82257c80 T dcn10_calc_vupdate_position
+ffffffff82257d20 T dcn10_setup_periodic_interrupt
+ffffffff82257e40 T dcn10_setup_vupdate_interrupt
+ffffffff82257f10 T dcn10_unblank_stream
+ffffffff82258030 T dcn10_send_immediate_sdp_message
+ffffffff82258090 T dcn10_set_clock
+ffffffff822581a0 T dcn10_get_clock
+ffffffff82258200 T dcn10_get_dcc_en_bits
 ffffffff82259000 T snprintf_count
 ffffffff82259090 T dcn10_clear_status_bits
 ffffffff82259260 T dcn10_get_hw_state
@@ -33383,39 +33383,39 @@ ffffffff82287560 t dcn20_setup_gsl_group_as_lock
 ffffffff822877d0 T dcn20_disable_plane
 ffffffff822878b0 T dcn20_disable_pixel_data
 ffffffff822878d0 T dcn20_blank_pixel_data
-ffffffff82287b10 T dcn20_enable_stream_timing
-ffffffff82288150 T dcn20_program_output_csc
-ffffffff82288240 T dcn20_set_output_transfer_func
-ffffffff822883e0 T dcn20_set_blend_lut
-ffffffff82288460 T dcn20_set_shaper_3dlut
-ffffffff82288530 T dcn20_set_input_transfer_func
-ffffffff82288730 T dcn20_update_odm
-ffffffff82288830 T dcn20_pipe_control_lock
-ffffffff82288b70 T dcn20_program_front_end_for_ctx
-ffffffff822899d0 t dcn20_program_pipe
-ffffffff8228a5b0 T dcn20_post_unlock_program_front_end
-ffffffff8228a920 T dcn20_prepare_bandwidth
-ffffffff8228aaa0 T dcn20_optimize_bandwidth
-ffffffff8228acd0 T dcn20_update_bandwidth
-ffffffff8228afc0 T dcn20_enable_writeback
-ffffffff8228b140 T dcn20_disable_writeback
-ffffffff8228b1e0 T dcn20_wait_for_blank_complete
-ffffffff8228b280 T dcn20_dmdata_status_done
-ffffffff8228b2d0 T dcn20_disable_stream_gating
-ffffffff8228b380 T dcn20_enable_stream_gating
-ffffffff8228b430 T dcn20_set_dmdata_attributes
-ffffffff8228b4f0 T dcn20_init_vm_ctx
-ffffffff8228b5c0 T dcn20_init_sys_ctx
-ffffffff8228b670 T dcn20_update_plane_addr
-ffffffff8228b7c0 T dcn20_unblank_stream
-ffffffff8228b9a0 T dcn20_setup_vupdate_interrupt
-ffffffff8228ba10 T dcn20_reset_hw_ctx_wrap
-ffffffff8228be20 T dcn20_update_mpcc
-ffffffff8228c0c0 T dcn20_enable_stream
-ffffffff8228c470 T dcn20_program_dmdata_engine
-ffffffff8228c510 T dcn20_fpga_init_hw
-ffffffff8228cb90 T dcn20_optimize_timing_for_fsft
-ffffffff8228cbd0 T dcn20_set_disp_pattern_generator
+ffffffff82287b20 T dcn20_enable_stream_timing
+ffffffff82288160 T dcn20_program_output_csc
+ffffffff82288250 T dcn20_set_output_transfer_func
+ffffffff822883f0 T dcn20_set_blend_lut
+ffffffff82288470 T dcn20_set_shaper_3dlut
+ffffffff82288540 T dcn20_set_input_transfer_func
+ffffffff82288740 T dcn20_update_odm
+ffffffff82288840 T dcn20_pipe_control_lock
+ffffffff82288b80 T dcn20_program_front_end_for_ctx
+ffffffff822899e0 t dcn20_program_pipe
+ffffffff8228a5c0 T dcn20_post_unlock_program_front_end
+ffffffff8228a930 T dcn20_prepare_bandwidth
+ffffffff8228aab0 T dcn20_optimize_bandwidth
+ffffffff8228ace0 T dcn20_update_bandwidth
+ffffffff8228afd0 T dcn20_enable_writeback
+ffffffff8228b150 T dcn20_disable_writeback
+ffffffff8228b1f0 T dcn20_wait_for_blank_complete
+ffffffff8228b290 T dcn20_dmdata_status_done
+ffffffff8228b2e0 T dcn20_disable_stream_gating
+ffffffff8228b390 T dcn20_enable_stream_gating
+ffffffff8228b440 T dcn20_set_dmdata_attributes
+ffffffff8228b500 T dcn20_init_vm_ctx
+ffffffff8228b5d0 T dcn20_init_sys_ctx
+ffffffff8228b680 T dcn20_update_plane_addr
+ffffffff8228b7d0 T dcn20_unblank_stream
+ffffffff8228b9b0 T dcn20_setup_vupdate_interrupt
+ffffffff8228ba20 T dcn20_reset_hw_ctx_wrap
+ffffffff8228be30 T dcn20_update_mpcc
+ffffffff8228c0d0 T dcn20_enable_stream
+ffffffff8228c480 T dcn20_program_dmdata_engine
+ffffffff8228c520 T dcn20_fpga_init_hw
+ffffffff8228cba0 T dcn20_optimize_timing_for_fsft
+ffffffff8228cbe0 T dcn20_set_disp_pattern_generator
 ffffffff8228d000 T dcn20_hw_sequencer_construct
 ffffffff8228e000 T enc2_fec_set_enable
 ffffffff8228e090 T enc2_fec_set_ready
@@ -33491,28 +33491,28 @@ ffffffff82295d20 T dcn20_acquire_dsc
 ffffffff82295e60 T dcn20_release_dsc
 ffffffff82295ed0 T dcn20_add_dsc_to_stream_resource
 ffffffff82296040 T dcn20_add_stream_to_ctx
-ffffffff822960f0 T dcn20_remove_stream_from_ctx
-ffffffff822961e0 T dcn20_split_stream_for_odm
-ffffffff822966e0 T dcn20_split_stream_for_mpc
-ffffffff82296880 T dcn20_calc_max_scaled_time
-ffffffff822968f0 T dcn20_set_mcif_arb_params
-ffffffff82296a70 T dcn20_validate_dsc
-ffffffff82296c30 T dcn20_find_secondary_pipe
-ffffffff82296e20 T dcn20_merge_pipes_for_validate
-ffffffff822970a0 T dcn20_validate_apply_pipe_split_flags
-ffffffff822979a0 T dcn20_fast_validate_bw
-ffffffff82297fb0 T dcn20_validate_bandwidth
-ffffffff82298050 T dcn20_acquire_free_pipe_for_layer
-ffffffff82298190 T dcn20_get_dcc_compression_cap
-ffffffff822981c0 T dcn20_patch_unknown_plane_state
-ffffffff82298220 T dcn20_dwbc_create
-ffffffff82298360 T dcn20_mmhubbub_create
-ffffffff822984f0 T dcn20_create_resource_pool
-ffffffff8229a010 t dcn20_resource_destruct
-ffffffff8229a560 t dcn20_destroy_resource_pool
-ffffffff8229a5d0 t dcn20_panel_cntl_create
-ffffffff8229a660 t read_dce_straps
-ffffffff8229a690 t dcn20_create_audio
+ffffffff82296100 T dcn20_remove_stream_from_ctx
+ffffffff822961f0 T dcn20_split_stream_for_odm
+ffffffff822966f0 T dcn20_split_stream_for_mpc
+ffffffff82296890 T dcn20_calc_max_scaled_time
+ffffffff82296900 T dcn20_set_mcif_arb_params
+ffffffff82296a80 T dcn20_validate_dsc
+ffffffff82296c50 T dcn20_find_secondary_pipe
+ffffffff82296e40 T dcn20_merge_pipes_for_validate
+ffffffff822970c0 T dcn20_validate_apply_pipe_split_flags
+ffffffff822979c0 T dcn20_fast_validate_bw
+ffffffff82297fd0 T dcn20_validate_bandwidth
+ffffffff82298070 T dcn20_acquire_free_pipe_for_layer
+ffffffff822981b0 T dcn20_get_dcc_compression_cap
+ffffffff822981e0 T dcn20_patch_unknown_plane_state
+ffffffff82298240 T dcn20_dwbc_create
+ffffffff82298380 T dcn20_mmhubbub_create
+ffffffff82298510 T dcn20_create_resource_pool
+ffffffff8229a030 t dcn20_resource_destruct
+ffffffff8229a580 t dcn20_destroy_resource_pool
+ffffffff8229a5f0 t dcn20_panel_cntl_create
+ffffffff8229a680 t read_dce_straps
+ffffffff8229a6b0 t dcn20_create_audio
 ffffffff8229b000 T enc2_set_dynamic_metadata
 ffffffff8229b2a0 T enc2_stream_encoder_dp_unblank
 ffffffff8229b660 T enc2_stream_encoder_dp_set_stream_attribute
@@ -33774,23 +33774,23 @@ ffffffff822d9370 T dcn30_acquire_post_bldn_3dlut
 ffffffff822d9500 T dcn30_release_post_bldn_3dlut
 ffffffff822d95b0 T dcn30_internal_validate_bw
 ffffffff822da3e0 t dcn30_split_stream_for_mpc_or_odm
-ffffffff822da730 T dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch
-ffffffff822da820 t is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch
-ffffffff822da8c0 T dcn30_setup_mclk_switch_using_fw_based_vblank_stretch
-ffffffff822da970 T dcn30_update_soc_for_wm_a
-ffffffff822da9d0 T dcn30_calculate_wm_and_dlg
-ffffffff822daa50 T dcn30_validate_bandwidth
-ffffffff822daf00 T dcn30_update_bw_bounding_box
-ffffffff822db5f0 T dcn30_create_resource_pool
-ffffffff822dcef0 t dcn30_resource_destruct
-ffffffff822dd550 t dcn30_destroy_resource_pool
-ffffffff822dd5c0 t dcn30_panel_cntl_create
-ffffffff822dd650 t dcn30_link_encoder_create
-ffffffff822dd710 t dcn30_get_panel_config_defaults
-ffffffff822dd790 t read_dce_straps
-ffffffff822dd7c0 t dcn30_create_audio
-ffffffff822dd7f0 t dcn30_stream_encoder_create
-ffffffff822dd9b0 t dcn30_hwseq_create
+ffffffff822da740 T dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch
+ffffffff822da830 t is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch
+ffffffff822da8e0 T dcn30_setup_mclk_switch_using_fw_based_vblank_stretch
+ffffffff822da990 T dcn30_update_soc_for_wm_a
+ffffffff822da9f0 T dcn30_calculate_wm_and_dlg
+ffffffff822daa70 T dcn30_validate_bandwidth
+ffffffff822daf20 T dcn30_update_bw_bounding_box
+ffffffff822db610 T dcn30_create_resource_pool
+ffffffff822dcf10 t dcn30_resource_destruct
+ffffffff822dd570 t dcn30_destroy_resource_pool
+ffffffff822dd5e0 t dcn30_panel_cntl_create
+ffffffff822dd670 t dcn30_link_encoder_create
+ffffffff822dd730 t dcn30_get_panel_config_defaults
+ffffffff822dd7b0 t read_dce_straps
+ffffffff822dd7e0 t dcn30_create_audio
+ffffffff822dd810 t dcn30_stream_encoder_create
+ffffffff822dd9d0 t dcn30_hwseq_create
 ffffffff822de000 T vpg3_update_generic_info_packet
 ffffffff822dea10 T vpg3_construct
 ffffffff822df000 T dccg301_create
@@ -34202,16 +34202,16 @@ ffffffff8234a3e0 T dcn32_subvp_in_use
 ffffffff8234a470 T dcn32_mpo_in_use
 ffffffff8234a4e0 T dcn32_any_surfaces_rotated
 ffffffff8234a570 T dcn32_is_center_timing
-ffffffff8234a5e0 T dcn32_is_psr_capable
-ffffffff8234a630 T dcn32_determine_det_override
-ffffffff8234a970 T dcn32_set_det_allocations
-ffffffff8234ab00 T dcn32_save_mall_state
-ffffffff8234abb0 T dcn32_restore_mall_state
-ffffffff8234ac60 T dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch
-ffffffff8234ae50 t is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch
-ffffffff8234af00 T dcn32_check_native_scaling_for_res
-ffffffff8234af60 T dcn32_subvp_drr_admissable
-ffffffff8234b130 T dcn32_subvp_vblank_admissable
+ffffffff8234a5f0 T dcn32_is_psr_capable
+ffffffff8234a640 T dcn32_determine_det_override
+ffffffff8234a980 T dcn32_set_det_allocations
+ffffffff8234ab10 T dcn32_save_mall_state
+ffffffff8234abc0 T dcn32_restore_mall_state
+ffffffff8234ac70 T dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch
+ffffffff8234ae60 t is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch
+ffffffff8234af10 T dcn32_check_native_scaling_for_res
+ffffffff8234af80 T dcn32_subvp_drr_admissable
+ffffffff8234b150 T dcn32_subvp_vblank_admissable
 ffffffff8234c000 T dcn321_link_encoder_construct
 ffffffff8234d000 T dcn321_create_resource_pool
 ffffffff8234d0d0 t dcn321_resource_construct
@@ -34257,32 +34257,32 @@ ffffffff8237e540 T dcn_bw_fabs
 ffffffff8237e580 T dcn_bw_log
 ffffffff8237f000 T swizzle_mode_to_macro_tile_size
 ffffffff8237f0a0 T dcn_validate_bandwidth
-ffffffff82381440 T dcn_bw_sync_calcs_and_dml
-ffffffff82381690 t dcn_bw_calc_rq_dlg_ttu
-ffffffff82381ec0 T dcn_find_dcfclk_suits_all
-ffffffff82382380 T dcn_bw_update_from_pplib_fclks
-ffffffff82382500 T dcn_bw_update_from_pplib_dcfclks
-ffffffff823825d0 T dcn_get_soc_clks
-ffffffff82382650 T dcn_bw_notify_pplib_of_wm_ranges
+ffffffff82381450 T dcn_bw_sync_calcs_and_dml
+ffffffff823816a0 t dcn_bw_calc_rq_dlg_ttu
+ffffffff82381ed0 T dcn_find_dcfclk_suits_all
+ffffffff82382390 T dcn_bw_update_from_pplib_fclks
+ffffffff82382510 T dcn_bw_update_from_pplib_dcfclks
+ffffffff823825e0 T dcn_get_soc_clks
+ffffffff82382660 T dcn_bw_notify_pplib_of_wm_ranges
 ffffffff82383000 T dcn10_resource_construct_fp
 ffffffff82384000 T dcn20_populate_dml_writeback_from_context
 ffffffff82384190 T dcn20_fpu_set_wb_arb_params
 ffffffff82384390 T dcn20_calculate_dlg_params
 ffffffff82384c20 T dcn20_populate_dml_pipes_from_context
-ffffffff82385ba0 T dcn20_calculate_wm
-ffffffff823864a0 T dcn20_update_bounding_box
-ffffffff82386730 T dcn20_cap_soc_clocks
-ffffffff82386aa0 T dcn20_patch_bounding_box
-ffffffff82386c90 T dcn20_validate_bandwidth_fp
-ffffffff82386e60 t dcn20_validate_bandwidth_internal
-ffffffff823872e0 T dcn20_fpu_set_wm_ranges
-ffffffff82387390 T dcn20_fpu_adjust_dppclk
-ffffffff82387430 T dcn21_populate_dml_pipes_from_context
-ffffffff82387550 T dcn21_validate_bandwidth_fp
-ffffffff82388090 T dcn21_update_bw_bounding_box
-ffffffff823884c0 T dcn21_clk_mgr_set_bw_params_wm_table
-ffffffff82388530 T dcn201_populate_dml_writeback_from_context_fpu
-ffffffff82388840 t calculate_wm_set_for_vlevel
+ffffffff82385bc0 T dcn20_calculate_wm
+ffffffff823864c0 T dcn20_update_bounding_box
+ffffffff82386750 T dcn20_cap_soc_clocks
+ffffffff82386ac0 T dcn20_patch_bounding_box
+ffffffff82386cb0 T dcn20_validate_bandwidth_fp
+ffffffff82386e80 t dcn20_validate_bandwidth_internal
+ffffffff82387300 T dcn20_fpu_set_wm_ranges
+ffffffff823873b0 T dcn20_fpu_adjust_dppclk
+ffffffff82387450 T dcn21_populate_dml_pipes_from_context
+ffffffff82387570 T dcn21_validate_bandwidth_fp
+ffffffff823880b0 T dcn21_update_bw_bounding_box
+ffffffff823884e0 T dcn21_clk_mgr_set_bw_params_wm_table
+ffffffff82388550 T dcn201_populate_dml_writeback_from_context_fpu
+ffffffff82388860 t calculate_wm_set_for_vlevel
 ffffffff82389000 T dml20_recalculate
 ffffffff823897b0 t dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
 ffffffff8238f050 T dml20_ModeSupportAndSystemConfigurationFull
@@ -34313,7 +34313,7 @@ ffffffff823ae000 T dml20v2_rq_dlg_get_rq_reg
 ffffffff823ae4e0 t dml20v2_rq_dlg_get_rq_params
 ffffffff823ae6b0 T dml20v2_rq_dlg_get_dlg_reg
 ffffffff823b0990 t get_surf_rq_param
-ffffffff823b1220 t calculate_ttu_cursor
+ffffffff823b1250 t calculate_ttu_cursor
 ffffffff823b2000 T dml21_recalculate
 ffffffff823b2770 t DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
 ffffffff823b8290 T dml21_ModeSupportAndSystemConfigurationFull
@@ -34331,7 +34331,7 @@ ffffffff823c4000 T dml21_rq_dlg_get_rq_reg
 ffffffff823c44e0 t dml_rq_dlg_get_rq_params
 ffffffff823c46b0 T dml21_rq_dlg_get_dlg_reg
 ffffffff823c6e10 t get_surf_rq_param
-ffffffff823c7780 t calculate_ttu_cursor
+ffffffff823c7770 t calculate_ttu_cursor
 ffffffff823c8000 T optc3_fpu_set_vrr_m_const
 ffffffff823c8540 T dcn30_fpu_populate_dml_writeback_from_context
 ffffffff823c8860 T dcn30_fpu_set_mcif_arb_params
@@ -34435,23 +34435,23 @@ ffffffff82420670 t get_surf_rq_param
 ffffffff82422000 T dcn32_build_wm_range_table_fpu
 ffffffff824223a0 T dcn32_find_dummy_latency_index_for_fw_based_mclk_switch
 ffffffff82422570 T dcn32_internal_validate_bw
-ffffffff824245f0 T dcn32_helper_populate_phantom_dlg_params
-ffffffff824247b0 T dcn32_predict_pipe_split
-ffffffff82424a00 T dcn32_set_phantom_stream_timing
-ffffffff82424d30 T dcn32_determine_max_vratio_prefetch
-ffffffff82424e10 t dcn32_split_stream_for_mpc_or_odm
-ffffffff82425200 T dcn32_calculate_wm_and_dlg_fpu
-ffffffff82426b20 T dcn32_patch_dpm_table
-ffffffff82426d30 T dcn32_update_bw_bounding_box_fpu
-ffffffff82429480 T dcn32_zero_pipe_dcc_fraction
-ffffffff824294f0 T dcn32_allow_subvp_with_active_margin
-ffffffff824295c0 T dcn32_allow_subvp_high_refresh_rate
-ffffffff824297e0 T dcn32_assign_fpo_vactive_candidate
-ffffffff824298a0 T dcn32_find_vactive_pipe
-ffffffff82429a10 T dcn32_set_clock_limits
-ffffffff82429a60 T dcn32_override_min_req_memclk
-ffffffff82429b30 t subvp_drr_schedulable
-ffffffff82429df0 t get_optimal_ntuple
+ffffffff82424610 T dcn32_helper_populate_phantom_dlg_params
+ffffffff824247d0 T dcn32_predict_pipe_split
+ffffffff82424a20 T dcn32_set_phantom_stream_timing
+ffffffff82424d50 T dcn32_determine_max_vratio_prefetch
+ffffffff82424e30 t dcn32_split_stream_for_mpc_or_odm
+ffffffff82425220 T dcn32_calculate_wm_and_dlg_fpu
+ffffffff82426b40 T dcn32_patch_dpm_table
+ffffffff82426d50 T dcn32_update_bw_bounding_box_fpu
+ffffffff824294a0 T dcn32_zero_pipe_dcc_fraction
+ffffffff82429510 T dcn32_allow_subvp_with_active_margin
+ffffffff824295e0 T dcn32_allow_subvp_high_refresh_rate
+ffffffff82429800 T dcn32_assign_fpo_vactive_candidate
+ffffffff824298c0 T dcn32_find_vactive_pipe
+ffffffff82429a30 T dcn32_set_clock_limits
+ffffffff82429a80 T dcn32_override_min_req_memclk
+ffffffff82429b50 t subvp_drr_schedulable
+ffffffff82429e20 t get_optimal_ntuple
 ffffffff8242b000 T dml32_recalculate
 ffffffff8242f510 T dml32_ModeSupportAndSystemConfigurationFull
 ffffffff82438000 T dml32_dscceComputeDelay
@@ -34906,15 +34906,15 @@ ffffffff82499160 T setup_hpo_dp_stream_encoder
 ffffffff824991b0 T reset_hpo_dp_stream_encoder
 ffffffff824991d0 T setup_hpo_dp_stream_attribute
 ffffffff82499250 T enable_hpo_dp_link_output
-ffffffff824992d0 T disable_hpo_dp_link_output
-ffffffff82499380 T update_hpo_dp_stream_allocation_table
-ffffffff824993a0 T setup_hpo_dp_audio_output
-ffffffff824993e0 T enable_hpo_dp_audio_packet
-ffffffff82499400 T disable_hpo_dp_audio_packet
-ffffffff82499450 T can_use_hpo_dp_link_hwss
-ffffffff82499480 T get_hpo_dp_link_hwss
-ffffffff824994b0 t set_hpo_dp_link_test_pattern
-ffffffff82499510 t set_hpo_dp_lane_settings
+ffffffff82499300 T disable_hpo_dp_link_output
+ffffffff824993d0 T update_hpo_dp_stream_allocation_table
+ffffffff824993f0 T setup_hpo_dp_audio_output
+ffffffff82499430 T enable_hpo_dp_audio_packet
+ffffffff82499450 T disable_hpo_dp_audio_packet
+ffffffff824994a0 T can_use_hpo_dp_link_hwss
+ffffffff824994d0 T get_hpo_dp_link_hwss
+ffffffff82499500 t set_hpo_dp_link_test_pattern
+ffffffff82499560 t set_hpo_dp_lane_settings
 ffffffff8249a000 T requires_fixed_vs_pe_retimer_hpo_link_hwss
 ffffffff8249a040 T get_hpo_fixed_vs_pe_retimer_dp_link_hwss
 ffffffff8249a070 t enable_hpo_fixed_vs_pe_retimer_dp_link_output
@@ -34938,28 +34938,28 @@ ffffffff8249e300 T link_set_all_streams_dpms_off_for_l
 ffffffff8249e420 T link_get_master_pipes_with_dpms_on
 ffffffff8249e610 T link_resume
 ffffffff8249e650 T link_set_dsc_on_stream
-ffffffff8249eb90 T link_set_dsc_pps_packet
-ffffffff8249ef50 T link_set_dsc_enable
-ffffffff8249f000 T link_update_dsc_config
-ffffffff8249f080 T link_calculate_sst_avg_time_slots_per_mtp
-ffffffff8249f120 T link_reduce_mst_payload
-ffffffff8249f5f0 t update_mst_stream_alloc_table
-ffffffff8249f880 T link_increase_mst_payload
-ffffffff8249fd40 T link_set_dpms_off
-ffffffff824a0aa0 t update_psp_stream_config
-ffffffff824a0ce0 t update_sst_payload
-ffffffff824a1490 t get_ext_hdmi_settings
-ffffffff824a16e0 t write_i2c_retimer_setting
-ffffffff824a1dc0 t write_i2c_default_retimer_setting
-ffffffff824a2350 t write_i2c_redriver_setting
-ffffffff824a2480 t disable_link
-ffffffff824a2620 T link_set_dpms_on
-ffffffff824a3200 t enable_stream_features
-ffffffff824a32c0 t allocate_usb4_bandwidth
-ffffffff824a3300 t allocate_mst_payload
-ffffffff824a3830 t log_vcp_x_y
-ffffffff824a39e0 t write_i2c
-ffffffff824a3a80 t enable_link_dp
+ffffffff8249eba0 T link_set_dsc_pps_packet
+ffffffff8249ef70 T link_set_dsc_enable
+ffffffff8249f020 T link_update_dsc_config
+ffffffff8249f0b0 T link_calculate_sst_avg_time_slots_per_mtp
+ffffffff8249f150 T link_reduce_mst_payload
+ffffffff8249f620 t update_mst_stream_alloc_table
+ffffffff8249f8b0 T link_increase_mst_payload
+ffffffff8249fd70 T link_set_dpms_off
+ffffffff824a0ae0 t update_psp_stream_config
+ffffffff824a0d20 t update_sst_payload
+ffffffff824a14d0 t get_ext_hdmi_settings
+ffffffff824a1720 t write_i2c_retimer_setting
+ffffffff824a1e00 t write_i2c_default_retimer_setting
+ffffffff824a2390 t write_i2c_redriver_setting
+ffffffff824a24c0 t disable_link
+ffffffff824a2660 T link_set_dpms_on
+ffffffff824a3250 t enable_stream_features
+ffffffff824a3310 t allocate_usb4_bandwidth
+ffffffff824a3350 t allocate_mst_payload
+ffffffff824a3880 t log_vcp_x_y
+ffffffff824a3a30 t write_i2c
+ffffffff824a3ad0 t enable_link_dp
 ffffffff824a4000 T link_create_link_service
 ffffffff824a4480 T link_destroy_link_service
 ffffffff824a44d0 T link_create
@@ -35431,10 +35431,10 @@ ffffffff824eb580 t fill_iram_v_2_3
 ffffffff824eba30 T dmcu_load_iram
 ffffffff824ec260 T is_psr_su_specific_panel
 ffffffff824ec300 T mod_power_calc_psr_configs
-ffffffff824ec3f0 T init_replay_config
-ffffffff824ec440 T mod_power_only_edp
-ffffffff824ec490 T psr_su_set_dsc_slice_height
-ffffffff824ec580 T fill_custom_backlight_caps
+ffffffff824ec400 T init_replay_config
+ffffffff824ec450 T mod_power_only_edp
+ffffffff824ec4a0 T psr_su_set_dsc_slice_height
+ffffffff824ec5a0 T fill_custom_backlight_caps
 ffffffff824ed000 T mod_vmid_get_for_ptb
 ffffffff824ed240 T mod_vmid_reset
 ffffffff824ed300 T mod_vmid_create
@@ -35746,9 +35746,9 @@ ffffffff8250a0f0 T pp_tables_get_num_of_entries
 ffffffff8250a1c0 T pp_tables_get_entry
 ffffffff8250a520 t init_non_clock_fields
 ffffffff8250a660 t pp_tables_initialize
-ffffffff8250b8a0 t pp_tables_uninitialize
-ffffffff8250bb30 t get_number_of_vce_state_table_entries
-ffffffff8250bc20 t get_vce_state_table_entry
+ffffffff8250b910 t pp_tables_uninitialize
+ffffffff8250bba0 t get_number_of_vce_state_table_entries
+ffffffff8250bc90 t get_vce_state_table_entry
 ffffffff8250c000 T smu10_init_function_pointers
 ffffffff8250c040 t smu10_hwmgr_backend_init
 ffffffff8250c770 t smu10_hwmgr_backend_fini
@@ -42206,18 +42206,18 @@ ffffffff8283a000 r isomappings
 ffffffff8283a080 r unimappings
 ffffffff8283a230 r replacements
 ffffffff8283dacd r apollo_pio_rec
-ffffffff8288baf1 r apollo_udma33_tim
-ffffffff828a11e1 r pp_r600_decoded_lanes
-ffffffff828d842b r cmd680_setup_channel.udma_tbl
-ffffffff828e09bd r apollo_udma100_tim
-ffffffff828e09c3 r cmd0646_9_tim_udma
-ffffffff828ef2dc r substchar
-ffffffff82946abb r apollo_udma133_tim
-ffffffff82946ac2 r apollo_udma66_tim
-ffffffff82946aec r cy_pio_rec
-ffffffff8294c2f8 R drm_ca
-ffffffff8294c320 R drm_filtops
-ffffffff8294c350 R drmread_filtops
+ffffffff8288bb54 r apollo_udma33_tim
+ffffffff828a1244 r pp_r600_decoded_lanes
+ffffffff828d84fe r cmd680_setup_channel.udma_tbl
+ffffffff828e0a90 r apollo_udma100_tim
+ffffffff828e0a96 r cmd0646_9_tim_udma
+ffffffff828ef3c6 r substchar
+ffffffff82946bc0 r apollo_udma133_tim
+ffffffff82946bc7 r apollo_udma66_tim
+ffffffff82946bf1 r cy_pio_rec
+ffffffff8294c400 R drm_ca
+ffffffff8294c428 R drm_filtops
+ffffffff8294c458 R drmread_filtops
 ffffffff8294d000 r vga_emulops
 ffffffff8294d048 R vga_stdscreen
 ffffffff8294d078 R vga_stdscreen_mono
@@ -46411,22 +46411,23 @@ ffffffff82dc2cdc r gfx9_SECT_CONTEXT_def_6
 ffffffff82dc2ce0 r gfx9_SECT_CONTEXT_def_7
 ffffffff82dc2df0 r gfx9_SECT_CONTEXT_def_2
 ffffffff82dc3260 r gfx9_SECT_CONTEXT_def_8
-ffffffff82dc34d0 r vgpr_init_compute_shader_arcturus
-ffffffff82dc3d60 r vgpr_init_regs_arcturus
-ffffffff82dc3ef0 r vgpr_init_regs
-ffffffff82dc4080 r sgpr1_init_regs
-ffffffff82dc4210 r sgpr2_init_regs
-ffffffff82dc43a0 r golden_settings_gc_9_0
-ffffffff82dc4580 r golden_settings_gc_9_0_vg10
-ffffffff82dc4730 r golden_settings_gc_9_2_1
-ffffffff82dc48b0 r golden_settings_gc_9_2_1_vg12
-ffffffff82dc49f0 r golden_settings_gc_9_0_vg20
-ffffffff82dc4b00 r golden_settings_gc_9_4_1_arct
-ffffffff82dc4c10 r golden_settings_gc_9_1
-ffffffff82dc4e50 r golden_settings_gc_9_1_rv2
-ffffffff82dc5020 r golden_settings_gc_9_1_rv1
-ffffffff82dc50d0 r golden_settings_gc_9_1_rn
-ffffffff82dc51f0 r golden_settings_gc_9_x_common
+ffffffff82dc34d0 r amdgpu_gfxoff_quirk_list
+ffffffff82dc3520 r vgpr_init_compute_shader_arcturus
+ffffffff82dc3db0 r vgpr_init_regs_arcturus
+ffffffff82dc3f40 r vgpr_init_regs
+ffffffff82dc40d0 r sgpr1_init_regs
+ffffffff82dc4260 r sgpr2_init_regs
+ffffffff82dc43f0 r golden_settings_gc_9_0
+ffffffff82dc45d0 r golden_settings_gc_9_0_vg10
+ffffffff82dc4780 r golden_settings_gc_9_2_1
+ffffffff82dc4900 r golden_settings_gc_9_2_1_vg12
+ffffffff82dc4a40 r golden_settings_gc_9_0_vg20
+ffffffff82dc4b50 r golden_settings_gc_9_4_1_arct
+ffffffff82dc4c60 r golden_settings_gc_9_1
+ffffffff82dc4ea0 r golden_settings_gc_9_1_rv2
+ffffffff82dc5070 r golden_settings_gc_9_1_rv1
+ffffffff82dc5120 r golden_settings_gc_9_1_rn
+ffffffff82dc5240 r golden_settings_gc_9_x_common
 ffffffff82dc6000 R gfx_v9_4_ras_ops
 ffffffff82dc6040 r gfx_v9_4_edc_counter_regs
 ffffffff82dc6420 r gfx_v9_4_ras_fields