--- 7.5/2024-07-28T20:35:28Z/2024-07-26T03:29:47Z/nm-bsd-ot14.txt	Mon Jul 29 03:04:30 2024
+++ 7.5/2024-07-28T20:35:28Z/2024-07-26T03:32:20Z/nm-bsd-ot14.txt	Mon Jul 29 05:14:58 2024
@@ -29384,92 +29384,92 @@ ffffffff81feaa60 t gfx_v9_4_3_late_init
 ffffffff81feaaf0 t gfx_v9_4_3_sw_init
 ffffffff81feafe0 t gfx_v9_4_3_sw_fini
 ffffffff81feb210 t gfx_v9_4_3_hw_init
-ffffffff81febdf0 t gfx_v9_4_3_hw_fini
-ffffffff81febed0 t gfx_v9_4_3_suspend
-ffffffff81febfb0 t gfx_v9_4_3_resume
-ffffffff81febfc0 t gfx_v9_4_3_is_idle
-ffffffff81fec1b0 t gfx_v9_4_3_wait_for_idle
-ffffffff81fec250 t gfx_v9_4_3_soft_reset
-ffffffff81feca90 t gfx_v9_4_3_set_clockgating_state
-ffffffff81fecc50 t gfx_v9_4_3_set_powergating_state
-ffffffff81fecc80 t gfx_v9_4_3_get_clockgating_state
-ffffffff81fece30 t gfx_v9_4_3_kiq_set_resources
-ffffffff81fed190 t gfx_v9_4_3_kiq_map_queues
-ffffffff81fed530 t gfx_v9_4_3_kiq_unmap_queues
-ffffffff81fed8f0 t gfx_v9_4_3_kiq_query_status
-ffffffff81fedc10 t gfx_v9_4_3_kiq_invalidate_tlbs
-ffffffff81fedd40 t gfx_v9_4_3_ring_get_rptr_compute
-ffffffff81fedd80 t gfx_v9_4_3_ring_get_wptr_compute
-ffffffff81feddf0 t gfx_v9_4_3_ring_set_wptr_compute
-ffffffff81fede50 t gfx_v9_4_3_ring_emit_fence_kiq
-ffffffff81fee2f0 t gfx_v9_4_3_ring_test_ring
-ffffffff81fee590 t gfx_v9_4_3_ring_emit_rreg
-ffffffff81fee850 t gfx_v9_4_3_ring_emit_wreg
-ffffffff81feeab0 t gfx_v9_4_3_ring_emit_reg_wait
-ffffffff81feeb10 t gfx_v9_4_3_ring_emit_reg_write_reg_wait
-ffffffff81feeb30 t gfx_v9_4_3_wait_reg_mem
-ffffffff81feee90 t gfx_v9_4_3_ring_emit_ib_compute
-ffffffff81fef1f0 t gfx_v9_4_3_ring_emit_fence
-ffffffff81fef5e0 t gfx_v9_4_3_ring_emit_pipeline_sync
-ffffffff81fef650 t gfx_v9_4_3_ring_emit_vm_flush
-ffffffff81fef670 t gfx_v9_4_3_ring_emit_hdp_flush
-ffffffff81fef760 t gfx_v9_4_3_ring_emit_gds_switch
-ffffffff81fef940 t gfx_v9_4_3_ring_test_ib
-ffffffff81fefb30 t gfx_v9_4_3_emit_mem_sync
-ffffffff81fefe20 t gfx_v9_4_3_emit_wave_limit
-ffffffff81ff0030 t gfx_v9_4_3_write_data_to_reg
-ffffffff81ff0260 t gfx_v9_4_3_set_eop_interrupt_state
-ffffffff81ff03e0 t gfx_v9_4_3_eop_irq
-ffffffff81ff0590 t gfx_v9_4_3_xcc_set_compute_eop_interrupt_state
-ffffffff81ff0710 t gfx_v9_4_3_ih_to_xcc_inst
-ffffffff81ff07f0 t gfx_v9_4_3_set_priv_reg_fault_state
-ffffffff81ff0c50 t gfx_v9_4_3_priv_reg_irq
-ffffffff81ff0cc0 t gfx_v9_4_3_fault
-ffffffff81ff0e40 t gfx_v9_4_3_set_priv_inst_fault_state
-ffffffff81ff12a0 t gfx_v9_4_3_priv_inst_irq
-ffffffff81ff1310 t gfx_v9_4_3_is_rlc_enabled
-ffffffff81ff1460 t gfx_v9_4_3_xcc_set_safe_mode
-ffffffff81ff1770 t gfx_v9_4_3_xcc_unset_safe_mode
-ffffffff81ff18b0 t gfx_v9_4_3_rlc_init
-ffffffff81ff1910 t gfx_v9_4_3_rlc_resume
-ffffffff81ff19d0 t gfx_v9_4_3_rlc_stop
-ffffffff81ff1a80 t gfx_v9_4_3_rlc_reset
-ffffffff81ff2200 t gfx_v9_4_3_rlc_start
-ffffffff81ff22b0 t gfx_v9_4_3_update_spm_vmid
-ffffffff81ff2510 t gfx_v9_4_3_is_rlcg_access_range
-ffffffff81ff25e0 t gfx_v9_4_3_xcc_rlc_resume
-ffffffff81ff2fa0 t gfx_v9_4_3_xcc_rlc_stop
-ffffffff81ff3800 t gfx_v9_4_3_xcc_rlc_start
-ffffffff81ff3c10 t gfx_v9_4_3_xcc_enable_gui_idle_interrupt
-ffffffff81ff3e70 t gfx_v9_4_3_xcc_select_se_sh
-ffffffff81ff40a0 t gfx_v9_4_3_mec_init
-ffffffff81ff4410 t gfx_v9_4_3_gpu_early_init
-ffffffff81ff4660 t amdgpu_bo_unreserve
-ffffffff81ff4770 t gfx_v9_4_3_get_gpu_clock_counter
-ffffffff81ff4b40 t gfx_v9_4_3_read_wave_data
-ffffffff81ff4ea0 t gfx_v9_4_3_read_wave_vgprs
-ffffffff81ff4ec0 t gfx_v9_4_3_read_wave_sgprs
-ffffffff81ff4f20 t gfx_v9_4_3_select_me_pipe_q
-ffffffff81ff4fa0 t gfx_v9_4_3_switch_compute_partition
-ffffffff81ff5350 t wave_read_ind
-ffffffff81ff5590 t wave_read_regs
-ffffffff81ff5870 t gfx_v9_4_3_xcc_constants_init
-ffffffff81ff6be0 t gfx_v9_4_3_xcc_cp_resume
-ffffffff81ff7e80 t gfx_v9_4_3_xcc_cp_compute_enable
-ffffffff81ff8060 t amdgpu_bo_reserve
-ffffffff81ff8200 t gfx_v9_4_3_xcc_kiq_init_register
-ffffffff81ffa2a0 t gfx_v9_4_3_xcc_mqd_init
-ffffffff81ffae40 t gfx_v9_4_3_xcc_fini
-ffffffff81ffb4c0 t gfx_v9_4_3_xcc_q_fini_register
-ffffffff81ffc020 t gfx_v9_4_3_xcc_update_sram_fgcg
-ffffffff81ffc2d0 t gfx_v9_4_3_xcc_update_repeater_fgcg
-ffffffff81ffc580 t gfx_v9_4_3_xcc_update_medium_grain_clock_gating
-ffffffff81ffd270 t gfx_v9_4_3_xcc_update_coarse_grain_clock_gating
-ffffffff81ffdc00 t gfx_v9_4_3_inst_query_ras_err_count
-ffffffff81ffdeb0 t gfx_v9_4_3_inst_query_ras_err_status
-ffffffff81ffeea0 t gfx_v9_4_3_inst_reset_ras_err_count
-ffffffff81fff090 t gfx_v9_4_3_inst_reset_ras_err_status
-ffffffff81fff930 t gfx_v9_4_3_inst_enable_watchdog_timer
+ffffffff81fec090 t gfx_v9_4_3_hw_fini
+ffffffff81fec170 t gfx_v9_4_3_suspend
+ffffffff81fec250 t gfx_v9_4_3_resume
+ffffffff81fec260 t gfx_v9_4_3_is_idle
+ffffffff81fec450 t gfx_v9_4_3_wait_for_idle
+ffffffff81fec4f0 t gfx_v9_4_3_soft_reset
+ffffffff81fecd30 t gfx_v9_4_3_set_clockgating_state
+ffffffff81fecef0 t gfx_v9_4_3_set_powergating_state
+ffffffff81fecf20 t gfx_v9_4_3_get_clockgating_state
+ffffffff81fed0d0 t gfx_v9_4_3_kiq_set_resources
+ffffffff81fed430 t gfx_v9_4_3_kiq_map_queues
+ffffffff81fed7d0 t gfx_v9_4_3_kiq_unmap_queues
+ffffffff81fedb90 t gfx_v9_4_3_kiq_query_status
+ffffffff81fedeb0 t gfx_v9_4_3_kiq_invalidate_tlbs
+ffffffff81fedfe0 t gfx_v9_4_3_ring_get_rptr_compute
+ffffffff81fee020 t gfx_v9_4_3_ring_get_wptr_compute
+ffffffff81fee090 t gfx_v9_4_3_ring_set_wptr_compute
+ffffffff81fee0f0 t gfx_v9_4_3_ring_emit_fence_kiq
+ffffffff81fee590 t gfx_v9_4_3_ring_test_ring
+ffffffff81fee830 t gfx_v9_4_3_ring_emit_rreg
+ffffffff81feeaf0 t gfx_v9_4_3_ring_emit_wreg
+ffffffff81feed50 t gfx_v9_4_3_ring_emit_reg_wait
+ffffffff81feedb0 t gfx_v9_4_3_ring_emit_reg_write_reg_wait
+ffffffff81feedd0 t gfx_v9_4_3_wait_reg_mem
+ffffffff81fef130 t gfx_v9_4_3_ring_emit_ib_compute
+ffffffff81fef490 t gfx_v9_4_3_ring_emit_fence
+ffffffff81fef880 t gfx_v9_4_3_ring_emit_pipeline_sync
+ffffffff81fef8f0 t gfx_v9_4_3_ring_emit_vm_flush
+ffffffff81fef910 t gfx_v9_4_3_ring_emit_hdp_flush
+ffffffff81fefa00 t gfx_v9_4_3_ring_emit_gds_switch
+ffffffff81fefbe0 t gfx_v9_4_3_ring_test_ib
+ffffffff81fefdd0 t gfx_v9_4_3_emit_mem_sync
+ffffffff81ff00c0 t gfx_v9_4_3_emit_wave_limit
+ffffffff81ff02d0 t gfx_v9_4_3_write_data_to_reg
+ffffffff81ff0500 t gfx_v9_4_3_set_eop_interrupt_state
+ffffffff81ff0680 t gfx_v9_4_3_eop_irq
+ffffffff81ff0830 t gfx_v9_4_3_xcc_set_compute_eop_interrupt_state
+ffffffff81ff09b0 t gfx_v9_4_3_ih_to_xcc_inst
+ffffffff81ff0a90 t gfx_v9_4_3_set_priv_reg_fault_state
+ffffffff81ff0ef0 t gfx_v9_4_3_priv_reg_irq
+ffffffff81ff0f60 t gfx_v9_4_3_fault
+ffffffff81ff10e0 t gfx_v9_4_3_set_priv_inst_fault_state
+ffffffff81ff1540 t gfx_v9_4_3_priv_inst_irq
+ffffffff81ff15b0 t gfx_v9_4_3_is_rlc_enabled
+ffffffff81ff1700 t gfx_v9_4_3_xcc_set_safe_mode
+ffffffff81ff1a10 t gfx_v9_4_3_xcc_unset_safe_mode
+ffffffff81ff1b50 t gfx_v9_4_3_rlc_init
+ffffffff81ff1bb0 t gfx_v9_4_3_rlc_resume
+ffffffff81ff1c70 t gfx_v9_4_3_rlc_stop
+ffffffff81ff1d20 t gfx_v9_4_3_rlc_reset
+ffffffff81ff24a0 t gfx_v9_4_3_rlc_start
+ffffffff81ff2550 t gfx_v9_4_3_update_spm_vmid
+ffffffff81ff27b0 t gfx_v9_4_3_is_rlcg_access_range
+ffffffff81ff2880 t gfx_v9_4_3_xcc_rlc_resume
+ffffffff81ff3240 t gfx_v9_4_3_xcc_rlc_stop
+ffffffff81ff3aa0 t gfx_v9_4_3_xcc_rlc_start
+ffffffff81ff3eb0 t gfx_v9_4_3_xcc_enable_gui_idle_interrupt
+ffffffff81ff4110 t gfx_v9_4_3_xcc_select_se_sh
+ffffffff81ff4340 t gfx_v9_4_3_mec_init
+ffffffff81ff46b0 t gfx_v9_4_3_gpu_early_init
+ffffffff81ff4900 t amdgpu_bo_unreserve
+ffffffff81ff4a10 t gfx_v9_4_3_get_gpu_clock_counter
+ffffffff81ff4de0 t gfx_v9_4_3_read_wave_data
+ffffffff81ff5140 t gfx_v9_4_3_read_wave_vgprs
+ffffffff81ff5160 t gfx_v9_4_3_read_wave_sgprs
+ffffffff81ff51c0 t gfx_v9_4_3_select_me_pipe_q
+ffffffff81ff5240 t gfx_v9_4_3_switch_compute_partition
+ffffffff81ff55f0 t wave_read_ind
+ffffffff81ff5830 t wave_read_regs
+ffffffff81ff5b10 t gfx_v9_4_3_xcc_constants_init
+ffffffff81ff6e80 t gfx_v9_4_3_xcc_cp_resume
+ffffffff81ff8120 t gfx_v9_4_3_xcc_cp_compute_enable
+ffffffff81ff8300 t amdgpu_bo_reserve
+ffffffff81ff84a0 t gfx_v9_4_3_xcc_kiq_init_register
+ffffffff81ffa540 t gfx_v9_4_3_xcc_mqd_init
+ffffffff81ffb0e0 t gfx_v9_4_3_xcc_fini
+ffffffff81ffb760 t gfx_v9_4_3_xcc_q_fini_register
+ffffffff81ffc2c0 t gfx_v9_4_3_xcc_update_sram_fgcg
+ffffffff81ffc570 t gfx_v9_4_3_xcc_update_repeater_fgcg
+ffffffff81ffc820 t gfx_v9_4_3_xcc_update_medium_grain_clock_gating
+ffffffff81ffd510 t gfx_v9_4_3_xcc_update_coarse_grain_clock_gating
+ffffffff81ffdea0 t gfx_v9_4_3_inst_query_ras_err_count
+ffffffff81ffe150 t gfx_v9_4_3_inst_query_ras_err_status
+ffffffff81fff140 t gfx_v9_4_3_inst_reset_ras_err_count
+ffffffff81fff330 t gfx_v9_4_3_inst_reset_ras_err_status
+ffffffff81fffbd0 t gfx_v9_4_3_inst_enable_watchdog_timer
 ffffffff82000000 t gfxhub_v1_0_get_mc_fb_offset
 ffffffff820000a0 t gfxhub_v1_0_setup_vm_pt_regs
 ffffffff820001f0 t gfxhub_v1_0_gart_enable