--- 7.5/2024-07-01T06:17:03Z/2024-06-15T00:00:00Z/nm-bsd-ot14.txt	Wed Jul  3 04:34:06 2024
+++ 7.5/2024-07-01T06:17:03Z/2024-06-16T00:00:00Z/nm-bsd-ot14.txt	Wed Jul  3 07:41:57 2024
@@ -12920,10 +12920,10 @@ ffffffff816a60c0 T cpu_intr_init
 ffffffff816a6350 T intr_printconfig
 ffffffff816a6380 T intr_barrier
 ffffffff816a63a0 T intr_enable_wakeup
-ffffffff816a6430 T intr_disable_wakeup
-ffffffff816a64c0 T splraise
-ffffffff816a6530 T spllower
-ffffffff816a65a0 T softintr
+ffffffff816a6440 T intr_disable_wakeup
+ffffffff816a64e0 T splraise
+ffffffff816a6550 T spllower
+ffffffff816a65c0 T softintr
 ffffffff816a7000 T x86_bus_space_io_read_1
 ffffffff816a7030 T x86_bus_space_io_read_2
 ffffffff816a7060 T x86_bus_space_io_read_4
@@ -19511,19 +19511,19 @@ ffffffff81a36540 T drm_bridge_chain_mode_valid
 ffffffff81a365f0 T drm_bridge_chain_mode_set
 ffffffff81a36690 T drm_atomic_bridge_chain_disable
 ffffffff81a367a0 T drm_atomic_bridge_chain_post_disable
-ffffffff81a36a10 T drm_atomic_bridge_chain_pre_enable
-ffffffff81a36c90 T drm_atomic_bridge_chain_enable
-ffffffff81a36dc0 T drm_atomic_bridge_chain_check
-ffffffff81a371c0 T drm_bridge_detect
-ffffffff81a37220 T drm_bridge_get_modes
-ffffffff81a37280 T drm_bridge_edid_read
-ffffffff81a37350 T drm_bridge_get_edid
-ffffffff81a373b0 T drm_bridge_hpd_enable
-ffffffff81a37490 T drm_bridge_hpd_disable
-ffffffff81a37530 T drm_bridge_hpd_notify
-ffffffff81a37590 t drm_bridge_atomic_duplicate_priv_state
-ffffffff81a375b0 t drm_bridge_atomic_destroy_priv_state
-ffffffff81a375d0 t select_bus_fmt_recursive
+ffffffff81a369e0 T drm_atomic_bridge_chain_pre_enable
+ffffffff81a36c50 T drm_atomic_bridge_chain_enable
+ffffffff81a36d80 T drm_atomic_bridge_chain_check
+ffffffff81a37180 T drm_bridge_detect
+ffffffff81a371e0 T drm_bridge_get_modes
+ffffffff81a37240 T drm_bridge_edid_read
+ffffffff81a37310 T drm_bridge_get_edid
+ffffffff81a37370 T drm_bridge_hpd_enable
+ffffffff81a37450 T drm_bridge_hpd_disable
+ffffffff81a374f0 T drm_bridge_hpd_notify
+ffffffff81a37550 t drm_bridge_atomic_duplicate_priv_state
+ffffffff81a37570 t drm_bridge_atomic_destroy_priv_state
+ffffffff81a37590 t select_bus_fmt_recursive
 ffffffff81a38000 T drm_buddy_init
 ffffffff81a384c0 T drm_buddy_fini
 ffffffff81a385d0 T drm_get_buddy
@@ -20689,85 +20689,86 @@ ffffffff81ab6880 T drm_dp_link_rate_to_bw_code
 ffffffff81ab68f0 T drm_dp_bw_code_to_link_rate
 ffffffff81ab6950 T drm_dp_dpcd_probe
 ffffffff81ab6ac0 t drm_dp_dpcd_access
-ffffffff81ab6c10 T drm_dp_dpcd_read
-ffffffff81ab6d70 T drm_dp_dpcd_write
-ffffffff81ab6ea0 T drm_dp_dpcd_read_link_status
-ffffffff81ab6ec0 T drm_dp_dpcd_read_phy_link_status
-ffffffff81ab6fd0 T drm_dp_downstream_is_type
-ffffffff81ab7020 T drm_dp_downstream_is_tmds
-ffffffff81ab7090 T drm_dp_send_real_edid_checksum
-ffffffff81ab7330 T drm_dp_read_dpcd_caps
-ffffffff81ab74f0 T drm_dp_read_downstream_info
-ffffffff81ab7600 T drm_dp_downstream_max_dotclock
-ffffffff81ab7650 T drm_dp_downstream_max_tmds_clock
-ffffffff81ab76f0 T drm_dp_downstream_min_tmds_clock
-ffffffff81ab7770 T drm_dp_downstream_max_bpc
-ffffffff81ab7810 T drm_dp_downstream_420_passthrough
-ffffffff81ab7870 T drm_dp_downstream_444_to_420_conversion
-ffffffff81ab78d0 T drm_dp_downstream_rgb_to_ycbcr_conversion
-ffffffff81ab7930 T drm_dp_downstream_mode
-ffffffff81ab79c0 T drm_dp_downstream_id
-ffffffff81ab79e0 T drm_dp_downstream_debug
-ffffffff81ab7aa0 T drm_dp_subconnector_type
-ffffffff81ab7b10 T drm_dp_set_subconnector_property
-ffffffff81ab7b80 T drm_dp_read_sink_count_cap
-ffffffff81ab7bd0 T drm_dp_read_sink_count
-ffffffff81ab7c40 T drm_dp_remote_aux_init
-ffffffff81ab7c70 t drm_dp_aux_crc_work
-ffffffff81ab7e10 T drm_dp_aux_init
-ffffffff81ab7ee0 T drm_dp_aux_register
-ffffffff81ab8030 T drm_dp_aux_unregister
-ffffffff81ab8060 T drm_dp_psr_setup_time
-ffffffff81ab80b0 T drm_dp_start_crc
-ffffffff81ab8170 T drm_dp_stop_crc
-ffffffff81ab8220 T drm_dp_read_desc
-ffffffff81ab8420 T drm_dp_dsc_sink_max_slice_count
-ffffffff81ab84b0 T drm_dp_dsc_sink_line_buf_depth
-ffffffff81ab84f0 T drm_dp_dsc_sink_supported_input_bpcs
-ffffffff81ab8560 T drm_dp_read_lttpr_common_caps
-ffffffff81ab8630 T drm_dp_read_lttpr_phy_caps
-ffffffff81ab8700 T drm_dp_lttpr_count
-ffffffff81ab87a0 T drm_dp_lttpr_max_link_rate
-ffffffff81ab8800 T drm_dp_lttpr_max_lane_count
-ffffffff81ab8830 T drm_dp_lttpr_voltage_swing_level_3_supported
-ffffffff81ab8860 T drm_dp_lttpr_pre_emphasis_level_3_supported
-ffffffff81ab8890 T drm_dp_get_phy_test_pattern
-ffffffff81ab89e0 T drm_dp_set_phy_test_pattern
-ffffffff81ab8ab0 T drm_dp_vsc_sdp_log
-ffffffff81ab8e10 T drm_dp_get_pcon_max_frl_bw
-ffffffff81ab8e60 T drm_dp_pcon_frl_prepare
-ffffffff81ab8ec0 T drm_dp_pcon_is_frl_ready
-ffffffff81ab8f20 T drm_dp_pcon_frl_configure_1
-ffffffff81ab9030 T drm_dp_pcon_frl_configure_2
-ffffffff81ab90a0 T drm_dp_pcon_reset_frl_config
-ffffffff81ab9100 T drm_dp_pcon_frl_enable
-ffffffff81ab91d0 T drm_dp_pcon_hdmi_link_active
-ffffffff81ab9230 T drm_dp_pcon_hdmi_link_mode
-ffffffff81ab92b0 T drm_dp_pcon_hdmi_frl_link_error_count
-ffffffff81ab93c0 T drm_dp_pcon_enc_is_dsc_1_2
-ffffffff81ab93f0 T drm_dp_pcon_dsc_max_slices
-ffffffff81ab9480 T drm_dp_pcon_dsc_max_slice_width
-ffffffff81ab94b0 T drm_dp_pcon_dsc_bpp_incr
-ffffffff81ab94f0 T drm_dp_pcon_pps_default
-ffffffff81ab9580 T drm_dp_pcon_pps_override_buf
-ffffffff81ab9640 T drm_dp_pcon_pps_override_param
-ffffffff81ab9750 T drm_dp_pcon_convert_rgb_to_ycbcr
-ffffffff81ab9800 T drm_edp_backlight_set_level
-ffffffff81ab98f0 T drm_edp_backlight_enable
-ffffffff81ab9b40 t drm_edp_backlight_set_enable
-ffffffff81ab9ca0 T drm_edp_backlight_disable
-ffffffff81ab9cf0 T drm_edp_backlight_init
-ffffffff81aba2b0 T drm_panel_dp_aux_backlight
-ffffffff81aba470 t __128b132b_channel_eq_delay_us
-ffffffff81aba4f0 t __8b10b_channel_eq_delay_us
-ffffffff81aba570 t drm_dp_aux_get_crc
-ffffffff81aba660 t drm_dp_i2c_xfer
-ffffffff81aba910 t drm_dp_i2c_functionality
-ffffffff81aba940 t drm_dp_i2c_do_msg
-ffffffff81abad70 t lock_bus
-ffffffff81abad90 t trylock_bus
-ffffffff81abadf0 t unlock_bus
-ffffffff81abae10 t dp_aux_backlight_update_status
+ffffffff81ab6c30 T drm_dp_dpcd_set_powered
+ffffffff81ab6ca0 T drm_dp_dpcd_read
+ffffffff81ab6e00 T drm_dp_dpcd_write
+ffffffff81ab6f30 T drm_dp_dpcd_read_link_status
+ffffffff81ab6f50 T drm_dp_dpcd_read_phy_link_status
+ffffffff81ab7060 T drm_dp_downstream_is_type
+ffffffff81ab70b0 T drm_dp_downstream_is_tmds
+ffffffff81ab7120 T drm_dp_send_real_edid_checksum
+ffffffff81ab73c0 T drm_dp_read_dpcd_caps
+ffffffff81ab7580 T drm_dp_read_downstream_info
+ffffffff81ab7690 T drm_dp_downstream_max_dotclock
+ffffffff81ab76e0 T drm_dp_downstream_max_tmds_clock
+ffffffff81ab7780 T drm_dp_downstream_min_tmds_clock
+ffffffff81ab7800 T drm_dp_downstream_max_bpc
+ffffffff81ab78a0 T drm_dp_downstream_420_passthrough
+ffffffff81ab7900 T drm_dp_downstream_444_to_420_conversion
+ffffffff81ab7960 T drm_dp_downstream_rgb_to_ycbcr_conversion
+ffffffff81ab79c0 T drm_dp_downstream_mode
+ffffffff81ab7a50 T drm_dp_downstream_id
+ffffffff81ab7a70 T drm_dp_downstream_debug
+ffffffff81ab7b30 T drm_dp_subconnector_type
+ffffffff81ab7ba0 T drm_dp_set_subconnector_property
+ffffffff81ab7c10 T drm_dp_read_sink_count_cap
+ffffffff81ab7c60 T drm_dp_read_sink_count
+ffffffff81ab7cd0 T drm_dp_remote_aux_init
+ffffffff81ab7d00 t drm_dp_aux_crc_work
+ffffffff81ab7ea0 T drm_dp_aux_init
+ffffffff81ab7f70 T drm_dp_aux_register
+ffffffff81ab80c0 T drm_dp_aux_unregister
+ffffffff81ab80f0 T drm_dp_psr_setup_time
+ffffffff81ab8140 T drm_dp_start_crc
+ffffffff81ab8200 T drm_dp_stop_crc
+ffffffff81ab82b0 T drm_dp_read_desc
+ffffffff81ab84b0 T drm_dp_dsc_sink_max_slice_count
+ffffffff81ab8540 T drm_dp_dsc_sink_line_buf_depth
+ffffffff81ab8580 T drm_dp_dsc_sink_supported_input_bpcs
+ffffffff81ab85f0 T drm_dp_read_lttpr_common_caps
+ffffffff81ab86c0 T drm_dp_read_lttpr_phy_caps
+ffffffff81ab8790 T drm_dp_lttpr_count
+ffffffff81ab8830 T drm_dp_lttpr_max_link_rate
+ffffffff81ab8890 T drm_dp_lttpr_max_lane_count
+ffffffff81ab88c0 T drm_dp_lttpr_voltage_swing_level_3_supported
+ffffffff81ab88f0 T drm_dp_lttpr_pre_emphasis_level_3_supported
+ffffffff81ab8920 T drm_dp_get_phy_test_pattern
+ffffffff81ab8a70 T drm_dp_set_phy_test_pattern
+ffffffff81ab8b40 T drm_dp_vsc_sdp_log
+ffffffff81ab8ea0 T drm_dp_get_pcon_max_frl_bw
+ffffffff81ab8ef0 T drm_dp_pcon_frl_prepare
+ffffffff81ab8f50 T drm_dp_pcon_is_frl_ready
+ffffffff81ab8fb0 T drm_dp_pcon_frl_configure_1
+ffffffff81ab90c0 T drm_dp_pcon_frl_configure_2
+ffffffff81ab9130 T drm_dp_pcon_reset_frl_config
+ffffffff81ab9190 T drm_dp_pcon_frl_enable
+ffffffff81ab9260 T drm_dp_pcon_hdmi_link_active
+ffffffff81ab92c0 T drm_dp_pcon_hdmi_link_mode
+ffffffff81ab9340 T drm_dp_pcon_hdmi_frl_link_error_count
+ffffffff81ab9450 T drm_dp_pcon_enc_is_dsc_1_2
+ffffffff81ab9480 T drm_dp_pcon_dsc_max_slices
+ffffffff81ab9510 T drm_dp_pcon_dsc_max_slice_width
+ffffffff81ab9540 T drm_dp_pcon_dsc_bpp_incr
+ffffffff81ab9580 T drm_dp_pcon_pps_default
+ffffffff81ab9610 T drm_dp_pcon_pps_override_buf
+ffffffff81ab96d0 T drm_dp_pcon_pps_override_param
+ffffffff81ab97e0 T drm_dp_pcon_convert_rgb_to_ycbcr
+ffffffff81ab9890 T drm_edp_backlight_set_level
+ffffffff81ab9980 T drm_edp_backlight_enable
+ffffffff81ab9bd0 t drm_edp_backlight_set_enable
+ffffffff81ab9d30 T drm_edp_backlight_disable
+ffffffff81ab9d80 T drm_edp_backlight_init
+ffffffff81aba340 T drm_panel_dp_aux_backlight
+ffffffff81aba500 t __128b132b_channel_eq_delay_us
+ffffffff81aba580 t __8b10b_channel_eq_delay_us
+ffffffff81aba600 t drm_dp_aux_get_crc
+ffffffff81aba700 t drm_dp_i2c_xfer
+ffffffff81aba9a0 t drm_dp_i2c_functionality
+ffffffff81aba9d0 t drm_dp_i2c_do_msg
+ffffffff81abae00 t lock_bus
+ffffffff81abae20 t trylock_bus
+ffffffff81abae80 t unlock_bus
+ffffffff81abaea0 t dp_aux_backlight_update_status
 ffffffff81abb000 T drm_dp_encode_sideband_req
 ffffffff81abb470 T drm_dp_decode_sideband_req
 ffffffff81abb9e0 T drm_dp_dump_sideband_msg_req_body
@@ -28202,14 +28203,14 @@ ffffffff81f1b350 T amdgpu_mes_flush_shader_debugger
 ffffffff81f1b470 T amdgpu_mes_ctx_get_offs
 ffffffff81f1b650 T amdgpu_mes_add_ring
 ffffffff81f1bac0 T amdgpu_mes_remove_ring
-ffffffff81f1bb30 T amdgpu_mes_get_aggregated_doorbell_index
-ffffffff81f1bb60 T amdgpu_mes_ctx_alloc_meta_data
-ffffffff81f1bc50 T amdgpu_mes_ctx_free_meta_data
-ffffffff81f1bc90 T amdgpu_mes_ctx_map_meta_data
-ffffffff81f1bf20 T amdgpu_mes_ctx_unmap_meta_data
-ffffffff81f1c1d0 T amdgpu_mes_self_test
-ffffffff81f1c8d0 t amdgpu_mes_test_queues
-ffffffff81f1cc20 T amdgpu_mes_init_microcode
+ffffffff81f1bb40 T amdgpu_mes_get_aggregated_doorbell_index
+ffffffff81f1bb70 T amdgpu_mes_ctx_alloc_meta_data
+ffffffff81f1bc60 T amdgpu_mes_ctx_free_meta_data
+ffffffff81f1bca0 T amdgpu_mes_ctx_map_meta_data
+ffffffff81f1bf30 T amdgpu_mes_ctx_unmap_meta_data
+ffffffff81f1c1e0 T amdgpu_mes_self_test
+ffffffff81f1c960 t amdgpu_mes_test_queues
+ffffffff81f1ccb0 T amdgpu_mes_init_microcode
 ffffffff81f1d000 T amdgpu_mmhub_ras_sw_init
 ffffffff81f1e000 T amdgpu_nbio_ras_sw_init
 ffffffff81f1e0f0 T amdgpu_nbio_get_pcie_replay_count
@@ -28223,41 +28224,41 @@ ffffffff81f1f2e0 T amdgpu_bo_placement_from_domain
 ffffffff81f1f560 T amdgpu_bo_create_reserved
 ffffffff81f1f940 T amdgpu_bo_unref
 ffffffff81f1f9a0 T amdgpu_bo_create
-ffffffff81f1fe50 t amdgpu_bo_reserve
-ffffffff81f20090 T amdgpu_bo_pin
-ffffffff81f200b0 T amdgpu_bo_gpu_offset
-ffffffff81f202d0 T amdgpu_bo_kmap
-ffffffff81f203a0 T amdgpu_bo_unpin
-ffffffff81f20450 t amdgpu_bo_unreserve
-ffffffff81f20560 T amdgpu_bo_create_kernel
-ffffffff81f205d0 T amdgpu_bo_create_kernel_at
-ffffffff81f20830 T amdgpu_bo_kunmap
-ffffffff81f20870 T amdgpu_bo_free_kernel
-ffffffff81f20a20 T amdgpu_bo_support_uswc
-ffffffff81f20a50 t dma_resv_unlock
-ffffffff81f20b00 T amdgpu_bo_create_user
-ffffffff81f20b70 T amdgpu_bo_create_vm
-ffffffff81f20c00 T amdgpu_bo_add_to_shadow_list
-ffffffff81f20cd0 T amdgpu_bo_ref
-ffffffff81f20d10 T amdgpu_bo_restore_shadow
-ffffffff81f20dc0 T amdgpu_bo_kptr
-ffffffff81f20df0 T amdgpu_bo_pin_restricted
-ffffffff81f21210 T amdgpu_bo_get_preferred_domain
-ffffffff81f21270 T amdgpu_bo_init
-ffffffff81f21370 T amdgpu_bo_fini
-ffffffff81f21410 T amdgpu_bo_set_tiling_flags
-ffffffff81f214a0 T amdgpu_bo_get_tiling_flags
-ffffffff81f21510 T amdgpu_bo_set_metadata
-ffffffff81f21680 T amdgpu_bo_get_metadata
-ffffffff81f21760 T amdgpu_bo_move_notify
-ffffffff81f21810 T amdgpu_bo_get_memory
-ffffffff81f21980 T amdgpu_bo_release_notify
-ffffffff81f21bc0 t dma_resv_trylock
-ffffffff81f21c70 T amdgpu_bo_fence
-ffffffff81f21cf0 T amdgpu_bo_fault_reserve_notify
-ffffffff81f21e80 T amdgpu_bo_sync_wait_resv
-ffffffff81f21f40 T amdgpu_bo_sync_wait
-ffffffff81f22010 T amdgpu_bo_gpu_offset_no_check
+ffffffff81f1fe40 t amdgpu_bo_reserve
+ffffffff81f20080 T amdgpu_bo_pin
+ffffffff81f200a0 T amdgpu_bo_gpu_offset
+ffffffff81f202c0 T amdgpu_bo_kmap
+ffffffff81f20390 T amdgpu_bo_unpin
+ffffffff81f20440 t amdgpu_bo_unreserve
+ffffffff81f20550 T amdgpu_bo_create_kernel
+ffffffff81f205c0 T amdgpu_bo_create_kernel_at
+ffffffff81f20820 T amdgpu_bo_kunmap
+ffffffff81f20860 T amdgpu_bo_free_kernel
+ffffffff81f20a10 T amdgpu_bo_support_uswc
+ffffffff81f20a40 t dma_resv_unlock
+ffffffff81f20af0 T amdgpu_bo_create_user
+ffffffff81f20b60 T amdgpu_bo_create_vm
+ffffffff81f20bf0 T amdgpu_bo_add_to_shadow_list
+ffffffff81f20cc0 T amdgpu_bo_ref
+ffffffff81f20d00 T amdgpu_bo_restore_shadow
+ffffffff81f20db0 T amdgpu_bo_kptr
+ffffffff81f20de0 T amdgpu_bo_pin_restricted
+ffffffff81f21200 T amdgpu_bo_get_preferred_domain
+ffffffff81f21260 T amdgpu_bo_init
+ffffffff81f21360 T amdgpu_bo_fini
+ffffffff81f21400 T amdgpu_bo_set_tiling_flags
+ffffffff81f21490 T amdgpu_bo_get_tiling_flags
+ffffffff81f21500 T amdgpu_bo_set_metadata
+ffffffff81f21670 T amdgpu_bo_get_metadata
+ffffffff81f21750 T amdgpu_bo_move_notify
+ffffffff81f21800 T amdgpu_bo_get_memory
+ffffffff81f21970 T amdgpu_bo_release_notify
+ffffffff81f21bb0 t dma_resv_trylock
+ffffffff81f21c60 T amdgpu_bo_fence
+ffffffff81f21ce0 T amdgpu_bo_fault_reserve_notify
+ffffffff81f21e70 T amdgpu_bo_sync_wait_resv
+ffffffff81f21f30 T amdgpu_bo_sync_wait
+ffffffff81f22000 T amdgpu_bo_gpu_offset_no_check
 ffffffff81f23000 T amdgpu_pll_compute
 ffffffff81f235a0 T amdgpu_pll_get_use_mask
 ffffffff81f23610 T amdgpu_pll_get_shared_dp_ppll
@@ -29389,96 +29390,96 @@ ffffffff81fe0290 t gfx_v9_4_3_reset_ras_error_count
 ffffffff81fe02b0 t gfx_v9_4_3_reset_ras_error_status
 ffffffff81fe02d0 t gfx_v9_4_3_enable_watchdog_timer
 ffffffff81fe02f0 t gfx_v9_4_3_early_init
-ffffffff81fe0a50 t gfx_v9_4_3_late_init
-ffffffff81fe0ae0 t gfx_v9_4_3_sw_init
-ffffffff81fe0fd0 t gfx_v9_4_3_sw_fini
-ffffffff81fe1200 t gfx_v9_4_3_hw_init
-ffffffff81fe1de0 t gfx_v9_4_3_hw_fini
-ffffffff81fe1ec0 t gfx_v9_4_3_suspend
-ffffffff81fe1fa0 t gfx_v9_4_3_resume
-ffffffff81fe1fb0 t gfx_v9_4_3_is_idle
-ffffffff81fe21a0 t gfx_v9_4_3_wait_for_idle
-ffffffff81fe2240 t gfx_v9_4_3_soft_reset
-ffffffff81fe2a80 t gfx_v9_4_3_set_clockgating_state
-ffffffff81fe2c40 t gfx_v9_4_3_set_powergating_state
-ffffffff81fe2c70 t gfx_v9_4_3_get_clockgating_state
-ffffffff81fe2e20 t gfx_v9_4_3_kiq_set_resources
-ffffffff81fe3180 t gfx_v9_4_3_kiq_map_queues
-ffffffff81fe3520 t gfx_v9_4_3_kiq_unmap_queues
-ffffffff81fe38e0 t gfx_v9_4_3_kiq_query_status
-ffffffff81fe3c00 t gfx_v9_4_3_kiq_invalidate_tlbs
-ffffffff81fe3d30 t gfx_v9_4_3_ring_get_rptr_compute
-ffffffff81fe3d70 t gfx_v9_4_3_ring_get_wptr_compute
-ffffffff81fe3de0 t gfx_v9_4_3_ring_set_wptr_compute
-ffffffff81fe3e40 t gfx_v9_4_3_ring_emit_fence_kiq
-ffffffff81fe42e0 t gfx_v9_4_3_ring_test_ring
-ffffffff81fe4580 t gfx_v9_4_3_ring_emit_rreg
-ffffffff81fe4840 t gfx_v9_4_3_ring_emit_wreg
-ffffffff81fe4aa0 t gfx_v9_4_3_ring_emit_reg_wait
-ffffffff81fe4b00 t gfx_v9_4_3_ring_emit_reg_write_reg_wait
-ffffffff81fe4b20 t gfx_v9_4_3_wait_reg_mem
-ffffffff81fe4e80 t gfx_v9_4_3_ring_emit_ib_compute
-ffffffff81fe51e0 t gfx_v9_4_3_ring_emit_fence
-ffffffff81fe55d0 t gfx_v9_4_3_ring_emit_pipeline_sync
-ffffffff81fe5640 t gfx_v9_4_3_ring_emit_vm_flush
-ffffffff81fe5660 t gfx_v9_4_3_ring_emit_hdp_flush
-ffffffff81fe5750 t gfx_v9_4_3_ring_emit_gds_switch
-ffffffff81fe5930 t gfx_v9_4_3_ring_test_ib
-ffffffff81fe5b20 t gfx_v9_4_3_emit_mem_sync
-ffffffff81fe5e10 t gfx_v9_4_3_emit_wave_limit
-ffffffff81fe6020 t gfx_v9_4_3_write_data_to_reg
-ffffffff81fe6250 t gfx_v9_4_3_set_eop_interrupt_state
-ffffffff81fe63d0 t gfx_v9_4_3_eop_irq
-ffffffff81fe6580 t gfx_v9_4_3_xcc_set_compute_eop_interrupt_state
-ffffffff81fe6700 t gfx_v9_4_3_ih_to_xcc_inst
-ffffffff81fe67e0 t gfx_v9_4_3_set_priv_reg_fault_state
-ffffffff81fe6c40 t gfx_v9_4_3_priv_reg_irq
-ffffffff81fe6cb0 t gfx_v9_4_3_fault
-ffffffff81fe6e30 t gfx_v9_4_3_set_priv_inst_fault_state
-ffffffff81fe7290 t gfx_v9_4_3_priv_inst_irq
-ffffffff81fe7300 t gfx_v9_4_3_is_rlc_enabled
-ffffffff81fe7450 t gfx_v9_4_3_xcc_set_safe_mode
-ffffffff81fe7760 t gfx_v9_4_3_xcc_unset_safe_mode
-ffffffff81fe78a0 t gfx_v9_4_3_rlc_init
-ffffffff81fe7900 t gfx_v9_4_3_rlc_resume
-ffffffff81fe79c0 t gfx_v9_4_3_rlc_stop
-ffffffff81fe7a70 t gfx_v9_4_3_rlc_reset
-ffffffff81fe81f0 t gfx_v9_4_3_rlc_start
-ffffffff81fe82a0 t gfx_v9_4_3_update_spm_vmid
-ffffffff81fe8500 t gfx_v9_4_3_is_rlcg_access_range
-ffffffff81fe85d0 t gfx_v9_4_3_xcc_rlc_resume
-ffffffff81fe8f90 t gfx_v9_4_3_xcc_rlc_stop
-ffffffff81fe97f0 t gfx_v9_4_3_xcc_rlc_start
-ffffffff81fe9c00 t gfx_v9_4_3_xcc_enable_gui_idle_interrupt
-ffffffff81fe9e60 t gfx_v9_4_3_xcc_select_se_sh
-ffffffff81fea090 t gfx_v9_4_3_mec_init
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-ffffffff81ff5080 t gfx_v9_4_3_inst_reset_ras_err_status
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+ffffffff81fe3530 t gfx_v9_4_3_kiq_unmap_queues
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+ffffffff81fe3df0 t gfx_v9_4_3_ring_set_wptr_compute
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+ffffffff81fe4850 t gfx_v9_4_3_ring_emit_wreg
+ffffffff81fe4ab0 t gfx_v9_4_3_ring_emit_reg_wait
+ffffffff81fe4b10 t gfx_v9_4_3_ring_emit_reg_write_reg_wait
+ffffffff81fe4b30 t gfx_v9_4_3_wait_reg_mem
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+ffffffff81fe5650 t gfx_v9_4_3_ring_emit_vm_flush
+ffffffff81fe5670 t gfx_v9_4_3_ring_emit_hdp_flush
+ffffffff81fe5760 t gfx_v9_4_3_ring_emit_gds_switch
+ffffffff81fe5940 t gfx_v9_4_3_ring_test_ib
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+ffffffff81fe5e20 t gfx_v9_4_3_emit_wave_limit
+ffffffff81fe6030 t gfx_v9_4_3_write_data_to_reg
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+ffffffff81fe63e0 t gfx_v9_4_3_eop_irq
+ffffffff81fe6590 t gfx_v9_4_3_xcc_set_compute_eop_interrupt_state
+ffffffff81fe6710 t gfx_v9_4_3_ih_to_xcc_inst
+ffffffff81fe67f0 t gfx_v9_4_3_set_priv_reg_fault_state
+ffffffff81fe6c50 t gfx_v9_4_3_priv_reg_irq
+ffffffff81fe6cc0 t gfx_v9_4_3_fault
+ffffffff81fe6e40 t gfx_v9_4_3_set_priv_inst_fault_state
+ffffffff81fe72a0 t gfx_v9_4_3_priv_inst_irq
+ffffffff81fe7310 t gfx_v9_4_3_is_rlc_enabled
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+ffffffff81fe7770 t gfx_v9_4_3_xcc_unset_safe_mode
+ffffffff81fe78b0 t gfx_v9_4_3_rlc_init
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+ffffffff81fe8200 t gfx_v9_4_3_rlc_start
+ffffffff81fe82b0 t gfx_v9_4_3_update_spm_vmid
+ffffffff81fe8510 t gfx_v9_4_3_is_rlcg_access_range
+ffffffff81fe85e0 t gfx_v9_4_3_xcc_rlc_resume
+ffffffff81fe8fa0 t gfx_v9_4_3_xcc_rlc_stop
+ffffffff81fe9800 t gfx_v9_4_3_xcc_rlc_start
+ffffffff81fe9c10 t gfx_v9_4_3_xcc_enable_gui_idle_interrupt
+ffffffff81fe9e70 t gfx_v9_4_3_xcc_select_se_sh
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+ffffffff81fea410 t gfx_v9_4_3_gpu_early_init
+ffffffff81fea660 t amdgpu_bo_unreserve
+ffffffff81fea770 t gfx_v9_4_3_get_gpu_clock_counter
+ffffffff81feab40 t gfx_v9_4_3_read_wave_data
+ffffffff81feaea0 t gfx_v9_4_3_read_wave_vgprs
+ffffffff81feaec0 t gfx_v9_4_3_read_wave_sgprs
+ffffffff81feaf20 t gfx_v9_4_3_select_me_pipe_q
+ffffffff81feafa0 t gfx_v9_4_3_switch_compute_partition
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+ffffffff81fecbe0 t gfx_v9_4_3_xcc_cp_resume
+ffffffff81fede80 t gfx_v9_4_3_xcc_cp_compute_enable
+ffffffff81fee060 t amdgpu_bo_reserve
+ffffffff81fee200 t gfx_v9_4_3_xcc_kiq_init_register
+ffffffff81ff02a0 t gfx_v9_4_3_xcc_mqd_init
+ffffffff81ff0e40 t gfx_v9_4_3_xcc_fini
+ffffffff81ff14c0 t gfx_v9_4_3_xcc_q_fini_register
+ffffffff81ff2020 t gfx_v9_4_3_xcc_update_sram_fgcg
+ffffffff81ff22d0 t gfx_v9_4_3_xcc_update_repeater_fgcg
+ffffffff81ff2580 t gfx_v9_4_3_xcc_update_medium_grain_clock_gating
+ffffffff81ff3270 t gfx_v9_4_3_xcc_update_coarse_grain_clock_gating
+ffffffff81ff3c00 t gfx_v9_4_3_inst_query_ras_err_count
+ffffffff81ff3eb0 t gfx_v9_4_3_inst_query_ras_err_status
+ffffffff81ff4ea0 t gfx_v9_4_3_inst_reset_ras_err_count
+ffffffff81ff5090 t gfx_v9_4_3_inst_reset_ras_err_status
+ffffffff81ff5930 t gfx_v9_4_3_inst_enable_watchdog_timer
 ffffffff81ff6000 t gfxhub_v1_0_get_mc_fb_offset
 ffffffff81ff60a0 t gfxhub_v1_0_setup_vm_pt_regs
 ffffffff81ff61f0 t gfxhub_v1_0_gart_enable
@@ -31538,17 +31539,17 @@ ffffffff8215d2c0 T pre_validate_dsc
 ffffffff8215d8e0 T dm_dp_mst_is_port_support_mode
 ffffffff8215db80 t amdgpu_dm_encoder_destroy
 ffffffff8215db90 t dm_dp_add_mst_connector
-ffffffff8215dda0 t dm_handle_mst_down_rep_msg_ready
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-ffffffff8215de10 t amdgpu_dm_mst_connector_early_unregister
-ffffffff8215df00 t dm_dp_mst_connector_destroy
-ffffffff8215dfa0 t dm_dp_mst_get_modes
-ffffffff8215e550 t dm_dp_mst_detect
-ffffffff8215e760 t dm_mst_atomic_best_encoder
-ffffffff8215e7c0 t dm_dp_mst_atomic_check
-ffffffff8215e7f0 t set_dsc_configs_from_fairness_vars
-ffffffff8215eae0 t increase_dsc_bpp
-ffffffff8215f080 t try_disable_dsc
+ffffffff8215ddc0 t dm_handle_mst_down_rep_msg_ready
+ffffffff8215dde0 t amdgpu_dm_mst_connector_late_register
+ffffffff8215de30 t amdgpu_dm_mst_connector_early_unregister
+ffffffff8215df20 t dm_dp_mst_connector_destroy
+ffffffff8215dfc0 t dm_dp_mst_get_modes
+ffffffff8215e570 t dm_dp_mst_detect
+ffffffff8215e780 t dm_mst_atomic_best_encoder
+ffffffff8215e7e0 t dm_dp_mst_atomic_check
+ffffffff8215e810 t set_dsc_configs_from_fairness_vars
+ffffffff8215eb00 t increase_dsc_bpp
+ffffffff8215f0a0 t try_disable_dsc
 ffffffff82160000 T amdgpu_dm_plane_get_format_info
 ffffffff82160020 T amdgpu_dm_plane_fill_blending_from_plane_state
 ffffffff82160120 T amdgpu_dm_plane_fill_plane_buffer_attributes
@@ -32003,9 +32004,9 @@ ffffffff8219f780 T dcn314_smu_set_dtbclk
 ffffffff821a0000 T dcn315_clk_mgr_construct
 ffffffff821a0890 T dcn315_clk_mgr_destroy
 ffffffff821a08e0 t dcn315_update_clocks
-ffffffff821a0e70 t dcn315_enable_pme_wa
-ffffffff821a0e80 t dcn315_notify_wm_ranges
-ffffffff821a1220 t dcn315_disable_otg_wa
+ffffffff821a0ef0 t dcn315_enable_pme_wa
+ffffffff821a0f00 t dcn315_notify_wm_ranges
+ffffffff821a12a0 t dcn315_disable_otg_wa
 ffffffff821a2000 T dcn315_smu_get_smu_version
 ffffffff821a2020 t dcn315_smu_send_msg_with_param
 ffffffff821a23d0 T dcn315_smu_set_dispclk
@@ -32050,17 +32051,17 @@ ffffffff821a6760 T dcn32_clk_mgr_construct
 ffffffff821a6a40 t dcn32_dump_clk_registers
 ffffffff821a6ce0 T dcn32_clk_mgr_destroy
 ffffffff821a6d50 t dcn32_update_clocks
-ffffffff821a7610 t dcn32_enable_pme_wa
-ffffffff821a7650 t dcn32_are_clock_states_equal
-ffffffff821a76c0 t dcn32_notify_wm_ranges
-ffffffff821a7850 t dcn32_set_hard_min_memclk
-ffffffff821a78e0 t dcn32_set_hard_max_memclk
-ffffffff821a7930 t dcn32_set_max_memclk
-ffffffff821a7970 t dcn32_set_min_memclk
-ffffffff821a79b0 t dcn32_get_memclk_states_from_smu
-ffffffff821a7c40 t dcn32_is_smu_present
-ffffffff821a7c70 t dcn32_get_dispclk_from_dentist
-ffffffff821a7d10 t dcn32_update_clocks_update_dentist
+ffffffff821a76b0 t dcn32_enable_pme_wa
+ffffffff821a76f0 t dcn32_are_clock_states_equal
+ffffffff821a7760 t dcn32_notify_wm_ranges
+ffffffff821a78f0 t dcn32_set_hard_min_memclk
+ffffffff821a7980 t dcn32_set_hard_max_memclk
+ffffffff821a79d0 t dcn32_set_max_memclk
+ffffffff821a7a10 t dcn32_set_min_memclk
+ffffffff821a7a50 t dcn32_get_memclk_states_from_smu
+ffffffff821a7ce0 t dcn32_is_smu_present
+ffffffff821a7d10 t dcn32_get_dispclk_from_dentist
+ffffffff821a7db0 t dcn32_update_clocks_update_dentist
 ffffffff821a9000 T dcn32_smu_send_fclk_pstate_message
 ffffffff821a9020 t dcn32_smu_send_msg_with_param
 ffffffff821a91a0 T dcn32_smu_send_cab_for_uclk_message
@@ -32086,67 +32087,67 @@ ffffffff821abd90 T dc_init_callbacks
 ffffffff821abde0 T dc_deinit_callbacks
 ffffffff821abe30 T dc_destroy
 ffffffff821abea0 T dc_validate_boot_timing
-ffffffff821ac2a0 T dc_enable_stereo
-ffffffff821ac3b0 T dc_trigger_sync
-ffffffff821aca10 T dc_z10_restore
-ffffffff821aca50 T dc_z10_save_init
-ffffffff821aca90 T dc_commit_streams
-ffffffff821acfe0 t commit_minimal_transition_state
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-ffffffff821ad500 t dc_commit_state_no_check
-ffffffff821aee30 T dc_release_state
-ffffffff821aeea0 T dc_acquire_release_mpc_3dlut
-ffffffff821aef70 T dc_post_update_surfaces_to_stream
-ffffffff821af3f0 T dc_copy_state
-ffffffff821af5e0 T dc_retain_state
-ffffffff821af610 T dc_set_generic_gpio_for_stereo
-ffffffff821af770 T dc_check_update_surfaces_for_stream
-ffffffff821b0180 T dc_dmub_update_dirty_rect
-ffffffff821b0390 T dc_update_planes_and_stream
-ffffffff821b1030 t fast_update_only
-ffffffff821b1390 t commit_planes_for_stream_fast
-ffffffff821b17e0 t commit_planes_for_stream
-ffffffff821b2f40 T dc_commit_updates_for_stream
-ffffffff821b3620 t copy_surface_update_to_plane
-ffffffff821b3a40 t copy_stream_update_to_stream
-ffffffff821b4140 T dc_get_current_stream_count
-ffffffff821b4180 T dc_get_stream_at_index
-ffffffff821b41d0 T dc_interrupt_to_irq_source
-ffffffff821b41f0 T dc_interrupt_set
-ffffffff821b4240 T dc_interrupt_ack
-ffffffff821b4260 T dc_power_down_on_boot
-ffffffff821b42b0 T dc_set_power_state
-ffffffff821b44e0 T dc_resume
-ffffffff821b4560 T dc_is_dmcu_initialized
-ffffffff821b45b0 T get_clock_requirements_for_state
-ffffffff821b4630 T dc_set_clock
-ffffffff821b4670 T dc_get_clock
-ffffffff821b46b0 T dc_set_psr_allow_active
-ffffffff821b47c0 T dc_allow_idle_optimizations
-ffffffff821b4870 T dc_unlock_memory_clock_frequency
-ffffffff821b48f0 T dc_lock_memory_clock_frequency
-ffffffff821b4990 T dc_enable_dcmode_clk_limit
-ffffffff821b4b60 t blank_and_force_memclk
-ffffffff821b4d90 T dc_is_plane_eligible_for_idle_optimizations
-ffffffff821b4df0 T dc_hardware_release
-ffffffff821b4e40 T dc_mclk_switch_using_fw_based_vblank_stretch_shut_down
-ffffffff821b4e80 T dc_is_dmub_outbox_supported
-ffffffff821b4ef0 T dc_enable_dmub_notifications
-ffffffff821b4f60 T dc_enable_dmub_outbox
-ffffffff821b4fb0 T dc_process_dmub_aux_transfer_async
-ffffffff821b5140 T get_link_index_from_dpia_port_index
-ffffffff821b5200 T dc_process_dmub_set_config_async
-ffffffff821b52e0 T dc_process_dmub_set_mst_slots
-ffffffff821b53d0 T dc_process_dmub_dpia_hpd_int_enable
-ffffffff821b54a0 T dc_print_dmub_diagnostic_data
-ffffffff821b54c0 T dc_disable_accelerated_mode
-ffffffff821b54e0 T dc_notify_vsync_int_state
-ffffffff821b5710 T dc_abm_save_restore
-ffffffff821b5900 T dc_query_current_properties
-ffffffff821b5970 T dc_set_edp_power
-ffffffff821b59e0 t create_links
-ffffffff821b5e90 t create_link_encoders
-ffffffff821b5f80 t dc_update_viusal_confirm_color
+ffffffff821ac2b0 T dc_enable_stereo
+ffffffff821ac3c0 T dc_trigger_sync
+ffffffff821aca20 T dc_z10_restore
+ffffffff821aca60 T dc_z10_save_init
+ffffffff821acaa0 T dc_commit_streams
+ffffffff821acff0 t commit_minimal_transition_state
+ffffffff821ad470 T dc_create_state
+ffffffff821ad510 t dc_commit_state_no_check
+ffffffff821aee40 T dc_release_state
+ffffffff821aeeb0 T dc_acquire_release_mpc_3dlut
+ffffffff821aef80 T dc_post_update_surfaces_to_stream
+ffffffff821af400 T dc_copy_state
+ffffffff821af5f0 T dc_retain_state
+ffffffff821af620 T dc_set_generic_gpio_for_stereo
+ffffffff821af780 T dc_check_update_surfaces_for_stream
+ffffffff821b0190 T dc_dmub_update_dirty_rect
+ffffffff821b03a0 T dc_update_planes_and_stream
+ffffffff821b1040 t fast_update_only
+ffffffff821b13a0 t commit_planes_for_stream_fast
+ffffffff821b17f0 t commit_planes_for_stream
+ffffffff821b2f50 T dc_commit_updates_for_stream
+ffffffff821b3630 t copy_surface_update_to_plane
+ffffffff821b3a50 t copy_stream_update_to_stream
+ffffffff821b4150 T dc_get_current_stream_count
+ffffffff821b4190 T dc_get_stream_at_index
+ffffffff821b41e0 T dc_interrupt_to_irq_source
+ffffffff821b4200 T dc_interrupt_set
+ffffffff821b4250 T dc_interrupt_ack
+ffffffff821b4270 T dc_power_down_on_boot
+ffffffff821b42c0 T dc_set_power_state
+ffffffff821b44f0 T dc_resume
+ffffffff821b4570 T dc_is_dmcu_initialized
+ffffffff821b45c0 T get_clock_requirements_for_state
+ffffffff821b4640 T dc_set_clock
+ffffffff821b4680 T dc_get_clock
+ffffffff821b46c0 T dc_set_psr_allow_active
+ffffffff821b47d0 T dc_allow_idle_optimizations
+ffffffff821b4880 T dc_unlock_memory_clock_frequency
+ffffffff821b4900 T dc_lock_memory_clock_frequency
+ffffffff821b49a0 T dc_enable_dcmode_clk_limit
+ffffffff821b4b70 t blank_and_force_memclk
+ffffffff821b4da0 T dc_is_plane_eligible_for_idle_optimizations
+ffffffff821b4e00 T dc_hardware_release
+ffffffff821b4e50 T dc_mclk_switch_using_fw_based_vblank_stretch_shut_down
+ffffffff821b4e90 T dc_is_dmub_outbox_supported
+ffffffff821b4f00 T dc_enable_dmub_notifications
+ffffffff821b4f70 T dc_enable_dmub_outbox
+ffffffff821b4fc0 T dc_process_dmub_aux_transfer_async
+ffffffff821b5150 T get_link_index_from_dpia_port_index
+ffffffff821b5210 T dc_process_dmub_set_config_async
+ffffffff821b52f0 T dc_process_dmub_set_mst_slots
+ffffffff821b53e0 T dc_process_dmub_dpia_hpd_int_enable
+ffffffff821b54b0 T dc_print_dmub_diagnostic_data
+ffffffff821b54d0 T dc_disable_accelerated_mode
+ffffffff821b54f0 T dc_notify_vsync_int_state
+ffffffff821b5720 T dc_abm_save_restore
+ffffffff821b5910 T dc_query_current_properties
+ffffffff821b5980 T dc_set_edp_power
+ffffffff821b59f0 t create_links
+ffffffff821b5ea0 t create_link_encoders
+ffffffff821b5f90 t dc_update_viusal_confirm_color
 ffffffff821b7000 T pre_surface_trace
 ffffffff821b7030 T update_surface_trace
 ffffffff821b7060 T post_surface_trace
@@ -34988,12 +34989,12 @@ ffffffff82496150 t intersect_frl_link_bw_support
 ffffffff82497000 T dpcd_get_tunneling_device_data
 ffffffff824970f0 T dpia_query_hpd_status
 ffffffff82498000 T link_dp_dpia_set_dptx_usb4_bw_alloc_support
-ffffffff82498340 T dpia_handle_bw_alloc_response
-ffffffff82498630 T dpia_handle_usb4_bandwidth_allocation_for_link
-ffffffff82498970 T link_dp_dpia_allocate_usb4_bandwidth_for_stream
-ffffffff82498c60 T dpia_validate_usb4_bw
-ffffffff82499060 t get_lowest_dpia_index
-ffffffff82499230 T link_dp_dpia_get_dp_overhead_in_dp_tunneling
+ffffffff82498350 T link_dp_dpia_allocate_usb4_bandwidth_for_stream
+ffffffff82498640 T dpia_handle_bw_alloc_response
+ffffffff82498930 T dpia_handle_usb4_bandwidth_allocation_for_link
+ffffffff82498c70 T dpia_validate_usb4_bw
+ffffffff82499070 t get_lowest_dpia_index
+ffffffff82499240 T link_dp_dpia_get_dp_overhead_in_dp_tunneling
 ffffffff8249a000 T dp_parse_link_loss_status
 ffffffff8249a160 T dp_handle_link_loss
 ffffffff8249a2a0 T dp_read_hpd_rx_irq_data
@@ -36964,17 +36965,17 @@ ffffffff8259bfc0 t smu_v13_0_6_is_mode1_reset_supporte
 ffffffff8259bff0 t smu_v13_0_6_is_mode2_reset_supported
 ffffffff8259c020 t smu_v13_0_6_mode1_reset
 ffffffff8259c0e0 t smu_v13_0_6_mode2_reset
-ffffffff8259c480 t smu_v13_0_6_get_dpm_ultimate_freq
-ffffffff8259c6c0 t smu_v13_0_6_set_soft_freq_limited_range
-ffffffff8259c940 t smu_v13_0_6_log_thermal_throttling_event
-ffffffff8259cc80 t smu_v13_0_6_get_gpu_metrics
-ffffffff8259d030 t smu_v13_0_6_smu_send_hbm_bad_page_num
-ffffffff8259d0c0 t smu_v13_0_6_get_smu_metrics_data
-ffffffff8259d380 t smu_v13_0_6_upload_dpm_level
-ffffffff8259d4b0 t smu_v13_0_6_i2c_xfer
-ffffffff8259d7e0 t smu_v13_0_6_i2c_func
-ffffffff8259d810 t smu_v13_0_6_set_irq_state
-ffffffff8259daf0 t smu_v13_0_6_irq_process
+ffffffff8259c4a0 t smu_v13_0_6_get_dpm_ultimate_freq
+ffffffff8259c6e0 t smu_v13_0_6_set_soft_freq_limited_range
+ffffffff8259c960 t smu_v13_0_6_log_thermal_throttling_event
+ffffffff8259cca0 t smu_v13_0_6_get_gpu_metrics
+ffffffff8259d050 t smu_v13_0_6_smu_send_hbm_bad_page_num
+ffffffff8259d0e0 t smu_v13_0_6_get_smu_metrics_data
+ffffffff8259d3a0 t smu_v13_0_6_upload_dpm_level
+ffffffff8259d4d0 t smu_v13_0_6_i2c_xfer
+ffffffff8259d800 t smu_v13_0_6_i2c_func
+ffffffff8259d830 t smu_v13_0_6_set_irq_state
+ffffffff8259db10 t smu_v13_0_6_irq_process
 ffffffff8259e000 T smu_v13_0_7_set_ppt_funcs
 ffffffff8259e060 t smu_v13_0_7_get_allowed_feature_mask
 ffffffff8259e1e0 t smu_v13_0_7_set_default_dpm_table
@@ -42172,16 +42173,16 @@ ffffffff82822230 r replacements
 ffffffff82825b41 r apollo_pio_rec
 ffffffff82873a8a r apollo_udma33_tim
 ffffffff82889213 r pp_r600_decoded_lanes
-ffffffff828c0271 r cmd680_setup_channel.udma_tbl
-ffffffff828c87f8 r apollo_udma100_tim
-ffffffff828c87fe r cmd0646_9_tim_udma
-ffffffff828d7167 r substchar
-ffffffff8292e843 r apollo_udma133_tim
-ffffffff8292e84a r apollo_udma66_tim
-ffffffff8292e874 r cy_pio_rec
-ffffffff82934100 R drm_ca
-ffffffff82934128 R drm_filtops
-ffffffff82934158 R drmread_filtops
+ffffffff828c0287 r cmd680_setup_channel.udma_tbl
+ffffffff828c880e r apollo_udma100_tim
+ffffffff828c8814 r cmd0646_9_tim_udma
+ffffffff828d717d r substchar
+ffffffff8292e859 r apollo_udma133_tim
+ffffffff8292e860 r apollo_udma66_tim
+ffffffff8292e88a r cy_pio_rec
+ffffffff82934118 R drm_ca
+ffffffff82934140 R drm_filtops
+ffffffff82934170 R drmread_filtops
 ffffffff82935000 r vga_emulops
 ffffffff82935048 R vga_stdscreen
 ffffffff82935078 R vga_stdscreen_mono
@@ -56767,6 +56768,7 @@ ffffffff838bc000 B x86_soft_intrs
 ffffffff838bd000 B i8259_imen
 ffffffff838be000 B prev_cache
 ffffffff838bf000 B intr_shared_edge
+ffffffff838bf004 B intr_suspended
 ffffffff838bf008 B fake_softclock_intrhand
 ffffffff838bf078 B fake_softnet_intrhand
 ffffffff838bf0e8 B fake_softtty_intrhand