--- 7.5/2024-07-01T06:17:03Z/2024-06-11T00:00:00Z/nm-bsd-ot14.txt	Tue Jul  2 17:42:28 2024
+++ 7.5/2024-07-01T06:17:03Z/2024-06-12T00:00:00Z/nm-bsd-ot14.txt	Tue Jul  2 20:21:22 2024
@@ -17772,90 +17772,90 @@ ffffffff81940b10 T qwx_mhi_submit_xfer
 ffffffff81940db0 T qwx_pcic_ext_irq_enable
 ffffffff81940de0 T qwx_pcic_ext_irq_disable
 ffffffff81940e10 T qwx_pci_intr
-ffffffff81941160 T qwx_pci_intr_mhi_ctrl
-ffffffff819411b0 T qwx_pci_intr_mhi_data
-ffffffff81941200 T qwx_pci_read_hw_version
-ffffffff81941280 T qwx_pci_alloc_event_rings
-ffffffff81941500 T qwx_pci_init_cmd_ring
-ffffffff81941590 T qwx_mhi_register
-ffffffff819415c0 T qwx_pcic_config_irq
-ffffffff81941870 T qwx_pci_attach_hook
-ffffffff819418c0 T qwx_pci_free_cmd_ring
-ffffffff81941940 T qwx_pci_free_event_rings
-ffffffff81941a40 T qwx_pci_free_xfer_rings
-ffffffff81941b30 T qwx_pci_alloc_xfer_ring
-ffffffff81941e80 T qwx_pci_alloc_xfer_rings_qca6390
-ffffffff81941fb0 T qwx_pci_alloc_xfer_rings_qcn9074
-ffffffff819420e0 T qwx_pci_alloc_event_ring
-ffffffff819421d0 T qwx_pci_read
-ffffffff81942200 T qwx_pci_write
-ffffffff81942230 T qwx_pcic_ce_irq_enable
-ffffffff81942270 T qwx_pcic_ce_irq_disable
-ffffffff819422b0 T qwx_pcic_ext_grp_disable
-ffffffff819422e0 T qwx_pcic_ext_irq_config
-ffffffff81942540 T qwx_pcic_ce_irqs_enable
-ffffffff819425e0 T qwx_pcic_ce_irqs_disable
-ffffffff81942680 T qwx_pci_aspm_restore
-ffffffff81942700 T qwx_pcic_ce_irq_disable_sync
-ffffffff819427a0 T qwx_pci_bus_wake_up
-ffffffff81942840 T qwx_mhi_wake_db_clear_valid
-ffffffff81942880 T qwx_mhi_device_wake
-ffffffff819428f0 T qwx_pci_bus_release
-ffffffff81942990 T qwx_mhi_device_zzz
-ffffffff819429f0 T qwx_pci_get_window_start
-ffffffff81942a60 T qwx_pci_select_window
-ffffffff81942b10 T qwx_pci_window_write32
-ffffffff81942c20 T qwx_pci_window_read32
-ffffffff81942d20 T qwx_pci_select_static_window
-ffffffff81942d50 T qwx_pci_soc_global_reset
-ffffffff81943080 T qwx_pci_clear_dbg_registers
-ffffffff81943420 T qwx_pci_set_link_reg
-ffffffff81943700 T qwx_pci_fix_l1ss
-ffffffff819437f0 T qwx_pci_enable_ltssm
-ffffffff81943c40 T qwx_pci_clear_all_intrs
-ffffffff81943d40 T qwx_pci_set_wlaon_pwr_ctrl
-ffffffff81943f00 T qwx_pci_force_wake
-ffffffff81943ff0 T qwx_pci_sw_reset
-ffffffff819441e0 T qwx_mhi_clear_vector
-ffffffff81944290 T qwx_mhi_reset_device
-ffffffff81944420 T qwx_pci_msi_config
-ffffffff81944490 T qwx_pci_msi_enable
-ffffffff819444f0 T qwx_pci_msi_disable
-ffffffff81944550 T qwx_pci_aspm_disable
-ffffffff819445f0 T qwx_mhi_start
-ffffffff81944990 T qwx_mhi_stop
-ffffffff819449b0 T qwx_mhi_unregister
-ffffffff819449e0 T qwx_mhi_ring_doorbell
-ffffffff81944a50 T qwx_mhi_init_xfer_rings
-ffffffff81944bc0 T qwx_mhi_init_event_rings
-ffffffff81944d10 T qwx_mhi_init_cmd_ring
-ffffffff81944d90 T qwx_mhi_init_dev_ctxt
-ffffffff81944f60 T qwx_pci_cmd_ring_get_elem
-ffffffff81944fc0 T qwx_mhi_cmd_ring_submit
-ffffffff81945110 T qwx_mhi_send_cmd
-ffffffff819451f0 T qwx_pci_xfer_ring_get_elem
-ffffffff81945240 T qwx_pci_xfer_ring_get_data
-ffffffff81945290 T qwx_mhi_start_channel
-ffffffff819455a0 T qwx_mhi_start_channels
-ffffffff819456d0 T qwx_rddm_prepare
-ffffffff819459a0 T qwx_mhi_fw_load_handler
-ffffffff81945c10 T qwx_mhi_await_device_reset
-ffffffff81945ce0 T qwx_mhi_fw_load_bhi
-ffffffff81945f80 T qwx_mhi_fw_load_bhie
-ffffffff81946350 T qwx_mhi_await_device_ready
-ffffffff819464f0 T qwx_mhi_ready_state_transition
-ffffffff819466f0 T qwx_mhi_init_mmio
-ffffffff81946a70 T qwx_mhi_set_state
-ffffffff81946af0 T qwx_mhi_mission_mode_state_transition
-ffffffff81946c70 T qwx_mhi_low_power_mode_state_transition
-ffffffff81946ce0 T qwx_pci_event_ring_get_elem
-ffffffff81946d30 T qwx_mhi_state_change
-ffffffff819470e0 T qwx_pci_intr_ctrl_event_mhi
-ffffffff81947120 T qwx_pci_intr_ctrl_event_ee
-ffffffff81947160 T qwx_pci_intr_ctrl_event_cmd_complete
-ffffffff819472b0 T qwx_pci_intr_ctrl_event
-ffffffff81947560 T qwx_pci_intr_data_event_tx
-ffffffff81947920 T qwx_pci_intr_data_event
+ffffffff81941170 T qwx_pci_intr_mhi_ctrl
+ffffffff819411c0 T qwx_pci_intr_mhi_data
+ffffffff81941210 T qwx_pci_read_hw_version
+ffffffff81941290 T qwx_pci_alloc_event_rings
+ffffffff81941510 T qwx_pci_init_cmd_ring
+ffffffff819415a0 T qwx_mhi_register
+ffffffff819415d0 T qwx_pcic_config_irq
+ffffffff81941880 T qwx_pci_attach_hook
+ffffffff819418d0 T qwx_pci_free_cmd_ring
+ffffffff81941950 T qwx_pci_free_event_rings
+ffffffff81941a50 T qwx_pci_free_xfer_rings
+ffffffff81941b40 T qwx_pci_alloc_xfer_ring
+ffffffff81941e90 T qwx_pci_alloc_xfer_rings_qca6390
+ffffffff81941fc0 T qwx_pci_alloc_xfer_rings_qcn9074
+ffffffff819420f0 T qwx_pci_alloc_event_ring
+ffffffff819421e0 T qwx_pci_read
+ffffffff81942210 T qwx_pci_write
+ffffffff81942240 T qwx_pcic_ce_irq_enable
+ffffffff81942280 T qwx_pcic_ce_irq_disable
+ffffffff819422c0 T qwx_pcic_ext_grp_disable
+ffffffff819422f0 T qwx_pcic_ext_irq_config
+ffffffff81942550 T qwx_pcic_ce_irqs_enable
+ffffffff819425f0 T qwx_pcic_ce_irqs_disable
+ffffffff81942690 T qwx_pci_aspm_restore
+ffffffff81942710 T qwx_pcic_ce_irq_disable_sync
+ffffffff819427b0 T qwx_pci_bus_wake_up
+ffffffff81942850 T qwx_mhi_wake_db_clear_valid
+ffffffff81942890 T qwx_mhi_device_wake
+ffffffff81942900 T qwx_pci_bus_release
+ffffffff819429a0 T qwx_mhi_device_zzz
+ffffffff81942a00 T qwx_pci_get_window_start
+ffffffff81942a70 T qwx_pci_select_window
+ffffffff81942b20 T qwx_pci_window_write32
+ffffffff81942c30 T qwx_pci_window_read32
+ffffffff81942d30 T qwx_pci_select_static_window
+ffffffff81942d60 T qwx_pci_soc_global_reset
+ffffffff81943090 T qwx_pci_clear_dbg_registers
+ffffffff81943430 T qwx_pci_set_link_reg
+ffffffff81943710 T qwx_pci_fix_l1ss
+ffffffff81943800 T qwx_pci_enable_ltssm
+ffffffff81943c50 T qwx_pci_clear_all_intrs
+ffffffff81943d50 T qwx_pci_set_wlaon_pwr_ctrl
+ffffffff81943f10 T qwx_pci_force_wake
+ffffffff81944000 T qwx_pci_sw_reset
+ffffffff819441f0 T qwx_mhi_clear_vector
+ffffffff819442a0 T qwx_mhi_reset_device
+ffffffff81944430 T qwx_pci_msi_config
+ffffffff819444a0 T qwx_pci_msi_enable
+ffffffff81944500 T qwx_pci_msi_disable
+ffffffff81944560 T qwx_pci_aspm_disable
+ffffffff81944600 T qwx_mhi_start
+ffffffff819449a0 T qwx_mhi_stop
+ffffffff819449c0 T qwx_mhi_unregister
+ffffffff819449f0 T qwx_mhi_ring_doorbell
+ffffffff81944a60 T qwx_mhi_init_xfer_rings
+ffffffff81944bd0 T qwx_mhi_init_event_rings
+ffffffff81944d20 T qwx_mhi_init_cmd_ring
+ffffffff81944da0 T qwx_mhi_init_dev_ctxt
+ffffffff81944f70 T qwx_pci_cmd_ring_get_elem
+ffffffff81944fd0 T qwx_mhi_cmd_ring_submit
+ffffffff81945120 T qwx_mhi_send_cmd
+ffffffff81945200 T qwx_pci_xfer_ring_get_elem
+ffffffff81945250 T qwx_pci_xfer_ring_get_data
+ffffffff819452a0 T qwx_mhi_start_channel
+ffffffff819455b0 T qwx_mhi_start_channels
+ffffffff819456e0 T qwx_rddm_prepare
+ffffffff819459b0 T qwx_mhi_fw_load_handler
+ffffffff81945c20 T qwx_mhi_await_device_reset
+ffffffff81945cf0 T qwx_mhi_fw_load_bhi
+ffffffff81945f90 T qwx_mhi_fw_load_bhie
+ffffffff81946360 T qwx_mhi_await_device_ready
+ffffffff81946500 T qwx_mhi_ready_state_transition
+ffffffff81946700 T qwx_mhi_init_mmio
+ffffffff81946a80 T qwx_mhi_set_state
+ffffffff81946b00 T qwx_mhi_mission_mode_state_transition
+ffffffff81946c80 T qwx_mhi_low_power_mode_state_transition
+ffffffff81946cf0 T qwx_pci_event_ring_get_elem
+ffffffff81946d40 T qwx_mhi_state_change
+ffffffff819470f0 T qwx_pci_intr_ctrl_event_mhi
+ffffffff81947130 T qwx_pci_intr_ctrl_event_ee
+ffffffff81947170 T qwx_pci_intr_ctrl_event_cmd_complete
+ffffffff819472c0 T qwx_pci_intr_ctrl_event
+ffffffff81947570 T qwx_pci_intr_data_event_tx
+ffffffff81947930 T qwx_pci_intr_data_event
 ffffffff81948000 T cmpci_match
 ffffffff81948030 T cmpci_attach
 ffffffff81948610 T cmpci_activate