--- 7.4/2024-02-01T07:17:04Z/2024-01-22T00:00:00Z/nm-bsd-ot14.txt Sun Feb 4 01:12:02 2024 +++ 7.4/2024-02-01T07:17:04Z/2024-01-23T00:00:00Z/nm-bsd-ot14.txt Sun Feb 4 04:06:01 2024 @@ -2,14 +2,14 @@ 00011006 A mp_pdirpa 0001419d A acpi_pdirpa 01000000 A __kernel_phys_base -025f6000 T __kernel_kutext_phys -025fa000 C __kernel_cptext_phys -025fb000 C __kernel_rodata_phys -02eed000 R __kernel_kutext_page_phys -02eef000 C __kernel_randomdata_phys -031ac000 R __kernel_data_phys -03502000 D __kernel_kudata_phys -03503000 C __kernel_bss_phys +025f8000 T __kernel_kutext_phys +025fc000 C __kernel_cptext_phys +025fd000 C __kernel_rodata_phys +02eef000 R __kernel_kutext_page_phys +02ef1000 C __kernel_randomdata_phys +031ae000 R __kernel_data_phys +03504000 D __kernel_kudata_phys +03505000 C __kernel_bss_phys 03a00000 B __kernel_phys_end 80000000 A __kernel_virt_to_phys ffffffff80000000 A __kernel_base @@ -18941,12 +18941,12 @@ ffffffff81932c00 T drm_mode_getcrtc ffffffff81932da0 t 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drm_object_property_get_default_value -ffffffff8196c990 T drm_mode_object_get_properties -ffffffff8196cad0 T drm_mode_obj_get_properties_ioctl -ffffffff8196cd20 T drm_mode_obj_find_prop_id -ffffffff8196cd80 T drm_mode_obj_set_property_ioctl -ffffffff8196e000 T drm_mode_debug_printmodeline -ffffffff8196e140 T drm_mode_vrefresh -ffffffff8196e1e0 T drm_mode_create -ffffffff8196e200 T drm_mode_destroy -ffffffff8196e240 T drm_mode_probed_add -ffffffff8196e2e0 T drm_analog_tv_mode -ffffffff8196eb80 T drm_cvt_mode -ffffffff8196f000 T drm_mode_set_name -ffffffff8196f050 T drm_gtf_mode_complex -ffffffff8196f350 T drm_gtf_mode -ffffffff8196f3a0 T drm_mode_get_hv_timing -ffffffff8196f3f0 T drm_mode_init -ffffffff8196f4c0 T drm_mode_set_crtcinfo -ffffffff8196f680 T drm_mode_copy -ffffffff8196f6e0 T drm_mode_duplicate -ffffffff8196f760 T drm_mode_match -ffffffff8196f900 T drm_mode_equal -ffffffff8196f920 T drm_mode_equal_no_clocks -ffffffff8196f940 T drm_mode_equal_no_clocks_no_stereo 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drm_panel_remove_follower -ffffffff81975640 T devm_drm_panel_add_follower -ffffffff81975690 T drm_panel_of_backlight -ffffffff81976000 T drm_get_panel_orientation_quirk -ffffffff81977000 T drm_pci_set_busid -ffffffff81977090 t kasprintf -ffffffff81978000 T drm_universal_plane_init -ffffffff819780e0 t __drm_universal_plane_init -ffffffff819785c0 T __drmm_universal_plane_alloc -ffffffff81978700 t drmm_universal_plane_alloc_release -ffffffff81978750 T __drm_universal_plane_alloc -ffffffff81978890 T drm_plane_register_all -ffffffff81978980 T drm_plane_unregister_all -ffffffff819789f0 T drm_plane_cleanup -ffffffff81978b40 T drm_plane_from_index -ffffffff81978ba0 T drm_plane_force_disable -ffffffff81978cb0 T drm_mode_plane_set_obj_prop -ffffffff81978d30 T drm_mode_getplane_res -ffffffff81978e30 T drm_mode_getplane -ffffffff81978f80 T drm_plane_check_pixel_format -ffffffff81979040 T drm_any_plane_has_format -ffffffff81979170 T drm_mode_setplane -ffffffff81979460 T drm_mode_cursor_ioctl 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drm_kms_helper_poll_disable -ffffffff8197ef50 T drm_kms_helper_poll_init -ffffffff8197efb0 t output_poll_execute -ffffffff8197f200 T drm_kms_helper_poll_fini -ffffffff8197f250 T drm_connector_helper_hpd_irq_event -ffffffff8197f310 t check_connector_changed -ffffffff8197f4e0 T drm_helper_hpd_irq_event -ffffffff8197f630 T drm_crtc_helper_mode_valid_fixed -ffffffff8197f680 T drm_connector_helper_get_modes_from_ddc -ffffffff8197f710 T drm_connector_helper_get_modes_fixed -ffffffff8197f880 T drm_connector_helper_get_modes -ffffffff8197f8f0 T drm_connector_helper_tv_get_modes -ffffffff8197fb30 t __delayed_work_tick -ffffffff81980000 T drm_property_create -ffffffff819801f0 T drm_property_create_enum -ffffffff819802a0 T drm_property_add_enum -ffffffff819804a0 T drm_property_destroy -ffffffff81980550 T drm_property_create_bitmask -ffffffff81980680 T drm_property_create_range -ffffffff819806f0 T drm_property_create_signed_range -ffffffff81980760 T drm_property_create_object -ffffffff81980800 T drm_property_create_bool -ffffffff81980860 T drm_mode_getproperty_ioctl -ffffffff81980ab0 T drm_property_create_blob -ffffffff81980bf0 t drm_property_free_blob -ffffffff81980c70 T drm_property_blob_put -ffffffff81980cb0 T drm_property_destroy_user_blobs -ffffffff81980d30 T drm_property_blob_get -ffffffff81980d70 T drm_property_lookup_blob -ffffffff81980d90 T drm_property_replace_global_blob -ffffffff81980ee0 T drm_property_replace_blob -ffffffff81980f50 T drm_mode_getblob_ioctl -ffffffff81981010 T drm_mode_createblob_ioctl -ffffffff81981110 T drm_mode_destroyblob_ioctl -ffffffff81981210 T drm_property_change_valid_get -ffffffff81981470 T drm_property_change_valid_put -ffffffff81982000 T drm_rect_intersect -ffffffff81982080 T drm_rect_clip_scaled -ffffffff819822f0 T drm_rect_calc_hscale -ffffffff819823c0 T drm_rect_calc_vscale -ffffffff81982490 T drm_rect_debug_print -ffffffff819825b0 T drm_rect_rotate -ffffffff81982670 T drm_rect_rotate_inv -ffffffff81983000 T drm_self_refresh_helper_update_avg_times -ffffffff81983150 T drm_self_refresh_helper_alter_state -ffffffff819832e0 T drm_self_refresh_helper_init -ffffffff81983470 t drm_self_refresh_helper_entry_work -ffffffff819835d0 T drm_self_refresh_helper_cleanup -ffffffff81983650 t __delayed_work_tick -ffffffff81984000 T drm_suballoc_manager_init -ffffffff81984180 T drm_suballoc_manager_fini -ffffffff81984290 t drm_suballoc_try_free -ffffffff81984380 T drm_suballoc_new -ffffffff81984da0 t drm_suballoc_event -ffffffff81984ee0 T drm_suballoc_free -ffffffff81986000 T drm_syncobj_find -ffffffff81986070 T drm_syncobj_add_point -ffffffff81986180 t syncobj_wait_syncobj_func -ffffffff81986230 t syncobj_eventfd_entry_func -ffffffff81986310 T drm_syncobj_replace_fence -ffffffff819863c0 T drm_syncobj_find_fence -ffffffff81986710 t drm_syncobj_fence_add_wait -ffffffff819867e0 T drm_syncobj_free -ffffffff81986860 T drm_syncobj_create -ffffffff81986a30 T drm_syncobj_get_handle -ffffffff81986b40 T drm_syncobj_get_fd -ffffffff81986b90 T drm_syncobj_open -ffffffff81986bc0 T drm_syncobj_release -ffffffff81986c00 t drm_syncobj_release_handle -ffffffff81986cc0 T drm_syncobj_create_ioctl -ffffffff81986df0 T drm_syncobj_destroy_ioctl -ffffffff81986f30 T drm_syncobj_handle_to_fd_ioctl -ffffffff81987120 T drm_syncobj_fd_to_handle_ioctl -ffffffff819872d0 T drm_syncobj_transfer_ioctl -ffffffff819876b0 T drm_timeout_abs_to_jiffies -ffffffff81987780 T drm_syncobj_wait_ioctl -ffffffff81987900 t drm_syncobj_array_find -ffffffff81987b20 t drm_syncobj_array_free -ffffffff81987c10 T drm_syncobj_timeline_wait_ioctl -ffffffff81987d90 T drm_syncobj_eventfd_ioctl -ffffffff81987dc0 T drm_syncobj_reset_ioctl -ffffffff81987ea0 T drm_syncobj_signal_ioctl -ffffffff81988000 T drm_syncobj_timeline_signal_ioctl -ffffffff81988240 T drm_syncobj_query_ioctl -ffffffff81988450 t drm_syncobj_array_wait_timeout -ffffffff819888b0 t syncobj_wait_fence_func -ffffffff819888d0 t syncobj_eventfd_entry_fence_func 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drm_crtc_vblank_get -ffffffff8198ac60 T drm_vblank_put -ffffffff8198ad90 T drm_crtc_vblank_put -ffffffff8198adb0 T drm_wait_one_vblank -ffffffff8198b2a0 T drm_crtc_wait_one_vblank -ffffffff8198b2c0 T drm_crtc_vblank_off -ffffffff8198b6b0 T drm_crtc_vblank_reset -ffffffff8198b7e0 T drm_crtc_set_max_vblank_count -ffffffff8198b8c0 T drm_crtc_vblank_on -ffffffff8198ba10 t drm_reset_vblank_timestamp -ffffffff8198bbf0 T drm_crtc_vblank_restore -ffffffff8198bfd0 T drm_legacy_modeset_ctl_ioctl -ffffffff8198c1f0 T drm_wait_vblank_ioctl -ffffffff8198c740 t drm_wait_vblank_reply -ffffffff8198c850 t drm_queue_vblank_event -ffffffff8198cb90 T drm_handle_vblank -ffffffff8198ce80 t drm_handle_vblank_events -ffffffff8198d110 T drm_crtc_handle_vblank -ffffffff8198d130 T drm_crtc_get_sequence_ioctl -ffffffff8198d300 T drm_crtc_queue_sequence_ioctl -ffffffff8198d5c0 t __get_vblank_counter -ffffffff8198e000 T drm_handle_vblank_works -ffffffff8198e1a0 T drm_vblank_cancel_pending_works -ffffffff8198e2e0 T drm_vblank_work_schedule -ffffffff8198e550 T drm_vblank_work_cancel_sync -ffffffff8198e6a0 T drm_vblank_work_flush -ffffffff8198e7d0 T drm_vblank_work_init -ffffffff8198e840 T drm_vblank_worker_init -ffffffff8198f000 T drm_vma_offset_manager_init -ffffffff8198f040 T drm_vma_offset_manager_destroy -ffffffff8198f060 T drm_vma_offset_lookup_locked -ffffffff8198f0f0 T drm_vma_offset_add -ffffffff8198f180 T drm_vma_offset_remove -ffffffff8198f1d0 T drm_vma_node_allow -ffffffff8198f1f0 t vma_node_allow -ffffffff8198f310 T drm_vma_node_allow_once -ffffffff8198f330 T drm_vma_node_revoke -ffffffff8198f3b0 T drm_vma_node_is_allowed -ffffffff81990000 T hdmi_avi_infoframe_init -ffffffff81990070 T hdmi_avi_infoframe_check -ffffffff819900c0 T hdmi_avi_infoframe_pack_only -ffffffff819902c0 T hdmi_avi_infoframe_pack -ffffffff81990320 T hdmi_spd_infoframe_init -ffffffff819903e0 T hdmi_spd_infoframe_check -ffffffff81990430 T hdmi_spd_infoframe_pack_only -ffffffff81990570 T hdmi_spd_infoframe_pack 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drm_dp_128b132b_eq_interlane_align_done -ffffffff819982e0 T drm_dp_128b132b_cds_interlane_align_done -ffffffff81998310 T drm_dp_128b132b_link_training_failed -ffffffff81998340 T drm_dp_read_clock_recovery_delay -ffffffff81998450 T drm_dp_read_channel_eq_delay -ffffffff81998550 T drm_dp_128b132b_read_aux_rd_interval -ffffffff81998600 T drm_dp_link_train_clock_recovery_delay -ffffffff81998690 t __8b10b_clock_recovery_delay_us -ffffffff81998710 T drm_dp_link_train_channel_eq_delay -ffffffff81998780 T drm_dp_phy_name -ffffffff819987c0 T drm_dp_lttpr_link_train_clock_recovery_delay -ffffffff819987e0 T drm_dp_lttpr_link_train_channel_eq_delay -ffffffff81998850 T drm_dp_link_rate_to_bw_code -ffffffff819988c0 T drm_dp_bw_code_to_link_rate -ffffffff81998920 T drm_dp_dpcd_probe -ffffffff81998a60 t drm_dp_dpcd_access -ffffffff81998b90 T drm_dp_dpcd_read -ffffffff81998cc0 T drm_dp_dpcd_write -ffffffff81998dd0 T drm_dp_dpcd_read_link_status -ffffffff81998df0 T drm_dp_dpcd_read_phy_link_status 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drm_fb_xrgb8888_to_xbgr8888_line +ffffffff81950200 t drm_fb_xrgb8888_to_abgr8888_line +ffffffff81951000 T drm_mode_legacy_fb_format +ffffffff819510f0 T drm_driver_legacy_fb_format +ffffffff819511f0 T __drm_format_info +ffffffff81951270 T drm_format_info +ffffffff81951320 T drm_get_format_info +ffffffff819513f0 T drm_format_info_block_width +ffffffff81951440 T drm_format_info_block_height +ffffffff81951490 T drm_format_info_bpp +ffffffff81951510 T drm_format_info_min_pitch +ffffffff81952000 T drm_framebuffer_check_src_coords +ffffffff81952120 T drm_mode_addfb +ffffffff81952330 T drm_mode_addfb2 +ffffffff81952430 T drm_mode_addfb_ioctl +ffffffff81952450 T drm_internal_framebuffer_create +ffffffff81952a30 T drm_mode_addfb2_ioctl +ffffffff81952b30 T drm_mode_rmfb +ffffffff81952d10 T drm_framebuffer_lookup +ffffffff81952d60 t drm_mode_rmfb_work_fn +ffffffff81952e20 T drm_mode_rmfb_ioctl +ffffffff81952e40 T drm_mode_getfb +ffffffff81952f90 T drm_mode_getfb2_ioctl +ffffffff81953340 T drm_mode_dirtyfb_ioctl +ffffffff819534e0 T drm_fb_release +ffffffff819535f0 T drm_framebuffer_free +ffffffff81953630 T drm_framebuffer_init +ffffffff81953790 T drm_framebuffer_unregister_private +ffffffff819537d0 T drm_framebuffer_cleanup +ffffffff81953830 T drm_framebuffer_remove +ffffffff81953cc0 T drm_framebuffer_plane_width +ffffffff81953d10 T drm_framebuffer_plane_height +ffffffff81953d60 T drm_framebuffer_print_info +ffffffff81955000 T drm_ref +ffffffff81955030 T drm_unref +ffffffff819550b0 T drm_fault +ffffffff81955280 T drm_flush +ffffffff819552b0 T udv_attach_drm +ffffffff819554a0 T drm_gem_init +ffffffff81955550 t drm_gem_init_release +ffffffff81955570 T drm_gem_object_init +ffffffff819556f0 T drm_gem_private_object_init +ffffffff81955810 T drm_gem_private_object_fini +ffffffff81955870 T drm_gem_handle_delete +ffffffff81955960 t drm_gem_object_release_handle +ffffffff819559f0 T drm_gem_dumb_map_offset +ffffffff81955b20 T drm_gem_object_lookup +ffffffff81955b90 T drm_gem_create_mmap_offset +ffffffff81955bc0 T drm_gem_handle_create_tail +ffffffff81955d30 t drm_gem_object_handle_put_unlocked +ffffffff81955e80 T drm_gem_handle_create +ffffffff81955ed0 T drm_gem_free_mmap_offset +ffffffff81955f00 T drm_gem_create_mmap_offset_size +ffffffff81955f30 T drm_gem_get_pages +ffffffff81955f80 T drm_gem_put_pages +ffffffff81955fb0 T drm_gem_objects_lookup +ffffffff81956110 T drm_gem_dma_resv_wait +ffffffff81956240 T drm_gem_close_ioctl +ffffffff81956290 T drm_gem_flink_ioctl +ffffffff81956400 T drm_gem_open_ioctl +ffffffff81956530 T drm_gem_open +ffffffff81956560 T drm_gem_release +ffffffff819565a0 T drm_gem_object_release +ffffffff819566f0 T drm_gem_lru_remove +ffffffff819567d0 T drm_gem_object_free +ffffffff81956820 T drm_gem_mmap_obj +ffffffff81956920 T drm_gem_mmap +ffffffff81956b90 T drm_gem_print_info +ffffffff81956cb0 T drm_gem_pin +ffffffff81956cf0 T drm_gem_unpin +ffffffff81956d30 T drm_gem_vmap +ffffffff81956d90 T drm_gem_vunmap +ffffffff81956e00 T drm_gem_vmap_unlocked +ffffffff81956ff0 T drm_gem_vunmap_unlocked +ffffffff819571b0 T drm_gem_lock_reservations +ffffffff819575a0 T drm_gem_unlock_reservations +ffffffff81957690 T drm_gem_lru_init +ffffffff819576d0 T drm_gem_lru_move_tail_locked +ffffffff819577d0 T drm_gem_lru_move_tail +ffffffff819578c0 T drm_gem_lru_scan +ffffffff81957ca0 T drm_gem_evict +ffffffff81958000 T drm_gem_plane_helper_prepare_fb +ffffffff81959000 T drm_gem_dma_create +ffffffff81959220 T drm_gem_dma_free_object +ffffffff819592c0 T drm_gem_dma_dumb_create_internal +ffffffff81959400 T drm_gem_dma_dumb_create +ffffffff81959440 T drm_gem_dma_fault +ffffffff819595e0 T drm_gem_dma_get_sg_table +ffffffff81959610 T drm_gem_dma_prime_import_sg_table +ffffffff81959640 T drm_gem_dma_vmap +ffffffff8195a000 T drm_gem_fb_destroy +ffffffff8195a0c0 T drm_gem_fb_create_handle +ffffffff8195a0e0 T drm_gem_fb_create +ffffffff8195a220 T drm_gem_fb_get_obj +ffffffff8195b000 T drm_ht_create +ffffffff8195b080 T drm_ht_verbose_list +ffffffff8195b140 T drm_ht_insert_item +ffffffff8195b190 T drm_ht_just_insert_please +ffffffff8195b260 T drm_ht_find_item +ffffffff8195b2b0 T drm_ht_remove_key +ffffffff8195b300 T drm_ht_remove_item +ffffffff8195b350 T drm_ht_remove +ffffffff8195c000 T drm_getunique +ffffffff8195c0a0 T drm_getclient +ffffffff8195c110 T drm_noop +ffffffff8195c170 T drm_invalid_op +ffffffff8195c1a0 T drm_version +ffffffff8195c3b0 T pledge_ioctl_drm +ffffffff8195c480 T drm_ioctl_kernel +ffffffff8195c4d0 T drm_ioctl +ffffffff8195c520 T drm_ioctl_flags +ffffffff8195c570 T drm_do_ioctl +ffffffff8195c8a0 T drmioctl +ffffffff8195c9f0 t drm_getstats +ffffffff8195ca40 t drm_setversion +ffffffff8195cba0 t drm_getcap +ffffffff8195cd60 t drm_setclientcap +ffffffff8195d000 T tasklet_unlock_wait +ffffffff8195d080 T tasklet_unlock_spin_wait +ffffffff8195d100 T tasklet_run +ffffffff8195d160 T set_current_state +ffffffff8195d200 T __set_current_state +ffffffff8195d290 T schedule +ffffffff8195d2d0 T schedule_timeout +ffffffff8195d380 T schedule_timeout_uninterruptible +ffffffff8195d3e0 T wake_up_process +ffffffff8195d460 T autoremove_wake_function +ffffffff8195d510 T prepare_to_wait +ffffffff8195d600 T finish_wait +ffffffff8195d6b0 T flush_workqueue +ffffffff8195d6f0 T flush_work +ffffffff8195d740 T flush_delayed_work +ffffffff8195d7e0 T kthread_func +ffffffff8195d820 T kthread_run +ffffffff8195d900 T kthread_create_worker +ffffffff8195d9c0 T kthread_destroy_worker +ffffffff8195da00 T kthread_init_work +ffffffff8195da20 T kthread_queue_work +ffffffff8195da60 T kthread_cancel_work_sync +ffffffff8195daa0 T kthread_flush_work +ffffffff8195dae0 T kthread_flush_worker +ffffffff8195db20 T kthread_lookup +ffffffff8195dba0 T kthread_should_park +ffffffff8195dc20 T kthread_parkme +ffffffff8195dce0 T kthread_park +ffffffff8195dde0 T kthread_unpark +ffffffff8195de40 T kthread_should_stop +ffffffff8195dec0 T kthread_stop +ffffffff8195e020 T dmi_match +ffffffff8195e0d0 T dmi_first_match +ffffffff8195e1c0 T dmi_get_system_info +ffffffff8195e230 T dmi_check_system +ffffffff8195e330 T alloc_pages +ffffffff8195e400 T __free_pages +ffffffff8195e570 T __pagevec_release +ffffffff8195e610 T kmap +ffffffff8195e650 T kunmap_va +ffffffff8195e670 T kmap_atomic_prot +ffffffff8195e700 T kunmap_atomic +ffffffff8195e780 T vmap +ffffffff8195e860 T vunmap +ffffffff8195e8b0 T is_vmalloc_addr +ffffffff8195e8f0 T print_hex_dump +ffffffff8195e9c0 T memchr_inv +ffffffff8195ea30 T panic_cmp +ffffffff8195ea50 T linux_root_RB_INSERT_COLOR +ffffffff8195ec50 T linux_root_RB_REMOVE_COLOR +ffffffff8195ef80 T linux_root_RB_REMOVE +ffffffff8195f0c0 T linux_root_RB_INSERT +ffffffff8195f130 T linux_root_RB_FIND +ffffffff8195f180 T linux_root_RB_NFIND +ffffffff8195f1d0 T linux_root_RB_NEXT +ffffffff8195f240 T linux_root_RB_PREV +ffffffff8195f2b0 T linux_root_RB_MINMAX +ffffffff8195f300 T idr_init +ffffffff8195f330 T idr_destroy +ffffffff8195f470 T idr_tree_SPLAY_REMOVE +ffffffff8195f4f0 T idr_preload +ffffffff8195f580 T idr_alloc +ffffffff8195f710 T idr_tree_SPLAY_INSERT +ffffffff8195f7b0 T idr_replace +ffffffff8195f830 T idr_remove +ffffffff8195f8f0 T idr_find +ffffffff8195f960 T idr_get_next +ffffffff8195fa90 T idr_for_each +ffffffff8195fba0 T idr_cmp +ffffffff8195fbe0 T idr_tree_SPLAY +ffffffff8195fd10 T idr_tree_SPLAY_MINMAX +ffffffff8195fe00 T ida_init +ffffffff8195fe30 T ida_destroy +ffffffff8195fe40 T ida_simple_get +ffffffff8195fe60 T ida_simple_remove +ffffffff8195fe80 T ida_alloc_min +ffffffff8195fea0 T ida_alloc_max +ffffffff8195fec0 T ida_free +ffffffff8195fee0 T xarray_cmp +ffffffff8195ff20 T xarray_tree_SPLAY_INSERT +ffffffff8195ffc0 T xarray_tree_SPLAY +ffffffff819600f0 T xarray_tree_SPLAY_REMOVE +ffffffff81960170 T xarray_tree_SPLAY_MINMAX +ffffffff81960260 T xa_init_flags +ffffffff819602e0 T xa_destroy +ffffffff81960420 T __xa_alloc +ffffffff819605a0 T __xa_alloc_cyclic +ffffffff81960600 T __xa_erase +ffffffff819606c0 T __xa_load +ffffffff81960730 T __xa_store +ffffffff819608b0 T xa_get_next +ffffffff819609e0 T sg_alloc_table +ffffffff81960a60 T sg_free_table +ffffffff81960ac0 T sg_copy_from_buffer +ffffffff81960af0 T i2c_master_xfer +ffffffff81960c20 T __i2c_transfer +ffffffff81960cd0 T i2c_transfer +ffffffff81960da0 T i2c_bb_master_xfer +ffffffff81960e80 T i2c_bb_functionality +ffffffff81960eb0 T i2c_bit_add_bus +ffffffff81960ef0 T vga_disable_bridge +ffffffff81960fa0 T vga_get_uninterruptible +ffffffff81960ff0 T vga_put +ffffffff81961070 T acpi_get_table +ffffffff81961130 T acpi_put_table +ffffffff81961160 T acpi_get_handle +ffffffff819611b0 T acpi_get_name +ffffffff81961250 T acpi_evaluate_object +ffffffff819614b0 T drm_linux_acpi_notify +ffffffff81961530 T register_acpi_notifier +ffffffff81961570 T unregister_acpi_notifier +ffffffff81961600 T acpi_format_exception +ffffffff81961650 T backlight_do_update_status +ffffffff81961670 T backlight_device_register +ffffffff81961720 T backlight_device_unregister +ffffffff81961780 T backlight_schedule_update_status +ffffffff819617a0 T backlight_enable +ffffffff819617e0 T backlight_disable +ffffffff81961820 T backlight_device_get_by_name +ffffffff81961890 T dev_set_drvdata +ffffffff81961930 T dev_get_drvdata +ffffffff81961990 T drm_sysfs_hotplug_event +ffffffff819619b0 T drm_sysfs_connector_hotplug_event +ffffffff819619d0 T drm_sysfs_connector_status_event +ffffffff819619f0 T drm_sysfs_connector_property_event +ffffffff81961a10 T dma_fence_get +ffffffff81961a50 T dma_fence_get_rcu +ffffffff81961a90 T dma_fence_get_rcu_safe +ffffffff81961ad0 T dma_fence_release +ffffffff81961b00 T dma_fence_put +ffffffff81961b70 T dma_fence_signal_timestamp_locked +ffffffff81961c20 T dma_fence_signal +ffffffff81961d50 T dma_fence_signal_locked +ffffffff81961e60 T dma_fence_signal_timestamp +ffffffff81961f40 T dma_fence_is_signaled +ffffffff81961fb0 T dma_fence_is_signaled_locked +ffffffff819620f0 T dma_fence_timestamp +ffffffff81962190 T dma_fence_wait_timeout +ffffffff819621f0 T dma_fence_default_wait +ffffffff819623d0 T dma_fence_wait +ffffffff81962430 T dma_fence_enable_sw_signaling +ffffffff81962580 T dma_fence_init +ffffffff819625e0 T dma_fence_add_callback +ffffffff81962710 T dma_fence_remove_callback +ffffffff81962790 T dma_fence_context_alloc +ffffffff819627d0 t dma_fence_default_wait_cb +ffffffff81962820 T dma_fence_wait_any_timeout +ffffffff81962b30 T dma_fence_set_deadline +ffffffff81962bd0 T dma_fence_get_stub +ffffffff81962d60 T dma_fence_allocate_private_stub +ffffffff81962e80 T dma_fence_array_create +ffffffff81962f90 t irq_dma_fence_array_work +ffffffff81963020 T dma_fence_array_first +ffffffff81963070 T dma_fence_array_next +ffffffff819630c0 t dma_fence_array_get_driver_name +ffffffff819630f0 t dma_fence_array_get_timeline_name +ffffffff81963120 t dma_fence_array_enable_signaling +ffffffff81963220 t dma_fence_array_signaled +ffffffff81963270 t dma_fence_array_release +ffffffff81963330 T dma_fence_chain_find_seqno +ffffffff81963450 T dma_fence_chain_walk +ffffffff81963680 T dma_fence_chain_init +ffffffff81963790 t dma_fence_chain_get_driver_name +ffffffff819637c0 t dma_fence_chain_get_timeline_name +ffffffff819637f0 t dma_fence_chain_enable_signaling +ffffffff819639a0 t dma_fence_chain_signaled +ffffffff81963a90 t dma_fence_chain_release +ffffffff81963bd0 T dma_fence_is_container +ffffffff81963c20 T dmabuf_read +ffffffff81963c50 T dmabuf_write +ffffffff81963c80 T dmabuf_ioctl +ffffffff81963cb0 T dmabuf_kqfilter +ffffffff81963ce0 T dmabuf_stat +ffffffff81963da0 T dmabuf_close +ffffffff81963e10 T dmabuf_seek +ffffffff81963ea0 T dma_buf_export +ffffffff81963f50 T dma_buf_get +ffffffff81963fe0 T dma_buf_put +ffffffff81964090 T dma_buf_fd +ffffffff819641a0 T get_dma_buf +ffffffff819641e0 T pcie_get_speed_cap +ffffffff81964390 T printk +ffffffff81964430 T pcie_get_width_cap +ffffffff81964520 T pcie_aspm_enabled +ffffffff819645b0 T wait_on_bit +ffffffff81964680 T wait_on_bit_timeout +ffffffff81964750 T wake_up_bit +ffffffff81964790 T clear_and_wake_up_bit +ffffffff819647e0 T bit_waitqueue +ffffffff81964810 T __var_waitqueue +ffffffff81964840 T drm_linux_init +ffffffff819649b0 T drm_linux_exit +ffffffff81964a10 T pci_resize_resource +ffffffff81964b60 T register_shrinker +ffffffff81964bb0 T unregister_shrinker +ffffffff81964c10 T drmbackoff +ffffffff81964ca0 T bitmap_zalloc +ffffffff81964cd0 T bitmap_free +ffffffff81964cf0 T atomic_dec_and_mutex_lock +ffffffff81964d70 T interval_tree_iter_first +ffffffff81964e20 T interval_tree_remove +ffffffff81964e40 T interval_tree_insert +ffffffff81964eb0 T syncfile_read +ffffffff81964ee0 T syncfile_write +ffffffff81964f10 T syncfile_ioctl +ffffffff81964f40 T syncfile_kqfilter +ffffffff81964f70 T syncfile_stat +ffffffff81965020 T syncfile_close +ffffffff819650c0 T syncfile_seek +ffffffff81965140 T fd_install +ffffffff81965210 T fput +ffffffff81965260 T get_unused_fd_flags +ffffffff81965370 T put_unused_fd +ffffffff81965400 T sync_file_get_fence +ffffffff819654b0 T sync_file_create +ffffffff81965540 T drm_firmware_drivers_only +ffffffff81965570 T memremap +ffffffff819655c0 T memunmap +ffffffff819655e0 T dma_tag_lookup +ffffffff81965650 T dma_alloc_coherent +ffffffff81965740 T dma_free_coherent +ffffffff81965870 T dma_get_sgtable +ffffffff81965940 T dma_map_resource +ffffffff81965a60 T component_add +ffffffff81965ad0 T component_add_typed +ffffffff81965b40 T component_bind_all +ffffffff81965bd0 T component_master_add_with_match +ffffffff81965cc0 t dma_fence_stub_get_name +ffffffff81965cf0 t dma_fence_array_cb_func +ffffffff81965d70 t dma_fence_chain_cb +ffffffff81965e30 t dma_fence_chain_timo +ffffffff81966000 T drmm_kzalloc +ffffffff81966100 T drmm_kcalloc +ffffffff81966210 T drmm_kstrdup +ffffffff81966340 T drmm_kfree +ffffffff81966440 T drmm_add_action +ffffffff81966500 T drmm_add_action_or_reset +ffffffff819665d0 T drm_managed_release +ffffffff81966690 T drmm_add_final_kfree +ffffffff81967000 T mipi_dsi_attach +ffffffff81967050 T mipi_dsi_detach +ffffffff819670a0 T devm_mipi_dsi_attach +ffffffff81967110 T mipi_dsi_packet_format_is_short +ffffffff81967150 T mipi_dsi_packet_format_is_long +ffffffff81967190 T mipi_dsi_create_packet +ffffffff819672a0 T mipi_dsi_shutdown_peripheral +ffffffff81967350 T mipi_dsi_turn_on_peripheral +ffffffff81967400 T mipi_dsi_set_maximum_return_packet_size +ffffffff819674b0 T mipi_dsi_compression_mode +ffffffff81967560 T mipi_dsi_picture_parameter_set +ffffffff81967610 T mipi_dsi_generic_write +ffffffff819676d0 T mipi_dsi_generic_read +ffffffff81967780 T mipi_dsi_dcs_write_buffer +ffffffff81967840 T mipi_dsi_dcs_write +ffffffff81967990 T mipi_dsi_dcs_read +ffffffff81967a30 T mipi_dsi_dcs_nop +ffffffff81967ae0 T mipi_dsi_dcs_soft_reset +ffffffff81967b90 T mipi_dsi_dcs_get_power_mode +ffffffff81967c50 T mipi_dsi_dcs_get_pixel_format +ffffffff81967d10 T mipi_dsi_dcs_enter_sleep_mode +ffffffff81967dc0 T mipi_dsi_dcs_exit_sleep_mode +ffffffff81967e70 T mipi_dsi_dcs_set_display_off +ffffffff81967f20 T mipi_dsi_dcs_set_display_on +ffffffff81967fd0 T mipi_dsi_dcs_set_column_address +ffffffff81968090 T mipi_dsi_dcs_set_page_address +ffffffff81968150 T mipi_dsi_dcs_set_tear_off +ffffffff81968200 T mipi_dsi_dcs_set_tear_on +ffffffff819682b0 T mipi_dsi_dcs_set_pixel_format +ffffffff81969000 T __drm_mm_interval_first +ffffffff819690c0 T drm_mm_reserve_node +ffffffff81969340 t add_hole +ffffffff819694a0 T drm_mm_insert_node_in_range +ffffffff81969a90 T drm_mm_remove_node +ffffffff81969bc0 T drm_mm_replace_node +ffffffff81969da0 T drm_mm_scan_init_with_range +ffffffff81969e30 T drm_mm_scan_add_block +ffffffff81969fa0 T drm_mm_scan_remove_block +ffffffff8196a020 T drm_mm_scan_color_evict +ffffffff8196a100 T drm_mm_init +ffffffff8196a1b0 T drm_mm_takedown +ffffffff8196a1f0 T drm_mm_print +ffffffff8196b000 T drm_modeset_register_all +ffffffff8196b0a0 T drm_modeset_unregister_all +ffffffff8196b0e0 T drm_mode_getresources +ffffffff8196b390 T drm_mode_config_reset +ffffffff8196b4f0 T drmm_mode_config_init +ffffffff8196bb70 T drm_mode_config_cleanup +ffffffff8196be90 t drm_mode_config_init_release +ffffffff8196bea0 T drm_mode_config_validate +ffffffff8196d000 T __drm_mode_object_add +ffffffff8196d100 T drm_mode_object_add +ffffffff8196d1e0 T drm_mode_object_register +ffffffff8196d230 T drm_mode_object_unregister +ffffffff8196d2d0 T drm_mode_object_lease_required +ffffffff8196d320 T __drm_mode_object_find +ffffffff8196d3d0 T drm_mode_object_find +ffffffff8196d480 T drm_mode_object_put +ffffffff8196d500 T drm_mode_object_get +ffffffff8196d560 T drm_object_attach_property +ffffffff8196d670 T drm_object_property_set_value +ffffffff8196d750 T drm_object_property_get_value +ffffffff8196d7e0 t __drm_object_property_get_value +ffffffff8196d8c0 T drm_object_property_get_default_value +ffffffff8196d990 T drm_mode_object_get_properties +ffffffff8196dad0 T drm_mode_obj_get_properties_ioctl +ffffffff8196dd20 T drm_mode_obj_find_prop_id +ffffffff8196dd80 T drm_mode_obj_set_property_ioctl +ffffffff8196f000 T drm_mode_debug_printmodeline +ffffffff8196f140 T drm_mode_vrefresh +ffffffff8196f1e0 T drm_mode_create +ffffffff8196f200 T drm_mode_destroy +ffffffff8196f240 T drm_mode_probed_add +ffffffff8196f2e0 T drm_analog_tv_mode +ffffffff8196fb80 T drm_cvt_mode +ffffffff81970000 T drm_mode_set_name +ffffffff81970050 T drm_gtf_mode_complex +ffffffff81970350 T drm_gtf_mode +ffffffff819703a0 T drm_mode_get_hv_timing +ffffffff819703f0 T drm_mode_init +ffffffff819704c0 T drm_mode_set_crtcinfo +ffffffff81970680 T drm_mode_copy +ffffffff819706e0 T drm_mode_duplicate +ffffffff81970760 T drm_mode_match +ffffffff81970900 T drm_mode_equal +ffffffff81970920 T drm_mode_equal_no_clocks +ffffffff81970940 T drm_mode_equal_no_clocks_no_stereo +ffffffff81970a00 T drm_mode_validate_driver +ffffffff81970af0 T drm_mode_validate_size +ffffffff81970b40 T drm_mode_validate_ycbcr420 +ffffffff81970bb0 T drm_mode_is_420_only +ffffffff81970c00 T drm_get_mode_status_name +ffffffff81970c80 T drm_mode_prune_invalid +ffffffff81970f10 T drm_mode_sort +ffffffff81970f40 t drm_mode_compare +ffffffff819710e0 T drm_connector_list_update +ffffffff819712b0 T drm_mode_parse_command_line_for_connector +ffffffff819712e0 T drm_mode_create_from_cmdline_mode +ffffffff819714a0 T drm_mode_convert_to_umode +ffffffff81971640 T drm_mode_convert_umode +ffffffff81971860 T drm_mode_is_420_also +ffffffff819718b0 T drm_mode_is_420 +ffffffff81972000 T drm_helper_move_panel_connectors_to_head +ffffffff819720f0 T drm_helper_mode_fill_fb_struct +ffffffff819721b0 T drm_crtc_init +ffffffff81972280 T drm_mode_config_helper_suspend +ffffffff81972310 T drm_mode_config_helper_resume +ffffffff81973000 T drm_modeset_lock_all +ffffffff81973290 T drm_modeset_acquire_init +ffffffff81973320 T drm_modeset_lock_all_ctx +ffffffff81973410 T drm_modeset_backoff +ffffffff819734e0 T drm_modeset_acquire_fini +ffffffff81973510 T drm_warn_on_modeset_not_all_locked +ffffffff81973660 T drm_modeset_unlock_all +ffffffff81973750 T drm_modeset_drop_locks +ffffffff819737e0 T drm_modeset_unlock +ffffffff819738b0 t modeset_lock +ffffffff81973bf0 T drm_modeset_lock_init +ffffffff81973c50 T drm_modeset_lock +ffffffff81973d70 T drm_modeset_lock_single_interruptible +ffffffff81973e90 t __ww_mutex_lock +ffffffff81975000 T drm_mtrr_add +ffffffff81975070 T drm_mtrr_del +ffffffff81976000 T drm_panel_init +ffffffff81976090 T drm_panel_add +ffffffff819760e0 T drm_panel_remove +ffffffff81976140 T drm_panel_prepare +ffffffff81976250 T drm_panel_unprepare +ffffffff81976360 T drm_panel_enable +ffffffff81976450 T drm_panel_disable +ffffffff81976530 T drm_panel_get_modes +ffffffff81976580 T drm_is_panel_follower +ffffffff819765d0 T drm_panel_add_follower +ffffffff81976620 T drm_panel_remove_follower +ffffffff81976640 T devm_drm_panel_add_follower +ffffffff81976690 T drm_panel_of_backlight +ffffffff81977000 T drm_get_panel_orientation_quirk +ffffffff81978000 T drm_pci_set_busid +ffffffff81978090 t kasprintf +ffffffff81979000 T drm_universal_plane_init +ffffffff819790e0 t __drm_universal_plane_init +ffffffff819795c0 T __drmm_universal_plane_alloc +ffffffff81979700 t drmm_universal_plane_alloc_release +ffffffff81979750 T __drm_universal_plane_alloc +ffffffff81979890 T drm_plane_register_all +ffffffff81979980 T drm_plane_unregister_all +ffffffff819799f0 T drm_plane_cleanup +ffffffff81979b40 T drm_plane_from_index +ffffffff81979ba0 T drm_plane_force_disable +ffffffff81979cb0 T drm_mode_plane_set_obj_prop +ffffffff81979d30 T drm_mode_getplane_res +ffffffff81979e30 T drm_mode_getplane +ffffffff81979f80 T drm_plane_check_pixel_format +ffffffff8197a040 T drm_any_plane_has_format +ffffffff8197a170 T drm_mode_setplane +ffffffff8197a460 T drm_mode_cursor_ioctl +ffffffff8197a4d0 t drm_mode_cursor_common +ffffffff8197aa10 T drm_mode_cursor2_ioctl +ffffffff8197aa30 T drm_mode_page_flip_ioctl +ffffffff8197af90 T drm_plane_enable_fb_damage_clips +ffffffff8197afb0 T drm_plane_get_damage_clips_count +ffffffff8197aff0 T __drm_plane_get_damage_clips +ffffffff8197b030 T drm_plane_get_damage_clips +ffffffff8197b0d0 T drm_create_scaling_filter_prop +ffffffff8197b220 T drm_plane_create_scaling_filter_property +ffffffff8197b290 t kvasprintf +ffffffff8197b330 t kasprintf +ffffffff8197b400 t create_in_format_blob +ffffffff8197b5f0 t __setplane_atomic +ffffffff8197b790 t __setplane_internal +ffffffff8197b9a0 t __setplane_check +ffffffff8197c000 T drm_plane_helper_update_primary +ffffffff8197c4b0 t get_connectors_for_crtc +ffffffff8197c5c0 T drm_plane_helper_disable_primary +ffffffff8197c670 T drm_plane_helper_destroy +ffffffff8197c6a0 T drm_plane_helper_atomic_check +ffffffff8197d000 T drm_prime_remove_buf_handle +ffffffff8197d0a0 T drm_prime_init_file_private +ffffffff8197d100 T drm_prime_destroy_file_private +ffffffff8197d160 T drm_gem_dmabuf_export +ffffffff8197d1c0 T drm_gem_dmabuf_release +ffffffff8197d200 T drm_gem_prime_fd_to_handle +ffffffff8197d420 T drm_gem_prime_import +ffffffff8197d480 t drm_prime_add_buf_handle +ffffffff8197d5c0 T drm_prime_fd_to_handle_ioctl +ffffffff8197d5f0 T drm_gem_prime_handle_to_fd +ffffffff8197d820 T drm_prime_handle_to_fd_ioctl +ffffffff8197d890 T drm_gem_map_attach +ffffffff8197d8e0 T drm_gem_map_detach +ffffffff8197d900 T drm_gem_dmabuf_vmap +ffffffff8197d920 T drm_gem_dmabuf_vunmap +ffffffff8197d940 T drm_gem_prime_mmap +ffffffff8197d990 T drm_prime_pages_to_sg +ffffffff8197d9e0 T drm_prime_get_contiguous_size +ffffffff8197da30 T drm_gem_prime_export +ffffffff8197dac0 T drm_gem_prime_import_dev +ffffffff8197db20 T drm_prime_sg_to_page_array +ffffffff8197db70 T drm_prime_sg_to_dma_addr_array +ffffffff8197dbc0 T drm_prime_gem_destroy +ffffffff8197e000 T __drm_puts_coredump +ffffffff8197e0e0 T __drm_printfn_coredump +ffffffff8197e2b0 T __drm_puts_seq_file +ffffffff8197e2e0 T __drm_printfn_seq_file +ffffffff8197e310 T __drm_printfn_info +ffffffff8197e340 T __drm_printfn_debug +ffffffff8197e370 T __drm_printfn_err +ffffffff8197e3b0 T drm_puts +ffffffff8197e3e0 T drm_printf +ffffffff8197e460 T drm_print_bits +ffffffff8197e690 T drm_dev_printk +ffffffff8197e730 T __drm_dev_dbg +ffffffff8197e7c0 T ___drm_dbg +ffffffff8197e850 T __drm_err +ffffffff8197e8e0 T drm_print_regset32 +ffffffff8197f000 T drm_crtc_mode_valid +ffffffff8197f050 T drm_encoder_mode_valid +ffffffff8197f090 T drm_connector_mode_valid +ffffffff8197f110 T drm_kms_helper_poll_enable +ffffffff8197f250 T drm_kms_helper_poll_reschedule +ffffffff8197f2b0 T drm_helper_probe_detect +ffffffff8197f4a0 T drm_helper_probe_single_connector_modes +ffffffff8197fa20 t __drm_helper_update_and_validate +ffffffff8197fdd0 T drm_kms_helper_hotplug_event +ffffffff8197fe10 T drm_kms_helper_connector_hotplug_event +ffffffff8197fe50 T drm_kms_helper_is_poll_worker +ffffffff8197fe80 T drm_kms_helper_poll_disable +ffffffff8197ff50 T drm_kms_helper_poll_init +ffffffff8197ffb0 t output_poll_execute +ffffffff81980200 T drm_kms_helper_poll_fini +ffffffff81980250 T drm_connector_helper_hpd_irq_event +ffffffff81980310 t check_connector_changed +ffffffff819804e0 T drm_helper_hpd_irq_event +ffffffff81980630 T drm_crtc_helper_mode_valid_fixed +ffffffff81980680 T drm_connector_helper_get_modes_from_ddc +ffffffff81980710 T drm_connector_helper_get_modes_fixed +ffffffff81980880 T drm_connector_helper_get_modes +ffffffff819808f0 T drm_connector_helper_tv_get_modes +ffffffff81980b30 t __delayed_work_tick +ffffffff81981000 T drm_property_create +ffffffff819811f0 T drm_property_create_enum +ffffffff819812a0 T drm_property_add_enum +ffffffff819814a0 T drm_property_destroy +ffffffff81981550 T drm_property_create_bitmask +ffffffff81981680 T drm_property_create_range +ffffffff819816f0 T drm_property_create_signed_range +ffffffff81981760 T drm_property_create_object +ffffffff81981800 T drm_property_create_bool +ffffffff81981860 T drm_mode_getproperty_ioctl +ffffffff81981ab0 T drm_property_create_blob +ffffffff81981bf0 t drm_property_free_blob +ffffffff81981c70 T drm_property_blob_put +ffffffff81981cb0 T drm_property_destroy_user_blobs +ffffffff81981d30 T drm_property_blob_get +ffffffff81981d70 T drm_property_lookup_blob +ffffffff81981d90 T drm_property_replace_global_blob +ffffffff81981ee0 T drm_property_replace_blob +ffffffff81981f50 T drm_mode_getblob_ioctl +ffffffff81982010 T drm_mode_createblob_ioctl +ffffffff81982110 T drm_mode_destroyblob_ioctl +ffffffff81982210 T drm_property_change_valid_get +ffffffff81982470 T drm_property_change_valid_put +ffffffff81983000 T drm_rect_intersect +ffffffff81983080 T drm_rect_clip_scaled +ffffffff819832f0 T drm_rect_calc_hscale +ffffffff819833c0 T drm_rect_calc_vscale +ffffffff81983490 T drm_rect_debug_print +ffffffff819835b0 T drm_rect_rotate +ffffffff81983670 T drm_rect_rotate_inv +ffffffff81984000 T drm_self_refresh_helper_update_avg_times +ffffffff81984150 T drm_self_refresh_helper_alter_state +ffffffff819842e0 T drm_self_refresh_helper_init +ffffffff81984470 t drm_self_refresh_helper_entry_work +ffffffff819845d0 T drm_self_refresh_helper_cleanup +ffffffff81984650 t __delayed_work_tick +ffffffff81985000 T drm_suballoc_manager_init +ffffffff81985180 T drm_suballoc_manager_fini +ffffffff81985290 t drm_suballoc_try_free +ffffffff81985380 T drm_suballoc_new +ffffffff81985da0 t drm_suballoc_event +ffffffff81985ee0 T drm_suballoc_free +ffffffff81987000 T drm_syncobj_find +ffffffff81987070 T drm_syncobj_add_point +ffffffff81987180 t syncobj_wait_syncobj_func +ffffffff81987230 t syncobj_eventfd_entry_func +ffffffff81987310 T drm_syncobj_replace_fence +ffffffff819873c0 T drm_syncobj_find_fence +ffffffff81987710 t drm_syncobj_fence_add_wait +ffffffff819877e0 T drm_syncobj_free +ffffffff81987860 T drm_syncobj_create +ffffffff81987a30 T drm_syncobj_get_handle +ffffffff81987b40 T drm_syncobj_get_fd +ffffffff81987b90 T drm_syncobj_open +ffffffff81987bc0 T drm_syncobj_release +ffffffff81987c00 t drm_syncobj_release_handle +ffffffff81987cc0 T drm_syncobj_create_ioctl +ffffffff81987df0 T drm_syncobj_destroy_ioctl +ffffffff81987f30 T drm_syncobj_handle_to_fd_ioctl +ffffffff81988120 T drm_syncobj_fd_to_handle_ioctl +ffffffff819882d0 T drm_syncobj_transfer_ioctl +ffffffff819886b0 T drm_timeout_abs_to_jiffies +ffffffff81988780 T drm_syncobj_wait_ioctl +ffffffff81988900 t drm_syncobj_array_find +ffffffff81988b20 t drm_syncobj_array_free +ffffffff81988c10 T drm_syncobj_timeline_wait_ioctl +ffffffff81988d90 T drm_syncobj_eventfd_ioctl +ffffffff81988dc0 T drm_syncobj_reset_ioctl +ffffffff81988ea0 T drm_syncobj_signal_ioctl +ffffffff81989000 T drm_syncobj_timeline_signal_ioctl +ffffffff81989240 T drm_syncobj_query_ioctl +ffffffff81989450 t drm_syncobj_array_wait_timeout +ffffffff819898b0 t syncobj_wait_fence_func +ffffffff819898d0 t syncobj_eventfd_entry_fence_func +ffffffff8198a000 T drm_vblank_count +ffffffff8198a090 T drm_crtc_accurate_vblank_count +ffffffff8198a1a0 t drm_update_vblank_count +ffffffff8198a5e0 T drm_vblank_disable_and_save +ffffffff8198a730 T drm_vblank_init +ffffffff8198a8b0 t vblank_disable_fn +ffffffff8198a930 t drm_vblank_init_release +ffffffff8198a9c0 T drm_dev_has_vblank +ffffffff8198a9f0 T drm_crtc_vblank_waitqueue +ffffffff8198aa40 T drm_calc_timestamping_constants +ffffffff8198ac60 T drm_crtc_vblank_helper_get_vblank_timestamp_internal +ffffffff8198b1b0 T drm_crtc_vblank_helper_get_vblank_timestamp +ffffffff8198b1d0 T drm_crtc_vblank_count +ffffffff8198b260 T drm_crtc_vblank_count_and_time +ffffffff8198b320 t drm_vblank_count_and_time +ffffffff8198b3d0 T drm_crtc_next_vblank_start +ffffffff8198b520 T drm_crtc_arm_vblank_event +ffffffff8198b600 T drm_crtc_send_vblank_event +ffffffff8198b7b0 t send_vblank_event +ffffffff8198b860 T drm_vblank_get +ffffffff8198b960 t drm_vblank_enable +ffffffff8198bb60 T drm_crtc_vblank_get +ffffffff8198bc60 T drm_vblank_put +ffffffff8198bd90 T drm_crtc_vblank_put +ffffffff8198bdb0 T drm_wait_one_vblank +ffffffff8198c2a0 T drm_crtc_wait_one_vblank +ffffffff8198c2c0 T drm_crtc_vblank_off +ffffffff8198c6b0 T drm_crtc_vblank_reset +ffffffff8198c7e0 T drm_crtc_set_max_vblank_count +ffffffff8198c8c0 T drm_crtc_vblank_on +ffffffff8198ca10 t drm_reset_vblank_timestamp +ffffffff8198cbf0 T drm_crtc_vblank_restore +ffffffff8198cfd0 T drm_legacy_modeset_ctl_ioctl +ffffffff8198d1f0 T drm_wait_vblank_ioctl +ffffffff8198d740 t drm_wait_vblank_reply +ffffffff8198d850 t drm_queue_vblank_event +ffffffff8198db90 T drm_handle_vblank +ffffffff8198de80 t drm_handle_vblank_events +ffffffff8198e110 T drm_crtc_handle_vblank +ffffffff8198e130 T drm_crtc_get_sequence_ioctl +ffffffff8198e300 T drm_crtc_queue_sequence_ioctl +ffffffff8198e5c0 t __get_vblank_counter +ffffffff8198f000 T drm_handle_vblank_works +ffffffff8198f1a0 T drm_vblank_cancel_pending_works +ffffffff8198f2e0 T drm_vblank_work_schedule +ffffffff8198f550 T drm_vblank_work_cancel_sync +ffffffff8198f6a0 T drm_vblank_work_flush +ffffffff8198f7d0 T drm_vblank_work_init +ffffffff8198f840 T drm_vblank_worker_init +ffffffff81990000 T drm_vma_offset_manager_init +ffffffff81990040 T drm_vma_offset_manager_destroy +ffffffff81990060 T drm_vma_offset_lookup_locked +ffffffff819900f0 T drm_vma_offset_add +ffffffff81990180 T drm_vma_offset_remove +ffffffff819901d0 T drm_vma_node_allow +ffffffff819901f0 t vma_node_allow +ffffffff81990310 T drm_vma_node_allow_once +ffffffff81990330 T drm_vma_node_revoke +ffffffff819903b0 T drm_vma_node_is_allowed +ffffffff81991000 T hdmi_avi_infoframe_init +ffffffff81991070 T hdmi_avi_infoframe_check +ffffffff819910c0 T hdmi_avi_infoframe_pack_only +ffffffff819912c0 T hdmi_avi_infoframe_pack +ffffffff81991320 T hdmi_spd_infoframe_init +ffffffff819913e0 T hdmi_spd_infoframe_check +ffffffff81991430 T hdmi_spd_infoframe_pack_only +ffffffff81991570 T hdmi_spd_infoframe_pack +ffffffff819916d0 T hdmi_audio_infoframe_init +ffffffff81991720 T hdmi_audio_infoframe_check +ffffffff81991770 T hdmi_audio_infoframe_pack_only +ffffffff819918d0 T hdmi_audio_infoframe_pack +ffffffff81991920 T hdmi_audio_infoframe_pack_for_dp +ffffffff81991a10 T hdmi_vendor_infoframe_init +ffffffff81991a70 T hdmi_vendor_infoframe_check +ffffffff81991b10 T hdmi_vendor_infoframe_pack_only +ffffffff81991cd0 T hdmi_vendor_infoframe_pack +ffffffff81991d70 T hdmi_drm_infoframe_init +ffffffff81991dd0 T hdmi_drm_infoframe_check +ffffffff81991e20 T hdmi_drm_infoframe_pack_only +ffffffff81992010 T hdmi_drm_infoframe_pack +ffffffff81992060 T hdmi_infoframe_check +ffffffff819921b0 T hdmi_infoframe_pack_only +ffffffff819923d0 T hdmi_infoframe_pack +ffffffff81992540 T hdmi_infoframe_log +ffffffff81993430 T hdmi_drm_infoframe_unpack_only +ffffffff81993510 T hdmi_infoframe_unpack +ffffffff81994000 T list_sort +ffffffff81995000 T radix_tree_lookup +ffffffff819950b0 T radix_tree_iter_find +ffffffff81995180 T radix_tree_delete +ffffffff81995310 T radix_tree_iter_delete +ffffffff81995330 T radix_tree_insert +ffffffff81996000 T sort +ffffffff81996040 t qsort +ffffffff81998000 T drm_dp_dual_mode_read +ffffffff81998110 T drm_dp_dual_mode_write +ffffffff819981f0 T drm_dp_dual_mode_detect +ffffffff81998490 T drm_dp_dual_mode_max_tmds_clock +ffffffff819985b0 T drm_dp_dual_mode_get_tmds_output +ffffffff819986d0 T drm_dp_dual_mode_set_tmds_output +ffffffff81998950 T drm_dp_get_dual_mode_type_name +ffffffff819989c0 T drm_lspcon_get_mode +ffffffff81998be0 T drm_lspcon_set_mode +ffffffff81999000 T drm_dp_channel_eq_ok +ffffffff81999080 T drm_dp_clock_recovery_ok +ffffffff819990f0 T drm_dp_get_adjust_request_voltage +ffffffff81999130 T drm_dp_get_adjust_request_pre_emphasis +ffffffff81999180 T drm_dp_get_adjust_tx_ffe_preset +ffffffff819991c0 T drm_dp_128b132b_lane_channel_eq_done +ffffffff81999240 T drm_dp_128b132b_lane_symbol_locked +ffffffff819992b0 T drm_dp_128b132b_eq_interlane_align_done +ffffffff819992e0 T drm_dp_128b132b_cds_interlane_align_done +ffffffff81999310 T drm_dp_128b132b_link_training_failed +ffffffff81999340 T drm_dp_read_clock_recovery_delay +ffffffff81999450 T drm_dp_read_channel_eq_delay +ffffffff81999550 T drm_dp_128b132b_read_aux_rd_interval +ffffffff81999600 T drm_dp_link_train_clock_recovery_delay +ffffffff81999690 t __8b10b_clock_recovery_delay_us +ffffffff81999710 T drm_dp_link_train_channel_eq_delay +ffffffff81999780 T drm_dp_phy_name +ffffffff819997c0 T drm_dp_lttpr_link_train_clock_recovery_delay +ffffffff819997e0 T drm_dp_lttpr_link_train_channel_eq_delay +ffffffff81999850 T drm_dp_link_rate_to_bw_code +ffffffff819998c0 T drm_dp_bw_code_to_link_rate +ffffffff81999920 T drm_dp_dpcd_probe +ffffffff81999a60 t drm_dp_dpcd_access +ffffffff81999b90 T drm_dp_dpcd_read +ffffffff81999cc0 T drm_dp_dpcd_write +ffffffff81999dd0 T drm_dp_dpcd_read_link_status +ffffffff81999df0 T drm_dp_dpcd_read_phy_link_status +ffffffff81999ef0 T drm_dp_downstream_is_type +ffffffff81999f40 T drm_dp_downstream_is_tmds +ffffffff81999fb0 T drm_dp_send_real_edid_checksum +ffffffff8199a200 T drm_dp_read_dpcd_caps +ffffffff8199a390 T drm_dp_read_downstream_info +ffffffff8199a490 T drm_dp_downstream_max_dotclock +ffffffff8199a4e0 T drm_dp_downstream_max_tmds_clock +ffffffff8199a580 T drm_dp_downstream_min_tmds_clock +ffffffff8199a600 T drm_dp_downstream_max_bpc +ffffffff8199a6a0 T drm_dp_downstream_420_passthrough +ffffffff8199a700 T drm_dp_downstream_444_to_420_conversion +ffffffff8199a760 T drm_dp_downstream_rgb_to_ycbcr_conversion +ffffffff8199a7c0 T drm_dp_downstream_mode +ffffffff8199a850 T drm_dp_downstream_id +ffffffff8199a870 T drm_dp_downstream_debug +ffffffff8199a910 T drm_dp_subconnector_type +ffffffff8199a980 T drm_dp_set_subconnector_property +ffffffff8199a9f0 T drm_dp_read_sink_count_cap +ffffffff8199aa40 T drm_dp_read_sink_count +ffffffff8199aaa0 T drm_dp_remote_aux_init +ffffffff8199aad0 t drm_dp_aux_crc_work +ffffffff8199ac40 T drm_dp_aux_init +ffffffff8199acf0 T drm_dp_aux_register +ffffffff8199ae10 T drm_dp_aux_unregister +ffffffff8199ae40 T drm_dp_psr_setup_time +ffffffff8199ae90 T drm_dp_start_crc +ffffffff8199af40 T drm_dp_stop_crc +ffffffff8199afd0 T drm_dp_read_desc +ffffffff8199b190 T drm_dp_dsc_sink_max_slice_count +ffffffff8199b220 T drm_dp_dsc_sink_line_buf_depth +ffffffff8199b260 T drm_dp_dsc_sink_supported_input_bpcs +ffffffff8199b2d0 T drm_dp_read_lttpr_common_caps +ffffffff8199b390 T drm_dp_read_lttpr_phy_caps +ffffffff8199b450 T drm_dp_lttpr_count +ffffffff8199b4e0 T drm_dp_lttpr_max_link_rate +ffffffff8199b540 T drm_dp_lttpr_max_lane_count +ffffffff8199b570 T drm_dp_lttpr_voltage_swing_level_3_supported +ffffffff8199b5a0 T drm_dp_lttpr_pre_emphasis_level_3_supported +ffffffff8199b5d0 T drm_dp_get_phy_test_pattern +ffffffff8199b6f0 T drm_dp_set_phy_test_pattern +ffffffff8199b7b0 T drm_dp_vsc_sdp_log +ffffffff8199bad0 T drm_dp_get_pcon_max_frl_bw +ffffffff8199bb20 T drm_dp_pcon_frl_prepare +ffffffff8199bb70 T drm_dp_pcon_is_frl_ready +ffffffff8199bbd0 T drm_dp_pcon_frl_configure_1 +ffffffff8199bcd0 T drm_dp_pcon_frl_configure_2 +ffffffff8199bd30 T drm_dp_pcon_reset_frl_config +ffffffff8199bd80 T drm_dp_pcon_frl_enable +ffffffff8199be40 T drm_dp_pcon_hdmi_link_active +ffffffff8199be90 T drm_dp_pcon_hdmi_link_mode +ffffffff8199bf00 T drm_dp_pcon_hdmi_frl_link_error_count +ffffffff8199bff0 T drm_dp_pcon_enc_is_dsc_1_2 +ffffffff8199c020 T drm_dp_pcon_dsc_max_slices +ffffffff8199c0b0 T drm_dp_pcon_dsc_max_slice_width +ffffffff8199c0e0 T drm_dp_pcon_dsc_bpp_incr +ffffffff8199c120 T drm_dp_pcon_pps_default +ffffffff8199c1a0 T drm_dp_pcon_pps_override_buf +ffffffff8199c240 T drm_dp_pcon_pps_override_param +ffffffff8199c310 T drm_dp_pcon_convert_rgb_to_ycbcr +ffffffff8199c3b0 T drm_edp_backlight_set_level +ffffffff8199c480 T drm_edp_backlight_enable +ffffffff8199c690 t drm_edp_backlight_set_enable +ffffffff8199c7c0 T drm_edp_backlight_disable +ffffffff8199c800 T drm_edp_backlight_init +ffffffff8199cd60 T drm_panel_dp_aux_backlight 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drm_dp_send_power_updown_phy +ffffffff8199f760 t drm_dp_mst_topology_put_port +ffffffff8199f880 t drm_dp_mst_wait_tx_reply +ffffffff8199fc20 T drm_dp_send_query_stream_enc_status +ffffffff8199fee0 T drm_dp_add_payload_part1 +ffffffff819a0090 T drm_dp_remove_payload +ffffffff819a0230 T drm_dp_add_payload_part2 +ffffffff819a03e0 T drm_dp_get_vc_payload_bw +ffffffff819a0480 T drm_dp_read_mst_cap +ffffffff819a04e0 T drm_dp_mst_topology_mgr_set_mst +ffffffff819a0790 t drm_dp_dpcd_write_payload +ffffffff819a0930 t drm_dp_mst_topology_put_mstb +ffffffff819a0a30 T drm_dp_mst_topology_mgr_suspend +ffffffff819a0af0 t drm_dp_mst_topology_mgr_invalidate_mstb +ffffffff819a0b60 T drm_dp_mst_topology_mgr_resume +ffffffff819a0da0 T drm_dp_mst_hpd_irq_handle_event +ffffffff819a1d10 T drm_dp_mst_hpd_irq_send_new_request +ffffffff819a1d90 T drm_dp_mst_detect_port +ffffffff819a1ef0 T drm_dp_mst_edid_read +ffffffff819a1ff0 T drm_dp_mst_get_edid +ffffffff819a2050 T drm_dp_atomic_find_time_slots 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intel_atomic_state_clear +ffffffff819e36e0 T intel_atomic_get_crtc_state +ffffffff819e4000 T intel_plane_alloc +ffffffff819e40c0 T intel_plane_free +ffffffff819e4100 T intel_plane_destroy_state +ffffffff819e41d0 T intel_plane_duplicate_state +ffffffff819e4280 T intel_adjusted_rate +ffffffff819e4300 T intel_plane_pixel_rate +ffffffff819e4390 T intel_plane_data_rate +ffffffff819e4450 T intel_plane_calc_min_cdclk +ffffffff819e45b0 T intel_plane_copy_uapi_to_hw_state +ffffffff819e4720 T intel_plane_copy_hw_state +ffffffff819e4810 T intel_plane_set_invisible +ffffffff819e4910 T intel_plane_atomic_check_with_state +ffffffff819e5560 T intel_plane_atomic_check +ffffffff819e56c0 T intel_plane_update_noarm +ffffffff819e5700 T intel_plane_update_arm +ffffffff819e5740 T intel_plane_disable_arm +ffffffff819e5760 T intel_crtc_planes_update_noarm +ffffffff819e5880 T intel_crtc_planes_update_arm +ffffffff819e5c70 T intel_atomic_plane_check_clipping +ffffffff819e5ed0 T intel_plane_check_src_coordinates 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vlv_get_backlight +ffffffff819ec3f0 t vlv_set_backlight +ffffffff819ec470 t vlv_disable_backlight +ffffffff819ec530 t vlv_enable_backlight +ffffffff819ec6d0 t vlv_hz_to_pwm +ffffffff819ec770 t i965_setup_backlight +ffffffff819ec9b0 t i9xx_get_backlight +ffffffff819eca50 t i9xx_set_backlight +ffffffff819ecb90 t i965_disable_backlight +ffffffff819ecc40 t i965_enable_backlight +ffffffff819ecdf0 t i965_hz_to_pwm +ffffffff819ece50 t i9xx_setup_backlight +ffffffff819ed190 t i9xx_disable_backlight +ffffffff819ed200 t i9xx_enable_backlight +ffffffff819ed3b0 t i9xx_hz_to_pwm +ffffffff819ed410 t intel_pwm_setup_backlight +ffffffff819ed520 t intel_pwm_get_backlight +ffffffff819ed5f0 t intel_pwm_set_backlight +ffffffff819ed6b0 t intel_pwm_disable_backlight +ffffffff819ed770 t intel_pwm_enable_backlight +ffffffff819ee000 T intel_bios_encoder_port +ffffffff819ee080 t dvo_port_to_port +ffffffff819ee260 T intel_bios_dp_max_link_rate +ffffffff819ee2e0 T intel_bios_dp_max_lane_count +ffffffff819ee330 T intel_bios_encoder_supports_dvi +ffffffff819ee360 T intel_bios_encoder_supports_hdmi +ffffffff819ee3a0 T intel_bios_encoder_supports_dp +ffffffff819ee3d0 T intel_bios_encoder_supports_edp +ffffffff819ee410 T intel_bios_encoder_supports_dsi +ffffffff819ee440 T intel_bios_encoder_is_lspcon +ffffffff819ee490 T intel_bios_hdmi_level_shift +ffffffff819ee4f0 T intel_bios_hdmi_max_tmds_clock +ffffffff819ee580 T intel_bios_is_valid_vbt +ffffffff819ee670 T intel_bios_init +ffffffff819f0500 T intel_bios_init_panel_early +ffffffff819f0520 t intel_bios_init_panel +ffffffff819f25a0 T intel_bios_init_panel_late +ffffffff819f25c0 T intel_bios_driver_remove +ffffffff819f26b0 T intel_bios_fini_panel +ffffffff819f2790 T intel_bios_is_tv_present +ffffffff819f2810 T intel_bios_is_lvds_present +ffffffff819f28c0 T intel_bios_is_port_present +ffffffff819f2990 T intel_bios_encoder_supports_dp_dual_mode +ffffffff819f2a00 T intel_bios_is_dsi_present +ffffffff819f2ad0 T intel_bios_get_dsc_params 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intel_cdclk_init +ffffffff819f87f0 T intel_modeset_calc_cdclk +ffffffff819f8e20 t intel_cdclk_can_crawl +ffffffff819f8eb0 T intel_update_max_cdclk +ffffffff819f9210 T intel_update_cdclk +ffffffff819f92b0 T intel_read_rawclk +ffffffff819f9430 t i9xx_hrawclk +ffffffff819f94e0 T intel_cdclk_debugfs_register +ffffffff819f9510 T intel_init_cdclk_hooks +ffffffff819f9930 t bxt_set_cdclk +ffffffff819f9fa0 t _bxt_set_cdclk +ffffffff819fa750 t skl_set_cdclk +ffffffff819fad50 t intel_cdclk_duplicate_state +ffffffff819fadd0 t intel_cdclk_destroy_state +ffffffff819fadf0 t bxt_get_cdclk +ffffffff819fb020 t bxt_modeset_calc_cdclk +ffffffff819fb470 t tgl_calc_voltage_level +ffffffff819fb4c0 t intel_compute_min_cdclk +ffffffff819fb6c0 t rplu_calc_voltage_level +ffffffff819fb710 t ehl_calc_voltage_level +ffffffff819fb760 t icl_calc_voltage_level +ffffffff819fb7b0 t bxt_calc_voltage_level +ffffffff819fb800 t skl_get_cdclk +ffffffff819fba10 t skl_modeset_calc_cdclk +ffffffff819fbc20 t bdw_get_cdclk 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intel_color_post_update +ffffffff819fe100 T intel_color_prepare_commit +ffffffff819fe130 T intel_color_cleanup_commit +ffffffff819fe180 T intel_color_check +ffffffff819fe1a0 T intel_color_get_config +ffffffff819fe220 T intel_color_lut_equal +ffffffff819fe280 T intel_color_assert_luts +ffffffff819fe570 T intel_color_crtc_init +ffffffff819fe5e0 T intel_color_init +ffffffff819fe710 T intel_color_init_hooks +ffffffff819fe840 t chv_color_check +ffffffff819fed50 t i9xx_color_commit_arm +ffffffff819fed60 t chv_load_luts +ffffffff819ff160 t chv_read_luts +ffffffff819ff3e0 t chv_lut_equal +ffffffff819ff710 t chv_read_csc +ffffffff819ff830 t intel_color_add_affected_planes +ffffffff819ff9a0 t _check_luts +ffffffff819ffb00 t i965_load_luts +ffffffff819ffe70 t i965_read_luts +ffffffff81a00240 t vlv_color_check +ffffffff81a006e0 t vlv_load_luts +ffffffff81a00890 t i965_lut_equal +ffffffff81a00a70 t vlv_read_csc +ffffffff81a00c50 t i9xx_color_check +ffffffff81a00ed0 t i9xx_load_luts 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ilk_csc_limited_range +ffffffff81a05290 t ilk_assign_csc +ffffffff81a05590 t ivb_color_check +ffffffff81a05be0 t bdw_load_luts +ffffffff81a05dc0 t bdw_read_luts +ffffffff81a05fb0 t ivb_lut_equal +ffffffff81a06370 t ilk_assign_luts +ffffffff81a06590 t ilk_color_commit_noarm +ffffffff81a065e0 t hsw_color_commit_arm +ffffffff81a06690 t ilk_read_csc +ffffffff81a066e0 t ivb_load_luts +ffffffff81a068c0 t ivb_read_luts +ffffffff81a06d70 t ivb_load_lut_10 +ffffffff81a06f70 t ilk_color_commit_arm +ffffffff81a06ff0 t ilk_color_check +ffffffff81a07250 t ilk_load_luts +ffffffff81a074e0 t ilk_read_luts +ffffffff81a07740 t ilk_lut_equal +ffffffff81a08000 T intel_combo_phy_power_up_lanes +ffffffff81a08120 T intel_combo_phy_init +ffffffff81a085c0 T intel_combo_phy_uninit +ffffffff81a08790 t icl_combo_phy_verify_state +ffffffff81a09000 T intel_connector_init +ffffffff81a09070 T intel_connector_alloc +ffffffff81a09100 T intel_connector_free +ffffffff81a09140 T intel_connector_destroy +ffffffff81a091a0 T intel_connector_register +ffffffff81a091b0 T intel_connector_unregister +ffffffff81a091c0 T intel_connector_attach_encoder +ffffffff81a091e0 T intel_connector_get_hw_state +ffffffff81a09230 T intel_connector_get_pipe +ffffffff81a092f0 T intel_connector_update_modes +ffffffff81a09320 T intel_ddc_get_modes +ffffffff81a09390 T intel_attach_force_audio_property +ffffffff81a09430 T intel_attach_broadcast_rgb_property +ffffffff81a094d0 T intel_attach_aspect_ratio_property +ffffffff81a09530 T intel_attach_hdmi_colorspace_property +ffffffff81a09580 T intel_attach_dp_colorspace_property +ffffffff81a095d0 T intel_attach_scaling_mode_property +ffffffff81a0a000 T intel_crt_port_enabled +ffffffff81a0a080 T intel_crt_reset +ffffffff81a0a160 T intel_crt_init +ffffffff81a0a590 t hsw_crt_get_config +ffffffff81a0a640 t hsw_crt_compute_config +ffffffff81a0a730 t hsw_pre_pll_enable_crt +ffffffff81a0a7a0 t hsw_pre_enable_crt +ffffffff81a0a840 t hsw_enable_crt +ffffffff81a0a9e0 t hsw_disable_crt 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i9xx_cursor_update_arm +ffffffff81a11b10 t i9xx_cursor_disable_arm +ffffffff81a11b30 t i9xx_cursor_get_hw_state +ffffffff81a11c20 t i9xx_check_cursor +ffffffff81a11ea0 t intel_check_cursor +ffffffff81a120b0 t intel_legacy_cursor_update +ffffffff81a12470 t intel_cursor_format_mod_supported +ffffffff81a13000 T intel_is_c10phy +ffffffff81a13040 T intel_cx0_phy_set_signal_levels +ffffffff81a13630 t intel_cx0_rmw +ffffffff81a13720 T intel_c10pll_readout_hw_state +ffffffff81a138b0 T intel_c10pll_dump_hw_state +ffffffff81a13b30 T intel_cx0_phy_check_hdmi_link_rate +ffffffff81a13ca0 T intel_cx0pll_calc_state +ffffffff81a140b0 T intel_c20pll_readout_hw_state +ffffffff81a145d0 t intel_c20_sram_read +ffffffff81a146e0 T intel_c20pll_dump_hw_state +ffffffff81a14a90 T intel_c10pll_calc_port_clock +ffffffff81a14b70 T intel_c20pll_calc_port_clock +ffffffff81a14c70 T intel_mtl_tbt_calc_port_clock +ffffffff81a14dd0 T intel_mtl_pll_enable +ffffffff81a165d0 T intel_mtl_pll_disable +ffffffff81a16a40 T intel_mtl_port_pll_type +ffffffff81a16ad0 T intel_c10pll_state_verify +ffffffff81a16dc0 t __intel_cx0_read +ffffffff81a17150 t __intel_cx0_write +ffffffff81a174a0 t intel_cx0_bus_reset +ffffffff81a175d0 t intel_cx0_wait_for_ack +ffffffff81a17750 t intel_cx0_powerdown_change_sequence +ffffffff81a179b0 t intel_c20_sram_write +ffffffff81a18000 T hsw_prepare_dp_ddi_buffers +ffffffff81a181a0 T intel_wait_ddi_buf_idle +ffffffff81a183a0 T intel_ddi_set_dp_msa +ffffffff81a18570 T intel_ddi_enable_transcoder_func +ffffffff81a18650 t intel_ddi_transcoder_func_reg_val_get +ffffffff81a18900 T intel_ddi_disable_transcoder_func +ffffffff81a18af0 T intel_ddi_toggle_hdcp_bits +ffffffff81a18c10 T intel_ddi_connector_get_hw_state +ffffffff81a18d60 T intel_ddi_get_hw_state +ffffffff81a18dd0 t intel_ddi_get_encoder_pipes +ffffffff81a19220 T intel_ddi_enable_transcoder_clock +ffffffff81a192e0 T intel_ddi_disable_transcoder_clock +ffffffff81a19350 T intel_ddi_level +ffffffff81a19530 T icl_ddi_combo_get_pll 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intel_ddi_tc_encoder_suspend_complete +ffffffff81a21920 t intel_ddi_tc_encoder_shutdown_complete +ffffffff81a21960 t lpt_digital_port_connected +ffffffff81a219d0 t bdw_digital_port_connected +ffffffff81a21a40 t hsw_digital_port_connected +ffffffff81a21ab0 t intel_ddi_init_dp_connector +ffffffff81a21b90 t intel_ddi_init_hdmi_connector +ffffffff81a21c00 t intel_ddi_encoder_reset +ffffffff81a21ce0 t intel_ddi_encoder_destroy +ffffffff81a21d90 t intel_ddi_encoder_late_register +ffffffff81a21df0 t mtl_ddi_enable_d2d +ffffffff81a21fb0 t intel_wait_ddi_buf_active +ffffffff81a222c0 t intel_ddi_main_link_aux_domain +ffffffff81a223b0 t icl_program_mg_dp_mode +ffffffff81a22680 t intel_ddi_init_dp_buf_reg +ffffffff81a22880 t intel_disable_ddi_buf +ffffffff81a22a30 t mtl_disable_ddi_buf +ffffffff81a22e50 t intel_ddi_disable_fec_state +ffffffff81a22fa0 t mtl_ddi_prepare_link_retrain +ffffffff81a232e0 t intel_ddi_prepare_link_retrain +ffffffff81a237e0 t intel_ddi_set_link_train +ffffffff81a23930 t intel_ddi_set_idle_link_train +ffffffff81a23b00 t intel_ddi_dp_voltage_max +ffffffff81a23bc0 t intel_ddi_dp_preemph_max +ffffffff81a24000 T is_hobl_buf_trans +ffffffff81a24040 T intel_ddi_buf_trans_init +ffffffff81a24300 t mtl_get_cx0_buf_trans +ffffffff81a243e0 t dg2_get_snps_buf_trans +ffffffff81a24450 t adlp_get_combo_buf_trans +ffffffff81a24570 t adlp_get_dkl_buf_trans +ffffffff81a245d0 t adls_get_combo_buf_trans +ffffffff81a246f0 t rkl_get_combo_buf_trans +ffffffff81a24810 t dg1_get_combo_buf_trans +ffffffff81a24930 t tgl_get_combo_buf_trans +ffffffff81a24a70 t tgl_get_dkl_buf_trans +ffffffff81a24ad0 t jsl_get_combo_buf_trans +ffffffff81a24b70 t ehl_get_combo_buf_trans +ffffffff81a24c10 t icl_get_combo_buf_trans +ffffffff81a24cc0 t icl_get_mg_buf_trans +ffffffff81a24d20 t bxt_get_buf_trans +ffffffff81a24da0 t kbl_y_get_buf_trans +ffffffff81a24e40 t kbl_u_get_buf_trans +ffffffff81a24ee0 t kbl_get_buf_trans +ffffffff81a24f80 t skl_y_get_buf_trans +ffffffff81a25020 t skl_u_get_buf_trans +ffffffff81a250c0 t skl_get_buf_trans +ffffffff81a25160 t bdw_get_buf_trans +ffffffff81a251f0 t hsw_get_buf_trans +ffffffff81a26000 T vlv_get_hpll_vco +ffffffff81a26050 T vlv_get_cck_clock +ffffffff81a26100 T vlv_get_cck_clock_hpll +ffffffff81a26200 T intel_update_czclk +ffffffff81a26280 T is_trans_port_sync_master +ffffffff81a262b0 T is_trans_port_sync_mode +ffffffff81a262f0 T intel_crtc_bigjoiner_slave_pipes +ffffffff81a26350 T intel_crtc_is_bigjoiner_slave +ffffffff81a263b0 T intel_crtc_is_bigjoiner_master +ffffffff81a26410 T intel_master_crtc +ffffffff81a264a0 T assert_transcoder +ffffffff81a26660 t transcoder_name +ffffffff81a266a0 T vlv_wait_port_ready +ffffffff81a267f0 T intel_enable_transcoder +ffffffff81a26a50 t assert_planes_disabled +ffffffff81a26b80 T intel_disable_transcoder +ffffffff81a26da0 T intel_rotation_info_size +ffffffff81a26df0 T intel_remapped_info_size +ffffffff81a26f20 T intel_plane_uses_fence +ffffffff81a26f70 T intel_fb_xy_to_linear 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intel_zero_m_n +ffffffff81a283a0 T intel_set_m_n +ffffffff81a28460 T intel_cpu_transcoder_has_m2_n2 +ffffffff81a284c0 T intel_cpu_transcoder_set_m1_n1 +ffffffff81a28670 T intel_cpu_transcoder_set_m2_n2 +ffffffff81a287d0 T i9xx_set_pipeconf +ffffffff81a28980 T ilk_set_pipeconf +ffffffff81a28b50 T bdw_get_pipe_misc_bpp +ffffffff81a28c20 T ilk_get_lanes_required +ffffffff81a28c80 T intel_get_m_n +ffffffff81a28d90 T intel_cpu_transcoder_get_m1_n1 +ffffffff81a28f20 T intel_cpu_transcoder_get_m2_n2 +ffffffff81a29080 T intel_crtc_get_pipe_config +ffffffff81a290f0 T i9xx_crtc_clock_get +ffffffff81a29380 T intel_dotclock_calculate +ffffffff81a293e0 T intel_crtc_dotclock +ffffffff81a294b0 T intel_encoder_current_mode +ffffffff81a29660 T intel_fuzzy_clock_check +ffffffff81a296b0 T intel_pipe_config_compare +ffffffff81a2ca00 t pipe_config_mismatch +ffffffff81a2caf0 t pipe_config_infoframe_mismatch +ffffffff81a2cc90 T intel_modeset_all_pipes +ffffffff81a2cea0 T intel_atomic_add_affected_planes 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i9xx_get_pipe_config +ffffffff81a382b0 t valleyview_crtc_enable +ffffffff81a38710 t i9xx_crtc_disable +ffffffff81a38ab0 t i9xx_pfit_enable +ffffffff81a38c20 t i9xx_crtc_enable +ffffffff81a39000 T intel_display_device_probe +ffffffff81a390f0 T intel_display_device_info_runtime_init +ffffffff81a39750 T intel_display_device_info_print +ffffffff81a3a000 T intel_display_driver_probe_defer +ffffffff81a3a030 T intel_display_driver_init_hw +ffffffff81a3a0f0 T intel_display_driver_early_probe +ffffffff81a3a170 T intel_display_driver_probe_noirq +ffffffff81a3a450 T intel_display_driver_probe_nogem +ffffffff81a3a760 T intel_display_driver_probe +ffffffff81a3a800 T intel_display_driver_register +ffffffff81a3a860 T intel_display_driver_remove +ffffffff81a3a910 T intel_display_driver_remove_noirq +ffffffff81a3a9c0 T intel_display_driver_remove_nogem +ffffffff81a3aa00 T intel_display_driver_unregister +ffffffff81a3aa80 T intel_display_driver_suspend +ffffffff81a3ab30 T __intel_display_driver_resume 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gen8_irq_power_well_pre_disable +ffffffff81a3f600 T valleyview_enable_display_irqs +ffffffff81a3f720 T valleyview_disable_display_irqs +ffffffff81a3f830 T ilk_de_irq_postinstall +ffffffff81a3f940 T gen8_de_irq_postinstall +ffffffff81a3fdb0 T gen11_de_irq_postinstall +ffffffff81a3fe20 T dg1_de_irq_postinstall +ffffffff81a3fe90 T intel_display_irq_init +ffffffff81a40000 T intel_display_power_domain_str +ffffffff81a40060 T __intel_display_power_is_enabled +ffffffff81a40120 T intel_display_power_is_enabled +ffffffff81a40240 T intel_display_power_set_target_dc_state +ffffffff81a40360 T intel_display_power_get +ffffffff81a403e0 t __intel_display_power_get_domain +ffffffff81a405d0 T intel_display_power_get_if_enabled +ffffffff81a40700 T __intel_display_power_put_async +ffffffff81a408f0 t __intel_display_power_put_domain +ffffffff81a40a60 T intel_display_power_flush_work +ffffffff81a40b80 t release_async_put_domains +ffffffff81a40c70 T intel_display_power_put_unchecked +ffffffff81a40cd0 T intel_display_power_get_in_set +ffffffff81a40db0 T intel_display_power_get_in_set_if_enabled +ffffffff81a40e60 T intel_display_power_put_mask_in_set +ffffffff81a40f30 T intel_power_domains_init +ffffffff81a41180 t intel_display_power_put_async_work +ffffffff81a413f0 T intel_power_domains_cleanup +ffffffff81a41410 T gen9_dbuf_slices_update +ffffffff81a41620 T intel_power_domains_init_hw +ffffffff81a41b20 t icl_display_core_init +ffffffff81a42320 t bxt_display_core_init +ffffffff81a42470 t vlv_cmnlane_wa +ffffffff81a42540 t assert_ved_power_gated +ffffffff81a425f0 t hsw_assert_cdclk +ffffffff81a42700 t intel_pch_reset_handshake +ffffffff81a427b0 T intel_power_domains_driver_remove +ffffffff81a428a0 T intel_power_domains_sanitize_state +ffffffff81a42990 T intel_power_domains_enable +ffffffff81a429f0 T intel_power_domains_disable +ffffffff81a42aa0 T intel_power_domains_suspend +ffffffff81a42c50 t icl_display_core_uninit +ffffffff81a42d60 t bxt_display_core_uninit +ffffffff81a42e20 T intel_power_domains_resume +ffffffff81a42ef0 T intel_display_power_suspend_late +ffffffff81a42fd0 t hsw_enable_pc8 +ffffffff81a43c80 T intel_display_power_resume_early +ffffffff81a43d70 t hsw_disable_pc8 +ffffffff81a44190 T intel_display_power_suspend +ffffffff81a44210 T intel_display_power_resume +ffffffff81a442f0 T intel_display_power_debug +ffffffff81a443b0 T intel_display_power_ddi_io_domain +ffffffff81a444a0 T intel_display_power_ddi_lanes_domain +ffffffff81a44590 T intel_display_power_aux_io_domain +ffffffff81a446a0 T intel_display_power_legacy_aux_domain +ffffffff81a447b0 T intel_display_power_tbt_aux_domain +ffffffff81a448c0 t __delayed_work_tick +ffffffff81a45000 T intel_display_power_map_init +ffffffff81a45180 t __set_power_wells +ffffffff81a45560 T intel_display_power_map_cleanup +ffffffff81a46000 T lookup_power_well +ffffffff81a460c0 T intel_power_well_enable +ffffffff81a46150 T intel_power_well_name +ffffffff81a46190 T intel_power_well_disable +ffffffff81a46200 T intel_power_well_sync_hw +ffffffff81a46270 T intel_power_well_get +ffffffff81a46310 T intel_power_well_put +ffffffff81a46410 T intel_power_well_is_enabled +ffffffff81a46430 T intel_power_well_is_enabled_cached +ffffffff81a46460 T intel_display_power_well_is_enabled +ffffffff81a46510 T intel_power_well_is_always_on +ffffffff81a46550 T intel_power_well_domains +ffffffff81a46580 T intel_power_well_refcount +ffffffff81a465b0 T gen9_sanitize_dc_state +ffffffff81a46680 T gen9_set_dc_state +ffffffff81a469e0 T gen9_enable_dc5 +ffffffff81a46c40 T skl_enable_dc6 +ffffffff81a46da0 T bxt_enable_dc9 +ffffffff81a46f50 T bxt_disable_dc9 +ffffffff81a47040 T gen9_disable_dc_states +ffffffff81a47410 T chv_phy_powergate_ch +ffffffff81a47520 t assert_chv_phy_status +ffffffff81a478d0 T chv_phy_powergate_lanes +ffffffff81a47b30 t i9xx_power_well_sync_hw_noop +ffffffff81a47b60 t i9xx_always_on_power_well_noop +ffffffff81a47b90 t i9xx_always_on_power_well_enabled +ffffffff81a47bc0 t chv_pipe_power_well_sync_hw +ffffffff81a47bf0 t chv_pipe_power_well_enable +ffffffff81a47c20 t chv_pipe_power_well_disable +ffffffff81a47c80 t chv_pipe_power_well_enabled +ffffffff81a47d80 t chv_dpio_cmn_power_well_enable +ffffffff81a47f90 t chv_dpio_cmn_power_well_disable +ffffffff81a480c0 t vlv_power_well_enabled +ffffffff81a481e0 t i830_pipes_power_well_sync_hw +ffffffff81a482d0 t i830_pipes_power_well_enable +ffffffff81a48390 t i830_pipes_power_well_disable +ffffffff81a483c0 t i830_pipes_power_well_enabled +ffffffff81a48460 t hsw_power_well_sync_hw +ffffffff81a48550 t hsw_power_well_enable +ffffffff81a487d0 t hsw_power_well_disable +ffffffff81a48890 t hsw_power_well_enabled +ffffffff81a48970 t gen9_dc_off_power_well_enable +ffffffff81a48980 t gen9_dc_off_power_well_disable +ffffffff81a48a20 t gen9_dc_off_power_well_enabled +ffffffff81a48ab0 t bxt_dpio_cmn_power_well_enable +ffffffff81a48ae0 t bxt_dpio_cmn_power_well_disable +ffffffff81a48b10 t bxt_dpio_cmn_power_well_enabled +ffffffff81a48b40 t vlv_display_power_well_enable +ffffffff81a48b70 t vlv_display_power_well_disable +ffffffff81a48be0 t vlv_dpio_cmn_power_well_enable +ffffffff81a48c60 t vlv_dpio_cmn_power_well_disable +ffffffff81a48d60 t vlv_power_well_enable +ffffffff81a48d80 t vlv_power_well_disable +ffffffff81a48da0 t icl_aux_power_well_enable +ffffffff81a49430 t icl_aux_power_well_disable +ffffffff81a496c0 t tgl_tc_cold_off_power_well_sync_hw +ffffffff81a496e0 t tgl_tc_cold_off_power_well_enable +ffffffff81a49700 t tgl_tc_cold_off_power_well_disable +ffffffff81a49720 t tgl_tc_cold_off_power_well_is_enabled +ffffffff81a49750 t xelpdp_aux_power_well_enable +ffffffff81a49820 t xelpdp_aux_power_well_disable +ffffffff81a498f0 t xelpdp_aux_power_well_enabled +ffffffff81a499a0 t chv_set_pipe_power_well +ffffffff81a49ba0 t vlv_display_power_well_init +ffffffff81a49f00 t vlv_set_power_well +ffffffff81a4a120 t hsw_wait_for_power_well_enable +ffffffff81a4a270 t hsw_wait_for_power_well_disable +ffffffff81a4a540 t tgl_tc_cold_request +ffffffff81a4b000 T intel_display_reset_prepare +ffffffff81a4b1e0 T intel_display_reset_finish +ffffffff81a4c000 T intel_display_rps_boost_after_vblank +ffffffff81a4c110 t do_rps_boost +ffffffff81a4c1c0 T intel_display_rps_mark_interactive +ffffffff81a4d000 T intel_dkl_phy_init +ffffffff81a4d020 T intel_dkl_phy_read +ffffffff81a4d150 T intel_dkl_phy_write +ffffffff81a4d260 T intel_dkl_phy_rmw +ffffffff81a4d390 T intel_dkl_phy_posting_read +ffffffff81a4e000 T intel_dmc_has_payload +ffffffff81a4e050 T intel_dmc_enable_pipe +ffffffff81a4e160 T intel_dmc_disable_pipe +ffffffff81a4e270 T intel_dmc_load_program +ffffffff81a4eaa0 t pipedmc_clock_gating_wa +ffffffff81a4ec90 T intel_dmc_disable_program +ffffffff81a4eec0 T assert_dmc_loaded +ffffffff81a4f040 T intel_dmc_init +ffffffff81a4f300 t dmc_load_work_fn +ffffffff81a4fc10 T intel_dmc_suspend +ffffffff81a4fca0 T intel_dmc_resume +ffffffff81a4fd40 T intel_dmc_fini +ffffffff81a4fe90 T intel_dmc_print_error_state +ffffffff81a4ff90 T intel_dmc_debugfs_register +ffffffff81a50000 T intel_dp_is_edp +ffffffff81a50030 T intel_dp_is_uhbr +ffffffff81a50070 T intel_dp_max_lane_count +ffffffff81a500e0 T intel_dp_link_required +ffffffff81a50120 T intel_dp_max_data_rate +ffffffff81a50180 T intel_dp_can_bigjoiner +ffffffff81a501d0 T intel_dp_get_link_train_fallback_values +ffffffff81a50580 T intel_dp_mode_to_fec_clock +ffffffff81a505d0 T intel_dp_dsc_nearest_valid_bpp +ffffffff81a506d0 T intel_dp_dsc_get_output_bpp +ffffffff81a507f0 T intel_dp_dsc_get_slice_count +ffffffff81a50980 T intel_dp_min_bpp +ffffffff81a509c0 T intel_dp_need_bigjoiner +ffffffff81a50a20 T intel_dp_source_supports_tps3 +ffffffff81a50a70 T intel_dp_source_supports_tps4 +ffffffff81a50ab0 T intel_dp_max_link_rate +ffffffff81a50b60 T intel_dp_rate_select +ffffffff81a50c00 T intel_dp_compute_rate +ffffffff81a50cd0 T intel_dp_has_hdmi_sink +ffffffff81a50d10 T intel_dp_adjust_compliance_config +ffffffff81a50e50 T intel_dp_dsc_compute_bpp +ffffffff81a50f00 T intel_dp_dsc_compute_config +ffffffff81a515d0 T intel_dp_limited_color_range +ffffffff81a51640 T intel_dp_compute_psr_vsc_sdp +ffffffff81a516c0 T intel_dp_needs_vsc_sdp +ffffffff81a51710 t intel_dp_compute_vsc_colorimetry +ffffffff81a51890 T intel_dp_compute_config +ffffffff81a51ce0 t intel_dp_compute_output_format +ffffffff81a51f10 t intel_dp_audio_compute_config +ffffffff81a51ff0 t intel_dp_drrs_compute_config +ffffffff81a52190 t intel_dp_compute_vsc_sdp +ffffffff81a52230 t intel_dp_compute_hdr_metadata_infoframe_sdp +ffffffff81a522c0 T intel_dp_set_link_params +ffffffff81a52300 T intel_edp_backlight_on +ffffffff81a523a0 T intel_edp_backlight_off +ffffffff81a52430 T intel_dp_sink_set_decompression_state +ffffffff81a524d0 T intel_dp_wait_source_oui +ffffffff81a525c0 T intel_dp_set_power +ffffffff81a527e0 T intel_dp_sync_state +ffffffff81a52860 t intel_dp_get_dpcd +ffffffff81a529c0 t intel_dp_reset_max_link_params +ffffffff81a52ac0 T intel_dp_initial_fastset_check +ffffffff81a52bf0 T intel_dp_check_frl_training +ffffffff81a531a0 T intel_dp_pcon_dsc_configure +ffffffff81a53390 T intel_dp_configure_protocol_converter +ffffffff81a53570 T intel_dp_get_colorimetry_status +ffffffff81a535d0 T intel_edp_fixup_vbt_bpp +ffffffff81a53660 T intel_write_dp_vsc_sdp +ffffffff81a53800 T intel_dp_set_infoframes +ffffffff81a53920 t intel_write_dp_sdp +ffffffff81a53c00 T intel_read_dp_sdp +ffffffff81a53f20 T intel_dp_get_active_pipes +ffffffff81a54140 T intel_dp_retrain_link +ffffffff81a543f0 t intel_dp_needs_link_retrain +ffffffff81a54570 T intel_dp_phy_test +ffffffff81a54c20 T intel_digital_port_connected +ffffffff81a54cd0 T intel_dp_encoder_flush_work +ffffffff81a54d30 T intel_dp_encoder_suspend +ffffffff81a54d70 T intel_dp_encoder_shutdown +ffffffff81a54db0 T intel_dp_hpd_pulse +ffffffff81a55420 T intel_dp_is_port_edp +ffffffff81a554b0 T intel_dp_init_connector +ffffffff81a56610 t intel_dp_modeset_retry_work_fn +ffffffff81a566b0 t intel_dp_set_common_rates +ffffffff81a56830 T intel_dp_mst_suspend +ffffffff81a568d0 T intel_dp_mst_resume +ffffffff81a56980 t intel_dp_output_format +ffffffff81a56ac0 t intel_dp_compute_link_config +ffffffff81a57280 t intel_dp_tmds_clock_valid +ffffffff81a57320 t intel_dp_set_sink_rates +ffffffff81a57550 t intel_dp_check_device_service_irq +ffffffff81a57b20 t intel_dp_force +ffffffff81a57c50 t intel_dp_connector_register +ffffffff81a57d20 t intel_dp_connector_unregister +ffffffff81a57d80 t intel_dp_oob_hotplug_event +ffffffff81a57e00 t intel_dp_set_edid +ffffffff81a58200 t intel_dp_get_modes +ffffffff81a582f0 t intel_dp_detect +ffffffff81a58bb0 t intel_dp_mode_valid +ffffffff81a58f30 t intel_dp_connector_atomic_check +ffffffff81a592a0 t intel_dp_get_dsc_sink_cap +ffffffff81a59410 t intel_dp_mode_min_output_bpp +ffffffff81a59470 t intel_dp_mode_valid_downstream +ffffffff81a59630 t icl_max_source_rate +ffffffff81a5a000 T intel_dp_aux_pack +ffffffff81a5a070 T intel_dp_aux_fini +ffffffff81a5a090 T intel_dp_aux_init +ffffffff81a5a2a0 t xelpdp_aux_ctl_reg +ffffffff81a5a370 t xelpdp_aux_data_reg +ffffffff81a5a440 t tgl_aux_ctl_reg +ffffffff81a5a4c0 t tgl_aux_data_reg +ffffffff81a5a550 t skl_aux_ctl_reg +ffffffff81a5a5d0 t skl_aux_data_reg +ffffffff81a5a660 t ilk_aux_ctl_reg +ffffffff81a5a6e0 t ilk_aux_data_reg +ffffffff81a5a770 t g4x_aux_ctl_reg +ffffffff81a5a7f0 t g4x_aux_data_reg +ffffffff81a5a890 t skl_get_aux_clock_divider +ffffffff81a5a8c0 t hsw_get_aux_clock_divider +ffffffff81a5a950 t ilk_get_aux_clock_divider +ffffffff81a5a9b0 t g4x_get_aux_clock_divider +ffffffff81a5aa00 t skl_get_aux_send_ctl +ffffffff81a5aa80 t g4x_get_aux_send_ctl +ffffffff81a5aae0 t kasprintf +ffffffff81a5abb0 t intel_dp_aux_transfer +ffffffff81a5ae40 T intel_dp_aux_ch +ffffffff81a5afa0 T intel_dp_aux_irq_handler +ffffffff81a5b040 t intel_dp_aux_xfer +ffffffff81a5c000 T intel_dp_aux_init_backlight_funcs +ffffffff81a5c260 t intel_dp_aux_hdr_setup_backlight +ffffffff81a5c3e0 t intel_dp_aux_hdr_get_backlight +ffffffff81a5c560 t intel_dp_aux_hdr_set_backlight +ffffffff81a5c660 t intel_dp_aux_hdr_disable_backlight +ffffffff81a5c6e0 t intel_dp_aux_hdr_enable_backlight +ffffffff81a5c910 t intel_dp_aux_vesa_setup_backlight +ffffffff81a5cb70 t intel_dp_aux_vesa_get_backlight +ffffffff81a5cba0 t intel_dp_aux_vesa_set_backlight +ffffffff81a5cc40 t intel_dp_aux_vesa_disable_backlight +ffffffff81a5ccf0 t intel_dp_aux_vesa_enable_backlight +ffffffff81a5d000 T intel_dp_hdcp_init +ffffffff81a5d0b0 t intel_dp_hdcp_write_an_aksv +ffffffff81a5d1a0 t intel_dp_hdcp_read_bksv +ffffffff81a5d230 t intel_dp_hdcp_read_bstatus +ffffffff81a5d2c0 t intel_dp_hdcp_repeater_present +ffffffff81a5d370 t intel_dp_hdcp_read_ri_prime +ffffffff81a5d400 t intel_dp_hdcp_read_ksv_ready +ffffffff81a5d4a0 t intel_dp_hdcp_read_ksv_fifo +ffffffff81a5d590 t intel_dp_hdcp_read_v_prime_part +ffffffff81a5d630 t intel_dp_hdcp_toggle_signalling +ffffffff81a5d660 t intel_dp_mst_hdcp_stream_encryption +ffffffff81a5d850 t intel_dp_hdcp_check_link +ffffffff81a5d8e0 t intel_dp_hdcp_capable +ffffffff81a5d990 t intel_dp_hdcp2_capable +ffffffff81a5da10 t intel_dp_hdcp2_write_msg +ffffffff81a5dbc0 t intel_dp_hdcp2_read_msg +ffffffff81a5e290 t intel_dp_hdcp2_config_stream_type +ffffffff81a5e2f0 t intel_dp_mst_hdcp2_stream_encryption +ffffffff81a5e550 t intel_dp_mst_hdcp2_check_link +ffffffff81a5e610 t intel_dp_hdcp2_check_link +ffffffff81a5f000 T intel_dp_init_lttpr_and_dprx_caps +ffffffff81a5f0d0 t intel_dp_init_lttpr +ffffffff81a5f3b0 T intel_dp_get_adjust_train +ffffffff81a5fab0 T intel_dp_program_link_training_pattern +ffffffff81a5fbd0 T intel_dp_set_signal_levels +ffffffff81a5ff70 T intel_dp_dump_link_status +ffffffff81a60060 T intel_dp_stop_link_train +ffffffff81a60310 T intel_dp_start_link_train +ffffffff81a620a0 T intel_dp_128b132b_sdp_crc16 +ffffffff81a62170 t intel_dp_link_train_phy +ffffffff81a64000 T intel_dp_mst_encoder_active_links +ffffffff81a64030 T intel_dp_mst_encoder_init +ffffffff81a64270 T intel_dp_mst_source_support +ffffffff81a642b0 T intel_dp_mst_encoder_cleanup +ffffffff81a64310 T intel_dp_mst_is_master_trans +ffffffff81a64350 T intel_dp_mst_is_slave_trans +ffffffff81a64390 T intel_dp_mst_add_topology_state_for_crtc +ffffffff81a64450 t intel_dp_add_mst_connector +ffffffff81a64680 t intel_dp_mst_poll_hpd_irq +ffffffff81a646a0 t intel_dp_mst_get_hw_state +ffffffff81a64700 t intel_dp_mst_connector_late_register +ffffffff81a64770 t intel_dp_mst_connector_early_unregister +ffffffff81a647a0 t intel_dp_mst_get_modes +ffffffff81a64840 t intel_dp_mst_detect +ffffffff81a64940 t intel_dp_mst_mode_valid_ctx +ffffffff81a64b60 t intel_mst_atomic_best_encoder +ffffffff81a64bc0 t intel_dp_mst_atomic_check +ffffffff81a64d30 t intel_dp_mst_compute_config +ffffffff81a65280 t intel_dp_mst_compute_config_late +ffffffff81a65380 t intel_mst_disable_dp +ffffffff81a65460 t intel_mst_post_disable_dp +ffffffff81a65710 t intel_mst_post_pll_disable_dp +ffffffff81a65770 t intel_mst_pre_pll_enable_dp +ffffffff81a657b0 t intel_mst_pre_enable_dp +ffffffff81a659d0 t intel_mst_enable_dp +ffffffff81a65d70 t intel_dp_mst_enc_get_hw_state +ffffffff81a65db0 t intel_dp_mst_enc_get_config +ffffffff81a65dd0 t intel_dp_mst_initial_fastset_check +ffffffff81a65df0 t intel_dp_mst_encoder_destroy +ffffffff81a65e20 t intel_dp_mst_find_vcpi_slots_for_bpp +ffffffff81a67000 T bxt_port_to_phy_channel +ffffffff81a67110 T bxt_ddi_phy_set_signal_levels +ffffffff81a674e0 T bxt_ddi_phy_is_enabled +ffffffff81a67610 T bxt_ddi_phy_uninit +ffffffff81a676f0 T bxt_ddi_phy_init +ffffffff81a67910 t _bxt_ddi_phy_init +ffffffff81a67e50 T bxt_ddi_phy_verify_state +ffffffff81a68130 t __phy_reg_verify_state +ffffffff81a68230 T bxt_ddi_phy_calc_lane_lat_optim_mask +ffffffff81a682a0 T bxt_ddi_phy_set_lane_optim_mask +ffffffff81a68500 T bxt_ddi_phy_get_lane_lat_optim_mask +ffffffff81a686e0 T vlv_dig_port_to_channel +ffffffff81a68750 T vlv_dig_port_to_phy +ffffffff81a687c0 T vlv_pipe_to_channel +ffffffff81a68820 T chv_set_phy_signal_level +ffffffff81a68b70 T chv_data_lane_soft_reset +ffffffff81a68d40 T chv_phy_pre_pll_enable +ffffffff81a68fe0 T chv_phy_pre_encoder_enable +ffffffff81a69240 T chv_phy_release_cl2_override +ffffffff81a692d0 T chv_phy_post_pll_disable +ffffffff81a69380 T vlv_set_phy_signal_level +ffffffff81a694f0 T vlv_phy_pre_pll_enable +ffffffff81a695f0 T vlv_phy_pre_encoder_enable +ffffffff81a696f0 T vlv_phy_reset_lanes +ffffffff81a6a000 T pnv_calc_dpll_params +ffffffff81a6a0c0 T i9xx_calc_dpll_params +ffffffff81a6a190 T vlv_calc_dpll_params +ffffffff81a6a250 T chv_calc_dpll_params +ffffffff81a6a320 T bxt_find_best_dpll +ffffffff81a6a340 t chv_find_best_dpll +ffffffff81a6a680 T i9xx_dpll_compute_fp +ffffffff81a6a6c0 T vlv_compute_dpll +ffffffff81a6a740 T chv_compute_dpll +ffffffff81a6a7c0 T intel_dpll_crtc_compute_clock +ffffffff81a6a8c0 T intel_dpll_crtc_get_shared_dpll +ffffffff81a6aa10 T intel_dpll_init_clock_hook +ffffffff81a6ab20 T i9xx_enable_pll +ffffffff81a6aef0 T vlv_enable_pll +ffffffff81a6b410 T chv_enable_pll +ffffffff81a6b9e0 T vlv_force_pll_on +ffffffff81a6bb30 T vlv_disable_pll +ffffffff81a6bc00 T chv_disable_pll +ffffffff81a6bd30 T i9xx_disable_pll +ffffffff81a6be50 T vlv_force_pll_off +ffffffff81a6bf50 T assert_pll_enabled +ffffffff81a6c050 T assert_pll_disabled +ffffffff81a6c150 t intel_pll_is_valid +ffffffff81a6c210 t mtl_crtc_compute_clock +ffffffff81a6c2d0 t dg2_crtc_compute_clock +ffffffff81a6c350 t hsw_crtc_compute_clock +ffffffff81a6c410 t hsw_crtc_get_shared_dpll +ffffffff81a6c4b0 t ilk_crtc_compute_clock +ffffffff81a6c7b0 t ilk_crtc_get_shared_dpll +ffffffff81a6c800 t g4x_find_best_dpll +ffffffff81a6cb40 t chv_crtc_compute_clock +ffffffff81a6cc50 t vlv_crtc_compute_clock +ffffffff81a6d0f0 t g4x_crtc_compute_clock +ffffffff81a6d250 t i9xx_compute_dpll +ffffffff81a6d4d0 t pnv_crtc_compute_clock +ffffffff81a6d8b0 t i9xx_crtc_compute_clock +ffffffff81a6d9d0 t i9xx_find_best_dpll +ffffffff81a6dd10 t i8xx_crtc_compute_clock +ffffffff81a6e000 T intel_get_shared_dpll_by_id +ffffffff81a6e040 T assert_shared_dpll +ffffffff81a6e1f0 T intel_dpll_get_hw_state +ffffffff81a6e220 T icl_tc_port_to_pll_id +ffffffff81a6e250 T intel_enable_shared_dpll +ffffffff81a6e5b0 T intel_disable_shared_dpll +ffffffff81a6e840 T intel_unreference_shared_dpll_crtc +ffffffff81a6e940 T intel_shared_dpll_swap_state +ffffffff81a6ea20 T icl_set_active_port_dpll +ffffffff81a6ea60 T intel_shared_dpll_init +ffffffff81a6ec60 T intel_compute_shared_dplls +ffffffff81a6ecf0 T intel_reserve_shared_dplls +ffffffff81a6ed80 T intel_release_shared_dplls +ffffffff81a6edc0 T intel_update_active_dpll +ffffffff81a6ee20 T intel_dpll_get_freq +ffffffff81a6eeb0 T intel_dpll_update_ref_clks +ffffffff81a6ef00 T intel_dpll_readout_hw_state +ffffffff81a6f130 T intel_dpll_sanitize_state +ffffffff81a6f210 T intel_dpll_dump_hw_state +ffffffff81a6f290 T intel_shared_dpll_state_verify +ffffffff81a6f470 t verify_single_dpll_state +ffffffff81a6f9e0 T intel_shared_dpll_verify_disabled +ffffffff81a6fa60 t icl_compute_dplls +ffffffff81a706a0 t icl_get_dplls +ffffffff81a70970 t icl_put_dplls +ffffffff81a70a30 t icl_update_active_dpll +ffffffff81a70ae0 t icl_update_dpll_ref_clks +ffffffff81a70b20 t icl_dump_hw_state +ffffffff81a70be0 t combo_pll_enable +ffffffff81a70df0 t combo_pll_disable +ffffffff81a70ec0 t combo_pll_get_hw_state +ffffffff81a70f40 t icl_ddi_combo_pll_get_freq +ffffffff81a71110 t icl_dpll_write +ffffffff81a71350 t adlp_cmtg_clock_gating_wa +ffffffff81a714b0 t icl_pll_disable +ffffffff81a71650 t icl_pll_get_hw_state +ffffffff81a71930 t tbt_pll_enable +ffffffff81a71ae0 t tbt_pll_disable +ffffffff81a71b00 t tbt_pll_get_hw_state +ffffffff81a71b20 t icl_ddi_tbt_pll_get_freq +ffffffff81a71b90 t mg_pll_enable +ffffffff81a721a0 t mg_pll_disable +ffffffff81a721e0 t dkl_pll_get_hw_state +ffffffff81a723f0 t icl_ddi_mg_pll_get_freq +ffffffff81a724d0 t icl_calc_dpll_state +ffffffff81a72610 t intel_find_shared_dpll +ffffffff81a72930 t intel_reference_shared_dpll +ffffffff81a72b50 t intel_unreference_shared_dpll +ffffffff81a72d50 t mg_pll_get_hw_state +ffffffff81a72fa0 t bxt_compute_dpll +ffffffff81a732a0 t bxt_get_dpll +ffffffff81a73370 t intel_put_dpll +ffffffff81a733d0 t bxt_update_dpll_ref_clks +ffffffff81a73410 t bxt_dump_hw_state +ffffffff81a734c0 t bxt_ddi_pll_enable +ffffffff81a73e90 t bxt_ddi_pll_disable +ffffffff81a740a0 t bxt_ddi_pll_get_hw_state +ffffffff81a744d0 t bxt_ddi_pll_get_freq +ffffffff81a74560 t bxt_ddi_set_dpll_hw_state +ffffffff81a74750 t skl_compute_dpll +ffffffff81a74eb0 t skl_get_dpll +ffffffff81a74f60 t skl_update_dpll_ref_clks +ffffffff81a74fa0 t skl_dump_hw_state +ffffffff81a75000 t skl_ddi_dpll0_enable +ffffffff81a750c0 t skl_ddi_dpll0_disable +ffffffff81a750f0 t skl_ddi_dpll0_get_hw_state +ffffffff81a751f0 t skl_ddi_pll_get_freq +ffffffff81a75280 t skl_ddi_wrpll_get_freq +ffffffff81a753e0 t skl_ddi_pll_enable +ffffffff81a75600 t skl_ddi_pll_disable +ffffffff81a75690 t skl_ddi_pll_get_hw_state +ffffffff81a757b0 t hsw_compute_dpll +ffffffff81a75fd0 t hsw_get_dpll +ffffffff81a76120 t hsw_update_dpll_ref_clks +ffffffff81a76190 t hsw_dump_hw_state +ffffffff81a761c0 t hsw_ddi_wrpll_enable +ffffffff81a76240 t hsw_ddi_wrpll_disable +ffffffff81a76320 t hsw_ddi_wrpll_get_hw_state +ffffffff81a763c0 t hsw_ddi_wrpll_get_freq +ffffffff81a764b0 t hsw_ddi_spll_enable +ffffffff81a76510 t hsw_ddi_spll_disable +ffffffff81a765e0 t hsw_ddi_spll_get_hw_state +ffffffff81a76670 t hsw_ddi_spll_get_freq +ffffffff81a76710 t hsw_ddi_lcpll_enable +ffffffff81a76740 t hsw_ddi_lcpll_disable +ffffffff81a76770 t hsw_ddi_lcpll_get_hw_state +ffffffff81a767a0 t hsw_ddi_lcpll_get_freq +ffffffff81a76820 t ibx_compute_dpll +ffffffff81a76850 t ibx_get_dpll +ffffffff81a76950 t ibx_dump_hw_state +ffffffff81a769b0 t ibx_pch_dpll_enable +ffffffff81a76b50 t ibx_pch_dpll_disable +ffffffff81a76bd0 t ibx_pch_dpll_get_hw_state +ffffffff81a77000 T intel_dpt_pin +ffffffff81a771e0 T intel_dpt_unpin +ffffffff81a77250 T intel_dpt_resume +ffffffff81a77320 T intel_dpt_suspend +ffffffff81a773f0 T intel_dpt_create +ffffffff81a777e0 t dpt_insert_page +ffffffff81a77850 t dpt_clear_range +ffffffff81a77880 t dpt_insert_entries +ffffffff81a77970 t dpt_cleanup +ffffffff81a779c0 t dpt_bind_vma +ffffffff81a77a50 t dpt_unbind_vma +ffffffff81a77a80 T intel_dpt_destroy +ffffffff81a77ad0 T intel_dpt_configure +ffffffff81a77c70 t __ww_mutex_lock +ffffffff81a78000 T intel_drrs_type_str +ffffffff81a78040 T intel_drrs_is_active +ffffffff81a78070 T intel_drrs_activate +ffffffff81a78260 T intel_drrs_deactivate +ffffffff81a78420 T intel_drrs_invalidate +ffffffff81a78440 t intel_drrs_frontbuffer_update +ffffffff81a78690 T intel_drrs_flush +ffffffff81a786b0 T intel_drrs_crtc_init +ffffffff81a78750 t intel_drrs_downclock_work +ffffffff81a78870 T intel_drrs_crtc_debugfs_add +ffffffff81a788a0 T intel_drrs_connector_debugfs_add +ffffffff81a788b0 t __delayed_work_tick +ffffffff81a79000 T intel_dsb_reg_write +ffffffff81a79140 T intel_dsb_finish +ffffffff81a791c0 T intel_dsb_commit +ffffffff81a79370 T intel_dsb_wait +ffffffff81a79560 T intel_dsb_prepare +ffffffff81a796e0 T intel_dsb_cleanup +ffffffff81a7a000 T intel_dsi_wait_panel_power_cycle +ffffffff81a7a0f0 T intel_dsi_shutdown +ffffffff81a7a1e0 T intel_dsi_bitrate +ffffffff81a7a270 T intel_dsi_tlpx_ns +ffffffff81a7a2c0 T intel_dsi_get_modes +ffffffff81a7a2d0 T intel_dsi_mode_valid +ffffffff81a7a390 T intel_dsi_host_init +ffffffff81a7a440 T intel_dsi_get_panel_orientation +ffffffff81a7b000 T intel_dsi_dcs_init_backlight_funcs +ffffffff81a7b0a0 t dcs_setup_backlight +ffffffff81a7b120 t dcs_get_backlight +ffffffff81a7b210 t dcs_set_backlight +ffffffff81a7b300 t dcs_disable_backlight +ffffffff81a7b660 t dcs_enable_backlight +ffffffff81a7c000 T intel_dsi_vbt_exec_sequence +ffffffff81a7c020 T intel_dsi_log_params +ffffffff81a7c3a0 T intel_dsi_vbt_init +ffffffff81a7c840 T intel_dsi_vbt_gpio_init +ffffffff81a7c860 T intel_dsi_vbt_gpio_cleanup +ffffffff81a7d000 T intel_dvo_init +ffffffff81a7d650 t intel_disable_dvo +ffffffff81a7d6f0 t intel_enable_dvo +ffffffff81a7d7c0 t intel_dvo_get_hw_state +ffffffff81a7d830 t intel_dvo_get_config +ffffffff81a7d8d0 t intel_dvo_compute_config +ffffffff81a7d960 t intel_dvo_pre_enable +ffffffff81a7da60 t intel_dvo_connector_get_hw_state +ffffffff81a7daf0 t intel_dvo_enc_destroy +ffffffff81a7db30 t intel_dvo_detect +ffffffff81a7dc30 t intel_dvo_get_modes +ffffffff81a7dca0 t intel_dvo_mode_valid +ffffffff81a7e000 T intel_fb_get_format_info +ffffffff81a7e2b0 T intel_fb_is_tiled_modifier +ffffffff81a7e2f0 t lookup_modifier +ffffffff81a7e530 T intel_fb_is_ccs_modifier +ffffffff81a7e570 T intel_fb_is_rc_ccs_cc_modifier +ffffffff81a7e5b0 T intel_fb_is_mc_ccs_modifier +ffffffff81a7e5f0 T intel_fb_plane_get_modifiers +ffffffff81a7e7d0 T intel_fb_plane_supports_modifier +ffffffff81a7e850 T intel_format_info_is_yuv_semiplanar +ffffffff81a7e8d0 T intel_fb_is_ccs_aux_plane +ffffffff81a7e980 T intel_fb_rc_ccs_cc_plane +ffffffff81a7ea50 T is_surface_linear +ffffffff81a7ebb0 T main_to_ccs_plane +ffffffff81a7ec60 T skl_ccs_to_main_plane +ffffffff81a7eda0 T skl_main_to_aux_plane +ffffffff81a7eec0 T intel_tile_size +ffffffff81a7ef00 T intel_tile_width_bytes +ffffffff81a7f320 T intel_tile_height +ffffffff81a7f380 T intel_tile_row_size +ffffffff81a7f400 T intel_fb_align_height +ffffffff81a7f480 T intel_fb_modifier_uses_dpt +ffffffff81a7f4c0 T intel_fb_uses_dpt +ffffffff81a7f520 T intel_cursor_alignment +ffffffff81a7f580 T intel_surf_alignment +ffffffff81a7f810 T intel_fb_plane_get_subsampling +ffffffff81a7f960 T intel_plane_adjust_aligned_offset +ffffffff81a7f9d0 t intel_adjust_aligned_offset +ffffffff81a7fb80 T intel_plane_compute_aligned_offset +ffffffff81a7fc80 t intel_compute_aligned_offset +ffffffff81a7fe40 T intel_fb_needs_pot_stride_remap +ffffffff81a7feb0 T intel_fb_supports_90_270_rotation +ffffffff81a7ff10 T intel_fill_fb_info +ffffffff81a80a10 t calc_plane_remap_info +ffffffff81a813c0 T intel_fb_fill_view +ffffffff81a81430 T intel_plane_compute_gtt +ffffffff81a81910 t intel_plane_check_stride +ffffffff81a81a70 T intel_framebuffer_init +ffffffff81a822d0 t gen12_ccs_aux_stride +ffffffff81a82330 T intel_user_framebuffer_create +ffffffff81a82490 T intel_framebuffer_create +ffffffff81a82520 t intel_adjust_tile_offset +ffffffff81a82660 t intel_user_framebuffer_destroy +ffffffff81a826d0 t intel_user_framebuffer_create_handle +ffffffff81a82700 t intel_user_framebuffer_dirty +ffffffff81a83000 T intel_pin_and_fence_fb_obj +ffffffff81a83330 t i915_gem_object_lock +ffffffff81a83540 T intel_unpin_fb_vma +ffffffff81a835b0 T intel_plane_pin_fb +ffffffff81a838e0 T intel_plane_unpin_fb +ffffffff81a84000 T intel_fbc_cleanup +ffffffff81a841c0 T intel_fbc_pre_update +ffffffff81a84850 T intel_fbc_post_update +ffffffff81a84a00 T intel_fbc_invalidate +ffffffff81a84b80 T intel_fbc_flush +ffffffff81a84e20 T intel_fbc_atomic_check +ffffffff81a853e0 T intel_fbc_disable +ffffffff81a854a0 t __intel_fbc_disable +ffffffff81a855e0 T intel_fbc_update +ffffffff81a85ca0 T intel_fbc_reset_underrun +ffffffff81a85e00 T intel_fbc_handle_fifo_underrun_irq +ffffffff81a85ec0 T intel_fbc_add_plane +ffffffff81a85ef0 T intel_fbc_init +ffffffff81a86170 T intel_fbc_sanitize +ffffffff81a86240 T intel_fbc_crtc_debugfs_add +ffffffff81a86270 T intel_fbc_debugfs_register +ffffffff81a862a0 t intel_fbc_is_ok +ffffffff81a86410 t intel_fbc_update_state +ffffffff81a86790 t intel_fbc_underrun_work_fn +ffffffff81a86860 t ivb_fbc_activate +ffffffff81a86ab0 t ilk_fbc_deactivate +ffffffff81a86b60 t ilk_fbc_is_active +ffffffff81a86bc0 t ivb_fbc_is_compressing +ffffffff81a86c30 t snb_fbc_nuke +ffffffff81a86cb0 t ilk_fbc_program_cfb +ffffffff81a86d10 t ivb_fbc_set_false_color +ffffffff81a86d90 t snb_fbc_activate +ffffffff81a86e20 t ilk_fbc_is_compressing +ffffffff81a86e90 t ilk_fbc_activate +ffffffff81a86fc0 t i965_fbc_nuke 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intel_set_pch_fifo_underrun_reporting +ffffffff81a8d5f0 T intel_cpu_fifo_underrun_irq_handler +ffffffff81a8d7e0 T intel_pch_fifo_underrun_irq_handler +ffffffff81a8d860 T intel_check_cpu_fifo_underruns +ffffffff81a8da70 T intel_check_pch_fifo_underruns +ffffffff81a8dba0 T intel_init_fifo_underrun_reporting +ffffffff81a8e000 T intel_frontbuffer_flip_prepare +ffffffff81a8e050 T intel_frontbuffer_flip_complete +ffffffff81a8e130 T intel_frontbuffer_flip +ffffffff81a8e200 T __intel_fb_invalidate +ffffffff81a8e290 T __intel_fb_flush +ffffffff81a8e380 T intel_frontbuffer_get +ffffffff81a8e4c0 t frontbuffer_active +ffffffff81a8e4f0 t frontbuffer_retire +ffffffff81a8e530 T intel_frontbuffer_put +ffffffff81a8e660 T intel_frontbuffer_track +ffffffff81a8f000 T intel_atomic_global_obj_init +ffffffff81a8f070 T intel_atomic_global_obj_cleanup +ffffffff81a8f160 T intel_atomic_get_global_obj_state +ffffffff81a8f3b0 T intel_atomic_get_old_global_obj_state +ffffffff81a8f410 T intel_atomic_get_new_global_obj_state +ffffffff81a8f470 T intel_atomic_swap_global_state +ffffffff81a8f5b0 T intel_atomic_clear_global_state +ffffffff81a8f6d0 T intel_atomic_lock_global_state +ffffffff81a8f760 T intel_atomic_serialize_global_state +ffffffff81a8f7f0 T intel_atomic_global_state_is_serialized +ffffffff81a90000 T intel_gmbus_is_valid_pin +ffffffff81a90100 T intel_gmbus_reset +ffffffff81a90160 T intel_bb_set_bits +ffffffff81a902a0 T intel_bb_set_dir +ffffffff81a902d0 T intel_bb_read_bits +ffffffff81a90460 T intel_acquire_bus +ffffffff81a90660 T intel_release_bus +ffffffff81a90800 T intel_send_start +ffffffff81a90820 T intel_send_stop +ffffffff81a90840 T intel_initiate_xfer +ffffffff81a90860 T intel_read_byte +ffffffff81a90880 T intel_write_byte +ffffffff81a908a0 T intel_gmbus_output_aksv +ffffffff81a90970 t do_gmbus_xfer +ffffffff81a90f70 T intel_gmbus_setup +ffffffff81a912f0 T intel_gmbus_teardown +ffffffff81a91370 T intel_gmbus_get_adapter +ffffffff81a913f0 T intel_gmbus_force_bit +ffffffff81a91490 T intel_gmbus_is_forced_bit +ffffffff81a914c0 T intel_gmbus_irq_handler +ffffffff81a91560 t gmbus_xfer_read +ffffffff81a91850 t gmbus_xfer_write +ffffffff81a91a90 t gmbus_wait +ffffffff81a91e70 t gmbus_wait_idle +ffffffff81a92000 t gmbus_xfer +ffffffff81a920e0 t gmbus_func +ffffffff81a92120 t gmbus_lock_bus +ffffffff81a92140 t gmbus_trylock_bus +ffffffff81a921a0 t gmbus_unlock_bus +ffffffff81a93000 T intel_hdcp_capable +ffffffff81a930a0 t intel_hdcp_read_valid_bksv +ffffffff81a93330 T intel_hdcp2_capable +ffffffff81a93450 T is_hdcp_supported +ffffffff81a934a0 T intel_hdcp_component_init +ffffffff81a93500 T intel_hdcp_init +ffffffff81a93680 t intel_hdcp_check_work +ffffffff81a95fc0 t intel_hdcp_prop_work +ffffffff81a96040 T intel_hdcp_enable +ffffffff81a96090 T intel_hdcp_disable +ffffffff81a961c0 t intel_hdcp_update_value +ffffffff81a96380 t _intel_hdcp2_disable +ffffffff81a96770 t _intel_hdcp_disable +ffffffff81a96a60 T intel_hdcp_update_pipe +ffffffff81a96bd0 T intel_hdcp_component_fini +ffffffff81a96c70 T intel_hdcp_cleanup +ffffffff81a96db0 T intel_hdcp_atomic_check +ffffffff81a96e40 T intel_hdcp_handle_cp_irq +ffffffff81a96f40 t __delayed_work_tick +ffffffff81a96f60 t hdcp2_authenticate_repeater_topology +ffffffff81a97220 t transcoder_name +ffffffff81a97260 t intel_hdcp_get_repeater_ctl +ffffffff81a97330 t ktime_get_raw +ffffffff81a973b0 t wait_remaining_ms_from_jiffies +ffffffff81a97440 t intel_hdcp_auth_downstream +ffffffff81a98610 t intel_write_sha_text +ffffffff81a99000 T intel_hdcp_gsc_cs_required +ffffffff81a99040 T intel_hdcp_gsc_init +ffffffff81a994b0 T intel_hdcp_gsc_fini +ffffffff81a99510 T intel_hdcp_gsc_msg_send +ffffffff81a99840 t gsc_hdcp_initiate_session +ffffffff81a99890 t gsc_hdcp_verify_receiver_cert_prepare_km +ffffffff81a998e0 t gsc_hdcp_verify_hprime +ffffffff81a99930 t gsc_hdcp_store_pairing_info +ffffffff81a99980 t gsc_hdcp_initiate_locality_check +ffffffff81a999d0 t gsc_hdcp_verify_lprime +ffffffff81a99a20 t gsc_hdcp_get_session_key +ffffffff81a99a70 t gsc_hdcp_repeater_check_flow_prepare_ack +ffffffff81a99ac0 t gsc_hdcp_verify_mprime +ffffffff81a99b10 t gsc_hdcp_enable_authentication +ffffffff81a99b60 t gsc_hdcp_close_session +ffffffff81a9a000 T intel_hdmi_to_i915 +ffffffff81a9a040 T hsw_write_infoframe +ffffffff81a9a450 t hsw_dip_data_reg +ffffffff81a9a600 T hsw_read_infoframe +ffffffff81a9a6c0 T intel_hdmi_infoframe_enable +ffffffff81a9a760 T intel_hdmi_infoframes_enabled +ffffffff81a9a880 T intel_read_infoframe +ffffffff81a9aa20 T intel_hdmi_read_gcp_infoframe +ffffffff81a9ab00 T intel_dp_dual_mode_set_tmds_output +ffffffff81a9abc0 T intel_hdmi_tmds_clock +ffffffff81a9ac10 T intel_hdmi_bpc_possible +ffffffff81a9ad30 T intel_hdmi_limited_color_range +ffffffff81a9ada0 T intel_hdmi_compute_has_hdmi_sink +ffffffff81a9ae10 T intel_hdmi_compute_config +ffffffff81a9b3c0 t intel_hdmi_compute_output_format +ffffffff81a9b520 t intel_hdmi_compute_hdmi_infoframe +ffffffff81a9b5e0 t intel_hdmi_compute_drm_infoframe +ffffffff81a9b6d0 T intel_hdmi_encoder_shutdown +ffffffff81a9b7a0 T intel_hdmi_handle_sink_scrambling +ffffffff81a9b890 T intel_infoframe_init +ffffffff81a9ba30 t vlv_write_infoframe +ffffffff81a9bd60 t vlv_read_infoframe +ffffffff81a9bee0 t vlv_set_infoframes +ffffffff81a9c220 t vlv_infoframes_enabled +ffffffff81a9c2b0 t g4x_write_infoframe +ffffffff81a9c550 t g4x_read_infoframe +ffffffff81a9c680 t g4x_set_infoframes +ffffffff81a9c910 t g4x_infoframes_enabled +ffffffff81a9c990 t hsw_set_infoframes +ffffffff81a9cc20 t hsw_infoframes_enabled +ffffffff81a9ccb0 t ibx_write_infoframe +ffffffff81a9cfc0 t ibx_read_infoframe +ffffffff81a9d130 t ibx_set_infoframes +ffffffff81a9d460 t ibx_infoframes_enabled +ffffffff81a9d4f0 t cpt_write_infoframe +ffffffff81a9d7f0 t cpt_read_infoframe +ffffffff81a9d960 t cpt_set_infoframes +ffffffff81a9dc40 t cpt_infoframes_enabled +ffffffff81a9dcb0 T intel_hdmi_init_connector +ffffffff81a9e430 T intel_hdmi_dsc_get_slice_height +ffffffff81a9e490 T intel_hdmi_dsc_get_num_slices +ffffffff81a9e610 T intel_hdmi_dsc_get_bpp +ffffffff81a9e6f0 t intel_hdmi_compute_clock +ffffffff81a9e950 t hdmi_port_clock_valid +ffffffff81a9eb70 t intel_write_infoframe +ffffffff81a9ed40 t intel_hdmi_detect +ffffffff81a9eee0 t intel_hdmi_force +ffffffff81a9ef80 t intel_hdmi_connector_register +ffffffff81a9ef90 t intel_hdmi_connector_unregister +ffffffff81a9efa0 t intel_hdmi_set_edid +ffffffff81a9f230 t intel_hdmi_get_modes +ffffffff81a9f240 t intel_hdmi_mode_valid +ffffffff81a9f3f0 t intel_hdmi_connector_atomic_check +ffffffff81a9f420 t intel_hdmi_mode_clock_valid +ffffffff81a9f5c0 t intel_hdmi_hdcp_write_an_aksv +ffffffff81a9f700 t intel_hdmi_hdcp_read_bksv +ffffffff81a9f7d0 t intel_hdmi_hdcp_read_bstatus +ffffffff81a9f8a0 t intel_hdmi_hdcp_repeater_present +ffffffff81a9f980 t intel_hdmi_hdcp_read_ri_prime +ffffffff81a9fa50 t intel_hdmi_hdcp_read_ksv_ready +ffffffff81a9fb30 t intel_hdmi_hdcp_read_ksv_fifo +ffffffff81a9fc00 t intel_hdmi_hdcp_read_v_prime_part +ffffffff81a9fcf0 t intel_hdmi_hdcp_toggle_signalling +ffffffff81a9ff60 t intel_hdmi_hdcp_check_link +ffffffff81aa0280 t intel_hdmi_hdcp2_capable +ffffffff81aa0340 t intel_hdmi_hdcp2_write_msg +ffffffff81aa0430 t intel_hdmi_hdcp2_read_msg +ffffffff81aa0830 t intel_hdmi_hdcp2_check_link +ffffffff81aa1000 T intel_hpd_pin_default +ffffffff81aa1030 T intel_encoder_hotplug +ffffffff81aa1160 T intel_hpd_trigger_irq +ffffffff81aa11d0 T intel_hpd_irq_handler +ffffffff81aa15f0 T intel_hpd_init +ffffffff81aa1700 T intel_hpd_poll_enable +ffffffff81aa1780 T intel_hpd_poll_disable +ffffffff81aa17e0 T intel_hpd_init_early +ffffffff81aa18f0 t i915_hotplug_work_func +ffffffff81aa1cd0 t i915_digport_work_func +ffffffff81aa1e50 t i915_hpd_poll_init_work +ffffffff81aa1f50 t intel_hpd_irq_storm_reenable_work +ffffffff81aa2270 T intel_hpd_cancel_work +ffffffff81aa2390 T intel_hpd_disable +ffffffff81aa2420 T intel_hpd_enable +ffffffff81aa2490 T intel_hpd_debugfs_register +ffffffff81aa24c0 t __delayed_work_tick +ffffffff81aa3000 T i915_hotplug_interrupt_update_locked +ffffffff81aa30c0 T i915_hotplug_interrupt_update +ffffffff81aa3190 T i9xx_hpd_irq_ack +ffffffff81aa32d0 T i9xx_hpd_irq_handler +ffffffff81aa3480 T ibx_hpd_irq_handler +ffffffff81aa3620 T xelpdp_pica_irq_handler +ffffffff81aa38e0 T icp_irq_handler +ffffffff81aa3b70 T spt_irq_handler +ffffffff81aa3e10 T ilk_hpd_irq_handler +ffffffff81aa3f30 T bxt_hpd_irq_handler +ffffffff81aa4090 T gen11_hpd_irq_handler +ffffffff81aa4300 T intel_hpd_enable_detection +ffffffff81aa4340 T intel_hpd_irq_setup +ffffffff81aa4390 T intel_hotplug_irq_init +ffffffff81aa4610 t i915_hpd_irq_setup +ffffffff81aa4720 t i915_hpd_enable_detection +ffffffff81aa47c0 t icp_hpd_irq_setup +ffffffff81aa49b0 t icp_hpd_enable_detection +ffffffff81aa4ab0 t dg1_hpd_irq_setup +ffffffff81aa4b10 t dg1_hpd_enable_detection +ffffffff81aa4c50 t xelpdp_hpd_irq_setup +ffffffff81aa5050 t xelpdp_hpd_enable_detection +ffffffff81aa51f0 t gen11_hpd_irq_setup +ffffffff81aa5440 t gen11_hpd_enable_detection +ffffffff81aa5640 t bxt_hpd_irq_setup +ffffffff81aa57c0 t bxt_hpd_enable_detection +ffffffff81aa58a0 t spt_hpd_irq_setup +ffffffff81aa5ac0 t spt_hpd_enable_detection +ffffffff81aa5be0 t ilk_hpd_irq_setup +ffffffff81aa5e50 t ilk_hpd_enable_detection +ffffffff81aa6000 T intel_hti_init +ffffffff81aa6070 T intel_hti_uses_phy +ffffffff81aa6110 T intel_hti_dpll_mask +ffffffff81aa7000 T intel_load_detect_get_pipe +ffffffff81aa7370 t intel_modeset_disable_planes +ffffffff81aa7430 T intel_load_detect_release_pipe +ffffffff81aa8000 T intel_lpe_audio_irq_handler +ffffffff81aa8020 T intel_lpe_audio_init +ffffffff81aa8050 T intel_lpe_audio_teardown +ffffffff81aa8070 T intel_lpe_audio_notify +ffffffff81aa9000 T lspcon_detect_hdr_capability +ffffffff81aa90b0 T lspcon_write_infoframe +ffffffff81aa97f0 T lspcon_read_infoframe +ffffffff81aa9830 T lspcon_set_infoframes +ffffffff81aa9a90 T lspcon_infoframes_enabled +ffffffff81aa9c60 T lspcon_wait_pcon_mode +ffffffff81aa9c80 t lspcon_wait_mode +ffffffff81aa9f40 T lspcon_init +ffffffff81aaa340 T intel_lspcon_infoframes_enabled +ffffffff81aaa370 T lspcon_resume +ffffffff81aaa610 t lspcon_change_mode +ffffffff81aab000 T intel_lvds_port_enabled +ffffffff81aab080 T intel_get_lvds_encoder +ffffffff81aab0e0 T intel_is_dual_link_lvds +ffffffff81aab140 T intel_lvds_init +ffffffff81aab7e0 t intel_enable_lvds +ffffffff81aab920 t intel_pre_enable_lvds +ffffffff81aabc00 t intel_lvds_compute_config +ffffffff81aabd60 t pch_disable_lvds +ffffffff81aabd80 t pch_post_disable_lvds +ffffffff81aabda0 t gmch_disable_lvds +ffffffff81aabdd0 t intel_lvds_get_hw_state +ffffffff81aabe90 t intel_lvds_get_config +ffffffff81aabfa0 t intel_lvds_shutdown +ffffffff81aac040 t compute_is_dual_link_lvds +ffffffff81aac110 t intel_no_lvds_dmi_callback +ffffffff81aac160 t intel_disable_lvds +ffffffff81aac280 t intel_lvds_get_modes +ffffffff81aac2d0 t intel_lvds_mode_valid +ffffffff81aac370 t intel_dual_link_lvds_callback +ffffffff81aad000 T _intel_modeset_lock_begin +ffffffff81aad060 T _intel_modeset_lock_loop +ffffffff81aad0a0 T _intel_modeset_lock_end +ffffffff81aae000 T intel_modeset_setup_hw_state +ffffffff81aaf2d0 t intel_crtc_disable_noatomic +ffffffff81aaf8b0 t intel_crtc_disable_noatomic_begin +ffffffff81ab0000 T intel_modeset_verify_crtc +ffffffff81ab0540 t verify_connector_state +ffffffff81ab09d0 T intel_modeset_verify_disabled +ffffffff81ab1000 T intel_opregion_notify_encoder +ffffffff81ab1180 t swsci +ffffffff81ab14b0 T intel_opregion_notify_adapter +ffffffff81ab1510 T intel_opregion_asle_intr +ffffffff81ab1560 T intel_opregion_setup +ffffffff81ab1d70 t asle_work +ffffffff81ab21e0 T intel_opregion_get_panel_type +ffffffff81ab22d0 T intel_opregion_get_edid +ffffffff81ab2390 T intel_opregion_headless_sku +ffffffff81ab23e0 T intel_opregion_register +ffffffff81ab2480 T intel_opregion_resume +ffffffff81ab2520 T intel_opregion_suspend +ffffffff81ab25d0 T intel_opregion_unregister +ffffffff81ab26a0 T intel_opregion_cleanup +ffffffff81ab2790 t intel_no_opregion_vbt_callback +ffffffff81ab27f0 t intel_use_opregion_panel_type_callback +ffffffff81ab3000 T intel_overlay_reset +ffffffff81ab3050 T intel_overlay_switch_off +ffffffff81ab3250 t intel_overlay_release_old_vid +ffffffff81ab33f0 T intel_overlay_put_image_ioctl +ffffffff81ab3700 t update_pfit_vscale_ratio +ffffffff81ab37d0 t check_overlay_dst +ffffffff81ab38a0 t check_overlay_src +ffffffff81ab3af0 t intel_overlay_do_put_image +ffffffff81ab4660 T intel_overlay_attrs_ioctl +ffffffff81ab4980 t check_gamma +ffffffff81ab4b70 T intel_overlay_setup +ffffffff81ab4de0 t intel_overlay_last_flip_retire +ffffffff81ab4e20 T intel_overlay_cleanup +ffffffff81ab4ee0 T intel_overlay_capture_error_state +ffffffff81ab4fd0 T intel_overlay_print_error_state +ffffffff81ab53a0 t intel_overlay_release_old_vid_tail +ffffffff81ab5470 t intel_overlay_off_tail +ffffffff81ab5620 t intel_overlay_flip_prepare +ffffffff81ab6000 T intel_panel_use_ssc +ffffffff81ab6060 T intel_panel_preferred_fixed_mode +ffffffff81ab60b0 T intel_panel_fixed_mode +ffffffff81ab6210 T intel_panel_downclock_mode +ffffffff81ab6300 T intel_panel_highest_mode +ffffffff81ab6360 T intel_panel_get_modes +ffffffff81ab63f0 T intel_panel_drrs_type +ffffffff81ab6420 T intel_panel_compute_config +ffffffff81ab6590 T intel_panel_add_edid_fixed_modes +ffffffff81ab6ac0 T intel_panel_add_vbt_lfp_fixed_mode +ffffffff81ab6b20 t intel_panel_add_fixed_mode +ffffffff81ab6ca0 T intel_panel_add_vbt_sdvo_fixed_mode +ffffffff81ab6d10 T intel_panel_add_encoder_fixed_mode +ffffffff81ab6d50 T intel_panel_fitting +ffffffff81ab73b0 T intel_panel_detect +ffffffff81ab7440 T intel_panel_mode_valid +ffffffff81ab74d0 T intel_panel_init_alloc +ffffffff81ab7520 T intel_panel_init +ffffffff81ab7640 T intel_panel_fini +ffffffff81ab8000 T intel_has_pch_trancoder +ffffffff81ab8060 T intel_crtc_pch_transcoder +ffffffff81ab80a0 T intel_pch_transcoder_get_m1_n1 +ffffffff81ab80f0 T intel_pch_transcoder_get_m2_n2 +ffffffff81ab8140 T ilk_pch_pre_enable +ffffffff81ab8170 T ilk_pch_enable +ffffffff81ab8750 t ilk_pch_transcoder_set_timings +ffffffff81ab89b0 T ilk_pch_disable +ffffffff81ab89d0 T ilk_pch_post_disable +ffffffff81ab8da0 T ilk_pch_get_config +ffffffff81ab8f60 T lpt_pch_enable +ffffffff81ab91d0 T lpt_pch_disable +ffffffff81ab92e0 T lpt_pch_get_config +ffffffff81ab93b0 T intel_pch_sanitize +ffffffff81ab9690 t assert_pch_dp_disabled +ffffffff81ab9810 t assert_pch_hdmi_disabled +ffffffff81aba000 T lpt_disable_iclkip +ffffffff81aba070 T lpt_iclkip +ffffffff81aba100 T lpt_program_iclkip +ffffffff81aba390 T lpt_get_iclkip +ffffffff81aba4a0 T lpt_disable_clkout_dp +ffffffff81aba580 T intel_init_pch_refclk +ffffffff81abc000 T intel_crtc_initial_plane_config +ffffffff81abd000 T intel_pmdemand_init +ffffffff81abd120 T intel_pmdemand_init_early +ffffffff81abd1a0 T intel_pmdemand_update_phys_mask +ffffffff81abd240 T intel_pmdemand_update_port_clock +ffffffff81abd280 T intel_pmdemand_atomic_check +ffffffff81abd620 t intel_pmdemand_update_max_ddiclk +ffffffff81abd6f0 t intel_pmdemand_update_active_non_tc_phys +ffffffff81abd8f0 T intel_pmdemand_init_pmdemand_params +ffffffff81abdac0 T intel_pmdemand_program_dbuf +ffffffff81abdc50 t intel_pmdemand_wait +ffffffff81abde40 T intel_pmdemand_pre_plane_update +ffffffff81abdf30 t intel_pmdemand_program_params +ffffffff81abe370 T intel_pmdemand_post_plane_update +ffffffff81abe450 t intel_pmdemand_duplicate_state +ffffffff81abe4e0 t intel_pmdemand_destroy_state +ffffffff81abf000 T intel_pps_lock +ffffffff81abf060 T intel_pps_unlock +ffffffff81abf0c0 T intel_pps_reset_all +ffffffff81abf210 T intel_pps_check_power_unlocked +ffffffff81abf4f0 t pps_name +ffffffff81abf590 T intel_pps_wait_power_cycle +ffffffff81abf630 t wait_panel_power_cycle +ffffffff81abf810 T intel_pps_vdd_on_unlocked +ffffffff81abfd80 T intel_pps_vdd_on +ffffffff81abff10 T intel_pps_vdd_off_sync +ffffffff81abffe0 t intel_pps_vdd_off_sync_unlocked +ffffffff81ac0400 T intel_pps_vdd_off_unlocked +ffffffff81ac05b0 T intel_pps_on_unlocked +ffffffff81ac0a40 T intel_pps_on +ffffffff81ac0ae0 T intel_pps_off_unlocked +ffffffff81ac0ec0 T intel_pps_off +ffffffff81ac0f60 T intel_pps_backlight_on +ffffffff81ac1150 T intel_pps_backlight_off +ffffffff81ac1340 T intel_pps_backlight_power +ffffffff81ac1530 T vlv_pps_init +ffffffff81ac1710 t vlv_detach_power_sequencer +ffffffff81ac18e0 t vlv_steal_power_sequencer +ffffffff81ac1a10 t pps_init_delays +ffffffff81ac1eb0 t pps_init_registers +ffffffff81ac2240 T intel_pps_have_panel_power_or_vdd +ffffffff81ac2390 T intel_pps_encoder_reset +ffffffff81ac2530 t vlv_initial_power_sequencer_setup +ffffffff81ac2840 t pps_vdd_init +ffffffff81ac29f0 T intel_pps_init +ffffffff81ac2e60 t edp_panel_vdd_work +ffffffff81ac2f10 T intel_pps_init_late +ffffffff81ac3150 T intel_pps_unlock_regs_wa +ffffffff81ac3260 T intel_pps_setup +ffffffff81ac32d0 T assert_pps_unlocked +ffffffff81ac3560 t intel_pps_get_registers +ffffffff81ac3d70 t wait_panel_status +ffffffff81ac4180 t intel_pps_readout_hw_state +ffffffff81ac4330 t __delayed_work_tick +ffffffff81ac5000 T intel_psr_irq_handler +ffffffff81ac5640 t transcoder_name +ffffffff81ac5680 T intel_psr_init_dpcd +ffffffff81ac5920 T intel_psr_compute_config +ffffffff81ac5b00 t intel_psr2_config_valid +ffffffff81ac5f70 T intel_psr_get_config +ffffffff81ac6110 T intel_psr_disable +ffffffff81ac6220 t intel_psr_disable_locked +ffffffff81ac65a0 T intel_psr_pause +ffffffff81ac6790 t intel_psr_exit +ffffffff81ac6a40 T intel_psr_resume +ffffffff81ac6ad0 t intel_psr_activate +ffffffff81ac71e0 T intel_psr2_disable_plane_sel_fetch_arm +ffffffff81ac7250 T intel_psr2_program_plane_sel_fetch_arm +ffffffff81ac72f0 T intel_psr2_program_plane_sel_fetch_noarm +ffffffff81ac7460 T intel_psr2_program_trans_man_trk_ctl +ffffffff81ac7550 T intel_psr2_sel_fetch_update +ffffffff81ac7cc0 T intel_psr_pre_plane_update +ffffffff81ac7e90 t wm_optimization_wa +ffffffff81ac8020 T intel_psr_post_plane_update +ffffffff81ac8c20 T intel_psr_wait_for_idle_locked +ffffffff81ac8df0 T intel_psr_debug_set +ffffffff81ac9110 T intel_psr_invalidate +ffffffff81ac9350 T intel_psr_flush +ffffffff81ac9780 T intel_psr_init +ffffffff81ac98b0 t intel_psr_work +ffffffff81ac9a50 t tgl_dc3co_disable_work +ffffffff81ac9aa0 T intel_psr_short_pulse +ffffffff81ac9e60 T intel_psr_enabled +ffffffff81ac9ee0 T intel_psr_lock +ffffffff81ac9fa0 T intel_psr_unlock +ffffffff81aca060 T intel_psr_debugfs_register +ffffffff81aca090 T intel_psr_connector_debugfs_add +ffffffff81aca0c0 t _compute_psr2_sdp_prior_scanline_indication +ffffffff81aca180 t _compute_psr2_wake_times +ffffffff81aca270 t intel_psr2_sel_fetch_config_valid +ffffffff81aca300 t psr2_granularity_check +ffffffff81aca3f0 t tgl_psr2_disable_dc3co +ffffffff81aca500 t __delayed_work_tick +ffffffff81acb000 T intel_lookup_range_min_qp +ffffffff81acb110 T intel_lookup_range_max_qp +ffffffff81acc000 T intel_init_quirks +ffffffff81acc0f0 T intel_has_quirk +ffffffff81acc130 t quirk_ssc_force_disable +ffffffff81acc160 t quirk_invert_brightness +ffffffff81acc190 t quirk_backlight_present +ffffffff81acc1c0 t quirk_increase_t12_delay +ffffffff81acc1f0 t quirk_increase_ddi_disabled_time +ffffffff81acc220 t intel_dmi_reverse_brightness +ffffffff81acc270 t intel_dmi_no_pps_backlight +ffffffff81acd000 T intel_sdvo_port_enabled +ffffffff81acd0a0 T intel_sdvo_init +ffffffff81ace030 t intel_sdvo_compute_config +ffffffff81ace3f0 t pch_disable_sdvo +ffffffff81ace420 t pch_post_disable_sdvo +ffffffff81ace430 t intel_disable_sdvo +ffffffff81ace5a0 t intel_sdvo_pre_enable +ffffffff81acef20 t intel_enable_sdvo +ffffffff81acf0f0 t intel_sdvo_get_hw_state +ffffffff81acf1e0 t intel_sdvo_get_config +ffffffff81acf600 t intel_sdvo_set_target_input +ffffffff81acf670 t intel_sdvo_get_input_pixel_clock_range +ffffffff81acf710 t intel_sdvo_ddc_proxy_xfer +ffffffff81acf7c0 t intel_sdvo_ddc_proxy_func +ffffffff81acf7f0 t __intel_sdvo_write_cmd +ffffffff81acfca0 t proxy_lock_bus +ffffffff81acfcd0 t proxy_trylock_bus +ffffffff81acfd00 t proxy_unlock_bus +ffffffff81acfd30 t intel_sdvo_enc_destroy +ffffffff81acfd40 t intel_sdvo_set_output_timings_from_mode +ffffffff81acfe40 t intel_sdvo_get_preferred_input_mode +ffffffff81ad01d0 t intel_sdvo_get_dtd_from_mode +ffffffff81ad0350 t intel_sdvo_read_response +ffffffff81ad07f0 t intel_sdvo_get_value +ffffffff81ad0860 t intel_sdvo_write_sdvox +ffffffff81ad0a50 t intel_sdvo_write_infoframe +ffffffff81ad0c10 t intel_sdvo_read_infoframe +ffffffff81ad0e30 t intel_sdvo_hotplug +ffffffff81ad0e70 t intel_sdvo_connector_get_hw_state +ffffffff81ad0f00 t intel_sdvo_detect +ffffffff81ad11f0 t intel_sdvo_connector_register +ffffffff81ad1200 t intel_sdvo_connector_unregister +ffffffff81ad1210 t intel_sdvo_connector_duplicate_state +ffffffff81ad1290 t intel_sdvo_connector_atomic_set_property +ffffffff81ad1460 t intel_sdvo_connector_atomic_get_property +ffffffff81ad1680 t intel_sdvo_get_analog_edid +ffffffff81ad16b0 t intel_sdvo_connector_matches_edid +ffffffff81ad1740 t intel_sdvo_get_modes +ffffffff81ad19e0 t intel_sdvo_mode_valid +ffffffff81ad1af0 t intel_sdvo_atomic_check +ffffffff81ad1ba0 t intel_sdvo_create_enhance_property +ffffffff81ad3000 T intel_snps_phy_wait_for_calibration +ffffffff81ad30d0 T intel_snps_phy_update_psr_power_state +ffffffff81ad3190 T intel_snps_phy_set_signal_levels +ffffffff81ad33e0 T intel_mpllb_calc_state +ffffffff81ad3570 T intel_snps_phy_check_hdmi_link_rate +ffffffff81ad3610 T intel_mpllb_enable +ffffffff81ad3850 T intel_mpllb_disable +ffffffff81ad39c0 T intel_mpllb_calc_port_clock +ffffffff81ad3a90 T intel_mpllb_readout_hw_state +ffffffff81ad3c00 T intel_mpllb_state_verify +ffffffff81ad5000 T vlv_plane_min_cdclk +ffffffff81ad50f0 T ivb_plane_min_cdclk +ffffffff81ad51b0 T hsw_plane_min_cdclk +ffffffff81ad5250 T chv_plane_check_rotation +ffffffff81ad52c0 T intel_sprite_plane_create +ffffffff81ad5610 t vlv_sprite_update_noarm +ffffffff81ad5710 t vlv_sprite_update_arm +ffffffff81ad5db0 t vlv_sprite_disable_arm +ffffffff81ad5e40 t vlv_sprite_get_hw_state +ffffffff81ad5f10 t vlv_sprite_check +ffffffff81ad5fe0 t ivb_sprite_update_noarm +ffffffff81ad6140 t ivb_sprite_update_arm +ffffffff81ad6510 t ivb_sprite_disable_arm +ffffffff81ad65c0 t ivb_sprite_get_hw_state +ffffffff81ad6680 t g4x_sprite_check +ffffffff81ad6920 t hsw_sprite_max_stride +ffffffff81ad6970 t g4x_sprite_max_stride +ffffffff81ad69e0 t ivb_sprite_min_cdclk +ffffffff81ad6b20 t g4x_sprite_update_noarm +ffffffff81ad6c80 t g4x_sprite_update_arm +ffffffff81ad70c0 t g4x_sprite_disable_arm +ffffffff81ad7170 t g4x_sprite_get_hw_state +ffffffff81ad7230 t g4x_sprite_min_cdclk +ffffffff81ad7300 t vlv_sprite_ctl +ffffffff81ad74f0 t vlv_sprite_format_mod_supported +ffffffff81ad7620 t ivb_sprite_ctl +ffffffff81ad7850 t g4x_sprite_ctl +ffffffff81ad7a10 t snb_sprite_format_mod_supported +ffffffff81ad7b00 t g4x_sprite_format_mod_supported +ffffffff81ad8000 T intel_sprite_set_colorkey_ioctl +ffffffff81ad9000 T intel_tc_port_in_tbt_alt_mode +ffffffff81ad9070 T intel_tc_port_in_dp_alt_mode +ffffffff81ad90e0 T intel_tc_port_in_legacy_mode +ffffffff81ad9150 T intel_tc_cold_requires_aux_pw +ffffffff81ad91c0 T intel_tc_port_get_lane_mask +ffffffff81ad92f0 T intel_tc_port_get_pin_assignment_mask +ffffffff81ad9420 T intel_tc_port_fia_max_lane_count +ffffffff81ad9600 T intel_tc_port_set_fia_lane_count +ffffffff81ad97d0 T intel_tc_port_init_mode +ffffffff81ad9a00 t intel_tc_port_update_mode +ffffffff81ad9db0 T intel_tc_port_sanitize_mode +ffffffff81ada0e0 T intel_tc_port_connected_locked +ffffffff81ada240 T intel_tc_port_ref_held +ffffffff81ada2a0 T intel_tc_port_connected +ffffffff81ada310 T intel_tc_port_link_needs_reset +ffffffff81ada3c0 T intel_tc_port_link_reset +ffffffff81ada4c0 T intel_tc_port_link_cancel_reset_work +ffffffff81ada570 T intel_tc_port_lock +ffffffff81ada590 t __intel_tc_port_lock +ffffffff81ada6d0 T intel_tc_port_suspend +ffffffff81ada730 T intel_tc_port_unlock +ffffffff81ada7b0 T intel_tc_port_get_link +ffffffff81ada840 T intel_tc_port_put_link +ffffffff81ada8f0 T intel_tc_port_init +ffffffff81adab30 t kasprintf +ffffffff81adac00 t intel_tc_port_disconnect_phy_work +ffffffff81adac50 t intel_tc_port_link_reset_work +ffffffff81adaf50 T intel_tc_port_cleanup +ffffffff81adb010 t intel_tc_port_needs_reset +ffffffff81adb110 t tgl_tc_phy_cold_off_domain +ffffffff81adb140 t xelpdp_tc_phy_hpd_live_status +ffffffff81adb250 t adlp_tc_phy_is_ready +ffffffff81adb350 t xelpdp_tc_phy_is_owned +ffffffff81adb420 t xelpdp_tc_phy_get_hw_state +ffffffff81adb5a0 t xelpdp_tc_phy_connect +ffffffff81adb7f0 t xelpdp_tc_phy_disconnect +ffffffff81adb930 t adlp_tc_phy_init +ffffffff81adb9a0 t tc_phy_get_current_mode +ffffffff81adbcc0 t tc_phy_wait_for_ready +ffffffff81adbe30 t xelpdp_tc_phy_enable_tcss_power +ffffffff81adc080 t tc_phy_verify_legacy_or_dp_alt_mode +ffffffff81adc260 t xelpdp_tc_phy_wait_for_tcss_power +ffffffff81adc470 t adlp_tc_phy_cold_off_domain +ffffffff81adc4d0 t adlp_tc_phy_hpd_live_status +ffffffff81adc5d0 t adlp_tc_phy_is_owned +ffffffff81adc690 t adlp_tc_phy_get_hw_state +ffffffff81adc720 t adlp_tc_phy_connect +ffffffff81adca10 t adlp_tc_phy_disconnect +ffffffff81adcb70 t icl_tc_phy_hpd_live_status +ffffffff81adccd0 t icl_tc_phy_is_ready +ffffffff81adcde0 t icl_tc_phy_is_owned +ffffffff81adcef0 t icl_tc_phy_get_hw_state +ffffffff81adcf80 t icl_tc_phy_connect +ffffffff81add0f0 t icl_tc_phy_disconnect +ffffffff81add170 t tgl_tc_phy_init +ffffffff81add2a0 t icl_tc_phy_take_ownership +ffffffff81add410 t icl_tc_phy_cold_off_domain +ffffffff81add470 t icl_tc_phy_init +ffffffff81add4d0 t __delayed_work_tick +ffffffff81ade000 T intel_tv_init +ffffffff81ade3f0 t intel_tv_compute_config +ffffffff81ade8a0 t intel_tv_get_config +ffffffff81aded60 t intel_tv_pre_enable +ffffffff81adf680 t intel_enable_tv +ffffffff81adf6e0 t intel_disable_tv +ffffffff81adf740 t intel_tv_get_hw_state +ffffffff81adf7a0 t intel_tv_connector_duplicate_state +ffffffff81adf820 t intel_tv_mode_to_mode +ffffffff81adf970 t intel_tv_get_modes +ffffffff81adfcb0 t intel_tv_detect +ffffffff81ae0140 t intel_tv_mode_valid +ffffffff81ae01f0 t intel_tv_atomic_check +ffffffff81ae1000 T i915_get_vblank_counter +ffffffff81ae11e0 T g4x_get_vblank_counter +ffffffff81ae1270 T intel_crtc_get_vblank_timestamp +ffffffff81ae1290 t i915_get_crtc_scanoutpos +ffffffff81ae1690 T intel_get_crtc_scanline +ffffffff81ae1700 t __intel_get_crtc_scanline +ffffffff81ae1950 T intel_wait_for_pipe_scanline_stopped +ffffffff81ae1960 t wait_for_pipe_scanline_moving +ffffffff81ae1bc0 T intel_wait_for_pipe_scanline_moving +ffffffff81ae1be0 T intel_crtc_update_active_timings +ffffffff81ae2000 T intel_dsc_source_support +ffffffff81ae2050 T intel_dsc_compute_params +ffffffff81ae2650 T intel_dsc_power_domain +ffffffff81ae2700 T intel_dsc_get_num_vdsc_instances +ffffffff81ae2750 T intel_dsc_dsi_pps_write +ffffffff81ae29f0 T intel_dsc_dp_pps_write +ffffffff81ae2ae0 T intel_uncompressed_joiner_enable +ffffffff81ae2c00 T intel_dsc_enable +ffffffff81ae4600 T intel_dsc_disable +ffffffff81ae4780 T intel_dsc_get_config +ffffffff81ae5000 T intel_vga_disable +ffffffff81ae5120 T intel_vga_redisable_power_on +ffffffff81ae51c0 T intel_vga_redisable +ffffffff81ae5280 T intel_vga_reset_io_mem +ffffffff81ae52e0 T intel_vga_register +ffffffff81ae5310 T intel_vga_unregister +ffffffff81ae6000 T intel_vrr_is_capable +ffffffff81ae6080 T intel_vrr_check_modeset +ffffffff81ae6110 T intel_vrr_vmin_vblank_start +ffffffff81ae6170 T intel_vrr_vmax_vblank_start +ffffffff81ae61d0 T intel_vrr_compute_config +ffffffff81ae6350 T intel_vrr_set_transcoder_timings +ffffffff81ae6530 T intel_vrr_send_push +ffffffff81ae65b0 T intel_vrr_is_push_sent +ffffffff81ae6640 T intel_vrr_enable +ffffffff81ae6760 T intel_vrr_disable +ffffffff81ae68a0 T intel_vrr_get_config +ffffffff81ae7000 T intel_update_watermarks +ffffffff81ae7040 T intel_compute_pipe_wm +ffffffff81ae7090 T intel_compute_intermediate_wm +ffffffff81ae7120 T intel_initial_watermarks +ffffffff81ae7170 T intel_atomic_update_watermarks +ffffffff81ae71b0 T intel_optimize_watermarks +ffffffff81ae71f0 T intel_compute_global_watermarks +ffffffff81ae7240 T intel_wm_get_hw_state +ffffffff81ae7280 T intel_wm_plane_visible +ffffffff81ae72e0 T intel_print_wm_latency +ffffffff81ae73f0 T intel_wm_init +ffffffff81ae7410 T intel_wm_debugfs_register +ffffffff81ae8000 T skl_update_scaler_crtc +ffffffff81ae80b0 t skl_update_scaler +ffffffff81ae83f0 T skl_update_scaler_plane +ffffffff81ae87f0 T intel_atomic_setup_scalers +ffffffff81ae8d50 T skl_pfit_enable +ffffffff81ae9240 T skl_program_plane_scaler +ffffffff81ae9930 T skl_detach_scalers +ffffffff81ae9a90 T skl_scaler_disable +ffffffff81ae9bc0 T skl_scaler_get_config +ffffffff81aea000 T skl_format_to_fourcc +ffffffff81aea180 T icl_is_nv12_y_plane +ffffffff81aea1f0 T icl_hdr_plane_mask +ffffffff81aea220 T icl_is_hdr_plane +ffffffff81aea260 T skl_calc_main_surface_offset +ffffffff81aea4a0 T skl_universal_plane_create +ffffffff81aeace0 t icl_plane_min_width +ffffffff81aeae70 t icl_hdr_plane_max_width +ffffffff81aeaec0 t icl_sdr_plane_max_width +ffffffff81aeaef0 t icl_plane_max_height +ffffffff81aeaf20 t icl_plane_min_cdclk +ffffffff81aeaf60 t glk_plane_max_width +ffffffff81aeb010 t skl_plane_max_height +ffffffff81aeb040 t glk_plane_min_cdclk +ffffffff81aeb0b0 t skl_plane_max_width +ffffffff81aeb180 t skl_plane_min_cdclk +ffffffff81aeb1f0 t skl_plane_max_stride +ffffffff81aeb290 t icl_plane_update_noarm +ffffffff81aebb40 t icl_plane_update_arm +ffffffff81aebce0 t icl_plane_disable_arm +ffffffff81aebdf0 t skl_plane_update_noarm +ffffffff81aebf90 t skl_plane_update_arm +ffffffff81aec2b0 t skl_plane_disable_arm +ffffffff81aec360 t skl_plane_get_hw_state +ffffffff81aec430 t skl_plane_check +ffffffff81aed060 t skl_plane_async_flip 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skl_watermark_ipc_enabled +ffffffff81af0ca0 T skl_watermark_ipc_update +ffffffff81af0d50 T skl_watermark_ipc_init +ffffffff81af0e20 T skl_wm_init +ffffffff81af1650 T intel_atomic_get_dbuf_state +ffffffff81af1670 T intel_dbuf_init +ffffffff81af16e0 T intel_dbuf_pre_plane_update +ffffffff81af19b0 T intel_dbuf_post_plane_update +ffffffff81af1a80 T intel_mbus_dbox_update +ffffffff81af1cf0 T skl_watermark_debugfs_register +ffffffff81af1d20 t skl_sagv_disable +ffffffff81af1e40 t skl_compute_wm +ffffffff81af5130 t skl_wm_get_hw_state_and_sanitize +ffffffff81af5920 t skl_build_plane_wm_single +ffffffff81af5cb0 t skl_compute_wm_params +ffffffff81af6080 t skl_compute_plane_wm +ffffffff81af64b0 t skl_compute_dbuf_slices +ffffffff81af69b0 t skl_ddb_entry_for_slices +ffffffff81af6af0 t intel_dbuf_duplicate_state +ffffffff81af6b80 t intel_dbuf_destroy_state +ffffffff81af7000 T pixel_format_from_register_bits +ffffffff81af7060 T vlv_dsi_wait_for_fifo_empty +ffffffff81af7120 T vlv_dsi_init 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i915_gem_object_set_to_cpu_domain +ffffffff81b08f30 T i915_gem_set_domain_ioctl +ffffffff81b09120 T i915_gem_object_prepare_read +ffffffff81b09270 T i915_gem_object_prepare_write +ffffffff81b0a000 T i915_gem_execbuffer2_ioctl +ffffffff81b0aba0 t eb_select_context +ffffffff81b0ac20 t eb_select_engine +ffffffff81b0b0a0 t eb_lookup_vmas +ffffffff81b0b7e0 t eb_release_vmas +ffffffff81b0bb20 t eb_relocate_parse +ffffffff81b0bc40 t eb_capture_stage +ffffffff81b0bd80 t eb_requests_create +ffffffff81b0c160 t eb_submit +ffffffff81b0c5c0 t eb_requests_get +ffffffff81b0c630 t eb_requests_add +ffffffff81b0c7c0 t signal_fence_array +ffffffff81b0c870 t eb_requests_put +ffffffff81b0c8e0 t eb_put_engine +ffffffff81b0ca30 t parse_timeline_fences +ffffffff81b0ce30 t eb_pin_engine +ffffffff81b0d140 t eb_validate_vmas +ffffffff81b0da30 t eb_relocate_vma +ffffffff81b0dc70 t eb_parse +ffffffff81b0e000 t eb_relocate_parse_slow +ffffffff81b0e6d0 t eb_pin_timeline +ffffffff81b0e920 t i915_gem_object_lock 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i915_gem_object_attach_phys +ffffffff81b18440 t i915_gem_object_shmem_to_phys +ffffffff81b19000 T i915_gem_suspend +ffffffff81b19060 T i915_gem_backup_suspend +ffffffff81b191e0 t lmem_suspend +ffffffff81b19300 T i915_gem_suspend_late +ffffffff81b19440 T i915_gem_freeze +ffffffff81b19480 T i915_gem_freeze_late +ffffffff81b19550 T i915_gem_resume +ffffffff81b196a0 t lmem_restore +ffffffff81b1a000 T i915_gem_object_init_memory_region +ffffffff81b1a070 T i915_gem_object_release_memory_region +ffffffff81b1a0d0 T i915_gem_object_create_region +ffffffff81b1a0f0 t __i915_gem_object_create_region +ffffffff81b1a260 T i915_gem_object_create_region_at +ffffffff81b1a300 T i915_gem_process_region +ffffffff81b1b000 T shmem_sg_free_table +ffffffff81b1b100 T shmem_sg_alloc_table +ffffffff81b1b250 T __shmem_writeback +ffffffff81b1b270 T __i915_gem_object_release_shmem +ffffffff81b1b330 T i915_gem_object_put_pages_shmem +ffffffff81b1b440 t shmem_get_pages +ffffffff81b1b590 t shmem_put_pages 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i915_gem_object_make_shrinkable +ffffffff81b1cd50 T i915_gem_object_make_purgeable +ffffffff81b1d000 T i915_gem_stolen_insert_node_in_range +ffffffff81b1d0d0 T i915_gem_stolen_insert_node +ffffffff81b1d180 T i915_gem_stolen_remove_node +ffffffff81b1d1c0 T i915_gem_object_create_stolen +ffffffff81b1d1e0 T i915_gem_stolen_lmem_setup +ffffffff81b1d4f0 T i915_gem_stolen_smem_setup +ffffffff81b1d590 T i915_gem_object_is_stolen +ffffffff81b1d5d0 T i915_gem_stolen_initialized +ffffffff81b1d610 T i915_gem_stolen_area_address +ffffffff81b1d640 T i915_gem_stolen_area_size +ffffffff81b1d680 T i915_gem_stolen_node_address +ffffffff81b1d6c0 T i915_gem_stolen_node_offset +ffffffff81b1d6f0 T i915_gem_stolen_node_allocated +ffffffff81b1d720 T i915_gem_stolen_node_size +ffffffff81b1d750 t init_stolen_lmem +ffffffff81b1d7f0 t release_stolen_lmem +ffffffff81b1d860 t _i915_gem_object_stolen_init +ffffffff81b1dc60 t i915_gem_init_stolen +ffffffff81b1e4b0 t init_stolen_smem +ffffffff81b1e510 t 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i915_gemfs_init +ffffffff81b28030 T i915_gemfs_fini +ffffffff81b29000 T inteldrm_gmch_match +ffffffff81b29060 T i915_alloc_ifp +ffffffff81b29180 T i965_alloc_ifp +ffffffff81b292e0 T intel_gtt_chipset_setup +ffffffff81b29430 T intel_gmch_enable_gtt +ffffffff81b29480 T intel_gmch_probe +ffffffff81b294b0 T intel_gmch_gtt_get +ffffffff81b29500 T intel_gmch_gtt_flush +ffffffff81b29600 T intel_gmch_remove +ffffffff81b29630 T intel_gmch_gtt_insert_sg_entries +ffffffff81b297d0 T intel_gmch_gtt_insert_page +ffffffff81b29900 T intel_gmch_gtt_clear_range +ffffffff81b2a000 T gen2_emit_flush +ffffffff81b2a0f0 T gen4_emit_flush_rcs +ffffffff81b2a240 T gen4_emit_flush_vcs +ffffffff81b2a290 T gen3_emit_breadcrumb +ffffffff81b2a450 T gen5_emit_breadcrumb +ffffffff81b2a590 T i830_emit_bb_start +ffffffff81b2a6c0 T gen3_emit_bb_start +ffffffff81b2a730 T gen4_emit_bb_start +ffffffff81b2a7a0 T gen2_irq_enable +ffffffff81b2a810 T gen2_irq_disable +ffffffff81b2a860 T gen3_irq_enable +ffffffff81b2a8d0 T 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gen7_blt_get_cmd_length_mask +ffffffff81bb5890 t gen9_blt_get_cmd_length_mask +ffffffff81bb5900 T intel_engine_cleanup_cmd_parser +ffffffff81bb59d0 T intel_engine_cmd_parser +ffffffff81bb6580 T i915_cmd_parser_get_version +ffffffff81bb7000 T i915_fence_context_timeout +ffffffff81bb8000 T i915_deps_init +ffffffff81bb8060 T i915_deps_fini +ffffffff81bb80f0 T i915_deps_sync +ffffffff81bb81a0 T i915_deps_add_dependency +ffffffff81bb83f0 T i915_deps_add_resv +ffffffff81bb9000 T i915_print_iommu_status +ffffffff81bb9050 T i915_driver_probe +ffffffff81bb98d0 t i915_driver_register +ffffffff81bb99c0 T inteldrm_init_backlight +ffffffff81bb9a30 t i915_welcome_messages +ffffffff81bb9bb0 T i915_driver_remove +ffffffff81bb9c90 T i915_driver_shutdown +ffffffff81bb9e30 T i915_driver_resume_switcheroo +ffffffff81bb9e90 t i915_drm_resume_early +ffffffff81bb9f80 t i915_drm_resume +ffffffff81bba1c0 T intagpsubmatch +ffffffff81bba210 T intagp_print +ffffffff81bba260 T inteldrm_wsioctl +ffffffff81bba440 T inteldrm_wsmmap +ffffffff81bba470 T inteldrm_alloc_screen +ffffffff81bba4a0 T inteldrm_free_screen +ffffffff81bba4c0 T inteldrm_show_screen +ffffffff81bba590 T inteldrm_load_font +ffffffff81bba5b0 T inteldrm_list_font +ffffffff81bba5d0 T inteldrm_scrollback +ffffffff81bba5f0 T inteldrm_getchar +ffffffff81bba610 T inteldrm_burner +ffffffff81bba6a0 T inteldrm_enter_ddb +ffffffff81bba700 T inteldrm_doswitch +ffffffff81bba780 T inteldrm_burner_cb +ffffffff81bba7b0 T inteldrm_backlight_update_status +ffffffff81bba810 T inteldrm_backlight_get_brightness +ffffffff81bba860 T inteldrm_match +ffffffff81bba8f0 T inteldrm_attach +ffffffff81bbacf0 T inteldrm_detach +ffffffff81bbad20 T inteldrm_activate +ffffffff81bbb030 T inteldrm_intr +ffffffff81bbb070 T inteldrm_attachhook +ffffffff81bbb2d0 T inteldrm_forcedetach +ffffffff81bbb310 T inteldrm_native_backlight +ffffffff81bbb440 T inteldrm_firmware_backlight +ffffffff81bbb5c0 t i915_pcode_init +ffffffff81bbb680 t i915_driver_open +ffffffff81bbb6a0 t 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i915_gem_driver_register +ffffffff81bbf550 T i915_gem_driver_unregister +ffffffff81bbf560 T i915_gem_driver_remove +ffffffff81bbf5c0 T i915_gem_driver_release +ffffffff81bbf6b0 T i915_gem_init_early +ffffffff81bbf730 T i915_gem_cleanup_early +ffffffff81bbf7b0 T i915_gem_open +ffffffff81bbf8c0 t i915_gem_gtt_prepare +ffffffff81bc0000 T i915_gem_evict_something +ffffffff81bc0440 t ungrab_vma +ffffffff81bc0570 t grab_vma +ffffffff81bc0690 T i915_gem_evict_for_node +ffffffff81bc08d0 T i915_gem_evict_vm +ffffffff81bc1000 T i915_gem_gtt_prepare_pages +ffffffff81bc1030 T i915_gem_gtt_finish_pages +ffffffff81bc1090 T i915_gem_gtt_reserve +ffffffff81bc1140 T i915_gem_gtt_insert +ffffffff81bc2000 T i915_gem_ww_ctx_init +ffffffff81bc2060 T i915_gem_ww_unlock_single +ffffffff81bc21a0 T i915_gem_ww_ctx_fini +ffffffff81bc2210 t i915_gem_ww_ctx_unlock_all +ffffffff81bc2370 T i915_gem_ww_ctx_backoff +ffffffff81bc3000 T i915_getparam_ioctl +ffffffff81bc4000 T intel_gpu_error_find_batch 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i915_memcpy_init_early +ffffffff81bcb000 T i915_mitigate_clear_residuals +ffffffff81bcc000 T i915_init +ffffffff81bcc220 t i915_check_nomodeset +ffffffff81bcc280 t i915_mock_selftests +ffffffff81bcc2b0 t i915_pmu_init +ffffffff81bcc2e0 t i915_pmu_exit +ffffffff81bcd000 T i915_params_dump +ffffffff81bcd670 T i915_params_copy +ffffffff81bcd870 T i915_params_free +ffffffff81bce000 T i915_pci_register_driver +ffffffff81bce030 T i915_pci_unregister_driver +ffffffff81bcf000 T i915_oa_config_release +ffffffff81bcf060 T i915_perf_get_oa_config +ffffffff81bcf0c0 T i915_perf_oa_timestamp_frequency +ffffffff81bcf170 T i915_oa_init_reg_state +ffffffff81bcf260 T i915_perf_open_ioctl +ffffffff81bcfa80 T i915_perf_register +ffffffff81bcfab0 T i915_perf_unregister +ffffffff81bcfb20 T i915_perf_add_config_ioctl +ffffffff81bcfb70 T i915_perf_remove_config_ioctl +ffffffff81bcfbe0 T i915_perf_init +ffffffff81bd02c0 t gen7_is_valid_b_counter_addr +ffffffff81bd0310 t hsw_is_valid_mux_addr +ffffffff81bd0390 t hsw_enable_metric_set +ffffffff81bd0450 t hsw_disable_metric_set +ffffffff81bd0520 t gen7_oa_enable +ffffffff81bd0690 t gen7_oa_disable +ffffffff81bd0750 t gen7_oa_read +ffffffff81bd0bb0 t gen7_oa_hw_tail_read +ffffffff81bd0c00 t gen8_oa_read +ffffffff81bd1230 t gen8_is_valid_mux_addr +ffffffff81bd12b0 t gen8_is_valid_flex_addr +ffffffff81bd1330 t chv_is_valid_mux_addr +ffffffff81bd13b0 t gen8_oa_enable +ffffffff81bd14f0 t gen8_oa_disable +ffffffff81bd15b0 t gen8_enable_metric_set +ffffffff81bd1670 t gen8_disable_metric_set +ffffffff81bd16d0 t gen8_oa_hw_tail_read +ffffffff81bd1720 t gen11_is_valid_mux_addr +ffffffff81bd17e0 t gen11_disable_metric_set +ffffffff81bd1840 t xehp_is_valid_b_counter_addr +ffffffff81bd1910 t gen12_is_valid_b_counter_addr +ffffffff81bd1960 t gen12_is_valid_mux_addr +ffffffff81bd19f0 t gen12_oa_enable +ffffffff81bd1b90 t gen12_oa_disable +ffffffff81bd1ce0 t gen12_enable_metric_set +ffffffff81bd1ed0 t gen12_disable_metric_set +ffffffff81bd2020 t gen12_oa_hw_tail_read +ffffffff81bd2080 T i915_perf_sysctl_register +ffffffff81bd20b0 T i915_perf_sysctl_unregister +ffffffff81bd20e0 T i915_perf_fini +ffffffff81bd2200 t destroy_config +ffffffff81bd2290 T i915_perf_ioctl_version +ffffffff81bd2390 t get_sseu_config +ffffffff81bd23e0 t emit_oa_config +ffffffff81bd2ab0 t i915_gem_object_lock +ffffffff81bd2cc0 t append_oa_status +ffffffff81bd2d40 t append_oa_sample +ffffffff81bd2ea0 t lrc_configure_all_contexts +ffffffff81bd3050 t oa_configure_all_contexts +ffffffff81bd3370 t gen8_modify_self +ffffffff81bd3540 t gen8_modify_context +ffffffff81bd36f0 t gen12_configure_oar_context +ffffffff81bd4000 T i915_query_ioctl +ffffffff81bd4100 t query_topology_info +ffffffff81bd4150 t query_engine_info +ffffffff81bd4390 t query_perf_config +ffffffff81bd4690 t query_memregion_info +ffffffff81bd4920 t query_hwconfig_blob +ffffffff81bd49a0 t query_geometry_subslices +ffffffff81bd4a30 t fill_topology_info +ffffffff81bd4bd0 t query_perf_config_data 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gen6_init_clock_gating +ffffffff81bec1f0 t ilk_init_clock_gating +ffffffff81bec3d0 t g4x_init_clock_gating +ffffffff81bec490 t i965gm_init_clock_gating +ffffffff81bec560 t i965g_init_clock_gating +ffffffff81bec5e0 t gen3_init_clock_gating +ffffffff81bec6e0 t i85x_init_clock_gating +ffffffff81bec780 t i830_init_clock_gating +ffffffff81bed000 T intel_platform_name +ffffffff81bed090 T intel_device_info_print +ffffffff81beda20 T intel_device_info_runtime_init_early +ffffffff81bedef0 T intel_device_info_runtime_init +ffffffff81bedfb0 T intel_device_info_driver_create +ffffffff81bee0c0 T intel_driver_caps_print +ffffffff81bef000 T intel_memory_region_lookup +ffffffff81bef0e0 T intel_memory_region_by_type +ffffffff81bef1a0 T intel_memory_region_reserve +ffffffff81bef1c0 T intel_memory_region_debug +ffffffff81bef220 T intel_memory_region_create +ffffffff81bef390 T intel_memory_region_set_name +ffffffff81bef410 T intel_memory_region_avail +ffffffff81bef490 T intel_memory_region_destroy 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atom_execute_table_scratch_unlocked +ffffffff81c070a0 t atom_execute_table_locked +ffffffff81c073b0 T atom_execute_table +ffffffff81c07460 T atom_parse +ffffffff81c07610 T atom_destroy +ffffffff81c07650 T atom_asic_init +ffffffff81c07860 t get_u32 +ffffffff81c078c0 T atom_parse_data_header +ffffffff81c07960 T atom_parse_cmd_header +ffffffff81c079e0 T atom_allocate_fb_scratch +ffffffff81c07ab0 t atom_op_move +ffffffff81c07c80 t atom_op_and +ffffffff81c07e60 t atom_op_or +ffffffff81c08040 t atom_op_shift_left +ffffffff81c08220 t atom_op_shift_right +ffffffff81c08400 t atom_op_mul +ffffffff81c08550 t atom_op_div +ffffffff81c086c0 t atom_op_add +ffffffff81c088a0 t atom_op_sub +ffffffff81c08a80 t atom_op_setport +ffffffff81c08c00 t atom_op_setregblock +ffffffff81c08cc0 t atom_op_setfbbase +ffffffff81c08d80 t atom_op_compare +ffffffff81c08f60 t atom_op_switch +ffffffff81c09190 t atom_op_jump +ffffffff81c09400 t atom_op_test +ffffffff81c095c0 t atom_op_delay +ffffffff81c096a0 t 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atombios_crtc_mode_set +ffffffff81c0e690 T radeon_atombios_init_crtc +ffffffff81c0e780 t radeon_bo_reserve +ffffffff81c0e8f0 t radeon_bo_unreserve +ffffffff81c0e9d0 t atombios_disable_ss +ffffffff81c0eab0 t atombios_crtc_program_pll +ffffffff81c0ed60 t atombios_crtc_prepare +ffffffff81c0ee20 t atombios_crtc_commit +ffffffff81c0eea0 t atombios_crtc_mode_fixup +ffffffff81c0fbb0 t atombios_crtc_disable +ffffffff81c0fe10 t radeon_get_shared_dp_ppll +ffffffff81c0ff00 t radeon_get_shared_nondp_ppll +ffffffff81c11000 T radeon_atom_copy_swap +ffffffff81c11020 T radeon_dp_aux_init +ffffffff81c11110 t radeon_dp_aux_transfer_atom +ffffffff81c112e0 T radeon_dp_getsinktype +ffffffff81c11350 T radeon_dp_getdpcd +ffffffff81c114c0 T radeon_dp_get_panel_mode +ffffffff81c115d0 T radeon_dp_set_link_config +ffffffff81c11650 t radeon_dp_get_dp_link_config +ffffffff81c117e0 T radeon_dp_mode_valid_helper +ffffffff81c11890 T radeon_dp_needs_link_train +ffffffff81c11900 T radeon_dp_set_rx_power_state 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radeon_process_i2c_ch +ffffffff81c18310 T radeon_atom_hw_i2c_func +ffffffff81c19000 T btc_get_max_clock_from_voltage_dependency_table +ffffffff81c190d0 T btc_apply_voltage_dependency_rules +ffffffff81c19140 T btc_skip_blacklist_clocks +ffffffff81c19230 T btc_adjust_clock_combinations +ffffffff81c19360 T btc_apply_voltage_delta_rules +ffffffff81c19480 T btc_program_mgcg_hw_sequence +ffffffff81c19580 T btc_dpm_enabled +ffffffff81c19590 T btc_notify_uvd_to_smc +ffffffff81c19600 T btc_reset_to_default +ffffffff81c19650 T btc_read_arb_registers +ffffffff81c196e0 T btc_dpm_vblank_too_short +ffffffff81c19750 T btc_dpm_pre_set_power_state +ffffffff81c1a970 T btc_dpm_set_power_state +ffffffff81c1aca0 t btc_set_power_state_conditionally_enable_ulv +ffffffff81c1add0 T btc_dpm_post_set_power_state +ffffffff81c1aef0 t btc_update_current_ps +ffffffff81c1aff0 T btc_dpm_enable +ffffffff81c1bed0 t btc_cg_clock_gating_enable +ffffffff81c1c000 t btc_mg_clock_gating_enable +ffffffff81c1c120 t btc_ls_clock_gating_enable +ffffffff81c1c250 t btc_init_stutter_mode +ffffffff81c1c2d0 T btc_dpm_disable +ffffffff81c1c5b0 T btc_dpm_setup_asic +ffffffff81c1c690 T btc_dpm_init +ffffffff81c1ca80 T btc_dpm_fini +ffffffff81c1cb30 T btc_dpm_debugfs_print_current_performance_level +ffffffff81c1cb80 T btc_dpm_get_current_sclk +ffffffff81c1cc00 T btc_dpm_get_current_mclk +ffffffff81c1cc80 T btc_dpm_get_sclk +ffffffff81c1ccd0 T btc_dpm_get_mclk +ffffffff81c1d000 T ci_dpm_powergate_uvd +ffffffff81c1d380 T ci_dpm_vblank_too_short +ffffffff81c1d410 T ci_fan_ctrl_get_fan_speed_percent +ffffffff81c1d4b0 T ci_fan_ctrl_set_fan_speed_percent +ffffffff81c1d580 T ci_fan_ctrl_set_mode +ffffffff81c1d720 t ci_fan_ctrl_set_static_mode +ffffffff81c1d7e0 t ci_thermal_start_smc_fan_control +ffffffff81c1da20 T ci_fan_ctrl_get_mode +ffffffff81c1da80 T ci_dpm_force_performance_level +ffffffff81c1e310 t ci_upload_dpm_level_enable_mask +ffffffff81c1e640 T ci_dpm_pre_set_power_state +ffffffff81c1e930 T ci_dpm_post_set_power_state +ffffffff81c1ea00 T ci_dpm_setup_asic +ffffffff81c1ec00 T ci_dpm_enable +ffffffff81c204d0 t ci_init_smc_table +ffffffff81c213c0 t ci_init_arb_table_index +ffffffff81c21450 t ci_populate_initial_mc_reg_table +ffffffff81c21690 t ci_populate_pm_base +ffffffff81c21a00 t ci_dpm_start_smc +ffffffff81c21a80 t ci_enable_vr_hot_gpio_interrupt +ffffffff81c21b20 t ci_notify_smc_display_change +ffffffff81c21bf0 t ci_enable_sclk_control +ffffffff81c21c20 t ci_enable_ulv +ffffffff81c21d70 t ci_enable_ds_master_switch +ffffffff81c21f60 t ci_start_dpm +ffffffff81c22150 t ci_enable_didt +ffffffff81c22400 t ci_enable_smc_cac +ffffffff81c22590 t ci_enable_power_containment +ffffffff81c22a10 t ci_power_control_set_level +ffffffff81c22b20 t ci_enable_auto_throttle_source +ffffffff81c22c00 t ci_enable_thermal_based_sclk_dpm +ffffffff81c22d50 t ci_thermal_start_thermal_controller +ffffffff81c23050 T ci_dpm_late_enable +ffffffff81c230f0 T ci_dpm_disable +ffffffff81c237e0 T ci_dpm_set_power_state +ffffffff81c24450 t ci_update_sclk_t +ffffffff81c244c0 t ci_update_and_upload_mc_reg_table +ffffffff81c24670 t ci_unfreeze_sclk_mclk_dpm +ffffffff81c24820 t ci_notify_link_speed_change_after_state_change +ffffffff81c24950 T ci_dpm_display_configuration_changed +ffffffff81c24ae0 T ci_dpm_fini +ffffffff81c24b90 T ci_dpm_init +ffffffff81c259f0 t ci_initialize_powertune_defaults +ffffffff81c25ae0 t ci_get_leakage_voltages +ffffffff81c25c90 t ci_patch_dependency_tables_with_leakage +ffffffff81c26300 t ci_set_private_data_variables_based_on_pptable +ffffffff81c26410 T ci_dpm_debugfs_print_current_performance_level +ffffffff81c26550 T ci_dpm_print_power_state +ffffffff81c26610 T ci_dpm_get_current_sclk +ffffffff81c266e0 T ci_dpm_get_current_mclk +ffffffff81c267b0 T ci_dpm_get_sclk +ffffffff81c26800 T ci_dpm_get_mclk +ffffffff81c26850 t ci_set_valid_flag +ffffffff81c268f0 t ci_populate_all_graphic_levels +ffffffff81c26e80 t ci_populate_all_memory_levels +ffffffff81c27780 t ci_populate_smc_vce_level +ffffffff81c278a0 t ci_populate_smc_acp_level +ffffffff81c279a0 t ci_populate_smc_samu_level +ffffffff81c27aa0 t ci_do_program_memory_timing_parameters +ffffffff81c27cc0 t ci_populate_smc_uvd_level +ffffffff81c27e10 t ci_populate_smc_initial_state +ffffffff81c27eb0 t ci_populate_bapm_parameters_in_dpm_table +ffffffff81c28040 t ci_populate_smc_voltage_table +ffffffff81c28160 t ci_min_max_v_gnbl_pm_lid_from_bapm_vddc +ffffffff81c283c0 t ci_enable_sclk_mclk_dpm +ffffffff81c28730 t ci_thermal_enable_alert +ffffffff81c288e0 t ci_enable_vce_dpm +ffffffff81c29000 T ci_copy_bytes_to_smc +ffffffff81c29240 T ci_start_smc +ffffffff81c29280 T ci_reset_smc +ffffffff81c292c0 T ci_program_jump_on_start +ffffffff81c292f0 T ci_stop_smc_clock +ffffffff81c29330 T ci_start_smc_clock +ffffffff81c29370 T ci_is_smc_running +ffffffff81c293e0 T ci_load_smc_ucode +ffffffff81c29570 T ci_read_smc_sram_dword +ffffffff81c29640 T ci_write_smc_sram_dword +ffffffff81c2a000 T cik_get_allowed_info_register +ffffffff81c2a0a0 T cik_didt_rreg +ffffffff81c2a140 T cik_didt_wreg +ffffffff81c2a1c0 T ci_get_temp +ffffffff81c2a210 T kv_get_temp +ffffffff81c2a260 T cik_pciep_rreg +ffffffff81c2a2e0 T cik_pciep_wreg +ffffffff81c2a350 T cik_get_xclk +ffffffff81c2a3c0 T cik_mm_rdoorbell +ffffffff81c2a420 T cik_mm_wdoorbell +ffffffff81c2a470 T ci_mc_load_microcode +ffffffff81c2a7b0 T cik_ring_test +ffffffff81c2aa50 T cik_fence_gfx_ring_emit +ffffffff81c2ae40 T cik_fence_compute_ring_emit +ffffffff81c2b0c0 T cik_semaphore_ring_emit +ffffffff81c2b280 T cik_copy_cpdma +ffffffff81c2b6d0 T cik_ring_ib_execute +ffffffff81c2bc70 T cik_ib_test +ffffffff81c2bf50 T cik_gfx_get_rptr +ffffffff81c2bfb0 T cik_gfx_get_wptr +ffffffff81c2bff0 T cik_gfx_set_wptr +ffffffff81c2c030 T cik_compute_get_rptr +ffffffff81c2c110 T cik_compute_get_wptr +ffffffff81c2c1f0 T cik_compute_set_wptr +ffffffff81c2c270 T cik_gpu_check_soft_reset +ffffffff81c2c3e0 T cik_asic_reset +ffffffff81c2c7f0 t cik_gpu_pci_config_reset +ffffffff81c2d000 T cik_gfx_is_lockup +ffffffff81c2d070 T cik_pcie_gart_tlb_flush +ffffffff81c2d0c0 T cik_ib_parse +ffffffff81c2d0f0 T cik_vm_init +ffffffff81c2d150 T cik_vm_fini +ffffffff81c2d180 T cik_vm_flush +ffffffff81c2ddf0 T cik_enter_rlc_safe_mode +ffffffff81c2dee0 T cik_exit_rlc_safe_mode +ffffffff81c2df20 T cik_update_cg +ffffffff81c2e420 t cik_enable_mgcg +ffffffff81c2e940 t cik_enable_cgcg +ffffffff81c2ecb0 T cik_init_cp_pg_table +ffffffff81c2ef20 T cik_get_csb_size +ffffffff81c2efb0 T cik_get_csb_buffer +ffffffff81c2f140 T cik_irq_set +ffffffff81c2fec0 t cik_disable_interrupt_state +ffffffff81c30380 T cik_irq_process +ffffffff81c31b50 t cik_irq_ack +ffffffff81c324d0 T cik_resume +ffffffff81c32560 t cik_init_golden_registers +ffffffff81c32720 t cik_startup +ffffffff81c354f0 T cik_suspend +ffffffff81c358e0 T cik_init +ffffffff81c35e00 t cik_init_microcode +ffffffff81c36b50 t cik_uvd_init +ffffffff81c36c00 t cik_vce_init +ffffffff81c36cd0 t cik_cp_fini +ffffffff81c36d50 t cik_irq_fini +ffffffff81c36e60 t cik_mec_fini +ffffffff81c36f10 t cik_pcie_gart_fini +ffffffff81c37010 T cik_fini +ffffffff81c37330 T dce8_program_fmt +ffffffff81c37460 T dce8_bandwidth_update +ffffffff81c38070 T cik_get_gpu_clock_counter +ffffffff81c38130 T cik_set_uvd_clocks +ffffffff81c381b0 t cik_set_uvd_clock +ffffffff81c38320 T cik_set_vce_clocks +ffffffff81c38560 t cik_wait_for_rlc_serdes +ffffffff81c38720 t cik_mec_init +ffffffff81c38900 t cik_uvd_start +ffffffff81c389e0 t cik_vce_start +ffffffff81c38af0 t cik_irq_init +ffffffff81c39670 t cik_cp_resume +ffffffff81c3ae10 t cik_uvd_resume +ffffffff81c3aee0 t cik_vce_resume +ffffffff81c3afd0 t pcie_capability_set_word +ffffffff81c3b0e0 t pcie_capability_read_word +ffffffff81c3b180 t pcie_capability_clear_and_set_word +ffffffff81c3b2a0 t pcie_capability_write_word +ffffffff81c3b360 t cik_get_cu_active_bitmap +ffffffff81c3b4e0 t radeon_bo_reserve +ffffffff81c3b650 t radeon_bo_unreserve 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+ffffffff81c3f000 T cypress_enable_spread_spectrum +ffffffff81c3f140 T cypress_start_dpm +ffffffff81c3f190 T cypress_enable_sclk_control +ffffffff81c3f1f0 T cypress_enable_mclk_control +ffffffff81c3f250 T cypress_notify_smc_display_change +ffffffff81c3f2a0 T cypress_program_response_times +ffffffff81c3f360 T cypress_advertise_gen2_capability +ffffffff81c3f430 T cypress_notify_link_speed_change_after_state_change +ffffffff81c3f4f0 T cypress_notify_link_speed_change_before_state_change +ffffffff81c3f5b0 T cypress_get_strobe_mode_settings +ffffffff81c3f6b0 T cypress_get_mclk_frequency_ratio +ffffffff81c3f760 T cypress_map_clkf_to_ibias +ffffffff81c3f820 T cypress_convert_power_level_to_smc +ffffffff81c3fbf0 t cypress_populate_mclk_value +ffffffff81c40000 T cypress_upload_sw_state +ffffffff81c40180 T cypress_upload_mc_reg_table +ffffffff81c40240 t cypress_convert_mc_reg_table_to_smc +ffffffff81c404d0 T cypress_calculate_burst_time +ffffffff81c40560 T cypress_program_memory_timing_parameters +ffffffff81c40700 T cypress_populate_smc_initial_state +ffffffff81c40ab0 T cypress_populate_smc_acpi_state +ffffffff81c40e30 T cypress_construct_voltage_tables +ffffffff81c40fc0 T cypress_populate_smc_voltage_tables +ffffffff81c410f0 T cypress_get_mvdd_configuration +ffffffff81c411c0 T cypress_populate_mc_reg_table +ffffffff81c41410 T cypress_get_table_locations +ffffffff81c414f0 T cypress_enable_display_gap +ffffffff81c41550 T cypress_dpm_setup_asic +ffffffff81c41640 T cypress_dpm_enable +ffffffff81c42110 t cypress_force_mc_use_s1 +ffffffff81c42390 t cypress_gfx_clock_gating_enable +ffffffff81c426a0 t cypress_mg_clock_gating_enable +ffffffff81c42920 T cypress_dpm_disable +ffffffff81c42b50 T cypress_dpm_set_power_state +ffffffff81c42d90 T cypress_dpm_display_configuration_changed +ffffffff81c42e70 T cypress_dpm_init +ffffffff81c430e0 T cypress_dpm_fini +ffffffff81c43170 T cypress_dpm_vblank_too_short +ffffffff81c431e0 t cypress_wait_for_mc_sequencer +ffffffff81c44000 T dce3_2_afmt_hdmi_write_speaker_allocation +ffffffff81c44070 T dce3_2_afmt_dp_write_speaker_allocation +ffffffff81c440e0 T dce3_2_afmt_write_sad_regs +ffffffff81c441e0 T dce3_2_audio_set_dto +ffffffff81c44320 T dce3_2_hdmi_update_acr +ffffffff81c44680 T dce3_2_set_audio_packet +ffffffff81c44810 T dce3_2_set_mute +ffffffff81c45000 T dce6_endpoint_rreg +ffffffff81c450e0 T dce6_endpoint_wreg +ffffffff81c451d0 T dce6_audio_get_pin +ffffffff81c45360 T dce6_afmt_select_pin +ffffffff81c453f0 T dce6_afmt_write_latency_fields +ffffffff81c454b0 T dce6_afmt_hdmi_write_speaker_allocation +ffffffff81c45580 T dce6_afmt_dp_write_speaker_allocation +ffffffff81c45650 T dce6_afmt_write_sad_regs +ffffffff81c45790 T dce6_audio_enable +ffffffff81c457e0 T dce6_hdmi_audio_set_dto +ffffffff81c45850 T dce6_dp_audio_set_dto +ffffffff81c46000 T eg_cg_rreg +ffffffff81c46080 T eg_cg_wreg +ffffffff81c460f0 T eg_pif_phy0_rreg +ffffffff81c46170 T eg_pif_phy0_wreg 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evergreen_get_number_of_dram_channels +ffffffff81c47e10 T evergreen_bandwidth_update +ffffffff81c47fd0 t evergreen_line_buffer_adjust +ffffffff81c481c0 t evergreen_program_watermarks +ffffffff81c48c20 T evergreen_mc_wait_for_idle +ffffffff81c48cc0 T evergreen_pcie_gart_tlb_flush +ffffffff81c48d90 T evergreen_mc_stop +ffffffff81c49890 T evergreen_mc_resume +ffffffff81c49fa0 T evergreen_mc_program +ffffffff81c4a3a0 T evergreen_ring_ib_execute +ffffffff81c4a830 T evergreen_mc_init +ffffffff81c4a970 T evergreen_print_gpu_status_regs +ffffffff81c4a9a0 T evergreen_is_display_hung +ffffffff81c4aba0 T evergreen_gpu_check_soft_reset +ffffffff81c4ad00 T evergreen_gpu_pci_config_reset +ffffffff81c4ae80 T evergreen_asic_reset +ffffffff81c4b1a0 T evergreen_gfx_is_lockup +ffffffff81c4b210 T sumo_rlc_fini +ffffffff81c4b3c0 t radeon_bo_reserve +ffffffff81c4b530 t radeon_bo_unreserve +ffffffff81c4b610 T sumo_rlc_init +ffffffff81c4bde0 T evergreen_rlc_resume +ffffffff81c4c150 T evergreen_get_vblank_counter +ffffffff81c4c1c0 T evergreen_disable_interrupt_state +ffffffff81c4c490 T evergreen_irq_set +ffffffff81c4ca50 T evergreen_irq_suspend +ffffffff81c4caa0 T evergreen_irq_process +ffffffff81c4d5f0 t evergreen_irq_ack +ffffffff81c4dcb0 T evergreen_resume +ffffffff81c4dd90 t evergreen_init_golden_registers +ffffffff81c4dfa0 t evergreen_startup +ffffffff81c4f830 T evergreen_suspend +ffffffff81c4f9d0 T evergreen_init +ffffffff81c4fdd0 t evergreen_pcie_gart_fini +ffffffff81c4fef0 T evergreen_fini +ffffffff81c500e0 T evergreen_pcie_gen2_enable +ffffffff81c50310 T evergreen_program_aspm +ffffffff81c509a0 t evergreen_latency_watermark +ffffffff81c50ba0 t evergreen_uvd_start +ffffffff81c50c50 t evergreen_cp_load_microcode +ffffffff81c50db0 t evergreen_cp_resume +ffffffff81c51a20 t evergreen_uvd_resume +ffffffff81c52000 T evergreen_cs_parse +ffffffff81c54760 T evergreen_dma_cs_parse +ffffffff81c558d0 T evergreen_ib_parse +ffffffff81c55d30 T evergreen_dma_ib_parse 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+ffffffff81c5ba20 T dce4_set_audio_packet +ffffffff81c5bc30 T dce4_set_mute +ffffffff81c5bd40 T evergreen_hdmi_enable +ffffffff81c5c070 T evergreen_dp_enable +ffffffff81c5d000 T kv_dpm_enable_bapm +ffffffff81c5d070 T kv_dpm_enable +ffffffff81c5df70 t kv_populate_vce_table +ffffffff81c5e1f0 t kv_populate_samu_table +ffffffff81c5e450 t kv_populate_acp_table +ffffffff81c5e5e0 t kv_start_am +ffffffff81c5e620 t kv_enable_auto_thermal_throttling +ffffffff81c5e660 t kv_enable_dpm_voltage_scaling +ffffffff81c5e6a0 t kv_set_dpm_interval +ffffffff81c5e6e0 t kv_start_dpm +ffffffff81c5e720 t kv_enable_didt +ffffffff81c5e9d0 T kv_dpm_late_enable +ffffffff81c5ebd0 T kv_dpm_powergate_uvd +ffffffff81c5ed50 T kv_dpm_disable +ffffffff81c5f0c0 T kv_dpm_force_performance_level +ffffffff81c5f240 t kv_force_dpm_lowest +ffffffff81c5f310 T kv_dpm_pre_set_power_state +ffffffff81c5f890 T kv_dpm_set_power_state +ffffffff81c60060 t kv_set_valid_clock_range +ffffffff81c60200 t kv_calculate_ds_divider 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ni_init_microcode +ffffffff81c637b0 t request_firmware +ffffffff81c63840 t release_firmware +ffffffff81c63880 T cayman_get_allowed_info_register +ffffffff81c63910 T tn_get_temp +ffffffff81c639a0 T cayman_pcie_gart_tlb_flush +ffffffff81c639f0 T cayman_cp_int_cntl_setup +ffffffff81c63a40 T cayman_fence_ring_emit +ffffffff81c63dd0 T cayman_ring_ib_execute +ffffffff81c64230 T cayman_gfx_get_rptr +ffffffff81c642c0 T cayman_gfx_get_wptr +ffffffff81c64330 T cayman_gfx_set_wptr +ffffffff81c643b0 T cayman_gpu_check_soft_reset +ffffffff81c64540 T cayman_asic_reset +ffffffff81c64840 T cayman_gfx_is_lockup +ffffffff81c648b0 T cayman_resume +ffffffff81c64940 t ni_init_golden_registers +ffffffff81c64a20 t cayman_startup +ffffffff81c65e60 T cayman_suspend +ffffffff81c66050 T cayman_init +ffffffff81c663c0 t cayman_uvd_init +ffffffff81c66470 t cayman_vce_init +ffffffff81c66540 t cayman_cp_fini +ffffffff81c665c0 t cayman_pcie_gart_fini +ffffffff81c66700 T cayman_fini +ffffffff81c66980 T cayman_vm_init +ffffffff81c669e0 T cayman_vm_fini +ffffffff81c66a10 T cayman_vm_decode_fault +ffffffff81c66aa0 T cayman_vm_flush +ffffffff81c66f00 T tn_set_vce_clocks +ffffffff81c67160 t cayman_uvd_start +ffffffff81c67210 t cayman_vce_start +ffffffff81c67320 t cayman_cp_load_microcode +ffffffff81c674b0 t cayman_cp_resume +ffffffff81c68370 t cayman_uvd_resume +ffffffff81c68440 t cayman_vce_resume +ffffffff81c69000 T cayman_dma_get_rptr +ffffffff81c69070 T cayman_dma_get_wptr +ffffffff81c690c0 T cayman_dma_set_wptr +ffffffff81c69110 T cayman_dma_ring_ib_execute +ffffffff81c694a0 T cayman_dma_stop +ffffffff81c69550 T cayman_dma_resume +ffffffff81c697b0 T cayman_dma_fini +ffffffff81c69870 T cayman_dma_is_lockup +ffffffff81c698f0 T cayman_dma_vm_copy_pages +ffffffff81c699f0 T cayman_dma_vm_write_pages +ffffffff81c69b50 T cayman_dma_vm_set_pages +ffffffff81c69cc0 T cayman_dma_vm_pad_ib +ffffffff81c69d10 T cayman_dma_vm_flush +ffffffff81c6b000 T ni_get_pi +ffffffff81c6b030 T ni_get_ps +ffffffff81c6b060 T ni_dpm_vblank_too_short +ffffffff81c6b0d0 T ni_dpm_force_performance_level +ffffffff81c6b220 T ni_copy_and_switch_arb_sets +ffffffff81c6b4f0 T ni_set_uvd_clock_before_set_eng_clock +ffffffff81c6b570 T ni_set_uvd_clock_after_set_eng_clock +ffffffff81c6b5f0 T ni_dpm_setup_asic +ffffffff81c6b800 T ni_update_current_ps +ffffffff81c6b8c0 T ni_update_requested_ps +ffffffff81c6b980 T ni_dpm_enable +ffffffff81c6c7e0 t ni_init_smc_table +ffffffff81c6d190 t ni_init_smc_spll_table +ffffffff81c6d300 t ni_init_arb_table_index +ffffffff81c6d3a0 t ni_populate_mc_reg_table +ffffffff81c6d6e0 t ni_initialize_smc_cac_tables +ffffffff81c6e960 t ni_initialize_hardware_cac_manager +ffffffff81c6ee90 t ni_populate_smc_tdp_limits +ffffffff81c6f040 t ni_program_response_times +ffffffff81c6f150 T ni_dpm_disable +ffffffff81c6f510 t ni_enable_power_containment +ffffffff81c6f5d0 t ni_enable_smc_cac +ffffffff81c6f6f0 T ni_dpm_pre_set_power_state +ffffffff81c6fcd0 T ni_dpm_set_power_state +ffffffff81c6ffc0 t ni_upload_sw_state +ffffffff81c70bb0 t ni_upload_mc_reg_table +ffffffff81c70d60 t ni_power_control_set_level +ffffffff81c70e30 T ni_dpm_post_set_power_state +ffffffff81c70f00 T ni_dpm_init +ffffffff81c718a0 T ni_dpm_fini +ffffffff81c71950 T ni_dpm_print_power_state +ffffffff81c71a20 T ni_dpm_debugfs_print_current_performance_level +ffffffff81c71a60 T ni_dpm_get_current_sclk +ffffffff81c71ad0 T ni_dpm_get_current_mclk +ffffffff81c71b40 T ni_dpm_get_sclk +ffffffff81c71ba0 T ni_dpm_get_mclk +ffffffff81c71c00 t ni_do_program_memory_timing_parameters +ffffffff81c71d40 t ni_calculate_sclk_params +ffffffff81c71f70 t ni_calculate_power_boost_limit +ffffffff81c72130 t ni_populate_mclk_value +ffffffff81c73000 T r100_wait_for_vblank +ffffffff81c73190 T r100_page_flip +ffffffff81c73450 T r100_page_flip_pending +ffffffff81c73500 T r100_pm_get_dynpm_state +ffffffff81c73720 T r100_pm_init_profile +ffffffff81c73800 T r100_pm_misc +ffffffff81c73c40 T r100_pm_prepare +ffffffff81c73cf0 T r100_pm_finish +ffffffff81c73da0 T r100_gui_idle +ffffffff81c73de0 T r100_hpd_sense +ffffffff81c73e40 T r100_hpd_set_polarity +ffffffff81c73f00 T r100_hpd_init +ffffffff81c73fa0 T r100_hpd_fini +ffffffff81c74010 T r100_pci_gart_tlb_flush +ffffffff81c74040 T r100_pci_gart_init +ffffffff81c74110 T r100_pci_gart_get_page_entry +ffffffff81c74140 T r100_pci_gart_set_page +ffffffff81c74180 T r100_pci_gart_enable +ffffffff81c74270 T r100_pci_gart_disable +ffffffff81c742f0 T r100_pci_gart_fini +ffffffff81c74370 T r100_irq_set +ffffffff81c74450 T r100_irq_disable +ffffffff81c744c0 T r100_irq_process +ffffffff81c747c0 T r100_get_vblank_counter +ffffffff81c74810 T r100_fence_ring_emit +ffffffff81c74c70 T r100_semaphore_ring_emit +ffffffff81c74ca0 T r100_copy_blit +ffffffff81c75330 T r100_ring_start +ffffffff81c75420 T r100_gfx_get_rptr +ffffffff81c75480 T r100_gfx_get_wptr +ffffffff81c754c0 T r100_gfx_set_wptr +ffffffff81c75500 T r100_cp_init +ffffffff81c75a30 T r100_debugfs_cp_init +ffffffff81c75a60 T r100_cp_fini +ffffffff81c75b00 T r100_cp_disable +ffffffff81c75c40 T r100_gui_wait_for_idle +ffffffff81c75d30 T r100_reloc_pitch_offset +ffffffff81c75e70 T r100_packet3_load_vbpntr +ffffffff81c76110 T r100_cs_parse_packet0 +ffffffff81c76220 T r100_cs_packet_parse_vline +ffffffff81c76430 T r100_cs_track_check_pkt3_indx_buffer +ffffffff81c764b0 T r100_cs_parse +ffffffff81c776a0 T r100_cs_track_clear +ffffffff81c77a30 T r100_cs_track_check +ffffffff81c78240 T r100_mc_wait_for_idle +ffffffff81c782e0 T r100_gpu_is_lockup +ffffffff81c78340 T r100_enable_bm +ffffffff81c78390 T r100_bm_disable +ffffffff81c78440 T r100_asic_reset +ffffffff81c78770 T r100_mc_stop +ffffffff81c78930 T r100_mc_resume +ffffffff81c789f0 T r100_set_common_regs +ffffffff81c78b90 T r100_vram_init_sizes +ffffffff81c78d80 T r100_vga_set_state +ffffffff81c78de0 T r100_pll_errata_after_index +ffffffff81c78e20 T r100_pll_rreg +ffffffff81c78f50 T r100_pll_wreg +ffffffff81c79060 T r100_debugfs_rbbm_init +ffffffff81c79090 T r100_debugfs_mc_info_init +ffffffff81c790c0 T r100_set_surface_reg +ffffffff81c792d0 T r100_clear_surface_reg +ffffffff81c79380 T r100_bandwidth_update +ffffffff81c79dd0 T r100_ring_test +ffffffff81c7a080 T r100_ring_ib_execute +ffffffff81c7a2e0 T r100_ib_test +ffffffff81c7a620 T r100_vga_render_disable +ffffffff81c7a680 T r100_resume +ffffffff81c7a870 t r100_startup +ffffffff81c7adb0 T r100_suspend +ffffffff81c7ae90 T r100_fini +ffffffff81c7afa0 T r100_restore_sanity +ffffffff81c7b040 T r100_init +ffffffff81c7b490 t r100_set_safe_registers +ffffffff81c7b510 T r100_mm_rreg_slow +ffffffff81c7b590 T r100_mm_wreg_slow +ffffffff81c7b5f0 T r100_io_rreg +ffffffff81c7b690 T r100_io_wreg +ffffffff81c7b700 t r100_get_vtx_size +ffffffff81c7b7f0 t r100_cs_track_texture_print +ffffffff81c7c000 T r200_copy_dma +ffffffff81c7c470 T r200_packet0_check +ffffffff81c7d240 t r200_get_vtx_size_0 +ffffffff81c7d400 t r200_get_vtx_size_1 +ffffffff81c7d490 T r200_set_safe_registers +ffffffff81c7e000 T rv370_pcie_rreg +ffffffff81c7e080 T rv370_pcie_wreg +ffffffff81c7e0f0 T rv370_pcie_gart_tlb_flush +ffffffff81c7e2f0 T rv370_pcie_gart_get_page_entry +ffffffff81c7e350 T rv370_pcie_gart_set_page +ffffffff81c7e390 T rv370_pcie_gart_init +ffffffff81c7e460 T rv370_pcie_gart_enable +ffffffff81c7e7c0 T rv370_pcie_gart_disable +ffffffff81c7e940 T rv370_pcie_gart_fini +ffffffff81c7e970 T r300_fence_ring_emit +ffffffff81c7eee0 T r300_ring_start +ffffffff81c7f850 T r300_mc_wait_for_idle +ffffffff81c7f8f0 T r300_asic_reset +ffffffff81c7fb10 T r300_mc_init +ffffffff81c7fbc0 T rv370_set_pcie_lanes +ffffffff81c7fd80 T rv370_get_pcie_lanes +ffffffff81c7fe30 T r300_cs_parse +ffffffff81c801a0 t r300_packet0_check +ffffffff81c81060 T r300_set_reg_safe +ffffffff81c810a0 T r300_mc_program +ffffffff81c81230 T r300_clock_startup +ffffffff81c812c0 T r300_resume +ffffffff81c81490 t r300_startup +ffffffff81c817f0 T r300_suspend +ffffffff81c81870 T r300_fini +ffffffff81c81950 T r300_init +ffffffff81c82000 T r420_pm_init_profile +ffffffff81c820f0 T r420_pipes_init +ffffffff81c822d0 T r420_mc_rreg +ffffffff81c82350 T r420_mc_wreg +ffffffff81c823c0 T r420_resume +ffffffff81c82590 t r420_startup +ffffffff81c82790 T r420_suspend +ffffffff81c82930 T r420_fini +ffffffff81c82a10 T r420_init +ffffffff81c82c90 T r420_debugfs_pipes_info_init +ffffffff81c82cc0 t r420_cp_errata_init +ffffffff81c83000 T r520_mc_wait_for_idle +ffffffff81c830a0 T r520_resume +ffffffff81c83190 t r520_startup +ffffffff81c83580 T r520_init +ffffffff81c84000 T r600_rcu_rreg +ffffffff81c84080 T r600_rcu_wreg +ffffffff81c840f0 T r600_uvd_ctx_rreg +ffffffff81c84170 T r600_uvd_ctx_wreg +ffffffff81c841e0 T r600_get_allowed_info_register +ffffffff81c84260 T r600_get_xclk +ffffffff81c84290 T r600_set_uvd_clocks +ffffffff81c847f0 T dce3_program_fmt +ffffffff81c84910 T rv6xx_get_temp +ffffffff81c84960 T r600_pm_get_dynpm_state +ffffffff81c84d70 T rs780_pm_init_profile +ffffffff81c84e80 T r600_pm_init_profile +ffffffff81c85120 T r600_pm_misc +ffffffff81c85200 T r600_gui_idle +ffffffff81c85240 T r600_hpd_sense +ffffffff81c85360 T r600_hpd_set_polarity +ffffffff81c855e0 T r600_hpd_init +ffffffff81c857c0 T r600_hpd_fini +ffffffff81c85970 T r600_pcie_gart_tlb_flush +ffffffff81c85aa0 T r600_pcie_gart_init +ffffffff81c85b40 T r600_mc_wait_for_idle +ffffffff81c85be0 T rs780_mc_rreg +ffffffff81c85c80 T rs780_mc_wreg +ffffffff81c85d10 T r600_vram_scratch_init +ffffffff81c85e10 t radeon_bo_reserve +ffffffff81c85f80 t radeon_bo_unreserve +ffffffff81c86060 T r600_vram_scratch_fini +ffffffff81c860e0 T r600_set_bios_scratch_engine_hung +ffffffff81c86130 T r600_gpu_check_soft_reset +ffffffff81c864d0 T r600_asic_reset +ffffffff81c86860 t r600_gpu_pci_config_reset +ffffffff81c86a70 T r600_gfx_is_lockup +ffffffff81c86ae0 T r6xx_remap_render_backend +ffffffff81c86ca0 T r600_count_pipe_bits +ffffffff81c86d10 T r600_pciep_rreg +ffffffff81c86d90 T r600_pciep_wreg +ffffffff81c86e00 T r600_cp_stop +ffffffff81c86e80 T r600_init_microcode +ffffffff81c87340 t request_firmware +ffffffff81c873d0 t release_firmware +ffffffff81c87410 T r600_gfx_get_rptr +ffffffff81c87470 T r600_gfx_get_wptr +ffffffff81c874b0 T r600_gfx_set_wptr +ffffffff81c874f0 T r600_cp_start +ffffffff81c87860 T r600_cp_resume +ffffffff81c87bc0 T r600_ring_init +ffffffff81c87c60 T r600_cp_fini +ffffffff81c87cf0 T r600_scratch_init +ffffffff81c87d60 T r600_ring_test +ffffffff81c88000 T r600_fence_ring_emit +ffffffff81c888a0 T r600_semaphore_ring_emit +ffffffff81c88a80 T r600_copy_cpdma +ffffffff81c89030 T r600_set_surface_reg +ffffffff81c89060 T r600_clear_surface_reg +ffffffff81c89090 T r600_vga_set_state +ffffffff81c890f0 T r600_resume +ffffffff81c89180 t r600_startup +ffffffff81c8ae60 T r600_suspend +ffffffff81c8afd0 T r600_irq_suspend +ffffffff81c8b090 t r600_pcie_gart_disable +ffffffff81c8b290 T r600_init +ffffffff81c8b9f0 T r600_ih_ring_init +ffffffff81c8ba60 T r600_irq_fini +ffffffff81c8bba0 t r600_pcie_gart_fini +ffffffff81c8bbd0 T r600_fini +ffffffff81c8bd60 T r600_ring_ib_execute +ffffffff81c8c1f0 T r600_ib_test +ffffffff81c8c4a0 T r600_ih_ring_alloc +ffffffff81c8c5c0 T r600_ih_ring_fini +ffffffff81c8c650 T r600_rlc_stop +ffffffff81c8c7e0 T r600_disable_interrupts +ffffffff81c8c890 T r600_irq_init +ffffffff81c8ccf0 t r600_disable_interrupt_state +ffffffff81c8cff0 T r600_irq_disable +ffffffff81c8d0b0 T r600_irq_set +ffffffff81c8d830 t r600_irq_ack +ffffffff81c8dd60 T r600_irq_process +ffffffff81c8e960 T r600_mmio_hdp_flush +ffffffff81c8e9e0 T r600_set_pcie_lanes +ffffffff81c8eb10 T r600_get_pcie_lanes +ffffffff81c8ebe0 T r600_get_gpu_clock_counter +ffffffff81c8ec70 t r600_cp_load_microcode +ffffffff81c8ef40 t r600_uvd_resume +ffffffff81c90000 T r600_fmt_is_valid_color +ffffffff81c90040 T r600_fmt_is_valid_texture +ffffffff81c90090 T r600_fmt_get_blocksize +ffffffff81c900d0 T r600_fmt_get_nblocksx +ffffffff81c90120 T r600_fmt_get_nblocksy +ffffffff81c90180 T r600_cs_common_vline_parse +ffffffff81c90440 T r600_mip_minify +ffffffff81c904a0 T r600_cs_parse +ffffffff81c92360 T r600_dma_cs_next_reloc +ffffffff81c923e0 T r600_dma_cs_parse +ffffffff81c92a80 t r600_cs_track_check +ffffffff81c93bc0 t r600_cs_check_reg +ffffffff81c94ae0 t r600_is_safe_reg +ffffffff81c94b80 t r600_texture_size +ffffffff81c95000 T r600_dma_get_rptr +ffffffff81c95060 T r600_dma_get_wptr +ffffffff81c950a0 T r600_dma_set_wptr +ffffffff81c950e0 T r600_dma_stop +ffffffff81c95170 T r600_dma_resume +ffffffff81c95370 T r600_dma_fini +ffffffff81c953f0 T r600_dma_is_lockup +ffffffff81c95460 T r600_dma_ring_test +ffffffff81c956d0 T r600_dma_fence_ring_emit +ffffffff81c958b0 T r600_dma_semaphore_ring_emit +ffffffff81c959d0 T r600_dma_ib_test +ffffffff81c95bf0 T r600_dma_ring_ib_execute +ffffffff81c95f40 T r600_copy_dma +ffffffff81c97000 T r600_dpm_print_class_info +ffffffff81c972b0 T r600_dpm_print_cap_info +ffffffff81c97340 T r600_dpm_print_ps_status +ffffffff81c973d0 T r600_dpm_get_vblank_time +ffffffff81c97490 T r600_dpm_get_vrefresh +ffffffff81c97520 T r600_calculate_u_and_p +ffffffff81c975a0 T r600_calculate_at +ffffffff81c97650 T r600_gfx_clockgating_enable +ffffffff81c97750 T r600_dynamicpm_enable +ffffffff81c977a0 T r600_enable_thermal_protection +ffffffff81c97800 T r600_enable_acpi_pm +ffffffff81c97850 T r600_enable_dynamic_pcie_gen2 +ffffffff81c978a0 T r600_dynamicpm_enabled +ffffffff81c978e0 T r600_enable_sclk_control +ffffffff81c97940 T r600_enable_mclk_control +ffffffff81c979a0 T r600_enable_spll_bypass +ffffffff81c979f0 T r600_wait_for_spll_change +ffffffff81c97a70 T r600_set_bsp +ffffffff81c97ab0 T r600_set_at +ffffffff81c97b10 T r600_set_tc +ffffffff81c97b70 T r600_select_td +ffffffff81c97c20 T r600_set_vrc +ffffffff81c97c60 T r600_set_tpu +ffffffff81c97cc0 T r600_set_tpc +ffffffff81c97d20 T r600_set_sstu +ffffffff81c97d80 T r600_set_sst +ffffffff81c97dd0 T r600_set_git +ffffffff81c97e20 T r600_set_fctu +ffffffff81c97e80 T r600_set_fct +ffffffff81c97ed0 T r600_set_ctxcgtt3d_rphc +ffffffff81c97f30 T r600_set_ctxcgtt3d_rsdc +ffffffff81c97f90 T r600_set_vddc3d_oorsu +ffffffff81c97ff0 T r600_set_vddc3d_oorphc +ffffffff81c98050 T r600_set_vddc3d_oorsdc +ffffffff81c980b0 T r600_set_mpll_lock_time +ffffffff81c98100 T r600_set_mpll_reset_time +ffffffff81c98150 T r600_engine_clock_entry_enable +ffffffff81c98250 T r600_engine_clock_entry_enable_pulse_skipping +ffffffff81c98350 T r600_engine_clock_entry_enable_post_divider +ffffffff81c98450 T r600_engine_clock_entry_set_post_divider +ffffffff81c98510 T r600_engine_clock_entry_set_reference_divider +ffffffff81c985d0 T r600_engine_clock_entry_set_feedback_divider +ffffffff81c98690 T r600_engine_clock_entry_set_step_time +ffffffff81c98750 T r600_vid_rt_set_ssu +ffffffff81c987b0 T r600_vid_rt_set_vru +ffffffff81c98810 T r600_vid_rt_set_vrt +ffffffff81c98870 T r600_voltage_control_enable_pins +ffffffff81c988c0 T r600_voltage_control_program_voltages +ffffffff81c98950 T r600_voltage_control_deactivate_static_control +ffffffff81c989e0 T r600_power_level_enable +ffffffff81c98a50 T r600_power_level_set_voltage_index +ffffffff81c98ac0 T r600_power_level_set_mem_clock_index +ffffffff81c98b20 T r600_power_level_set_eng_clock_index +ffffffff81c98b90 T r600_power_level_set_watermark_id +ffffffff81c98c00 T r600_power_level_set_pcie_gen2 +ffffffff81c98c60 T r600_power_level_get_current_index +ffffffff81c98ca0 T r600_power_level_get_target_index +ffffffff81c98ce0 T r600_power_level_set_enter_index +ffffffff81c98d40 T r600_wait_for_power_level_unequal +ffffffff81c98e30 T r600_wait_for_power_level +ffffffff81c98f20 T r600_start_dpm +ffffffff81c99200 T r600_stop_dpm +ffffffff81c99250 T r600_dpm_pre_set_power_state +ffffffff81c99280 T r600_dpm_post_set_power_state +ffffffff81c992b0 T r600_is_uvd_state +ffffffff81c992f0 T r600_is_internal_thermal_sensor +ffffffff81c99330 T r600_dpm_late_enable +ffffffff81c99440 T r600_get_platform_caps +ffffffff81c994e0 T r600_parse_extended_power_table +ffffffff81c9a2a0 T r600_free_extended_power_table +ffffffff81c9a3a0 T r600_get_pcie_gen_support +ffffffff81c9a3f0 T r600_get_pcie_lane_support +ffffffff81c9a450 T r600_encode_pci_lane_width +ffffffff81c9b000 T r600_audio_update_hdmi +ffffffff81c9b170 t r600_audio_status +ffffffff81c9b290 T r600_hdmi_buffer_status_changed +ffffffff81c9b330 T r600_hdmi_update_audio_settings +ffffffff81c9b700 T r600_audio_enable +ffffffff81c9b780 T r600_audio_get_pin +ffffffff81c9b7b0 T r600_hdmi_update_acr +ffffffff81c9bb50 T r600_set_avi_packet +ffffffff81c9bd50 T r600_hdmi_audio_workaround +ffffffff81c9be20 T r600_hdmi_audio_set_dto +ffffffff81c9bee0 T r600_set_vbi_packet +ffffffff81c9bfa0 T r600_set_audio_packet +ffffffff81c9c270 T r600_set_mute +ffffffff81c9c380 T r600_hdmi_enable +ffffffff81c9d000 T radeon_acpi_is_pcie_performance_request_supported +ffffffff81c9d040 T radeon_acpi_pcie_notify_device_ready +ffffffff81c9d160 T radeon_acpi_pcie_performance_request +ffffffff81c9d4f0 T radeon_acpi_init +ffffffff81c9dc60 t radeon_acpi_event +ffffffff81c9df60 T radeon_acpi_fini +ffffffff81c9e000 T radeon_agp_head_init +ffffffff81c9e050 T radeon_agp_init +ffffffff81c9e0a0 T radeon_agp_resume +ffffffff81c9e130 T radeon_agp_fini +ffffffff81c9e180 T radeon_agp_suspend +ffffffff81c9f000 T radeon_agp_disable +ffffffff81c9f120 T radeon_asic_init +ffffffff81c9f8f0 t radeon_invalid_rreg +ffffffff81c9f930 t radeon_invalid_wreg +ffffffff81c9f970 t radeon_invalid_get_allowed_info_register +ffffffff81ca0000 T radeon_atombios_i2c_init +ffffffff81ca03a0 T radeon_atombios_lookup_gpio +ffffffff81ca04a0 T radeon_get_atom_connector_info_from_object_table +ffffffff81ca0de0 t radeon_lookup_i2c_gpio +ffffffff81ca10d0 t radeon_atom_apply_quirks +ffffffff81ca14f0 T radeon_get_atom_connector_info_from_supported_devices_table +ffffffff81ca19f0 T radeon_atom_get_clock_info +ffffffff81ca1dd0 T radeon_atombios_sideport_present +ffffffff81ca1e80 T radeon_atombios_get_tmds_info +ffffffff81ca1fc0 T radeon_atombios_get_ppll_ss_info +ffffffff81ca20e0 T radeon_atombios_get_asic_ss_info +ffffffff81ca23c0 t radeon_atombios_get_igp_ss_overrides +ffffffff81ca24d0 T radeon_atombios_get_lvds_info +ffffffff81ca2830 T radeon_atombios_get_primary_dac_info +ffffffff81ca28f0 T radeon_atom_get_tv_timings +ffffffff81ca2b30 T radeon_atombios_get_tv_info +ffffffff81ca2bf0 T radeon_atombios_get_tv_dac_info +ffffffff81ca2cf0 T radeon_atombios_get_default_voltages +ffffffff81ca2db0 T radeon_atombios_get_power_modes +ffffffff81ca3e20 T radeon_atom_get_clock_dividers +ffffffff81ca4110 T radeon_atom_get_memory_pll_dividers +ffffffff81ca4250 T radeon_atom_set_clock_gating +ffffffff81ca42a0 T radeon_atom_get_engine_clock +ffffffff81ca42f0 T radeon_atom_get_memory_clock +ffffffff81ca4340 T radeon_atom_set_engine_clock +ffffffff81ca4390 T radeon_atom_set_memory_clock +ffffffff81ca43f0 T radeon_atom_set_engine_dram_timings +ffffffff81ca4460 T radeon_atom_update_memory_dll +ffffffff81ca44b0 T radeon_atom_set_ac_timing +ffffffff81ca4500 T radeon_atom_set_voltage +ffffffff81ca45d0 T radeon_atom_get_max_vddc +ffffffff81ca46b0 T radeon_atom_get_leakage_vddc_based_on_leakage_idx +ffffffff81ca4780 T radeon_atom_get_leakage_id_from_vbios +ffffffff81ca4840 T radeon_atom_get_leakage_vddc_based_on_leakage_params +ffffffff81ca4a60 T radeon_atom_get_voltage_evv +ffffffff81ca4b20 T radeon_atom_get_voltage_gpio_settings +ffffffff81ca4c20 T radeon_atom_is_voltage_gpio +ffffffff81ca4db0 T radeon_atom_get_svi2_info +ffffffff81ca4ea0 T radeon_atom_get_max_voltage +ffffffff81ca5030 T radeon_atom_get_min_voltage +ffffffff81ca5170 T radeon_atom_get_voltage_step +ffffffff81ca5270 T radeon_atom_round_to_true_voltage +ffffffff81ca53d0 T radeon_atom_get_voltage_table +ffffffff81ca5640 T radeon_atom_get_memory_info +ffffffff81ca57f0 T radeon_atom_get_mclk_range_table +ffffffff81ca5a30 T radeon_atom_init_mc_reg_table +ffffffff81ca5ca0 T radeon_atom_initialize_bios_scratch_regs +ffffffff81ca5d70 T radeon_save_bios_scratch_regs +ffffffff81ca5e50 T radeon_restore_bios_scratch_regs +ffffffff81ca5f30 T radeon_atom_output_lock +ffffffff81ca5fc0 T radeon_atombios_connected_scratch_regs +ffffffff81ca6730 T radeon_atombios_encoder_crtc_scratch_regs +ffffffff81ca6880 T radeon_atombios_encoder_dpms_scratch_regs +ffffffff81ca6ab0 t radeon_atombios_parse_misc_flags_1_3 +ffffffff81ca6c90 t radeon_atombios_add_pplib_thermal_controller +ffffffff81ca7090 t radeon_atombios_parse_pplib_clock_info +ffffffff81ca7440 t radeon_atombios_parse_pplib_non_clock_info +ffffffff81ca8000 T radeon_audio_init +ffffffff81ca81f0 t radeon_audio_enable +ffffffff81ca8350 T radeon_audio_endpoint_rreg +ffffffff81ca8390 T radeon_audio_endpoint_wreg +ffffffff81ca83d0 T radeon_audio_get_pin +ffffffff81ca8420 T radeon_audio_detect +ffffffff81ca8580 T radeon_audio_fini +ffffffff81ca8610 T radeon_audio_mode_set +ffffffff81ca8660 T radeon_audio_dpms +ffffffff81ca86b0 T radeon_audio_decode_dfs_div +ffffffff81ca8710 T radeon_audio_component_init +ffffffff81ca8780 T radeon_audio_component_fini +ffffffff81ca87d0 t radeon_audio_hdmi_mode_set +ffffffff81ca8eb0 t radeon_audio_write_speaker_allocation +ffffffff81ca8f60 t radeon_audio_write_sad_regs +ffffffff81ca9030 t radeon_audio_set_avi_packet +ffffffff81ca9170 t radeon_audio_dp_mode_set +ffffffff81ca92f0 t radeon_audio_rreg +ffffffff81ca9340 t radeon_audio_wreg +ffffffff81caa000 T radeon_benchmark +ffffffff81caa940 t radeon_benchmark_move +ffffffff81caac20 t radeon_bo_reserve +ffffffff81caad90 t radeon_bo_unreserve +ffffffff81caae70 t radeon_benchmark_do_move +ffffffff81cab000 T radeon_get_bios +ffffffff81cabfc0 t igp_read_bios_from_vram +ffffffff81cac0d0 t radeon_read_bios +ffffffff81cad000 T radeon_legacy_get_engine_clock +ffffffff81cad0d0 T radeon_legacy_get_memory_clock +ffffffff81cad1a0 T radeon_get_clock_info +ffffffff81cad730 T radeon_legacy_set_engine_clock +ffffffff81cada80 T radeon_legacy_set_clock_gating +ffffffff81caf000 T radeon_combios_check_hardcoded_edid +ffffffff81caf100 t combios_get_table_offset +ffffffff81caf690 T radeon_bios_get_hardcoded_edid +ffffffff81caf710 T radeon_combios_i2c_init +ffffffff81cafdb0 t combios_setup_i2c_bus +ffffffff81cb00a0 t radeon_combios_get_i2c_info_from_table +ffffffff81cb02f0 T radeon_combios_get_clock_info +ffffffff81cb04e0 T radeon_combios_sideport_present +ffffffff81cb0560 T radeon_combios_get_primary_dac_info +ffffffff81cb06b0 T radeon_combios_get_tv_info +ffffffff81cb07b0 T radeon_combios_get_tv_dac_info +ffffffff81cb0a40 T radeon_combios_get_lvds_info +ffffffff81cb10b0 T radeon_legacy_get_tmds_info_from_table +ffffffff81cb1180 T radeon_legacy_get_tmds_info_from_combios +ffffffff81cb1390 T radeon_legacy_get_ext_tmds_info_from_table +ffffffff81cb15c0 T radeon_legacy_get_ext_tmds_info_from_combios +ffffffff81cb1900 T radeon_get_legacy_connector_info_from_table +ffffffff81cb3a70 T radeon_get_legacy_connector_info_from_bios +ffffffff81cb4660 T radeon_combios_get_power_modes +ffffffff81cb4d30 T radeon_external_tmds_setup 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radeon_scratch_free +ffffffff81cbf4c0 T radeon_doorbell_get +ffffffff81cbf570 T radeon_doorbell_free +ffffffff81cbf5c0 T radeon_wb_disable +ffffffff81cbf5f0 T radeon_wb_fini +ffffffff81cbf690 t radeon_bo_reserve +ffffffff81cbf800 t radeon_bo_unreserve +ffffffff81cbf8e0 T radeon_wb_init +ffffffff81cbfbc0 T radeon_vram_location +ffffffff81cbfce0 T radeon_gtt_location +ffffffff81cbfe10 T radeon_device_is_virtual +ffffffff81cbfe40 T radeon_card_posted +ffffffff81cc0050 T radeon_update_bandwidth_info +ffffffff81cc00d0 T radeon_boot_test_post_card +ffffffff81cc0190 T radeon_dummy_page_init +ffffffff81cc0250 T radeon_dummy_page_fini +ffffffff81cc02b0 T radeon_atombios_init +ffffffff81cc0440 t cail_reg_read +ffffffff81cc04a0 t cail_reg_write +ffffffff81cc0500 t cail_ioreg_read +ffffffff81cc0520 t cail_ioreg_write +ffffffff81cc0540 t cail_mc_read +ffffffff81cc0570 t cail_mc_write +ffffffff81cc05a0 t cail_pll_read +ffffffff81cc05d0 t cail_pll_write +ffffffff81cc0600 T radeon_atombios_fini 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radeon_encoder_set_active_device +ffffffff81cca440 T radeon_get_connector_for_encoder +ffffffff81cca4b0 T radeon_get_connector_for_encoder_init +ffffffff81cca520 T radeon_get_external_encoder +ffffffff81cca5b0 T radeon_encoder_get_dp_bridge_encoder_id +ffffffff81cca650 T radeon_panel_mode_fixup +ffffffff81cca820 T radeon_dig_monitor_is_duallink +ffffffff81cca940 T radeon_encoder_is_digital +ffffffff81ccb000 T radeon_fbdev_setup +ffffffff81ccb150 T radeon_fbdev_set_suspend +ffffffff81ccb1a0 T radeon_fbdev_robj_is_fb +ffffffff81ccb210 T radeondrm_burner +ffffffff81ccb290 T radeondrm_burner_cb +ffffffff81ccb2c0 t radeon_fbdev_fb_helper_fb_probe +ffffffff81ccb800 t radeon_bo_reserve +ffffffff81ccb970 t radeon_bo_unreserve +ffffffff81ccba50 t radeon_fbdev_client_unregister +ffffffff81ccbab0 t radeon_fbdev_client_restore +ffffffff81ccbaf0 t radeon_fbdev_client_hotplug +ffffffff81ccc000 T radeon_fence_emit +ffffffff81ccc120 T radeon_fence_process +ffffffff81ccc1e0 t radeon_fence_activity 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T radeon_ib_get +ffffffff81cd5100 T radeon_ib_free +ffffffff81cd5140 T radeon_ib_schedule +ffffffff81cd53d0 T radeon_ib_pool_init +ffffffff81cd5470 T radeon_ib_pool_fini +ffffffff81cd54e0 T radeon_ib_ring_tests +ffffffff81cd6000 T radeon_driver_irq_handler_kms +ffffffff81cd6050 T radeon_msi_ok +ffffffff81cd6150 T radeon_irq_kms_init +ffffffff81cd63e0 t radeon_hotplug_work_func +ffffffff81cd6490 t radeon_dp_work_func +ffffffff81cd6500 T radeon_irq_kms_fini +ffffffff81cd66a0 T radeon_irq_kms_sw_irq_get +ffffffff81cd6740 T radeon_irq_kms_sw_irq_get_delayed +ffffffff81cd6780 T radeon_irq_kms_sw_irq_put +ffffffff81cd6810 T radeon_irq_kms_pflip_irq_get +ffffffff81cd68c0 T radeon_irq_kms_pflip_irq_put +ffffffff81cd6960 T radeon_irq_kms_enable_afmt +ffffffff81cd69f0 T radeon_irq_kms_disable_afmt +ffffffff81cd6a80 T radeon_irq_kms_enable_hpd +ffffffff81cd6b70 T radeon_irq_kms_disable_hpd +ffffffff81cd6c50 T radeon_irq_kms_set_irq_n_enabled +ffffffff81cd6dc0 t __delayed_work_tick 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radeon_legacy_primary_dac_detect +ffffffff81cdd900 t radeon_legacy_tv_dac_dpms +ffffffff81cddb10 t radeon_legacy_tv_dac_prepare +ffffffff81cddb70 t radeon_legacy_tv_dac_commit +ffffffff81cddbc0 t radeon_legacy_tv_dac_mode_set +ffffffff81cddf60 t radeon_legacy_tv_dac_detect +ffffffff81cdeb60 t radeon_ext_tmds_enc_destroy +ffffffff81cdebb0 t radeon_legacy_tmds_ext_dpms +ffffffff81cdec80 t radeon_legacy_tmds_ext_prepare +ffffffff81cded50 t radeon_legacy_tmds_ext_commit +ffffffff81cdee20 t radeon_legacy_tmds_ext_mode_set +ffffffff81cdf000 T radeon_legacy_tv_mode_set +ffffffff81ce00f0 T radeon_legacy_tv_adjust_crtc_reg +ffffffff81ce0200 T radeon_legacy_tv_adjust_pll1 +ffffffff81ce0300 T radeon_legacy_tv_adjust_pll2 +ffffffff81ce1000 T radeon_ttm_bo_is_radeon_bo +ffffffff81ce1040 t radeon_ttm_bo_destroy +ffffffff81ce1170 T radeon_ttm_placement_from_domain +ffffffff81ce12d0 T radeon_bo_create +ffffffff81ce14a0 T radeon_bo_kmap +ffffffff81ce1590 T radeon_bo_check_tiling +ffffffff81ce1670 T radeon_bo_kunmap +ffffffff81ce1700 T radeon_bo_ref +ffffffff81ce1740 T radeon_bo_unref +ffffffff81ce1790 T radeon_bo_pin_restricted +ffffffff81ce1ab0 T radeon_bo_pin +ffffffff81ce1ad0 T radeon_bo_unpin +ffffffff81ce1b40 T radeon_bo_evict_vram +ffffffff81ce1ba0 T radeon_bo_force_delete +ffffffff81ce1d00 T radeon_bo_init +ffffffff81ce1de0 T radeon_bo_fini +ffffffff81ce1e20 T radeon_bo_list_validate +ffffffff81ce2130 T radeon_bo_get_surface_reg +ffffffff81ce23b0 T radeon_bo_set_tiling_flags +ffffffff81ce26b0 T radeon_bo_get_tiling_flags +ffffffff81ce2700 T radeon_bo_move_notify +ffffffff81ce27d0 T radeon_bo_fault_reserve_notify +ffffffff81ce2a60 t ttm_bo_move_to_lru_tail_unlocked +ffffffff81ce2aa0 T radeon_bo_fence +ffffffff81ce3000 T radeon_pm_get_type_index +ffffffff81ce3080 T radeon_pm_acpi_event_handler +ffffffff81ce3160 t radeon_pm_update_profile +ffffffff81ce3280 t radeon_pm_set_clocks +ffffffff81ce3c40 T radeon_dpm_enable_uvd +ffffffff81ce3d00 T radeon_pm_compute_clocks +ffffffff81ce4710 T radeon_dpm_enable_vce +ffffffff81ce4780 T radeon_pm_suspend +ffffffff81ce4880 T radeon_pm_resume +ffffffff81ce4b70 T radeon_pm_init +ffffffff81ce5280 T radeon_pm_late_init +ffffffff81ce5340 T radeon_pm_fini +ffffffff81ce5460 t radeon_dpm_thermal_work_handler +ffffffff81ce5540 t radeon_dynpm_idle_work_handler +ffffffff81ce57c0 t __delayed_work_tick +ffffffff81ce6000 T radeon_gem_prime_get_sg_table +ffffffff81ce6030 T radeon_gem_prime_pin +ffffffff81ce60c0 t radeon_bo_reserve +ffffffff81ce6230 t radeon_bo_unreserve +ffffffff81ce6310 T radeon_gem_prime_unpin +ffffffff81ce6390 T radeon_gem_prime_export +ffffffff81ce7000 T radeon_ring_supports_scratch_reg +ffffffff81ce7030 T radeon_ring_free_size +ffffffff81ce70e0 T radeon_ring_lockup_update +ffffffff81ce7140 T radeon_ring_alloc +ffffffff81ce72c0 T radeon_ring_lock +ffffffff81ce7340 T radeon_ring_commit +ffffffff81ce7440 T radeon_ring_unlock_commit +ffffffff81ce7470 T radeon_ring_undo +ffffffff81ce74a0 T radeon_ring_unlock_undo +ffffffff81ce74c0 T radeon_ring_test_lockup +ffffffff81ce75e0 T radeon_ring_backup +ffffffff81ce7780 T radeon_ring_restore +ffffffff81ce7930 T radeon_ring_init +ffffffff81ce7b20 t radeon_bo_reserve +ffffffff81ce7c90 t radeon_bo_unreserve +ffffffff81ce7d70 T radeon_ring_fini +ffffffff81ce8000 T radeon_sa_bo_manager_init +ffffffff81ce80d0 T radeon_sa_bo_manager_fini +ffffffff81ce8100 T radeon_sa_bo_manager_start +ffffffff81ce8240 t radeon_bo_reserve +ffffffff81ce83b0 t radeon_bo_unreserve +ffffffff81ce8490 T radeon_sa_bo_manager_suspend +ffffffff81ce8540 T radeon_sa_bo_new +ffffffff81ce85b0 T radeon_sa_bo_free +ffffffff81ce9000 T radeon_semaphore_create +ffffffff81ce90e0 T radeon_semaphore_emit_signal +ffffffff81ce9170 T radeon_semaphore_emit_wait +ffffffff81ce9200 T radeon_semaphore_free +ffffffff81cea000 T radeon_sync_create +ffffffff81cea090 T radeon_sync_fence +ffffffff81cea140 T radeon_sync_resv +ffffffff81cea280 T radeon_sync_rings +ffffffff81cea440 T radeon_sync_free +ffffffff81ceb000 T radeon_test_moves +ffffffff81ceb070 t radeon_do_test_moves +ffffffff81ceb680 T radeon_test_ring_sync +ffffffff81ceb950 t radeon_test_create_and_emit_fence +ffffffff81cebac0 T radeon_test_syncing +ffffffff81cebd90 t radeon_test_ring_sync2 +ffffffff81cec100 t radeon_bo_reserve +ffffffff81cec270 t radeon_bo_unreserve +ffffffff81ced000 T radeon_get_rdev +ffffffff81ced030 T radeon_ttm_tt_set_userptr +ffffffff81ced080 T radeon_ttm_tt_is_bound +ffffffff81ced0d0 T radeon_ttm_tt_has_userptr +ffffffff81ced120 T radeon_ttm_tt_is_readonly +ffffffff81ced170 T radeon_ttm_init +ffffffff81ced390 T radeon_ttm_set_active_vram_size +ffffffff81ced3d0 t radeon_bo_reserve +ffffffff81ced540 t radeon_bo_unreserve +ffffffff81ced620 T radeon_ttm_fini +ffffffff81ced6f0 t radeon_ttm_tt_create +ffffffff81ced7d0 t radeon_ttm_tt_populate +ffffffff81ced880 t radeon_ttm_tt_unpopulate +ffffffff81ced970 t radeon_ttm_tt_destroy +ffffffff81ced9c0 t radeon_evict_flags +ffffffff81cedb20 t radeon_bo_move +ffffffff81cedf20 t radeon_ttm_io_mem_reserve +ffffffff81cee000 T radeon_ucode_print_mc_hdr +ffffffff81cee0b0 t radeon_ucode_print_common_hdr +ffffffff81cee1e0 T radeon_ucode_print_smc_hdr +ffffffff81cee270 T radeon_ucode_print_gfx_hdr +ffffffff81cee340 T radeon_ucode_print_rlc_hdr +ffffffff81cee440 T radeon_ucode_print_sdma_hdr +ffffffff81cee520 T radeon_ucode_validate +ffffffff81cef000 T radeon_uvd_init +ffffffff81cef4f0 t radeon_uvd_idle_work_handler +ffffffff81cef660 t radeon_bo_reserve +ffffffff81cef860 t radeon_bo_unreserve +ffffffff81cef940 T radeon_uvd_fini +ffffffff81cefa10 T radeon_uvd_suspend +ffffffff81cefbd0 T radeon_uvd_note_usage +ffffffff81cefe10 T radeon_uvd_get_destroy_msg +ffffffff81ceff20 T radeon_uvd_resume +ffffffff81ceffb0 T radeon_uvd_force_into_uvd_segment +ffffffff81cf0050 T radeon_uvd_free_handles +ffffffff81cf0210 T radeon_uvd_cs_parse +ffffffff81cf0930 T radeon_uvd_get_create_msg +ffffffff81cf0ab0 t radeon_uvd_send_msg +ffffffff81cf0c50 T radeon_uvd_calc_upll_dividers +ffffffff81cf0e20 T radeon_uvd_send_upll_ctlreq +ffffffff81cf1160 t __delayed_work_tick +ffffffff81cf2000 T radeon_vce_init +ffffffff81cf2620 t radeon_vce_idle_work_handler +ffffffff81cf26e0 t radeon_bo_reserve +ffffffff81cf2850 t radeon_bo_unreserve +ffffffff81cf2930 T radeon_vce_fini +ffffffff81cf29b0 T radeon_vce_suspend +ffffffff81cf2a90 T radeon_vce_resume +ffffffff81cf2be0 T radeon_vce_note_usage +ffffffff81cf2d00 T radeon_vce_free_handles +ffffffff81cf2dc0 T radeon_vce_get_destroy_msg +ffffffff81cf2ff0 T radeon_vce_get_create_msg +ffffffff81cf3340 T radeon_vce_cs_reloc +ffffffff81cf3440 T radeon_vce_cs_parse +ffffffff81cf3bb0 T radeon_vce_semaphore_emit +ffffffff81cf3d70 T radeon_vce_ib_execute +ffffffff81cf3f00 T radeon_vce_fence_emit +ffffffff81cf4130 T radeon_vce_ring_test +ffffffff81cf4280 T radeon_vce_ib_test +ffffffff81cf43a0 t __delayed_work_tick +ffffffff81cf5000 T radeon_vm_manager_init +ffffffff81cf5060 T radeon_vm_manager_fini +ffffffff81cf5180 T radeon_vm_get_bos +ffffffff81cf52d0 T radeon_vm_grab_id +ffffffff81cf5460 T radeon_vm_flush +ffffffff81cf55f0 T radeon_vm_fence +ffffffff81cf56a0 T radeon_vm_bo_find +ffffffff81cf56f0 T radeon_vm_bo_add +ffffffff81cf57e0 T radeon_vm_bo_set_addr +ffffffff81cf5c30 t radeon_bo_unreserve +ffffffff81cf5d10 t radeon_vm_clear_bo +ffffffff81cf5f00 T radeon_vm_map_gart +ffffffff81cf5f40 T radeon_vm_update_page_directory +ffffffff81cf62c0 T radeon_vm_bo_update +ffffffff81cf6900 t radeon_vm_fence_pts +ffffffff81cf6990 T radeon_vm_clear_freed +ffffffff81cf6a70 T radeon_vm_clear_invalids +ffffffff81cf6b10 T radeon_vm_bo_rmv +ffffffff81cf6c00 T radeon_vm_bo_invalidate +ffffffff81cf6cb0 T radeon_vm_init +ffffffff81cf6f10 T radeon_vm_fini +ffffffff81cf71f0 t radeon_bo_reserve +ffffffff81cf7360 t radeon_vm_frag_ptes +ffffffff81cf8000 T rs400_gart_adjust_size +ffffffff81cf80c0 T rs400_gart_tlb_flush +ffffffff81cf8140 T rs400_gart_init +ffffffff81cf8240 T rs400_gart_enable +ffffffff81cf85a0 T rs400_gart_disable +ffffffff81cf8600 T rs400_gart_fini +ffffffff81cf8670 T rs400_gart_get_page_entry +ffffffff81cf86d0 T rs400_gart_set_page +ffffffff81cf8710 T rs400_mc_wait_for_idle +ffffffff81cf87b0 T rs400_mc_rreg +ffffffff81cf8840 T rs400_mc_wreg +ffffffff81cf88c0 T rs400_resume +ffffffff81cf89f0 t rs400_mc_program +ffffffff81cf8ae0 t rs400_startup +ffffffff81cf8cd0 T rs400_suspend +ffffffff81cf8d70 T rs400_fini +ffffffff81cf8e60 T rs400_init +ffffffff81cfa000 T avivo_wait_for_vblank +ffffffff81cfa280 T rs600_page_flip +ffffffff81cfa550 T rs600_page_flip_pending +ffffffff81cfa5c0 T avivo_program_fmt +ffffffff81cfa6e0 T rs600_pm_misc +ffffffff81cfaa20 T rs600_pm_prepare +ffffffff81cfab20 T rs600_pm_finish +ffffffff81cfac20 T rs600_hpd_sense +ffffffff81cfac80 T rs600_hpd_set_polarity +ffffffff81cfad40 T rs600_hpd_init +ffffffff81cfae20 T rs600_hpd_fini +ffffffff81cfaed0 T rs600_asic_reset +ffffffff81cfb140 T rs600_gart_tlb_flush +ffffffff81cfb200 T rs600_gart_get_page_entry +ffffffff81cfb260 T rs600_gart_set_page +ffffffff81cfb2a0 T rs600_irq_set +ffffffff81cfb480 T rs600_irq_disable +ffffffff81cfb500 t rs600_irq_ack +ffffffff81cfb6b0 T rs600_irq_process +ffffffff81cfba10 T rs600_get_vblank_counter +ffffffff81cfba60 T rs600_mc_wait_for_idle +ffffffff81cfbb00 T rs600_bandwidth_update +ffffffff81cfbbf0 T rs600_mc_rreg +ffffffff81cfbc70 T rs600_mc_wreg +ffffffff81cfbce0 T rs600_set_safe_registers +ffffffff81cfbd20 T rs600_resume +ffffffff81cfbe50 t rs600_startup +ffffffff81cfc670 T rs600_suspend +ffffffff81cfc770 T rs600_fini +ffffffff81cfc870 t rs600_gart_fini +ffffffff81cfc8e0 T rs600_init +ffffffff81cfd000 T rs690_mc_wait_for_idle +ffffffff81cfd0a0 T rs690_pm_info +ffffffff81cfd310 T rs690_line_buffer_adjust +ffffffff81cfd430 T rs690_bandwidth_update +ffffffff81cfd780 t rs690_crtc_bandwidth_compute +ffffffff81cfdb70 t rs690_compute_mode_priority +ffffffff81cfdff0 T rs690_mc_rreg +ffffffff81cfe080 T rs690_mc_wreg +ffffffff81cfe100 T rs690_resume +ffffffff81cfe1f0 t rs690_startup +ffffffff81cfe4d0 T rs690_suspend +ffffffff81cfe530 T rs690_fini +ffffffff81cfe5e0 T rs690_init +ffffffff81cff000 T rs780_dpm_enable +ffffffff81cffbf0 T rs780_dpm_disable +ffffffff81cffcd0 T rs780_dpm_set_power_state +ffffffff81d000b0 t rs780_force_voltage +ffffffff81d001f0 t rs780_enable_voltage_scaling +ffffffff81d003b0 T rs780_dpm_setup_asic +ffffffff81d003e0 T rs780_dpm_display_configuration_changed +ffffffff81d00530 T rs780_dpm_init +ffffffff81d00aa0 T rs780_dpm_print_power_state +ffffffff81d00b30 T rs780_dpm_fini +ffffffff81d00bc0 T rs780_dpm_get_sclk +ffffffff81d00c00 T rs780_dpm_get_mclk +ffffffff81d00c30 T rs780_dpm_debugfs_print_current_performance_level +ffffffff81d00c60 T rs780_dpm_get_current_sclk +ffffffff81d00cf0 T rs780_dpm_get_current_mclk +ffffffff81d00d20 T rs780_dpm_force_performance_level +ffffffff81d00f10 t rs780_force_fbdiv +ffffffff81d02000 T rv515_ring_start +ffffffff81d02af0 T rv515_mc_wait_for_idle +ffffffff81d02b90 T rv515_vga_render_disable +ffffffff81d02be0 T rv515_mc_rreg +ffffffff81d02c70 T rv515_mc_wreg +ffffffff81d02cf0 T rv515_debugfs +ffffffff81d02d00 T rv515_mc_stop +ffffffff81d03270 T rv515_mc_resume +ffffffff81d03850 T rv515_clock_startup +ffffffff81d03910 T rv515_resume +ffffffff81d03b50 t rv515_startup +ffffffff81d04020 T rv515_suspend +ffffffff81d04090 T rv515_set_safe_registers +ffffffff81d040d0 T rv515_fini +ffffffff81d04180 T rv515_init +ffffffff81d04460 T atom_rv515_force_tv_scaler +ffffffff81d07b00 T rv515_bandwidth_avivo_update +ffffffff81d07ca0 t rv515_crtc_bandwidth_compute +ffffffff81d07fb0 t rv515_compute_mode_priority +ffffffff81d08480 T rv515_bandwidth_update +ffffffff81d09000 T rv6xx_dpm_enable +ffffffff81d09800 t rv6xx_calculate_stepping_parameters +ffffffff81d099e0 t rv6xx_program_stepping_parameters_except_lowest_entry +ffffffff81d09fb0 t rv6xx_program_stepping_parameters_lowest_entry +ffffffff81d0a080 t rv6xx_enable_dynamic_pcie_gen2 +ffffffff81d0a240 T rv6xx_dpm_disable +ffffffff81d0a4b0 T rv6xx_dpm_set_power_state +ffffffff81d0aea0 T rv6xx_setup_asic +ffffffff81d0afe0 T rv6xx_dpm_display_configuration_changed +ffffffff81d0b060 T rv6xx_dpm_init +ffffffff81d0b5a0 T rv6xx_dpm_print_power_state +ffffffff81d0b660 T rv6xx_dpm_debugfs_print_current_performance_level +ffffffff81d0b690 T rv6xx_dpm_get_current_sclk +ffffffff81d0b700 T rv6xx_dpm_get_current_mclk +ffffffff81d0b770 T rv6xx_dpm_fini +ffffffff81d0b800 T rv6xx_dpm_get_sclk +ffffffff81d0b840 T rv6xx_dpm_get_mclk +ffffffff81d0b880 T rv6xx_dpm_force_performance_level +ffffffff81d0ba10 t rv6xx_generate_steps +ffffffff81d0bd10 t rv6xx_output_stepping +ffffffff81d0be20 t rv6xx_program_mclk_stepping_entry +ffffffff81d0c090 t rv6xx_program_engine_spread_spectrum +ffffffff81d0c380 t rv6xx_step_sw_voltage +ffffffff81d0d000 T rv730_populate_sclk_value +ffffffff81d0d230 T rv730_populate_mclk_value +ffffffff81d0d470 T rv730_read_clock_registers +ffffffff81d0d590 T rv730_populate_smc_acpi_state +ffffffff81d0d740 T rv730_populate_smc_initial_state +ffffffff81d0d900 T rv730_program_memory_timing_parameters +ffffffff81d0dae0 T rv730_start_dpm +ffffffff81d0db70 T rv730_stop_dpm +ffffffff81d0dc30 T rv730_program_dcodt +ffffffff81d0dd00 T rv730_get_odt_values +ffffffff81d0e000 T rv740_get_decoded_reference_divider +ffffffff81d0e0a0 T rv740_get_dll_speed +ffffffff81d0e2b0 T rv740_populate_sclk_value +ffffffff81d0e4b0 T rv740_populate_mclk_value +ffffffff81d0e860 T rv740_read_clock_registers +ffffffff81d0e990 T rv740_populate_smc_acpi_state +ffffffff81d0ebc0 T rv740_enable_mclk_spread_spectrum +ffffffff81d0ec10 T rv740_get_mclk_frequency_ratio +ffffffff81d0f000 T rv770_set_uvd_clocks +ffffffff81d0f570 T rv770_get_xclk +ffffffff81d0f5d0 T rv770_page_flip +ffffffff81d0f8d0 T rv770_page_flip_pending +ffffffff81d0f940 T rv770_get_temp +ffffffff81d0f9a0 T rv770_pm_misc +ffffffff81d0fa80 T r700_cp_stop +ffffffff81d0fb00 T r700_cp_fini +ffffffff81d0fb90 T rv770_set_clk_bypass_mode +ffffffff81d0fcb0 T r700_vram_gtt_location +ffffffff81d0fe40 T rv770_resume +ffffffff81d0fed0 t rv770_init_golden_registers +ffffffff81d10060 t rv770_startup +ffffffff81d11c00 T rv770_suspend +ffffffff81d11e20 T rv770_init +ffffffff81d12210 t rv770_pcie_gart_fini +ffffffff81d12390 T rv770_fini +ffffffff81d12630 t rv770_uvd_start +ffffffff81d126e0 t rv770_cp_load_microcode +ffffffff81d129b0 t rv770_uvd_resume +ffffffff81d13000 T rv770_copy_dma +ffffffff81d14000 T rv770_get_ps +ffffffff81d14030 T rv770_get_pi +ffffffff81d14060 T evergreen_get_pi +ffffffff81d14090 T rv770_restore_cgcg +ffffffff81d14110 T rv770_stop_dpm +ffffffff81d141d0 T rv770_dpm_enabled +ffffffff81d14210 T rv770_enable_thermal_protection +ffffffff81d14270 T rv770_enable_acpi_pm +ffffffff81d142c0 T rv770_get_seq_value +ffffffff81d14300 T rv770_write_smc_soft_register +ffffffff81d14330 T rv770_populate_smc_t +ffffffff81d144e0 T rv770_populate_smc_sp +ffffffff81d14540 T rv770_map_clkf_to_ibias +ffffffff81d145a0 T rv770_populate_vddc_value +ffffffff81d14650 T rv770_populate_mvdd_value +ffffffff81d146a0 T rv770_calculate_memory_refresh_rate +ffffffff81d14720 T rv770_enable_backbias +ffffffff81d14780 T rv770_setup_bsp +ffffffff81d14870 T rv770_program_git +ffffffff81d148c0 T rv770_program_tp +ffffffff81d14940 T rv770_program_tpp +ffffffff81d14980 T rv770_program_sstp +ffffffff81d149c0 T rv770_program_engine_speed_parameters +ffffffff81d14a10 T rv770_program_vc +ffffffff81d14a60 T rv770_clear_vc +ffffffff81d14aa0 T rv770_upload_firmware +ffffffff81d14ae0 T rv770_populate_initial_mvdd_value +ffffffff81d14b30 T rv770_get_memory_module_index +ffffffff81d14b70 T rv770_enable_voltage_control +ffffffff81d14bc0 T rv770_halt_smc +ffffffff81d14c20 T rv770_resume_smc +ffffffff81d14c70 T rv770_set_sw_state +ffffffff81d14cd0 T rv770_set_boot_state +ffffffff81d14d20 T rv770_set_uvd_clock_before_set_eng_clock +ffffffff81d14d90 T rv770_set_uvd_clock_after_set_eng_clock +ffffffff81d14e00 T rv770_restrict_performance_levels_before_switch +ffffffff81d14e60 T rv770_dpm_force_performance_level +ffffffff81d14f20 T r7xx_start_smc +ffffffff81d14f50 T r7xx_stop_smc +ffffffff81d14f80 T rv770_read_voltage_smio_registers +ffffffff81d14fc0 T rv770_reset_smio_status +ffffffff81d15080 T rv770_get_memory_type +ffffffff81d150d0 T rv770_get_pcie_gen2_status +ffffffff81d15140 T rv770_get_max_vddc +ffffffff81d151a0 T rv770_program_response_times +ffffffff81d152f0 T rv770_enable_auto_throttle_source +ffffffff81d15470 T rv770_dpm_enable +ffffffff81d164f0 T rv770_dpm_late_enable +ffffffff81d16620 T rv770_dpm_disable +ffffffff81d16990 T rv770_dpm_set_power_state +ffffffff81d17080 t rv770_program_dcodt_after_state_switch +ffffffff81d17100 T rv770_dpm_setup_asic +ffffffff81d17470 T rv770_dpm_display_configuration_changed +ffffffff81d174f0 T rv7xx_parse_power_table +ffffffff81d17a70 T rv770_get_engine_memory_ss +ffffffff81d17b00 T rv770_dpm_init +ffffffff81d17d40 T rv770_dpm_print_power_state +ffffffff81d17e60 T rv770_dpm_debugfs_print_current_performance_level +ffffffff81d17e90 T rv770_dpm_get_current_sclk +ffffffff81d17f00 T rv770_dpm_get_current_mclk +ffffffff81d17f70 T rv770_dpm_fini +ffffffff81d18000 T rv770_dpm_get_sclk +ffffffff81d18050 T rv770_dpm_get_mclk +ffffffff81d180a0 T rv770_dpm_vblank_too_short +ffffffff81d18110 t rv770_convert_power_level_to_smc +ffffffff81d19000 T rv770_copy_bytes_to_smc +ffffffff81d19210 T rv770_start_smc +ffffffff81d19260 T rv770_reset_smc +ffffffff81d192b0 T rv770_stop_smc_clock +ffffffff81d19300 T rv770_start_smc_clock +ffffffff81d19350 T rv770_is_smc_running +ffffffff81d19390 T rv770_send_msg_to_smc +ffffffff81d19470 T rv770_wait_for_smc_inactive +ffffffff81d19510 T rv770_load_smc_ucode +ffffffff81d196a0 T rv770_read_smc_sram_dword +ffffffff81d19760 T rv770_write_smc_sram_dword +ffffffff81d1a000 T si_get_allowed_info_register +ffffffff81d1a090 T si_get_xclk +ffffffff81d1a100 T si_get_temp +ffffffff81d1a150 T si_mc_load_microcode +ffffffff81d1a410 T dce6_bandwidth_update +ffffffff81d1a5d0 t dce6_line_buffer_adjust +ffffffff81d1a780 t dce6_program_watermarks +ffffffff81d1b230 T si_fence_ring_emit +ffffffff81d1b690 T si_ring_ib_execute +ffffffff81d1be00 T si_gpu_check_soft_reset +ffffffff81d1bfa0 T si_asic_reset +ffffffff81d1c320 t si_gpu_pci_config_reset +ffffffff81d1c640 T si_gfx_is_lockup +ffffffff81d1c6b0 T si_vram_gtt_location +ffffffff81d1c750 T si_pcie_gart_tlb_flush +ffffffff81d1c7a0 T si_ib_parse +ffffffff81d1ce40 T si_vm_init +ffffffff81d1ce80 T si_vm_fini +ffffffff81d1ceb0 T si_vm_flush +ffffffff81d1d550 T si_init_uvd_internal_cg +ffffffff81d1d5a0 T si_get_csb_size +ffffffff81d1d630 T si_get_csb_buffer +ffffffff81d1d7b0 T si_rlc_reset +ffffffff81d1d830 T si_irq_set +ffffffff81d1dd20 t si_disable_interrupt_state +ffffffff81d1dfa0 T si_irq_process +ffffffff81d1f2a0 t si_irq_ack +ffffffff81d1f890 T si_resume +ffffffff81d1f920 t si_init_golden_registers +ffffffff81d1fae0 t si_startup +ffffffff81d21f00 T si_suspend +ffffffff81d221f0 t si_fini_cg +ffffffff81d22290 T si_init +ffffffff81d235f0 t si_cp_fini +ffffffff81d236e0 t si_irq_fini +ffffffff81d237b0 t si_pcie_gart_fini +ffffffff81d238b0 T si_fini +ffffffff81d23ad0 T si_get_gpu_clock_counter +ffffffff81d23b90 T si_set_uvd_clocks +ffffffff81d240f0 T si_set_vce_clocks +ffffffff81d24630 t si_vce_send_vcepll_ctlreq +ffffffff81d24870 t dce6_latency_watermark +ffffffff81d24ab0 t si_rlc_stop +ffffffff81d24c60 t si_vm_reg_valid +ffffffff81d24dc0 t si_vm_packet3_cp_dma_check +ffffffff81d24f30 t si_uvd_start +ffffffff81d24fe0 t si_vce_start +ffffffff81d250f0 t si_irq_init +ffffffff81d25bd0 t si_cp_load_microcode +ffffffff81d25fb0 t si_cp_resume +ffffffff81d26e70 t si_uvd_resume +ffffffff81d26f40 t si_vce_resume +ffffffff81d27030 t pcie_capability_set_word +ffffffff81d27140 t pcie_capability_read_word +ffffffff81d271e0 t pcie_capability_clear_and_set_word +ffffffff81d27300 t pcie_capability_write_word +ffffffff81d273c0 t si_update_cg +ffffffff81d27930 t si_enable_mgcg +ffffffff81d27d50 t si_enable_cgcg +ffffffff81d280e0 t request_firmware +ffffffff81d28170 t release_firmware +ffffffff81d29000 T si_dma_is_lockup +ffffffff81d29080 T si_dma_vm_copy_pages +ffffffff81d29170 T si_dma_vm_write_pages +ffffffff81d292d0 T si_dma_vm_set_pages +ffffffff81d29440 T si_dma_vm_flush +ffffffff81d298b0 T si_copy_dma +ffffffff81d2a000 T si_dpm_force_performance_level +ffffffff81d2a160 T si_get_ddr3_mclk_frequency_ratio +ffffffff81d2a1c0 T si_get_mclk_frequency_ratio +ffffffff81d2a240 T si_trim_voltage_table_to_fit_state_table +ffffffff81d2a350 T si_dpm_setup_asic +ffffffff81d2a520 T si_fan_ctrl_get_fan_speed_percent +ffffffff81d2a5b0 T si_fan_ctrl_set_fan_speed_percent +ffffffff81d2a670 T si_fan_ctrl_set_mode +ffffffff81d2a8c0 T si_fan_ctrl_get_mode +ffffffff81d2a910 T si_dpm_enable +ffffffff81d2bc90 t si_init_smc_table +ffffffff81d2cea0 t si_init_smc_spll_table +ffffffff81d2d020 t si_init_arb_table_index +ffffffff81d2d0b0 t si_populate_mc_reg_table +ffffffff81d2d500 t si_initialize_smc_cac_tables +ffffffff81d2f150 t si_initialize_hardware_cac_manager +ffffffff81d2f200 t si_initialize_smc_dte_tables +ffffffff81d2f400 t si_populate_smc_tdp_limits +ffffffff81d2f600 t si_populate_smc_tdp_limits_2 +ffffffff81d2f6d0 t si_program_response_times +ffffffff81d2f7f0 t si_program_ds_registers +ffffffff81d2f880 t si_dpm_start_smc +ffffffff81d2f8b0 t si_enable_auto_throttle_source +ffffffff81d2fa40 t si_thermal_start_thermal_controller +ffffffff81d2ff00 T si_dpm_late_enable +ffffffff81d30050 T si_dpm_disable +ffffffff81d303d0 t si_enable_power_containment +ffffffff81d304a0 t si_enable_smc_cac +ffffffff81d30600 T si_dpm_pre_set_power_state +ffffffff81d31170 T si_dpm_set_power_state +ffffffff81d316d0 t si_halt_smc +ffffffff81d31730 t si_upload_sw_state +ffffffff81d32130 t si_upload_smc_data +ffffffff81d32270 t si_upload_ulv_state +ffffffff81d323b0 t si_upload_mc_reg_table +ffffffff81d32550 t si_set_pcie_lane_width_in_smc +ffffffff81d325f0 t si_resume_smc +ffffffff81d32650 t si_set_vce_clock +ffffffff81d326f0 t si_notify_link_speed_change_after_state_change +ffffffff81d32820 t si_set_power_state_conditionally_enable_ulv +ffffffff81d32900 t si_power_control_set_level +ffffffff81d32a90 T si_dpm_post_set_power_state +ffffffff81d32ac0 T si_dpm_display_configuration_changed +ffffffff81d32ba0 T si_dpm_init +ffffffff81d345e0 T si_dpm_fini +ffffffff81d34690 T si_dpm_debugfs_print_current_performance_level +ffffffff81d346e0 T si_dpm_get_current_sclk +ffffffff81d34750 T si_dpm_get_current_mclk +ffffffff81d347c0 t si_do_program_memory_timing_parameters +ffffffff81d34950 t si_populate_mvdd_value +ffffffff81d349d0 t si_convert_power_level_to_smc +ffffffff81d35280 t si_calculate_sclk_params +ffffffff81d354b0 t si_program_cac_config_registers +ffffffff81d36000 T si_copy_bytes_to_smc +ffffffff81d36240 T si_start_smc +ffffffff81d36280 T si_reset_smc +ffffffff81d362c0 T si_program_jump_on_start +ffffffff81d362f0 T si_stop_smc_clock +ffffffff81d36330 T si_start_smc_clock +ffffffff81d36370 T si_is_smc_running +ffffffff81d363d0 T si_send_msg_to_smc +ffffffff81d364a0 T si_wait_for_smc_inactive +ffffffff81d36540 T si_load_smc_ucode +ffffffff81d366e0 T si_read_smc_sram_dword +ffffffff81d367b0 T si_write_smc_sram_dword +ffffffff81d37000 T sumo_get_pi +ffffffff81d37030 T sumo_gfx_clockgating_initialize +ffffffff81d37110 T sumo_program_vc +ffffffff81d37150 T sumo_clear_vc +ffffffff81d37190 T sumo_program_sstp +ffffffff81d37210 T sumo_take_smu_control +ffffffff81d37240 T sumo_get_sleep_divider_from_id +ffffffff81d37270 T sumo_get_sleep_divider_id_from_clock +ffffffff81d37320 T sumo_dpm_enable +ffffffff81d379b0 T sumo_dpm_late_enable +ffffffff81d37f70 T sumo_dpm_disable +ffffffff81d382c0 T sumo_dpm_pre_set_power_state +ffffffff81d387b0 T sumo_dpm_set_power_state +ffffffff81d39260 T sumo_dpm_post_set_power_state +ffffffff81d39300 T sumo_dpm_setup_asic +ffffffff81d39400 T sumo_dpm_display_configuration_changed +ffffffff81d39430 T sumo_convert_vid2_to_vid7 +ffffffff81d39480 T sumo_construct_sclk_voltage_mapping_table +ffffffff81d39540 T sumo_construct_vid_mapping_table +ffffffff81d396b0 T sumo_dpm_init +ffffffff81d39f60 T sumo_dpm_print_power_state +ffffffff81d3a080 T sumo_dpm_debugfs_print_current_performance_level +ffffffff81d3a0b0 T sumo_dpm_get_current_sclk +ffffffff81d3a120 T sumo_dpm_get_current_mclk +ffffffff81d3a150 T sumo_dpm_get_current_vddc +ffffffff81d3a220 T sumo_dpm_fini +ffffffff81d3a2b0 T sumo_dpm_get_sclk +ffffffff81d3a300 T sumo_dpm_get_mclk +ffffffff81d3a330 T sumo_dpm_force_performance_level +ffffffff81d3a720 t sumo_power_level_enable +ffffffff81d3a950 t sumo_program_power_level +ffffffff81d3b000 T sumo_initialize_m3_arb +ffffffff81d3b2c0 T sumo_smu_notify_alt_vddnb_change +ffffffff81d3b360 t sumo_send_msg_to_smu +ffffffff81d3b4f0 T sumo_smu_pg_init +ffffffff81d3b510 T sumo_enable_boost_timer +ffffffff81d3b640 T sumo_set_tdp_limit +ffffffff81d3b6c0 T sumo_boost_state_enable +ffffffff81d3b710 T sumo_get_running_fw_version +ffffffff81d3c000 T trinity_dpm_enable_bapm +ffffffff81d3c080 T trinity_dpm_enable +ffffffff81d3c520 T trinity_dpm_late_enable +ffffffff81d3ca60 T trinity_dpm_disable +ffffffff81d3ce50 T trinity_dpm_force_performance_level +ffffffff81d3cf00 T trinity_dpm_pre_set_power_state +ffffffff81d3d4c0 T trinity_dpm_set_power_state +ffffffff81d3da30 T trinity_dpm_post_set_power_state +ffffffff81d3dad0 T trinity_dpm_setup_asic +ffffffff81d3db30 T trinity_dpm_display_configuration_changed +ffffffff81d3dbc0 T trinity_dpm_init +ffffffff81d3e4a0 T trinity_dpm_print_power_state +ffffffff81d3e5b0 T trinity_dpm_debugfs_print_current_performance_level +ffffffff81d3e640 T trinity_dpm_get_current_sclk +ffffffff81d3e6a0 T trinity_dpm_get_current_mclk +ffffffff81d3e6d0 T trinity_dpm_fini +ffffffff81d3e770 T trinity_dpm_get_sclk +ffffffff81d3e7c0 T trinity_dpm_get_mclk +ffffffff81d3e7f0 t trinity_program_power_level +ffffffff81d3f000 T trinity_dpm_bapm_enable +ffffffff81d3f150 T trinity_dpm_config +ffffffff81d3f230 T trinity_dpm_force_state +ffffffff81d3f310 T trinity_dpm_n_levels_disabled +ffffffff81d3f3f0 T trinity_uvd_dpm_config +ffffffff81d3f4c0 T trinity_dpm_no_forced_level +ffffffff81d3f590 T trinity_dce_enable_voltage_adjustment +ffffffff81d3f6e0 T trinity_gfx_dynamic_mgpg_config +ffffffff81d3f7b0 T trinity_acquire_mutex +ffffffff81d3f840 T trinity_release_mutex +ffffffff81d40000 T uvd_v1_0_get_rptr +ffffffff81d40040 T uvd_v1_0_get_wptr +ffffffff81d40080 T uvd_v1_0_set_wptr +ffffffff81d400c0 T uvd_v1_0_fence_emit +ffffffff81d404b0 T uvd_v1_0_resume +ffffffff81d40610 T uvd_v1_0_init +ffffffff81d40b90 T uvd_v1_0_start +ffffffff81d41310 T uvd_v1_0_fini +ffffffff81d41480 T uvd_v1_0_stop +ffffffff81d415f0 T uvd_v1_0_ring_test +ffffffff81d417c0 T uvd_v1_0_semaphore_emit +ffffffff81d417f0 T uvd_v1_0_ib_execute +ffffffff81d41980 T uvd_v1_0_ib_test +ffffffff81d42000 T uvd_v2_2_fence_emit +ffffffff81d42450 T uvd_v2_2_semaphore_emit +ffffffff81d42650 T uvd_v2_2_resume +ffffffff81d43000 T uvd_v3_1_semaphore_emit +ffffffff81d44000 T uvd_v4_2_resume +ffffffff81d45000 T vce_v1_0_get_rptr +ffffffff81d45090 T vce_v1_0_get_wptr +ffffffff81d45120 T vce_v1_0_set_wptr +ffffffff81d451b0 T vce_v1_0_enable_mgcg +ffffffff81d45470 T vce_v1_0_load_fw +ffffffff81d45640 T vce_v1_0_bo_size +ffffffff81d456b0 T vce_v1_0_resume +ffffffff81d46020 T vce_v1_0_start +ffffffff81d467e0 T vce_v1_0_init +ffffffff81d47000 T vce_v2_0_enable_mgcg +ffffffff81d47070 t vce_v2_0_set_dyn_cg +ffffffff81d47260 T vce_v2_0_bo_size +ffffffff81d472d0 T vce_v2_0_resume +ffffffff81d48000 T aldebaran_reset_init +ffffffff81d480c0 t aldebaran_async_reset +ffffffff81d48120 t aldebaran_get_reset_handler +ffffffff81d481c0 T aldebaran_reset_fini +ffffffff81d48220 t aldebaran_mode2_prepare_hwcontext +ffffffff81d48340 t aldebaran_mode2_perform_reset +ffffffff81d48500 t aldebaran_mode2_restore_hwcontext +ffffffff81d489e0 t aldebaran_mode2_reset +ffffffff81d49000 T aldebaran_reg_base_init +ffffffff81d4a000 T amdgpu_acpi_is_pcie_performance_request_supported +ffffffff81d4a040 T amdgpu_acpi_is_power_shift_control_supported +ffffffff81d4a070 T amdgpu_acpi_pcie_notify_device_ready +ffffffff81d4a180 T amdgpu_acpi_pcie_performance_request +ffffffff81d4a500 T amdgpu_acpi_power_shift_control +ffffffff81d4a640 T amdgpu_acpi_smart_shift_update +ffffffff81d4a6e0 T amdgpu_acpi_get_tmr_info +ffffffff81d4a770 T amdgpu_acpi_get_mem_info +ffffffff81d4a830 T amdgpu_acpi_init +ffffffff81d4a8e0 t amdgpu_acpi_event +ffffffff81d4abf0 T amdgpu_acpi_get_backlight_caps +ffffffff81d4ac40 T amdgpu_acpi_fini +ffffffff81d4ac60 T amdgpu_acpi_should_gpu_reset +ffffffff81d4acb0 T amdgpu_acpi_detect +ffffffff81d4b5e0 T amdgpu_acpi_release +ffffffff81d4c000 T amdgpu_afmt_acr +ffffffff81d4d000 T amdgpu_amdkfd_init +ffffffff81d4d040 T amdgpu_amdkfd_fini +ffffffff81d4d070 T amdgpu_amdkfd_device_probe +ffffffff81d4d0a0 T amdgpu_amdkfd_device_init +ffffffff81d4d260 t amdgpu_amdkfd_reset_work +ffffffff81d4d2e0 T amdgpu_amdkfd_device_fini_sw +ffffffff81d4d330 T amdgpu_amdkfd_interrupt +ffffffff81d4d360 T amdgpu_amdkfd_suspend +ffffffff81d4d390 T amdgpu_amdkfd_resume +ffffffff81d4d3c0 T amdgpu_amdkfd_pre_reset +ffffffff81d4d3f0 T amdgpu_amdkfd_post_reset +ffffffff81d4d420 T amdgpu_amdkfd_gpu_reset +ffffffff81d4d480 T amdgpu_amdkfd_alloc_gtt_mem +ffffffff81d4d730 t amdgpu_bo_reserve +ffffffff81d4d890 t amdgpu_bo_unreserve +ffffffff81d4d970 T amdgpu_amdkfd_free_gtt_mem +ffffffff81d4d9e0 T amdgpu_amdkfd_alloc_gws +ffffffff81d4dac0 T amdgpu_amdkfd_free_gws +ffffffff81d4db00 T amdgpu_amdkfd_get_fw_version +ffffffff81d4dbb0 T amdgpu_amdkfd_get_local_mem_info +ffffffff81d4dd50 T amdgpu_amdkfd_xcp_memory_size +ffffffff81d4ddf0 T amdgpu_amdkfd_get_gpu_clock_counter +ffffffff81d4de30 T amdgpu_amdkfd_get_max_engine_clock_in_mhz +ffffffff81d4de90 T amdgpu_amdkfd_get_cu_info +ffffffff81d4dfa0 T amdgpu_amdkfd_get_dmabuf_info +ffffffff81d4e0f0 T amdgpu_amdkfd_get_xgmi_hops_count +ffffffff81d4e160 T amdgpu_amdkfd_get_xgmi_bandwidth_mbytes +ffffffff81d4e1f0 T amdgpu_amdkfd_get_pcie_bandwidth_mbytes +ffffffff81d4e350 T amdgpu_amdkfd_submit_ib +ffffffff81d4e4b0 T amdgpu_amdkfd_set_compute_idle +ffffffff81d4e500 T amdgpu_amdkfd_is_kfd_vmid +ffffffff81d4e540 T amdgpu_amdkfd_flush_gpu_tlb_vmid +ffffffff81d4e670 T amdgpu_amdkfd_flush_gpu_tlb_pasid +ffffffff81d4e6b0 T amdgpu_amdkfd_have_atomics_support +ffffffff81d4e6e0 T amdgpu_amdkfd_debug_mem_fence +ffffffff81d4e700 T amdgpu_amdkfd_ras_poison_consumption_handler +ffffffff81d4e710 T amdgpu_amdkfd_send_close_event_drain_irq +ffffffff81d4e730 T amdgpu_amdkfd_ras_query_utcl2_poison_status +ffffffff81d4e780 T amdgpu_amdkfd_check_and_lock_kfd +ffffffff81d4e7b0 T amdgpu_amdkfd_unlock_kfd +ffffffff81d4e7e0 T amdgpu_amdkfd_unmap_hiq +ffffffff81d4f000 T amdgpu_atom_execute_table +ffffffff81d4f0a0 t amdgpu_atom_execute_table_locked +ffffffff81d4f3c0 T amdgpu_atom_parse +ffffffff81d4f910 T amdgpu_atom_destroy +ffffffff81d4f950 T amdgpu_atom_asic_init +ffffffff81d4fa70 t get_u32 +ffffffff81d4fad0 T amdgpu_atom_parse_data_header +ffffffff81d4fb70 T amdgpu_atom_parse_cmd_header +ffffffff81d4fbf0 t atom_op_move +ffffffff81d4fdc0 t atom_op_and +ffffffff81d4ffa0 t atom_op_or +ffffffff81d50180 t atom_op_shift_left +ffffffff81d50360 t atom_op_shift_right +ffffffff81d50540 t atom_op_mul +ffffffff81d50690 t atom_op_div +ffffffff81d50800 t atom_op_add +ffffffff81d509e0 t atom_op_sub +ffffffff81d50bc0 t atom_op_setport +ffffffff81d50d40 t atom_op_setregblock +ffffffff81d50e00 t atom_op_setfbbase +ffffffff81d50ec0 t atom_op_compare +ffffffff81d510a0 t atom_op_switch +ffffffff81d512d0 t atom_op_jump +ffffffff81d51540 t atom_op_test +ffffffff81d51700 t atom_op_delay +ffffffff81d517e0 t atom_op_calltable +ffffffff81d51930 t atom_op_repeat +ffffffff81d51960 t atom_op_clear +ffffffff81d51a70 t atom_op_nop +ffffffff81d51aa0 t atom_op_eot +ffffffff81d51ad0 t atom_op_mask +ffffffff81d51d80 t atom_op_postcard +ffffffff81d51e30 t atom_op_beep +ffffffff81d51e50 t atom_op_savereg +ffffffff81d51e80 t atom_op_restorereg +ffffffff81d51eb0 t atom_op_setdatablock +ffffffff81d51ff0 t atom_op_xor +ffffffff81d521d0 t atom_op_shl +ffffffff81d523f0 t atom_op_shr +ffffffff81d52610 t atom_op_debug +ffffffff81d526c0 t atom_op_processds +ffffffff81d52780 t atom_op_mul32 +ffffffff81d528e0 t atom_op_div32 +ffffffff81d52a70 t atom_put_dst +ffffffff81d52f80 t atom_get_src_int +ffffffff81d53600 t atom_iio_execute +ffffffff81d54000 T amdgpu_atombios_lookup_i2c_gpio +ffffffff81d54260 T amdgpu_atombios_i2c_init +ffffffff81d54520 T amdgpu_atombios_lookup_gpio +ffffffff81d54620 T amdgpu_atombios_has_dce_engine_info +ffffffff81d546a0 T amdgpu_atombios_get_connector_info_from_object_table +ffffffff81d54f00 T amdgpu_atombios_get_clock_info +ffffffff81d55240 T amdgpu_atombios_get_gfx_info +ffffffff81d55300 T amdgpu_atombios_get_vram_width +ffffffff81d55390 T amdgpu_atombios_get_asic_ss_info +ffffffff81d55670 t amdgpu_atombios_get_igp_ss_overrides +ffffffff81d55790 T amdgpu_atombios_get_clock_dividers +ffffffff81d559b0 T amdgpu_atombios_has_gpu_virtualization_table +ffffffff81d55a00 T amdgpu_atombios_scratch_regs_lock +ffffffff81d55a60 T amdgpu_atombios_scratch_regs_engine_hung +ffffffff81d55ab0 T amdgpu_atombios_scratch_regs_set_backlight_level +ffffffff81d55b10 T amdgpu_atombios_scratch_need_asic_init +ffffffff81d55b60 T amdgpu_atombios_copy_swap +ffffffff81d55b80 T amdgpu_atombios_sysfs_init +ffffffff81d55bb0 T amdgpu_atombios_fini +ffffffff81d55c60 T amdgpu_atombios_init +ffffffff81d55f00 t cail_reg_read +ffffffff81d55f20 t cail_reg_write +ffffffff81d55f40 t cail_mc_read +ffffffff81d55f70 t cail_mc_write +ffffffff81d55fa0 t cail_pll_read +ffffffff81d55fd0 t cail_pll_write +ffffffff81d56000 T amdgpu_atombios_get_data_table +ffffffff81d57000 T amdgpu_atombios_crtc_overscan_setup +ffffffff81d57150 T amdgpu_atombios_crtc_scaler_setup +ffffffff81d571d0 T amdgpu_atombios_crtc_lock +ffffffff81d57230 T amdgpu_atombios_crtc_enable +ffffffff81d57290 T amdgpu_atombios_crtc_blank +ffffffff81d572f0 T amdgpu_atombios_crtc_powergate +ffffffff81d57360 T amdgpu_atombios_crtc_powergate_init +ffffffff81d573d0 T amdgpu_atombios_crtc_set_dtd_timing +ffffffff81d57500 T amdgpu_atombios_crtc_set_disp_eng_pll +ffffffff81d575f0 T amdgpu_atombios_crtc_set_dce_clock +ffffffff81d576e0 T amdgpu_atombios_crtc_program_pll +ffffffff81d57a00 T amdgpu_atombios_crtc_prepare_pll +ffffffff81d57f00 T amdgpu_atombios_crtc_set_pll +ffffffff81d59000 T amdgpu_atombios_dp_aux_init +ffffffff81d59090 t amdgpu_atombios_dp_aux_transfer +ffffffff81d59200 T amdgpu_atombios_dp_get_sinktype +ffffffff81d59270 T amdgpu_atombios_dp_get_dpcd +ffffffff81d59420 T amdgpu_atombios_dp_get_panel_mode +ffffffff81d59510 T amdgpu_atombios_dp_set_link_config +ffffffff81d59590 t amdgpu_atombios_dp_get_dp_link_config +ffffffff81d59720 T amdgpu_atombios_dp_mode_valid_helper +ffffffff81d597a0 T amdgpu_atombios_dp_needs_link_train +ffffffff81d59810 T amdgpu_atombios_dp_set_rx_power_state +ffffffff81d59890 T amdgpu_atombios_dp_link_train +ffffffff81d59df0 t amdgpu_atombios_dp_process_aux_ch +ffffffff81d59f50 t amdgpu_atombios_dp_get_adjust_train +ffffffff81d5b000 T amdgpu_atombios_encoder_get_backlight_level_from_reg +ffffffff81d5b050 T amdgpu_atombios_encoder_set_backlight_level_to_reg +ffffffff81d5b0a0 T amdgpu_atombios_encoder_get_backlight_level +ffffffff81d5b100 T amdgpu_atombios_encoder_set_backlight_level +ffffffff81d5b210 T amdgpu_atombios_encoder_setup_dig_transmitter +ffffffff81d5bc30 T amdgpu_atombios_encoder_init_backlight +ffffffff81d5bdd0 t amdgpu_atombios_encoder_get_backlight_brightness +ffffffff81d5be30 T amdgpu_atombios_encoder_fini_backlight +ffffffff81d5bec0 T amdgpu_atombios_encoder_is_digital +ffffffff81d5bf10 T amdgpu_atombios_encoder_mode_fixup +ffffffff81d5bff0 T amdgpu_atombios_encoder_get_encoder_mode +ffffffff81d5c190 T amdgpu_atombios_encoder_setup_dig_encoder +ffffffff81d5c670 t amdgpu_atombios_encoder_get_bpc +ffffffff81d5c6c0 T amdgpu_atombios_encoder_set_edp_panel_power +ffffffff81d5c7c0 T amdgpu_atombios_encoder_dpms +ffffffff81d5c930 t amdgpu_atombios_encoder_setup_dig +ffffffff81d5cce0 t amdgpu_atombios_encoder_setup_dvo +ffffffff81d5ce90 T amdgpu_atombios_encoder_set_crtc_source +ffffffff81d5d270 T amdgpu_atombios_encoder_init_dig +ffffffff81d5d340 t amdgpu_atombios_encoder_setup_external_encoder +ffffffff81d5d5b0 T amdgpu_atombios_encoder_dac_detect +ffffffff81d5d770 T amdgpu_atombios_encoder_dig_detect +ffffffff81d5d870 T amdgpu_atombios_encoder_setup_ext_encoder_ddc +ffffffff81d5d8c0 T amdgpu_atombios_encoder_set_bios_scratch_regs +ffffffff81d5de10 T amdgpu_atombios_encoder_get_lcd_info +ffffffff81d5e170 T amdgpu_atombios_encoder_get_dig_info +ffffffff81d5e1e0 t amdgpu_atombios_encoder_update_backlight_status +ffffffff81d5f000 T amdgpu_atombios_i2c_xfer +ffffffff81d5f370 T amdgpu_atombios_i2c_func +ffffffff81d5f3a0 T amdgpu_atombios_i2c_channel_trans +ffffffff81d60000 T amdgpu_atomfirmware_query_firmware_capability +ffffffff81d600a0 T amdgpu_atomfirmware_gpu_virtualization_supported +ffffffff81d600e0 T amdgpu_atomfirmware_scratch_regs_init +ffffffff81d60160 T amdgpu_atomfirmware_allocate_fb_scratch +ffffffff81d60360 T amdgpu_atomfirmware_get_vram_info +ffffffff81d60800 t convert_atom_mem_type_to_vram_type +ffffffff81d60880 T amdgpu_atomfirmware_mem_ecc_supported +ffffffff81d60950 T amdgpu_atomfirmware_sram_ecc_supported +ffffffff81d60990 T amdgpu_atomfirmware_dynamic_boot_config_supported +ffffffff81d609d0 T amdgpu_atomfirmware_ras_rom_addr +ffffffff81d60a80 T amdgpu_atomfirmware_get_clock_info +ffffffff81d60cd0 T amdgpu_atomfirmware_get_gfx_info +ffffffff81d60e50 T amdgpu_atomfirmware_mem_training_supported +ffffffff81d60e90 T amdgpu_atomfirmware_get_fw_reserved_fb_size +ffffffff81d60f20 T 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athub_v3_0_set_clockgating +ffffffff81df20d0 T athub_v3_0_get_clockgating +ffffffff81df2120 t athub_v3_0_get_cg_cntl +ffffffff81df21c0 t athub_v3_0_set_cg_cntl +ffffffff81df3000 t cz_ih_early_init +ffffffff81df3050 t cz_ih_sw_init +ffffffff81df30b0 t cz_ih_sw_fini +ffffffff81df30f0 t cz_ih_hw_init +ffffffff81df3310 t cz_ih_hw_fini +ffffffff81df33e0 t cz_ih_suspend +ffffffff81df34b0 t cz_ih_resume +ffffffff81df34f0 t cz_ih_is_idle +ffffffff81df3540 t cz_ih_wait_for_idle +ffffffff81df35e0 t cz_ih_soft_reset +ffffffff81df36c0 t cz_ih_set_clockgating_state +ffffffff81df36f0 t cz_ih_set_powergating_state +ffffffff81df3720 t cz_ih_get_wptr +ffffffff81df3810 t cz_ih_decode_iv +ffffffff81df3890 t cz_ih_set_rptr +ffffffff81df4000 T dce_v10_0_disable_dce +ffffffff81df4150 t dce_v10_0_early_init +ffffffff81df4210 t dce_v10_0_sw_init +ffffffff81df4520 t dce_v10_0_sw_fini +ffffffff81df4640 t dce_v10_0_hw_init +ffffffff81df49a0 t dce_v10_0_hw_fini +ffffffff81df4b30 t dce_v10_0_suspend +ffffffff81df4b90 t dce_v10_0_resume +ffffffff81df4c00 t dce_v10_0_is_idle +ffffffff81df4c30 t dce_v10_0_wait_for_idle +ffffffff81df4c60 t dce_v10_0_check_soft_reset +ffffffff81df4c70 t dce_v10_0_soft_reset +ffffffff81df4d40 t dce_v10_0_set_clockgating_state +ffffffff81df4d70 t dce_v10_0_set_powergating_state +ffffffff81df4da0 t dce_v10_0_audio_endpt_rreg +ffffffff81df4e30 t dce_v10_0_audio_endpt_wreg +ffffffff81df4eb0 t dce_v10_0_bandwidth_update +ffffffff81df5920 t dce_v10_0_vblank_get_counter +ffffffff81df5970 t dce_v10_0_hpd_sense +ffffffff81df59d0 t dce_v10_0_hpd_set_polarity +ffffffff81df5aa0 t dce_v10_0_hpd_get_gpio_reg +ffffffff81df5ad0 t dce_v10_0_page_flip +ffffffff81df5bd0 t dce_v10_0_crtc_get_scanoutpos +ffffffff81df5c70 t dce_v10_0_encoder_add +ffffffff81df5ec0 t dce_v10_0_latency_watermark +ffffffff81df60f0 t dce_v10_0_encoder_destroy +ffffffff81df6150 t dce_v10_0_encoder_prepare +ffffffff81df6350 t dce_v10_0_encoder_commit +ffffffff81df6380 t dce_v10_0_encoder_mode_set +ffffffff81df72f0 t dce_v10_0_encoder_disable +ffffffff81df7400 t dce_v10_0_ext_dpms +ffffffff81df7430 t dce_v10_0_ext_prepare +ffffffff81df7460 t dce_v10_0_ext_commit +ffffffff81df7490 t dce_v10_0_ext_mode_set +ffffffff81df74c0 t dce_v10_0_ext_disable +ffffffff81df74f0 t dce_v10_0_set_crtc_irq_state +ffffffff81df75d0 t dce_v10_0_crtc_irq +ffffffff81df7810 t dce_v10_0_set_crtc_vblank_interrupt_state +ffffffff81df78e0 t dce_v10_0_set_crtc_vline_interrupt_state +ffffffff81df79b0 t dce_v10_0_set_pageflip_irq_state +ffffffff81df7a60 t dce_v10_0_pageflip_irq +ffffffff81df7bc0 t dce_v10_0_set_hpd_irq_state +ffffffff81df7c90 t dce_v10_0_hpd_irq +ffffffff81df7dc0 t dce_v10_0_afmt_init +ffffffff81df7ed0 t dce_v10_0_audio_init +ffffffff81df7fa0 t INIT_DELAYED_WORK +ffffffff81df7fe0 t dce_v10_0_crtc_cursor_set2 +ffffffff81df82a0 t dce_v10_0_crtc_cursor_move +ffffffff81df8370 t dce_v10_0_crtc_gamma_set +ffffffff81df83b0 t dce_v10_0_crtc_destroy +ffffffff81df83e0 t amdgpu_bo_reserve +ffffffff81df85e0 t amdgpu_bo_unreserve +ffffffff81df86c0 t dce_v10_0_lock_cursor +ffffffff81df8720 t dce_v10_0_cursor_move_locked +ffffffff81df8880 t dce_v10_0_show_cursor +ffffffff81df8920 t dce_v10_0_crtc_load_lut +ffffffff81df8cb0 t dce_v10_0_crtc_dpms +ffffffff81df8e90 t dce_v10_0_crtc_prepare +ffffffff81df8ed0 t dce_v10_0_crtc_commit +ffffffff81df8f00 t dce_v10_0_crtc_mode_fixup +ffffffff81df90b0 t dce_v10_0_crtc_mode_set +ffffffff81df9290 t dce_v10_0_crtc_set_base +ffffffff81df92b0 t dce_v10_0_crtc_set_base_atomic +ffffffff81df92d0 t dce_v10_0_crtc_disable +ffffffff81df9460 t dce_v10_0_crtc_do_set_base +ffffffff81df9b60 t __delayed_work_tick +ffffffff81df9b80 t dce_v10_0_is_display_hung +ffffffff81dfa000 T dce_v11_0_disable_dce +ffffffff81dfa160 t dce_v11_0_early_init +ffffffff81dfa290 t dce_v11_0_sw_init +ffffffff81dfa5b0 t dce_v11_0_sw_fini +ffffffff81dfa6d0 t dce_v11_0_hw_init +ffffffff81dfaa90 t dce_v11_0_hw_fini +ffffffff81dfac20 t dce_v11_0_suspend +ffffffff81dfac80 t dce_v11_0_resume +ffffffff81dfacf0 t dce_v11_0_is_idle +ffffffff81dfad20 t dce_v11_0_wait_for_idle +ffffffff81dfad50 t dce_v11_0_soft_reset +ffffffff81dfaf60 t dce_v11_0_set_clockgating_state +ffffffff81dfaf90 t dce_v11_0_set_powergating_state +ffffffff81dfafc0 t dce_v11_0_audio_endpt_rreg +ffffffff81dfb050 t dce_v11_0_audio_endpt_wreg +ffffffff81dfb0d0 t dce_v11_0_bandwidth_update +ffffffff81dfbb40 t dce_v11_0_vblank_get_counter +ffffffff81dfbb90 t dce_v11_0_hpd_sense +ffffffff81dfbbf0 t dce_v11_0_hpd_set_polarity +ffffffff81dfbcc0 t dce_v11_0_hpd_get_gpio_reg +ffffffff81dfbcf0 t dce_v11_0_page_flip +ffffffff81dfbdf0 t dce_v11_0_crtc_get_scanoutpos +ffffffff81dfbe90 t dce_v11_0_encoder_add +ffffffff81dfc0e0 t dce_v11_0_latency_watermark +ffffffff81dfc310 t dce_v11_0_encoder_destroy +ffffffff81dfc370 t dce_v11_0_encoder_prepare +ffffffff81dfc570 t dce_v11_0_encoder_commit +ffffffff81dfc5a0 t dce_v11_0_encoder_mode_set +ffffffff81dfd510 t dce_v11_0_encoder_disable +ffffffff81dfd620 t dce_v11_0_ext_dpms +ffffffff81dfd650 t dce_v11_0_ext_prepare +ffffffff81dfd680 t dce_v11_0_ext_commit +ffffffff81dfd6b0 t dce_v11_0_ext_mode_set +ffffffff81dfd6e0 t dce_v11_0_ext_disable +ffffffff81dfd710 t dce_v11_0_set_crtc_irq_state +ffffffff81dfd7f0 t dce_v11_0_crtc_irq +ffffffff81dfda10 t dce_v11_0_set_crtc_vblank_interrupt_state +ffffffff81dfdae0 t dce_v11_0_set_crtc_vline_interrupt_state +ffffffff81dfdbb0 t dce_v11_0_set_pageflip_irq_state +ffffffff81dfdc60 t dce_v11_0_pageflip_irq +ffffffff81dfddc0 t dce_v11_0_set_hpd_irq_state +ffffffff81dfde90 t dce_v11_0_hpd_irq +ffffffff81dfdfc0 t dce_v11_0_afmt_init +ffffffff81dfe0d0 t dce_v11_0_audio_init +ffffffff81dfe1d0 t INIT_DELAYED_WORK +ffffffff81dfe210 t dce_v11_0_crtc_cursor_set2 +ffffffff81dfe4d0 t dce_v11_0_crtc_cursor_move +ffffffff81dfe5a0 t dce_v11_0_crtc_gamma_set +ffffffff81dfe5e0 t dce_v11_0_crtc_destroy +ffffffff81dfe610 t amdgpu_bo_reserve +ffffffff81dfe810 t amdgpu_bo_unreserve +ffffffff81dfe8f0 t dce_v11_0_lock_cursor +ffffffff81dfe950 t dce_v11_0_cursor_move_locked +ffffffff81dfeab0 t dce_v11_0_show_cursor +ffffffff81dfeb50 t dce_v11_0_crtc_load_lut +ffffffff81dfeeb0 t dce_v11_0_crtc_dpms +ffffffff81dff090 t dce_v11_0_crtc_prepare +ffffffff81dff0d0 t dce_v11_0_crtc_commit +ffffffff81dff100 t dce_v11_0_crtc_mode_fixup +ffffffff81dff370 t dce_v11_0_crtc_mode_set +ffffffff81dff5d0 t dce_v11_0_crtc_set_base +ffffffff81dff5f0 t dce_v11_0_crtc_set_base_atomic +ffffffff81dff610 t dce_v11_0_crtc_disable +ffffffff81dff7b0 t dce_v11_0_crtc_do_set_base +ffffffff81dffeb0 t __delayed_work_tick +ffffffff81e00000 t df_v1_7_sw_init +ffffffff81e00040 t df_v1_7_sw_fini +ffffffff81e00070 t df_v1_7_enable_broadcast_mode +ffffffff81e001a0 t df_v1_7_get_fb_channel_number +ffffffff81e00230 t df_v1_7_get_hbm_channel_number +ffffffff81e00280 t df_v1_7_update_medium_grain_clock_gating +ffffffff81e00400 t df_v1_7_get_clockgating_state +ffffffff81e00490 t df_v1_7_enable_ecc_force_par_wr_rmw +ffffffff81e01000 t df_v3_6_sw_init +ffffffff81e01150 t df_v3_6_sw_fini +ffffffff81e01180 t df_v3_6_enable_broadcast_mode +ffffffff81e012b0 t df_v3_6_get_fb_channel_number +ffffffff81e01390 t df_v3_6_get_hbm_channel_number +ffffffff81e013e0 t df_v3_6_update_medium_grain_clock_gating +ffffffff81e01580 t df_v3_6_get_clockgating_state +ffffffff81e01610 t df_v3_6_pmc_start +ffffffff81e01910 t df_v3_6_pmc_stop +ffffffff81e01bb0 t df_v3_6_pmc_get_count +ffffffff81e01d40 t df_v3_6_get_fica +ffffffff81e01e30 t df_v3_6_set_fica +ffffffff81e01f10 t df_v3_6_query_ras_poison_mode +ffffffff81e03000 t df_v4_3_query_ras_poison_mode +ffffffff81e04000 T dimgrey_cavefish_reg_base_init +ffffffff81e05000 T emu_soc_asic_init +ffffffff81e06000 t gfx_v10_0_early_init +ffffffff81e067e0 t gfx_v10_0_late_init +ffffffff81e06850 t gfx_v10_0_sw_init +ffffffff81e06d60 t gfx_v10_0_sw_fini +ffffffff81e06f80 t gfx_v10_0_hw_init +ffffffff81e09ce0 t gfx_v10_0_hw_fini +ffffffff81e09dc0 t gfx_v10_0_suspend +ffffffff81e09e00 t gfx_v10_0_resume +ffffffff81e09e10 t gfx_v10_0_is_idle +ffffffff81e09ea0 t gfx_v10_0_wait_for_idle +ffffffff81e09fa0 t gfx_v10_0_soft_reset +ffffffff81e0a300 t gfx_v10_0_set_clockgating_state +ffffffff81e0a5b0 t gfx_v10_0_set_powergating_state +ffffffff81e0a670 t gfx_v10_0_get_clockgating_state +ffffffff81e0a780 t gfx_v10_0_get_gpu_clock_counter +ffffffff81e0ac90 t gfx_v10_0_select_se_sh +ffffffff81e0ad30 t gfx_v10_0_read_wave_data +ffffffff81e0af90 t gfx_v10_0_read_wave_vgprs +ffffffff81e0afc0 t gfx_v10_0_read_wave_sgprs +ffffffff81e0b040 t gfx_v10_0_select_me_pipe_q +ffffffff81e0b060 t gfx_v10_0_init_spm_golden_registers +ffffffff81e0b0d0 t gfx_v10_0_update_perfmon_mgcg +ffffffff81e0b200 t wave_read_ind +ffffffff81e0b2f0 t wave_read_regs +ffffffff81e0b450 t gfx10_kiq_set_resources +ffffffff81e0b770 t gfx10_kiq_map_queues +ffffffff81e0bb00 t gfx10_kiq_unmap_queues +ffffffff81e0bf00 t gfx10_kiq_query_status +ffffffff81e0c1f0 t gfx10_kiq_invalidate_tlbs +ffffffff81e0c310 t gfx_v10_0_ring_get_rptr_compute +ffffffff81e0c340 t gfx_v10_0_ring_get_wptr_compute +ffffffff81e0c3b0 t gfx_v10_0_ring_set_wptr_compute +ffffffff81e0c4f0 t gfx_v10_0_ring_emit_ib_compute +ffffffff81e0c830 t gfx_v10_0_ring_emit_fence_kiq +ffffffff81e0cc60 t gfx_v10_0_ring_test_ring +ffffffff81e0cec0 t gfx_v10_0_ring_test_ib +ffffffff81e0d150 t gfx_v10_0_ring_emit_rreg +ffffffff81e0d3e0 t gfx_v10_0_ring_emit_wreg +ffffffff81e0d610 t gfx_v10_0_ring_emit_reg_wait +ffffffff81e0d660 t gfx_v10_0_ring_emit_reg_write_reg_wait +ffffffff81e0d6f0 t gfx_v10_0_wait_reg_mem +ffffffff81e0da20 t gfx_v10_0_ring_get_rptr_gfx +ffffffff81e0da50 t gfx_v10_0_ring_get_wptr_gfx +ffffffff81e0db60 t gfx_v10_0_ring_set_wptr_gfx +ffffffff81e0dd70 t gfx_v10_0_ring_emit_ib_gfx +ffffffff81e0e3f0 t gfx_v10_0_ring_emit_fence +ffffffff81e0e7c0 t gfx_v10_0_ring_emit_pipeline_sync +ffffffff81e0e820 t gfx_v10_0_ring_emit_vm_flush +ffffffff81e0e9f0 t gfx_v10_0_ring_emit_hdp_flush +ffffffff81e0eac0 t gfx_v10_0_ring_emit_gds_switch +ffffffff81e0eba0 t gfx_v10_0_ring_emit_init_cond_exec +ffffffff81e0edd0 t gfx_v10_0_ring_emit_patch_cond_exec +ffffffff81e0ee90 t gfx_v10_0_ring_emit_sb +ffffffff81e0ef80 t gfx_v10_0_ring_emit_cntxcntl +ffffffff81e0f470 t gfx_v10_0_ring_emit_frame_cntl +ffffffff81e0f580 t gfx_v10_0_ring_soft_recovery +ffffffff81e0f5f0 t gfx_v10_0_ring_preempt_ib +ffffffff81e0f760 t gfx_v10_0_emit_mem_sync +ffffffff81e0fa90 t gfx_v10_0_write_data_to_reg +ffffffff81e0fca0 t gfx_v10_0_set_eop_interrupt_state +ffffffff81e0fd80 t gfx_v10_0_eop_irq +ffffffff81e0ff30 t gfx_v10_0_set_gfx_eop_interrupt_state +ffffffff81e100d0 t gfx_v10_0_set_compute_eop_interrupt_state +ffffffff81e10290 t gfx_v10_0_kiq_set_interrupt_state +ffffffff81e10580 t gfx_v10_0_kiq_irq +ffffffff81e10600 t gfx_v10_0_set_priv_reg_fault_state +ffffffff81e10740 t gfx_v10_0_priv_reg_irq +ffffffff81e107a0 t gfx_v10_0_handle_priv_fault +ffffffff81e10900 t gfx_v10_0_set_priv_inst_fault_state +ffffffff81e10a40 t gfx_v10_0_priv_inst_irq +ffffffff81e10aa0 t gfx_v10_0_is_rlc_enabled +ffffffff81e10b30 t gfx_v10_0_set_safe_mode +ffffffff81e10de0 t gfx_v10_0_unset_safe_mode +ffffffff81e10e90 t gfx_v10_0_rlc_init +ffffffff81e10eb0 t gfx_v10_0_get_csb_size +ffffffff81e10ee0 t gfx_v10_0_get_csb_buffer +ffffffff81e11050 t gfx_v10_0_rlc_resume +ffffffff81e11ac0 t gfx_v10_0_rlc_stop +ffffffff81e11ba0 t gfx_v10_0_rlc_reset +ffffffff81e11d50 t gfx_v10_0_rlc_start +ffffffff81e11f00 t gfx_v10_0_update_spm_vmid +ffffffff81e11f40 t gfx_v10_0_wait_for_rlc_autoload_complete +ffffffff81e12860 t gfx_v10_0_init_csb +ffffffff81e12b40 t gfx_v10_0_update_spm_vmid_internal +ffffffff81e12c60 t gfx_v10_0_rlc_backdoor_autoload_config_mec_cache +ffffffff81e12f30 t gfx_v10_0_is_rlcg_access_range +ffffffff81e12f60 t gfx_v10_0_gfx_mqd_init +ffffffff81e13350 t gfx_v10_0_compute_mqd_init +ffffffff81e13800 t gfx_v10_0_mec_init +ffffffff81e13a10 t gfx_v10_0_compute_ring_init +ffffffff81e13b50 t gfx_v10_0_rlc_backdoor_autoload_buffer_init +ffffffff81e13db0 t gfx_v10_0_gpu_early_init +ffffffff81e14010 t amdgpu_bo_unreserve +ffffffff81e140f0 t gfx_v10_0_cp_resume +ffffffff81e16ad0 t gfx_v10_3_get_disabled_sa +ffffffff81e16bf0 t gfx_v10_0_get_rb_active_bitmap +ffffffff81e16d20 t gfx_v10_0_get_wgp_active_bitmap_per_sh +ffffffff81e16e30 t gfx_v10_0_enable_gui_idle_interrupt +ffffffff81e16f40 t gfx_v10_0_cp_gfx_enable +ffffffff81e171b0 t gfx_v10_0_cp_compute_enable +ffffffff81e17350 t amdgpu_bo_reserve +ffffffff81e174c0 t gfx_v10_0_kiq_init_register +ffffffff81e18360 t gfx_v10_0_cp_gfx_switch_pipe +ffffffff81e18460 t gfx_v10_0_cp_gfx_set_doorbell +ffffffff81e18740 t gfx_v10_0_cp_gfx_start +ffffffff81e19130 t gfx_v10_0_update_fine_grain_clock_gating +ffffffff81e19480 t gfx_v10_0_update_medium_grain_clock_gating +ffffffff81e19bc0 t gfx_v10_0_update_3d_clock_gating +ffffffff81e19fb0 t gfx_v10_0_update_coarse_grain_clock_gating +ffffffff81e1a390 t gfx_v10_cntl_pg +ffffffff81e1b000 t gfx_v11_0_early_init +ffffffff81e1b750 t gfx_v11_0_late_init +ffffffff81e1b7c0 t gfx_v11_0_sw_init +ffffffff81e1bd00 t gfx_v11_0_sw_fini +ffffffff81e1bf10 t gfx_v11_0_hw_init +ffffffff81e20390 t gfx_v11_0_hw_fini +ffffffff81e20490 t gfx_v11_0_suspend +ffffffff81e204d0 t gfx_v11_0_resume +ffffffff81e204e0 t gfx_v11_0_is_idle +ffffffff81e20570 t gfx_v11_0_wait_for_idle +ffffffff81e20670 t gfx_v11_0_check_soft_reset +ffffffff81e207a0 t gfx_v11_0_soft_reset +ffffffff81e214e0 t gfx_v11_0_post_soft_reset +ffffffff81e214f0 t gfx_v11_0_set_clockgating_state +ffffffff81e22130 t gfx_v11_0_set_powergating_state +ffffffff81e221d0 t gfx_v11_0_get_clockgating_state +ffffffff81e223a0 t gfx_v11_0_get_gpu_clock_counter +ffffffff81e22720 t gfx_v11_0_select_se_sh +ffffffff81e227c0 t gfx_v11_0_read_wave_data +ffffffff81e22a00 t gfx_v11_0_read_wave_vgprs +ffffffff81e22a30 t gfx_v11_0_read_wave_sgprs +ffffffff81e22ab0 t gfx_v11_0_select_me_pipe_q +ffffffff81e22ad0 t gfx_v11_0_update_perf_clk +ffffffff81e22c00 t gfx_v11_0_get_gfx_shadow_info +ffffffff81e22c70 t wave_read_ind +ffffffff81e22d60 t wave_read_regs +ffffffff81e22ec0 t gfx11_kiq_set_resources +ffffffff81e231e0 t gfx11_kiq_map_queues +ffffffff81e23570 t gfx11_kiq_unmap_queues +ffffffff81e23970 t gfx11_kiq_query_status +ffffffff81e23c60 t gfx11_kiq_invalidate_tlbs +ffffffff81e23d80 t gfx_v11_0_ring_get_rptr_compute +ffffffff81e23db0 t gfx_v11_0_ring_get_wptr_compute +ffffffff81e23e20 t gfx_v11_0_ring_set_wptr_compute +ffffffff81e23f60 t gfx_v11_0_ring_emit_ib_compute +ffffffff81e242a0 t gfx_v11_0_ring_emit_fence_kiq +ffffffff81e246d0 t gfx_v11_0_ring_test_ring +ffffffff81e24950 t gfx_v11_0_ring_test_ib +ffffffff81e24bf0 t gfx_v11_0_ring_emit_rreg +ffffffff81e24e80 t gfx_v11_0_ring_emit_wreg +ffffffff81e250b0 t gfx_v11_0_ring_emit_reg_wait +ffffffff81e25100 t gfx_v11_0_ring_emit_reg_write_reg_wait +ffffffff81e25170 t gfx_v11_0_wait_reg_mem +ffffffff81e254a0 t gfx_v11_0_ring_get_rptr_gfx +ffffffff81e254d0 t gfx_v11_0_ring_get_wptr_gfx +ffffffff81e255e0 t gfx_v11_0_ring_set_wptr_gfx +ffffffff81e25800 t gfx_v11_0_ring_emit_ib_gfx +ffffffff81e25e90 t gfx_v11_0_ring_emit_fence +ffffffff81e26260 t gfx_v11_0_ring_emit_pipeline_sync +ffffffff81e262c0 t gfx_v11_0_ring_emit_vm_flush +ffffffff81e26490 t gfx_v11_0_ring_emit_hdp_flush +ffffffff81e26560 t gfx_v11_0_ring_emit_gds_switch +ffffffff81e26640 t gfx_v11_0_ring_emit_init_cond_exec +ffffffff81e26870 t gfx_v11_0_ring_emit_patch_cond_exec +ffffffff81e26930 t gfx_v11_0_ring_emit_cntxcntl +ffffffff81e26a90 t gfx_v11_0_ring_emit_gfx_shadow +ffffffff81e26e50 t gfx_v11_0_ring_emit_frame_cntl +ffffffff81e26f60 t gfx_v11_0_ring_soft_recovery +ffffffff81e26fd0 t gfx_v11_0_ring_preempt_ib +ffffffff81e27140 t gfx_v11_0_emit_mem_sync +ffffffff81e27470 t gfx_v11_0_write_data_to_reg +ffffffff81e27680 t gfx_v11_0_set_eop_interrupt_state +ffffffff81e27710 t gfx_v11_0_eop_irq +ffffffff81e278c0 t gfx_v11_0_set_gfx_eop_interrupt_state +ffffffff81e27a60 t gfx_v11_0_set_compute_eop_interrupt_state +ffffffff81e27bf0 t gfx_v11_0_set_priv_reg_fault_state +ffffffff81e27d30 t gfx_v11_0_priv_reg_irq +ffffffff81e27d90 t gfx_v11_0_handle_priv_fault +ffffffff81e27ef0 t gfx_v11_0_set_priv_inst_fault_state +ffffffff81e28030 t gfx_v11_0_priv_inst_irq +ffffffff81e28090 t gfx_v11_0_rlc_gc_fed_irq +ffffffff81e280e0 t gfx_v11_0_is_rlc_enabled +ffffffff81e28170 t gfx_v11_0_set_safe_mode +ffffffff81e282d0 t gfx_v11_0_unset_safe_mode +ffffffff81e28340 t gfx_v11_0_rlc_init +ffffffff81e283c0 t gfx_v11_0_get_csb_size +ffffffff81e283f0 t gfx_v11_0_get_csb_buffer +ffffffff81e28560 t gfx_v11_0_rlc_resume +ffffffff81e292c0 t gfx_v11_0_rlc_stop +ffffffff81e293a0 t gfx_v11_0_rlc_reset +ffffffff81e29550 t gfx_v11_0_rlc_start +ffffffff81e29700 t gfx_v11_0_update_spm_vmid +ffffffff81e29800 t gfx_v11_0_init_csb +ffffffff81e29990 t gfx_v11_0_gfx_mqd_init +ffffffff81e29d70 t gfx_v11_0_compute_mqd_init +ffffffff81e2a2a0 t gfx_v11_0_mec_init +ffffffff81e2a3e0 t gfx_v11_0_compute_ring_init +ffffffff81e2a520 t gfx_v11_0_rlc_autoload_buffer_init +ffffffff81e2a710 t gfx_v11_0_gpu_early_init +ffffffff81e2a7e0 t amdgpu_bo_unreserve +ffffffff81e2a8c0 t gfx_v11_0_disable_gpa_mode +ffffffff81e2aa60 t gfx_v11_0_cp_resume +ffffffff81e2e860 t gfx_v11_0_config_me_cache +ffffffff81e2ec20 t gfx_v11_0_config_pfp_cache +ffffffff81e2efe0 t gfx_v11_0_config_mec_cache +ffffffff81e2f3a0 t gfx_v11_0_enable_gui_idle_interrupt +ffffffff81e2f4b0 t gfx_v11_0_cp_compute_enable +ffffffff81e2f690 t gfx_v11_0_cp_gfx_enable +ffffffff81e2f8a0 t amdgpu_bo_reserve +ffffffff81e2fa10 t gfx_v11_0_kiq_init_register +ffffffff81e308b0 t gfx_v11_0_cp_gfx_switch_pipe +ffffffff81e30990 t gfx_v11_0_cp_gfx_set_doorbell +ffffffff81e30b70 t gfx_v11_0_cp_gfx_start +ffffffff81e313f0 t gfx_v11_cntl_pg +ffffffff81e32000 t gfx_v11_0_3_rlc_gc_fed_irq +ffffffff81e32200 t gfx_v11_0_3_poison_consumption_handler +ffffffff81e33000 t gfx_v8_0_early_init +ffffffff81e332f0 t gfx_v8_0_late_init +ffffffff81e33a10 t gfx_v8_0_sw_init +ffffffff81e33dd0 t gfx_v8_0_sw_fini +ffffffff81e33f70 t gfx_v8_0_hw_init +ffffffff81e36110 t gfx_v8_0_hw_fini +ffffffff81e365c0 t gfx_v8_0_suspend +ffffffff81e36600 t gfx_v8_0_resume +ffffffff81e36610 t gfx_v8_0_is_idle +ffffffff81e36680 t gfx_v8_0_wait_for_idle +ffffffff81e36730 t gfx_v8_0_check_soft_reset +ffffffff81e36810 t gfx_v8_0_pre_soft_reset +ffffffff81e36970 t gfx_v8_0_soft_reset +ffffffff81e36b30 t gfx_v8_0_post_soft_reset +ffffffff81e36cb0 t gfx_v8_0_set_clockgating_state +ffffffff81e36f30 t gfx_v8_0_set_powergating_state +ffffffff81e372e0 t gfx_v8_0_get_clockgating_state +ffffffff81e373c0 t gfx_v8_0_get_gpu_clock_counter +ffffffff81e37460 t gfx_v8_0_select_se_sh +ffffffff81e374c0 t gfx_v8_0_read_wave_data +ffffffff81e37960 t gfx_v8_0_read_wave_sgprs +ffffffff81e37a10 t gfx_v8_0_select_me_pipe_q +ffffffff81e37a30 t gfx_v8_0_ring_get_rptr +ffffffff81e37a60 t gfx_v8_0_ring_get_wptr_compute +ffffffff81e37a90 t gfx_v8_0_ring_set_wptr_compute +ffffffff81e37ad0 t gfx_v8_0_ring_emit_fence_kiq +ffffffff81e37ef0 t gfx_v8_0_ring_test_ring +ffffffff81e380f0 t gfx_v8_0_ring_emit_rreg +ffffffff81e38380 t gfx_v8_0_ring_emit_wreg +ffffffff81e385b0 t gfx_v8_0_ring_get_wptr_gfx +ffffffff81e38610 t gfx_v8_0_ring_set_wptr_gfx +ffffffff81e38680 t gfx_v8_0_ring_emit_ib_gfx +ffffffff81e38be0 t gfx_v8_0_ring_emit_fence_gfx +ffffffff81e390d0 t gfx_v8_0_ring_emit_pipeline_sync +ffffffff81e393c0 t gfx_v8_0_ring_emit_vm_flush +ffffffff81e39770 t gfx_v8_0_ring_emit_hdp_flush +ffffffff81e39a90 t gfx_v8_0_ring_emit_gds_switch +ffffffff81e3a240 t gfx_v8_0_ring_test_ib +ffffffff81e3a3f0 t gfx_v8_0_ring_emit_init_cond_exec +ffffffff81e3a620 t gfx_v8_0_ring_emit_patch_cond_exec +ffffffff81e3a6d0 t gfx_v8_ring_emit_sb +ffffffff81e3a7c0 t gfx_v8_ring_emit_cntxcntl +ffffffff81e3ad60 t gfx_v8_0_ring_soft_recovery +ffffffff81e3ad90 t gfx_v8_0_emit_mem_sync +ffffffff81e3af90 t gfx_v8_0_ring_emit_ib_compute +ffffffff81e3b290 t gfx_v8_0_ring_emit_fence_compute +ffffffff81e3b590 t gfx_v8_0_emit_mem_sync_compute +ffffffff81e3b850 t gfx_v8_0_emit_wave_limit +ffffffff81e3ba00 t gfx_v8_0_set_eop_interrupt_state +ffffffff81e3bc10 t gfx_v8_0_eop_irq +ffffffff81e3bd20 t gfx_v8_0_set_priv_reg_fault_state +ffffffff81e3bda0 t gfx_v8_0_priv_reg_irq +ffffffff81e3bea0 t gfx_v8_0_set_priv_inst_fault_state +ffffffff81e3bf20 t gfx_v8_0_priv_inst_irq +ffffffff81e3c020 t gfx_v8_0_set_cp_ecc_int_state +ffffffff81e3c280 t gfx_v8_0_cp_ecc_error_irq +ffffffff81e3c2d0 t gfx_v8_0_set_sq_int_state +ffffffff81e3c360 t gfx_v8_0_sq_irq +ffffffff81e3c3d0 t gfx_v8_0_parse_sq_irq +ffffffff81e3c620 t gfx_v8_0_is_rlc_enabled +ffffffff81e3c660 t gfx_v8_0_set_safe_mode +ffffffff81e3c760 t gfx_v8_0_unset_safe_mode +ffffffff81e3c800 t gfx_v8_0_rlc_init +ffffffff81e3c8b0 t gfx_v8_0_get_csb_size +ffffffff81e3c8e0 t gfx_v8_0_get_csb_buffer +ffffffff81e3ca50 t gfx_v8_0_cp_jump_table_num +ffffffff81e3ca90 t gfx_v8_0_rlc_resume +ffffffff81e3ce10 t gfx_v8_0_rlc_stop +ffffffff81e3ce80 t gfx_v8_0_rlc_reset +ffffffff81e3cf00 t gfx_v8_0_rlc_start +ffffffff81e3cf80 t gfx_v8_0_update_spm_vmid +ffffffff81e3cff0 t gfx_v8_0_init_save_restore_list +ffffffff81e3d400 t gfx_v8_0_wait_for_rlc_serdes +ffffffff81e3d620 t gfx_v8_0_sq_irq_work_func +ffffffff81e3d640 t gfx_v8_0_init_microcode +ffffffff81e3deb0 t gfx_v8_0_mec_init +ffffffff81e3dfb0 t gfx_v8_0_compute_ring_init +ffffffff81e3e0e0 t gfx_v8_0_gpu_early_init +ffffffff81e3e580 t amdgpu_bo_unreserve +ffffffff81e3e660 t gfx_v8_0_kiq_resume +ffffffff81e3e910 t gfx_v8_0_cp_gfx_resume +ffffffff81e3f3d0 t gfx_v8_0_kcq_resume +ffffffff81e3fd90 t amdgpu_bo_reserve +ffffffff81e3ff00 t gfx_v8_0_mqd_commit +ffffffff81e400e0 t gfx_v8_0_mqd_init +ffffffff81e40500 t gfx_v8_0_deactivate_hqd +ffffffff81e405c0 t gfx_v8_0_update_medium_grain_clock_gating +ffffffff81e40900 t gfx_v8_0_update_coarse_grain_clock_gating +ffffffff81e41000 t gfx_v9_0_ras_error_inject +ffffffff81e411b0 t gfx_v9_0_query_ras_error_count +ffffffff81e41d80 t gfx_v9_0_reset_ras_error_count +ffffffff81e427b0 T gfx_v9_0_select_se_sh +ffffffff81e42850 t gfx_v9_0_early_init +ffffffff81e43380 t gfx_v9_0_late_init +ffffffff81e44270 t gfx_v9_0_sw_init +ffffffff81e44920 t gfx_v9_0_sw_fini +ffffffff81e44ae0 t gfx_v9_0_hw_init +ffffffff81e47a90 t gfx_v9_0_hw_fini +ffffffff81e48240 t gfx_v9_0_suspend +ffffffff81e48280 t gfx_v9_0_resume +ffffffff81e48290 t gfx_v9_0_is_idle +ffffffff81e48310 t gfx_v9_0_wait_for_idle +ffffffff81e48400 t gfx_v9_0_soft_reset +ffffffff81e487a0 t gfx_v9_0_set_clockgating_state +ffffffff81e48870 t gfx_v9_0_set_powergating_state +ffffffff81e48c60 t gfx_v9_0_get_clockgating_state +ffffffff81e48d70 t gfx_v9_0_get_gpu_clock_counter +ffffffff81e49500 t gfx_v9_0_read_wave_data +ffffffff81e49740 t gfx_v9_0_read_wave_vgprs +ffffffff81e497a0 t gfx_v9_0_read_wave_sgprs +ffffffff81e497d0 t gfx_v9_0_select_me_pipe_q +ffffffff81e497f0 t wave_read_ind +ffffffff81e498e0 t wave_read_regs +ffffffff81e49a30 t gfx_v9_0_kiq_set_resources +ffffffff81e49d50 t gfx_v9_0_kiq_map_queues +ffffffff81e4a090 t gfx_v9_0_kiq_unmap_queues +ffffffff81e4a3c0 t gfx_v9_0_kiq_query_status +ffffffff81e4a6b0 t gfx_v9_0_kiq_invalidate_tlbs +ffffffff81e4a7d0 t gfx_v9_0_ring_get_rptr_compute +ffffffff81e4a800 t gfx_v9_0_ring_get_wptr_compute +ffffffff81e4a870 t gfx_v9_0_ring_set_wptr_compute +ffffffff81e4a8d0 t gfx_v9_0_ring_emit_fence_kiq +ffffffff81e4ad00 t gfx_v9_0_ring_test_ring +ffffffff81e4af30 t gfx_v9_0_ring_emit_rreg +ffffffff81e4b1c0 t gfx_v9_0_ring_emit_wreg +ffffffff81e4b3f0 t gfx_v9_0_ring_emit_reg_wait +ffffffff81e4b440 t gfx_v9_0_ring_emit_reg_write_reg_wait +ffffffff81e4b4e0 t gfx_v9_0_wait_reg_mem +ffffffff81e4b810 t gfx_v9_0_ring_get_rptr_gfx +ffffffff81e4b840 t gfx_v9_0_ring_get_wptr_gfx +ffffffff81e4b950 t gfx_v9_0_ring_set_wptr_gfx +ffffffff81e4ba80 t gfx_v9_0_ring_emit_ib_gfx +ffffffff81e4c100 t gfx_v9_0_ring_emit_fence +ffffffff81e4c4c0 t gfx_v9_0_ring_emit_pipeline_sync +ffffffff81e4c520 t gfx_v9_0_ring_emit_vm_flush +ffffffff81e4c630 t gfx_v9_0_ring_emit_hdp_flush +ffffffff81e4c700 t gfx_v9_0_ring_emit_gds_switch +ffffffff81e4c7e0 t gfx_v9_0_ring_emit_init_cond_exec +ffffffff81e4ca10 t gfx_v9_0_ring_emit_patch_cond_exec +ffffffff81e4cad0 t gfx_v9_ring_emit_sb +ffffffff81e4cbc0 t gfx_v9_ring_emit_cntxcntl +ffffffff81e4d0a0 t gfx_v9_0_ring_emit_frame_cntl +ffffffff81e4d1b0 t gfx_v9_0_ring_soft_recovery +ffffffff81e4d220 t gfx_v9_0_ring_preempt_ib +ffffffff81e4d3e0 t gfx_v9_0_emit_mem_sync +ffffffff81e4d6a0 t gfx_v9_0_write_data_to_reg +ffffffff81e4d8b0 t gfx_v9_0_ring_test_ib +ffffffff81e4da60 t gfx_v9_0_ring_patch_cntl +ffffffff81e4daa0 t gfx_v9_0_ring_patch_ce_meta +ffffffff81e4dba0 t gfx_v9_0_ring_patch_de_meta +ffffffff81e4dc70 t gfx_v9_0_ring_emit_ib_compute +ffffffff81e4dfa0 t gfx_v9_0_emit_wave_limit +ffffffff81e4e180 t gfx_v9_0_set_eop_interrupt_state +ffffffff81e4e360 t gfx_v9_0_eop_irq +ffffffff81e4e4a0 t gfx_v9_0_set_compute_eop_interrupt_state +ffffffff81e4e660 t gfx_v9_0_set_priv_reg_fault_state +ffffffff81e4e7a0 t gfx_v9_0_priv_reg_irq +ffffffff81e4e8a0 t gfx_v9_0_set_priv_inst_fault_state +ffffffff81e4e9e0 t gfx_v9_0_priv_inst_irq +ffffffff81e4eae0 t gfx_v9_0_set_cp_ecc_error_state +ffffffff81e4f370 t gfx_v9_0_is_rlc_enabled +ffffffff81e4f400 t gfx_v9_0_set_safe_mode +ffffffff81e4f560 t gfx_v9_0_unset_safe_mode +ffffffff81e4f5d0 t gfx_v9_0_rlc_init +ffffffff81e4f640 t gfx_v9_0_get_csb_size +ffffffff81e4f670 t gfx_v9_0_get_csb_buffer +ffffffff81e4f7b0 t gfx_v9_0_cp_jump_table_num +ffffffff81e4f800 t gfx_v9_0_rlc_resume +ffffffff81e50f10 t gfx_v9_0_rlc_stop +ffffffff81e512b0 t gfx_v9_0_rlc_reset +ffffffff81e51450 t gfx_v9_0_rlc_start +ffffffff81e515a0 t gfx_v9_0_update_spm_vmid +ffffffff81e515e0 t gfx_v9_0_is_rlcg_access_range +ffffffff81e51630 t gfx_v9_0_init_csb +ffffffff81e517c0 t gfx_v9_0_enable_lbpw +ffffffff81e518b0 t gfx_v9_0_update_spm_vmid_internal +ffffffff81e519d0 t gfx_v9_0_init_always_on_cu_mask +ffffffff81e51c60 t gfx_v9_0_enable_gui_idle_interrupt +ffffffff81e51d60 t gfx_v9_0_mec_init +ffffffff81e51f40 t gfx_v9_0_compute_ring_init +ffffffff81e52080 t gfx_v9_0_gpu_early_init +ffffffff81e524c0 t amdgpu_bo_unreserve +ffffffff81e525a0 t gfx_v9_0_cp_gfx_enable +ffffffff81e52690 t amdgpu_bo_reserve +ffffffff81e52800 t gfx_v9_0_kiq_init_register +ffffffff81e534e0 t gfx_v9_0_mqd_init +ffffffff81e53a30 t gfx_v9_0_update_medium_grain_clock_gating +ffffffff81e53f60 t gfx_v9_0_update_3d_clock_gating +ffffffff81e54350 t gfx_v9_0_update_coarse_grain_clock_gating +ffffffff81e55000 t gfx_v9_4_query_ras_error_count +ffffffff81e55e00 t gfx_v9_4_query_ras_error_status +ffffffff81e55fd0 t gfx_v9_4_reset_ras_error_count +ffffffff81e57000 T gfx_v9_4_2_do_edc_gpr_workarounds +ffffffff81e57720 T gfx_v9_4_2_init_golden_registers +ffffffff81e577b0 T gfx_v9_4_2_debug_trap_config_init +ffffffff81e57890 T gfx_v9_4_2_set_power_brake_sequence +ffffffff81e57a70 t gfx_v9_4_2_query_ras_error_count +ffffffff81e57b20 t gfx_v9_4_2_query_ras_error_status +ffffffff81e58380 t gfx_v9_4_2_reset_ras_error_count +ffffffff81e583e0 t gfx_v9_4_2_reset_ras_error_status +ffffffff81e588b0 t gfx_v9_4_2_enable_watchdog_timer +ffffffff81e58ad0 t gfx_v9_4_2_query_uctl2_poison_status +ffffffff81e58b50 t gfx_v9_4_2_run_shader +ffffffff81e58f50 t gfx_v9_4_2_wait_for_waves_assigned +ffffffff81e595a0 t gfx_v9_4_2_query_sram_edc_count +ffffffff81e598e0 t gfx_v9_4_2_query_utc_edc_count +ffffffff81e59ac0 t wave_read_ind +ffffffff81e5a000 t gfx_v9_4_3_xcp_suspend +ffffffff81e5a0a0 t gfx_v9_4_3_xcp_resume +ffffffff81e5a1e0 t gfx_v9_4_3_query_ras_error_count +ffffffff81e5a200 t gfx_v9_4_3_query_ras_error_status +ffffffff81e5a220 t gfx_v9_4_3_reset_ras_error_count +ffffffff81e5a240 t gfx_v9_4_3_reset_ras_error_status +ffffffff81e5a260 t gfx_v9_4_3_enable_watchdog_timer +ffffffff81e5a280 t gfx_v9_4_3_early_init +ffffffff81e5a940 t gfx_v9_4_3_late_init +ffffffff81e5a9c0 t gfx_v9_4_3_sw_init +ffffffff81e5ae20 t gfx_v9_4_3_sw_fini +ffffffff81e5afd0 t gfx_v9_4_3_hw_init +ffffffff81e5ba70 t gfx_v9_4_3_hw_fini +ffffffff81e5bb30 t gfx_v9_4_3_suspend +ffffffff81e5bbf0 t gfx_v9_4_3_resume +ffffffff81e5bc00 t gfx_v9_4_3_is_idle +ffffffff81e5bdb0 t gfx_v9_4_3_wait_for_idle +ffffffff81e5be40 t gfx_v9_4_3_soft_reset +ffffffff81e5c550 t gfx_v9_4_3_set_clockgating_state +ffffffff81e5c6b0 t gfx_v9_4_3_set_powergating_state +ffffffff81e5c6e0 t gfx_v9_4_3_get_clockgating_state +ffffffff81e5c850 t gfx_v9_4_3_kiq_set_resources +ffffffff81e5cb70 t gfx_v9_4_3_kiq_map_queues +ffffffff81e5ced0 t gfx_v9_4_3_kiq_unmap_queues +ffffffff81e5d250 t gfx_v9_4_3_kiq_query_status +ffffffff81e5d540 t gfx_v9_4_3_kiq_invalidate_tlbs +ffffffff81e5d660 t gfx_v9_4_3_ring_get_rptr_compute +ffffffff81e5d6a0 t gfx_v9_4_3_ring_get_wptr_compute +ffffffff81e5d710 t gfx_v9_4_3_ring_set_wptr_compute +ffffffff81e5d770 t gfx_v9_4_3_ring_emit_fence_kiq +ffffffff81e5dbc0 t gfx_v9_4_3_ring_test_ring +ffffffff81e5de20 t gfx_v9_4_3_ring_emit_rreg +ffffffff81e5e0b0 t gfx_v9_4_3_ring_emit_wreg +ffffffff81e5e2e0 t gfx_v9_4_3_ring_emit_reg_wait +ffffffff81e5e330 t gfx_v9_4_3_ring_emit_reg_write_reg_wait +ffffffff81e5e350 t gfx_v9_4_3_wait_reg_mem +ffffffff81e5e680 t gfx_v9_4_3_ring_emit_ib_compute +ffffffff81e5e9b0 t gfx_v9_4_3_ring_emit_fence +ffffffff81e5ed60 t gfx_v9_4_3_ring_emit_pipeline_sync +ffffffff81e5edc0 t gfx_v9_4_3_ring_emit_vm_flush +ffffffff81e5ede0 t gfx_v9_4_3_ring_emit_hdp_flush +ffffffff81e5eeb0 t gfx_v9_4_3_ring_emit_gds_switch +ffffffff81e5f050 t gfx_v9_4_3_ring_test_ib +ffffffff81e5f200 t gfx_v9_4_3_emit_mem_sync +ffffffff81e5f4c0 t gfx_v9_4_3_emit_wave_limit +ffffffff81e5f6b0 t gfx_v9_4_3_write_data_to_reg +ffffffff81e5f8c0 t gfx_v9_4_3_set_eop_interrupt_state +ffffffff81e5fa30 t gfx_v9_4_3_eop_irq +ffffffff81e5fbd0 t gfx_v9_4_3_xcc_set_compute_eop_interrupt_state +ffffffff81e5fd30 t gfx_v9_4_3_ih_to_xcc_inst +ffffffff81e5fe00 t gfx_v9_4_3_set_priv_reg_fault_state +ffffffff81e601e0 t gfx_v9_4_3_priv_reg_irq +ffffffff81e60240 t gfx_v9_4_3_fault +ffffffff81e603c0 t gfx_v9_4_3_set_priv_inst_fault_state +ffffffff81e607a0 t gfx_v9_4_3_priv_inst_irq +ffffffff81e60800 t gfx_v9_4_3_is_rlc_enabled +ffffffff81e60920 t gfx_v9_4_3_xcc_set_safe_mode +ffffffff81e60bc0 t gfx_v9_4_3_xcc_unset_safe_mode +ffffffff81e60ce0 t gfx_v9_4_3_rlc_init +ffffffff81e60d30 t gfx_v9_4_3_rlc_resume +ffffffff81e60df0 t gfx_v9_4_3_rlc_stop +ffffffff81e60e90 t gfx_v9_4_3_rlc_reset +ffffffff81e61520 t gfx_v9_4_3_rlc_start +ffffffff81e615c0 t gfx_v9_4_3_update_spm_vmid +ffffffff81e617d0 t gfx_v9_4_3_is_rlcg_access_range +ffffffff81e61880 t gfx_v9_4_3_xcc_rlc_resume +ffffffff81e620d0 t gfx_v9_4_3_xcc_rlc_stop +ffffffff81e627f0 t gfx_v9_4_3_xcc_rlc_start +ffffffff81e62b80 t gfx_v9_4_3_xcc_enable_gui_idle_interrupt +ffffffff81e62da0 t gfx_v9_4_3_xcc_select_se_sh +ffffffff81e62fa0 t gfx_v9_4_3_mec_init +ffffffff81e63290 t gfx_v9_4_3_gpu_early_init +ffffffff81e634c0 t amdgpu_bo_unreserve +ffffffff81e635a0 t gfx_v9_4_3_get_gpu_clock_counter +ffffffff81e638e0 t gfx_v9_4_3_read_wave_data +ffffffff81e63bb0 t gfx_v9_4_3_read_wave_vgprs +ffffffff81e63bd0 t gfx_v9_4_3_read_wave_sgprs +ffffffff81e63c20 t gfx_v9_4_3_select_me_pipe_q +ffffffff81e63c90 t gfx_v9_4_3_switch_compute_partition +ffffffff81e63ff0 t wave_read_ind +ffffffff81e641f0 t wave_read_regs +ffffffff81e64480 t gfx_v9_4_3_xcc_constants_init +ffffffff81e65500 t gfx_v9_4_3_xcc_cp_resume +ffffffff81e664b0 t gfx_v9_4_3_xcc_cp_compute_enable +ffffffff81e66650 t amdgpu_bo_reserve +ffffffff81e667c0 t gfx_v9_4_3_xcc_kiq_init_register +ffffffff81e68400 t gfx_v9_4_3_xcc_mqd_init +ffffffff81e68e40 t gfx_v9_4_3_xcc_fini +ffffffff81e693e0 t gfx_v9_4_3_xcc_q_fini_register +ffffffff81e69d90 t gfx_v9_4_3_xcc_update_sram_fgcg +ffffffff81e6a000 t gfx_v9_4_3_xcc_update_repeater_fgcg +ffffffff81e6a270 t gfx_v9_4_3_xcc_update_medium_grain_clock_gating +ffffffff81e6adc0 t gfx_v9_4_3_xcc_update_coarse_grain_clock_gating +ffffffff81e6b620 t gfx_v9_4_3_inst_query_ras_err_count +ffffffff81e6b880 t gfx_v9_4_3_inst_query_ras_err_status +ffffffff81e6c600 t gfx_v9_4_3_inst_reset_ras_err_count +ffffffff81e6c7c0 t gfx_v9_4_3_inst_reset_ras_err_status +ffffffff81e6cf40 t gfx_v9_4_3_inst_enable_watchdog_timer +ffffffff81e6e000 t gfxhub_v1_0_get_mc_fb_offset +ffffffff81e6e090 t gfxhub_v1_0_setup_vm_pt_regs +ffffffff81e6e1d0 t gfxhub_v1_0_gart_enable +ffffffff81e6f700 t gfxhub_v1_0_gart_disable +ffffffff81e6f9a0 t gfxhub_v1_0_set_fault_enable_default +ffffffff81e6faa0 t gfxhub_v1_0_init +ffffffff81e70000 T gfxhub_v1_1_get_xgmi_info +ffffffff81e71000 t gfxhub_v1_2_get_mc_fb_offset +ffffffff81e71120 t gfxhub_v1_2_setup_vm_pt_regs +ffffffff81e71190 t gfxhub_v1_2_gart_enable +ffffffff81e71220 t gfxhub_v1_2_gart_disable +ffffffff81e71280 t gfxhub_v1_2_set_fault_enable_default +ffffffff81e712f0 t gfxhub_v1_2_init +ffffffff81e715f0 t gfxhub_v1_2_get_xgmi_info +ffffffff81e71860 t gfxhub_v1_2_xcp_suspend +ffffffff81e718a0 t gfxhub_v1_2_xcp_resume +ffffffff81e71910 t gfxhub_v1_2_xcc_setup_vm_pt_regs +ffffffff81e71c30 t gfxhub_v1_2_xcc_gart_enable +ffffffff81e75070 t gfxhub_v1_2_xcc_gart_disable +ffffffff81e756e0 t gfxhub_v1_2_xcc_set_fault_enable_default +ffffffff81e76000 t gfxhub_v2_0_get_fb_location +ffffffff81e76090 t gfxhub_v2_0_get_mc_fb_offset +ffffffff81e76120 t gfxhub_v2_0_setup_vm_pt_regs +ffffffff81e76260 t gfxhub_v2_0_gart_enable +ffffffff81e77490 t gfxhub_v2_0_gart_disable +ffffffff81e776e0 t gfxhub_v2_0_set_fault_enable_default +ffffffff81e777e0 t gfxhub_v2_0_init +ffffffff81e778b0 t gfxhub_v2_0_print_l2_protection_fault_status +ffffffff81e77a80 t gfxhub_v2_0_get_invalidate_req +ffffffff81e78000 t gfxhub_v2_1_get_fb_location +ffffffff81e78090 t gfxhub_v2_1_get_mc_fb_offset +ffffffff81e78120 t gfxhub_v2_1_setup_vm_pt_regs +ffffffff81e78260 t gfxhub_v2_1_gart_enable +ffffffff81e79560 t gfxhub_v2_1_gart_disable +ffffffff81e797b0 t gfxhub_v2_1_set_fault_enable_default +ffffffff81e798d0 t gfxhub_v2_1_init +ffffffff81e799a0 t gfxhub_v2_1_get_xgmi_info +ffffffff81e79ae0 t gfxhub_v2_1_utcl2_harvest +ffffffff81e79cc0 t gfxhub_v2_1_save_regs +ffffffff81e7a730 t gfxhub_v2_1_restore_regs +ffffffff81e7b350 t gfxhub_v2_1_halt +ffffffff81e7b720 t gfxhub_v2_1_print_l2_protection_fault_status +ffffffff81e7b8f0 t gfxhub_v2_1_get_invalidate_req +ffffffff81e7c000 t gfxhub_v3_0_get_fb_location +ffffffff81e7c090 t gfxhub_v3_0_get_mc_fb_offset +ffffffff81e7c120 t gfxhub_v3_0_setup_vm_pt_regs +ffffffff81e7c260 t gfxhub_v3_0_gart_enable +ffffffff81e7d560 t gfxhub_v3_0_gart_disable +ffffffff81e7d800 t gfxhub_v3_0_set_fault_enable_default +ffffffff81e7d9d0 t gfxhub_v3_0_init +ffffffff81e7daa0 t gfxhub_v3_0_print_l2_protection_fault_status +ffffffff81e7dc70 t gfxhub_v3_0_get_invalidate_req +ffffffff81e7e000 t gfxhub_v3_0_3_get_fb_location +ffffffff81e7e090 t gfxhub_v3_0_3_get_mc_fb_offset +ffffffff81e7e120 t gfxhub_v3_0_3_setup_vm_pt_regs +ffffffff81e7e260 t gfxhub_v3_0_3_gart_enable +ffffffff81e7f450 t gfxhub_v3_0_3_gart_disable +ffffffff81e7f6f0 t gfxhub_v3_0_3_set_fault_enable_default +ffffffff81e7f810 t gfxhub_v3_0_3_init +ffffffff81e7f8e0 t gfxhub_v3_0_3_print_l2_protection_fault_status +ffffffff81e7fab0 t gfxhub_v3_0_3_get_invalidate_req +ffffffff81e80000 t gmc_v10_0_early_init +ffffffff81e80170 t gmc_v10_0_late_init +ffffffff81e801e0 t gmc_v10_0_sw_init +ffffffff81e805d0 t gmc_v10_0_sw_fini +ffffffff81e80620 t gmc_v10_0_hw_init +ffffffff81e80830 t gmc_v10_0_hw_fini +ffffffff81e808d0 t gmc_v10_0_suspend +ffffffff81e80970 t gmc_v10_0_resume +ffffffff81e809d0 t gmc_v10_0_is_idle +ffffffff81e80a00 t gmc_v10_0_wait_for_idle +ffffffff81e80a30 t gmc_v10_0_soft_reset +ffffffff81e80a60 t gmc_v10_0_set_clockgating_state +ffffffff81e80b10 t gmc_v10_0_set_powergating_state +ffffffff81e80b40 t gmc_v10_0_get_clockgating_state +ffffffff81e80be0 t gmc_v10_0_flush_gpu_tlb +ffffffff81e80e70 t gmc_v10_0_flush_gpu_tlb_pasid +ffffffff81e81120 t gmc_v10_0_emit_flush_gpu_tlb +ffffffff81e812d0 t gmc_v10_0_emit_pasid_mapping +ffffffff81e81350 t gmc_v10_0_map_mtype +ffffffff81e813a0 t gmc_v10_0_get_vm_pde +ffffffff81e81490 t gmc_v10_0_get_vm_pte +ffffffff81e81570 t gmc_v10_0_get_vbios_fb_size +ffffffff81e816e0 t gmc_v10_0_flush_vm_hub +ffffffff81e81b10 t gmc_v10_0_vm_fault_interrupt_state +ffffffff81e81bb0 t gmc_v10_0_process_interrupt +ffffffff81e81e90 t gmc_v10_0_ecc_interrupt_state +ffffffff81e81ec0 t gmc_v10_0_gart_init +ffffffff81e82000 t gmc_v11_0_early_init +ffffffff81e821f0 t gmc_v11_0_late_init +ffffffff81e82260 t gmc_v11_0_sw_init +ffffffff81e82570 t gmc_v11_0_sw_fini +ffffffff81e825c0 t gmc_v11_0_hw_init +ffffffff81e82720 t gmc_v11_0_hw_fini +ffffffff81e827a0 t gmc_v11_0_suspend +ffffffff81e82820 t gmc_v11_0_resume +ffffffff81e82880 t gmc_v11_0_is_idle +ffffffff81e828b0 t gmc_v11_0_wait_for_idle +ffffffff81e828e0 t gmc_v11_0_soft_reset +ffffffff81e82910 t gmc_v11_0_set_clockgating_state +ffffffff81e82990 t gmc_v11_0_set_powergating_state +ffffffff81e829c0 t gmc_v11_0_get_clockgating_state +ffffffff81e82a00 t gmc_v11_0_flush_gpu_tlb +ffffffff81e82eb0 t gmc_v11_0_flush_gpu_tlb_pasid +ffffffff81e83120 t gmc_v11_0_emit_flush_gpu_tlb +ffffffff81e832d0 t gmc_v11_0_emit_pasid_mapping +ffffffff81e83350 t gmc_v11_0_map_mtype +ffffffff81e833a0 t gmc_v11_0_get_vm_pde +ffffffff81e834a0 t gmc_v11_0_get_vm_pte +ffffffff81e83580 t gmc_v11_0_get_vbios_fb_size +ffffffff81e836f0 t gmc_v11_0_vm_fault_interrupt_state +ffffffff81e83790 t gmc_v11_0_process_interrupt +ffffffff81e839c0 t gmc_v11_0_ecc_interrupt_state +ffffffff81e839f0 t gmc_v11_0_gart_init +ffffffff81e84000 t gmc_v7_0_early_init +ffffffff81e840a0 t gmc_v7_0_late_init +ffffffff81e840f0 t gmc_v7_0_sw_init +ffffffff81e84520 t gmc_v7_0_sw_fini +ffffffff81e845a0 t gmc_v7_0_hw_init +ffffffff81e84f10 t gmc_v7_0_hw_fini +ffffffff81e84fd0 t gmc_v7_0_suspend +ffffffff81e85010 t gmc_v7_0_resume +ffffffff81e85070 t gmc_v7_0_is_idle +ffffffff81e850c0 t gmc_v7_0_wait_for_idle +ffffffff81e85160 t gmc_v7_0_soft_reset +ffffffff81e853c0 t gmc_v7_0_set_clockgating_state +ffffffff81e85620 t gmc_v7_0_set_powergating_state +ffffffff81e85650 t gmc_v7_0_flush_gpu_tlb +ffffffff81e85680 t gmc_v7_0_flush_gpu_tlb_pasid +ffffffff81e85740 t gmc_v7_0_emit_flush_gpu_tlb +ffffffff81e857e0 t gmc_v7_0_emit_pasid_mapping +ffffffff81e85810 t gmc_v7_0_set_prt +ffffffff81e859d0 t gmc_v7_0_get_vm_pde +ffffffff81e85a30 t gmc_v7_0_get_vm_pte +ffffffff81e85a70 t gmc_v7_0_get_vbios_fb_size +ffffffff81e85ae0 t gmc_v7_0_vm_fault_interrupt_state +ffffffff81e85bb0 t gmc_v7_0_process_interrupt +ffffffff81e85e50 t gmc_v7_0_gart_init +ffffffff81e86000 t gmc_v8_0_early_init +ffffffff81e860a0 t gmc_v8_0_late_init +ffffffff81e860f0 t gmc_v8_0_sw_init +ffffffff81e866a0 t gmc_v8_0_sw_fini +ffffffff81e86720 t gmc_v8_0_hw_init +ffffffff81e87390 t gmc_v8_0_hw_fini +ffffffff81e87450 t gmc_v8_0_suspend +ffffffff81e87490 t gmc_v8_0_resume +ffffffff81e874f0 t gmc_v8_0_is_idle +ffffffff81e87540 t gmc_v8_0_wait_for_idle +ffffffff81e875e0 t gmc_v8_0_check_soft_reset +ffffffff81e87650 t gmc_v8_0_pre_soft_reset +ffffffff81e877c0 t gmc_v8_0_soft_reset +ffffffff81e87890 t gmc_v8_0_post_soft_reset +ffffffff81e87900 t gmc_v8_0_set_clockgating_state +ffffffff81e87ec0 t gmc_v8_0_set_powergating_state +ffffffff81e87ef0 t gmc_v8_0_get_clockgating_state +ffffffff81e87f60 t gmc_v8_0_flush_gpu_tlb +ffffffff81e87f90 t gmc_v8_0_flush_gpu_tlb_pasid +ffffffff81e88050 t gmc_v8_0_emit_flush_gpu_tlb +ffffffff81e880f0 t gmc_v8_0_emit_pasid_mapping +ffffffff81e88120 t gmc_v8_0_set_prt +ffffffff81e882e0 t gmc_v8_0_get_vm_pde +ffffffff81e88340 t gmc_v8_0_get_vm_pte +ffffffff81e88390 t gmc_v8_0_get_vbios_fb_size +ffffffff81e88400 t gmc_v8_0_vm_fault_interrupt_state +ffffffff81e884d0 t gmc_v8_0_process_interrupt +ffffffff81e88860 t gmc_v8_0_gart_init +ffffffff81e89000 T gmc_v9_0_restore_registers +ffffffff81e89160 t gmc_v9_0_early_init +ffffffff81e89510 t gmc_v9_0_late_init +ffffffff81e89620 t gmc_v9_0_sw_init +ffffffff81e89d80 t gmc_v9_0_sw_fini +ffffffff81e89e40 t gmc_v9_0_hw_init +ffffffff81e8a2f0 t gmc_v9_0_hw_fini +ffffffff81e8a3b0 t gmc_v9_0_suspend +ffffffff81e8a470 t gmc_v9_0_resume +ffffffff81e8a4d0 t gmc_v9_0_is_idle +ffffffff81e8a500 t gmc_v9_0_wait_for_idle +ffffffff81e8a530 t gmc_v9_0_soft_reset +ffffffff81e8a560 t gmc_v9_0_set_clockgating_state +ffffffff81e8a5c0 t gmc_v9_0_set_powergating_state +ffffffff81e8a5f0 t gmc_v9_0_get_clockgating_state +ffffffff81e8a630 t gmc_v9_0_flush_gpu_tlb +ffffffff81e8acd0 t gmc_v9_0_flush_gpu_tlb_pasid +ffffffff81e8b080 t gmc_v9_0_emit_flush_gpu_tlb +ffffffff81e8b280 t gmc_v9_0_emit_pasid_mapping +ffffffff81e8b300 t gmc_v9_0_map_mtype +ffffffff81e8b340 t gmc_v9_0_get_vm_pde +ffffffff81e8b440 t gmc_v9_0_get_vm_pte +ffffffff81e8b770 t gmc_v9_0_override_vm_pte_flags +ffffffff81e8b830 t gmc_v9_0_get_vbios_fb_size +ffffffff81e8b9d0 t gmc_v9_0_query_memory_partition +ffffffff81e8ba30 t gmc_v9_0_vm_fault_interrupt_state +ffffffff81e8bed0 t gmc_v9_0_process_interrupt +ffffffff81e8c6d0 t gmc_v9_0_ecc_interrupt_state +ffffffff81e8c830 t gmc_v9_0_init_mem_ranges +ffffffff81e8cc50 t gmc_v9_0_gart_init +ffffffff81e8cd80 t gmc_v9_0_save_registers +ffffffff81e8d000 t hdp_v4_0_query_ras_error_count +ffffffff81e8d0c0 t hdp_v4_0_reset_ras_error_count +ffffffff81e8d1e0 t hdp_v4_0_flush_hdp +ffffffff81e8d230 t hdp_v4_0_invalidate_hdp +ffffffff81e8d310 t hdp_v4_0_update_clock_gating +ffffffff81e8d410 t hdp_v4_0_get_clockgating_state +ffffffff81e8d460 t hdp_v4_0_init_registers +ffffffff81e8e000 t hdp_v5_0_flush_hdp +ffffffff81e8e050 t hdp_v5_0_invalidate_hdp +ffffffff81e8e0f0 t hdp_v5_0_update_clock_gating +ffffffff81e8e4f0 t hdp_v5_0_get_clockgating_state +ffffffff81e8e610 t hdp_v5_0_init_registers +ffffffff81e8f000 t hdp_v5_2_flush_hdp +ffffffff81e8f050 t hdp_v5_2_update_clock_gating +ffffffff81e8f460 t hdp_v5_2_get_clockgating_state +ffffffff81e90000 t hdp_v6_0_flush_hdp +ffffffff81e90050 t hdp_v6_0_update_clock_gating +ffffffff81e90380 t hdp_v6_0_get_clockgating_state +ffffffff81e91000 t iceland_ih_early_init +ffffffff81e91050 t iceland_ih_sw_init +ffffffff81e910b0 t iceland_ih_sw_fini +ffffffff81e910f0 t iceland_ih_hw_init +ffffffff81e91310 t iceland_ih_hw_fini +ffffffff81e913e0 t iceland_ih_suspend +ffffffff81e914b0 t iceland_ih_resume +ffffffff81e914f0 t iceland_ih_is_idle +ffffffff81e91540 t iceland_ih_wait_for_idle +ffffffff81e915e0 t iceland_ih_soft_reset +ffffffff81e916c0 t iceland_ih_set_clockgating_state +ffffffff81e916f0 t iceland_ih_set_powergating_state +ffffffff81e91720 t iceland_ih_get_wptr +ffffffff81e91810 t iceland_ih_decode_iv +ffffffff81e91890 t iceland_ih_set_rptr +ffffffff81e92000 t ih_v6_0_early_init +ffffffff81e92050 t ih_v6_0_sw_init +ffffffff81e921b0 t ih_v6_0_sw_fini +ffffffff81e921f0 t ih_v6_0_hw_init +ffffffff81e927a0 t ih_v6_0_hw_fini +ffffffff81e92800 t ih_v6_0_suspend +ffffffff81e92860 t ih_v6_0_resume +ffffffff81e92870 t ih_v6_0_is_idle +ffffffff81e928a0 t ih_v6_0_wait_for_idle +ffffffff81e928d0 t ih_v6_0_soft_reset +ffffffff81e92900 t ih_v6_0_set_clockgating_state +ffffffff81e92a30 t ih_v6_0_set_powergating_state +ffffffff81e92bb0 t ih_v6_0_get_clockgating_state +ffffffff81e92c40 t ih_v6_0_get_wptr +ffffffff81e92d30 t ih_v6_0_set_rptr +ffffffff81e92e00 t ih_v6_0_self_irq +ffffffff81e92e70 t ih_v6_0_toggle_interrupts +ffffffff81e93050 t force_update_wptr_for_self_int +ffffffff81e94000 t ih_v6_1_early_init +ffffffff81e94050 t ih_v6_1_sw_init +ffffffff81e941b0 t ih_v6_1_sw_fini +ffffffff81e941f0 t ih_v6_1_hw_init +ffffffff81e947a0 t ih_v6_1_hw_fini +ffffffff81e94800 t ih_v6_1_suspend +ffffffff81e94860 t ih_v6_1_resume +ffffffff81e94870 t ih_v6_1_is_idle +ffffffff81e948a0 t ih_v6_1_wait_for_idle +ffffffff81e948d0 t ih_v6_1_soft_reset +ffffffff81e94900 t ih_v6_1_set_clockgating_state +ffffffff81e94a30 t ih_v6_1_set_powergating_state +ffffffff81e94bb0 t ih_v6_1_get_clockgating_state +ffffffff81e94c40 t ih_v6_1_get_wptr +ffffffff81e94d30 t ih_v6_1_set_rptr +ffffffff81e94e00 t ih_v6_1_self_irq +ffffffff81e94e70 t ih_v6_1_toggle_interrupts +ffffffff81e95050 t force_update_wptr_for_self_int +ffffffff81e96000 t imu_v11_0_init_microcode +ffffffff81e96170 t imu_v11_0_load_microcode +ffffffff81e964f0 t imu_v11_0_setup +ffffffff81e96780 t imu_v11_0_start +ffffffff81e96880 t imu_v11_0_program_rlc_ram +ffffffff81e96a40 t imu_v11_0_wait_for_reset_status +ffffffff81e96b90 t program_imu_rlc_ram +ffffffff81e97000 T imu_v11_0_3_program_rlc_ram +ffffffff81e98000 T jpeg_v1_0_early_init +ffffffff81e98080 T jpeg_v1_0_sw_init +ffffffff81e98170 T jpeg_v1_0_sw_fini +ffffffff81e98190 T jpeg_v1_0_start +ffffffff81e98c40 t jpeg_v1_0_decode_ring_get_rptr +ffffffff81e98cd0 t jpeg_v1_0_decode_ring_get_wptr +ffffffff81e98d60 t jpeg_v1_0_decode_ring_set_wptr +ffffffff81e98dd0 t jpeg_v1_0_decode_ring_emit_ib +ffffffff81e996f0 t jpeg_v1_0_decode_ring_emit_fence +ffffffff81e9a030 t jpeg_v1_0_decode_ring_emit_vm_flush +ffffffff81e9a0a0 t jpeg_v1_0_decode_ring_nop +ffffffff81e9a200 t jpeg_v1_0_decode_ring_insert_start +ffffffff81e9a3c0 t jpeg_v1_0_decode_ring_insert_end +ffffffff81e9a580 t jpeg_v1_0_ring_begin_use +ffffffff81e9a680 t jpeg_v1_0_decode_ring_emit_wreg +ffffffff81e9a8e0 t jpeg_v1_0_decode_ring_emit_reg_wait +ffffffff81e9ad00 t jpeg_v1_0_set_interrupt_state +ffffffff81e9ad30 t jpeg_v1_0_process_interrupt +ffffffff81e9b000 T jpeg_v2_0_dec_ring_insert_start +ffffffff81e9b1a0 T jpeg_v2_0_dec_ring_insert_end +ffffffff81e9b340 T jpeg_v2_0_dec_ring_emit_fence +ffffffff81e9ba20 T jpeg_v2_0_dec_ring_emit_ib +ffffffff81e9c1d0 T jpeg_v2_0_dec_ring_emit_reg_wait +ffffffff81e9c580 T jpeg_v2_0_dec_ring_emit_vm_flush +ffffffff81e9c5f0 T jpeg_v2_0_dec_ring_emit_wreg +ffffffff81e9c830 T jpeg_v2_0_dec_ring_nop +ffffffff81e9c990 t jpeg_v2_0_early_init +ffffffff81e9ca20 t jpeg_v2_0_sw_init +ffffffff81e9cb50 t jpeg_v2_0_sw_fini +ffffffff81e9cba0 t jpeg_v2_0_hw_init +ffffffff81e9cc20 t jpeg_v2_0_hw_fini +ffffffff81e9cd00 t jpeg_v2_0_suspend +ffffffff81e9cd30 t jpeg_v2_0_resume +ffffffff81e9cdc0 t jpeg_v2_0_is_idle +ffffffff81e9ce50 t jpeg_v2_0_wait_for_idle +ffffffff81e9ce90 t jpeg_v2_0_set_clockgating_state +ffffffff81e9cf40 t jpeg_v2_0_set_powergating_state +ffffffff81e9d660 t jpeg_v2_0_dec_ring_get_rptr +ffffffff81e9d6f0 t jpeg_v2_0_dec_ring_get_wptr +ffffffff81e9d790 t jpeg_v2_0_dec_ring_set_wptr +ffffffff81e9d830 t jpeg_v2_0_set_interrupt_state +ffffffff81e9d860 t jpeg_v2_0_process_interrupt +ffffffff81e9d8f0 t jpeg_v2_0_enable_clock_gating +ffffffff81e9daa0 t jpeg_v2_0_disable_clock_gating +ffffffff81e9e000 t jpeg_v2_6_query_ras_poison_status +ffffffff81e9e150 t jpeg_v2_5_early_init +ffffffff81e9e350 t jpeg_v2_5_sw_init +ffffffff81e9e5f0 t jpeg_v2_5_sw_fini +ffffffff81e9e640 t jpeg_v2_5_hw_init +ffffffff81e9e730 t jpeg_v2_5_hw_fini +ffffffff81e9e8b0 t jpeg_v2_5_suspend +ffffffff81e9e8e0 t jpeg_v2_5_resume +ffffffff81e9e9e0 t jpeg_v2_5_is_idle +ffffffff81e9eae0 t jpeg_v2_5_wait_for_idle +ffffffff81e9eb90 t jpeg_v2_5_set_clockgating_state +ffffffff81e9ec40 t jpeg_v2_5_set_powergating_state +ffffffff81e9f370 t jpeg_v2_5_dec_ring_get_rptr +ffffffff81e9f410 t jpeg_v2_5_dec_ring_get_wptr +ffffffff81e9f4c0 t jpeg_v2_5_dec_ring_set_wptr +ffffffff81e9f570 t jpeg_v2_6_dec_ring_insert_start +ffffffff81e9f730 t jpeg_v2_6_dec_ring_insert_end +ffffffff81e9f8f0 t jpeg_v2_5_set_interrupt_state +ffffffff81e9f920 t jpeg_v2_5_process_interrupt +ffffffff81e9f9e0 t jpeg_v2_6_set_ras_interrupt_state +ffffffff81e9fa10 t jpeg_v2_5_enable_clock_gating +ffffffff81e9faf0 t jpeg_v2_5_disable_clock_gating +ffffffff81ea0000 t jpeg_v3_0_early_init +ffffffff81ea0110 t jpeg_v3_0_sw_init +ffffffff81ea0240 t jpeg_v3_0_sw_fini +ffffffff81ea0290 t jpeg_v3_0_hw_init +ffffffff81ea0310 t jpeg_v3_0_hw_fini +ffffffff81ea03f0 t jpeg_v3_0_suspend +ffffffff81ea0420 t jpeg_v3_0_resume +ffffffff81ea04b0 t jpeg_v3_0_is_idle +ffffffff81ea0540 t jpeg_v3_0_wait_for_idle +ffffffff81ea0580 t jpeg_v3_0_set_clockgating_state +ffffffff81ea0630 t jpeg_v3_0_set_powergating_state +ffffffff81ea0e10 t jpeg_v3_0_dec_ring_get_rptr +ffffffff81ea0ea0 t jpeg_v3_0_dec_ring_get_wptr +ffffffff81ea0f40 t jpeg_v3_0_dec_ring_set_wptr +ffffffff81ea0fe0 t jpeg_v3_0_set_interrupt_state +ffffffff81ea1010 t jpeg_v3_0_process_interrupt +ffffffff81ea10a0 t jpeg_v3_0_enable_clock_gating +ffffffff81ea1170 t jpeg_v3_0_disable_clock_gating +ffffffff81ea2000 t jpeg_v4_0_query_ras_poison_status +ffffffff81ea2150 t jpeg_v4_0_early_init +ffffffff81ea2220 t jpeg_v4_0_sw_init +ffffffff81ea23c0 t jpeg_v4_0_sw_fini +ffffffff81ea2410 t jpeg_v4_0_hw_init +ffffffff81ea2a40 t jpeg_v4_0_hw_fini +ffffffff81ea2b10 t jpeg_v4_0_suspend +ffffffff81ea2b40 t jpeg_v4_0_resume +ffffffff81ea2b90 t jpeg_v4_0_is_idle +ffffffff81ea2c20 t jpeg_v4_0_wait_for_idle +ffffffff81ea2c60 t jpeg_v4_0_set_clockgating_state +ffffffff81ea2d10 t jpeg_v4_0_set_powergating_state +ffffffff81ea3470 t jpeg_v4_0_dec_ring_get_rptr +ffffffff81ea3500 t jpeg_v4_0_dec_ring_get_wptr +ffffffff81ea35a0 t jpeg_v4_0_dec_ring_set_wptr +ffffffff81ea3640 t jpeg_v4_0_set_interrupt_state +ffffffff81ea3670 t jpeg_v4_0_process_interrupt +ffffffff81ea3710 t jpeg_v4_0_set_ras_interrupt_state +ffffffff81ea3740 t jpeg_v4_0_enable_clock_gating +ffffffff81ea3900 t jpeg_v4_0_disable_clock_gating +ffffffff81ea4000 t jpeg_v4_0_3_early_init +ffffffff81ea4170 t jpeg_v4_0_3_sw_init +ffffffff81ea44a0 t jpeg_v4_0_3_sw_fini +ffffffff81ea44f0 t jpeg_v4_0_3_hw_init +ffffffff81ea4f50 t jpeg_v4_0_3_hw_fini +ffffffff81ea4fe0 t jpeg_v4_0_3_suspend +ffffffff81ea5060 t jpeg_v4_0_3_resume +ffffffff81ea50b0 t jpeg_v4_0_3_is_idle +ffffffff81ea5290 t jpeg_v4_0_3_wait_for_idle +ffffffff81ea53e0 t jpeg_v4_0_3_set_clockgating_state +ffffffff81ea5470 t jpeg_v4_0_3_set_powergating_state +ffffffff81ea60d0 t jpeg_v4_0_3_dec_ring_get_rptr +ffffffff81ea6240 t jpeg_v4_0_3_dec_ring_get_wptr +ffffffff81ea63d0 t jpeg_v4_0_3_dec_ring_set_wptr +ffffffff81ea6570 t jpeg_v4_0_3_dec_ring_emit_ib +ffffffff81ea6dd0 t jpeg_v4_0_3_dec_ring_emit_fence +ffffffff81ea7560 t jpeg_v4_0_3_dec_ring_emit_vm_flush +ffffffff81ea75d0 t jpeg_v4_0_3_dec_ring_nop +ffffffff81ea7730 t jpeg_v4_0_3_dec_ring_insert_start +ffffffff81ea78d0 t jpeg_v4_0_3_dec_ring_insert_end +ffffffff81ea7a70 t jpeg_v4_0_3_dec_ring_emit_wreg +ffffffff81ea7cb0 t jpeg_v4_0_3_dec_ring_emit_reg_wait +ffffffff81ea8060 t jpeg_v4_0_3_set_interrupt_state +ffffffff81ea8090 t jpeg_v4_0_3_process_interrupt +ffffffff81ea82d0 t jpeg_v4_0_3_query_ras_error_count +ffffffff81ea83c0 t jpeg_v4_0_3_reset_ras_error_count +ffffffff81ea84b0 t jpeg_v4_0_3_disable_clock_gating +ffffffff81ea9000 t lsdma_v6_0_copy_mem +ffffffff81ea9370 t lsdma_v6_0_fill_mem +ffffffff81ea9660 t lsdma_v6_0_update_memory_power_gating +ffffffff81eaa000 t mca_v3_0_ras_block_match +ffffffff81eaa050 t mca_v3_0_mp0_query_ras_error_count +ffffffff81eaa070 t mca_v3_0_mp1_query_ras_error_count +ffffffff81eaa090 t mca_v3_0_mpio_query_ras_error_count +ffffffff81eab000 t mes_v10_0_early_init +ffffffff81eab060 t mes_v10_0_late_init +ffffffff81eab0b0 t mes_v10_1_sw_init +ffffffff81eab550 t mes_v10_1_sw_fini +ffffffff81eab670 t mes_v10_1_hw_init +ffffffff81eabf60 t mes_v10_1_hw_fini +ffffffff81eac050 t mes_v10_1_suspend +ffffffff81eac160 t mes_v10_1_resume +ffffffff81eac1b0 t mes_v10_1_kiq_hw_init +ffffffff81eac5c0 t mes_v10_1_add_hw_queue +ffffffff81eac740 t mes_v10_1_remove_hw_queue +ffffffff81eac7d0 t mes_v10_1_unmap_legacy_queue +ffffffff81eac8c0 t mes_v10_1_suspend_gang +ffffffff81eac8f0 t mes_v10_1_resume_gang +ffffffff81eac920 t mes_v10_1_submit_pkt_and_poll_completion +ffffffff81eacb20 t mes_v10_1_load_microcode +ffffffff81ead340 t mes_v10_1_enable +ffffffff81ead7c0 t mes_v10_1_queue_init +ffffffff81eada60 t amdgpu_bo_unreserve +ffffffff81eadb40 t mes_v10_1_ring_get_rptr +ffffffff81eadb70 t mes_v10_1_ring_get_wptr +ffffffff81eadbe0 t mes_v10_1_ring_set_wptr +ffffffff81eae000 t mes_v11_0_early_init +ffffffff81eae060 t mes_v11_0_late_init +ffffffff81eae0d0 t mes_v11_0_sw_init +ffffffff81eae570 t mes_v11_0_sw_fini +ffffffff81eae730 t mes_v11_0_hw_init +ffffffff81eaef60 t mes_v11_0_hw_fini +ffffffff81eaef90 t mes_v11_0_suspend +ffffffff81eaefa0 t mes_v11_0_resume +ffffffff81eaeff0 t mes_v11_0_kiq_hw_init +ffffffff81eaf200 t mes_v11_0_kiq_hw_fini +ffffffff81eaf340 t mes_v11_0_add_hw_queue +ffffffff81eaf540 t mes_v11_0_remove_hw_queue +ffffffff81eaf5d0 t mes_v11_0_unmap_legacy_queue +ffffffff81eaf6d0 t mes_v11_0_suspend_gang +ffffffff81eaf700 t mes_v11_0_resume_gang +ffffffff81eaf730 t mes_v11_0_misc_op +ffffffff81eaf8f0 t mes_v11_0_submit_pkt_and_poll_completion +ffffffff81eafb10 t mes_v11_0_load_microcode +ffffffff81eb02a0 t mes_v11_0_enable +ffffffff81eb07b0 t mes_v11_0_queue_init +ffffffff81eb1250 t amdgpu_bo_unreserve +ffffffff81eb1330 t mes_v11_0_mqd_init +ffffffff81eb1520 t mes_v11_0_kiq_dequeue +ffffffff81eb1960 t mes_v11_0_ring_get_rptr +ffffffff81eb1990 t mes_v11_0_ring_get_wptr +ffffffff81eb1a00 t mes_v11_0_ring_set_wptr +ffffffff81eb2000 t mmhub_v1_0_query_ras_error_count +ffffffff81eb2150 t mmhub_v1_0_reset_ras_error_count +ffffffff81eb2200 t mmhub_v1_0_get_fb_location +ffffffff81eb2320 t mmhub_v1_0_init +ffffffff81eb23d0 t mmhub_v1_0_gart_enable +ffffffff81eb3720 t mmhub_v1_0_set_fault_enable_default +ffffffff81eb3840 t mmhub_v1_0_gart_disable +ffffffff81eb3ae0 t mmhub_v1_0_set_clockgating +ffffffff81eb3f70 t mmhub_v1_0_get_clockgating +ffffffff81eb4090 t mmhub_v1_0_setup_vm_pt_regs +ffffffff81eb41d0 t mmhub_v1_0_update_power_gating +ffffffff81eb5000 t mmhub_v1_7_query_ras_error_count +ffffffff81eb5150 t mmhub_v1_7_query_ras_error_status +ffffffff81eb5230 t mmhub_v1_7_reset_ras_error_count +ffffffff81eb52d0 t mmhub_v1_7_reset_ras_error_status +ffffffff81eb53d0 t mmhub_v1_7_get_fb_location +ffffffff81eb54f0 t mmhub_v1_7_init +ffffffff81eb5590 t mmhub_v1_7_gart_enable +ffffffff81eb6aa0 t mmhub_v1_7_set_fault_enable_default +ffffffff81eb6bc0 t mmhub_v1_7_gart_disable +ffffffff81eb6e60 t mmhub_v1_7_set_clockgating +ffffffff81eb7200 t mmhub_v1_7_get_clockgating +ffffffff81eb7320 t mmhub_v1_7_setup_vm_pt_regs +ffffffff81eb8000 t mmhub_v1_8_get_fb_location +ffffffff81eb8120 t mmhub_v1_8_init +ffffffff81eb8280 t mmhub_v1_8_gart_enable +ffffffff81eb9e90 t mmhub_v1_8_set_fault_enable_default +ffffffff81eba060 t mmhub_v1_8_gart_disable +ffffffff81eba3a0 t mmhub_v1_8_set_clockgating +ffffffff81eba3d0 t mmhub_v1_8_get_clockgating +ffffffff81eba400 t mmhub_v1_8_setup_vm_pt_regs +ffffffff81eba610 t mmhub_v1_8_query_ras_error_count +ffffffff81eba770 t mmhub_v1_8_query_ras_error_status +ffffffff81ebaa20 t mmhub_v1_8_reset_ras_error_count +ffffffff81ebab30 t mmhub_v1_8_reset_ras_error_status +ffffffff81ebc000 t mmhub_v2_0_init +ffffffff81ebc0d0 t mmhub_v2_0_gart_enable +ffffffff81ebd290 t mmhub_v2_0_set_fault_enable_default +ffffffff81ebd3b0 t mmhub_v2_0_gart_disable +ffffffff81ebd640 t mmhub_v2_0_set_clockgating +ffffffff81ebd990 t mmhub_v2_0_get_clockgating +ffffffff81ebdb20 t mmhub_v2_0_setup_vm_pt_regs +ffffffff81ebdc60 t mmhub_v2_0_print_l2_protection_fault_status +ffffffff81ebdeb0 t mmhub_v2_0_get_invalidate_req +ffffffff81ebe000 t mmhub_v2_3_init +ffffffff81ebe0e0 t mmhub_v2_3_gart_enable +ffffffff81ebf4b0 t mmhub_v2_3_set_fault_enable_default +ffffffff81ebf5b0 t mmhub_v2_3_gart_disable +ffffffff81ebf850 t mmhub_v2_3_set_clockgating +ffffffff81ebfcf0 t mmhub_v2_3_get_clockgating +ffffffff81ebfee0 t mmhub_v2_3_setup_vm_pt_regs +ffffffff81ec0020 t mmhub_v2_3_print_l2_protection_fault_status +ffffffff81ec0230 t mmhub_v2_3_get_invalidate_req +ffffffff81ec1000 t mmhub_v3_0_get_fb_location +ffffffff81ec1090 t mmhub_v3_0_get_mc_fb_offset +ffffffff81ec1120 t mmhub_v3_0_init +ffffffff81ec1200 t mmhub_v3_0_gart_enable +ffffffff81ec2420 t mmhub_v3_0_set_fault_enable_default +ffffffff81ec2540 t mmhub_v3_0_gart_disable +ffffffff81ec27d0 t mmhub_v3_0_set_clockgating +ffffffff81ec29a0 t mmhub_v3_0_get_clockgating +ffffffff81ec2a50 t mmhub_v3_0_setup_vm_pt_regs +ffffffff81ec2b90 t mmhub_v3_0_print_l2_protection_fault_status +ffffffff81ec2d90 t mmhub_v3_0_get_invalidate_req +ffffffff81ec3000 t mmhub_v3_0_1_get_fb_location +ffffffff81ec3090 t mmhub_v3_0_1_get_mc_fb_offset +ffffffff81ec3120 t mmhub_v3_0_1_init +ffffffff81ec31f0 t mmhub_v3_0_1_gart_enable +ffffffff81ec44f0 t mmhub_v3_0_1_set_fault_enable_default +ffffffff81ec45f0 t mmhub_v3_0_1_gart_disable +ffffffff81ec4890 t mmhub_v3_0_1_set_clockgating +ffffffff81ec4a50 t mmhub_v3_0_1_get_clockgating +ffffffff81ec4b00 t mmhub_v3_0_1_setup_vm_pt_regs +ffffffff81ec4c40 t mmhub_v3_0_1_print_l2_protection_fault_status +ffffffff81ec4e40 t mmhub_v3_0_1_get_invalidate_req +ffffffff81ec5000 t mmhub_v3_0_2_get_fb_location +ffffffff81ec5090 t mmhub_v3_0_2_get_mc_fb_offset +ffffffff81ec5120 t mmhub_v3_0_2_init +ffffffff81ec51f0 t mmhub_v3_0_2_gart_enable +ffffffff81ec63e0 t mmhub_v3_0_2_set_fault_enable_default +ffffffff81ec6500 t mmhub_v3_0_2_gart_disable +ffffffff81ec6790 t mmhub_v3_0_2_set_clockgating +ffffffff81ec67c0 t mmhub_v3_0_2_get_clockgating +ffffffff81ec67f0 t mmhub_v3_0_2_setup_vm_pt_regs +ffffffff81ec6930 t mmhub_v3_0_2_print_l2_protection_fault_status +ffffffff81ec6b10 t mmhub_v3_0_2_get_invalidate_req +ffffffff81ec7000 t mmhub_v9_4_query_ras_error_count +ffffffff81ec7150 t mmhub_v9_4_query_ras_error_status +ffffffff81ec7230 t mmhub_v9_4_reset_ras_error_count +ffffffff81ec7300 t mmhub_v9_4_get_fb_location +ffffffff81ec7420 t mmhub_v9_4_init +ffffffff81ec7570 t mmhub_v9_4_gart_enable +ffffffff81ec8a00 t mmhub_v9_4_set_fault_enable_default +ffffffff81ec8bf0 t mmhub_v9_4_gart_disable +ffffffff81ec8f60 t mmhub_v9_4_set_clockgating +ffffffff81ec9440 t mmhub_v9_4_get_clockgating +ffffffff81ec9570 t mmhub_v9_4_setup_vm_pt_regs +ffffffff81ec95c0 t mmhub_v9_4_setup_hubid_vm_pt_regs +ffffffff81eca000 T xgpu_ai_mailbox_set_irq_funcs +ffffffff81eca050 T xgpu_ai_mailbox_add_irq_id +ffffffff81eca0e0 T xgpu_ai_mailbox_get_irq +ffffffff81eca190 t xgpu_ai_mailbox_flr_work +ffffffff81eca390 T xgpu_ai_mailbox_put_irq +ffffffff81eca3d0 t xgpu_ai_request_full_gpu_access +ffffffff81eca3f0 t xgpu_ai_release_full_gpu_access +ffffffff81eca410 t xgpu_ai_request_init_data +ffffffff81eca470 t xgpu_ai_request_reset +ffffffff81eca520 t xgpu_ai_mailbox_trans_msg +ffffffff81eca740 t xgpu_ai_ras_poison_handler +ffffffff81eca770 t xgpu_ai_set_mailbox_ack_irq +ffffffff81eca800 t xgpu_ai_mailbox_ack_irq +ffffffff81eca850 t xgpu_ai_set_mailbox_rcv_irq +ffffffff81eca8e0 t xgpu_ai_mailbox_rcv_irq +ffffffff81eca9c0 t xgpu_ai_send_access_requests +ffffffff81ecaab0 t xgpu_ai_poll_msg +ffffffff81ecb000 T xgpu_nv_mailbox_set_irq_funcs +ffffffff81ecb050 T xgpu_nv_mailbox_add_irq_id +ffffffff81ecb0e0 T xgpu_nv_mailbox_get_irq +ffffffff81ecb190 t xgpu_nv_mailbox_flr_work +ffffffff81ecb3b0 T xgpu_nv_mailbox_put_irq +ffffffff81ecb3f0 t xgpu_nv_request_full_gpu_access +ffffffff81ecb410 t xgpu_nv_release_full_gpu_access +ffffffff81ecb430 t xgpu_nv_request_init_data +ffffffff81ecb450 t xgpu_nv_request_reset +ffffffff81ecb550 t xgpu_nv_mailbox_trans_msg +ffffffff81ecb6f0 t xgpu_nv_ras_poison_handler +ffffffff81ecb710 t xgpu_nv_set_mailbox_ack_irq +ffffffff81ecb790 t xgpu_nv_mailbox_ack_irq +ffffffff81ecb7e0 t xgpu_nv_set_mailbox_rcv_irq +ffffffff81ecb860 t xgpu_nv_mailbox_rcv_irq +ffffffff81ecb910 t xgpu_nv_send_access_requests +ffffffff81ecc000 T xgpu_vi_init_golden_registers +ffffffff81ecc0c0 T xgpu_vi_mailbox_set_irq_funcs +ffffffff81ecc110 T xgpu_vi_mailbox_add_irq_id +ffffffff81ecc1a0 T xgpu_vi_mailbox_get_irq +ffffffff81ecc250 t xgpu_vi_mailbox_flr_work +ffffffff81ecc3a0 T xgpu_vi_mailbox_put_irq +ffffffff81ecc3e0 t xgpu_vi_request_full_gpu_access +ffffffff81ecc400 t xgpu_vi_release_full_gpu_access +ffffffff81ecc420 t xgpu_vi_request_reset +ffffffff81ecc440 t xgpu_vi_wait_reset_cmpl +ffffffff81ecc520 t xgpu_vi_set_mailbox_ack_irq +ffffffff81ecc5a0 t xgpu_vi_mailbox_ack_irq +ffffffff81ecc5f0 t xgpu_vi_set_mailbox_rcv_irq +ffffffff81ecc670 t xgpu_vi_mailbox_rcv_irq +ffffffff81ecc720 t xgpu_vi_mailbox_rcv_msg +ffffffff81ecc840 t xgpu_vi_send_access_requests +ffffffff81ecd000 t navi10_ih_early_init +ffffffff81ecd060 t navi10_ih_sw_init +ffffffff81ecd1d0 t navi10_ih_sw_fini +ffffffff81ecd210 t navi10_ih_hw_init +ffffffff81ecd630 t navi10_ih_hw_fini +ffffffff81ecd690 t navi10_ih_suspend +ffffffff81ecd6f0 t navi10_ih_resume +ffffffff81ecd700 t navi10_ih_is_idle +ffffffff81ecd730 t navi10_ih_wait_for_idle +ffffffff81ecd760 t navi10_ih_soft_reset +ffffffff81ecd790 t navi10_ih_set_clockgating_state +ffffffff81ecd8c0 t navi10_ih_set_powergating_state +ffffffff81ecd8f0 t navi10_ih_get_clockgating_state +ffffffff81ecd980 t navi10_ih_get_wptr +ffffffff81ecda90 t navi10_ih_set_rptr +ffffffff81ecdb60 t navi10_ih_self_irq +ffffffff81ecdbe0 t navi10_ih_toggle_interrupts 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nbio_v2_3_enable_aspm +ffffffff81ecfc80 t nbio_v2_3_program_aspm +ffffffff81ed0330 t nbio_v2_3_apply_lc_spc_mode_wa +ffffffff81ed03c0 t nbio_v2_3_apply_l1_link_width_reconfig_wa +ffffffff81ed0430 t nbio_v2_3_clear_doorbell_interrupt +ffffffff81ed1000 t nbio_v4_3_get_hdp_flush_req_offset +ffffffff81ed1040 t nbio_v4_3_get_hdp_flush_done_offset +ffffffff81ed1080 t nbio_v4_3_get_pcie_index_offset +ffffffff81ed10b0 t nbio_v4_3_get_pcie_data_offset +ffffffff81ed10f0 t nbio_v4_3_get_rev_id +ffffffff81ed1180 t nbio_v4_3_mc_access_enable +ffffffff81ed1230 t nbio_v4_3_get_memsize +ffffffff81ed12a0 t nbio_v4_3_sdma_doorbell_range +ffffffff81ed1410 t nbio_v4_3_vcn_doorbell_range +ffffffff81ed15c0 t nbio_v4_3_gc_doorbell_init +ffffffff81ed16b0 t nbio_v4_3_enable_doorbell_aperture +ffffffff81ed17b0 t nbio_v4_3_enable_doorbell_selfring_aperture +ffffffff81ed1920 t nbio_v4_3_ih_doorbell_range +ffffffff81ed1a40 t nbio_v4_3_update_medium_grain_clock_gating +ffffffff81ed1b80 t nbio_v4_3_update_medium_grain_light_sleep +ffffffff81ed1cb0 t nbio_v4_3_get_clockgating_state +ffffffff81ed1dc0 t nbio_v4_3_ih_control +ffffffff81ed1f10 t nbio_v4_3_init_registers +ffffffff81ed2040 t nbio_v4_3_remap_hdp_registers +ffffffff81ed2150 t nbio_v4_3_program_aspm +ffffffff81ed2e50 t nbio_v4_3_get_rom_offset +ffffffff81ed2ee0 t nbio_v4_3_sriov_sdma_doorbell_range +ffffffff81ed2f10 t nbio_v4_3_sriov_vcn_doorbell_range +ffffffff81ed2f40 t nbio_v4_3_sriov_gc_doorbell_init +ffffffff81ed2f70 t nbio_v4_3_sriov_ih_doorbell_range +ffffffff81ed2fa0 t nbio_v4_3_handle_ras_err_event_athub_intr_no_bifring +ffffffff81ed30b0 t nbio_v4_3_init_ras_err_event_athub_interrupt +ffffffff81ed30f0 t nbio_v4_3_set_ras_err_event_athub_irq_state +ffffffff81ed3200 t nbio_v4_3_process_err_event_athub_irq +ffffffff81ed4000 t nbio_v6_1_get_hdp_flush_req_offset +ffffffff81ed4040 t nbio_v6_1_get_hdp_flush_done_offset +ffffffff81ed4080 t nbio_v6_1_get_pcie_index_offset +ffffffff81ed40c0 t nbio_v6_1_get_pcie_data_offset +ffffffff81ed4100 t nbio_v6_1_get_rev_id +ffffffff81ed4190 t nbio_v6_1_mc_access_enable +ffffffff81ed4240 t nbio_v6_1_get_memsize +ffffffff81ed42b0 t nbio_v6_1_sdma_doorbell_range +ffffffff81ed4340 t nbio_v6_1_enable_doorbell_aperture +ffffffff81ed4440 t nbio_v6_1_enable_doorbell_selfring_aperture +ffffffff81ed45b0 t nbio_v6_1_ih_doorbell_range +ffffffff81ed46d0 t nbio_v6_1_update_medium_grain_clock_gating +ffffffff81ed4770 t nbio_v6_1_update_medium_grain_light_sleep +ffffffff81ed4810 t nbio_v6_1_get_clockgating_state +ffffffff81ed4890 t nbio_v6_1_ih_control +ffffffff81ed49e0 t nbio_v6_1_init_registers +ffffffff81ed4ab0 t nbio_v6_1_remap_hdp_registers +ffffffff81ed4bc0 t nbio_v6_1_program_aspm +ffffffff81ed5000 t nbio_v7_0_get_hdp_flush_req_offset +ffffffff81ed5040 t nbio_v7_0_get_hdp_flush_done_offset +ffffffff81ed5080 t nbio_v7_0_get_pcie_index_offset +ffffffff81ed50c0 t nbio_v7_0_get_pcie_data_offset +ffffffff81ed5100 t nbio_v7_0_get_rev_id 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nbio_v7_2_get_pcie_port_index_offset +ffffffff81ed6130 t nbio_v7_2_get_pcie_port_data_offset +ffffffff81ed6170 t nbio_v7_2_get_rev_id +ffffffff81ed6250 t nbio_v7_2_mc_access_enable +ffffffff81ed6390 t nbio_v7_2_get_memsize +ffffffff81ed6400 t nbio_v7_2_sdma_doorbell_range +ffffffff81ed64a0 t nbio_v7_2_vcn_doorbell_range +ffffffff81ed6520 t nbio_v7_2_enable_doorbell_aperture +ffffffff81ed6600 t nbio_v7_2_enable_doorbell_selfring_aperture +ffffffff81ed6770 t nbio_v7_2_ih_doorbell_range +ffffffff81ed6800 t nbio_v7_2_update_medium_grain_clock_gating +ffffffff81ed68c0 t nbio_v7_2_update_medium_grain_light_sleep +ffffffff81ed6a50 t nbio_v7_2_get_clockgating_state +ffffffff81ed6ae0 t nbio_v7_2_ih_control +ffffffff81ed6c30 t nbio_v7_2_init_registers +ffffffff81ed6df0 t nbio_v7_2_remap_hdp_registers +ffffffff81ed7000 t nbio_v7_4_query_ras_error_count +ffffffff81ed71a0 t nbio_v7_4_handle_ras_controller_intr_no_bifring +ffffffff81ed73e0 t nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring 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nbio_v7_4_ih_control +ffffffff81ed81f0 t nbio_v7_4_init_registers +ffffffff81ed82e0 t nbio_v7_4_remap_hdp_registers +ffffffff81ed83f0 t nbio_v7_4_program_aspm +ffffffff81ed8800 t nbio_v7_4_set_ras_controller_irq_state +ffffffff81ed8990 t nbio_v7_4_process_ras_controller_irq +ffffffff81ed89c0 t nbio_v7_4_set_ras_err_event_athub_irq_state +ffffffff81ed8b50 t nbio_v7_4_process_err_event_athub_irq +ffffffff81ed9000 t nbio_v7_7_get_hdp_flush_req_offset +ffffffff81ed9040 t nbio_v7_7_get_hdp_flush_done_offset +ffffffff81ed9080 t nbio_v7_7_get_pcie_index_offset +ffffffff81ed90c0 t nbio_v7_7_get_pcie_data_offset +ffffffff81ed9100 t nbio_v7_7_get_pcie_port_index_offset +ffffffff81ed9130 t nbio_v7_7_get_pcie_port_data_offset +ffffffff81ed9170 t nbio_v7_7_get_rev_id +ffffffff81ed9200 t nbio_v7_7_mc_access_enable +ffffffff81ed92b0 t nbio_v7_7_get_memsize +ffffffff81ed9320 t nbio_v7_7_sdma_doorbell_range +ffffffff81ed93b0 t nbio_v7_7_vcn_doorbell_range +ffffffff81ed9430 t nbio_v7_7_enable_doorbell_aperture +ffffffff81ed9510 t nbio_v7_7_enable_doorbell_selfring_aperture +ffffffff81ed9680 t nbio_v7_7_ih_doorbell_range +ffffffff81ed97a0 t nbio_v7_7_update_medium_grain_clock_gating +ffffffff81ed98e0 t nbio_v7_7_update_medium_grain_light_sleep +ffffffff81ed9af0 t nbio_v7_7_get_clockgating_state +ffffffff81ed9c00 t nbio_v7_7_ih_control +ffffffff81ed9d50 t nbio_v7_7_init_registers +ffffffff81ed9e70 t nbio_v7_7_remap_hdp_registers +ffffffff81eda000 t nbio_v7_9_get_hdp_flush_req_offset +ffffffff81eda040 t nbio_v7_9_get_hdp_flush_done_offset +ffffffff81eda080 t nbio_v7_9_get_pcie_index_offset +ffffffff81eda0c0 t nbio_v7_9_get_pcie_data_offset +ffffffff81eda100 t nbio_v7_9_get_pcie_index_hi_offset +ffffffff81eda140 t nbio_v7_9_get_rev_id +ffffffff81eda1d0 t nbio_v7_9_mc_access_enable +ffffffff81eda280 t nbio_v7_9_get_memsize +ffffffff81eda2f0 t nbio_v7_9_sdma_doorbell_range +ffffffff81eda630 t nbio_v7_9_vcn_doorbell_range +ffffffff81eda7c0 t nbio_v7_9_enable_doorbell_aperture +ffffffff81eda930 t nbio_v7_9_enable_doorbell_selfring_aperture +ffffffff81edaaa0 t nbio_v7_9_ih_doorbell_range +ffffffff81edaba0 t nbio_v7_9_enable_doorbell_interrupt +ffffffff81edacb0 t nbio_v7_9_update_medium_grain_clock_gating +ffffffff81edace0 t nbio_v7_9_update_medium_grain_light_sleep +ffffffff81edad10 t nbio_v7_9_get_clockgating_state +ffffffff81edad40 t nbio_v7_9_ih_control +ffffffff81edae90 t nbio_v7_9_init_registers +ffffffff81edb1a0 t nbio_v7_9_remap_hdp_registers +ffffffff81edb2b0 t nbio_v7_9_get_compute_partition_mode +ffffffff81edb340 t nbio_v7_9_get_memory_partition_mode +ffffffff81edb430 t nbio_v7_9_get_pcie_replay_count +ffffffff81edb490 t nbio_v7_9_get_pcie_usage +ffffffff81edb5f0 t nbio_v7_9_query_ras_error_count +ffffffff81edb620 t nbio_v7_9_handle_ras_controller_intr_no_bifring +ffffffff81edb740 t nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring +ffffffff81edb850 t nbio_v7_9_init_ras_controller_interrupt +ffffffff81edb890 t nbio_v7_9_init_ras_err_event_athub_interrupt +ffffffff81edb8d0 t nbio_v7_9_set_ras_controller_irq_state +ffffffff81edb900 t nbio_v7_9_process_ras_controller_irq +ffffffff81edb930 t nbio_v7_9_set_ras_err_event_athub_irq_state +ffffffff81edb960 t nbio_v7_9_process_err_event_athub_irq +ffffffff81edc000 T nv_grbm_select +ffffffff81edc0a0 T nv_set_virt_ops +ffffffff81edc0e0 t nv_common_early_init +ffffffff81edc4d0 t nv_common_late_init +ffffffff81edc580 t nv_common_sw_init +ffffffff81edc5c0 t nv_common_sw_fini +ffffffff81edc5f0 t nv_common_hw_init +ffffffff81edc6f0 t nv_common_hw_fini +ffffffff81edc750 t nv_common_suspend +ffffffff81edc7b0 t nv_common_resume +ffffffff81edc7f0 t nv_common_is_idle +ffffffff81edc820 t nv_common_wait_for_idle +ffffffff81edc850 t nv_common_soft_reset +ffffffff81edc880 t nv_common_set_clockgating_state +ffffffff81edc950 t nv_common_set_powergating_state +ffffffff81edc980 t nv_common_get_clockgating_state +ffffffff81edc9f0 t nv_didt_rreg +ffffffff81edca90 t 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psp_v11_0_8_ring_set_wptr +ffffffff81ee2000 T psp_v12_0_set_psp_funcs +ffffffff81ee2030 t psp_v12_0_init_microcode +ffffffff81ee20e0 t psp_v12_0_bootloader_load_sysdrv +ffffffff81ee2410 t psp_v12_0_bootloader_load_sos +ffffffff81ee2790 t psp_v12_0_ring_create +ffffffff81ee3190 t psp_v12_0_ring_stop +ffffffff81ee33b0 t psp_v12_0_ring_destroy +ffffffff81ee3430 t psp_v12_0_mode1_reset +ffffffff81ee3530 t psp_v12_0_ring_get_wptr +ffffffff81ee35a0 t psp_v12_0_ring_set_wptr +ffffffff81ee4000 T psp_v13_0_set_psp_funcs +ffffffff81ee4030 t psp_v13_0_init_microcode +ffffffff81ee4130 t psp_v13_0_wait_for_bootloader_steady_state +ffffffff81ee4240 t psp_v13_0_bootloader_load_kdb +ffffffff81ee4260 t psp_v13_0_bootloader_load_spl +ffffffff81ee4280 t psp_v13_0_bootloader_load_sysdrv +ffffffff81ee42a0 t psp_v13_0_bootloader_load_soc_drv +ffffffff81ee42c0 t psp_v13_0_bootloader_load_intf_drv +ffffffff81ee42e0 t psp_v13_0_bootloader_load_dbg_drv +ffffffff81ee4300 t psp_v13_0_bootloader_load_ras_drv +ffffffff81ee4320 t psp_v13_0_bootloader_load_sos +ffffffff81ee46f0 t psp_v13_0_ring_create +ffffffff81ee4d90 t psp_v13_0_ring_stop +ffffffff81ee5120 t psp_v13_0_ring_destroy +ffffffff81ee51a0 t psp_v13_0_memory_training +ffffffff81ee55d0 t psp_v13_0_ring_get_wptr +ffffffff81ee5640 t psp_v13_0_ring_set_wptr +ffffffff81ee5740 t psp_v13_0_load_usbc_pd_fw +ffffffff81ee5930 t psp_v13_0_read_usbc_pd_fw +ffffffff81ee5a50 t psp_v13_0_update_spirom +ffffffff81ee5c30 t psp_v13_0_vbflash_status +ffffffff81ee5c90 t psp_v13_0_fatal_error_recovery_quirk +ffffffff81ee5dc0 t psp_v13_0_bootloader_load_component +ffffffff81ee6030 t psp_v13_0_memory_training_send_msg +ffffffff81ee61a0 t psp_v13_0_exec_spi_cmd +ffffffff81ee7000 T psp_v13_0_4_set_psp_funcs +ffffffff81ee7030 t psp_v13_0_4_init_microcode +ffffffff81ee70d0 t psp_v13_0_4_bootloader_load_kdb +ffffffff81ee70f0 t psp_v13_0_4_bootloader_load_spl +ffffffff81ee7110 t psp_v13_0_4_bootloader_load_sysdrv +ffffffff81ee7130 t psp_v13_0_4_bootloader_load_soc_drv +ffffffff81ee7150 t psp_v13_0_4_bootloader_load_intf_drv +ffffffff81ee7170 t psp_v13_0_4_bootloader_load_dbg_drv +ffffffff81ee7190 t psp_v13_0_4_bootloader_load_sos +ffffffff81ee7500 t psp_v13_0_4_ring_create +ffffffff81ee7bb0 t psp_v13_0_4_ring_stop +ffffffff81ee7f40 t psp_v13_0_4_ring_destroy +ffffffff81ee7fc0 t psp_v13_0_4_ring_get_wptr +ffffffff81ee8030 t psp_v13_0_4_ring_set_wptr +ffffffff81ee8130 t psp_v13_0_4_bootloader_load_component +ffffffff81ee8300 t psp_v13_0_4_wait_for_bootloader +ffffffff81ee9000 T psp_v3_1_set_psp_funcs +ffffffff81ee9030 t psp_v3_1_init_microcode +ffffffff81ee90c0 t psp_v3_1_bootloader_load_sysdrv +ffffffff81ee93f0 t psp_v3_1_bootloader_load_sos +ffffffff81ee9770 t psp_v3_1_ring_create +ffffffff81eea290 t psp_v3_1_ring_stop +ffffffff81eea4b0 t psp_v3_1_ring_destroy +ffffffff81eea530 t psp_v3_1_smu_reload_quirk +ffffffff81eea580 t psp_v3_1_mode1_reset +ffffffff81eea680 t psp_v3_1_ring_get_wptr +ffffffff81eea6d0 t psp_v3_1_ring_set_wptr +ffffffff81eeb000 t sdma_v2_4_early_init +ffffffff81eeb0f0 t sdma_v2_4_sw_init +ffffffff81eeb4a0 t sdma_v2_4_sw_fini +ffffffff81eeb550 t sdma_v2_4_hw_init +ffffffff81eeb8f0 t sdma_v2_4_hw_fini +ffffffff81eeb930 t sdma_v2_4_suspend +ffffffff81eeb970 t sdma_v2_4_resume +ffffffff81eeb980 t sdma_v2_4_is_idle +ffffffff81eeb9c0 t sdma_v2_4_wait_for_idle +ffffffff81eeba60 t sdma_v2_4_soft_reset +ffffffff81eebba0 t sdma_v2_4_set_clockgating_state +ffffffff81eebbd0 t sdma_v2_4_set_powergating_state +ffffffff81eebc00 t sdma_v2_4_ring_get_rptr +ffffffff81eebc40 t sdma_v2_4_ring_get_wptr +ffffffff81eebca0 t sdma_v2_4_ring_set_wptr +ffffffff81eebce0 t sdma_v2_4_ring_emit_ib +ffffffff81eebf90 t sdma_v2_4_ring_emit_fence +ffffffff81eec390 t sdma_v2_4_ring_emit_pipeline_sync +ffffffff81eec610 t sdma_v2_4_ring_emit_vm_flush +ffffffff81eec880 t sdma_v2_4_ring_emit_hdp_flush +ffffffff81eecb00 t sdma_v2_4_ring_test_ring +ffffffff81eecde0 t sdma_v2_4_ring_test_ib +ffffffff81eecfb0 t sdma_v2_4_ring_insert_nop +ffffffff81eed0e0 t sdma_v2_4_ring_pad_ib +ffffffff81eed210 t sdma_v2_4_ring_emit_wreg +ffffffff81eed360 t sdma_v2_4_emit_copy_buffer +ffffffff81eed420 t sdma_v2_4_emit_fill_buffer +ffffffff81eed4b0 t sdma_v2_4_vm_copy_pte +ffffffff81eed570 t sdma_v2_4_vm_write_pte +ffffffff81eed640 t sdma_v2_4_vm_set_pte_pde +ffffffff81eed740 t sdma_v2_4_set_trap_irq_state +ffffffff81eed800 t sdma_v2_4_process_trap_irq +ffffffff81eed8a0 t sdma_v2_4_process_illegal_inst_irq +ffffffff81eed920 t sdma_v2_4_enable +ffffffff81eee000 t sdma_v3_0_early_init +ffffffff81eee100 t sdma_v3_0_sw_init +ffffffff81eee4c0 t sdma_v3_0_sw_fini +ffffffff81eee570 t sdma_v3_0_hw_init +ffffffff81eee6a0 t sdma_v3_0_hw_fini +ffffffff81eee6f0 t sdma_v3_0_suspend +ffffffff81eee740 t sdma_v3_0_resume +ffffffff81eee750 t sdma_v3_0_is_idle +ffffffff81eee790 t sdma_v3_0_wait_for_idle +ffffffff81eee830 t sdma_v3_0_check_soft_reset +ffffffff81eee890 t sdma_v3_0_pre_soft_reset +ffffffff81eee8e0 t sdma_v3_0_soft_reset +ffffffff81eee9b0 t sdma_v3_0_post_soft_reset +ffffffff81eeea00 t sdma_v3_0_set_clockgating_state +ffffffff81eeec60 t sdma_v3_0_set_powergating_state +ffffffff81eeec90 t sdma_v3_0_get_clockgating_state +ffffffff81eeed10 t sdma_v3_0_ring_get_rptr +ffffffff81eeed50 t sdma_v3_0_ring_get_wptr +ffffffff81eeedd0 t sdma_v3_0_ring_set_wptr +ffffffff81eeee80 t sdma_v3_0_ring_emit_ib +ffffffff81eef130 t sdma_v3_0_ring_emit_fence +ffffffff81eef530 t sdma_v3_0_ring_emit_pipeline_sync +ffffffff81eef7b0 t sdma_v3_0_ring_emit_vm_flush +ffffffff81eefa20 t sdma_v3_0_ring_emit_hdp_flush +ffffffff81eefca0 t sdma_v3_0_ring_test_ring +ffffffff81eeff80 t sdma_v3_0_ring_test_ib +ffffffff81ef0150 t sdma_v3_0_ring_insert_nop +ffffffff81ef0280 t sdma_v3_0_ring_pad_ib +ffffffff81ef03b0 t sdma_v3_0_ring_emit_wreg +ffffffff81ef0500 t sdma_v3_0_emit_copy_buffer +ffffffff81ef05c0 t sdma_v3_0_emit_fill_buffer +ffffffff81ef0650 t sdma_v3_0_vm_copy_pte +ffffffff81ef0710 t sdma_v3_0_vm_write_pte +ffffffff81ef07e0 t sdma_v3_0_vm_set_pte_pde +ffffffff81ef08e0 t sdma_v3_0_set_trap_irq_state +ffffffff81ef09a0 t sdma_v3_0_process_trap_irq +ffffffff81ef0a40 t sdma_v3_0_process_illegal_inst_irq +ffffffff81ef0ac0 t sdma_v3_0_ctx_switch_enable +ffffffff81ef0c60 t sdma_v3_0_enable +ffffffff81ef0dd0 t sdma_v3_0_gfx_resume +ffffffff81ef2000 t sdma_v4_0_early_init +ffffffff81ef22d0 t sdma_v4_0_late_init +ffffffff81ef2570 t sdma_v4_0_sw_init +ffffffff81ef29b0 t sdma_v4_0_sw_fini +ffffffff81ef2a70 t sdma_v4_0_hw_init +ffffffff81ef59d0 t sdma_v4_0_hw_fini +ffffffff81ef5a90 t sdma_v4_0_suspend +ffffffff81ef5ae0 t sdma_v4_0_resume +ffffffff81ef5b60 t sdma_v4_0_is_idle +ffffffff81ef5c90 t sdma_v4_0_wait_for_idle +ffffffff81ef5e30 t sdma_v4_0_soft_reset +ffffffff81ef5e60 t sdma_v4_0_set_clockgating_state +ffffffff81ef6360 t sdma_v4_0_set_powergating_state +ffffffff81ef6420 t sdma_v4_0_get_clockgating_state +ffffffff81ef64c0 t sdma_v4_0_query_ras_error_count +ffffffff81ef6690 t sdma_v4_0_reset_ras_error_count +ffffffff81ef67e0 t sdma_v4_0_ring_get_rptr +ffffffff81ef6840 t sdma_v4_0_ring_get_wptr +ffffffff81ef6a30 t sdma_v4_0_ring_set_wptr +ffffffff81ef6cb0 t sdma_v4_0_ring_emit_ib +ffffffff81ef6f60 t sdma_v4_0_ring_emit_fence +ffffffff81ef7380 t sdma_v4_0_ring_emit_pipeline_sync +ffffffff81ef73e0 t sdma_v4_0_ring_emit_vm_flush +ffffffff81ef7400 t sdma_v4_0_ring_emit_hdp_flush +ffffffff81ef74b0 t sdma_v4_0_ring_test_ring +ffffffff81ef7790 t sdma_v4_0_ring_test_ib +ffffffff81ef7960 t sdma_v4_0_ring_insert_nop +ffffffff81ef7a90 t sdma_v4_0_ring_pad_ib +ffffffff81ef7bc0 t sdma_v4_0_ring_emit_wreg +ffffffff81ef7d10 t sdma_v4_0_ring_emit_reg_wait +ffffffff81ef7d60 t sdma_v4_0_wait_reg_mem +ffffffff81ef8070 t sdma_v4_0_page_ring_get_wptr +ffffffff81ef8220 t sdma_v4_0_page_ring_set_wptr +ffffffff81ef83e0 t sdma_v4_0_emit_copy_buffer +ffffffff81ef84a0 t sdma_v4_0_emit_fill_buffer +ffffffff81ef8530 t sdma_v4_0_vm_copy_pte +ffffffff81ef85f0 t sdma_v4_0_vm_write_pte +ffffffff81ef86c0 t sdma_v4_0_vm_set_pte_pde +ffffffff81ef87c0 t sdma_v4_0_set_trap_irq_state +ffffffff81ef8960 t sdma_v4_0_process_trap_irq +ffffffff81ef8a90 t sdma_v4_0_process_illegal_inst_irq +ffffffff81ef8bb0 t sdma_v4_0_set_ecc_irq_state +ffffffff81ef8d50 t sdma_v4_0_process_vm_hole_irq +ffffffff81ef8d90 t sdma_v4_0_print_iv_entry +ffffffff81ef8ed0 t sdma_v4_0_process_doorbell_invalid_irq +ffffffff81ef8f10 t sdma_v4_0_process_pool_timeout_irq +ffffffff81ef8f50 t sdma_v4_0_process_srbm_write_irq +ffffffff81ef8f90 t sdma_v4_0_process_ras_data_cb +ffffffff81ef9010 t sdma_v4_0_ctx_switch_enable +ffffffff81ef96e0 t sdma_v4_0_enable +ffffffff81ef9ca0 t sdma_v4_0_gfx_enable +ffffffff81efb000 t sdma_v4_4_query_ras_error_count +ffffffff81efb290 t sdma_v4_4_reset_ras_error_count +ffffffff81efc000 t sdma_v4_4_2_early_init +ffffffff81efc280 t sdma_v4_4_2_late_init +ffffffff81efc2f0 t sdma_v4_4_2_sw_init +ffffffff81efc810 t sdma_v4_4_2_sw_fini +ffffffff81efc8c0 t sdma_v4_4_2_hw_init +ffffffff81efc910 t sdma_v4_4_2_hw_fini +ffffffff81efc9d0 t sdma_v4_4_2_suspend +ffffffff81efcab0 t sdma_v4_4_2_resume +ffffffff81efcb00 t sdma_v4_4_2_is_idle +ffffffff81efcba0 t sdma_v4_4_2_wait_for_idle +ffffffff81efccc0 t sdma_v4_4_2_soft_reset +ffffffff81efccf0 t sdma_v4_4_2_set_clockgating_state +ffffffff81efd0f0 t sdma_v4_4_2_set_powergating_state +ffffffff81efd120 t sdma_v4_4_2_get_clockgating_state +ffffffff81efd200 t sdma_v4_4_2_xcp_suspend +ffffffff81efd2c0 t sdma_v4_4_2_xcp_resume +ffffffff81efd300 t sdma_v4_4_2_ring_get_rptr +ffffffff81efd370 t sdma_v4_4_2_ring_get_wptr +ffffffff81efd4b0 t sdma_v4_4_2_ring_set_wptr +ffffffff81efd670 t sdma_v4_4_2_ring_emit_ib +ffffffff81efd920 t sdma_v4_4_2_ring_emit_fence +ffffffff81efdd40 t sdma_v4_4_2_ring_emit_pipeline_sync +ffffffff81efdda0 t sdma_v4_4_2_ring_emit_vm_flush +ffffffff81efddc0 t sdma_v4_4_2_ring_emit_hdp_flush +ffffffff81efde70 t sdma_v4_4_2_ring_test_ring +ffffffff81efe150 t sdma_v4_4_2_ring_test_ib +ffffffff81efe320 t sdma_v4_4_2_ring_insert_nop +ffffffff81efe450 t sdma_v4_4_2_ring_pad_ib +ffffffff81efe580 t sdma_v4_4_2_ring_emit_wreg +ffffffff81efe6d0 t sdma_v4_4_2_ring_emit_reg_wait +ffffffff81efe720 t sdma_v4_4_2_wait_reg_mem +ffffffff81efea30 t sdma_v4_4_2_page_ring_get_wptr +ffffffff81efeb30 t sdma_v4_4_2_page_ring_set_wptr +ffffffff81efec40 t sdma_v4_4_2_emit_copy_buffer +ffffffff81efed00 t sdma_v4_4_2_emit_fill_buffer +ffffffff81efed90 t sdma_v4_4_2_vm_copy_pte +ffffffff81efee50 t sdma_v4_4_2_vm_write_pte +ffffffff81efef20 t sdma_v4_4_2_vm_set_pte_pde +ffffffff81eff020 t sdma_v4_4_2_set_trap_irq_state +ffffffff81eff100 t sdma_v4_4_2_process_trap_irq +ffffffff81eff220 t sdma_v4_4_2_process_illegal_inst_irq +ffffffff81eff2b0 t sdma_v4_4_2_set_ecc_irq_state +ffffffff81eff390 t sdma_v4_4_2_process_vm_hole_irq +ffffffff81eff470 t sdma_v4_4_2_process_doorbell_invalid_irq +ffffffff81eff550 t sdma_v4_4_2_process_pool_timeout_irq +ffffffff81eff630 t sdma_v4_4_2_process_srbm_write_irq +ffffffff81eff710 t sdma_v4_4_2_query_ras_error_count +ffffffff81eff860 t sdma_v4_4_2_reset_ras_error_count +ffffffff81eff990 t sdma_v4_4_2_inst_init_golden_registers +ffffffff81effb10 t sdma_v4_4_2_inst_start +ffffffff81f00eb0 t sdma_v4_4_2_inst_ctx_switch_enable +ffffffff81f01180 t sdma_v4_4_2_inst_enable +ffffffff81f02000 t sdma_v5_0_early_init +ffffffff81f02130 t sdma_v5_0_sw_init +ffffffff81f02310 t sdma_v5_0_sw_fini +ffffffff81f023a0 t sdma_v5_0_hw_init +ffffffff81f03600 t sdma_v5_0_hw_fini +ffffffff81f03660 t sdma_v5_0_suspend +ffffffff81f036c0 t sdma_v5_0_resume +ffffffff81f036d0 t sdma_v5_0_is_idle +ffffffff81f03760 t sdma_v5_0_wait_for_idle +ffffffff81f03820 t sdma_v5_0_soft_reset +ffffffff81f03850 t sdma_v5_0_set_clockgating_state +ffffffff81f03a50 t sdma_v5_0_set_powergating_state +ffffffff81f03a80 t sdma_v5_0_get_clockgating_state +ffffffff81f03b20 t sdma_v5_0_ring_get_rptr +ffffffff81f03b80 t sdma_v5_0_ring_get_wptr +ffffffff81f03d20 t sdma_v5_0_ring_set_wptr +ffffffff81f04070 t sdma_v5_0_ring_emit_ib +ffffffff81f04330 t sdma_v5_0_ring_emit_fence +ffffffff81f04790 t sdma_v5_0_ring_emit_pipeline_sync +ffffffff81f04a10 t sdma_v5_0_ring_emit_vm_flush +ffffffff81f04a30 t sdma_v5_0_ring_emit_hdp_flush +ffffffff81f04cd0 t sdma_v5_0_ring_test_ring +ffffffff81f05090 t sdma_v5_0_ring_test_ib +ffffffff81f053c0 t sdma_v5_0_ring_insert_nop +ffffffff81f054f0 t sdma_v5_0_ring_pad_ib +ffffffff81f05620 t sdma_v5_0_ring_init_cond_exec +ffffffff81f05850 t sdma_v5_0_ring_patch_cond_exec +ffffffff81f05910 t sdma_v5_0_ring_emit_wreg +ffffffff81f05a60 t sdma_v5_0_ring_emit_reg_wait +ffffffff81f05ce0 t sdma_v5_0_ring_emit_reg_write_reg_wait +ffffffff81f05d60 t sdma_v5_0_ring_preempt_ib +ffffffff81f05ea0 t sdma_v5_0_ring_emit_mem_sync +ffffffff81f060b0 t sdma_v5_0_emit_copy_buffer +ffffffff81f06170 t sdma_v5_0_emit_fill_buffer +ffffffff81f06200 t sdma_v5_0_vm_copy_pte +ffffffff81f062c0 t sdma_v5_0_vm_write_pte +ffffffff81f06390 t sdma_v5_0_vm_set_pte_pde +ffffffff81f06490 t sdma_v5_0_set_trap_irq_state +ffffffff81f06520 t sdma_v5_0_process_trap_irq +ffffffff81f06630 t sdma_v5_0_process_illegal_inst_irq +ffffffff81f06660 t sdma_v5_0_mqd_init +ffffffff81f06740 t sdma_v5_0_ctx_switch_enable +ffffffff81f06a80 t sdma_v5_0_enable +ffffffff81f07000 t sdma_v5_2_early_init +ffffffff81f07130 t sdma_v5_2_sw_init +ffffffff81f07390 t sdma_v5_2_sw_fini +ffffffff81f07420 t sdma_v5_2_hw_init +ffffffff81f08fc0 t sdma_v5_2_hw_fini +ffffffff81f09020 t sdma_v5_2_suspend +ffffffff81f09080 t sdma_v5_2_resume +ffffffff81f09090 t sdma_v5_2_is_idle +ffffffff81f09140 t sdma_v5_2_wait_for_idle +ffffffff81f09240 t sdma_v5_2_soft_reset +ffffffff81f09500 t sdma_v5_2_set_clockgating_state +ffffffff81f09860 t sdma_v5_2_set_powergating_state +ffffffff81f09890 t sdma_v5_2_get_clockgating_state +ffffffff81f09920 t sdma_v5_2_ring_get_rptr +ffffffff81f09980 t sdma_v5_2_ring_get_wptr +ffffffff81f09ac0 t sdma_v5_2_ring_set_wptr +ffffffff81f09c70 t sdma_v5_2_ring_emit_ib +ffffffff81f09f30 t sdma_v5_2_ring_emit_fence +ffffffff81f0a390 t sdma_v5_2_ring_emit_pipeline_sync +ffffffff81f0a610 t sdma_v5_2_ring_emit_vm_flush +ffffffff81f0a630 t sdma_v5_2_ring_emit_hdp_flush +ffffffff81f0a8d0 t sdma_v5_2_ring_test_ring +ffffffff81f0ac90 t sdma_v5_2_ring_test_ib +ffffffff81f0afc0 t sdma_v5_2_ring_insert_nop +ffffffff81f0b0f0 t sdma_v5_2_ring_pad_ib +ffffffff81f0b220 t sdma_v5_2_ring_init_cond_exec +ffffffff81f0b450 t sdma_v5_2_ring_patch_cond_exec +ffffffff81f0b510 t sdma_v5_2_ring_begin_use +ffffffff81f0b530 t sdma_v5_2_ring_end_use +ffffffff81f0b550 t sdma_v5_2_ring_emit_wreg +ffffffff81f0b6a0 t sdma_v5_2_ring_emit_reg_wait +ffffffff81f0b920 t sdma_v5_2_ring_emit_reg_write_reg_wait +ffffffff81f0b9a0 t sdma_v5_2_ring_preempt_ib +ffffffff81f0bb10 t sdma_v5_2_ring_emit_mem_sync +ffffffff81f0bd20 t sdma_v5_2_emit_copy_buffer +ffffffff81f0bde0 t sdma_v5_2_emit_fill_buffer +ffffffff81f0be70 t sdma_v5_2_vm_copy_pte +ffffffff81f0bf30 t sdma_v5_2_vm_write_pte +ffffffff81f0c000 t sdma_v5_2_vm_set_pte_pde +ffffffff81f0c100 t sdma_v5_2_set_trap_irq_state +ffffffff81f0c1c0 t sdma_v5_2_process_trap_irq +ffffffff81f0c300 t sdma_v5_2_process_illegal_inst_irq +ffffffff81f0c330 t sdma_v5_2_mqd_init +ffffffff81f0c410 t sdma_v5_2_ctx_switch_enable +ffffffff81f0c820 t sdma_v5_2_enable +ffffffff81f0d000 t sdma_v6_0_early_init +ffffffff81f0d120 t sdma_v6_0_sw_init +ffffffff81f0d2e0 t sdma_v6_0_sw_fini +ffffffff81f0d370 t sdma_v6_0_hw_init +ffffffff81f0d380 t sdma_v6_0_hw_fini +ffffffff81f0d450 t sdma_v6_0_suspend +ffffffff81f0d490 t sdma_v6_0_resume +ffffffff81f0d4a0 t sdma_v6_0_is_idle +ffffffff81f0d530 t sdma_v6_0_wait_for_idle +ffffffff81f0d5f0 t sdma_v6_0_check_soft_reset +ffffffff81f0d6b0 t sdma_v6_0_soft_reset +ffffffff81f0db70 t sdma_v6_0_set_clockgating_state +ffffffff81f0dba0 t sdma_v6_0_set_powergating_state +ffffffff81f0dbd0 t sdma_v6_0_get_clockgating_state +ffffffff81f0dc00 t sdma_v6_0_ring_get_rptr +ffffffff81f0dc60 t sdma_v6_0_ring_get_wptr +ffffffff81f0dcd0 t sdma_v6_0_ring_set_wptr +ffffffff81f0e020 t sdma_v6_0_ring_emit_ib +ffffffff81f0e2e0 t sdma_v6_0_ring_emit_fence +ffffffff81f0e740 t sdma_v6_0_ring_emit_pipeline_sync +ffffffff81f0e9c0 t sdma_v6_0_ring_emit_vm_flush +ffffffff81f0ec30 t sdma_v6_0_ring_emit_hdp_flush +ffffffff81f0eed0 t sdma_v6_0_ring_test_ring +ffffffff81f0f290 t sdma_v6_0_ring_test_ib +ffffffff81f0f5c0 t sdma_v6_0_ring_insert_nop +ffffffff81f0f6f0 t sdma_v6_0_ring_pad_ib +ffffffff81f0f820 t sdma_v6_0_ring_init_cond_exec +ffffffff81f0fa50 t sdma_v6_0_ring_patch_cond_exec +ffffffff81f0fb10 t sdma_v6_0_ring_emit_wreg +ffffffff81f0fc60 t sdma_v6_0_ring_emit_reg_wait +ffffffff81f0fee0 t sdma_v6_0_ring_emit_reg_write_reg_wait +ffffffff81f0ff60 t sdma_v6_0_ring_preempt_ib +ffffffff81f100b0 t sdma_v6_0_ring_emit_mem_sync +ffffffff81f102c0 t sdma_v6_0_emit_copy_buffer +ffffffff81f10380 t sdma_v6_0_emit_fill_buffer +ffffffff81f10410 t sdma_v6_0_vm_copy_pte +ffffffff81f104d0 t sdma_v6_0_vm_write_pte +ffffffff81f105a0 t sdma_v6_0_vm_set_pte_pde +ffffffff81f106a0 t sdma_v6_0_set_trap_irq_state +ffffffff81f10730 t sdma_v6_0_process_trap_irq +ffffffff81f10860 t sdma_v6_0_process_illegal_inst_irq +ffffffff81f10890 t sdma_v6_0_mqd_init +ffffffff81f109b0 t sdma_v6_0_start +ffffffff81f10c90 t sdma_v6_0_enable +ffffffff81f10e20 t sdma_v6_0_gfx_resume +ffffffff81f11eb0 t sdma_v6_0_gfx_stop +ffffffff81f13000 T sienna_cichlid_reset_init +ffffffff81f130c0 t sienna_cichlid_async_reset +ffffffff81f13120 t sienna_cichlid_get_reset_handler +ffffffff81f131b0 T sienna_cichlid_reset_fini +ffffffff81f13210 t sienna_cichlid_mode2_prepare_hwcontext +ffffffff81f13360 t sienna_cichlid_mode2_perform_reset +ffffffff81f133e0 t sienna_cichlid_mode2_restore_hwcontext +ffffffff81f136d0 t sienna_cichlid_mode2_reset +ffffffff81f14000 T smu_v11_0_i2c_control_init +ffffffff81f140d0 T smu_v11_0_i2c_control_fini +ffffffff81f14110 t smu_v11_0_i2c_xfer +ffffffff81f152c0 t smu_v11_0_i2c_func +ffffffff81f152f0 t smu_v11_0_i2c_enable +ffffffff81f15440 t smu_v11_0_i2c_abort +ffffffff81f15550 t lock_bus +ffffffff81f155f0 t trylock_bus +ffffffff81f15640 t unlock_bus +ffffffff81f16000 T smu_v13_0_10_reset_init +ffffffff81f160c0 t smu_v13_0_10_async_reset +ffffffff81f16120 t smu_v13_0_10_get_reset_handler +ffffffff81f161d0 T smu_v13_0_10_reset_fini +ffffffff81f16230 t smu_v13_0_10_mode2_prepare_hwcontext +ffffffff81f16360 t smu_v13_0_10_mode2_perform_reset +ffffffff81f163e0 t smu_v13_0_10_mode2_restore_hwcontext +ffffffff81f16740 t smu_v13_0_10_mode2_reset +ffffffff81f17000 t smuio_v11_0_get_rom_index_offset +ffffffff81f17040 t smuio_v11_0_get_rom_data_offset +ffffffff81f17080 t smuio_v11_0_update_rom_clock_gating +ffffffff81f171d0 t smuio_v11_0_get_clock_gating_state +ffffffff81f18000 t smuio_v11_0_6_get_rom_index_offset +ffffffff81f18040 t smuio_v11_0_6_get_rom_data_offset +ffffffff81f18080 t smuio_v11_0_6_update_rom_clock_gating +ffffffff81f181d0 t smuio_v11_0_6_get_clock_gating_state +ffffffff81f19000 t smuio_v13_0_get_rom_index_offset +ffffffff81f19040 t smuio_v13_0_get_rom_data_offset +ffffffff81f19080 t smuio_v13_0_update_rom_clock_gating +ffffffff81f191d0 t smuio_v13_0_get_clock_gating_state +ffffffff81f19270 t smuio_v13_0_get_die_id +ffffffff81f192f0 t smuio_v13_0_get_socket_id +ffffffff81f19380 t smuio_v13_0_is_host_gpu_xgmi_supported +ffffffff81f1a000 t smuio_v13_0_3_get_die_id +ffffffff81f1a080 t smuio_v13_0_3_get_socket_id +ffffffff81f1a110 t smuio_v13_0_3_get_pkg_type +ffffffff81f1b000 t smuio_v13_0_6_get_rom_index_offset +ffffffff81f1b040 t smuio_v13_0_6_get_rom_data_offset +ffffffff81f1c000 t smuio_v9_0_get_rom_index_offset +ffffffff81f1c040 t smuio_v9_0_get_rom_data_offset +ffffffff81f1c080 t smuio_v9_0_update_rom_clock_gating +ffffffff81f1c1c0 t smuio_v9_0_get_clock_gating_state +ffffffff81f1d000 T soc15_grbm_select +ffffffff81f1d090 T soc15_program_register_sequence +ffffffff81f1d290 T soc15_set_virt_ops +ffffffff81f1d300 t soc15_common_early_init +ffffffff81f1d720 t soc15_common_late_init +ffffffff81f1d780 t soc15_common_sw_init +ffffffff81f1d7e0 t soc15_common_sw_fini +ffffffff81f1d830 t soc15_common_hw_init +ffffffff81f1d950 t soc15_common_hw_fini +ffffffff81f1da20 t soc15_common_suspend +ffffffff81f1da60 t soc15_common_resume +ffffffff81f1daa0 t soc15_common_is_idle +ffffffff81f1dad0 t soc15_common_wait_for_idle +ffffffff81f1db00 t soc15_common_soft_reset +ffffffff81f1db30 t soc15_common_set_clockgating_state +ffffffff81f1de70 t soc15_common_set_powergating_state +ffffffff81f1dea0 t soc15_common_get_clockgating_state +ffffffff81f1dfd0 t soc15_uvd_ctx_rreg +ffffffff81f1e070 t soc15_uvd_ctx_wreg +ffffffff81f1e100 t soc15_didt_rreg +ffffffff81f1e1a0 t soc15_didt_wreg +ffffffff81f1e220 t soc15_gc_cac_rreg +ffffffff81f1e340 t soc15_gc_cac_wreg +ffffffff81f1e450 t soc15_se_cac_rreg +ffffffff81f1e570 t soc15_se_cac_wreg +ffffffff81f1e680 t soc15_read_disabled_bios +ffffffff81f1e6b0 t soc15_read_register +ffffffff81f1e7b0 t soc15_asic_reset +ffffffff81f1e8b0 t soc15_asic_reset_method +ffffffff81f1ea60 t soc15_get_xclk +ffffffff81f1eac0 t soc15_set_uvd_clocks +ffffffff81f1eaf0 t soc15_set_vce_clocks +ffffffff81f1eb20 t soc15_get_config_memsize +ffffffff81f1eb40 t soc15_need_full_reset +ffffffff81f1eb70 t soc15_get_pcie_usage +ffffffff81f1eca0 t soc15_need_reset_on_init +ffffffff81f1ed50 t soc15_get_pcie_replay_count +ffffffff81f1edc0 t soc15_supports_baco +ffffffff81f1ee20 t soc15_pre_asic_init +ffffffff81f1ee30 t soc15_query_video_codecs +ffffffff81f1ef20 t vega20_get_pcie_usage +ffffffff81f20000 T soc21_grbm_select +ffffffff81f20090 t soc21_common_early_init +ffffffff81f20200 t soc21_common_late_init +ffffffff81f202e0 t soc21_common_sw_init +ffffffff81f20320 t soc21_common_sw_fini +ffffffff81f20350 t soc21_common_hw_init +ffffffff81f20410 t soc21_common_hw_fini +ffffffff81f204b0 t soc21_common_suspend +ffffffff81f20550 t soc21_common_resume +ffffffff81f20610 t soc21_common_is_idle +ffffffff81f20640 t soc21_common_wait_for_idle +ffffffff81f20670 t soc21_common_soft_reset +ffffffff81f206a0 t soc21_common_set_clockgating_state +ffffffff81f20750 t soc21_common_set_powergating_state +ffffffff81f207b0 t soc21_common_get_clockgating_state +ffffffff81f20800 t soc21_didt_rreg +ffffffff81f208a0 t soc21_didt_wreg +ffffffff81f20920 t soc21_read_disabled_bios +ffffffff81f20950 t soc21_read_register +ffffffff81f20a40 t soc21_asic_reset +ffffffff81f20b20 t soc21_asic_reset_method +ffffffff81f20be0 t soc21_get_xclk +ffffffff81f20c10 t soc21_set_uvd_clocks +ffffffff81f20c40 t soc21_set_vce_clocks +ffffffff81f20c70 t soc21_get_config_memsize +ffffffff81f20c90 t soc21_need_full_reset +ffffffff81f20cf0 t soc21_init_doorbell_index +ffffffff81f20e10 t soc21_need_reset_on_init +ffffffff81f20eb0 t soc21_pre_asic_init +ffffffff81f20ee0 t soc21_update_umd_stable_pstate +ffffffff81f20f60 t soc21_query_video_codecs +ffffffff81f22000 t tonga_ih_early_init +ffffffff81f22050 t tonga_ih_sw_init +ffffffff81f220d0 t tonga_ih_sw_fini +ffffffff81f22110 t tonga_ih_hw_init +ffffffff81f222f0 t tonga_ih_hw_fini +ffffffff81f22390 t tonga_ih_suspend +ffffffff81f22430 t tonga_ih_resume +ffffffff81f22470 t tonga_ih_is_idle +ffffffff81f224c0 t tonga_ih_wait_for_idle +ffffffff81f22560 t tonga_ih_check_soft_reset +ffffffff81f225c0 t tonga_ih_pre_soft_reset +ffffffff81f22670 t tonga_ih_soft_reset +ffffffff81f22740 t tonga_ih_post_soft_reset +ffffffff81f22780 t tonga_ih_set_clockgating_state +ffffffff81f227b0 t tonga_ih_set_powergating_state +ffffffff81f227e0 t tonga_ih_get_wptr +ffffffff81f228d0 t tonga_ih_decode_iv +ffffffff81f22950 t tonga_ih_set_rptr +ffffffff81f23000 t umc_v6_0_init_registers +ffffffff81f24000 t umc_v6_1_query_ras_error_count +ffffffff81f244e0 t umc_v6_1_query_ras_error_address +ffffffff81f247c0 t umc_v6_1_err_cnt_init +ffffffff81f25000 T umc_v6_7_convert_error_address +ffffffff81f25320 t umc_v6_7_query_ras_error_count +ffffffff81f25360 t umc_v6_7_query_ras_error_address +ffffffff81f25380 t umc_v6_7_query_ras_poison_mode +ffffffff81f253e0 t umc_v6_7_ecc_info_query_ras_error_count +ffffffff81f25400 t umc_v6_7_ecc_info_query_ras_error_address +ffffffff81f25420 t umc_v6_7_query_ecc_error_count +ffffffff81f25690 t umc_v6_7_reset_error_count_per_channel +ffffffff81f25790 t umc_v6_7_query_error_address +ffffffff81f258b0 t umc_v6_7_ecc_info_querry_ecc_error_count +ffffffff81f25a80 t umc_v6_7_ecc_info_query_error_address +ffffffff81f26000 t umc_v8_10_query_ras_error_count +ffffffff81f26040 t umc_v8_10_query_ras_error_address +ffffffff81f26060 t umc_v8_10_err_cnt_init +ffffffff81f26080 t umc_v8_10_query_ras_poison_mode +ffffffff81f260b0 t umc_v8_10_ecc_info_query_ras_error_count +ffffffff81f260d0 t umc_v8_10_ecc_info_query_ras_error_address +ffffffff81f260f0 t umc_v8_10_set_eeprom_table_version +ffffffff81f26120 t umc_v8_10_query_ecc_error_count +ffffffff81f261f0 t umc_v8_10_clear_error_count_per_channel +ffffffff81f26260 t umc_v8_10_query_error_address +ffffffff81f26390 t umc_v8_10_convert_error_address +ffffffff81f265b0 t umc_v8_10_err_cnt_init_per_channel +ffffffff81f26660 t umc_v8_10_ecc_info_query_ecc_error_count +ffffffff81f26740 t umc_v8_10_ecc_info_query_error_address +ffffffff81f27000 t umc_v8_7_query_ras_error_count +ffffffff81f27310 t umc_v8_7_query_ras_error_address +ffffffff81f274d0 t umc_v8_7_err_cnt_init +ffffffff81f27630 t umc_v8_7_ecc_info_query_ras_error_count +ffffffff81f27750 t umc_v8_7_ecc_info_query_ras_error_address +ffffffff81f28000 t uvd_v5_0_early_init +ffffffff81f28050 t uvd_v5_0_sw_init +ffffffff81f28140 t uvd_v5_0_sw_fini +ffffffff81f28190 t uvd_v5_0_hw_init +ffffffff81f28690 t uvd_v5_0_hw_fini +ffffffff81f28710 t uvd_v5_0_suspend +ffffffff81f28810 t uvd_v5_0_resume +ffffffff81f28860 t uvd_v5_0_is_idle +ffffffff81f288b0 t uvd_v5_0_wait_for_idle +ffffffff81f28940 t uvd_v5_0_soft_reset +ffffffff81f289e0 t uvd_v5_0_set_clockgating_state +ffffffff81f28b80 t uvd_v5_0_set_powergating_state +ffffffff81f28bc0 t uvd_v5_0_get_clockgating_state +ffffffff81f28c40 t uvd_v5_0_ring_get_rptr +ffffffff81f28c80 t uvd_v5_0_ring_get_wptr +ffffffff81f28cc0 t uvd_v5_0_ring_set_wptr +ffffffff81f28cf0 t uvd_v5_0_ring_emit_ib +ffffffff81f28f60 t uvd_v5_0_ring_emit_fence +ffffffff81f29510 t uvd_v5_0_ring_test_ring +ffffffff81f296b0 t uvd_v5_0_ring_insert_nop +ffffffff81f29810 t uvd_v5_0_set_interrupt_state +ffffffff81f29840 t uvd_v5_0_process_interrupt +ffffffff81f298a0 t uvd_v5_0_stop +ffffffff81f299b0 t uvd_v5_0_start +ffffffff81f2b000 t uvd_v6_0_early_init +ffffffff81f2b160 t uvd_v6_0_sw_init +ffffffff81f2b3c0 t uvd_v6_0_sw_fini +ffffffff81f2b480 t uvd_v6_0_hw_init +ffffffff81f2ba30 t uvd_v6_0_hw_fini +ffffffff81f2bab0 t uvd_v6_0_suspend +ffffffff81f2bbb0 t uvd_v6_0_resume +ffffffff81f2bc00 t uvd_v6_0_is_idle +ffffffff81f2bc50 t uvd_v6_0_wait_for_idle +ffffffff81f2bce0 t uvd_v6_0_check_soft_reset +ffffffff81f2bd60 t uvd_v6_0_pre_soft_reset +ffffffff81f2bda0 t uvd_v6_0_soft_reset +ffffffff81f2be70 t uvd_v6_0_post_soft_reset +ffffffff81f2bf10 t uvd_v6_0_set_clockgating_state +ffffffff81f2c0a0 t uvd_v6_0_set_powergating_state +ffffffff81f2c110 t uvd_v6_0_get_clockgating_state +ffffffff81f2c1a0 t uvd_v6_0_ring_get_rptr +ffffffff81f2c1e0 t uvd_v6_0_ring_get_wptr +ffffffff81f2c220 t uvd_v6_0_ring_set_wptr +ffffffff81f2c250 t uvd_v6_0_ring_emit_ib +ffffffff81f2c5b0 t uvd_v6_0_ring_emit_fence +ffffffff81f2cb60 t uvd_v6_0_ring_emit_pipeline_sync +ffffffff81f2cf50 t uvd_v6_0_ring_emit_vm_flush +ffffffff81f2d2b0 t uvd_v6_0_ring_emit_hdp_flush +ffffffff81f2d2e0 t uvd_v6_0_ring_test_ring +ffffffff81f2d480 t uvd_v6_0_ring_insert_nop +ffffffff81f2d5e0 t uvd_v6_0_ring_emit_wreg +ffffffff81f2d860 t uvd_v6_0_enc_ring_get_rptr +ffffffff81f2d8c0 t uvd_v6_0_enc_ring_get_wptr +ffffffff81f2d920 t uvd_v6_0_enc_ring_set_wptr +ffffffff81f2d960 t uvd_v6_0_enc_ring_emit_ib +ffffffff81f2dba0 t uvd_v6_0_enc_ring_emit_fence +ffffffff81f2dde0 t uvd_v6_0_enc_ring_emit_pipeline_sync +ffffffff81f2df90 t uvd_v6_0_enc_ring_emit_vm_flush +ffffffff81f2e1a0 t uvd_v6_0_enc_ring_test_ring +ffffffff81f2e2f0 t uvd_v6_0_enc_ring_test_ib +ffffffff81f2e7d0 t uvd_v6_0_enc_ring_insert_end +ffffffff81f2e860 t uvd_v6_0_set_interrupt_state +ffffffff81f2e890 t uvd_v6_0_process_interrupt +ffffffff81f2e990 t uvd_v6_0_stop +ffffffff81f2eaa0 t uvd_v6_0_start +ffffffff81f30000 t uvd_v7_0_early_init +ffffffff81f30270 t uvd_v7_0_sw_init +ffffffff81f30690 t uvd_v7_0_sw_fini +ffffffff81f30780 t uvd_v7_0_hw_init +ffffffff81f33540 t uvd_v7_0_hw_fini +ffffffff81f33850 t uvd_v7_0_suspend +ffffffff81f33900 t uvd_v7_0_resume +ffffffff81f33950 t uvd_v7_0_set_clockgating_state +ffffffff81f33980 t uvd_v7_0_ring_get_rptr +ffffffff81f33a20 t uvd_v7_0_ring_get_wptr +ffffffff81f33ac0 t uvd_v7_0_ring_set_wptr +ffffffff81f33b40 t uvd_v7_0_ring_patch_cs_in_place +ffffffff81f33bb0 t uvd_v7_0_ring_emit_ib +ffffffff81f33f50 t uvd_v7_0_ring_emit_fence +ffffffff81f345a0 t uvd_v7_0_ring_emit_vm_flush +ffffffff81f34610 t uvd_v7_0_ring_emit_hdp_flush +ffffffff81f34640 t uvd_v7_0_ring_test_ring +ffffffff81f348d0 t uvd_v7_0_ring_insert_nop +ffffffff81f34a70 t uvd_v7_0_ring_emit_wreg +ffffffff81f34d40 t uvd_v7_0_ring_emit_reg_wait +ffffffff81f350f0 t uvd_v7_0_enc_ring_get_rptr +ffffffff81f351e0 t uvd_v7_0_enc_ring_get_wptr +ffffffff81f352e0 t uvd_v7_0_enc_ring_set_wptr +ffffffff81f353e0 t uvd_v7_0_enc_ring_emit_ib +ffffffff81f35620 t uvd_v7_0_enc_ring_emit_fence +ffffffff81f35860 t uvd_v7_0_enc_ring_emit_vm_flush +ffffffff81f358d0 t uvd_v7_0_enc_ring_test_ring +ffffffff81f35a30 t uvd_v7_0_enc_ring_test_ib +ffffffff81f35f10 t uvd_v7_0_enc_ring_insert_end +ffffffff81f35fa0 t uvd_v7_0_enc_ring_emit_wreg +ffffffff81f360f0 t uvd_v7_0_enc_ring_emit_reg_wait +ffffffff81f362b0 t uvd_v7_0_set_interrupt_state +ffffffff81f362e0 t uvd_v7_0_process_interrupt +ffffffff81f37000 t vce_v3_0_early_init +ffffffff81f37180 t vce_v3_0_sw_init +ffffffff81f372e0 t vce_v3_0_sw_fini +ffffffff81f37330 t vce_v3_0_hw_init +ffffffff81f37400 t vce_v3_0_hw_fini +ffffffff81f374f0 t vce_v3_0_suspend +ffffffff81f375c0 t vce_v3_0_resume +ffffffff81f376a0 t vce_v3_0_is_idle +ffffffff81f37710 t vce_v3_0_wait_for_idle +ffffffff81f377c0 t vce_v3_0_check_soft_reset +ffffffff81f378c0 t vce_v3_0_pre_soft_reset +ffffffff81f37960 t vce_v3_0_soft_reset +ffffffff81f37a30 t vce_v3_0_post_soft_reset +ffffffff81f37ad0 t vce_v3_0_set_clockgating_state +ffffffff81f37dc0 t vce_v3_0_set_powergating_state +ffffffff81f385e0 t vce_v3_0_get_clockgating_state +ffffffff81f386a0 t vce_v3_0_ring_get_rptr +ffffffff81f38770 t vce_v3_0_ring_get_wptr +ffffffff81f38840 t vce_v3_0_ring_set_wptr +ffffffff81f38900 t vce_v3_0_ring_emit_ib +ffffffff81f38b40 t vce_v3_0_emit_pipeline_sync +ffffffff81f38cf0 t vce_v3_0_emit_vm_flush +ffffffff81f38f60 t vce_v3_0_set_interrupt_state +ffffffff81f38fd0 t vce_v3_0_process_interrupt +ffffffff81f39090 t vce_v3_0_stop +ffffffff81f3a000 t vce_v4_0_early_init +ffffffff81f3a0b0 t vce_v4_0_sw_init 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+ffffffff81f3d6d0 T vcn_dec_sw_ring_emit_vm_flush +ffffffff81f3d740 T vcn_dec_sw_ring_emit_wreg +ffffffff81f3e000 T vcn_v1_0_set_pg_for_begin_use +ffffffff81f3e140 T vcn_v1_0_ring_end_use +ffffffff81f3e1b0 t vcn_v1_0_early_init +ffffffff81f3e310 t vcn_v1_0_sw_init +ffffffff81f3e5b0 t vcn_v1_0_sw_fini +ffffffff81f3e610 t vcn_v1_0_hw_init +ffffffff81f3e6e0 t vcn_v1_0_hw_fini +ffffffff81f3e7e0 t vcn_v1_0_suspend +ffffffff81f3e850 t vcn_v1_0_resume +ffffffff81f3e930 t vcn_v1_0_is_idle +ffffffff81f3e9c0 t vcn_v1_0_wait_for_idle +ffffffff81f3ea00 t vcn_v1_0_set_clockgating_state +ffffffff81f3eab0 t vcn_v1_0_set_powergating_state +ffffffff81f3f010 t vcn_v1_0_dec_ring_get_rptr +ffffffff81f3f0a0 t vcn_v1_0_dec_ring_get_wptr +ffffffff81f3f130 t vcn_v1_0_dec_ring_set_wptr +ffffffff81f3f240 t vcn_v1_0_ring_patch_cs_in_place +ffffffff81f3f400 t vcn_v1_0_dec_ring_emit_ib +ffffffff81f3f780 t vcn_v1_0_dec_ring_emit_fence +ffffffff81f3fd90 t vcn_v1_0_dec_ring_emit_vm_flush +ffffffff81f3fe00 t vcn_v1_0_dec_ring_insert_nop +ffffffff81f3ff90 t vcn_v1_0_dec_ring_insert_start +ffffffff81f40160 t vcn_v1_0_dec_ring_insert_end +ffffffff81f40270 t vcn_v1_0_ring_begin_use +ffffffff81f40310 t vcn_v1_0_dec_ring_emit_wreg +ffffffff81f405c0 t vcn_v1_0_dec_ring_emit_reg_wait +ffffffff81f40940 t vcn_v1_0_enc_ring_get_rptr +ffffffff81f40a20 t vcn_v1_0_enc_ring_get_wptr +ffffffff81f40b00 t vcn_v1_0_enc_ring_set_wptr +ffffffff81f40bc0 t vcn_v1_0_enc_ring_emit_ib +ffffffff81f40e00 t vcn_v1_0_enc_ring_emit_fence +ffffffff81f41040 t vcn_v1_0_enc_ring_emit_vm_flush +ffffffff81f410b0 t vcn_v1_0_enc_ring_insert_end +ffffffff81f41140 t vcn_v1_0_enc_ring_emit_wreg +ffffffff81f41290 t vcn_v1_0_enc_ring_emit_reg_wait +ffffffff81f41450 t vcn_v1_0_set_interrupt_state +ffffffff81f41480 t vcn_v1_0_process_interrupt +ffffffff81f41530 t vcn_v1_0_idle_work_handler +ffffffff81f416a0 t vcn_v1_0_pause_dpg_mode +ffffffff81f42540 t vcn_v1_0_enable_clock_gating +ffffffff81f42970 t vcn_v1_0_disable_clock_gating +ffffffff81f42f30 t vcn_1_0_enable_static_power_gating +ffffffff81f430e0 t vcn_v1_0_start_dpg_mode +ffffffff81f46ea0 t vcn_v1_0_start_spg_mode +ffffffff81f490a0 t vcn_v1_0_clock_gating_dpg_mode +ffffffff81f4a000 T vcn_v2_0_dec_ring_insert_start +ffffffff81f4a1c0 T vcn_v2_0_dec_ring_insert_end +ffffffff81f4a2c0 T vcn_v2_0_dec_ring_insert_nop +ffffffff81f4a430 T vcn_v2_0_dec_ring_emit_fence +ffffffff81f4a9f0 T vcn_v2_0_dec_ring_emit_ib +ffffffff81f4ad50 T vcn_v2_0_dec_ring_emit_reg_wait +ffffffff81f4b0a0 T vcn_v2_0_dec_ring_emit_vm_flush +ffffffff81f4b110 T vcn_v2_0_dec_ring_emit_wreg +ffffffff81f4b390 T vcn_v2_0_enc_ring_emit_fence +ffffffff81f4b5d0 T vcn_v2_0_enc_ring_insert_end +ffffffff81f4b660 T vcn_v2_0_enc_ring_emit_ib +ffffffff81f4b8a0 T vcn_v2_0_enc_ring_emit_reg_wait +ffffffff81f4ba60 T vcn_v2_0_enc_ring_emit_vm_flush +ffffffff81f4bad0 T vcn_v2_0_enc_ring_emit_wreg +ffffffff81f4bc20 T vcn_v2_0_dec_ring_test_ring +ffffffff81f4bec0 t vcn_v2_0_early_init +ffffffff81f4c020 t vcn_v2_0_sw_init +ffffffff81f4c350 t vcn_v2_0_sw_fini +ffffffff81f4c3d0 t vcn_v2_0_hw_init +ffffffff81f4cd50 t vcn_v2_0_hw_fini +ffffffff81f4ce50 t vcn_v2_0_suspend +ffffffff81f4ce80 t vcn_v2_0_resume +ffffffff81f4ced0 t vcn_v2_0_is_idle +ffffffff81f4cf60 t vcn_v2_0_wait_for_idle +ffffffff81f4cfa0 t vcn_v2_0_set_clockgating_state +ffffffff81f4d030 t vcn_v2_0_set_powergating_state +ffffffff81f4d5f0 t vcn_v2_0_dec_ring_get_rptr +ffffffff81f4d680 t vcn_v2_0_dec_ring_get_wptr +ffffffff81f4d720 t vcn_v2_0_dec_ring_set_wptr +ffffffff81f4d860 t vcn_v2_0_enc_ring_get_rptr +ffffffff81f4d940 t vcn_v2_0_enc_ring_get_wptr +ffffffff81f4da30 t vcn_v2_0_enc_ring_set_wptr +ffffffff81f4db20 t vcn_v2_0_set_interrupt_state +ffffffff81f4db50 t vcn_v2_0_process_interrupt +ffffffff81f4dc00 t vcn_v2_0_pause_dpg_mode +ffffffff81f4e3f0 t vcn_v2_0_enable_clock_gating +ffffffff81f4e680 t vcn_v2_0_disable_clock_gating +ffffffff81f4eaa0 t vcn_v2_0_start +ffffffff81f53050 t vcn_v2_0_enable_static_power_gating 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vcn_v2_6_set_ras_interrupt_state +ffffffff81f5d040 t vcn_v2_5_pause_dpg_mode +ffffffff81f5d7c0 t vcn_v2_5_enable_clock_gating +ffffffff81f5dad0 t vcn_v2_5_disable_clock_gating +ffffffff81f5dfc0 t vcn_v2_5_start_dpg_mode +ffffffff81f61990 t vcn_v2_5_clock_gating_dpg_mode +ffffffff81f62740 t vcn_v2_5_mc_resume_dpg_mode +ffffffff81f67000 t vcn_v3_0_early_init +ffffffff81f67220 t vcn_v3_0_sw_init +ffffffff81f676e0 t vcn_v3_0_sw_fini +ffffffff81f677c0 t vcn_v3_0_hw_init +ffffffff81f68310 t vcn_v3_0_hw_fini +ffffffff81f68410 t vcn_v3_0_suspend +ffffffff81f68440 t vcn_v3_0_resume +ffffffff81f68490 t vcn_v3_0_is_idle +ffffffff81f68580 t vcn_v3_0_wait_for_idle +ffffffff81f68620 t vcn_v3_0_set_clockgating_state +ffffffff81f68730 t vcn_v3_0_set_powergating_state +ffffffff81f6acc0 t vcn_v3_0_dec_ring_get_rptr +ffffffff81f6ad60 t vcn_v3_0_dec_ring_get_wptr +ffffffff81f6ae10 t vcn_v3_0_dec_ring_set_wptr +ffffffff81f6af80 t vcn_v3_0_ring_patch_cs_in_place +ffffffff81f6b2a0 t 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amdgpu_dm_crtc_vrr_active_irq +ffffffff81faa0f0 T amdgpu_dm_crtc_set_vupdate_irq +ffffffff81faa1a0 T amdgpu_dm_crtc_vrr_active +ffffffff81faa1e0 T amdgpu_dm_crtc_enable_vblank +ffffffff81faa200 t dm_set_vblank +ffffffff81faa450 T amdgpu_dm_crtc_disable_vblank +ffffffff81faa470 T amdgpu_dm_crtc_init +ffffffff81faa650 t vblank_control_worker +ffffffff81faa790 t dm_crtc_reset_state +ffffffff81faa830 t amdgpu_dm_crtc_destroy +ffffffff81faa860 t dm_crtc_duplicate_state +ffffffff81faaa10 t dm_crtc_destroy_state +ffffffff81faaa50 t dm_crtc_helper_mode_fixup +ffffffff81faaa80 t dm_crtc_helper_disable +ffffffff81faaab0 t dm_crtc_helper_atomic_check +ffffffff81fab000 T hdcp_update_display +ffffffff81fab280 t process_output +ffffffff81fab3d0 T hdcp_reset_display +ffffffff81fab530 T hdcp_handle_cpirq +ffffffff81fab560 T hdcp_destroy +ffffffff81fab650 T hdcp_create_workqueue +ffffffff81faba30 t event_cpirq +ffffffff81faba80 t event_property_update +ffffffff81fabcb0 t event_callback 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dm_helpers_dp_read_dpcd +ffffffff81fadbb0 T dm_helpers_dp_write_dpcd +ffffffff81fadc30 T dm_helpers_submit_i2c +ffffffff81fadd50 T dm_helpers_dp_write_dsc_enable +ffffffff81fae380 T dm_helpers_is_dp_sink_present +ffffffff81fae410 T dm_helpers_read_local_edid +ffffffff81fae670 T dm_helper_dmub_aux_transfer_sync +ffffffff81fae690 T dm_helpers_dmub_set_config_sync +ffffffff81fae6b0 T dm_set_dcn_clocks +ffffffff81fae6e0 T dm_helpers_smu_timeout +ffffffff81fae710 T dm_helpers_init_panel_settings +ffffffff81fae780 T dm_helpers_override_panel_settings +ffffffff81fae7c0 T dm_helpers_allocate_gpu_mem +ffffffff81fae8c0 T dm_helpers_free_gpu_mem +ffffffff81fae950 T dm_helpers_dmub_outbox_interrupt_control +ffffffff81fae9e0 T dm_helpers_mst_enable_stream_features +ffffffff81faeaf0 T dm_helpers_dp_handle_test_pattern_request +ffffffff81faee20 T dm_set_phyd32clk +ffffffff81faee50 T dm_helpers_enable_periodic_detection +ffffffff81faee80 T dm_helpers_dp_mst_update_branch_bandwidth +ffffffff81faeeb0 T dm_get_adaptive_sync_support_type +ffffffff81faef20 t execute_synaptics_rc_command +ffffffff81fb0000 T amdgpu_dm_irq_register_interrupt +ffffffff81fb01a0 t dm_irq_work_func +ffffffff81fb01c0 T amdgpu_dm_irq_unregister_interrupt +ffffffff81fb0340 T amdgpu_dm_irq_init +ffffffff81fb0430 T amdgpu_dm_irq_fini +ffffffff81fb05d0 T amdgpu_dm_irq_suspend +ffffffff81fb06e0 T amdgpu_dm_irq_resume_early +ffffffff81fb08a0 T amdgpu_dm_irq_resume_late +ffffffff81fb0a60 T amdgpu_dm_set_irq_funcs +ffffffff81fb0b20 T amdgpu_dm_outbox_init +ffffffff81fb0b50 T amdgpu_dm_hpd_init +ffffffff81fb0c00 T amdgpu_dm_hpd_fini +ffffffff81fb0cb0 t amdgpu_dm_set_crtc_irq_state +ffffffff81fb0d30 t amdgpu_dm_irq_handler +ffffffff81fb0f30 t amdgpu_dm_set_vline0_irq_state +ffffffff81fb0fb0 t amdgpu_dm_set_dmub_outbox_irq_state +ffffffff81fb1000 t amdgpu_dm_set_vupdate_irq_state +ffffffff81fb1080 t amdgpu_dm_set_dmub_trace_irq_state +ffffffff81fb10d0 t amdgpu_dm_set_pflip_irq_state +ffffffff81fb1150 t amdgpu_dm_set_hpd_irq_state +ffffffff81fb2000 T needs_dsc_aux_workaround +ffffffff81fb2050 T dm_dp_create_fake_mst_encoders +ffffffff81fb2100 T dm_handle_mst_sideband_msg_ready_event +ffffffff81fb2340 T amdgpu_dm_initialize_dp_connector +ffffffff81fb2440 t kasprintf +ffffffff81fb2510 t dm_dp_aux_transfer +ffffffff81fb2650 T dm_mst_get_pbn_divider +ffffffff81fb26b0 T compute_mst_dsc_configs_for_state +ffffffff81fb2950 t is_dsc_need_re_compute +ffffffff81fb2b20 t compute_mst_dsc_configs_for_link +ffffffff81fb3150 T pre_validate_dsc +ffffffff81fb3700 T dm_dp_mst_is_port_support_mode +ffffffff81fb3960 t amdgpu_dm_encoder_destroy +ffffffff81fb3970 t dm_dp_add_mst_connector +ffffffff81fb3b30 t dm_handle_mst_down_rep_msg_ready +ffffffff81fb3b50 t amdgpu_dm_mst_connector_late_register +ffffffff81fb3ba0 t amdgpu_dm_mst_connector_early_unregister +ffffffff81fb3c70 t dm_dp_mst_connector_destroy +ffffffff81fb3cf0 t dm_dp_mst_get_modes +ffffffff81fb41e0 t dm_dp_mst_detect +ffffffff81fb43a0 t dm_mst_atomic_best_encoder +ffffffff81fb4400 t dm_dp_mst_atomic_check +ffffffff81fb4430 t set_dsc_configs_from_fairness_vars +ffffffff81fb4700 t increase_dsc_bpp +ffffffff81fb4c50 t try_disable_dsc +ffffffff81fb5000 T amdgpu_dm_plane_get_format_info +ffffffff81fb5020 T amdgpu_dm_plane_fill_blending_from_plane_state +ffffffff81fb5120 T amdgpu_dm_plane_fill_plane_buffer_attributes +ffffffff81fb56a0 T amdgpu_dm_plane_helper_check_state +ffffffff81fb58c0 T amdgpu_dm_plane_fill_dc_scaling_info +ffffffff81fb5b20 T amdgpu_dm_plane_handle_cursor_update +ffffffff81fb5db0 T amdgpu_dm_plane_init +ffffffff81fb6bb0 T is_video_format +ffffffff81fb6c00 t dm_drm_plane_reset +ffffffff81fb6c90 t dm_drm_plane_duplicate_state +ffffffff81fb6d20 t dm_drm_plane_destroy_state +ffffffff81fb6d60 t dm_plane_format_mod_supported +ffffffff81fb6e90 t dm_plane_helper_prepare_fb +ffffffff81fb7140 t dm_plane_helper_cleanup_fb +ffffffff81fb71e0 t dm_plane_atomic_check +ffffffff81fb72b0 t dm_plane_atomic_async_check +ffffffff81fb72f0 t dm_plane_atomic_async_update +ffffffff81fb73a0 t amdgpu_bo_reserve +ffffffff81fb75a0 t amdgpu_bo_unreserve +ffffffff81fb8000 T dm_pp_apply_display_requirements +ffffffff81fb81d0 T dm_pp_get_clock_levels_by_type +ffffffff81fb8510 T dm_pp_get_clock_levels_by_type_with_latency +ffffffff81fb86d0 T dm_pp_get_clock_levels_by_type_with_voltage +ffffffff81fb8880 T dm_pp_notify_wm_clock_changes +ffffffff81fb88d0 T dm_pp_apply_power_level_change_request +ffffffff81fb8900 T dm_pp_apply_clock_for_voltage_request +ffffffff81fb89a0 T dm_pp_get_static_clocks +ffffffff81fb8a60 T dm_pp_get_funcs +ffffffff81fb8b70 t pp_rv_set_wm_ranges +ffffffff81fb8cf0 t pp_rv_set_pme_wa_enable +ffffffff81fb8d10 t pp_rv_set_active_display_count +ffffffff81fb8d30 t pp_rv_set_min_deep_sleep_dcfclk +ffffffff81fb8d50 t pp_rv_set_hard_min_dcefclk_by_freq +ffffffff81fb8d70 t pp_rv_set_hard_min_fclk_by_freq +ffffffff81fb8d90 t pp_nv_set_display_count +ffffffff81fb8df0 t pp_nv_set_hard_min_dcefclk_by_freq +ffffffff81fb8e60 t pp_nv_set_min_deep_sleep_dcfclk +ffffffff81fb8ec0 t pp_nv_set_voltage_by_freq +ffffffff81fb8f50 t pp_nv_set_wm_ranges +ffffffff81fb8fa0 t pp_nv_set_hard_min_uclk_by_freq +ffffffff81fb9010 t pp_nv_get_maximum_sustainable_clocks +ffffffff81fb9070 t pp_nv_get_uclk_dpm_states +ffffffff81fb90d0 t pp_nv_set_pstate_handshake_support +ffffffff81fb9120 t pp_rn_set_wm_ranges +ffffffff81fb9170 t pp_rn_get_dpm_clock_table +ffffffff81fba000 T amdgpu_dm_set_psr_caps +ffffffff81fba150 T amdgpu_dm_link_setup_psr +ffffffff81fba2e0 T amdgpu_dm_psr_enable +ffffffff81fba3e0 T amdgpu_dm_psr_disable +ffffffff81fba460 T amdgpu_dm_psr_disable_all +ffffffff81fbb000 T amdgpu_dm_setup_replay +ffffffff81fbb0f0 T amdgpu_dm_replay_enable +ffffffff81fbb270 T amdgpu_dm_replay_disable +ffffffff81fbc000 T dm_get_elapse_time_in_ns +ffffffff81fbc030 T dm_perf_trace_timestamp +ffffffff81fbd000 T dc_assert_fp_enabled +ffffffff81fbd070 T dc_fpu_begin +ffffffff81fbd0c0 T dc_fpu_end +ffffffff81fbe000 T dal_vector_construct +ffffffff81fbe0d0 T dal_vector_presized_create +ffffffff81fbe340 T dal_vector_create +ffffffff81fbe460 T dal_vector_destruct +ffffffff81fbe4b0 T dal_vector_destroy +ffffffff81fbe530 T dal_vector_get_count +ffffffff81fbe560 T dal_vector_at_index +ffffffff81fbe5a0 T dal_vector_remove_at_index +ffffffff81fbe630 T dal_vector_set_at_index +ffffffff81fbe690 T dal_vector_insert_at +ffffffff81fbe790 T dal_vector_reserve +ffffffff81fbe840 T dal_vector_append +ffffffff81fbe940 T dal_vector_clone +ffffffff81fbe9f0 T dal_vector_capacity +ffffffff81fbea20 T dal_vector_clear +ffffffff81fbf000 T fixed_point_to_int_frac +ffffffff81fbf1f0 T convert_float_matrix +ffffffff81fbf2b0 T reduce_fraction +ffffffff81fc0000 T is_rgb_cspace +ffffffff81fc0080 T is_lower_pipe_tree_visible +ffffffff81fc00e0 T is_upper_pipe_tree_visible +ffffffff81fc0140 T is_pipe_tree_visible +ffffffff81fc01c0 T build_prescale_params +ffffffff81fc1000 T dc_fixpt_from_fraction +ffffffff81fc11c0 T dc_fixpt_mul +ffffffff81fc1360 T dc_fixpt_sqr +ffffffff81fc14d0 T dc_fixpt_recip +ffffffff81fc1540 T dc_fixpt_sinc +ffffffff81fc1730 T dc_fixpt_sin +ffffffff81fc1760 T dc_fixpt_cos +ffffffff81fc1850 T dc_fixpt_exp +ffffffff81fc1b30 t fixed31_32_exp_from_taylor_series +ffffffff81fc1f10 T dc_fixpt_log +ffffffff81fc2120 T dc_fixpt_u4d19 +ffffffff81fc2160 T dc_fixpt_u3d19 +ffffffff81fc21a0 T dc_fixpt_u2d19 +ffffffff81fc21e0 T dc_fixpt_u0d19 +ffffffff81fc2210 T dc_fixpt_clamp_u0d14 +ffffffff81fc2260 T dc_fixpt_clamp_u0d10 +ffffffff81fc22b0 T dc_fixpt_s4d19 +ffffffff81fc3000 T bios_parser_create +ffffffff81fc4270 t bios_parser_get_connectors_number +ffffffff81fc42d0 t bios_parser_get_connector_id +ffffffff81fc4360 t bios_parser_get_src_obj +ffffffff81fc4460 t bios_parser_get_i2c_info +ffffffff81fc4680 t bios_parser_get_hpd_info +ffffffff81fc4760 t bios_parser_get_device_tag +ffffffff81fc4960 t bios_parser_get_spread_spectrum_info +ffffffff81fc4b60 t bios_parser_get_ss_entry_number +ffffffff81fc4da0 t bios_parser_get_embedded_panel_info +ffffffff81fc5310 t bios_parser_get_gpio_pin_info +ffffffff81fc5420 t bios_parser_get_encoder_cap_info +ffffffff81fc5520 t bios_parser_set_scratch_critical_state +ffffffff81fc5530 t bios_parser_is_device_id_supported +ffffffff81fc55f0 t bios_parser_encoder_control +ffffffff81fc5630 t bios_parser_transmitter_control +ffffffff81fc5670 t bios_parser_enable_crtc +ffffffff81fc56c0 t bios_parser_adjust_pixel_clock +ffffffff81fc5700 t bios_parser_set_pixel_clock +ffffffff81fc5740 t bios_parser_set_dce_clock +ffffffff81fc5780 t bios_parser_enable_spread_spectrum_on_ppll +ffffffff81fc57d0 t bios_parser_program_crtc_timing +ffffffff81fc5810 t bios_parser_program_display_engine_pll +ffffffff81fc5850 t bios_parser_enable_disp_power_gating +ffffffff81fc5890 t bios_parser_destroy +ffffffff81fc5950 t bios_get_board_layout_info +ffffffff81fc5bd0 t get_bios_object +ffffffff81fc5da0 t get_ss_info_from_ss_info_table +ffffffff81fc5f70 t get_ss_info_v3_1 +ffffffff81fc60e0 t get_ss_entry_number_from_ss_info_tbl +ffffffff81fc7000 T firmware_parser_create +ffffffff81fc8e70 t bios_parser_get_connectors_number +ffffffff81fc8fe0 t bios_parser_get_connector_id +ffffffff81fc9040 t bios_parser_get_src_obj +ffffffff81fc92e0 t bios_parser_get_i2c_info +ffffffff81fc9580 t bios_parser_get_hpd_info +ffffffff81fc96f0 t bios_parser_get_device_tag +ffffffff81fc99c0 t bios_parser_get_spread_spectrum_info +ffffffff81fc9e40 t bios_parser_get_ss_entry_number +ffffffff81fc9e70 t bios_parser_get_embedded_panel_info +ffffffff81fca070 t bios_parser_get_gpio_pin_info +ffffffff81fca190 t bios_parser_get_encoder_cap_info +ffffffff81fca300 t bios_parser_is_accelerated_mode +ffffffff81fca310 t bios_parser_set_scratch_critical_state +ffffffff81fca320 t bios_parser_is_device_id_supported +ffffffff81fca390 t bios_parser_encoder_control +ffffffff81fca3d0 t bios_parser_transmitter_control +ffffffff81fca410 t bios_parser_enable_crtc +ffffffff81fca460 t bios_parser_set_pixel_clock +ffffffff81fca4a0 t bios_parser_set_dce_clock +ffffffff81fca4e0 t bios_parser_program_crtc_timing +ffffffff81fca520 t bios_parser_enable_disp_power_gating +ffffffff81fca560 t firmware_parser_destroy +ffffffff81fca620 t bios_get_board_layout_info +ffffffff81fcaac0 t bios_parser_pack_data_tables +ffffffff81fcaaf0 t bios_get_atom_dc_golden_table +ffffffff81fcac30 t bios_parser_enable_lvtma_control +ffffffff81fcac80 t bios_parser_get_soc_bb_info +ffffffff81fcad90 t bios_parser_get_disp_connector_caps_info +ffffffff81fcaef0 t bios_parser_get_lttpr_caps +ffffffff81fcb040 t bios_parser_get_lttpr_interop +ffffffff81fcb180 t bios_parser_get_connector_speed_cap_info +ffffffff81fcb2d0 t get_bios_object +ffffffff81fcb430 t get_bios_object_from_path_v3 +ffffffff81fcc000 T object_id_from_bios_object_id +ffffffff81fcd000 T bios_get_image +ffffffff81fcd050 T bios_is_accelerated_mode +ffffffff81fcd0b0 T bios_set_scratch_acc_mode_change +ffffffff81fcd0f0 T bios_set_scratch_critical_state +ffffffff81fcd130 T bios_get_vga_enabled_displays +ffffffff81fce000 T dal_bios_parser_create +ffffffff81fce070 T dal_bios_parser_destroy +ffffffff81fcf000 T dal_bios_parser_init_cmd_tbl +ffffffff81fcf810 t encoder_control_digx_v3 +ffffffff81fcf910 t encoder_control_digx_v4 +ffffffff81fcfa10 t encoder_control_digx_v5 +ffffffff81fcfb60 t encoder_control_dig1_v1 +ffffffff81fcfbe0 t encoder_control_dig2_v1 +ffffffff81fcfc60 t encoder_control_dig_v1 +ffffffff81fcfcc0 t transmitter_control_v2 +ffffffff81fcfe60 t transmitter_control_v3 +ffffffff81fd0010 t transmitter_control_v4 +ffffffff81fd01c0 t transmitter_control_v1_5 +ffffffff81fd0330 t transmitter_control_v1_6 +ffffffff81fd0490 t set_pixel_clock_v3 +ffffffff81fd0600 t set_pixel_clock_v5 +ffffffff81fd07a0 t set_pixel_clock_v6 +ffffffff81fd0940 t set_pixel_clock_v7 +ffffffff81fd0b10 t enable_spread_spectrum_on_ppll_v1 +ffffffff81fd0c30 t enable_spread_spectrum_on_ppll_v2 +ffffffff81fd0d60 t enable_spread_spectrum_on_ppll_v3 +ffffffff81fd0e70 t adjust_display_pll_v2 +ffffffff81fd0fc0 t adjust_display_pll_v3 +ffffffff81fd1130 t dac1_encoder_control_v1 +ffffffff81fd11b0 t dac2_encoder_control_v1 +ffffffff81fd1230 t dac1_output_control_v1 +ffffffff81fd1290 t dac2_output_control_v1 +ffffffff81fd12f0 t set_crtc_using_dtd_timing_v3 +ffffffff81fd1440 t set_crtc_timing_v1 +ffffffff81fd15c0 t enable_crtc_v1 +ffffffff81fd1660 t enable_crtc_mem_req_v1 +ffffffff81fd1700 t program_clock_v5 +ffffffff81fd1810 t program_clock_v6 +ffffffff81fd1930 t external_encoder_control_v3 +ffffffff81fd1ae0 t enable_disp_power_gating_v2_1 +ffffffff81fd1bb0 t set_dce_clock_v2_1 +ffffffff81fd2000 T dal_firmware_parser_init_cmd_tbl +ffffffff81fd23d0 t encoder_control_digx_v1_5 +ffffffff81fd25a0 t encoder_control_fallback +ffffffff81fd2600 t transmitter_control_v1_6 +ffffffff81fd27a0 t transmitter_control_v1_7 +ffffffff81fd2990 t transmitter_control_fallback +ffffffff81fd29f0 t set_pixel_clock_v7 +ffffffff81fd2c40 t set_pixel_clock_fallback +ffffffff81fd2ca0 t set_crtc_using_dtd_timing_v3 +ffffffff81fd2df0 t enable_crtc_v1 +ffffffff81fd2e90 t external_encoder_control_v3 +ffffffff81fd2ec0 t enable_disp_power_gating_v2_1 +ffffffff81fd3010 t enable_disp_power_gating_fallback +ffffffff81fd3070 t set_dce_clock_v2_1 +ffffffff81fd31a0 t get_smu_clock_info_v3_1 +ffffffff81fd3210 t enable_lvtma_control +ffffffff81fd4000 T dal_bios_parser_init_cmd_tbl_helper +ffffffff81fd40a0 T dal_cmd_table_helper_controller_id_to_atom +ffffffff81fd41c0 T dal_cmd_table_helper_transmitter_bp_to_atom +ffffffff81fd4240 T dal_cmd_table_helper_encoder_mode_bp_to_atom +ffffffff81fd42d0 T dal_cmd_table_helper_assign_control_parameter +ffffffff81fd4390 T dal_cmd_table_helper_clock_source_id_to_ref_clk_src +ffffffff81fd4470 T dal_cmd_table_helper_encoder_id_to_atom +ffffffff81fd5000 T dal_bios_parser_init_cmd_tbl_helper2 +ffffffff81fd50b0 T dal_cmd_table_helper_controller_id_to_atom2 +ffffffff81fd51c0 T dal_cmd_table_helper_transmitter_bp_to_atom2 +ffffffff81fd5240 T dal_cmd_table_helper_encoder_mode_bp_to_atom2 +ffffffff81fd52d0 T dal_cmd_table_helper_clock_source_id_to_ref_clk_src2 +ffffffff81fd53b0 T dal_cmd_table_helper_encoder_id_to_atom2 +ffffffff81fd6000 T dal_cmd_tbl_helper_dce110_get_table ffffffff81fd6030 t encoder_action_to_atom ffffffff81fd60b0 t engine_bp_to_atom ffffffff81fd6100 t clock_source_id_to_atom -ffffffff81fd61d0 t clock_source_id_to_atom_phy_clk_src_id -ffffffff81fd6220 t signal_type_to_atom_dig_mode -ffffffff81fd6280 t hpd_sel_to_atom -ffffffff81fd62c0 t dig_encoder_sel_to_atom -ffffffff81fd62f0 t phy_id_to_atom -ffffffff81fd6330 t disp_power_gating_action_to_atom -ffffffff81fd63a0 t dc_clock_type_to_atom -ffffffff81fd6420 t transmitter_color_depth_to_atom -ffffffff81fd7000 T dal_cmd_tbl_helper_dce80_get_table +ffffffff81fd61a0 t clock_source_id_to_atom_phy_clk_src_id +ffffffff81fd61f0 t signal_type_to_atom_dig_mode +ffffffff81fd6250 t hpd_sel_to_atom +ffffffff81fd6290 t dig_encoder_sel_to_atom +ffffffff81fd62c0 t phy_id_to_atom +ffffffff81fd6300 t disp_power_gating_action_to_atom +ffffffff81fd7000 T dal_cmd_tbl_helper_dce112_get_table2 ffffffff81fd7030 t encoder_action_to_atom ffffffff81fd70b0 t engine_bp_to_atom ffffffff81fd7100 t clock_source_id_to_atom @@ -31076,16601 +31055,16615 @@ ffffffff81fd71d0 t clock_source_id_to_atom_phy_clk_src ffffffff81fd7220 t signal_type_to_atom_dig_mode ffffffff81fd7280 t hpd_sel_to_atom ffffffff81fd72c0 t dig_encoder_sel_to_atom -ffffffff81fd7310 t phy_id_to_atom -ffffffff81fd7350 t disp_power_gating_action_to_atom -ffffffff81fd8000 T clk_mgr_helper_get_active_display_cnt -ffffffff81fd80e0 T clk_mgr_helper_get_active_plane_cnt -ffffffff81fd8190 T clk_mgr_exit_optimized_pwr_state -ffffffff81fd82a0 T clk_mgr_optimize_pwr_state -ffffffff81fd8390 T dc_clk_mgr_create -ffffffff81fd8a50 T dc_destroy_clk_mgr -ffffffff81fd9000 T dentist_get_divider_from_did -ffffffff81fd9070 T dce_adjust_dp_ref_freq_for_ss -ffffffff81fd9170 T dce_get_dp_ref_freq_khz -ffffffff81fd92a0 T dce12_get_dp_ref_freq_khz -ffffffff81fd92c0 T dce_get_max_pixel_clock_for_all_paths -ffffffff81fd94d0 T dce_get_required_clocks_state -ffffffff81fd9580 T dce_set_clock -ffffffff81fd96e0 T dce_clock_read_ss_info -ffffffff81fd9800 T dce_clk_mgr_construct -ffffffff81fd99f0 t dce_update_clocks -ffffffff81fda000 T dce110_get_min_vblank_time_us -ffffffff81fda090 T dce110_fill_display_configs -ffffffff81fda300 T dce11_pplib_apply_display_requirements -ffffffff81fda5f0 T dce110_clk_mgr_construct -ffffffff81fda6a0 t dce11_update_clocks -ffffffff81fdb000 T dce112_set_clock -ffffffff81fdb180 T dce112_set_dispclk -ffffffff81fdb2a0 T dce112_set_dprefclk -ffffffff81fdb310 T dce112_clk_mgr_construct -ffffffff81fdb3c0 t dce112_update_clocks -ffffffff81fdc000 T dce120_clk_mgr_construct -ffffffff81fdc090 T dce121_clk_mgr_construct -ffffffff81fdc1c0 t dce12_update_clocks -ffffffff81fdd000 T rv1_clk_mgr_construct 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clk_mgr_optimize_pwr_state +ffffffff81fda390 T dc_clk_mgr_create +ffffffff81fdaa50 T dc_destroy_clk_mgr +ffffffff81fdb000 T dentist_get_divider_from_did +ffffffff81fdb070 T dce_adjust_dp_ref_freq_for_ss +ffffffff81fdb170 T dce_get_dp_ref_freq_khz +ffffffff81fdb2a0 T dce12_get_dp_ref_freq_khz +ffffffff81fdb2c0 T dce_get_max_pixel_clock_for_all_paths +ffffffff81fdb4d0 T dce_get_required_clocks_state +ffffffff81fdb580 T dce_set_clock +ffffffff81fdb6e0 T dce_clock_read_ss_info +ffffffff81fdb800 T dce_clk_mgr_construct +ffffffff81fdb9f0 t dce_update_clocks +ffffffff81fdc000 T dce110_get_min_vblank_time_us +ffffffff81fdc090 T dce110_fill_display_configs +ffffffff81fdc300 T dce11_pplib_apply_display_requirements +ffffffff81fdc5f0 T dce110_clk_mgr_construct +ffffffff81fdc6a0 t dce11_update_clocks +ffffffff81fdd000 T dce112_set_clock +ffffffff81fdd180 T dce112_set_dispclk +ffffffff81fdd2a0 T dce112_set_dprefclk +ffffffff81fdd310 T dce112_clk_mgr_construct +ffffffff81fdd3c0 t dce112_update_clocks +ffffffff81fde000 T dce120_clk_mgr_construct +ffffffff81fde090 T dce121_clk_mgr_construct +ffffffff81fde1c0 t dce12_update_clocks +ffffffff81fdf000 T rv1_clk_mgr_construct +ffffffff81fdf0c0 t rv1_update_clocks +ffffffff81fdf5a0 t rv1_init_clocks +ffffffff81fdf630 t rv1_enable_pme_wa +ffffffff81fe0000 T rv1_vbios_smu_set_dispclk +ffffffff81fe00e0 t rv1_vbios_smu_send_msg_with_param +ffffffff81fe01f0 T rv1_vbios_smu_set_dprefclk +ffffffff81fe1000 T rv2_clk_mgr_construct +ffffffff81fe2000 T dentist_get_did_from_divider +ffffffff81fe2080 T dcn20_update_clocks_update_dpp_dto +ffffffff81fe2150 T dcn20_update_clocks_update_dentist +ffffffff81fe2640 T dcn2_update_clocks +ffffffff81fe2bc0 T dcn2_read_clocks_from_hw_dentist +ffffffff81fe2c90 T dcn2_update_clocks_fpga +ffffffff81fe2dc0 T dcn2_init_clocks +ffffffff81fe2e60 T dcn2_get_clock +ffffffff81fe2ed0 T dcn20_clk_mgr_construct +ffffffff81fe3000 t dcn2_enable_pme_wa +ffffffff81fe3050 t dcn2_are_clock_states_equal +ffffffff81fe30c0 t dcn2_notify_link_rate_change +ffffffff81fe4000 T dcn201_clk_mgr_construct +ffffffff81fe4120 t dcn201_update_clocks +ffffffff81fe4340 t dcn201_init_clocks +ffffffff81fe5000 T rn_clk_mgr_construct +ffffffff81fe58a0 t rn_update_clocks +ffffffff81fe5e60 t rn_set_low_power_state +ffffffff81fe6040 t rn_init_clocks +ffffffff81fe60e0 t rn_enable_pme_wa +ffffffff81fe60f0 t rn_are_clock_states_equal +ffffffff81fe6140 t rn_notify_wm_ranges +ffffffff81fe64d0 t rn_notify_link_rate_change +ffffffff81fe7000 T rn_vbios_smu_get_smu_version +ffffffff81fe7020 t rn_vbios_smu_send_msg_with_param +ffffffff81fe71b0 T rn_vbios_smu_set_dispclk +ffffffff81fe72d0 T rn_vbios_smu_set_dprefclk +ffffffff81fe7340 T rn_vbios_smu_set_hard_min_dcfclk +ffffffff81fe73c0 T rn_vbios_smu_set_min_deep_sleep_dcfclk +ffffffff81fe7440 T rn_vbios_smu_set_phyclk +ffffffff81fe7480 T rn_vbios_smu_set_dppclk +ffffffff81fe7530 T rn_vbios_smu_set_dcn_low_power_state +ffffffff81fe7550 T rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn +ffffffff81fe7570 T rn_vbios_smu_enable_pme_wa +ffffffff81fe7590 T rn_vbios_smu_is_periodic_retraining_disabled +ffffffff81fe8000 T dcn3_init_clocks +ffffffff81fe83b0 t dcn3_init_clocks_fpga +ffffffff81fe83c0 T dcn3_clk_mgr_construct +ffffffff81fe8510 T dcn3_clk_mgr_destroy +ffffffff81fe8570 t dcn3_update_clocks +ffffffff81fe8990 t dcn3_enable_pme_wa +ffffffff81fe89d0 t dcn3_are_clock_states_equal +ffffffff81fe8a30 t dcn3_notify_wm_ranges +ffffffff81fe8cc0 t dcn30_notify_link_rate_change +ffffffff81fe8de0 t dcn3_set_hard_min_memclk +ffffffff81fe8e80 t dcn3_set_hard_max_memclk +ffffffff81fe8ee0 t dcn3_set_max_memclk +ffffffff81fe8f20 t dcn3_set_min_memclk +ffffffff81fe8f60 t dcn3_get_memclk_states_from_smu +ffffffff81fe90a0 t dcn3_is_smu_present +ffffffff81fea000 T dcn30_smu_test_message +ffffffff81fea070 t dcn30_smu_send_msg_with_param +ffffffff81fea1d0 T dcn30_smu_get_smu_version +ffffffff81fea1f0 T dcn30_smu_check_driver_if_version +ffffffff81fea240 T dcn30_smu_check_msg_header_version +ffffffff81fea290 T dcn30_smu_set_dram_addr_high +ffffffff81fea2b0 T dcn30_smu_set_dram_addr_low +ffffffff81fea2d0 T dcn30_smu_transfer_wm_table_smu_2_dram +ffffffff81fea2f0 T dcn30_smu_transfer_wm_table_dram_2_smu +ffffffff81fea310 T dcn30_smu_set_hard_min_by_freq +ffffffff81fea360 T dcn30_smu_set_hard_max_by_freq +ffffffff81fea3b0 T dcn30_smu_get_dpm_freq_by_index +ffffffff81fea400 T dcn30_smu_get_dc_mode_max_dpm_freq +ffffffff81fea450 T dcn30_smu_set_min_deep_sleep_dcef_clk +ffffffff81fea470 T dcn30_smu_set_num_of_displays +ffffffff81fea490 T dcn30_smu_set_display_refresh_from_mall +ffffffff81fea4c0 T dcn30_smu_set_external_client_df_cstate_allow +ffffffff81fea4e0 T dcn30_smu_set_pme_workaround +ffffffff81feb000 T dcn301_smu_get_smu_version +ffffffff81feb070 t dcn301_smu_send_msg_with_param +ffffffff81feb1f0 T dcn301_smu_set_dispclk +ffffffff81feb290 T dcn301_smu_set_dprefclk +ffffffff81feb340 T dcn301_smu_set_hard_min_dcfclk +ffffffff81feb3e0 T dcn301_smu_set_min_deep_sleep_dcfclk +ffffffff81feb480 T dcn301_smu_set_dppclk +ffffffff81feb520 T dcn301_smu_set_display_idle_optimization +ffffffff81feb570 T dcn301_smu_enable_phy_refclk_pwrdwn +ffffffff81feb5c0 T dcn301_smu_enable_pme_wa +ffffffff81feb5e0 T dcn301_smu_set_dram_addr_high +ffffffff81feb630 T dcn301_smu_set_dram_addr_low +ffffffff81feb680 T dcn301_smu_transfer_dpm_table_smu_2_dram +ffffffff81feb6a0 T dcn301_smu_transfer_wm_table_dram_2_smu +ffffffff81fec000 T vg_clk_mgr_construct +ffffffff81fec840 T vg_clk_mgr_destroy +ffffffff81fec890 t vg_update_clocks +ffffffff81fecbd0 t vg_init_clocks +ffffffff81fecc70 t vg_enable_pme_wa +ffffffff81fecc80 t vg_are_clock_states_equal +ffffffff81feccd0 t vg_notify_wm_ranges +ffffffff81fee000 T dcn31_update_clocks +ffffffff81fee610 T dcn31_init_clocks +ffffffff81fee6c0 T dcn31_are_clock_states_equal +ffffffff81fee720 T dcn31_get_dtb_ref_freq_khz +ffffffff81fee750 T dcn31_clk_mgr_construct +ffffffff81feee20 T dcn31_clk_mgr_destroy +ffffffff81feee70 t dcn31_set_low_power_state +ffffffff81fef080 t dcn31_enable_pme_wa +ffffffff81fef090 t dcn31_notify_wm_ranges +ffffffff81fef410 t find_clk_for_voltage +ffffffff81ff0000 T dcn31_smu_get_smu_version +ffffffff81ff0020 t dcn31_smu_send_msg_with_param +ffffffff81ff0230 T dcn31_smu_set_dispclk +ffffffff81ff02a0 T dcn31_smu_set_dprefclk +ffffffff81ff0310 T dcn31_smu_set_hard_min_dcfclk +ffffffff81ff0390 T dcn31_smu_set_min_deep_sleep_dcfclk +ffffffff81ff0410 T dcn31_smu_set_dppclk +ffffffff81ff0480 T dcn31_smu_set_display_idle_optimization +ffffffff81ff04d0 T dcn31_smu_enable_phy_refclk_pwrdwn +ffffffff81ff0520 T dcn31_smu_enable_pme_wa +ffffffff81ff0560 T dcn31_smu_set_dram_addr_high +ffffffff81ff05a0 T dcn31_smu_set_dram_addr_low +ffffffff81ff05e0 T dcn31_smu_transfer_dpm_table_smu_2_dram +ffffffff81ff0620 T dcn31_smu_transfer_wm_table_dram_2_smu +ffffffff81ff0660 T dcn31_smu_set_zstate_support +ffffffff81ff06d0 T dcn31_smu_set_dtbclk +ffffffff81ff1000 T dcn314_update_clocks +ffffffff81ff15d0 t dcn314_disable_otg_wa +ffffffff81ff1760 T dcn314_are_clock_states_equal +ffffffff81ff17c0 T dcn314_clk_mgr_construct +ffffffff81ff24d0 T dcn314_clk_mgr_destroy +ffffffff81ff2520 t dcn314_enable_pme_wa +ffffffff81ff2530 t dcn314_notify_wm_ranges +ffffffff81ff3000 T dcn314_smu_get_smu_version +ffffffff81ff3020 t dcn314_smu_send_msg_with_param +ffffffff81ff3250 T dcn314_smu_set_dispclk +ffffffff81ff32c0 T dcn314_smu_set_dprefclk +ffffffff81ff3330 T dcn314_smu_set_hard_min_dcfclk +ffffffff81ff33b0 T dcn314_smu_set_min_deep_sleep_dcfclk +ffffffff81ff3430 T dcn314_smu_set_dppclk +ffffffff81ff34a0 T dcn314_smu_set_display_idle_optimization +ffffffff81ff34f0 T dcn314_smu_enable_phy_refclk_pwrdwn +ffffffff81ff3540 T dcn314_smu_enable_pme_wa +ffffffff81ff3580 T dcn314_smu_set_dram_addr_high +ffffffff81ff35c0 T dcn314_smu_set_dram_addr_low +ffffffff81ff3600 T dcn314_smu_transfer_dpm_table_smu_2_dram +ffffffff81ff3640 T dcn314_smu_transfer_wm_table_dram_2_smu +ffffffff81ff3680 T dcn314_smu_set_zstate_support +ffffffff81ff36d0 T dcn314_smu_set_dtbclk +ffffffff81ff4000 T dcn315_clk_mgr_construct +ffffffff81ff4810 T dcn315_clk_mgr_destroy +ffffffff81ff4860 t dcn315_update_clocks +ffffffff81ff4da0 t dcn315_enable_pme_wa +ffffffff81ff4db0 t dcn315_notify_wm_ranges +ffffffff81ff5130 t dcn315_disable_otg_wa +ffffffff81ff6000 T dcn315_smu_get_smu_version +ffffffff81ff6020 t dcn315_smu_send_msg_with_param +ffffffff81ff6310 T dcn315_smu_set_dispclk +ffffffff81ff6380 T dcn315_smu_set_hard_min_dcfclk +ffffffff81ff6400 T dcn315_smu_set_min_deep_sleep_dcfclk +ffffffff81ff6480 T dcn315_smu_set_dppclk +ffffffff81ff64f0 T dcn315_smu_set_display_idle_optimization +ffffffff81ff6540 T dcn315_smu_enable_phy_refclk_pwrdwn +ffffffff81ff6590 T dcn315_smu_enable_pme_wa +ffffffff81ff65d0 T dcn315_smu_set_dram_addr_high +ffffffff81ff6610 T dcn315_smu_set_dram_addr_low +ffffffff81ff6650 T dcn315_smu_transfer_dpm_table_smu_2_dram +ffffffff81ff6690 T dcn315_smu_transfer_wm_table_dram_2_smu +ffffffff81ff66d0 T dcn315_smu_get_dpref_clk +ffffffff81ff6730 T dcn315_smu_get_dtbclk +ffffffff81ff6790 T dcn315_smu_set_dtbclk +ffffffff81ff7000 T dcn316_clk_mgr_construct +ffffffff81ff7650 T dcn316_clk_mgr_destroy +ffffffff81ff76a0 t dcn316_update_clocks +ffffffff81ff7c90 t dcn316_enable_pme_wa +ffffffff81ff7ca0 t dcn316_notify_wm_ranges +ffffffff81ff8020 t find_clk_for_voltage +ffffffff81ff9000 T dcn316_smu_get_smu_version +ffffffff81ff9020 t dcn316_smu_send_msg_with_param +ffffffff81ff91b0 T dcn316_smu_set_dispclk +ffffffff81ff9220 T dcn316_smu_set_hard_min_dcfclk +ffffffff81ff92a0 T dcn316_smu_set_min_deep_sleep_dcfclk +ffffffff81ff9320 T dcn316_smu_set_dppclk +ffffffff81ff9390 T dcn316_smu_set_display_idle_optimization +ffffffff81ff93e0 T dcn316_smu_enable_phy_refclk_pwrdwn +ffffffff81ff9430 T dcn316_smu_set_dram_addr_high +ffffffff81ff9470 T dcn316_smu_set_dram_addr_low +ffffffff81ff94b0 T dcn316_smu_transfer_dpm_table_smu_2_dram +ffffffff81ff94f0 T dcn316_smu_transfer_wm_table_dram_2_smu +ffffffff81ff9530 T dcn316_smu_enable_pme_wa +ffffffff81ff9570 T dcn316_smu_set_dtbclk +ffffffff81ff95b0 T dcn316_smu_get_dpref_clk +ffffffff81ff9610 T dcn316_smu_get_smu_fclk +ffffffff81ffa000 T dcn32_init_clocks +ffffffff81ffa560 T dcn32_update_clocks_update_dpp_dto +ffffffff81ffa6a0 T dcn32_clk_mgr_construct +ffffffff81ffa940 t dcn32_dump_clk_registers +ffffffff81ffab60 T dcn32_clk_mgr_destroy +ffffffff81ffabc0 t dcn32_update_clocks +ffffffff81ffb420 t dcn32_enable_pme_wa +ffffffff81ffb460 t dcn32_are_clock_states_equal +ffffffff81ffb4d0 t dcn32_notify_wm_ranges +ffffffff81ffb650 t dcn32_set_hard_min_memclk +ffffffff81ffb6e0 t dcn32_set_hard_max_memclk +ffffffff81ffb730 t dcn32_set_max_memclk +ffffffff81ffb770 t dcn32_set_min_memclk +ffffffff81ffb7b0 t dcn32_get_memclk_states_from_smu +ffffffff81ffba00 t dcn32_is_smu_present +ffffffff81ffba30 t dcn32_get_dispclk_from_dentist +ffffffff81ffbac0 t dcn32_update_clocks_update_dentist +ffffffff81ffc000 T dcn32_smu_send_fclk_pstate_message +ffffffff81ffc020 t dcn32_smu_send_msg_with_param +ffffffff81ffc160 T dcn32_smu_send_cab_for_uclk_message +ffffffff81ffc190 T dcn32_smu_transfer_wm_table_dram_2_smu +ffffffff81ffc1b0 T dcn32_smu_set_pme_workaround +ffffffff81ffc1d0 T dcn32_smu_set_hard_min_by_freq +ffffffff81ffc220 T dcn32_smu_wait_for_dmub_ack_mclk +ffffffff81ffd000 T dc_stream_adjust_vmin_vmax +ffffffff81ffd170 T dc_stream_get_last_used_drr_vtotal +ffffffff81ffd2d0 T dc_stream_get_crtc_position +ffffffff81ffd500 T dc_stream_configure_crc +ffffffff81ffd670 T dc_stream_get_crc +ffffffff81ffd750 T dc_stream_set_dyn_expansion +ffffffff81ffd9c0 T dc_stream_set_dither_option +ffffffff81ffdb60 T dc_stream_set_gamut_remap +ffffffff81ffdce0 T dc_stream_program_csc_matrix +ffffffff81ffdf00 T dc_stream_set_static_screen_params +ffffffff81ffe080 T dc_create +ffffffff81ffe600 t dc_construct_ctx +ffffffff81ffe770 t dc_destruct +ffffffff81ffea40 T dc_hardware_init +ffffffff81ffeb10 T dc_init_callbacks +ffffffff81ffeb60 T dc_deinit_callbacks +ffffffff81ffebb0 T dc_destroy +ffffffff81ffec00 T dc_validate_boot_timing +ffffffff81ffefa0 T dc_enable_stereo +ffffffff81fff0a0 T dc_trigger_sync +ffffffff81fff6d0 T dc_z10_restore +ffffffff81fff710 T dc_z10_save_init +ffffffff81fff750 T dc_commit_streams +ffffffff81fffc30 t commit_minimal_transition_state +ffffffff82000060 T dc_create_state +ffffffff820000f0 t dc_commit_state_no_check +ffffffff82001770 T dc_release_state +ffffffff820017d0 T dc_acquire_release_mpc_3dlut +ffffffff820018a0 T dc_post_update_surfaces_to_stream +ffffffff82001cb0 T dc_copy_state +ffffffff82001e80 T dc_retain_state +ffffffff82001eb0 T dc_set_generic_gpio_for_stereo +ffffffff82001fc0 T dc_check_update_surfaces_for_stream +ffffffff820029a0 T dc_dmub_update_dirty_rect +ffffffff82002bb0 T dc_update_planes_and_stream +ffffffff82003730 t fast_update_only +ffffffff82003a90 t commit_planes_for_stream_fast +ffffffff82003eb0 t commit_planes_for_stream +ffffffff82005430 T dc_commit_updates_for_stream +ffffffff82005a50 t copy_surface_update_to_plane +ffffffff82005e60 t copy_stream_update_to_stream +ffffffff82006500 T dc_get_current_stream_count +ffffffff82006540 T dc_get_stream_at_index +ffffffff82006590 T dc_interrupt_to_irq_source +ffffffff820065b0 T dc_interrupt_set +ffffffff82006600 T dc_interrupt_ack +ffffffff82006620 T dc_power_down_on_boot +ffffffff82006670 T dc_set_power_state +ffffffff82006850 T dc_resume +ffffffff820068d0 T dc_is_dmcu_initialized +ffffffff82006920 T get_clock_requirements_for_state +ffffffff820069a0 T dc_set_clock +ffffffff820069e0 T dc_get_clock +ffffffff82006a20 T dc_set_psr_allow_active +ffffffff82006b20 T dc_allow_idle_optimizations +ffffffff82006bc0 T dc_unlock_memory_clock_frequency +ffffffff82006c30 T dc_lock_memory_clock_frequency +ffffffff82006cc0 T dc_enable_dcmode_clk_limit +ffffffff82006e80 t blank_and_force_memclk +ffffffff82007060 T dc_is_plane_eligible_for_idle_optimizations +ffffffff820070b0 T dc_hardware_release +ffffffff82007100 T dc_mclk_switch_using_fw_based_vblank_stretch_shut_down +ffffffff82007140 T dc_is_dmub_outbox_supported +ffffffff820071b0 T dc_enable_dmub_notifications +ffffffff82007220 T dc_enable_dmub_outbox +ffffffff82007260 T dc_process_dmub_aux_transfer_async +ffffffff820073e0 T get_link_index_from_dpia_port_index +ffffffff82007490 T dc_process_dmub_set_config_async +ffffffff82007570 T dc_process_dmub_set_mst_slots +ffffffff82007660 T dc_process_dmub_dpia_hpd_int_enable +ffffffff82007720 T dc_print_dmub_diagnostic_data +ffffffff82007740 T dc_disable_accelerated_mode +ffffffff82007760 T dc_notify_vsync_int_state +ffffffff82007980 T dc_abm_save_restore +ffffffff82007b50 T dc_query_current_properties +ffffffff82007bc0 T dc_set_edp_power +ffffffff82007c30 t create_links +ffffffff82008090 t create_link_encoders +ffffffff82008170 t dc_update_viusal_confirm_color +ffffffff82009000 T pre_surface_trace +ffffffff82009030 T update_surface_trace +ffffffff82009060 T post_surface_trace +ffffffff82009090 T context_timing_trace +ffffffff82009240 T context_clock_trace +ffffffff82009270 T dc_status_to_str +ffffffff8200a000 T find_color_matrix +ffffffff8200a0b0 T color_space_to_black_color +ffffffff8200a120 T hwss_wait_for_blank_complete +ffffffff8200a1c0 T get_mpctree_visual_confirm_color +ffffffff8200a220 T get_surface_visual_confirm_color +ffffffff8200a2d0 T get_hdr_visual_confirm_color +ffffffff8200a390 T get_subvp_visual_confirm_color +ffffffff8200a490 T hwss_build_fast_sequence +ffffffff8200ab50 T hwss_execute_sequence +ffffffff8200af40 T hwss_setup_dpp +ffffffff8200afe0 T hwss_program_bias_and_scale +ffffffff8200b060 T hwss_program_manual_trigger +ffffffff8200b0b0 T hwss_power_on_mpc_mem_pwr +ffffffff8200b100 T hwss_set_output_csc +ffffffff8200b150 T hwss_set_ocsc_default +ffffffff8200b1a0 T hwss_send_dmcub_cmd +ffffffff8200b1c0 T get_mclk_switch_visual_confirm_color +ffffffff8200b320 T get_surface_tile_visual_confirm_color +ffffffff8200c000 T link_enc_cfg_init +ffffffff8200c1b0 T link_enc_cfg_copy +ffffffff8200c1e0 T link_enc_cfg_link_encs_assign +ffffffff8200d5a0 T link_enc_cfg_validate +ffffffff8200dd40 T link_enc_cfg_link_enc_unassign +ffffffff8200ded0 T link_enc_cfg_is_transmitter_mappable +ffffffff8200dff0 T link_enc_cfg_get_stream_using_link_enc +ffffffff8200e0f0 T link_enc_cfg_get_link_using_link_enc +ffffffff8200e200 T link_enc_cfg_get_link_enc_used_by_link +ffffffff8200e380 T link_enc_cfg_get_next_avail_link_enc +ffffffff8200e4f0 T link_enc_cfg_get_link_enc_used_by_stream +ffffffff8200e510 T link_enc_cfg_get_link_enc +ffffffff8200e5a0 T link_enc_cfg_get_link_enc_used_by_stream_current +ffffffff8200e720 T link_enc_cfg_is_link_enc_avail +ffffffff8200e920 T link_enc_cfg_set_transient_mode +ffffffff8200f000 T dc_get_link_at_index +ffffffff8200f030 T dc_get_edp_links +ffffffff8200f0b0 T dc_get_edp_link_panel_inst +ffffffff8200f170 T dc_link_detect +ffffffff8200f1a0 T dc_link_detect_connection_type +ffffffff8200f1d0 T dc_link_get_status +ffffffff8200f200 T dc_link_is_hdcp14 +ffffffff8200f230 T dc_link_is_hdcp22 +ffffffff8200f260 T dc_link_clear_dprx_states +ffffffff8200f290 T dc_link_reset_cur_dp_mst_topology +ffffffff8200f2c0 T dc_link_bandwidth_kbps +ffffffff8200f2f0 T dc_get_cur_link_res_map +ffffffff8200f310 T dc_restore_link_res_map +ffffffff8200f330 T dc_link_update_dsc_config +ffffffff8200f360 T dc_is_oem_i2c_device_present +ffffffff8200f3b0 T dc_submit_i2c +ffffffff8200f3e0 T dc_submit_i2c_oem +ffffffff8200f430 T dc_link_dp_handle_automated_test +ffffffff8200f460 T dc_link_dp_set_test_pattern +ffffffff8200f490 T dc_link_set_drive_settings +ffffffff8200f520 T dc_link_set_preferred_link_settings +ffffffff8200f540 T dc_link_set_preferred_training_settings +ffffffff8200f570 T dc_dp_trace_is_initialized +ffffffff8200f5a0 T dc_dp_trace_set_is_logged_flag +ffffffff8200f5d0 T dc_dp_trace_is_logged +ffffffff8200f600 T dc_dp_trace_get_lt_end_timestamp +ffffffff8200f630 T dc_dp_trace_get_lt_counts +ffffffff8200f660 T dc_dp_trace_get_link_loss_count +ffffffff8200f690 T dc_link_add_remote_sink +ffffffff8200f6c0 T dc_link_remove_remote_sink +ffffffff8200f6f0 T dc_link_aux_transfer_raw +ffffffff8200f720 T dc_link_bw_kbps_from_raw_frl_link_rate_data +ffffffff8200f740 T dc_link_decide_edp_link_settings +ffffffff8200f770 T dc_link_dp_get_max_link_enc_cap +ffffffff8200f7a0 T dc_link_dp_mst_decide_link_encoding_format +ffffffff8200f7d0 T dc_link_get_link_cap +ffffffff8200f800 T dc_link_get_highest_encoding_format +ffffffff8200f8c0 T dc_link_is_dp_sink_present +ffffffff8200f8f0 T dc_link_is_fec_supported +ffffffff8200f920 T dc_link_overwrite_extended_receiver_cap +ffffffff8200f950 T dc_link_should_enable_fec +ffffffff8200f980 T dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link +ffffffff8200f9b0 T dc_link_handle_usb4_bw_alloc_response +ffffffff8200f9e0 T dc_link_check_link_loss_status +ffffffff8200fa10 T dc_link_dp_allow_hpd_rx_irq +ffffffff8200fa40 T dc_link_dp_handle_link_loss +ffffffff8200fa70 T dc_link_dp_read_hpd_rx_irq_data +ffffffff8200faa0 T dc_link_handle_hpd_rx_irq +ffffffff8200fad0 T dc_link_dp_receiver_power_ctrl +ffffffff8200fb00 T dc_link_decide_lttpr_mode +ffffffff8200fb30 T dc_link_edp_panel_backlight_power_on +ffffffff8200fb60 T dc_link_get_backlight_level +ffffffff8200fb90 T dc_link_get_backlight_level_nits +ffffffff8200fbc0 T dc_link_set_backlight_level +ffffffff8200fbf0 T dc_link_set_backlight_level_nits +ffffffff8200fc20 T dc_link_get_target_backlight_pwm +ffffffff8200fc50 T dc_link_get_psr_state +ffffffff8200fc80 T dc_link_set_psr_allow_active +ffffffff8200fcb0 T dc_link_setup_psr +ffffffff8200fce0 T dc_link_get_replay_state +ffffffff8200fd10 T dc_link_wait_for_t12 +ffffffff8200fd40 T dc_link_get_hpd_state +ffffffff8200fd70 T dc_link_enable_hpd +ffffffff8200fda0 T dc_link_disable_hpd +ffffffff8200fdd0 T dc_link_enable_hpd_filter +ffffffff8200fe00 T dc_link_validate +ffffffff82010000 T resource_parse_asic_id +ffffffff82010250 T dc_create_resource_pool +ffffffff82010550 T dc_destroy_resource_pool +ffffffff820105c0 T resource_construct +ffffffff82010aa0 T resource_unreference_clock_source +ffffffff82010b20 T resource_reference_clock_source +ffffffff82010ba0 T resource_get_clock_source_reference +ffffffff82010c20 T resource_are_vblanks_synchronizable +ffffffff82010e40 T resource_are_streams_timing_synchronizable +ffffffff82010f30 T resource_find_used_clk_src_for_sharing +ffffffff82011060 T resource_get_num_mpc_splits +ffffffff820110f0 T resource_get_num_odm_splits +ffffffff820111b0 T resource_get_otg_master +ffffffff82011250 T resource_build_scaling_params +ffffffff82011fe0 t calculate_odm_slice_in_timing_active +ffffffff82012160 T resource_build_scaling_params_for_context +ffffffff820122b0 T resource_find_free_secondary_pipe_legacy +ffffffff82012350 T resource_find_free_pipe_used_in_cur_mpc_blending_tree +ffffffff820123c0 T resource_is_pipe_type +ffffffff82012440 T recource_find_free_pipe_not_used_in_cur_res_ctx +ffffffff820124c0 T resource_find_free_pipe_used_as_cur_sec_dpp_in_mpcc_combine +ffffffff820125e0 T resource_is_for_mpcc_combine +ffffffff82012670 T resource_find_any_free_pipe +ffffffff820126e0 T resource_get_otg_master_for_stream +ffffffff82012810 T resource_get_opp_head +ffffffff820128a0 T dc_add_plane_to_context +ffffffff82012b60 T dc_remove_plane_from_context +ffffffff82012d40 T dc_rem_all_planes_for_stream +ffffffff82012f00 T dc_add_all_planes_for_stream +ffffffff82013080 T dc_is_timing_changed +ffffffff820130e0 T dc_is_stream_unchanged +ffffffff820131c0 T dc_is_stream_scaling_unchanged +ffffffff82013260 T update_audio_usage +ffffffff820132d0 T dc_add_stream_to_ctx +ffffffff820133a0 T dc_remove_stream_from_ctx +ffffffff820137b0 T resource_map_pool_resources +ffffffff82014210 t acquire_first_split_pipe +ffffffff82014380 t add_hpo_dp_link_enc_to_ctx +ffffffff82014450 t find_first_free_audio +ffffffff82014500 T dc_resource_state_copy_construct_current +ffffffff82014520 T dc_resource_state_copy_construct +ffffffff820146c0 T dc_resource_state_construct +ffffffff820146e0 T dc_resource_is_dsc_encoding_supported +ffffffff82014730 T dc_validate_with_context +ffffffff82015360 t planes_changed_for_existing_stream +ffffffff820154e0 T dc_validate_global_state +ffffffff82015860 T dc_resource_state_destruct +ffffffff82015940 T dc_resource_find_first_free_pll +ffffffff820159b0 T resource_build_info_frame +ffffffff820160e0 T resource_map_clock_resources +ffffffff82016270 T pipe_need_reprogram +ffffffff820163e0 T resource_build_bit_depth_reduction_params +ffffffff82016610 T dc_validate_stream +ffffffff820167e0 T dc_validate_plane +ffffffff82016870 T resource_pixel_format_to_bpp +ffffffff820168f0 T get_audio_check +ffffffff82016a10 T get_temp_dp_link_res +ffffffff82016b20 T reset_syncd_pipes_from_disabled_pipes +ffffffff82016c70 T check_syncd_pipes_for_disabled_master_pipe +ffffffff82016db0 T reset_sync_context_for_pipe +ffffffff82016e60 T resource_transmitter_to_phy_idx +ffffffff82016ec0 T get_link_hwss +ffffffff82016f50 T is_h_timing_divisible_by_2 +ffffffff82016fb0 T dc_resource_acquire_secondary_pipe_for_mpc_odm +ffffffff820171c0 T update_dp_encoder_resources_for_test_harness +ffffffff82017480 t calculate_plane_rec_in_timing_active +ffffffff82017750 t calculate_init_and_vp +ffffffff82018000 T dc_sink_retain +ffffffff82018030 T dc_sink_release +ffffffff820180a0 T dc_sink_create +ffffffff82019000 T dc_stat_get_dmub_notification +ffffffff820190b0 T dc_stat_get_dmub_dataout +ffffffff8201a000 T update_stream_signal +ffffffff8201a080 T dc_stream_retain +ffffffff8201a0b0 T dc_stream_release +ffffffff8201a130 T dc_create_stream_for_sink +ffffffff8201a470 T dc_copy_stream +ffffffff8201a540 T dc_stream_get_status_from_state +ffffffff8201a5a0 T dc_stream_get_status +ffffffff8201a610 T dc_optimize_timing_for_fsft +ffffffff8201a660 T dc_stream_set_cursor_attributes +ffffffff8201a860 t program_cursor_attributes +ffffffff8201a9c0 T dc_stream_set_cursor_position +ffffffff8201aae0 t program_cursor_position +ffffffff8201ac20 T dc_stream_add_writeback +ffffffff8201ae30 T dc_stream_remove_writeback +ffffffff8201af60 T dc_stream_warmup_writeback +ffffffff8201afa0 T dc_stream_get_vblank_counter +ffffffff8201b070 T dc_stream_send_dp_sdp +ffffffff8201b300 T dc_stream_get_scanoutpos +ffffffff8201b3e0 T dc_stream_dmdata_status_done +ffffffff8201b4a0 T dc_stream_set_dynamic_metadata +ffffffff8201b600 T dc_stream_add_dsc_to_resource +ffffffff8201b650 T dc_stream_get_pipe_ctx +ffffffff8201b700 T dc_stream_log +ffffffff8201c000 T enable_surface_flip_reporting +ffffffff8201c030 T dc_create_plane_state +ffffffff8201c1d0 T dc_plane_get_status +ffffffff8201c350 T dc_plane_state_retain +ffffffff8201c380 T dc_plane_state_release +ffffffff8201c4d0 T dc_gamma_retain +ffffffff8201c500 T dc_gamma_release +ffffffff8201c560 T dc_create_gamma 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dc_dmub_srv_is_restore_required +ffffffff8201eae0 T dc_dmub_srv_get_dmub_outbox0_msg +ffffffff8201eb10 T dc_dmub_trace_event_control +ffffffff8201eb30 T dc_dmub_srv_drr_update_cmd +ffffffff8201ebc0 T dc_dmub_srv_set_drr_manual_trigger_cmd +ffffffff8201ec50 T dc_dmub_srv_p_state_delegate +ffffffff8201f000 T dc_dmub_srv_query_caps_cmd +ffffffff8201f0c0 T dc_dmub_srv_get_visual_confirm_color_cmd +ffffffff8201f1a0 T dc_dmub_setup_subvp_dmub_command +ffffffff8201fbb0 T dc_dmub_srv_get_diagnostic_data +ffffffff8201fbf0 T dc_send_update_cursor_info_to_dmu +ffffffff8201ff60 T dc_dmub_check_min_version +ffffffff8201ffa0 T dc_dmub_srv_enable_dpia_trace +ffffffff82021000 T dc_edid_parser_send_cea +ffffffff820210b0 T dc_edid_parser_recv_cea_ack +ffffffff82021140 T dc_edid_parser_recv_amd_vsdb +ffffffff82022000 T generic_reg_update_ex +ffffffff82022330 t set_reg_field_values +ffffffff820224e0 T generic_reg_set_ex +ffffffff820226d0 T generic_reg_get +ffffffff82022740 T generic_reg_get2 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dce_abm_set_backlight_level_pwm +ffffffff82024810 t dce_abm_get_current_backlight +ffffffff82024840 t dce_abm_get_target_backlight +ffffffff82025000 T dce_aud_az_enable +ffffffff82025150 T dce_aud_az_disable +ffffffff82025340 T dce_aud_az_configure +ffffffff82025fc0 t check_audio_bandwidth +ffffffff82026150 T dce_aud_wall_dto_setup +ffffffff820262d0 T dce_aud_hw_init +ffffffff820264a0 T dce_aud_destroy +ffffffff820264f0 T dce_audio_create +ffffffff820265b0 t dce_aud_endpoint_valid +ffffffff82027000 T dce110_engine_destroy +ffffffff82027050 T dce110_aux_engine_construct +ffffffff820270d0 t dce_aux_configure_timeout +ffffffff820272b0 T dce_aux_transfer_raw +ffffffff82027ae0 t acquire +ffffffff82027d50 T dce_aux_transfer_dmub_raw +ffffffff82027e50 T dce_aux_transfer_with_retries +ffffffff82029000 T look_up_in_video_optimized_rate_tlb +ffffffff82029070 T dce110_clk_src_construct +ffffffff82029270 t calc_pll_max_vco_construct +ffffffff82029410 T dce112_clk_src_construct +ffffffff820294a0 T dcn20_clk_src_construct +ffffffff82029550 T dcn3_clk_src_construct +ffffffff82029600 T dcn31_clk_src_construct +ffffffff820296b0 T dcn301_clk_src_construct +ffffffff82029760 t dce110_clock_source_power_down +ffffffff820297f0 t dce110_program_pix_clk +ffffffff82029e80 t dce110_get_pix_clk_dividers +ffffffff8202a500 t get_pixel_clk_frequency_100hz +ffffffff8202a610 t get_ss_info_from_atombios +ffffffff8202a8e0 t dce112_program_pix_clk +ffffffff8202aaf0 t dce112_get_pix_clk_dividers +ffffffff8202ac00 t dcn20_program_pix_clk +ffffffff8202ac90 t dcn20_override_dp_pix_clk +ffffffff8202ad80 t dcn3_program_pix_clk +ffffffff8202af30 t dcn3_get_pix_clk_dividers +ffffffff8202b000 t dcn31_program_pix_clk +ffffffff8202c000 T dce_dmcu_create +ffffffff8202c0c0 T dcn10_dmcu_create +ffffffff8202c180 T dcn20_dmcu_create +ffffffff8202c240 T dcn21_dmcu_create +ffffffff8202c330 T dce_dmcu_destroy +ffffffff8202c380 t dce_dmcu_init +ffffffff8202c3b0 t dce_dmcu_load_iram +ffffffff8202c510 t dce_dmcu_set_psr_enable +ffffffff8202c640 t dce_dmcu_setup_psr +ffffffff8202c970 t dce_get_dmcu_psr_state +ffffffff8202ca50 t dce_psr_wait_loop +ffffffff8202cb80 t dce_get_psr_wait_loop +ffffffff8202cbb0 t dce_is_dmcu_initialized +ffffffff8202cc10 t dcn10_dmcu_init +ffffffff8202d150 t dcn10_dmcu_load_iram +ffffffff8202d390 t dcn10_dmcu_set_psr_enable +ffffffff8202d520 t dcn10_dmcu_setup_psr +ffffffff8202d8e0 t dcn10_get_dmcu_psr_state +ffffffff8202da00 t dcn10_psr_wait_loop +ffffffff8202db10 t dcn10_get_psr_wait_loop +ffffffff8202db40 t dcn10_is_dmcu_initialized +ffffffff8202db70 t dcn10_send_edid_cea +ffffffff8202dd10 t dcn10_recv_amd_vsdb +ffffffff8202ddc0 t dcn10_recv_edid_cea_ack +ffffffff8202de40 t dcn10_get_scp_results +ffffffff8202df60 t dcn20_lock_phy +ffffffff8202e090 t dcn20_unlock_phy +ffffffff8202e1c0 t dcn21_dmcu_init +ffffffff8202f000 T dce_enable_fe_clock +ffffffff8202f040 T dce_pipe_control_lock +ffffffff8202f240 T dce_set_blender_mode +ffffffff8202f350 T dce_clock_gating_power_up +ffffffff8202f3f0 T dce_crtc_switch_to_clk_src +ffffffff8202f5b0 T dce_use_lut +ffffffff82030000 T dce_i2c_oem_device_present +ffffffff82030080 T dce_i2c_submit_command +ffffffff82031000 T acquire_i2c_hw_engine +ffffffff820313a0 T dce_i2c_submit_command_hw +ffffffff82031ce0 t set_speed +ffffffff82031e30 T dce_i2c_hw_construct +ffffffff82031ea0 T dce100_i2c_hw_construct +ffffffff82031f10 T dce112_i2c_hw_construct +ffffffff82031f80 T dcn1_i2c_hw_construct +ffffffff82031ff0 T dcn2_i2c_hw_construct +ffffffff82032080 t is_hw_busy +ffffffff82033000 T dce_i2c_sw_construct +ffffffff82033030 T dce_i2c_engine_acquire_sw +ffffffff820330d0 T dce_i2c_submit_command_sw +ffffffff820338a0 t write_byte_sw +ffffffff82034000 T dce_ipp_construct +ffffffff82034050 T dce_ipp_destroy +ffffffff820340a0 t dce_ipp_cursor_set_position +ffffffff820341d0 t dce_ipp_cursor_set_attributes +ffffffff82034460 t dce_ipp_program_prescale +ffffffff82034620 t dce_ipp_program_input_lut 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dce110_stream_encoder_update_hdmi_info_packets +ffffffff82040190 t dce110_stream_encoder_stop_hdmi_info_packets +ffffffff82040430 t dce110_stream_encoder_update_dp_info_packets +ffffffff820405c0 t dce110_stream_encoder_stop_dp_info_packets +ffffffff82040730 t dce110_stream_encoder_dp_blank +ffffffff82040870 t dce110_stream_encoder_dp_unblank +ffffffff82040a30 t setup_stereo_sync +ffffffff82040ab0 t dce110_stream_encoder_set_avmute +ffffffff82040af0 t dig_connect_to_otg +ffffffff82040b30 t dce110_reset_hdmi_stream_attribute +ffffffff82040c30 t dig_source_otg +ffffffff82040ca0 t dce110_stream_encoder_set_stream_attribute_helper +ffffffff82040d90 t dce110_update_generic_info_packet +ffffffff82042000 T dce_transform_get_optimal_number_of_taps +ffffffff82042300 T dce110_opp_set_csc_adjustment +ffffffff820423c0 t program_color_matrix +ffffffff820425f0 T dce110_opp_set_csc_default +ffffffff82042730 T dce110_opp_program_regamma_pwl +ffffffff82042fe0 T dce110_opp_power_on_regamma_lut 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dce110_resource_build_pipe_hw_param +ffffffff82059150 T dce110_find_first_free_match_stream_enc_for_link +ffffffff820591f0 T dce110_create_resource_pool +ffffffff8205a190 t dce110_resource_destruct +ffffffff8205a4b0 t dce110_destroy_resource_pool +ffffffff8205a510 t dce110_panel_cntl_create +ffffffff8205a5a0 t dce110_link_encoder_create +ffffffff8205a6a0 t dce110_validate_bandwidth +ffffffff8205a790 t dce110_validate_global +ffffffff8205a870 t dce110_acquire_underlay +ffffffff8205aa50 t dce110_validate_plane +ffffffff8205aab0 t dce110_add_stream_to_ctx +ffffffff8205ab80 t read_dce_straps +ffffffff8205abf0 t create_audio +ffffffff8205ac20 t dce110_stream_encoder_create +ffffffff8205acc0 t dce110_hwseq_create +ffffffff8205b000 T dce110_timing_generator_set_early_control +ffffffff8205b070 T dce110_timing_generator_enable_crtc +ffffffff8205b100 T dce110_timing_generator_program_blank_color +ffffffff8205b190 T dce110_timing_generator_disable_crtc +ffffffff8205b1e0 T dce110_timing_generator_program_timing_generator +ffffffff8205b3d0 T dce110_timing_generator_set_drr +ffffffff8205b510 T dce110_timing_generator_set_static_screen_control +ffffffff8205b5a0 T dce110_timing_generator_get_vblank_counter +ffffffff8205b600 T dce110_timing_generator_get_position +ffffffff8205b6a0 T dce110_timing_generator_get_crtc_scanoutpos +ffffffff8205b790 T dce110_timing_generator_program_blanking +ffffffff8205ba00 T dce110_timing_generator_set_test_pattern +ffffffff8205bcf0 T dce110_timing_generator_validate_timing +ffffffff8205bdb0 T dce110_timing_generator_wait_for_vblank +ffffffff8205bf20 T dce110_timing_generator_is_counter_moving +ffffffff8205bfa0 T dce110_timing_generator_wait_for_vactive +ffffffff8205c080 T dce110_timing_generator_setup_global_swap_lock +ffffffff8205c1e0 T dce110_timing_generator_tear_down_global_swap_lock +ffffffff8205c260 T dce110_timing_generator_enable_advanced_request +ffffffff8205c300 T dce110_timing_generator_set_lock_master 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dce112_compressor_program_compressed_surface_address_and_pitch +ffffffff82060b40 T dce112_compressor_program_lpt_control +ffffffff82060db0 T dce112_compressor_set_fbc_invalidation_triggers +ffffffff82060e40 T dce112_compressor_construct +ffffffff82060f00 T dce112_compressor_create +ffffffff82060ff0 T dce112_compressor_destroy +ffffffff82062000 T dce112_hw_sequencer_construct +ffffffff82062050 t dce112_enable_display_power_gating +ffffffff82063000 T dce112_validate_bandwidth +ffffffff820630c0 T resource_map_phy_clock_resources +ffffffff82063230 T dce112_add_stream_to_ctx +ffffffff820632d0 T dce112_create_resource_pool +ffffffff82064620 t dce112_resource_destruct +ffffffff820648e0 t dce112_destroy_resource_pool +ffffffff82064940 t dce112_panel_cntl_create +ffffffff820649d0 t dce112_link_encoder_create +ffffffff82064ad0 t dce112_validate_global +ffffffff82064b70 t read_dce_straps +ffffffff82064be0 t create_audio +ffffffff82064c10 t dce112_stream_encoder_create +ffffffff82064cb0 t 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hubp1_vready_workaround +ffffffff8207b1f0 T hubp1_program_tiling +ffffffff8207b450 T hubp1_program_size +ffffffff8207b5d0 T hubp1_program_rotation +ffffffff8207b740 T hubp1_program_pixel_format +ffffffff8207bd10 T hubp1_program_surface_flip_and_addr +ffffffff8207c590 T hubp1_dcc_control +ffffffff8207c650 T hubp1_program_surface_config +ffffffff8207c760 T hubp1_program_requestor +ffffffff8207cb30 T hubp1_program_deadline +ffffffff8207d240 T hubp1_is_flip_pending +ffffffff8207d350 T min_set_viewport +ffffffff8207d650 T hubp1_read_state_common +ffffffff8207e340 T hubp1_read_state +ffffffff8207e610 T hubp1_get_cursor_pitch +ffffffff8207e6b0 T hubp1_cursor_set_attributes +ffffffff8207e960 T hubp1_cursor_set_position +ffffffff8207ecc0 T hubp1_clk_cntl +ffffffff8207ed10 T hubp1_vtg_sel +ffffffff8207ed50 T hubp1_in_blank +ffffffff8207edc0 T hubp1_soft_reset +ffffffff8207ee00 T hubp1_set_flip_int +ffffffff8207ee50 T hubp1_init +ffffffff8207ee80 T dcn10_hubp_construct +ffffffff8207eef0 t hubp1_setup +ffffffff8207efb0 t hubp1_setup_interdependent +ffffffff8207f330 t hubp1_set_vm_system_aperture_settings +ffffffff8207f550 t hubp1_set_vm_context0_settings +ffffffff8207f830 t hubp1_set_hubp_blank_en +ffffffff8207f870 t hubp1_disconnect +ffffffff8207f900 t hubp1_disable_control +ffffffff8207f940 t hubp1_get_underflow_status +ffffffff8207f9b0 t hubp1_wait_pipe_read_start +ffffffff82080000 T dcn10_lock_all_pipes +ffffffff82080130 T dcn10_log_hw_state +ffffffff82081c10 T dcn10_did_underflow_occur +ffffffff82081cb0 T dcn10_enable_power_gating_plane +ffffffff82081e50 T dcn10_disable_vga +ffffffff82082040 T dcn10_dpp_pg_control +ffffffff82082290 T dcn10_hubp_pg_control +ffffffff820824e0 T dcn10_bios_golden_init +ffffffff82082640 T dcn10_enable_stream_timing +ffffffff82082a40 T dcn10_verify_allow_pstate_change_high +ffffffff82082d90 T dcn10_plane_atomic_disconnect +ffffffff82082ec0 T dcn10_plane_atomic_power_down +ffffffff82083020 T dcn10_plane_atomic_disable +ffffffff82083160 T dcn10_disable_plane +ffffffff82083300 T dcn10_init_pipes +ffffffff820839c0 T dcn10_init_hw +ffffffff82083eb0 T dcn10_power_down_on_boot +ffffffff82084000 T dcn10_reset_hw_ctx_wrap +ffffffff82084340 T dcn10_update_plane_addr +ffffffff82084460 T dcn10_set_input_transfer_func +ffffffff820845d0 T dcn10_set_output_transfer_func +ffffffff820846a0 T dcn10_pipe_control_lock +ffffffff82084770 T dcn10_cursor_lock +ffffffff82084930 T dcn10_enable_vblanks_synchronization +ffffffff82085110 T dcn10_enable_timing_synchronization +ffffffff82085510 T dcn10_enable_per_frame_crtc_position_reset +ffffffff820856e0 T dcn10_program_gamut_remap +ffffffff820858e0 T dcn10_program_output_csc +ffffffff82085a10 T dcn10_update_visual_confirm_color +ffffffff82085a90 T dcn10_update_mpcc +ffffffff82085d40 T dcn10_blank_pixel_data +ffffffff82085e80 T dcn10_set_hdr_multiplier +ffffffff82085f10 T dcn10_program_pipe +ffffffff82086ab0 T dcn10_wait_for_pending_cleared +ffffffff82086bb0 T dcn10_post_unlock_program_front_end +ffffffff82086e50 T dcn10_prepare_bandwidth +ffffffff82086ff0 T dcn10_optimize_bandwidth +ffffffff82087190 T dcn10_set_drr +ffffffff82087290 T dcn10_get_position +ffffffff82087320 T dcn10_set_static_screen_control +ffffffff820873c0 T dcn10_setup_stereo +ffffffff82087510 T dcn10_wait_for_mpcc_disconnect +ffffffff820876c0 T dcn10_dummy_display_power_gating +ffffffff820876f0 T dcn10_update_pending_status +ffffffff82087830 T dcn10_update_dchub +ffffffff82087860 T dcn10_set_cursor_position +ffffffff82087da0 T dcn10_set_cursor_attribute +ffffffff82087df0 T dcn10_set_cursor_sdr_white_level +ffffffff82087eb0 T dcn10_get_vupdate_offset_from_vsync +ffffffff82087f40 T dcn10_calc_vupdate_position +ffffffff82087fd0 T dcn10_setup_periodic_interrupt +ffffffff820880e0 T dcn10_setup_vupdate_interrupt +ffffffff820881a0 T dcn10_unblank_stream +ffffffff820882b0 T dcn10_send_immediate_sdp_message +ffffffff82088310 T dcn10_set_clock +ffffffff82088420 T dcn10_get_clock +ffffffff82088480 T dcn10_get_dcc_en_bits +ffffffff82089000 T snprintf_count +ffffffff82089090 T dcn10_clear_status_bits +ffffffff82089240 T dcn10_get_hw_state +ffffffff8208b000 T dcn10_hw_sequencer_construct +ffffffff8208c000 T dcn10_ipp_construct +ffffffff8208c050 T dcn20_ipp_construct +ffffffff8208c0a0 t dcn10_ipp_destroy +ffffffff8208d000 T dcn10_link_encoder_set_dp_phy_pattern_training_pattern +ffffffff8208d0b0 T dcn10_get_dig_frontend +ffffffff8208d170 T enc1_configure_encoder +ffffffff8208d1f0 T dcn10_psr_program_dp_dphy_fast_training +ffffffff8208d270 T dcn10_psr_program_secondary_packet +ffffffff8208d2f0 T dcn10_is_dig_enabled +ffffffff8208d350 T dcn10_link_encoder_validate_dvi_output +ffffffff8208d400 T dcn10_link_encoder_validate_dp_output +ffffffff8208d440 T dcn10_link_encoder_construct +ffffffff8208d620 T dcn10_link_encoder_validate_output_with_stream +ffffffff8208d820 T dcn10_link_encoder_hw_init +ffffffff8208da20 T dcn10_aux_initialize +ffffffff8208dab0 T dcn10_link_encoder_destroy +ffffffff8208db00 T dcn10_link_encoder_setup +ffffffff8208dc50 T dcn10_link_encoder_enable_tmds_output +ffffffff8208dd40 T dcn10_link_encoder_enable_tmds_output_with_clk_pattern_wa +ffffffff8208de60 T dcn10_link_encoder_enable_dp_output +ffffffff8208dfc0 T dcn10_link_encoder_enable_dp_mst_output +ffffffff8208e120 T dcn10_link_encoder_disable_output +ffffffff8208e2f0 T dcn10_link_encoder_dp_set_lane_settings +ffffffff8208e490 T dcn10_link_encoder_dp_set_phy_pattern +ffffffff8208ebb0 t set_dp_phy_pattern_hbr2_compliance_cp2520_2 +ffffffff8208edb0 T dcn10_link_encoder_update_mst_stream_allocation_table +ffffffff8208f080 T dcn10_link_encoder_connect_dig_be_to_fe +ffffffff8208f1c0 T dcn10_link_encoder_enable_hpd +ffffffff8208f200 T dcn10_link_encoder_disable_hpd +ffffffff8208f240 T dcn10_get_dig_mode +ffffffff8208f2b0 T dcn10_link_encoder_get_max_link_cap +ffffffff8208f330 t program_pattern_symbols +ffffffff82090000 T mpc1_set_bg_color +ffffffff820901e0 T mpc1_get_mpcc +ffffffff82090270 T mpc1_update_stereo_mix +ffffffff82090390 T mpc1_assert_idle_mpcc +ffffffff82090460 T mpc1_get_mpcc_for_dpp +ffffffff82090510 T mpc1_is_mpcc_idle +ffffffff82090600 T mpc1_assert_mpcc_idle_before_connect +ffffffff82090740 T mpc1_insert_plane +ffffffff82090ce0 T mpc1_remove_mpcc +ffffffff820910a0 T mpc1_mpc_init +ffffffff820913c0 T mpc1_mpc_init_single_inst +ffffffff820915b0 T mpc1_init_mpcc_list_from_hw +ffffffff82091880 T mpc1_read_mpcc_state +ffffffff82091a10 T mpc1_cursor_lock +ffffffff82091a90 T mpc1_get_mpc_out_mux +ffffffff82091b10 T dcn10_mpc_construct +ffffffff82091c90 t mpc1_update_blending +ffffffff82092000 T opp1_program_bit_depth_reduction +ffffffff82092400 T opp1_set_dyn_expansion +ffffffff82092570 T opp1_program_fmt +ffffffff82092870 T opp1_program_stereo +ffffffff82092960 T opp1_pipe_clock_control +ffffffff820929a0 T opp1_destroy +ffffffff820929f0 T dcn10_opp_construct +ffffffff82093000 T optc1_program_global_sync +ffffffff82093150 T optc1_setup_vertical_interrupt0 +ffffffff820931e0 T optc1_setup_vertical_interrupt1 +ffffffff82093250 T optc1_setup_vertical_interrupt2 +ffffffff820932c0 T optc1_program_timing +ffffffff820939a0 T optc1_is_two_pixels_per_containter +ffffffff820939f0 T optc1_set_vtg_params +ffffffff82093b20 T optc1_set_blank_data_double_buffer +ffffffff82093b60 T optc1_set_timing_double_buffer +ffffffff82093ba0 T optc1_set_blank +ffffffff82093c70 T optc1_is_blanked +ffffffff82093cf0 T optc1_enable_optc_clock +ffffffff82093f10 T optc1_disable_crtc +ffffffff82094000 T optc1_program_blank_color +ffffffff820940b0 T optc1_validate_timing +ffffffff820941b0 T optc1_get_vblank_counter +ffffffff82094210 T optc1_lock +ffffffff820942f0 T optc1_unlock +ffffffff82094360 T optc1_get_position +ffffffff820943f0 T optc1_is_counter_moving +ffffffff82094470 T optc1_did_triggered_reset_occur +ffffffff82094510 T optc1_disable_reset_trigger +ffffffff820945d0 T optc1_enable_reset_trigger +ffffffff820946e0 T optc1_enable_crtc_reset +ffffffff82094840 T optc1_wait_for_state +ffffffff82094910 T optc1_set_early_control +ffffffff82094940 T optc1_set_static_screen_control +ffffffff820949e0 T optc1_set_drr +ffffffff82094b80 T optc1_set_vtotal_min_max +ffffffff82094c20 T optc1_get_crtc_scanoutpos +ffffffff82094d30 T optc1_program_stereo +ffffffff82094f40 T optc1_is_stereo_left_eye +ffffffff82094fb0 T optc1_get_hw_timing +ffffffff820950c0 T optc1_read_otg_state +ffffffff820953d0 T optc1_get_otg_active_size +ffffffff820954e0 T optc1_clear_optc_underflow +ffffffff82095530 T optc1_tg_init +ffffffff820955e0 T optc1_is_tg_enabled +ffffffff82095650 T optc1_is_optc_underflow_occurred +ffffffff820956c0 T optc1_configure_crc +ffffffff82095930 T optc1_get_crc +ffffffff82095a30 T dcn10_timing_generator_init +ffffffff82095aa0 t optc1_enable_crtc +ffffffff82095ba0 t optc1_set_test_pattern +ffffffff82096290 t optc1_program_manual_trigger +ffffffff82096340 t optc1_setup_manual_trigger +ffffffff82097000 T dcn10_find_first_free_match_stream_enc_for_link +ffffffff820970b0 T dcn10_create_resource_pool +ffffffff82098230 t dcn10_resource_destruct +ffffffff82098540 t dcn10_destroy_resource_pool +ffffffff820985a0 t dcn10_panel_cntl_create +ffffffff82098630 t dcn10_link_encoder_create +ffffffff82098730 t dcn10_validate_bandwidth +ffffffff820987b0 t dcn10_validate_global +ffffffff82098990 t dcn10_acquire_free_pipe_for_layer +ffffffff82098ac0 t dcn10_validate_plane +ffffffff82098b10 t dcn10_add_stream_to_ctx +ffffffff82098ce0 t dcn10_patch_unknown_plane_state +ffffffff82098d40 t read_dce_straps +ffffffff82098d70 t create_audio +ffffffff82098da0 t dcn10_stream_encoder_create +ffffffff82098e40 t dcn10_hwseq_create +ffffffff82098ef0 t dcn10_get_dcc_compression_cap +ffffffff82099000 T enc1_update_generic_info_packet +ffffffff82099430 T enc1_stream_encoder_dp_set_stream_attribute +ffffffff82099910 T enc1_stream_encoder_set_stream_attribute_helper +ffffffff82099990 T enc1_stream_encoder_hdmi_set_stream_attribute +ffffffff82099f80 T enc1_stream_encoder_dvi_set_stream_attribute +ffffffff8209a110 T enc1_stream_encoder_set_throttled_vcp_size +ffffffff8209a330 T enc1_stream_encoder_update_dp_info_packets +ffffffff8209a530 T enc1_stream_encoder_send_immediate_sdp_message +ffffffff8209a940 T enc1_stream_encoder_stop_dp_info_packets +ffffffff8209ab10 T enc1_stream_encoder_dp_blank +ffffffff8209acb0 T enc1_stream_encoder_dp_unblank +ffffffff8209aee0 T enc1_stream_encoder_set_avmute +ffffffff8209af20 T enc1_reset_hdmi_stream_attribute +ffffffff8209aff0 T get_audio_clock_info +ffffffff8209b0e0 T enc1_se_enable_audio_clock +ffffffff8209b140 T enc1_se_enable_dp_audio +ffffffff8209b210 T enc1_se_audio_mute_control +ffffffff8209b260 T enc1_se_dp_audio_setup +ffffffff8209b270 t enc1_se_audio_setup +ffffffff8209b3d0 T enc1_se_dp_audio_enable +ffffffff8209b620 T enc1_se_dp_audio_disable +ffffffff8209b790 T enc1_se_hdmi_audio_setup +ffffffff8209bc50 T enc1_se_hdmi_audio_disable +ffffffff8209bce0 T enc1_setup_stereo_sync +ffffffff8209bd60 T enc1_dig_connect_to_otg +ffffffff8209bda0 T enc1_dig_source_otg +ffffffff8209be10 T enc1_stream_encoder_dp_get_pixel_format +ffffffff8209bf00 T dcn10_stream_encoder_construct +ffffffff8209bf60 t enc1_stream_encoder_update_hdmi_info_packets +ffffffff8209c310 t enc1_stream_encoder_stop_hdmi_info_packets +ffffffff8209d000 T dccg2_update_dpp_dto +ffffffff8209d160 T dccg2_get_dccg_ref_freq +ffffffff8209d220 T dccg2_set_fifo_errdet_ovr_en +ffffffff8209d260 T dccg2_otg_add_pixel +ffffffff8209d300 T dccg2_otg_drop_pixel +ffffffff8209d3a0 T dccg2_init +ffffffff8209d3d0 T dccg2_create +ffffffff8209d480 T dcn_dccg_destroy +ffffffff8209e000 T dpp20_read_state +ffffffff8209e1d0 T dpp2_power_on_obuf +ffffffff8209e2a0 T dpp2_dummy_program_input_lut +ffffffff8209e2d0 T dscl2_calc_lb_num_partitions +ffffffff8209e400 T dpp2_cnv_set_alpha_keyer +ffffffff8209e680 T dpp2_set_cursor_attributes +ffffffff8209e7e0 T oppn20_dummy_program_regamma_pwl +ffffffff8209e810 T dpp2_construct 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+ffffffff820aac00 T hubbub2_get_dchub_ref_freq +ffffffff820aace0 T hubbub2_read_state +ffffffff820aaeb0 T hubbub2_construct +ffffffff820aaf10 t hubbub2_program_watermarks +ffffffff820ac000 T hubp2_set_vm_system_aperture_settings +ffffffff820ac1e0 T hubp2_program_deadline +ffffffff820ac980 T hubp2_vready_at_or_After_vsync +ffffffff820aca20 T hubp2_setup_interdependent +ffffffff820ace90 T hubp2_program_size +ffffffff820ad010 T hubp2_program_rotation +ffffffff820ad180 T hubp2_dcc_control +ffffffff820ad240 T hubp2_program_pixel_format +ffffffff820ad810 T hubp2_program_surface_config +ffffffff820ada50 T hubp2_get_lines_per_chunk +ffffffff820adb10 T hubp2_cursor_set_attributes +ffffffff820aded0 T hubp2_dmdata_set_attributes +ffffffff820ae2b0 T hubp2_dmdata_load +ffffffff820ae340 T hubp2_dmdata_status_done +ffffffff820ae3b0 T hubp2_program_surface_flip_and_addr +ffffffff820aeca0 T hubp2_enable_triplebuffer +ffffffff820aed70 T hubp2_is_triplebuffer_enabled +ffffffff820aedf0 T hubp2_set_flip_control_surface_gsl +ffffffff820aee40 T hubp2_is_flip_pending +ffffffff820aef50 T hubp2_set_blank +ffffffff820aefb0 T hubp2_set_blank_regs +ffffffff820af0b0 T hubp2_cursor_set_position +ffffffff820af520 T hubp2_clk_cntl +ffffffff820af570 T hubp2_vtg_sel +ffffffff820af5b0 T hubp2_clear_underflow +ffffffff820af600 T hubp2_read_state_common +ffffffff820b0250 T hubp2_read_state +ffffffff820b0520 T hubp2_construct +ffffffff820b0590 t hubp2_setup +ffffffff820b0a30 t hubp2_validate_dml_output +ffffffff820b2000 T dcn20_set_flip_control_gsl +ffffffff820b2050 T dcn20_enable_power_gating_plane +ffffffff820b24b0 T dcn20_dccg_init +ffffffff820b2530 T dcn20_disable_vga +ffffffff820b25f0 T dcn20_program_triple_buffer +ffffffff820b2640 T dcn20_init_blank +ffffffff820b2850 T dcn20_dsc_pg_control +ffffffff820b2c60 T dcn20_dpp_pg_control +ffffffff820b2f10 T dcn20_hubp_pg_control +ffffffff820b31c0 T dcn20_plane_atomic_disable +ffffffff820b3310 t dcn20_setup_gsl_group_as_lock +ffffffff820b3570 T dcn20_disable_plane +ffffffff820b3650 T dcn20_disable_pixel_data +ffffffff820b3670 T dcn20_blank_pixel_data +ffffffff820b3890 T dcn20_enable_stream_timing +ffffffff820b3e50 T dcn20_program_output_csc +ffffffff820b3f40 T dcn20_set_output_transfer_func +ffffffff820b40c0 T dcn20_set_blend_lut +ffffffff820b4130 T dcn20_set_shaper_3dlut +ffffffff820b41f0 T dcn20_set_input_transfer_func +ffffffff820b43b0 T dcn20_update_odm +ffffffff820b44a0 T dcn20_pipe_control_lock +ffffffff820b47c0 T dcn20_program_front_end_for_ctx +ffffffff820b5470 t dcn20_program_pipe +ffffffff820b5f10 T dcn20_post_unlock_program_front_end +ffffffff820b61e0 T dcn20_prepare_bandwidth +ffffffff820b6350 T dcn20_optimize_bandwidth +ffffffff820b6560 T dcn20_update_bandwidth +ffffffff820b6820 T dcn20_enable_writeback +ffffffff820b6970 T dcn20_disable_writeback +ffffffff820b6a00 T dcn20_wait_for_blank_complete +ffffffff820b6a90 T dcn20_dmdata_status_done +ffffffff820b6ae0 T dcn20_disable_stream_gating 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+ffffffff820ba420 T enc2_hw_init +ffffffff820ba500 T dcn20_link_encoder_construct +ffffffff820bb000 T mmhubbub2_config_mcif_irq +ffffffff820bb130 T mmhubbub2_enable_mcif +ffffffff820bb170 T mmhubbub2_disable_mcif +ffffffff820bb1b0 T mcifwb2_dump_frame +ffffffff820bb2c0 T dcn20_mmhubbub_construct +ffffffff820bb310 t mmhubbub2_config_mcif_buf +ffffffff820bb960 t mmhubbub2_config_mcif_arb +ffffffff820bc000 T mpc2_update_blending +ffffffff820bc2a0 T mpc2_set_denorm +ffffffff820bc310 T mpc2_set_denorm_clamp +ffffffff820bc460 T mpc2_set_output_csc +ffffffff820bc650 T mpc2_set_ocsc_default +ffffffff820bc830 T mpc20_power_on_ogam_lut +ffffffff820bc8b0 T mpc2_set_output_gamma +ffffffff820bd0b0 T mpc2_assert_idle_mpcc +ffffffff820bd1c0 T mpc2_assert_mpcc_idle_before_connect +ffffffff820bd410 T dcn20_mpc_construct +ffffffff820bd4d0 t mpc2_get_mpcc_for_dpp +ffffffff820be000 T opp2_set_disp_pattern_generator +ffffffff820be810 T opp2_dpg_set_blank_color +ffffffff820be990 T opp2_program_dpg_dimensions +ffffffff820bea20 T opp2_dpg_is_blanked +ffffffff820beae0 T opp2_program_left_edge_extra_pixel +ffffffff820beb30 T dcn20_opp_construct +ffffffff820bf000 T optc2_enable_crtc +ffffffff820bf100 T optc2_set_gsl +ffffffff820bf1f0 T optc2_set_gsl_source_select +ffffffff820bf2b0 T optc2_set_dsc_config +ffffffff820bf380 T optc2_get_dsc_status +ffffffff820bf3c0 T optc2_is_two_pixels_per_containter +ffffffff820bf3d0 T optc2_set_odm_bypass +ffffffff820bf510 T optc2_set_odm_combine +ffffffff820bf700 T optc2_get_optc_source +ffffffff820bf7d0 T optc2_triplebuffer_lock +ffffffff820bf8f0 T optc2_triplebuffer_unlock +ffffffff820bf9a0 T optc2_lock_doublebuffer_enable +ffffffff820bfb80 T optc2_lock_doublebuffer_disable +ffffffff820bfc60 T optc2_setup_manual_trigger +ffffffff820bfdf0 T optc2_program_manual_trigger +ffffffff820bfe60 T optc2_configure_crc +ffffffff820bfef0 T optc2_get_last_used_drr_vtotal +ffffffff820bff30 T dcn20_timing_generator_init +ffffffff820bffa0 t optc2_set_dwb_source +ffffffff820c0040 t optc2_align_vblanks +ffffffff820c1000 T dcn20_dpp_destroy +ffffffff820c1050 T dcn20_dpp_create +ffffffff820c1120 T dcn20_ipp_create +ffffffff820c11d0 T dcn20_opp_create +ffffffff820c1280 T dcn20_aux_engine_create +ffffffff820c1320 T dcn20_i2c_hw_create +ffffffff820c13b0 T dcn20_mpc_create +ffffffff820c1440 T dcn20_hubbub_create +ffffffff820c1510 T dcn20_timing_generator_create +ffffffff820c15a0 T dcn20_link_encoder_create +ffffffff820c16a0 T dcn20_stream_encoder_create +ffffffff820c1760 T dcn20_hwseq_create +ffffffff820c17d0 T dcn20_clock_source_destroy +ffffffff820c1820 T dcn20_dsc_create +ffffffff820c18e0 T dcn20_dsc_destroy +ffffffff820c1930 T dcn20_hubp_create +ffffffff820c1a00 T dcn20_build_mapped_resource +ffffffff820c1c20 T dcn20_acquire_dsc +ffffffff820c1d60 T dcn20_release_dsc +ffffffff820c1dd0 T dcn20_add_dsc_to_stream_resource +ffffffff820c1f40 T dcn20_add_stream_to_ctx +ffffffff820c1fd0 T dcn20_remove_stream_from_ctx +ffffffff820c20c0 T dcn20_split_stream_for_odm +ffffffff820c2570 T dcn20_split_stream_for_mpc +ffffffff820c26f0 T dcn20_calc_max_scaled_time +ffffffff820c2760 T dcn20_set_mcif_arb_params +ffffffff820c28d0 T dcn20_validate_dsc +ffffffff820c2a80 T dcn20_find_secondary_pipe +ffffffff820c2c60 T dcn20_merge_pipes_for_validate +ffffffff820c2ed0 T dcn20_validate_apply_pipe_split_flags +ffffffff820c3760 T dcn20_fast_validate_bw +ffffffff820c3cb0 T dcn20_validate_bandwidth +ffffffff820c3d30 T dcn20_acquire_free_pipe_for_layer +ffffffff820c3e50 T dcn20_get_dcc_compression_cap +ffffffff820c3e80 T dcn20_patch_unknown_plane_state +ffffffff820c3ee0 T dcn20_dwbc_create +ffffffff820c3ff0 T dcn20_mmhubbub_create +ffffffff820c4150 T dcn20_create_resource_pool +ffffffff820c58f0 t dcn20_resource_destruct +ffffffff820c5da0 t dcn20_destroy_resource_pool +ffffffff820c5e00 t dcn20_panel_cntl_create +ffffffff820c5e90 t read_dce_straps +ffffffff820c5ec0 t dcn20_create_audio +ffffffff820c6000 T enc2_set_dynamic_metadata +ffffffff820c6260 T enc2_stream_encoder_dp_unblank +ffffffff820c65a0 T enc2_stream_encoder_dp_set_stream_attribute +ffffffff820c6600 T enc2_get_fifo_cal_average_level +ffffffff820c6660 T dcn20_stream_encoder_construct +ffffffff820c66c0 t enc2_stream_encoder_update_hdmi_info_packets +ffffffff820c6790 t enc2_stream_encoder_stop_hdmi_info_packets +ffffffff820c6aa0 t enc2_stream_encoder_update_dp_info_packets_sdp_line_num +ffffffff820c6b60 t enc2_stream_encoder_update_dp_info_packets +ffffffff820c6c10 t enc2_read_state +ffffffff820c6d90 t enc2_dp_set_dsc_config +ffffffff820c6e60 t enc2_dp_set_dsc_pps_info_packet +ffffffff820c7330 t enc2_dp_set_odm_combine +ffffffff820c7370 t enc2_update_hdmi_info_packet +ffffffff820c8000 T dcn20_vmid_setup +ffffffff820c9000 T dccg201_create +ffffffff820c90b0 t dccg201_update_dpp_dto +ffffffff820ca000 T dpp201_construct +ffffffff820ca080 t dpp201_get_optimal_number_of_taps +ffffffff820ca440 t dpp201_cnv_setup +ffffffff820cb000 T hubbub201_construct +ffffffff820cb060 t hubbub201_program_watermarks +ffffffff820cc000 T dcn201_hubp_construct +ffffffff820cc070 t hubp201_setup +ffffffff820cc350 t hubp201_program_surface_config +ffffffff820cd000 T dcn201_update_plane_addr +ffffffff820cd2a0 T dcn201_init_blank +ffffffff820cd3e0 T dcn201_init_hw +ffffffff820cdbb0 T dcn201_plane_atomic_disconnect +ffffffff820cdd20 T dcn201_update_mpcc +ffffffff820cdfb0 T dcn201_pipe_control_lock +ffffffff820ce0b0 T dcn201_set_cursor_attribute +ffffffff820ce140 T dcn201_set_dmdata_attributes +ffffffff820ce250 T dcn201_unblank_stream +ffffffff820cf000 T dcn201_hw_sequencer_construct +ffffffff820d0000 T dcn201_link_encoder_construct +ffffffff820d0190 t dcn201_link_encoder_is_in_alt_mode +ffffffff820d0200 t dcn201_link_encoder_get_max_link_cap +ffffffff820d1000 T dcn201_mpc_construct +ffffffff820d10c0 t mpc201_set_out_rate_control +ffffffff820d2000 T dcn201_opp_construct +ffffffff820d3000 T optc201_is_two_pixels_per_containter +ffffffff820d3010 T dcn201_timing_generator_init +ffffffff820d3080 t optc201_validate_timing +ffffffff820d3180 t optc201_triplebuffer_unlock +ffffffff820d3230 t optc201_triplebuffer_lock +ffffffff820d3350 t optc201_get_optc_source +ffffffff820d4000 T dcn201_create_resource_pool +ffffffff820d4a30 t dcn201_resource_destruct +ffffffff820d4d30 t dcn201_destroy_resource_pool +ffffffff820d4d90 t dcn201_link_init +ffffffff820d4de0 t dcn201_link_encoder_create +ffffffff820d4e90 t dcn201_acquire_free_pipe_for_layer +ffffffff820d4fa0 t dcn201_populate_dml_writeback_from_context +ffffffff820d5000 t read_dce_straps +ffffffff820d5030 t dcn201_create_audio +ffffffff820d5060 t dcn201_stream_encoder_create +ffffffff820d5100 t dcn201_hwseq_create +ffffffff820d5170 t dcn201_get_dcc_compression_cap +ffffffff820d6000 T dccg21_create +ffffffff820d60b0 t dccg21_update_dpp_dto +ffffffff820d7000 T dcn21_dchvm_init +ffffffff820d7200 T hubbub21_init_dchub +ffffffff820d73d0 T hubbub21_program_urgent_watermarks +ffffffff820d7bf0 T hubbub21_program_stutter_watermarks +ffffffff820d80e0 T hubbub21_program_pstate_watermarks +ffffffff820d8380 T hubbub21_program_watermarks +ffffffff820d84e0 T hubbub21_wm_read_state +ffffffff820d8780 T hubbub21_construct +ffffffff820d87e0 t hubbub21_apply_DEDCN21_147_wa +ffffffff820d9000 T apply_DEDCN21_142_wa_for_hostvm_deadline +ffffffff820d92e0 T hubp21_program_deadline +ffffffff820d9310 T hubp21_program_requestor +ffffffff820d96b0 T hubp21_construct +ffffffff820d9720 t hubp21_setup +ffffffff820d9780 t hubp21_set_viewport +ffffffff820d9a80 t hubp21_program_surface_flip_and_addr +ffffffff820da370 t hubp21_set_vm_system_aperture_settings +ffffffff820da4a0 t hubp21_init +ffffffff820da4d0 t hubp21_validate_dml_output +ffffffff820dc000 T dcn21_init_sys_ctx +ffffffff820dc110 T dcn21_s0i3_golden_init_wa +ffffffff820dc170 T dcn21_exit_optimized_pwr_state +ffffffff820dc190 T dcn21_optimize_pwr_state +ffffffff820dc1c0 T dcn21_PLAT_58856_wa +ffffffff820dc260 T dcn21_set_abm_immediate_disable +ffffffff820dc3a0 T dcn21_set_pipe +ffffffff820dc4d0 T dcn21_set_backlight_level +ffffffff820dc6d0 T dcn21_is_abm_supported +ffffffff820dd000 T dcn21_hw_sequencer_construct +ffffffff820de000 T dcn21_link_encoder_enable_dp_output +ffffffff820de140 t dcn21_link_encoder_acquire_phy +ffffffff820de320 T dcn21_link_encoder_construct +ffffffff820de500 t dcn21_link_encoder_enable_dp_mst_output +ffffffff820de570 t dcn21_link_encoder_disable_output +ffffffff820df000 T dcn21_fast_validate_bw +ffffffff820df6a0 T dcn21_create_resource_pool +ffffffff820e09d0 t dcn21_resource_destruct +ffffffff820e0e70 t dcn21_destroy_resource_pool +ffffffff820e0ed0 t dcn21_panel_cntl_create +ffffffff820e0f60 t dcn21_link_encoder_create +ffffffff820e1060 t dcn21_validate_bandwidth +ffffffff820e10e0 t dcn21_patch_unknown_plane_state +ffffffff820e1130 t dcn21_get_panel_config_defaults +ffffffff820e1170 t read_dce_straps +ffffffff820e11a0 t dcn21_create_audio +ffffffff820e11d0 t dcn21_stream_encoder_create +ffffffff820e1270 t dcn21_hwseq_create +ffffffff820e2000 T afmt3_setup_hdmi_audio +ffffffff820e21d0 T afmt3_se_audio_setup +ffffffff820e2370 T afmt3_audio_mute_control +ffffffff820e23e0 T afmt3_audio_info_immediate_update +ffffffff820e2420 T afmt3_setup_dp_audio +ffffffff820e2510 T afmt3_construct +ffffffff820e3000 T cm_helper_program_gamcor_xfer_func +ffffffff820e33c0 T cm3_helper_translate_curve_to_hw_format +ffffffff820e3fd0 T cm3_helper_convert_to_custom_float +ffffffff820e4420 T cm3_helper_translate_curve_to_degamma_hw_format +ffffffff820e4c40 T is_rgb_equal +ffffffff820e5000 T dccg3_create +ffffffff820e50b0 T dccg30_create +ffffffff820e6000 T dcn30_link_encoder_validate_output_with_stream +ffffffff820e6010 T dcn30_link_encoder_construct +ffffffff820e61f0 T enc3_hw_init +ffffffff820e7000 T enc3_stream_encoder_update_hdmi_info_packets +ffffffff820e7100 t enc3_update_hdmi_info_packet +ffffffff820e74f0 T enc3_stream_encoder_stop_hdmi_info_packets +ffffffff820e7ad0 T enc3_dp_set_dsc_pps_info_packet +ffffffff820e7df0 T enc3_stream_encoder_update_dp_info_packets_sdp_line_num +ffffffff820e7eb0 T enc3_stream_encoder_update_dp_info_packets +ffffffff820e8170 T enc3_audio_mute_control +ffffffff820e81e0 T enc3_se_dp_audio_setup +ffffffff820e8260 T enc3_se_dp_audio_enable +ffffffff820e8350 T enc3_se_hdmi_audio_setup +ffffffff820e8660 T dcn30_dio_stream_encoder_construct +ffffffff820e86d0 t enc3_stream_encoder_hdmi_set_stream_attribute +ffffffff820e8cd0 t enc3_stream_encoder_dvi_set_stream_attribute +ffffffff820e8ed0 t enc3_read_state +ffffffff820e9060 t enc3_dp_set_dsc_config +ffffffff820e9130 t enc3_dp_set_odm_combine +ffffffff820ea000 T dpp30_read_state +ffffffff820ea050 T dpp3_program_post_csc +ffffffff820ea240 T dpp3_set_pre_degam +ffffffff820ea2f0 T dpp3_cnv_setup +ffffffff820eabc0 T dpp3_set_cursor_attributes +ffffffff820ead30 T dpp3_get_optimal_number_of_taps +ffffffff820eb750 T dpp3_construct +ffffffff820eb7b0 t dpp3_deferred_update +ffffffff820ebb90 t dpp3_program_blnd_lut +ffffffff820ec5e0 t dpp3_program_shaper +ffffffff820ee660 t dpp3_program_3dlut +ffffffff820eee10 t dpp3_set3dlut_ram12 +ffffffff820ef000 T dpp3_program_cm_dealpha +ffffffff820ef0a0 T dpp3_program_cm_bias +ffffffff820ef190 T dpp3_program_gamcor_lut +ffffffff820efbb0 t dpp3_power_on_gamcor_lut +ffffffff820efce0 T dpp3_set_hdr_multiplier +ffffffff820efd30 T dpp3_cm_set_gamut_remap +ffffffff820f0000 T dwb3_config_fc +ffffffff820f01b0 T dwb3_set_stereo +ffffffff820f0270 T dwb3_enable +ffffffff820f03a0 T dwb3_set_denorm +ffffffff820f04c0 T dwb3_disable +ffffffff820f0570 T dwb3_update +ffffffff820f06a0 T dwb3_is_enabled +ffffffff820f0740 T dwb3_set_new_content +ffffffff820f0780 T dcn30_dwbc_construct +ffffffff820f07d0 T dwb3_set_host_read_rate_control +ffffffff820f0840 t dwb3_get_caps +ffffffff820f1000 T dwb3_ogam_set_input_transfer_func +ffffffff820f19f0 T dwb3_set_gamut_remap +ffffffff820f1ca0 T dwb3_program_hdr_mult +ffffffff820f2000 T hubbub3_init_dchub_sys_ctx +ffffffff820f21c0 T hubbub3_program_watermarks +ffffffff820f22c0 T hubbub3_dcc_support_swizzle +ffffffff820f2380 T hubbub3_get_dcc_compression_cap +ffffffff820f2560 T hubbub3_force_wm_propagate_to_pipes +ffffffff820f2610 T hubbub3_force_pstate_change_control +ffffffff820f2690 T hubbub3_init_watermarks +ffffffff820f29d0 T hubbub3_construct +ffffffff820f3000 T hubp3_set_vm_system_aperture_settings +ffffffff820f3130 T hubp3_program_surface_flip_and_addr +ffffffff820f3b20 T hubp3_dcc_control +ffffffff820f3be0 T hubp3_dcc_control_sienna_cichlid +ffffffff820f3d00 T hubp3_dmdata_set_attributes +ffffffff820f3f00 T hubp3_program_surface_config +ffffffff820f41f0 T hubp3_read_state +ffffffff820f44c0 T hubp3_setup +ffffffff820f4550 T hubp3_init +ffffffff820f4580 T hubp3_construct +ffffffff820f5000 T dcn30_set_blend_lut +ffffffff820f5070 T dcn30_set_input_transfer_func +ffffffff820f51d0 T dcn30_set_output_transfer_func +ffffffff820f5500 T dcn30_update_writeback +ffffffff820f5590 t dcn30_set_writeback +ffffffff820f5740 T dcn30_mmhubbub_warmup +ffffffff820f5990 T dcn30_enable_writeback +ffffffff820f5a40 T dcn30_disable_writeback +ffffffff820f5b20 T dcn30_program_all_writeback_pipes_in_tree +ffffffff820f5e20 T dcn30_init_hw +ffffffff820f6550 T dcn30_set_avmute +ffffffff820f65b0 T dcn30_update_info_frame +ffffffff820f66a0 T dcn30_program_dmdata_engine +ffffffff820f6740 T dcn30_apply_idle_power_optimizations +ffffffff820f6c60 T dcn30_does_plane_fit_in_mall +ffffffff820f6d10 T dcn30_hardware_release +ffffffff820f6e00 T dcn30_set_disp_pattern_generator +ffffffff820f6e70 T dcn30_prepare_bandwidth +ffffffff820f6f60 T dcn30_set_static_screen_control +ffffffff820f7000 T dcn30_hw_sequencer_construct +ffffffff820f8000 T dcn30_mmhubbub_construct +ffffffff820f8050 t mmhubbub3_warmup_mcif +ffffffff820f8260 t mmhubbub3_config_mcif_buf +ffffffff820f8710 t mmhubbub3_config_mcif_arb +ffffffff820f9000 T mpc3_is_dwb_idle +ffffffff820f9070 T mpc3_set_dwb_mux +ffffffff820f90f0 T mpc3_disable_dwb_mux +ffffffff820f9170 T mpc3_set_out_rate_control +ffffffff820f9280 T mpc3_get_ogam_current +ffffffff820f9320 T mpc3_power_on_ogam_lut +ffffffff820f93f0 T mpc3_set_output_gamma +ffffffff820fa030 T mpc3_set_denorm +ffffffff820fa0a0 T mpc3_set_denorm_clamp +ffffffff820fa1f0 T mpc3_program_shaper +ffffffff820fc3b0 t mpc3_power_on_shaper_3dlut +ffffffff820fc730 T mpc3_init_mpcc +ffffffff820fc7b0 T mpc3_set_gamut_remap +ffffffff820fca20 T mpc3_program_3dlut +ffffffff820fd190 t mpc3_set3dlut_ram12 +ffffffff820fd370 T mpc3_set_output_csc +ffffffff820fd4e0 T mpc3_set_ocsc_default +ffffffff820fd650 T mpc3_set_rmu_mux +ffffffff820fd6f0 T mpc3_get_rmu_mux_status +ffffffff820fd7a0 T mpcc3_acquire_rmu +ffffffff820fd900 T dcn30_mpc_construct +ffffffff820fd9d0 t mpcc3_release_rmu +ffffffff820fdb40 t mpc3_set_mpc_mem_lp_mode +ffffffff820fe000 T optc3_triplebuffer_lock +ffffffff820fe120 T optc3_lock_doublebuffer_enable +ffffffff820fe3b0 T optc3_lock_doublebuffer_disable +ffffffff820fe4d0 T optc3_lock +ffffffff820fe5a0 T optc3_set_out_mux +ffffffff820fe5e0 T optc3_program_blank_color +ffffffff820fe710 T optc3_set_drr_trigger_window +ffffffff820fe7a0 T optc3_set_vtotal_change_limit +ffffffff820fe810 T optc3_set_dsc_config +ffffffff820fe860 T optc3_set_odm_bypass +ffffffff820fe9e0 T optc3_set_odm_combine +ffffffff820fed30 T optc3_wait_drr_doublebuffer_pending_clear +ffffffff820fedb0 T optc3_set_vtotal_min_max +ffffffff820fedf0 T optc3_tg_init +ffffffff820fee50 T dcn30_timing_generator_init +ffffffff820ff000 T dcn30_add_stream_to_ctx +ffffffff820ff020 T dcn30_populate_dml_pipes_from_context +ffffffff820ff100 T dcn30_populate_dml_writeback_from_context +ffffffff820ff160 T dcn30_calc_max_scaled_time +ffffffff820ff1c0 T dcn30_set_mcif_arb_params +ffffffff820ff330 T dcn30_acquire_post_bldn_3dlut +ffffffff820ff4c0 T dcn30_release_post_bldn_3dlut +ffffffff820ff570 T dcn30_internal_validate_bw +ffffffff821002e0 t dcn30_split_stream_for_mpc_or_odm +ffffffff82100600 T dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch +ffffffff821006e0 t is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch +ffffffff82100780 T dcn30_setup_mclk_switch_using_fw_based_vblank_stretch +ffffffff82100820 T dcn30_update_soc_for_wm_a +ffffffff82100870 T dcn30_calculate_wm_and_dlg +ffffffff821008e0 T dcn30_validate_bandwidth +ffffffff82100d10 T dcn30_update_bw_bounding_box +ffffffff82101370 T dcn30_create_resource_pool +ffffffff82102920 t dcn30_resource_destruct +ffffffff82102ea0 t dcn30_destroy_resource_pool +ffffffff82102f00 t dcn30_panel_cntl_create +ffffffff82102f90 t dcn30_link_encoder_create +ffffffff82103040 t dcn30_get_panel_config_defaults +ffffffff821030c0 t read_dce_straps +ffffffff821030f0 t dcn30_create_audio +ffffffff82103120 t dcn30_stream_encoder_create +ffffffff821032a0 t dcn30_hwseq_create +ffffffff82104000 T vpg3_update_generic_info_packet +ffffffff821049a0 T vpg3_construct +ffffffff82105000 T dccg301_create +ffffffff82106000 T dcn301_link_encoder_construct +ffffffff82107000 T hubbub301_construct +ffffffff82108000 T dcn301_hw_sequencer_construct +ffffffff82109000 T optc301_set_drr +ffffffff82109230 T optc301_setup_manual_trigger +ffffffff82109350 T dcn301_timing_generator_init +ffffffff8210a000 T dcn301_panel_cntl_construct +ffffffff8210a050 t dcn301_panel_cntl_destroy +ffffffff8210a0a0 t dcn301_panel_cntl_hw_init +ffffffff8210a2b0 t dcn301_is_panel_backlight_on +ffffffff8210a310 t dcn301_is_panel_powered_on +ffffffff8210a3c0 t dcn301_store_backlight_level +ffffffff8210a460 t dcn301_get_16_bit_backlight_from_pwm +ffffffff8210b000 T dcn301_create_resource_pool +ffffffff8210c590 t dcn301_destruct +ffffffff8210cad0 t dcn301_destroy_resource_pool +ffffffff8210cb30 t dcn301_panel_cntl_create +ffffffff8210cbc0 t dcn301_link_encoder_create +ffffffff8210cc70 t dcn301_calculate_wm_and_dlg +ffffffff8210cce0 t read_dce_straps +ffffffff8210cd10 t dcn301_create_audio +ffffffff8210cd40 t dcn301_stream_encoder_create +ffffffff8210cec0 t dcn301_hwseq_create +ffffffff8210d000 T dcn302_dpp_pg_control +ffffffff8210d2a0 T dcn302_hubp_pg_control +ffffffff8210d550 T dcn302_dsc_pg_control +ffffffff8210e000 T dcn302_hw_sequencer_construct +ffffffff8210f000 T dcn302_update_bw_bounding_box +ffffffff8210f050 T dcn302_create_resource_pool +ffffffff821104a0 t dcn302_resource_destruct +ffffffff821109e0 t dcn302_destroy_resource_pool +ffffffff82110a30 t dcn302_panel_cntl_create +ffffffff82110ac0 t dcn302_link_encoder_create +ffffffff82110b70 t dcn302_get_panel_config_defaults +ffffffff82110bf0 t read_dce_straps +ffffffff82110c20 t dcn302_create_audio +ffffffff82110c50 t dcn302_stream_encoder_create +ffffffff82110dd0 t dcn302_hwseq_create +ffffffff82111000 T dcn303_dpp_pg_control +ffffffff82111030 T dcn303_hubp_pg_control +ffffffff82111060 T dcn303_dsc_pg_control +ffffffff82111090 T dcn303_enable_power_gating_plane +ffffffff82112000 T dcn303_hw_sequencer_construct +ffffffff82113000 T dcn303_update_bw_bounding_box +ffffffff82113050 T dcn303_create_resource_pool +ffffffff821142a0 t dcn303_resource_destruct +ffffffff821147e0 t dcn303_destroy_resource_pool +ffffffff82114830 t dcn303_panel_cntl_create +ffffffff821148c0 t dcn303_link_encoder_create +ffffffff82114970 t dcn303_get_panel_config_defaults +ffffffff821149f0 t read_dce_straps +ffffffff82114a20 t dcn303_create_audio +ffffffff82114a50 t dcn303_stream_encoder_create +ffffffff82114bd0 t dcn303_hwseq_create +ffffffff82115000 T afmt31_powerdown +ffffffff82115090 T afmt31_poweron +ffffffff82115120 T afmt31_construct +ffffffff82116000 T apg31_construct +ffffffff82116050 t apg31_se_audio_setup +ffffffff82116160 t apg31_enable +ffffffff82116270 t apg31_disable +ffffffff82117000 T dccg31_update_dpp_dto +ffffffff82117160 T dccg31_set_dpstreamclk +ffffffff821172f0 t dccg31_disable_dpstreamclk +ffffffff82117440 T dccg31_enable_symclk32_se +ffffffff82117740 T dccg31_disable_symclk32_se +ffffffff82117a10 T dccg31_enable_symclk32_le +ffffffff82117b20 T dccg31_disable_symclk32_le +ffffffff82117c10 T dccg31_set_symclk32_le_root_clock_gating +ffffffff82117d20 T dccg31_disable_dscclk +ffffffff82117f70 T dccg31_enable_dscclk +ffffffff821181e0 T dccg31_set_physymclk +ffffffff821186f0 T dccg31_set_dtbclk_dto +ffffffff821189a0 T dccg31_set_audio_dtbclk_dto +ffffffff82118ab0 T dccg31_get_dccg_ref_freq +ffffffff82118ae0 T dccg31_set_dispclk_change_mode +ffffffff82118b30 T dccg31_init +ffffffff82119110 T dccg31_otg_add_pixel +ffffffff82119150 T dccg31_otg_drop_pixel +ffffffff82119190 T dccg31_create +ffffffff8211a000 T dcn31_link_encoder_set_dio_phy_mux +ffffffff8211a390 T dcn31_link_encoder_construct +ffffffff8211a560 T dcn31_link_encoder_construct_minimal +ffffffff8211a5e0 T dcn31_link_encoder_enable_dp_output +ffffffff8211a820 T dcn31_link_encoder_enable_dp_mst_output +ffffffff8211aa60 T dcn31_link_encoder_disable_output +ffffffff8211acd0 T dcn31_link_encoder_is_in_alt_mode +ffffffff8211ae20 T dcn31_link_encoder_get_max_link_cap +ffffffff8211afa0 t enc31_hw_init +ffffffff8211b000 T dcn31_hpo_dp_link_enc_enable +ffffffff8211b160 T dcn31_hpo_dp_link_enc_disable +ffffffff8211b1d0 T dcn31_hpo_dp_link_enc_set_link_test_pattern +ffffffff8211bb30 T dcn31_hpo_dp_link_enc_update_stream_allocation_table +ffffffff8211bdb0 T dcn31_hpo_dp_link_enc_set_throttled_vcp_size +ffffffff8211c050 T dcn31_hpo_dp_link_enc_read_state +ffffffff8211c2f0 T dcn31_hpo_dp_link_enc_enable_dp_output +ffffffff8211c3f0 T dcn31_hpo_dp_link_enc_disable_output +ffffffff8211c530 T dcn31_hpo_dp_link_enc_set_ffe +ffffffff8211c620 T hpo_dp_link_encoder31_construct +ffffffff8211c680 t dcn31_hpo_dp_link_enc_is_in_alt_mode +ffffffff8211d000 T dcn31_hpo_dp_stream_encoder_construct +ffffffff8211d070 t dcn31_hpo_dp_stream_enc_enable_stream +ffffffff8211d1b0 t dcn31_hpo_dp_stream_enc_dp_unblank +ffffffff8211d460 t dcn31_hpo_dp_stream_enc_dp_blank +ffffffff8211d560 t dcn31_hpo_dp_stream_enc_disable +ffffffff8211d5d0 t dcn31_hpo_dp_stream_enc_set_stream_attribute +ffffffff8211de80 t dcn31_hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num +ffffffff8211df40 t dcn31_hpo_dp_stream_enc_update_dp_info_packets +ffffffff8211e160 t dcn31_hpo_dp_stream_enc_stop_dp_info_packets +ffffffff8211e2f0 t dcn31_hpo_dp_stream_enc_set_dsc_pps_info_packet +ffffffff8211e590 t dcn31_hpo_dp_stream_enc_map_stream_to_link +ffffffff8211e690 t dcn31_hpo_dp_stream_enc_audio_setup +ffffffff8211e740 t dcn31_hpo_dp_stream_enc_audio_enable +ffffffff8211e810 t dcn31_hpo_dp_stream_enc_audio_disable +ffffffff8211e9c0 t dcn31_hpo_dp_stream_enc_read_state +ffffffff8211eb50 t dcn31_set_hblank_min_symbol_width +ffffffff8211f000 T hubbub31_init_dchub_sys_ctx +ffffffff8211f1e0 T hubbub31_init +ffffffff8211f280 T hubbub31_construct +ffffffff8211f320 t hubbub31_get_dcc_compression_cap +ffffffff8211f500 t hubbub31_get_dchub_ref_freq +ffffffff8211f5e0 t hubbub31_program_watermarks +ffffffff82120f00 t hubbub31_verify_allow_pstate_change_high +ffffffff821210c0 t dcn31_program_det_size +ffffffff821212a0 t dcn31_program_compbuf_size +ffffffff82121520 t dcn31_init_crb +ffffffff82122000 T hubp31_set_unbounded_requesting +ffffffff82122090 T hubp31_soft_reset +ffffffff821220e0 T hubp31_construct +ffffffff82122150 t hubp31_program_extended_blank +ffffffff82123000 T dcn31_init_hw +ffffffff82123850 T dcn31_dsc_pg_control +ffffffff82123ba0 T dcn31_enable_power_gating_plane +ffffffff82123e00 T dcn31_update_info_frame +ffffffff82123f30 T dcn31_z10_save_init +ffffffff82123fc0 T dcn31_z10_restore +ffffffff82124070 T dcn31_hubp_pg_control +ffffffff82124390 T dcn31_init_sys_ctx +ffffffff82124440 T dcn31_reset_hw_ctx_wrap +ffffffff82124790 T dcn31_setup_hpo_hw_control +ffffffff82125000 T dcn31_hw_sequencer_construct +ffffffff82126000 T optc31_immediate_disable_crtc +ffffffff82126100 T optc31_set_drr +ffffffff82126310 T optc3_init_odm +ffffffff82126480 T dcn31_timing_generator_init +ffffffff821264f0 t optc31_enable_crtc +ffffffff821265f0 t optc31_disable_crtc +ffffffff821266d0 t optc31_set_odm_combine +ffffffff82127000 T dcn31_panel_cntl_construct +ffffffff82127040 t dcn31_panel_cntl_destroy +ffffffff82127090 t dcn31_panel_cntl_hw_init +ffffffff82127190 t dcn31_is_panel_backlight_on +ffffffff82127230 t dcn31_is_panel_powered_on +ffffffff821272e0 t dcn31_store_backlight_level +ffffffff821273b0 t dcn31_get_16_bit_backlight_from_pwm +ffffffff82128000 T dcn31x_populate_dml_pipes_from_context +ffffffff82128180 T dcn31_populate_dml_pipes_from_context +ffffffff821285c0 T dcn31_calculate_wm_and_dlg +ffffffff82128630 T dcn31_populate_dml_writeback_from_context +ffffffff82128690 T dcn31_set_mcif_arb_params +ffffffff821286f0 T dcn31_validate_bandwidth +ffffffff82128ae0 T dcn31_create_resource_pool +ffffffff82129e80 t dcn31_resource_destruct +ffffffff8212a4f0 t dcn31_destroy_resource_pool +ffffffff8212a550 t dcn31_panel_cntl_create +ffffffff8212a5c0 t dcn31_link_encoder_create +ffffffff8212a670 t dcn31_link_enc_create_minimal +ffffffff8212a710 t dcn31_get_panel_config_defaults +ffffffff8212a750 t read_dce_straps +ffffffff8212a780 t dcn31_create_audio +ffffffff8212a7b0 t dcn31_stream_encoder_create +ffffffff8212a930 t dcn31_hpo_dp_stream_encoder_create +ffffffff8212aaf0 t dcn31_hpo_dp_link_encoder_create +ffffffff8212ab80 t dcn31_hwseq_create +ffffffff8212b000 T vpg31_powerdown +ffffffff8212b090 T vpg31_poweron +ffffffff8212b120 T vpg31_construct +ffffffff8212c000 T dccg314_create +ffffffff8212c0b0 t dccg314_init +ffffffff8212c210 t dccg314_set_dpstreamclk +ffffffff8212c5d0 t dccg314_set_dtbclk_dto +ffffffff8212c7c0 t dccg314_set_pixel_rate_div +ffffffff8212cb30 t dccg314_set_valid_pixel_rate +ffffffff8212cba0 t dccg314_trigger_dio_fifo_resync +ffffffff8212cc40 t dccg314_dpp_root_clock_control +ffffffff8212d000 T dcn314_dio_stream_encoder_construct +ffffffff8212d070 t enc314_stream_encoder_hdmi_set_stream_attribute +ffffffff8212d670 t enc314_stream_encoder_dvi_set_stream_attribute +ffffffff8212d880 t enc314_stream_encoder_dp_blank +ffffffff8212d900 t enc314_stream_encoder_dp_unblank +ffffffff8212dc80 t enc314_read_state +ffffffff8212dde0 t enc314_dp_set_dsc_config +ffffffff8212de30 t enc314_dp_set_odm_combine +ffffffff8212de70 t enc314_set_dig_input_mode +ffffffff8212dec0 t enc314_enable_fifo +ffffffff8212df60 t enc314_disable_fifo +ffffffff8212dfb0 t enc314_reset_fifo +ffffffff8212f000 T dcn314_update_odm +ffffffff8212f600 T dcn314_dsc_pg_control +ffffffff8212f9d0 T dcn314_enable_power_gating_plane +ffffffff8212fc60 T dcn314_calculate_dccg_k1_k2_values +ffffffff8212fe10 T dcn314_set_pixels_per_cycle +ffffffff8212ff00 T dcn314_resync_fifo_dccg_dio +ffffffff821300a0 T dcn314_dpp_root_clock_control +ffffffff82130100 T dcn314_disable_link_output +ffffffff82131000 T dcn314_hw_sequencer_construct +ffffffff82132000 T dcn314_timing_generator_init +ffffffff82132070 t optc314_enable_crtc +ffffffff82132170 t optc314_disable_crtc +ffffffff82132250 t optc314_phantom_crtc_post_enable +ffffffff82132310 t optc314_set_odm_bypass +ffffffff82132480 t optc314_set_odm_combine +ffffffff82132770 t optc314_set_h_timing_div_manual_mode +ffffffff82133000 T dcn314_validate_bandwidth +ffffffff82133490 T dcn314_create_resource_pool +ffffffff821347b0 t dcn314_resource_destruct +ffffffff82134e20 t dcn314_get_preferred_eng_id_dpia +ffffffff82134e50 t dcn314_destroy_resource_pool +ffffffff82134eb0 t dcn31_panel_cntl_create +ffffffff82134f20 t dcn31_link_encoder_create +ffffffff82134fd0 t dcn31_link_enc_create_minimal +ffffffff82135070 t dcn314_populate_dml_pipes_from_context +ffffffff82135100 t dcn314_update_bw_bounding_box +ffffffff82135150 t dcn314_get_panel_config_defaults +ffffffff82135190 t read_dce_straps +ffffffff821351c0 t dcn31_create_audio +ffffffff821351f0 t dcn314_stream_encoder_create +ffffffff82135370 t dcn31_hpo_dp_stream_encoder_create +ffffffff82135530 t dcn31_hpo_dp_link_encoder_create +ffffffff821355c0 t dcn314_hwseq_create +ffffffff82136000 T dcn315_create_resource_pool +ffffffff82137280 t dcn315_resource_destruct +ffffffff821378e0 t dcn315_destroy_resource_pool +ffffffff82137940 t dcn31_panel_cntl_create +ffffffff821379b0 t dcn31_link_encoder_create +ffffffff82137a60 t dcn31_link_enc_create_minimal +ffffffff82137b00 t dcn315_populate_dml_pipes_from_context +ffffffff82138200 t dcn315_get_panel_config_defaults +ffffffff82138240 t read_dce_straps +ffffffff82138270 t dcn31_create_audio +ffffffff821382a0 t dcn315_stream_encoder_create +ffffffff82138420 t dcn31_hpo_dp_stream_encoder_create +ffffffff821385e0 t dcn31_hpo_dp_link_encoder_create +ffffffff82138670 t dcn31_hwseq_create +ffffffff82139000 T dcn316_create_resource_pool +ffffffff8213a290 t dcn316_resource_destruct +ffffffff8213a8f0 t dcn316_destroy_resource_pool +ffffffff8213a950 t dcn31_panel_cntl_create +ffffffff8213a9c0 t dcn31_link_encoder_create +ffffffff8213aa70 t dcn31_link_enc_create_minimal +ffffffff8213ab10 t dcn316_populate_dml_pipes_from_context +ffffffff8213ae40 t dcn316_get_panel_config_defaults +ffffffff8213ae80 t read_dce_straps +ffffffff8213aeb0 t dcn31_create_audio +ffffffff8213aee0 t dcn316_stream_encoder_create +ffffffff8213b060 t dcn31_hpo_dp_stream_encoder_create +ffffffff8213b220 t dcn31_hpo_dp_link_encoder_create +ffffffff8213b2b0 t dcn31_hwseq_create +ffffffff8213c000 T dccg32_create +ffffffff8213c0b0 t dccg32_get_dccg_ref_freq +ffffffff8213c0e0 t dccg32_otg_add_pixel +ffffffff8213c120 t dccg32_otg_drop_pixel +ffffffff8213c160 t dccg32_set_dpstreamclk +ffffffff8213c4a0 t dccg32_set_dtbclk_dto +ffffffff8213c6a0 t dccg32_set_pixel_rate_div +ffffffff8213ca10 t dccg32_set_valid_pixel_rate +ffffffff8213ca80 t dccg32_trigger_dio_fifo_resync +ffffffff8213d000 T enc32_hw_init +ffffffff8213d090 T dcn32_link_encoder_enable_dp_output +ffffffff8213d0e0 T dcn32_link_encoder_construct +ffffffff8213d2d0 t dcn32_link_encoder_is_in_alt_mode +ffffffff8213d350 t dcn32_link_encoder_get_max_link_cap +ffffffff8213e000 T enc32_stream_encoder_dp_unblank +ffffffff8213e500 T enc32_enable_fifo +ffffffff8213e5a0 t enc32_reset_fifo +ffffffff8213e6a0 T dcn32_dio_stream_encoder_construct +ffffffff8213e710 t enc32_stream_encoder_hdmi_set_stream_attribute +ffffffff8213ec90 t enc32_stream_encoder_dvi_set_stream_attribute +ffffffff8213ee10 t enc32_read_state +ffffffff8213ef70 t enc32_dp_set_dsc_config +ffffffff8213efc0 t enc32_dp_set_odm_combine +ffffffff8213f000 t enc32_set_dig_input_mode +ffffffff82140000 T dpp32_construct +ffffffff82140060 t dscl32_calc_lb_num_partitions +ffffffff82141000 T hpo_dp_link_encoder32_construct +ffffffff82141060 t dcn32_hpo_dp_link_enc_is_in_alt_mode +ffffffff82142000 T hubbub32_set_request_limit +ffffffff82142130 T dcn32_program_det_size +ffffffff821422d0 T hubbub32_program_urgent_watermarks +ffffffff82142a40 T hubbub32_program_stutter_watermarks +ffffffff82142e90 T hubbub32_program_pstate_watermarks +ffffffff82143320 T hubbub32_program_usr_watermarks +ffffffff82143580 T hubbub32_force_usr_retraining_allow +ffffffff82143600 T hubbub32_force_wm_propagate_to_pipes +ffffffff821436a0 T hubbub32_init +ffffffff821437e0 T hubbub32_construct +ffffffff82143860 t hubbub32_wm_read_state +ffffffff82143c80 t hubbub32_program_watermarks +ffffffff82143d90 t hubbub32_init_watermarks +ffffffff821441d0 t dcn32_program_compbuf_size +ffffffff82144460 t dcn32_init_crb +ffffffff82145000 T hubp32_update_force_pstate_disallow +ffffffff82145090 T hubp32_update_force_cursor_pstate_disallow +ffffffff82145120 T hubp32_update_mall_sel +ffffffff821451b0 T hubp32_prepare_subvp_buffering +ffffffff82145250 T hubp32_phantom_hubp_post_enable +ffffffff82145360 T hubp32_cursor_set_attributes +ffffffff82145620 T hubp32_init +ffffffff82145650 T hubp32_construct +ffffffff82146000 T dcn32_dsc_pg_control +ffffffff82146320 T dcn32_enable_power_gating_plane +ffffffff82146590 T dcn32_hubp_pg_control +ffffffff82146800 T dcn32_apply_idle_power_optimizations +ffffffff82146af0 T dcn32_commit_subvp_config +ffffffff82146ba0 T dcn32_subvp_pipe_control_lock +ffffffff82146d70 T dcn32_subvp_pipe_control_lock_fast +ffffffff82146df0 T dcn32_set_mpc_shaper_3dlut +ffffffff82146f10 T dcn32_set_mcm_luts +ffffffff821470a0 T dcn32_set_input_transfer_func +ffffffff821471e0 T dcn32_set_output_transfer_func +ffffffff82147420 T dcn32_update_force_pstate +ffffffff82147640 T dcn32_update_mall_sel +ffffffff82147830 T dcn32_program_mall_pipe_config +ffffffff82147920 T dcn32_init_hw +ffffffff821481e0 T dcn32_update_odm +ffffffff821487e0 T dcn32_calculate_dccg_k1_k2_values +ffffffff82148a10 T dcn32_is_dp_dig_pixel_rate_div_policy +ffffffff82148ab0 T dcn32_set_pixels_per_cycle +ffffffff82148bf0 T dcn32_resync_fifo_dccg_dio +ffffffff82148d90 T dcn32_unblank_stream +ffffffff82148fa0 T dcn32_disable_link_output +ffffffff82149310 T dcn32_update_phantom_vp_position +ffffffff82149420 T dcn32_apply_update_flags_for_phantom +ffffffff821494a0 T dcn32_dsc_pg_status +ffffffff82149580 T dcn32_update_dsc_pg +ffffffff82149680 T dcn32_enable_phantom_streams +ffffffff821497c0 T dcn32_init_blank +ffffffff82149a00 T dcn32_blank_phantom +ffffffff82149b80 T dcn32_is_pipe_topology_transition_seamless +ffffffff8214a000 T dcn32_hw_sequencer_init_functions +ffffffff8214b000 T dcn32_mmhubbub_construct +ffffffff8214b050 t mmhubbub32_warmup_mcif +ffffffff8214b260 t mmhubbub32_config_mcif_buf +ffffffff8214b710 t mmhubbub32_config_mcif_arb +ffffffff8214c000 T mpc32_mpc_init +ffffffff8214c1e0 T mpc32_power_on_blnd_lut +ffffffff8214c350 T mpc32_configure_post1dlut +ffffffff8214c450 T mpc32_program_post1dluta_settings +ffffffff8214c660 T mpc32_program_post1dlutb_settings +ffffffff8214c870 T mpc32_program_post1dlut_pwl +ffffffff8214cca0 T mpc32_program_post1dlut +ffffffff8214cfb0 T mpc32_configure_shaper_lut +ffffffff8214d0d0 T mpc32_program_shaper_luta_settings +ffffffff8214df60 T mpc32_program_shaper_lutb_settings +ffffffff8214edf0 T mpc32_program_shaper_lut +ffffffff8214ef90 T mpc32_power_on_shaper_3dlut +ffffffff8214f1c0 T mpc32_program_shaper +ffffffff8214f4e0 T mpc32_select_3dlut_ram +ffffffff8214f590 T mpc32_select_3dlut_ram_mask +ffffffff8214f660 T mpc32_set3dlut_ram12 +ffffffff8214f860 T mpc32_set3dlut_ram10 +ffffffff8214f930 T mpc32_program_3dlut +ffffffff82150300 T dcn32_mpc_construct +ffffffff82151000 T optc32_set_h_timing_div_manual_mode +ffffffff82151040 T dcn32_timing_generator_init +ffffffff821510b0 t optc32_enable_crtc +ffffffff821511b0 t optc32_disable_crtc +ffffffff82151290 t optc32_phantom_crtc_post_enable +ffffffff82151350 t optc32_disable_phantom_otg +ffffffff82151390 t optc32_set_drr +ffffffff82151550 t optc32_set_odm_bypass +ffffffff821516c0 t optc32_set_odm_combine +ffffffff82152000 T dcn32_panel_cntl_create +ffffffff82152070 T dcn32_acquire_post_bldn_3dlut +ffffffff82152160 T dcn32_release_post_bldn_3dlut +ffffffff82152210 T dcn32_retain_phantom_pipes +ffffffff821522f0 T dcn32_remove_phantom_pipes +ffffffff82152460 T dcn32_add_phantom_pipes +ffffffff82152890 T dcn32_validate_bandwidth +ffffffff82152d70 T dcn32_populate_dml_pipes_from_context +ffffffff821531a0 T dcn32_calculate_wm_and_dlg +ffffffff82153210 T dcn32_create_resource_pool +ffffffff821532c0 t dcn32_resource_construct +ffffffff8215e800 T dcn32_acquire_free_pipe_as_secondary_dpp_pipe +ffffffff8215eb00 T dcn32_calc_num_avail_chans_for_mall +ffffffff8215eb70 t dcn32_mpc_create +ffffffff821631d0 t dcn32_dwbc_create +ffffffff82163bd0 t dcn32_mmhubbub_create +ffffffff82164080 t dcn32_resource_destruct +ffffffff82164710 t dcn32_destroy_resource_pool +ffffffff82164770 t dcn32_link_encoder_create +ffffffff82165840 t dcn32_update_bw_bounding_box +ffffffff82165890 t read_dce_straps +ffffffff821658c0 t dcn32_create_audio +ffffffff82165c40 t dcn32_stream_encoder_create +ffffffff82167a80 t dcn32_hpo_dp_stream_encoder_create +ffffffff82168860 t dcn32_hpo_dp_link_encoder_create +ffffffff82168cb0 t dcn32_hwseq_create +ffffffff821691a0 t dcn32_vpg_create +ffffffff8216a000 T dcn32_helper_mall_bytes_to_ways +ffffffff8216a060 T dcn32_helper_calculate_mall_bytes_for_cursor +ffffffff8216a100 T dcn32_helper_calculate_num_ways_for_subvp +ffffffff8216a180 T dcn32_merge_pipes_for_subvp +ffffffff8216a340 T dcn32_all_pipes_have_stream_and_plane +ffffffff8216a3d0 T dcn32_subvp_in_use +ffffffff8216a460 T dcn32_mpo_in_use +ffffffff8216a4d0 T dcn32_any_surfaces_rotated +ffffffff8216a560 T dcn32_is_center_timing +ffffffff8216a5d0 T dcn32_is_psr_capable +ffffffff8216a620 T dcn32_determine_det_override +ffffffff8216a960 T dcn32_set_det_allocations +ffffffff8216aaf0 T dcn32_save_mall_state +ffffffff8216aba0 T dcn32_restore_mall_state +ffffffff8216ac50 T dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch +ffffffff8216ae00 t is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch +ffffffff8216aeb0 T dcn32_check_native_scaling_for_res +ffffffff8216af10 T dcn32_subvp_drr_admissable +ffffffff8216b0d0 T dcn32_subvp_vblank_admissable +ffffffff8216c000 T dcn321_link_encoder_construct +ffffffff8216d000 T dcn321_create_resource_pool +ffffffff8216d0b0 t dcn321_resource_construct +ffffffff82178550 t dcn321_mpc_create +ffffffff8217cbb0 t dcn321_dwbc_create +ffffffff8217d5b0 t dcn321_mmhubbub_create +ffffffff8217da60 t dcn321_resource_destruct +ffffffff8217e0f0 t dcn321_destroy_resource_pool +ffffffff8217e150 t dcn321_link_encoder_create +ffffffff8217f220 t dcn321_update_bw_bounding_box +ffffffff8217f270 t read_dce_straps +ffffffff8217f2a0 t dcn321_create_audio +ffffffff8217f620 t dcn321_stream_encoder_create +ffffffff82181460 t dcn321_hpo_dp_stream_encoder_create +ffffffff82182240 t dcn321_hpo_dp_link_encoder_create +ffffffff82182690 t dcn321_hwseq_create +ffffffff82182b80 t dcn321_vpg_create +ffffffff82183000 T bw_int_to_fixed_nonconst +ffffffff82183090 T bw_frc_to_fixed +ffffffff82183260 T bw_floor2 +ffffffff82183310 T bw_ceil2 +ffffffff82183390 T bw_mul +ffffffff82184000 T convert_to_custom_float_format +ffffffff82185000 T bw_calcs_init +ffffffff82185e60 T bw_calcs +ffffffff82187800 t calculate_bandwidth +ffffffff8218f000 T scaler_settings_calculation +ffffffff8218f350 T mode_support_and_system_configuration +ffffffff82195180 T display_pipe_configuration +ffffffff82195ab0 T dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation +ffffffff8219b000 T dcn_bw_mod +ffffffff8219b060 T dcn_bw_min2 +ffffffff8219b0a0 T dcn_bw_max +ffffffff8219b0d0 T dcn_bw_max2 +ffffffff8219b110 T dcn_bw_floor2 +ffffffff8219b1b0 T dcn_bw_floor +ffffffff8219b1e0 T dcn_bw_ceil +ffffffff8219b220 T dcn_bw_ceil2 +ffffffff8219b2d0 T dcn_bw_max3 +ffffffff8219b350 T dcn_bw_max5 +ffffffff8219b490 T dcn_bw_pow +ffffffff8219b520 T dcn_bw_fabs +ffffffff8219b560 T dcn_bw_log +ffffffff8219c000 T swizzle_mode_to_macro_tile_size +ffffffff8219c090 T dcn_validate_bandwidth +ffffffff8219e300 T dcn_bw_sync_calcs_and_dml +ffffffff8219e550 t dcn_bw_calc_rq_dlg_ttu +ffffffff8219ed20 T dcn_find_dcfclk_suits_all +ffffffff8219f180 T dcn_bw_update_from_pplib_fclks +ffffffff8219f300 T dcn_bw_update_from_pplib_dcfclks +ffffffff8219f3d0 T dcn_get_soc_clks +ffffffff8219f450 T dcn_bw_notify_pplib_of_wm_ranges +ffffffff821a0000 T dcn10_resource_construct_fp +ffffffff821a1000 T dcn20_populate_dml_writeback_from_context +ffffffff821a1180 T dcn20_fpu_set_wb_arb_params +ffffffff821a1330 T dcn20_calculate_dlg_params +ffffffff821a1b70 T dcn20_populate_dml_pipes_from_context +ffffffff821a2a80 T dcn20_calculate_wm +ffffffff821a3270 T dcn20_update_bounding_box +ffffffff821a34f0 T dcn20_cap_soc_clocks +ffffffff821a3850 T dcn20_patch_bounding_box +ffffffff821a3a40 T dcn20_validate_bandwidth_fp +ffffffff821a3be0 t dcn20_validate_bandwidth_internal +ffffffff821a3fe0 T dcn20_fpu_set_wm_ranges +ffffffff821a4080 T dcn20_fpu_adjust_dppclk +ffffffff821a4120 T dcn21_populate_dml_pipes_from_context +ffffffff821a4230 T dcn21_validate_bandwidth_fp +ffffffff821a4cc0 T dcn21_update_bw_bounding_box +ffffffff821a50d0 T dcn21_clk_mgr_set_bw_params_wm_table +ffffffff821a5130 T dcn201_populate_dml_writeback_from_context_fpu +ffffffff821a5430 t calculate_wm_set_for_vlevel +ffffffff821a6000 T dml20_recalculate +ffffffff821a6740 t dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation +ffffffff821abbe0 T dml20_ModeSupportAndSystemConfigurationFull +ffffffff821b3040 t TruncToValidBPP +ffffffff821b3220 t CalculateVMAndRowBytes +ffffffff821b38e0 t CalculatePrefetchSourceLines +ffffffff821b3ab0 t CalculateWriteBackDelay +ffffffff821b3d80 t CalculatePrefetchSchedule +ffffffff821b4c30 t CalculateFlipSchedule +ffffffff821b5000 t adjust_ReturnBW +ffffffff821b6000 T dml20v2_recalculate +ffffffff821b6740 t dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation +ffffffff821bbd60 T dml20v2_ModeSupportAndSystemConfigurationFull +ffffffff821c3140 t TruncToValidBPP +ffffffff821c36d0 t CalculateVMAndRowBytes +ffffffff821c3d90 t CalculatePrefetchSourceLines +ffffffff821c3f60 t CalculateWriteBackDelay +ffffffff821c4230 t CalculateDelayAfterScaler +ffffffff821c4590 t CalculatePrefetchSchedule +ffffffff821c52b0 t CalculateFlipSchedule +ffffffff821c5680 t adjust_ReturnBW +ffffffff821c6000 T dml20_rq_dlg_get_rq_reg +ffffffff821c6490 t dml20_rq_dlg_get_rq_params +ffffffff821c6660 T dml20_rq_dlg_get_dlg_reg +ffffffff821c8550 t get_surf_rq_param +ffffffff821c8db0 t calculate_ttu_cursor +ffffffff821ca000 T dml20v2_rq_dlg_get_rq_reg +ffffffff821ca490 t dml20v2_rq_dlg_get_rq_params +ffffffff821ca660 T dml20v2_rq_dlg_get_dlg_reg +ffffffff821cc560 t get_surf_rq_param +ffffffff821ccdc0 t calculate_ttu_cursor +ffffffff821ce000 T dml21_recalculate +ffffffff821ce710 t DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation +ffffffff821d3ed0 T dml21_ModeSupportAndSystemConfigurationFull +ffffffff821da380 t TruncToValidBPP +ffffffff821da910 t CalculateDCFCLKDeepSleep +ffffffff821dac50 t CalculateVMAndRowBytes +ffffffff821db4b0 t CalculatePrefetchSourceLines +ffffffff821db680 t CalculateWriteBackDelay +ffffffff821db950 t CalculatePrefetchSchedulePerPlane +ffffffff821dc190 t CalculateUrgentBurstFactor +ffffffff821dc5a0 t CalculateFlipSchedule +ffffffff821dca80 t CalculateWatermarksAndDRAMSpeedChangeSupport +ffffffff821dda70 t CalculatePrefetchSchedule +ffffffff821e0000 T dml21_rq_dlg_get_rq_reg +ffffffff821e0490 t dml_rq_dlg_get_rq_params +ffffffff821e0660 T dml21_rq_dlg_get_dlg_reg +ffffffff821e2930 t get_surf_rq_param +ffffffff821e3250 t calculate_ttu_cursor +ffffffff821e4000 T optc3_fpu_set_vrr_m_const +ffffffff821e44a0 T dcn30_fpu_populate_dml_writeback_from_context +ffffffff821e47b0 T dcn30_fpu_set_mcif_arb_params +ffffffff821e4920 T dcn30_fpu_update_soc_for_wm_a +ffffffff821e49f0 T dcn30_fpu_calculate_wm_and_dlg +ffffffff821e5480 T dcn30_find_dummy_latency_index_for_fw_based_mclk_switch +ffffffff821e5670 T dcn30_fpu_update_dram_channel_width_bytes +ffffffff821e56d0 T dcn30_fpu_update_max_clk +ffffffff821e5780 T dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk +ffffffff821e5880 T dcn30_fpu_update_bw_bounding_box +ffffffff821e5a60 T dcn3_fpu_build_wm_range_table +ffffffff821e5d40 T patch_dcn30_soc_bounding_box +ffffffff821e6000 T dml30_recalculate +ffffffff821e65f0 t DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation +ffffffff821ed0b0 T dml30_CalculateBytePerPixelAnd256BBlockSizes +ffffffff821ed320 T dml30_CalculateWriteBackDISPCLK +ffffffff821ed490 t dml_max3 +ffffffff821ed4f0 T dml30_ModeSupportAndSystemConfigurationFull +ffffffff821f5040 t CalculateSwathAndDETConfiguration +ffffffff821f5740 t TruncToValidBPP +ffffffff821f59a0 t CalculateVMAndRowBytes +ffffffff821f6010 t CalculatePrefetchSourceLines +ffffffff821f61e0 t CalculateUrgentBurstFactor +ffffffff821f6470 t CalculateDCFCLKDeepSleep +ffffffff821f6790 t UseMinimumDCFCLK +ffffffff821f7ab0 t CalculatePrefetchSchedule +ffffffff821f8f50 t CalculateFlipSchedule +ffffffff821f9450 t CalculateWatermarksAndDRAMSpeedChangeSupport +ffffffff821fa190 t CalculateSwathWidth +ffffffff821fb000 T dml30_rq_dlg_get_rq_reg +ffffffff821fb4b0 t dml_rq_dlg_get_rq_params +ffffffff821fb740 T dml30_rq_dlg_get_dlg_reg +ffffffff821fde10 t get_surf_rq_param +ffffffff821fe7a0 t calculate_ttu_cursor +ffffffff821ff000 T dcn301_update_bw_bounding_box +ffffffff821ff2e0 T dcn301_fpu_set_wm_ranges +ffffffff821ff380 T dcn301_fpu_init_soc_bounding_box +ffffffff821ff420 T dcn301_calculate_wm_and_dlg_fp +ffffffff821ff750 t calculate_wm_set_for_vlevel +ffffffff82200000 T dcn302_fpu_update_bw_bounding_box +ffffffff82200940 T dcn302_fpu_init_soc_bounding_box +ffffffff82201000 T dcn303_fpu_update_bw_bounding_box +ffffffff822019a0 T dcn303_fpu_init_soc_bounding_box +ffffffff82202000 T dcn31_zero_pipe_dcc_fraction +ffffffff82202060 T dcn31_update_soc_for_wm_a +ffffffff82202110 T dcn315_update_soc_for_wm_a +ffffffff822021e0 T dcn31_calculate_wm_and_dlg_fp +ffffffff82202840 T dcn31_update_bw_bounding_box +ffffffff82202be0 T dcn315_update_bw_bounding_box +ffffffff82202ed0 T dcn316_update_bw_bounding_box +ffffffff82203280 T dcn_get_max_non_odm_pix_rate_100hz +ffffffff822032e0 T dcn_get_approx_det_segs_required_for_pstate +ffffffff82204000 T dml31_recalculate +ffffffff822042d0 t DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation +ffffffff8220b190 T dml31_CalculateWriteBackDISPCLK +ffffffff8220b300 t dml_max3 +ffffffff8220b360 T dml31_ModeSupportAndSystemConfigurationFull +ffffffff82213440 t CalculateSwathAndDETConfiguration +ffffffff82213aa0 t TruncToValidBPP +ffffffff82213cf0 t CalculateDCFCLKDeepSleep +ffffffff82214010 t CalculateVMAndRowBytes +ffffffff82214650 t CalculatePrefetchSourceLines +ffffffff82214820 t CalculateUrgentBurstFactor +ffffffff82214ab0 t UseMinimumDCFCLK +ffffffff82215a40 t CalculatePrefetchSchedulePerPlane +ffffffff822161a0 t CalculateFlipSchedule +ffffffff82216730 t CalculateWatermarksAndDRAMSpeedChangeSupport +ffffffff82217350 t CalculateSwathWidth +ffffffff82217860 t CalculatePrefetchSchedule +ffffffff82218c40 t CalculateVupdateAndDynamicMetadataParameters +ffffffff82219000 T dml31_rq_dlg_get_rq_reg +ffffffff822194b0 t dml_rq_dlg_get_rq_params +ffffffff82219740 T dml31_rq_dlg_get_dlg_reg +ffffffff8221c100 t get_surf_rq_param +ffffffff8221d000 T dcn314_update_bw_bounding_box_fpu +ffffffff8221d3f0 T dcn314_populate_dml_pipes_from_context_fpu +ffffffff8221e000 T dml314_recalculate +ffffffff8221e270 t DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation +ffffffff82225050 T dml314_CalculateWriteBackDISPCLK +ffffffff822251c0 t dml_max3 +ffffffff82225220 T dml314_ModeSupportAndSystemConfigurationFull +ffffffff8222d5a0 t CalculateBytePerPixelAnd256BBlockSizes +ffffffff8222d810 t CalculateSwathAndDETConfiguration +ffffffff8222de50 t TruncToValidBPP +ffffffff8222e0a0 t CalculateDCFCLKDeepSleep +ffffffff8222e3c0 t CalculateVMAndRowBytes +ffffffff8222ea00 t CalculatePrefetchSourceLines +ffffffff8222ebd0 t CalculateUrgentBurstFactor +ffffffff8222ee60 t CalculateMaxVStartup +ffffffff8222efa0 t UseMinimumDCFCLK +ffffffff8222ff30 t CalculatePrefetchSchedulePerPlane +ffffffff82230690 t CalculateFlipSchedule +ffffffff82230c20 t CalculateWatermarksAndDRAMSpeedChangeSupport +ffffffff82231840 t CalculateSwathWidth +ffffffff82231d50 t CalculatePrefetchSchedule +ffffffff82233130 t CalculateVupdateAndDynamicMetadataParameters +ffffffff82234000 T dml314_rq_dlg_get_rq_reg +ffffffff822344b0 t dml_rq_dlg_get_rq_params +ffffffff82234740 T dml314_rq_dlg_get_dlg_reg +ffffffff82237100 t get_surf_rq_param +ffffffff82238000 T dcn32_build_wm_range_table_fpu +ffffffff82238390 T dcn32_find_dummy_latency_index_for_fw_based_mclk_switch +ffffffff82238540 T dcn32_internal_validate_bw +ffffffff8223a3b0 T dcn32_helper_populate_phantom_dlg_params +ffffffff8223a550 T dcn32_predict_pipe_split +ffffffff8223a780 T dcn32_set_phantom_stream_timing +ffffffff8223aa90 T dcn32_determine_max_vratio_prefetch +ffffffff8223ab70 t dcn32_split_stream_for_mpc_or_odm +ffffffff8223af20 T dcn32_calculate_wm_and_dlg_fpu +ffffffff8223c650 T dcn32_patch_dpm_table +ffffffff8223c860 T dcn32_update_bw_bounding_box_fpu +ffffffff8223eed0 T dcn32_zero_pipe_dcc_fraction +ffffffff8223ef30 T dcn32_allow_subvp_with_active_margin +ffffffff8223f000 T dcn32_allow_subvp_high_refresh_rate +ffffffff8223f200 T dcn32_assign_fpo_vactive_candidate +ffffffff8223f2c0 T dcn32_find_vactive_pipe +ffffffff8223f430 T dcn32_set_clock_limits +ffffffff8223f480 T dcn32_override_min_req_memclk +ffffffff8223f540 t subvp_drr_schedulable +ffffffff8223f7d0 t get_optimal_ntuple +ffffffff82240000 T dml32_recalculate +ffffffff82244320 T dml32_ModeSupportAndSystemConfigurationFull +ffffffff8224c000 T dml32_dscceComputeDelay +ffffffff8224c140 T dml32_dscComputeDelay +ffffffff8224c180 T IsVertical +ffffffff8224c1b0 T dml32_CalculateSinglePipeDPPCLKAndSCLThroughput +ffffffff8224c4d0 t dml_max3 +ffffffff8224c530 T dml32_CalculateBytePerPixelAndBlockSizes +ffffffff8224c860 T dml32_CalculateSwathAndDETConfiguration +ffffffff8224d090 T dml32_CalculateSwathWidth +ffffffff8224d950 T dml32_UnboundedRequest +ffffffff8224d9c0 T dml32_CalculateDETBufferSize +ffffffff8224e000 T dml32_CalculateODMMode +ffffffff8224e780 T dml32_CalculateRequiredDispclk +ffffffff8224e940 T dml32_RoundToDFSGranularity +ffffffff8224e9d0 T dml32_CalculateOutputLink +ffffffff8224f440 T dml32_TruncToValidBPP +ffffffff8224f770 T dml32_CalculateDPPCLK +ffffffff8224f910 T dml32_RequiredDTBCLK +ffffffff8224fb60 t dml_max4 +ffffffff8224fbe0 T dml32_DSCDelayRequirement +ffffffff822500a0 T dml32_CalculateSurfaceSizeInMall +ffffffff82250bf0 T dml32_CalculateVMRowAndSwath +ffffffff82251a00 T dml32_CalculateVMAndRowBytes +ffffffff82252650 T dml32_CalculatePrefetchSourceLines +ffffffff822528a0 T dml32_CalculateMALLUseForStaticScreen +ffffffff822529e0 T dml32_CalculateRowBandwidth +ffffffff82252b40 T dml32_CalculateUrgentLatency +ffffffff82252bf0 T dml32_CalculateUrgentBurstFactor +ffffffff82252ea0 T dml32_CalculateDCFCLKDeepSleep +ffffffff822531f0 T dml32_CalculateWriteBackDelay +ffffffff82253350 T dml32_UseMinimumDCFCLK +ffffffff822543c0 T dml32_CalculateExtraLatencyBytes +ffffffff82254580 T dml32_CalculateTWait +ffffffff82254670 T dml32_CalculateVUpdateAndDynamicMetadataParameters +ffffffff822548d0 T dml32_get_return_bw_mbps +ffffffff82254a90 T dml32_get_return_bw_mbps_vm_only +ffffffff82254b70 T dml32_CalculateExtraLatency +ffffffff82254d90 T dml32_CalculatePrefetchSchedule +ffffffff822563a0 T dml32_CalculateFlipSchedule +ffffffff82256900 T dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport +ffffffff82257a10 T dml32_CalculateWriteBackDISPCLK +ffffffff82257be0 T dml32_CalculateMinAndMaxPrefetchMode +ffffffff82257c30 T dml32_CalculatePixelDeliveryTimes +ffffffff822580b0 T dml32_CalculateMetaAndPTETimes +ffffffff82258810 T dml32_CalculateVMGroupAndRequestTimes +ffffffff82258d50 T dml32_CalculateDCCConfiguration +ffffffff82259360 T dml32_CalculateStutterEfficiency +ffffffff8225a280 T dml32_CalculateMaxDETAndMinCompressedBufferSize +ffffffff8225a370 T dml32_CalculateVActiveBandwithSupport +ffffffff8225a4e0 T dml32_CalculatePrefetchBandwithSupport +ffffffff8225a800 T dml32_CalculateBandwidthAvailableForImmediateFlip +ffffffff8225a950 T dml32_CalculateImmediateFlipBandwithSupport +ffffffff8225abd0 T dml32_CalculateDETSwathFillLatencyHiding +ffffffff8225b000 T dml32_rq_dlg_get_rq_reg +ffffffff8225b6a0 T dml32_rq_dlg_get_dlg_reg +ffffffff8225e000 T dcn321_update_bw_bounding_box_fpu +ffffffff82260760 t get_optimal_ntuple +ffffffff82261000 T dml_init_instance +ffffffff82261310 T dml_get_status_message +ffffffff82261350 T dml_log_pipe_params +ffffffff82261380 T dml_log_mode_support_params +ffffffff82262000 T dml_get_voltage_level +ffffffff82262240 t fetch_socbb_params +ffffffff82262730 t fetch_ip_params +ffffffff82262bd0 t fetch_pipe_params +ffffffff82263c50 T PixelClockAdjustmentForProgressiveToInterlaceUnit +ffffffff82263cd0 T get_clk_dcf_deepsleep +ffffffff82263de0 T get_wm_urgent +ffffffff82263ef0 T get_wm_memory_trip +ffffffff82264000 T get_wm_writeback_urgent +ffffffff82264110 T get_wm_stutter_exit +ffffffff82264220 T get_wm_stutter_enter_exit +ffffffff82264330 T get_wm_z8_stutter_exit +ffffffff82264440 T get_wm_z8_stutter_enter_exit +ffffffff82264550 T get_stutter_efficiency_z8 +ffffffff82264660 T get_stutter_num_bursts_z8 +ffffffff82264770 T get_wm_dram_clock_change +ffffffff82264880 T get_wm_writeback_dram_clock_change +ffffffff82264990 T get_stutter_efficiency +ffffffff82264aa0 T get_stutter_efficiency_no_vblank +ffffffff82264bb0 T get_stutter_period +ffffffff82264cc0 T get_urgent_latency +ffffffff82264dd0 T get_urgent_extra_latency +ffffffff82264ee0 T get_nonurgent_latency +ffffffff82264ff0 T get_dram_clock_change_latency +ffffffff82265100 T get_dispclk_calculated +ffffffff82265210 T get_total_data_read_bw +ffffffff82265320 T get_return_bw +ffffffff82265430 T get_tcalc +ffffffff82265540 T get_fraction_of_urgent_bandwidth +ffffffff82265650 T get_fraction_of_urgent_bandwidth_imm_flip +ffffffff82265760 T get_cstate_max_cap_mode +ffffffff82265880 T get_comp_buffer_size_kbytes +ffffffff82265990 T get_pixel_chunk_size_in_kbyte +ffffffff82265ab0 T get_alpha_pixel_chunk_size_in_kbyte +ffffffff82265bd0 T get_meta_chunk_size_in_kbyte +ffffffff82265cf0 T get_min_pixel_chunk_size_in_byte +ffffffff82265e00 T get_min_meta_chunk_size_in_byte +ffffffff82265f20 T get_fclk_watermark +ffffffff82266030 T get_usr_retraining_watermark +ffffffff82266140 T get_comp_buffer_reserved_space_kbytes +ffffffff82266260 T get_comp_buffer_reserved_space_64bytes +ffffffff82266380 T get_comp_buffer_reserved_space_zs +ffffffff822664a0 T get_unbounded_request_enabled +ffffffff822665c0 T get_dsc_delay +ffffffff822666f0 T get_dppclk_calculated +ffffffff82266810 T get_dscclk_calculated +ffffffff82266930 T get_min_ttu_vblank +ffffffff82266a50 T get_min_ttu_vblank_in_us +ffffffff82266b70 T get_vratio_prefetch_l +ffffffff82266c90 T get_vratio_prefetch_c +ffffffff82266db0 T get_dst_x_after_scaler +ffffffff82266ed0 T get_dst_y_after_scaler +ffffffff82266ff0 T get_dst_y_per_vm_vblank +ffffffff82267110 T get_dst_y_per_row_vblank +ffffffff82267230 T get_dst_y_prefetch +ffffffff82267350 T get_dst_y_per_vm_flip +ffffffff82267470 T get_dst_y_per_row_flip +ffffffff82267590 T get_refcyc_per_vm_group_vblank +ffffffff822676b0 T get_refcyc_per_vm_group_flip +ffffffff822677d0 T get_refcyc_per_vm_req_vblank +ffffffff822678f0 T get_refcyc_per_vm_req_flip +ffffffff82267a10 T get_refcyc_per_vm_group_vblank_in_us +ffffffff82267b30 T get_refcyc_per_vm_group_flip_in_us +ffffffff82267c50 T get_refcyc_per_vm_req_vblank_in_us +ffffffff82267d70 T get_refcyc_per_vm_req_flip_in_us +ffffffff82267e90 T get_refcyc_per_vm_dmdata_in_us +ffffffff82267fb0 T get_dmdata_dl_delta_in_us +ffffffff822680d0 T get_refcyc_per_line_delivery_l_in_us +ffffffff822681f0 T get_refcyc_per_line_delivery_c_in_us +ffffffff82268310 T get_refcyc_per_line_delivery_pre_l_in_us +ffffffff82268430 T get_refcyc_per_line_delivery_pre_c_in_us +ffffffff82268550 T get_refcyc_per_req_delivery_l_in_us +ffffffff82268670 T get_refcyc_per_req_delivery_c_in_us +ffffffff82268790 T get_refcyc_per_req_delivery_pre_l_in_us +ffffffff822688b0 T get_refcyc_per_req_delivery_pre_c_in_us +ffffffff822689d0 T get_refcyc_per_cursor_req_delivery_in_us +ffffffff82268af0 T get_refcyc_per_cursor_req_delivery_pre_in_us +ffffffff82268c10 T get_refcyc_per_meta_chunk_nom_l_in_us +ffffffff82268d30 T get_refcyc_per_meta_chunk_nom_c_in_us +ffffffff82268e50 T get_refcyc_per_meta_chunk_vblank_l_in_us +ffffffff82268f70 T get_refcyc_per_meta_chunk_vblank_c_in_us +ffffffff82269090 T get_refcyc_per_meta_chunk_flip_l_in_us +ffffffff822691b0 T get_refcyc_per_meta_chunk_flip_c_in_us +ffffffff822692d0 T get_vstartup +ffffffff82269400 T get_vupdate_offset +ffffffff82269530 T get_vupdate_width +ffffffff82269650 T get_vready_offset +ffffffff82269770 T get_vready_at_or_after_vsync +ffffffff822698a0 T get_min_dst_y_next_start +ffffffff822699d0 T get_dst_y_per_pte_row_nom_l +ffffffff82269af0 T get_dst_y_per_pte_row_nom_c +ffffffff82269c10 T get_dst_y_per_meta_row_nom_l +ffffffff82269d30 T get_dst_y_per_meta_row_nom_c +ffffffff82269e50 T get_refcyc_per_pte_group_nom_l_in_us +ffffffff82269f70 T get_refcyc_per_pte_group_nom_c_in_us +ffffffff8226a090 T get_refcyc_per_pte_group_vblank_l_in_us +ffffffff8226a1b0 T get_refcyc_per_pte_group_vblank_c_in_us +ffffffff8226a2d0 T get_refcyc_per_pte_group_flip_l_in_us +ffffffff8226a3f0 T get_refcyc_per_pte_group_flip_c_in_us +ffffffff8226a510 T get_vstartup_calculated +ffffffff8226a640 T get_dpte_row_height_linear_c +ffffffff8226a770 T get_swath_height_l +ffffffff8226a8a0 T get_swath_height_c +ffffffff8226a9d0 T get_det_stored_buffer_size_l_bytes +ffffffff8226ab00 T get_det_stored_buffer_size_c_bytes +ffffffff8226ac30 T get_dpte_group_size_in_bytes +ffffffff8226ad60 T get_vm_group_size_in_bytes +ffffffff8226ae90 T get_dpte_row_height_linear_l +ffffffff8226afc0 T get_pte_buffer_mode +ffffffff8226b0f0 T get_subviewport_lines_needed_in_mall +ffffffff8226b220 T get_surface_size_in_mall +ffffffff8226b350 T get_total_immediate_flip_bytes +ffffffff8226b470 T get_total_immediate_flip_bw +ffffffff8226b650 T get_total_prefetch_bw +ffffffff8226b830 T get_total_surface_size_in_mall_bytes +ffffffff8226b9d0 T get_det_buffer_size_kbytes +ffffffff8226bb00 T get_is_phantom_pipe +ffffffff8226bc30 T Calculate256BBlockSizes +ffffffff8226bd20 T CalculateMinAndMaxPrefetchMode +ffffffff8226bda0 T ModeSupportAndSystemConfiguration +ffffffff8226c0b0 T CalculateWriteBackDISPCLK +ffffffff8226d000 T print__rq_params_st +ffffffff8226d030 T print__data_rq_sizing_params_st +ffffffff8226d060 T print__data_rq_dlg_params_st +ffffffff8226d090 T print__data_rq_misc_params_st +ffffffff8226d0c0 T print__rq_dlg_params_st +ffffffff8226d0f0 T print__dlg_sys_params_st +ffffffff8226d120 T print__data_rq_regs_st +ffffffff8226d150 T print__rq_regs_st +ffffffff8226d180 T print__dlg_regs_st +ffffffff8226d1b0 T print__ttu_regs_st +ffffffff8226e000 T dml1_extract_rq_regs +ffffffff8226e330 T dml1_rq_dlg_get_rq_params +ffffffff8226e510 t get_surf_rq_param +ffffffff8226f0c0 T dml1_rq_dlg_get_dlg_params +ffffffff82272000 T _do_calc_rc_params +ffffffff82272fc0 t get_qp_set +ffffffff82274000 T dc_bandwidth_in_kbps_from_timing +ffffffff82274290 T dc_dsc_stream_bandwidth_in_kbps +ffffffff822743e0 T dc_dsc_parse_dsc_dpcd +ffffffff82274680 t dsc_throughput_from_dpcd +ffffffff82274840 T dc_dsc_compute_bandwidth_range +ffffffff82274a30 t intersect_dsc_caps +ffffffff82274c00 t setup_dsc_config +ffffffff822753d0 T dc_dsc_compute_config +ffffffff822754c0 T dc_dsc_stream_bandwidth_overhead_in_kbps +ffffffff82275600 T dc_dsc_get_policy_for_timing +ffffffff822756a0 T dc_dsc_policy_set_max_target_bpp_limit +ffffffff822756d0 T dc_dsc_policy_set_enable_dsc_when_not_needed +ffffffff82275700 T dc_dsc_policy_set_disable_dsc_stream_overhead +ffffffff82275730 T dc_set_disable_128b_132b_stream_overhead +ffffffff82275760 T dc_dsc_get_default_config_option +ffffffff822757b0 t fit_num_slices_up +ffffffff82275860 t decide_dsc_target_bpp_x16 +ffffffff82276000 T calc_rc_params +ffffffff82277000 T dscc_compute_dsc_parameters +ffffffff82278000 T dal_hw_factory_dce110_init ffffffff82278060 t define_hpd_registers ffffffff822780b0 t define_ddc_registers -ffffffff82279000 T dal_hw_translate_dce120_init +ffffffff82279000 T dal_hw_translate_dce110_init ffffffff82279030 t offset_to_id -ffffffff822793a0 t id_to_offset -ffffffff8227a000 T dal_hw_factory_dce80_init +ffffffff82279390 t id_to_offset +ffffffff8227a000 T dal_hw_factory_dce120_init ffffffff8227a060 t define_hpd_registers ffffffff8227a0b0 t define_ddc_registers -ffffffff8227b000 T dal_hw_translate_dce80_init +ffffffff8227b000 T dal_hw_translate_dce120_init ffffffff8227b030 t offset_to_id -ffffffff8227b7b0 t id_to_offset -ffffffff8227c000 T dal_hw_factory_dcn10_init +ffffffff8227b3a0 t id_to_offset +ffffffff8227c000 T dal_hw_factory_dce80_init ffffffff8227c060 t define_hpd_registers ffffffff8227c0b0 t define_ddc_registers -ffffffff8227c150 t define_generic_registers -ffffffff8227d000 T dal_hw_translate_dcn10_init +ffffffff8227d000 T dal_hw_translate_dce80_init ffffffff8227d030 t offset_to_id -ffffffff8227d390 t id_to_offset -ffffffff8227e000 T dal_hw_factory_dcn20_init +ffffffff8227d7b0 t id_to_offset +ffffffff8227e000 T dal_hw_factory_dcn10_init ffffffff8227e060 t define_hpd_registers ffffffff8227e0b0 t define_ddc_registers -ffffffff8227e160 t define_generic_registers -ffffffff8227f000 T dal_hw_translate_dcn20_init +ffffffff8227e150 t define_generic_registers +ffffffff8227f000 T dal_hw_translate_dcn10_init ffffffff8227f030 t offset_to_id -ffffffff8227f2b0 t id_to_offset -ffffffff82280000 T dal_hw_factory_dcn21_init +ffffffff8227f390 t id_to_offset +ffffffff82280000 T dal_hw_factory_dcn20_init ffffffff82280060 t define_hpd_registers ffffffff822800b0 t define_ddc_registers ffffffff82280160 t define_generic_registers -ffffffff82281000 T dal_hw_translate_dcn21_init +ffffffff82281000 T dal_hw_translate_dcn20_init ffffffff82281030 t offset_to_id ffffffff822812b0 t id_to_offset -ffffffff82282000 T dal_hw_factory_dcn30_init +ffffffff82282000 T dal_hw_factory_dcn21_init ffffffff82282060 t define_hpd_registers ffffffff822820b0 t define_ddc_registers ffffffff82282160 t define_generic_registers -ffffffff82283000 T dal_hw_translate_dcn30_init +ffffffff82283000 T dal_hw_translate_dcn21_init ffffffff82283030 t offset_to_id -ffffffff822832c0 t id_to_offset -ffffffff82284000 T dal_hw_factory_dcn315_init +ffffffff822832b0 t id_to_offset +ffffffff82284000 T dal_hw_factory_dcn30_init ffffffff82284060 t define_hpd_registers ffffffff822840b0 t define_ddc_registers ffffffff82284160 t define_generic_registers -ffffffff82285000 T dal_hw_translate_dcn315_init +ffffffff82285000 T dal_hw_translate_dcn30_init ffffffff82285030 t offset_to_id -ffffffff822852b0 t id_to_offset -ffffffff82286000 T dal_hw_factory_dcn32_init +ffffffff822852c0 t id_to_offset +ffffffff82286000 T dal_hw_factory_dcn315_init ffffffff82286060 t define_hpd_registers ffffffff822860b0 t define_ddc_registers ffffffff82286160 t define_generic_registers -ffffffff82287000 T dal_hw_translate_dcn32_init +ffffffff82287000 T dal_hw_translate_dcn315_init ffffffff82287030 t offset_to_id -ffffffff82287290 t id_to_offset -ffffffff82288000 T dal_gpio_open -ffffffff822880c0 T dal_gpio_open_ex -ffffffff82288180 T dal_gpio_get_value -ffffffff82288200 T dal_gpio_set_value -ffffffff82288280 T dal_gpio_get_mode -ffffffff822882b0 T dal_gpio_lock_pin -ffffffff822882d0 T dal_gpio_unlock_pin -ffffffff822882f0 T dal_gpio_change_mode -ffffffff82288370 T dal_gpio_get_id -ffffffff822883a0 T dal_gpio_get_enum -ffffffff822883d0 T dal_gpio_set_config -ffffffff82288450 T dal_gpio_get_pin_info -ffffffff822884b0 T dal_gpio_get_sync_source -ffffffff82288540 T dal_gpio_get_output_state -ffffffff82288570 T dal_gpio_get_ddc -ffffffff822885a0 T dal_gpio_get_hpd -ffffffff822885d0 T dal_gpio_get_generic -ffffffff82288600 T dal_gpio_close -ffffffff82288650 T dal_gpio_create -ffffffff822887e0 T dal_gpio_destroy -ffffffff82289000 T dal_gpio_service_create -ffffffff82289240 T dal_gpio_service_create_irq -ffffffff82289300 T dal_gpio_create_irq -ffffffff82289380 T dal_gpio_service_create_generic_mux -ffffffff82289420 T dal_gpio_destroy_generic_mux -ffffffff822894b0 T dal_gpio_get_generic_pin_info -ffffffff82289510 T dal_gpio_service_destroy -ffffffff82289640 T dal_mux_setup_config -ffffffff822896a0 T dal_gpio_service_lock -ffffffff82289720 T dal_gpio_service_unlock -ffffffff822897a0 T dal_gpio_service_open -ffffffff822899e0 T dal_gpio_service_close -ffffffff82289a80 T dal_irq_get_source -ffffffff82289af0 T dal_irq_get_rx_source -ffffffff82289b40 T dal_irq_setup_hpd_filter -ffffffff82289ba0 T dal_gpio_destroy_irq -ffffffff82289c30 T dal_gpio_create_ddc -ffffffff82289da0 T dal_gpio_destroy_ddc -ffffffff82289e70 T dal_ddc_close -ffffffff82289ec0 T dal_ddc_open -ffffffff8228a020 T dal_ddc_change_mode -ffffffff8228a0c0 T dal_ddc_get_line -ffffffff8228a0e0 T dal_ddc_set_config -ffffffff8228b000 T dal_hw_ddc_init -ffffffff8228b100 T dal_hw_ddc_get_pin -ffffffff8228b110 t dal_hw_ddc_destroy -ffffffff8228b170 t set_config -ffffffff8228c000 T dal_hw_factory_init -ffffffff8228d000 T dal_hw_generic_init -ffffffff8228d100 T dal_hw_generic_get_pin -ffffffff8228d110 t dal_hw_generic_destroy +ffffffff822872b0 t id_to_offset +ffffffff82288000 T dal_hw_factory_dcn32_init +ffffffff82288060 t define_hpd_registers +ffffffff822880b0 t define_ddc_registers +ffffffff82288160 t define_generic_registers +ffffffff82289000 T dal_hw_translate_dcn32_init +ffffffff82289030 t offset_to_id +ffffffff82289290 t id_to_offset +ffffffff8228a000 T dal_gpio_open +ffffffff8228a0c0 T dal_gpio_open_ex +ffffffff8228a180 T dal_gpio_get_value +ffffffff8228a200 T dal_gpio_set_value +ffffffff8228a280 T dal_gpio_get_mode +ffffffff8228a2b0 T dal_gpio_lock_pin +ffffffff8228a2d0 T dal_gpio_unlock_pin +ffffffff8228a2f0 T dal_gpio_change_mode +ffffffff8228a370 T dal_gpio_get_id +ffffffff8228a3a0 T dal_gpio_get_enum +ffffffff8228a3d0 T dal_gpio_set_config +ffffffff8228a450 T dal_gpio_get_pin_info +ffffffff8228a4b0 T dal_gpio_get_sync_source +ffffffff8228a540 T dal_gpio_get_output_state +ffffffff8228a570 T dal_gpio_get_ddc +ffffffff8228a5a0 T dal_gpio_get_hpd +ffffffff8228a5d0 T dal_gpio_get_generic +ffffffff8228a600 T dal_gpio_close +ffffffff8228a650 T dal_gpio_create +ffffffff8228a7e0 T dal_gpio_destroy +ffffffff8228b000 T dal_gpio_service_create +ffffffff8228b240 T dal_gpio_service_create_irq +ffffffff8228b300 T dal_gpio_create_irq +ffffffff8228b380 T dal_gpio_service_create_generic_mux +ffffffff8228b420 T dal_gpio_destroy_generic_mux +ffffffff8228b4b0 T dal_gpio_get_generic_pin_info +ffffffff8228b510 T dal_gpio_service_destroy +ffffffff8228b640 T dal_mux_setup_config +ffffffff8228b6a0 T dal_gpio_service_lock +ffffffff8228b720 T dal_gpio_service_unlock +ffffffff8228b7a0 T dal_gpio_service_open +ffffffff8228b9e0 T dal_gpio_service_close +ffffffff8228ba80 T dal_irq_get_source +ffffffff8228baf0 T dal_irq_get_rx_source +ffffffff8228bb40 T dal_irq_setup_hpd_filter +ffffffff8228bba0 T dal_gpio_destroy_irq +ffffffff8228bc30 T dal_gpio_create_ddc +ffffffff8228bda0 T dal_gpio_destroy_ddc +ffffffff8228be70 T dal_ddc_close +ffffffff8228bec0 T dal_ddc_open +ffffffff8228c020 T dal_ddc_change_mode +ffffffff8228c0c0 T dal_ddc_get_line +ffffffff8228c0e0 T dal_ddc_set_config +ffffffff8228d000 T dal_hw_ddc_init +ffffffff8228d100 T dal_hw_ddc_get_pin +ffffffff8228d110 t dal_hw_ddc_destroy ffffffff8228d170 t set_config -ffffffff8228e000 T dal_hw_gpio_open -ffffffff8228e0b0 T dal_hw_gpio_config_mode -ffffffff8228e1a0 T dal_hw_gpio_get_value -ffffffff8228e200 T dal_hw_gpio_set_value -ffffffff8228e290 T dal_hw_gpio_change_mode -ffffffff8228e2a0 T dal_hw_gpio_close -ffffffff8228e350 T dal_hw_gpio_construct -ffffffff8228e3b0 T dal_hw_gpio_destruct -ffffffff8228f000 T dal_hw_hpd_init -ffffffff8228f100 T dal_hw_hpd_get_pin -ffffffff8228f110 t dal_hw_hpd_destroy -ffffffff8228f170 t get_value -ffffffff8228f210 t set_config -ffffffff82290000 T dal_hw_translate_init -ffffffff82291000 T dc_process_hdcp_msg -ffffffff82291180 t hdmi_14_process_transaction -ffffffff822912d0 t dp_11_process_transaction -ffffffff82292000 T dal_irq_service_dummy_set -ffffffff82292050 T dal_irq_service_dummy_ack -ffffffff822920a0 T dce110_vblank_set -ffffffff82292170 T to_dal_irq_source_dce110 -ffffffff822922f0 T dal_irq_service_dce110_create -ffffffff82292370 t hpd_ack -ffffffff82293000 T dal_irq_service_dce120_create -ffffffff82293080 t hpd_ack -ffffffff82294000 T dal_irq_service_dce80_create -ffffffff82294080 t hpd_ack -ffffffff82295000 T dal_irq_service_dcn10_create +ffffffff8228e000 T dal_hw_factory_init +ffffffff8228f000 T dal_hw_generic_init +ffffffff8228f100 T dal_hw_generic_get_pin +ffffffff8228f110 t dal_hw_generic_destroy +ffffffff8228f170 t set_config +ffffffff82290000 T dal_hw_gpio_open +ffffffff822900b0 T dal_hw_gpio_config_mode +ffffffff822901a0 T dal_hw_gpio_get_value +ffffffff82290200 T dal_hw_gpio_set_value +ffffffff82290290 T dal_hw_gpio_change_mode +ffffffff822902a0 T dal_hw_gpio_close +ffffffff82290350 T dal_hw_gpio_construct +ffffffff822903b0 T dal_hw_gpio_destruct +ffffffff82291000 T dal_hw_hpd_init +ffffffff82291100 T dal_hw_hpd_get_pin +ffffffff82291110 t dal_hw_hpd_destroy +ffffffff82291170 t get_value +ffffffff82291210 t set_config +ffffffff82292000 T dal_hw_translate_init +ffffffff82293000 T dc_process_hdcp_msg +ffffffff82293180 t hdmi_14_process_transaction +ffffffff822932d0 t dp_11_process_transaction +ffffffff82294000 T dal_irq_service_dummy_set +ffffffff82294050 T dal_irq_service_dummy_ack +ffffffff822940a0 T dce110_vblank_set +ffffffff82294170 T to_dal_irq_source_dce110 +ffffffff822942f0 T dal_irq_service_dce110_create +ffffffff82294370 t hpd_ack +ffffffff82295000 T dal_irq_service_dce120_create ffffffff82295080 t hpd_ack -ffffffff82295130 t to_dal_irq_source_dcn10 -ffffffff82296000 T dal_irq_service_dcn20_create +ffffffff82296000 T dal_irq_service_dce80_create ffffffff82296080 t hpd_ack -ffffffff82296130 t to_dal_irq_source_dcn20 -ffffffff82297000 T dal_irq_service_dcn201_create +ffffffff82297000 T dal_irq_service_dcn10_create ffffffff82297080 t hpd_ack -ffffffff82297130 t to_dal_irq_source_dcn201 -ffffffff82298000 T dal_irq_service_dcn21_create +ffffffff82297130 t to_dal_irq_source_dcn10 +ffffffff82298000 T dal_irq_service_dcn20_create ffffffff82298080 t hpd_ack -ffffffff82298130 t to_dal_irq_source_dcn21 -ffffffff82299000 T dal_irq_service_dcn30_create +ffffffff82298130 t to_dal_irq_source_dcn20 +ffffffff82299000 T dal_irq_service_dcn201_create ffffffff82299080 t hpd_ack -ffffffff82299130 t to_dal_irq_source_dcn30 -ffffffff8229a000 T dal_irq_service_dcn302_create +ffffffff82299130 t to_dal_irq_source_dcn201 +ffffffff8229a000 T dal_irq_service_dcn21_create ffffffff8229a080 t hpd_ack -ffffffff8229a130 t to_dal_irq_source_dcn302 -ffffffff8229b000 T dal_irq_service_dcn303_create +ffffffff8229a130 t to_dal_irq_source_dcn21 +ffffffff8229b000 T dal_irq_service_dcn30_create ffffffff8229b080 t hpd_ack -ffffffff8229b130 t to_dal_irq_source_dcn303 -ffffffff8229c000 T dal_irq_service_dcn31_create +ffffffff8229b130 t to_dal_irq_source_dcn30 +ffffffff8229c000 T dal_irq_service_dcn302_create ffffffff8229c080 t hpd_ack -ffffffff8229c130 t to_dal_irq_source_dcn31 -ffffffff8229d000 T dal_irq_service_dcn314_create +ffffffff8229c130 t to_dal_irq_source_dcn302 +ffffffff8229d000 T dal_irq_service_dcn303_create ffffffff8229d080 t hpd_ack -ffffffff8229d130 t to_dal_irq_source_dcn314 -ffffffff8229e000 T dal_irq_service_dcn315_create +ffffffff8229d130 t to_dal_irq_source_dcn303 +ffffffff8229e000 T dal_irq_service_dcn31_create ffffffff8229e080 t hpd_ack -ffffffff8229e130 t to_dal_irq_source_dcn315 -ffffffff8229f000 T dal_irq_service_dcn32_create +ffffffff8229e130 t to_dal_irq_source_dcn31 +ffffffff8229f000 T dal_irq_service_dcn314_create ffffffff8229f080 t hpd_ack -ffffffff8229f130 t to_dal_irq_source_dcn32 -ffffffff822a0000 T dal_irq_service_construct -ffffffff822a0070 T dal_irq_service_destroy -ffffffff822a0100 T dal_irq_service_set_generic -ffffffff822a0180 T dal_irq_service_set -ffffffff822a0330 T dal_irq_service_ack -ffffffff822a04a0 T dal_irq_service_ack_generic -ffffffff822a0510 T dal_irq_service_to_irq_source -ffffffff822a1000 T dp_handle_automated_test -ffffffff822a1820 T dp_set_test_pattern -ffffffff822a1f00 t set_crtc_test_pattern -ffffffff822a2370 T dp_set_preferred_link_settings -ffffffff822a24c0 t dp_retrain_link_dp_test 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-ffffffff822a4000 T dp_fpga_hpo_enable_link_and_stream -ffffffff822a5000 T set_dio_throttled_vcp_size -ffffffff822a5020 T setup_dio_stream_encoder -ffffffff822a5110 T reset_dio_stream_encoder -ffffffff822a51e0 T setup_dio_stream_attribute -ffffffff822a5380 T enable_dio_dp_link_output -ffffffff822a5410 T disable_dio_link_output -ffffffff822a5470 T set_dio_dp_link_test_pattern -ffffffff822a54d0 T set_dio_dp_lane_settings -ffffffff822a5510 T update_dio_stream_allocation_table -ffffffff822a5580 T setup_dio_audio_output -ffffffff822a55f0 T enable_dio_audio_packet -ffffffff822a56b0 T disable_dio_audio_packet -ffffffff822a5790 T can_use_dio_link_hwss -ffffffff822a57d0 T get_dio_link_hwss -ffffffff822a6000 T dp_dio_fixed_vs_pe_retimer_lane_cfg_to_hw_cfg -ffffffff822a6040 T dp_dio_fixed_vs_pe_retimer_exit_manual_automation -ffffffff822a6280 T enable_dio_fixed_vs_pe_retimer_program_4lane_output -ffffffff822a63b0 T requires_fixed_vs_pe_retimer_dio_link_hwss -ffffffff822a63f0 T get_dio_fixed_vs_pe_retimer_link_hwss -ffffffff822a6420 t enable_dio_fixed_vs_pe_retimer_dp_link_output -ffffffff822a6590 t set_dio_fixed_vs_pe_retimer_dp_link_test_pattern -ffffffff822a7000 T can_use_dpia_link_hwss -ffffffff822a7050 T get_dpia_link_hwss -ffffffff822a7080 t update_dpia_stream_allocation_table -ffffffff822a8000 T set_hpo_dp_throttled_vcp_size -ffffffff822a8030 T set_hpo_dp_hblank_min_symbol_width -ffffffff822a8120 T setup_hpo_dp_stream_encoder -ffffffff822a8170 T reset_hpo_dp_stream_encoder -ffffffff822a8190 T setup_hpo_dp_stream_attribute -ffffffff822a8210 T enable_hpo_dp_link_output -ffffffff822a8290 T disable_hpo_dp_link_output -ffffffff822a8330 T update_hpo_dp_stream_allocation_table -ffffffff822a8350 T setup_hpo_dp_audio_output -ffffffff822a8390 T enable_hpo_dp_audio_packet -ffffffff822a83b0 T disable_hpo_dp_audio_packet -ffffffff822a8400 T can_use_hpo_dp_link_hwss -ffffffff822a8430 T get_hpo_dp_link_hwss -ffffffff822a8460 t set_hpo_dp_link_test_pattern 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-ffffffff825e44a0 T sdmmc_io_write_2 -ffffffff825e4600 T sdmmc_io_read_4 -ffffffff825e4760 T sdmmc_io_write_4 -ffffffff825e48c0 T sdmmc_io_read_multi_1 -ffffffff825e49b0 T sdmmc_io_write_multi_1 -ffffffff825e4aa0 T sdmmc_io_read_region_1 -ffffffff825e4b90 T sdmmc_io_write_region_1 -ffffffff825e4c80 T sdmmc_io_xchg -ffffffff825e4e10 T sdmmc_intr_enable -ffffffff825e5080 T sdmmc_intr_disable -ffffffff825e52f0 T sdmmc_intr_establish -ffffffff825e53f0 T sdmmc_intr_disestablish -ffffffff825e54e0 T sdmmc_card_intr -ffffffff825e5530 T sdmmc_intr_task -ffffffff825e55c0 T sdmmc_io_set_blocklen -ffffffff825e6000 T sdmmc_mem_enable -ffffffff825e6450 T sdmmc_mem_send_op_cond -ffffffff825e6600 T sdmmc_mem_signal_voltage -ffffffff825e66c0 T sdmmc_mem_scan -ffffffff825e69d0 T sdmmc_decode_csd -ffffffff825e6e00 T sdmmc_decode_cid -ffffffff825e72a0 T sdmmc_mem_send_scr -ffffffff825e73e0 T sdmmc_mem_decode_scr -ffffffff825e7440 T sdmmc_mem_send_cxd_data -ffffffff825e75b0 T sdmmc_mem_set_bus_width -ffffffff825e76c0 T sdmmc_mem_sd_switch -ffffffff825e7970 T sdmmc_be512_to_bitfield512 -ffffffff825e7a20 T sdmmc_mem_mmc_switch -ffffffff825e7b10 T sdmmc_mem_init -ffffffff825e7c60 T sdmmc_mem_set_blocklen -ffffffff825e7d60 T sdmmc_mem_sd_init -ffffffff825e8140 T sdmmc_mem_mmc_init -ffffffff825e8800 T sdmmc_mem_select_transfer_mode -ffffffff825e8880 T sdmmc_mem_execute_tuning -ffffffff825e8910 T sdmmc_mem_read_block_subr -ffffffff825e8c70 T sdmmc_mem_single_read_block -ffffffff825e8d40 T sdmmc_mem_read_block -ffffffff825e8ef0 T sdmmc_mem_write_block_subr -ffffffff825e9240 T sdmmc_mem_single_write_block -ffffffff825e9310 T sdmmc_mem_write_block -ffffffff825e94c0 T sdmmc_mem_hibernate_write -ffffffff825ea000 T sdmmc_scsi_cmd -ffffffff825ea1f0 T sdmmc_minphys -ffffffff825ea270 T sdmmc_scsi_attach -ffffffff825ea460 T sdmmc_alloc_ccbs -ffffffff825ea5a0 T sdmmc_free_ccbs -ffffffff825ea600 T sdmmc_scsi_detach -ffffffff825ea760 T sdmmc_stimeout -ffffffff825ea7e0 T sdmmc_ccb_alloc -ffffffff825ea890 T sdmmc_ccb_free -ffffffff825ea970 T sdmmc_inquiry -ffffffff825eabe0 T sdmmc_start_xs -ffffffff825eacd0 T sdmmc_complete_xs -ffffffff825eada0 T sdmmc_done_xs -ffffffff825eadf0 T sdmmc_scsi_hibernate_io -ffffffff825eb000 T bwfm_sdio_preinit -ffffffff825eb4a0 T bwfm_sdio_txcheck -ffffffff825eb4e0 T bwfm_sdio_txdata -ffffffff825eb550 T bwfm_sdio_txctl -ffffffff825eb6a0 T bwfm_sdio_buscore_read -ffffffff825eb6b0 T bwfm_sdio_buscore_write -ffffffff825eb6d0 T bwfm_sdio_buscore_prepare -ffffffff825eb810 T bwfm_sdio_buscore_activate -ffffffff825eb890 T bwfm_sdio_match -ffffffff825eb940 T bwfm_sdio_attach -ffffffff825ebc00 T bwfm_sdio_detach -ffffffff825ebc60 T bwfm_sdio_task -ffffffff825ebdc0 T bwfm_sdio_write_1 -ffffffff825ebdf0 T bwfm_sdio_read_1 -ffffffff825ebe20 T bwfm_sdio_write_4 -ffffffff825ebed0 T bwfm_sdio_read_4 -ffffffff825ebf80 T bwfm_sdio_load_microcode -ffffffff825ec1e0 T bwfm_sdio_clkctl -ffffffff825ec310 T bwfm_sdio_dev_write -ffffffff825ec360 T bwfm_sdio_intr -ffffffff825ec3a0 T bwfm_sdio_ram_read_write -ffffffff825ec5d0 T bwfm_sdio_htclk -ffffffff825ec840 T bwfm_sdio_readshared -ffffffff825ec910 T bwfm_sdio_dev_read -ffffffff825ec950 T bwfm_sdio_rx_frames -ffffffff825ecd00 T bwfm_sdio_tx_frames -ffffffff825ece00 T bwfm_sdio_backplane -ffffffff825eceb0 T bwfm_sdio_buf_read -ffffffff825ecf90 T bwfm_sdio_buf_write -ffffffff825ed040 T bwfm_sdio_frame_read_write -ffffffff825ed1c0 T bwfm_sdio_newbuf -ffffffff825ed240 T bwfm_sdio_tx_ok -ffffffff825ed2a0 T bwfm_sdio_tx_ctrlframe -ffffffff825ed3a0 T bwfm_sdio_tx_dataframe -ffffffff825ed4f0 T bwfm_sdio_rx_glom -ffffffff825ee000 T onewire_match -ffffffff825ee050 T onewire_attach -ffffffff825ee0f0 T onewire_detach -ffffffff825ee160 T onewire_activate -ffffffff825ee180 T onewire_scan -ffffffff825ee3a0 T onewire_createthread -ffffffff825ee410 T onewire_print -ffffffff825ee4e0 T onewirebus_print -ffffffff825ee530 T onewire_lock -ffffffff825ee550 T onewire_unlock -ffffffff825ee570 T onewire_reset -ffffffff825ee590 T onewire_bit -ffffffff825ee5b0 T onewire_read_byte -ffffffff825ee6f0 T onewire_write_byte -ffffffff825ee7d0 T onewire_read_block -ffffffff825ee870 T onewire_write_block -ffffffff825ee910 T onewire_triplet -ffffffff825ee9f0 T onewire_matchrom -ffffffff825eeb40 T onewire_search -ffffffff825eeee0 T onewire_thread -ffffffff825ef000 T onewire_crc -ffffffff825ef0b0 T onewire_crc16 -ffffffff825ef170 T onewire_famname -ffffffff825ef1b0 T onewire_matchbyfam -ffffffff825f0000 T owid_match -ffffffff825f0030 T owid_attach -ffffffff825f0100 T owid_detach -ffffffff825f0140 T owid_activate -ffffffff825f1000 T owsbm_match -ffffffff825f1030 T owsbm_attach -ffffffff825f11d0 T owsbm_detach -ffffffff825f1240 T owsbm_activate -ffffffff825f1270 T owsbm_update -ffffffff825f2000 T owtemp_match -ffffffff825f2030 T owtemp_attach -ffffffff825f2130 T owtemp_detach -ffffffff825f21a0 T owtemp_activate -ffffffff825f21d0 T owtemp_update -ffffffff825f3000 T owctr_match -ffffffff825f3030 T owctr_attach -ffffffff825f3180 T owctr_detach -ffffffff825f31f0 T owctr_activate -ffffffff825f3220 T owctr_update -ffffffff825f3250 T owctr_update_counter -ffffffff825f4000 A __text_page_start -ffffffff825f4000 T Xsyscall_meltdown -ffffffff825f400c T Xsyscall -ffffffff825f426e t Xsyscall_trampback -ffffffff825f4280 T intr_user_exit -ffffffff825f42c2 t intr_user_exit_post_ast -ffffffff825f43ee t Xiretq_trampback -ffffffff825f43fa T doreti_iret -ffffffff825f5000 T alltraps -ffffffff825f5138 T recall_trap -ffffffff825f5150 T alltraps_kern -ffffffff825f5153 T alltraps_kern_meltdown -ffffffff825f6000 ? Xsyscall32 -ffffffff825f6000 A __kutext_start -ffffffff825f6000 A __text_page_end -ffffffff825f7000 ? Xtrap00 -ffffffff825f7010 ? Xtrap01 -ffffffff825f7020 ? Xtrap02 -ffffffff825f7028 c calltrap_specstk -ffffffff825f70f0 ? calltrap_specstk_tramp -ffffffff825f7110 ? Xtrap03 -ffffffff825f7120 ? Xtrap04 -ffffffff825f7130 ? Xtrap05 -ffffffff825f7140 ? Xtrap06 -ffffffff825f7150 ? Xtrap07 -ffffffff825f7160 ? Xtrap08 -ffffffff825f7170 ? Xtrap09 -ffffffff825f7180 ? Xtrap0a -ffffffff825f7190 ? Xtrap0b -ffffffff825f71a0 ? Xtrap0c -ffffffff825f71b0 ? Xtrap0d -ffffffff825f7240 ? Xtrap0e -ffffffff825f7250 ? Xintrspurious -ffffffff825f7250 ? Xtrap0f -ffffffff825f7260 ? Xtrap10 -ffffffff825f7270 ? Xtrap11 -ffffffff825f7280 ? Xtrap12 -ffffffff825f7290 ? Xtrap13 -ffffffff825f72a0 ? Xtrap14 -ffffffff825f72b0 ? Xtrap15 -ffffffff825f72c0 ? Xtrap16 -ffffffff825f72c0 ? Xtrap17 -ffffffff825f72c0 ? Xtrap18 -ffffffff825f72c0 ? Xtrap19 -ffffffff825f72c0 ? Xtrap1a -ffffffff825f72c0 ? Xtrap1b -ffffffff825f72c0 ? Xtrap1c -ffffffff825f72c0 ? Xtrap1d -ffffffff825f72c0 ? Xtrap1e -ffffffff825f72c0 ? Xtrap1f -ffffffff825f72d0 ? x2apic_eoi -ffffffff825f72f0 ? Xintr_lapic_ipi -ffffffff825f7330 ? Xipi_invltlb -ffffffff825f7360 ? Xipi_invlpg -ffffffff825f7390 ? Xipi_invlrange -ffffffff825f73d0 ? Xipi_invltlb_pcid -ffffffff825f7410 ? Xipi_invlpg_pcid -ffffffff825f7460 ? Xipi_invlrange_pcid -ffffffff825f74d0 ? Xintr_lapic_ltimer -ffffffff825f7510 ? Xintr_xen_upcall -ffffffff825f7550 ? Xintr_hyperv_upcall -ffffffff825f7590 ? Xintr_legacy0 -ffffffff825f75d0 ? Xintr_legacy1 -ffffffff825f7610 ? Xintr_legacy2 -ffffffff825f7650 ? Xintr_legacy3 -ffffffff825f7690 ? Xintr_legacy4 -ffffffff825f76d0 ? Xintr_legacy5 -ffffffff825f7710 ? Xintr_legacy6 -ffffffff825f7750 ? Xintr_legacy7 -ffffffff825f7790 ? Xintr_legacy8 -ffffffff825f77d0 ? Xintr_legacy9 -ffffffff825f7810 ? Xintr_legacy10 -ffffffff825f7850 ? Xintr_legacy11 -ffffffff825f7890 ? Xintr_legacy12 -ffffffff825f78d0 ? Xintr_legacy13 -ffffffff825f7910 ? Xintr_legacy14 -ffffffff825f7950 ? Xintr_legacy15 -ffffffff825f7990 ? Xintr_ioapic_edge0 -ffffffff825f79d0 ? Xintr_ioapic_edge1 -ffffffff825f7a10 ? Xintr_ioapic_edge2 -ffffffff825f7a50 ? Xintr_ioapic_edge3 -ffffffff825f7a90 ? Xintr_ioapic_edge4 -ffffffff825f7ad0 ? Xintr_ioapic_edge5 -ffffffff825f7b10 ? Xintr_ioapic_edge6 -ffffffff825f7b50 ? Xintr_ioapic_edge7 -ffffffff825f7b90 ? Xintr_ioapic_edge8 -ffffffff825f7bd0 ? Xintr_ioapic_edge9 -ffffffff825f7c10 ? Xintr_ioapic_edge10 -ffffffff825f7c50 ? Xintr_ioapic_edge11 -ffffffff825f7c90 ? Xintr_ioapic_edge12 -ffffffff825f7cd0 ? Xintr_ioapic_edge13 -ffffffff825f7d10 ? Xintr_ioapic_edge14 -ffffffff825f7d50 ? Xintr_ioapic_edge15 -ffffffff825f7d90 ? Xintr_ioapic_edge16 -ffffffff825f7dd0 ? Xintr_ioapic_edge17 -ffffffff825f7e10 ? Xintr_ioapic_edge18 -ffffffff825f7e50 ? Xintr_ioapic_edge19 -ffffffff825f7e90 ? Xintr_ioapic_edge20 -ffffffff825f7ed0 ? Xintr_ioapic_edge21 -ffffffff825f7f10 ? Xintr_ioapic_edge22 -ffffffff825f7f50 ? Xintr_ioapic_edge23 -ffffffff825f7f90 ? Xintr_ioapic_edge24 -ffffffff825f7fd0 ? Xintr_ioapic_edge25 -ffffffff825f8010 ? Xintr_ioapic_edge26 -ffffffff825f8050 ? Xintr_ioapic_edge27 -ffffffff825f8090 ? Xintr_ioapic_edge28 -ffffffff825f80d0 ? Xintr_ioapic_edge29 -ffffffff825f8110 ? Xintr_ioapic_edge30 -ffffffff825f8150 ? Xintr_ioapic_edge31 -ffffffff825f8190 ? Xintr_ioapic_edge32 -ffffffff825f81d0 ? Xintr_ioapic_edge33 -ffffffff825f8210 ? Xintr_ioapic_edge34 -ffffffff825f8250 ? Xintr_ioapic_edge35 -ffffffff825f8290 ? Xintr_ioapic_edge36 -ffffffff825f82d0 ? Xintr_ioapic_edge37 -ffffffff825f8310 ? Xintr_ioapic_edge38 -ffffffff825f8350 ? Xintr_ioapic_edge39 -ffffffff825f8390 ? Xintr_ioapic_edge40 -ffffffff825f83d0 ? Xintr_ioapic_edge41 -ffffffff825f8410 ? Xintr_ioapic_edge42 -ffffffff825f8450 ? Xintr_ioapic_edge43 -ffffffff825f8490 ? Xintr_ioapic_edge44 -ffffffff825f84d0 ? Xintr_ioapic_edge45 -ffffffff825f8510 ? Xintr_ioapic_edge46 -ffffffff825f8550 ? Xintr_ioapic_edge47 -ffffffff825f8590 ? Xintr_ioapic_edge48 -ffffffff825f85d0 ? Xintr_ioapic_edge49 -ffffffff825f8610 ? Xintr_ioapic_edge50 -ffffffff825f8650 ? Xintr_ioapic_edge51 -ffffffff825f8690 ? Xintr_ioapic_edge52 -ffffffff825f86d0 ? Xintr_ioapic_edge53 -ffffffff825f8710 ? Xintr_ioapic_edge54 -ffffffff825f8750 ? Xintr_ioapic_edge55 -ffffffff825f8790 ? Xintr_ioapic_edge56 -ffffffff825f87d0 ? Xintr_ioapic_edge57 -ffffffff825f8810 ? Xintr_ioapic_edge58 -ffffffff825f8850 ? Xintr_ioapic_edge59 -ffffffff825f8890 ? Xintr_ioapic_edge60 -ffffffff825f88d0 ? Xintr_ioapic_edge61 -ffffffff825f8910 ? Xintr_ioapic_edge62 -ffffffff825f8950 ? Xintr_ioapic_edge63 -ffffffff825f8990 ? Xintr_ioapic_level0 -ffffffff825f89d0 ? Xintr_ioapic_level1 -ffffffff825f8a10 ? Xintr_ioapic_level2 -ffffffff825f8a50 ? Xintr_ioapic_level3 -ffffffff825f8a90 ? Xintr_ioapic_level4 -ffffffff825f8ad0 ? Xintr_ioapic_level5 -ffffffff825f8b10 ? Xintr_ioapic_level6 -ffffffff825f8b50 ? Xintr_ioapic_level7 -ffffffff825f8b90 ? Xintr_ioapic_level8 -ffffffff825f8bd0 ? Xintr_ioapic_level9 -ffffffff825f8c10 ? Xintr_ioapic_level10 -ffffffff825f8c50 ? Xintr_ioapic_level11 -ffffffff825f8c90 ? Xintr_ioapic_level12 -ffffffff825f8cd0 ? Xintr_ioapic_level13 -ffffffff825f8d10 ? Xintr_ioapic_level14 -ffffffff825f8d50 ? Xintr_ioapic_level15 -ffffffff825f8d90 ? Xintr_ioapic_level16 -ffffffff825f8dd0 ? Xintr_ioapic_level17 -ffffffff825f8e10 ? Xintr_ioapic_level18 -ffffffff825f8e50 ? Xintr_ioapic_level19 -ffffffff825f8e90 ? Xintr_ioapic_level20 -ffffffff825f8ed0 ? Xintr_ioapic_level21 -ffffffff825f8f10 ? Xintr_ioapic_level22 -ffffffff825f8f50 ? Xintr_ioapic_level23 -ffffffff825f8f90 ? Xintr_ioapic_level24 -ffffffff825f8fd0 ? Xintr_ioapic_level25 -ffffffff825f9010 ? Xintr_ioapic_level26 -ffffffff825f9050 ? Xintr_ioapic_level27 -ffffffff825f9090 ? Xintr_ioapic_level28 -ffffffff825f90d0 ? Xintr_ioapic_level29 -ffffffff825f9110 ? Xintr_ioapic_level30 -ffffffff825f9150 ? Xintr_ioapic_level31 -ffffffff825f9190 ? Xintr_ioapic_level32 -ffffffff825f91d0 ? Xintr_ioapic_level33 -ffffffff825f9210 ? Xintr_ioapic_level34 -ffffffff825f9250 ? Xintr_ioapic_level35 -ffffffff825f9290 ? Xintr_ioapic_level36 -ffffffff825f92d0 ? Xintr_ioapic_level37 -ffffffff825f9310 ? Xintr_ioapic_level38 -ffffffff825f9350 ? Xintr_ioapic_level39 -ffffffff825f9390 ? Xintr_ioapic_level40 -ffffffff825f93d0 ? Xintr_ioapic_level41 -ffffffff825f9410 ? Xintr_ioapic_level42 -ffffffff825f9450 ? Xintr_ioapic_level43 -ffffffff825f9490 ? Xintr_ioapic_level44 -ffffffff825f94d0 ? Xintr_ioapic_level45 -ffffffff825f9510 ? Xintr_ioapic_level46 -ffffffff825f9550 ? Xintr_ioapic_level47 -ffffffff825f9590 ? Xintr_ioapic_level48 -ffffffff825f95d0 ? Xintr_ioapic_level49 -ffffffff825f9610 ? Xintr_ioapic_level50 -ffffffff825f9650 ? Xintr_ioapic_level51 -ffffffff825f9690 ? Xintr_ioapic_level52 -ffffffff825f96d0 ? Xintr_ioapic_level53 -ffffffff825f9710 ? Xintr_ioapic_level54 -ffffffff825f9750 ? Xintr_ioapic_level55 -ffffffff825f9790 ? Xintr_ioapic_level56 -ffffffff825f97d0 ? Xintr_ioapic_level57 -ffffffff825f9810 ? Xintr_ioapic_level58 -ffffffff825f9850 ? Xintr_ioapic_level59 -ffffffff825f9890 ? Xintr_ioapic_level60 -ffffffff825f98d0 ? Xintr_ioapic_level61 -ffffffff825f9910 ? Xintr_ioapic_level62 -ffffffff825f9950 ? Xintr_ioapic_level63 -ffffffff825fa000 ? codepatch_fill_nop -ffffffff825fa000 A __cptext_start -ffffffff825fa000 A __kutext_end -ffffffff825fa0b0 ? codepatch_maprw -ffffffff825fa190 ? codepatch_unmaprw -ffffffff825fa200 ? codepatch_nop -ffffffff825fa360 ? codepatch_replace -ffffffff825fa510 ? codepatch_call -ffffffff825fa530 ? codepatch_jmp -ffffffff825fb000 A __cptext_end -ffffffff825fb000 A __rodata_start -ffffffff825fb000 C _etext -ffffffff825fb000 C etext -ffffffff825fc000 r seeprom_read -ffffffff825fc004 r icl_mg_pll_find_divisors.div1_vals -ffffffff825fc034 r athn_ac2qid -ffffffff825fc034 r athn_ac2qid -ffffffff825fc034 r athn_ac2qid -ffffffff825fc040 r rtwn_get_rssi.cckoff -ffffffff825fc068 r rsu_ac2qid -ffffffff825fc078 r pckbc_portcmd -ffffffff825fc07c r tht_fifo_write_pad.pad -ffffffff825fc084 r rsu_get_rssi.cckoff -ffffffff825fc0a4 r adlp_n_revids -ffffffff825fc0e8 r apple_iso_trans -ffffffff825fc0f0 r wihap_check_tx.txratetable -ffffffff825fc0f4 r dmamode -ffffffff825fc118 r gen9_edram_size_mb.sets -ffffffff825fc12c r dg2_g12_revid_step_tbl -ffffffff825fd000 r isomappings -ffffffff825fd080 r unimappings -ffffffff825fd230 r replacements -ffffffff8260093f r apollo_pio_rec -ffffffff8264cf3a r apollo_udma33_tim -ffffffff82662049 r pp_r600_decoded_lanes -ffffffff826981a5 r cmd680_setup_channel.udma_tbl -ffffffff826a0657 r apollo_udma100_tim -ffffffff826a065d r cmd0646_9_tim_udma -ffffffff826aeaad r substchar -ffffffff827045b4 r apollo_udma133_tim -ffffffff827045bb r apollo_udma66_tim -ffffffff827045e5 r cy_pio_rec -ffffffff82709cd0 R drm_ca -ffffffff82709cf8 R drm_filtops -ffffffff82709d28 R drmread_filtops -ffffffff8270a000 r vga_emulops -ffffffff8270a048 R vga_stdscreen -ffffffff8270a078 R vga_stdscreen_mono -ffffffff8270a0a8 R vga_stdscreen_bf -ffffffff8270a0d8 R vga_40lscreen -ffffffff8270a108 R vga_40lscreen_mono -ffffffff8270a138 R vga_40lscreen_bf -ffffffff8270a168 R vga_50lscreen -ffffffff8270a198 R vga_50lscreen_mono -ffffffff8270a1c8 R vga_50lscreen_bf -ffffffff8270a1f8 R vga_screenlist -ffffffff8270a208 R vga_screenlist_mono -ffffffff8270a218 R vga_accessops -ffffffff8270a278 r i945_wm_info -ffffffff8270a2b8 r bgansitopc -ffffffff8270a2c0 r pctoansi -ffffffff8270a300 r sdma_offsets -ffffffff8270a300 r sdma_offsets -ffffffff8270a338 r iha_rate_tbl -ffffffff8270a370 r i830_a_wm_info -ffffffff8270a3a8 r gen9_edram_size_mb.ways -ffffffff8270a408 r aggr_periodic_times -ffffffff8270a500 r michael_final.pad -ffffffff8270a528 r rt_copysa.maskarray -ffffffff8270a530 r i915_wm_info -ffffffff8270a538 r amdgpu_ih_clientid_jpeg -ffffffff8270a538 r amdgpu_ih_clientid_uvds -ffffffff8270a538 r amdgpu_ih_clientid_vcns -ffffffff8270a538 r amdgpu_ih_clientid_vcns -ffffffff8270a538 r amdgpu_ih_clientid_vcns -ffffffff8270a568 r jsl_ehl_revids -ffffffff8270a578 r vga_setfontset.cmaptabb -ffffffff8270a5e8 r i830_bc_wm_info -ffffffff8270a650 r hsw_activate_psr2.map -ffffffff8270a658 r tgl_revids -ffffffff8270a690 r __drm_universal_plane_init.default_modifiers -ffffffff8270a6a0 r iwn_tid2fifo -ffffffff8270a6b8 r vga_setfontset.cmaptaba -ffffffff8270a6c0 r crtc_offsets -ffffffff8270a6c0 r crtc_offsets -ffffffff8270a6c0 r crtc_offsets -ffffffff8270a768 r rtwn_r88e_get_rssi.cckoff -ffffffff8270b000 R edid_vendors -ffffffff8270b2c0 R edid_nvendors -ffffffff8270b2d0 R edid_products -ffffffff8270b330 R edid_nproducts -ffffffff8270b340 r _edid_modes -ffffffff8270c000 R videomode_list -ffffffff8270d080 R videomode_count -ffffffff8270e000 r ahc_hard_errors -ffffffff8270e080 r critical_sections -ffffffff8270e0b0 r patches -ffffffff8270ed50 r seqprog -ffffffff82710000 r ahc_switch -ffffffff82711000 r termstat_strings -ffffffff82711020 r critical_sections -ffffffff82711060 r seqprog -ffffffff82711d50 r patches -ffffffff82713000 r ahd_switch -ffffffff82714000 R aic_switch -ffffffff82715000 R adw_switch -ffffffff82716000 R gdt_switch -ffffffff82717000 R twe_switch -ffffffff82718000 R ciss_switch -ffffffff82718030 R ciss_level -ffffffff82718050 R ciss_stat -ffffffff82719000 R ami_switch -ffffffff82719028 R ami_raw_switch -ffffffff8271a000 R mfi_switch -ffffffff8271a028 R mfi_pd_switch -ffffffff8271a050 r mfi_iop_xscale -ffffffff8271a080 r mfi_iop_ppc -ffffffff8271a0b0 r mfi_iop_gen2 -ffffffff8271a0e0 r mfi_iop_skinny -ffffffff8271a110 r mfi_bbu_indicators -ffffffff8271b000 R qlw_switch -ffffffff8271c000 R isp_2100_risc_code -ffffffff8272ebf0 R isp_2200_risc_code -ffffffff82741990 R isp_2300_risc_code -ffffffff8275b408 R qla_switch -ffffffff8275b430 r qla_regs_2100 -ffffffff8275b460 r qla_regs_2200 -ffffffff8275b490 r qla_regs_23XX -ffffffff8275c000 R ahci_atascsi_methods -ffffffff8275d000 R nvme_switch -ffffffff8275d028 r nvme_ops -ffffffff8275e000 R mpi_switch -ffffffff8275e060 r bwi_rf_calc_nrssi_slope_11b.save_phy_regs -ffffffff8275e090 r chv_oa_mux_regs -ffffffff8275e0b0 r fiji_clock_stretcher_lookup_table -ffffffff8275e0b0 r tonga_clock_stretcher_lookup_table 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gfx_v10_0_ip_block -ffffffff82b510b8 r gfx_v10_0_gfx_funcs -ffffffff82b51120 r golden_settings_gc_rlc_spm_10_0_nv10 -ffffffff82b573c0 r golden_settings_gc_rlc_spm_10_1_nv14 -ffffffff82b5ade0 r golden_settings_gc_rlc_spm_10_1_2_nv12 -ffffffff82b61080 r gfx_v10_0_kiq_pm4_funcs -ffffffff82b610c0 r gfx_v10_0_ring_funcs_kiq -ffffffff82b61200 r gfx_v10_0_ring_funcs_gfx -ffffffff82b61340 r gfx_v10_0_ring_funcs_compute -ffffffff82b61480 r gfx_v10_0_eop_irq_funcs -ffffffff82b61490 r gfx_v10_0_kiq_irq_funcs -ffffffff82b614a0 r gfx_v10_0_priv_reg_irq_funcs -ffffffff82b614b0 r gfx_v10_0_priv_inst_irq_funcs -ffffffff82b614c0 r gfx_v10_0_rlc_funcs -ffffffff82b61528 r gfx_v10_0_rlc_funcs_sriov -ffffffff82b61590 r gfx10_cs_data -ffffffff82b615b0 r gfx10_SECT_CONTEXT_defs -ffffffff82b61640 r gfx10_SECT_CONTEXT_def_1 -ffffffff82b619a0 r gfx10_SECT_CONTEXT_def_3 -ffffffff82b619b0 r gfx10_SECT_CONTEXT_def_4 -ffffffff82b61c28 r gfx10_SECT_CONTEXT_def_5 -ffffffff82b61c30 r gfx10_SECT_CONTEXT_def_6 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gfx_v8_0_ip_block -ffffffff82b670b8 R gfx_v8_1_ip_block -ffffffff82b670d0 r gfx_v8_0_gfx_funcs -ffffffff82b67130 r gfx_v8_0_ring_funcs_kiq -ffffffff82b67270 r gfx_v8_0_ring_funcs_gfx -ffffffff82b673b0 r gfx_v8_0_ring_funcs_compute -ffffffff82b674f0 r amdgpu_gds_reg_offset -ffffffff82b675f0 r gfx_v8_0_eop_irq_funcs -ffffffff82b67600 r gfx_v8_0_priv_reg_irq_funcs -ffffffff82b67610 r gfx_v8_0_priv_inst_irq_funcs -ffffffff82b67620 r gfx_v8_0_cp_ecc_error_irq_funcs -ffffffff82b67630 r gfx_v8_0_sq_irq_funcs -ffffffff82b67640 r sq_edc_source_names -ffffffff82b67678 r iceland_rlc_funcs -ffffffff82b676e0 r vi_cs_data -ffffffff82b67700 r vi_SECT_CONTEXT_defs -ffffffff82b67780 r vi_SECT_CONTEXT_def_1 -ffffffff82b67ad0 r vi_SECT_CONTEXT_def_3 -ffffffff82b67af0 r vi_SECT_CONTEXT_def_4 -ffffffff82b67d64 r vi_SECT_CONTEXT_def_5 -ffffffff82b67d6c r vi_SECT_CONTEXT_def_6 -ffffffff82b67d70 r vi_SECT_CONTEXT_def_2 -ffffffff82b681c0 r vi_SECT_CONTEXT_def_7 -ffffffff82b68570 r vgpr_init_compute_shader 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gfx_v9_4_3_ras_ta_mem_list -ffffffff82b773d0 r gfx_v9_4_3_ras_tcc_mem_list -ffffffff82b773e0 r gfx_v9_4_3_ras_tca_mem_list -ffffffff82b773f0 r gfx_v9_4_3_ras_tci_mem_list -ffffffff82b77400 r gfx_v9_4_3_ras_tcp_mem_list -ffffffff82b77590 r gfx_v9_4_3_ras_td_mem_list -ffffffff82b775c0 r gfx_v9_4_3_ras_tcx_mem_list -ffffffff82b77b40 r gfx_v9_4_3_ras_atc_l2_mem_list -ffffffff82b77b50 r gfx_v9_4_3_ras_utcl2_mem_list -ffffffff82b77b60 r gfx_v9_4_3_ras_vml2_mem_list -ffffffff82b77b70 r gfx_v9_4_3_ras_vml2_walker_mem_list -ffffffff82b78000 R gfxhub_v1_0_funcs -ffffffff82b79000 R gfxhub_v1_2_funcs -ffffffff82b7a000 R gfxhub_v2_0_funcs -ffffffff82b7a060 r gfxhub_v2_0_vmhub_funcs -ffffffff82b7a070 r gfxhub_client_ids -ffffffff82b7b000 R gfxhub_v2_1_funcs -ffffffff82b7b060 r gfxhub_v2_1_vmhub_funcs -ffffffff82b7b070 r gfxhub_client_ids -ffffffff82b7c000 R gfxhub_v3_0_funcs -ffffffff82b7c060 r gfxhub_v3_0_vmhub_funcs +ffffffff8229f130 t to_dal_irq_source_dcn314 +ffffffff822a0000 T dal_irq_service_dcn315_create +ffffffff822a0080 t hpd_ack +ffffffff822a0130 t to_dal_irq_source_dcn315 +ffffffff822a1000 T dal_irq_service_dcn32_create +ffffffff822a1080 t hpd_ack +ffffffff822a1130 t to_dal_irq_source_dcn32 +ffffffff822a2000 T dal_irq_service_construct +ffffffff822a2070 T dal_irq_service_destroy +ffffffff822a2100 T dal_irq_service_set_generic +ffffffff822a2180 T dal_irq_service_set +ffffffff822a2330 T dal_irq_service_ack +ffffffff822a24a0 T dal_irq_service_ack_generic +ffffffff822a2510 T dal_irq_service_to_irq_source +ffffffff822a3000 T dp_handle_automated_test +ffffffff822a3820 T dp_set_test_pattern +ffffffff822a3f00 t set_crtc_test_pattern +ffffffff822a4370 T dp_set_preferred_link_settings +ffffffff822a44c0 t dp_retrain_link_dp_test +ffffffff822a45c0 T dp_set_preferred_training_settings +ffffffff822a5000 T dp_trace_init +ffffffff822a50a0 T dp_trace_reset +ffffffff822a5130 T dp_trace_is_initialized +ffffffff822a5160 T dp_trace_detect_lt_init +ffffffff822a51b0 T dp_trace_commit_lt_init +ffffffff822a5200 T dp_trace_link_loss_increment +ffffffff822a5230 T dp_trace_lt_fail_count_update +ffffffff822a5270 T dp_trace_lt_total_count_increment +ffffffff822a52b0 T dp_trace_set_is_logged_flag +ffffffff822a52f0 T dp_trace_is_logged +ffffffff822a5330 T dp_trace_lt_result_update +ffffffff822a5370 T dp_trace_set_lt_start_timestamp +ffffffff822a5450 T dp_trace_set_lt_end_timestamp +ffffffff822a5530 T dp_trace_get_lt_end_timestamp +ffffffff822a5570 T dp_trace_get_lt_counts +ffffffff822a55b0 T dp_trace_get_link_loss_count +ffffffff822a55e0 T dp_trace_set_edp_power_timestamp +ffffffff822a56c0 T dp_trace_get_edp_poweron_timestamp +ffffffff822a56f0 T dp_trace_get_edp_poweroff_timestamp +ffffffff822a5720 T dp_trace_source_sequence +ffffffff822a6000 T dp_fpga_hpo_enable_link_and_stream +ffffffff822a7000 T set_dio_throttled_vcp_size +ffffffff822a7020 T setup_dio_stream_encoder +ffffffff822a7110 T reset_dio_stream_encoder +ffffffff822a71e0 T setup_dio_stream_attribute +ffffffff822a7380 T enable_dio_dp_link_output +ffffffff822a7410 T disable_dio_link_output +ffffffff822a7470 T set_dio_dp_link_test_pattern +ffffffff822a74d0 T set_dio_dp_lane_settings +ffffffff822a7510 T update_dio_stream_allocation_table +ffffffff822a7580 T setup_dio_audio_output +ffffffff822a75f0 T enable_dio_audio_packet +ffffffff822a76b0 T disable_dio_audio_packet +ffffffff822a7790 T can_use_dio_link_hwss +ffffffff822a77d0 T get_dio_link_hwss +ffffffff822a8000 T dp_dio_fixed_vs_pe_retimer_lane_cfg_to_hw_cfg +ffffffff822a8040 T dp_dio_fixed_vs_pe_retimer_exit_manual_automation +ffffffff822a8280 T enable_dio_fixed_vs_pe_retimer_program_4lane_output +ffffffff822a83b0 T requires_fixed_vs_pe_retimer_dio_link_hwss +ffffffff822a83f0 T get_dio_fixed_vs_pe_retimer_link_hwss +ffffffff822a8420 t enable_dio_fixed_vs_pe_retimer_dp_link_output +ffffffff822a8590 t set_dio_fixed_vs_pe_retimer_dp_link_test_pattern +ffffffff822a9000 T can_use_dpia_link_hwss +ffffffff822a9050 T get_dpia_link_hwss +ffffffff822a9080 t update_dpia_stream_allocation_table +ffffffff822aa000 T set_hpo_dp_throttled_vcp_size +ffffffff822aa030 T set_hpo_dp_hblank_min_symbol_width +ffffffff822aa120 T setup_hpo_dp_stream_encoder +ffffffff822aa170 T reset_hpo_dp_stream_encoder +ffffffff822aa190 T setup_hpo_dp_stream_attribute +ffffffff822aa210 T enable_hpo_dp_link_output +ffffffff822aa290 T disable_hpo_dp_link_output +ffffffff822aa330 T update_hpo_dp_stream_allocation_table +ffffffff822aa350 T setup_hpo_dp_audio_output +ffffffff822aa390 T enable_hpo_dp_audio_packet +ffffffff822aa3b0 T disable_hpo_dp_audio_packet +ffffffff822aa400 T can_use_hpo_dp_link_hwss +ffffffff822aa430 T get_hpo_dp_link_hwss +ffffffff822aa460 t set_hpo_dp_link_test_pattern +ffffffff822aa4b0 t set_hpo_dp_lane_settings +ffffffff822ab000 T requires_fixed_vs_pe_retimer_hpo_link_hwss +ffffffff822ab040 T get_hpo_fixed_vs_pe_retimer_dp_link_hwss +ffffffff822ab070 t enable_hpo_fixed_vs_pe_retimer_dp_link_output +ffffffff822ab0d0 t set_hpo_fixed_vs_pe_retimer_dp_link_test_pattern +ffffffff822ab450 t set_hpo_fixed_vs_pe_retimer_dp_lane_settings +ffffffff822ab4d0 t dp_hpo_fixed_vs_pe_retimer_set_tx_ffe +ffffffff822ac000 T link_reset_cur_dp_mst_topology +ffffffff822ac060 T link_detect_connection_type +ffffffff822ac180 T link_detect +ffffffff822ada40 T link_clear_dprx_states +ffffffff822ada70 T link_is_hdcp14 +ffffffff822adad0 T link_is_hdcp22 +ffffffff822adb40 T link_get_status +ffffffff822adb70 T link_add_remote_sink +ffffffff822add10 T link_remove_remote_sink +ffffffff822addf0 t wait_for_entering_dp_alt_mode +ffffffff822ae000 T link_blank_all_dp_displays +ffffffff822ae0d0 T link_blank_dp_stream +ffffffff822ae1e0 T link_blank_all_edp_displays +ffffffff822ae2a0 T link_set_all_streams_dpms_off_for_link +ffffffff822ae3a0 T link_get_master_pipes_with_dpms_on +ffffffff822ae560 T link_resume +ffffffff822ae5a0 T link_set_dsc_on_stream +ffffffff822aea40 T link_set_dsc_pps_packet +ffffffff822aedd0 T link_set_dsc_enable +ffffffff822aee70 T link_update_dsc_config +ffffffff822aeee0 T link_calculate_sst_avg_time_slots_per_mtp +ffffffff822aef50 T link_reduce_mst_payload +ffffffff822af370 t update_mst_stream_alloc_table +ffffffff822af5f0 T link_increase_mst_payload +ffffffff822afa00 T link_set_dpms_off +ffffffff822b05b0 t update_psp_stream_config +ffffffff822b07b0 t update_sst_payload +ffffffff822b0df0 t get_ext_hdmi_settings +ffffffff822b1040 t write_i2c_retimer_setting +ffffffff822b1690 t write_i2c_default_retimer_setting +ffffffff822b1b80 t write_i2c_redriver_setting +ffffffff822b1ca0 t disable_link +ffffffff822b1e10 T link_set_dpms_on +ffffffff822b2840 t enable_stream_features +ffffffff822b2900 t allocate_mst_payload +ffffffff822b2d60 t log_vcp_x_y +ffffffff822b2ee0 t write_i2c +ffffffff822b2f70 t enable_link_dp +ffffffff822b4000 T link_create_link_service +ffffffff822b4470 T link_destroy_link_service +ffffffff822b44c0 T link_create +ffffffff822b54e0 T link_destroy +ffffffff822b6000 T link_get_cur_link_res +ffffffff822b6150 T link_get_cur_res_map +ffffffff822b6230 T link_restore_res_map +ffffffff822b7000 T dp_link_bandwidth_kbps +ffffffff822b70a0 T link_validate_mode_timing +ffffffff822b7680 t get_tmds_output_pixel_clock_100hz +ffffffff822b76f0 T link_validate_dpia_bandwidth +ffffffff822b8000 T link_create_ddc_service +ffffffff822b8170 T link_destroy_ddc_service +ffffffff822b8200 T set_ddc_transaction_type +ffffffff822b8230 T link_is_in_aux_transaction_mode +ffffffff822b8270 T set_dongle_type +ffffffff822b82a0 T link_get_aux_defer_delay +ffffffff822b83d0 T link_query_ddc_data +ffffffff822b8780 T link_aux_transfer_raw +ffffffff822b87b0 T link_get_fixed_vs_pe_retimer_write_address +ffffffff822b8840 T link_get_fixed_vs_pe_retimer_read_address +ffffffff822b88d0 T link_configure_fixed_vs_pe_retimer +ffffffff822b89a0 T link_aux_transfer_with_retries_no_mutex +ffffffff822b89b0 T link_query_fixed_vs_pe_retimer +ffffffff822b8a80 T try_to_configure_aux_timeout +ffffffff822b8b60 T get_ddc_pin +ffffffff822b8b90 T write_scdc_data +ffffffff822b8c80 T read_scdc_data +ffffffff822b9000 T is_dp_active_dongle +ffffffff822b9040 T is_dp_branch_device +ffffffff822b9070 T dp_parse_lttpr_repeater_count +ffffffff822b90f0 T link_bw_kbps_from_raw_frl_link_rate_data +ffffffff822b9130 T dp_is_fec_supported +ffffffff822b91e0 T dp_should_enable_fec +ffffffff822b92f0 T dp_is_128b_132b_signal +ffffffff822b93c0 T dp_is_lttpr_present +ffffffff822b9430 T decide_fallback_link_setting +ffffffff822b9700 T link_dp_get_encoding_format +ffffffff822b9750 t reduce_link_rate +ffffffff822b9810 T edp_decide_link_settings +ffffffff822b9940 T decide_edp_link_settings_with_dsc +ffffffff822b9d00 T link_decide_link_settings +ffffffff822ba130 T mst_decide_link_encoding_format +ffffffff822ba1b0 T dp_overwrite_extended_receiver_cap +ffffffff822ba2c0 t get_active_converter_info +ffffffff822ba6f0 T dpcd_set_source_specific_data +ffffffff822ba830 T dpcd_write_cable_id_to_dprx +ffffffff822ba8a0 T read_is_mst_supported +ffffffff822ba950 T dp_retrieve_lttpr_cap +ffffffff822bab60 T detect_dp_sink_caps +ffffffff822bab70 t retrieve_link_cap +ffffffff822bbc80 T detect_edp_sink_caps +ffffffff822bbfa0 T dp_get_max_link_enc_cap +ffffffff822bc090 T dp_get_verified_link_cap +ffffffff822bc0e0 T dp_get_max_link_cap +ffffffff822bc2d0 T dp_verify_link_cap_with_retries +ffffffff822bc7a0 T dp_is_sink_present +ffffffff822bca20 t intersect_frl_link_bw_support +ffffffff822bd000 T dpcd_get_tunneling_device_data +ffffffff822bd0d0 T dpia_query_hpd_status +ffffffff822be000 T link_dp_dpia_set_dptx_usb4_bw_alloc_support +ffffffff822be1b0 T dpia_handle_bw_alloc_response +ffffffff822be4c0 T dpia_handle_usb4_bandwidth_allocation_for_link +ffffffff822be690 T link_dp_dpia_allocate_usb4_bandwidth_for_stream +ffffffff822be810 T dpia_validate_usb4_bw +ffffffff822be940 t get_lowest_dpia_index +ffffffff822bf000 T dp_parse_link_loss_status +ffffffff822bf130 T dp_handle_link_loss +ffffffff822bf240 T dp_read_hpd_rx_irq_data +ffffffff822bf370 T dp_should_allow_hpd_rx_irq +ffffffff822bf3c0 T dp_handle_hpd_rx_irq +ffffffff822c0000 T dpcd_write_rx_power_ctrl +ffffffff822c0050 T dp_enable_link_phy +ffffffff822c00e0 T dp_disable_link_phy +ffffffff822c01b0 T dp_set_hw_lane_settings +ffffffff822c02a0 T dp_set_drive_settings +ffffffff822c0390 T dp_set_fec_ready +ffffffff822c0510 T dp_set_fec_enable +ffffffff822c1000 T dp_log_training_result +ffffffff822c1190 T dp_initialize_scrambling_data_symbols +ffffffff822c1230 T dp_training_pattern_to_dpcd_training_pattern +ffffffff822c12b0 T dp_get_nibble_at_index +ffffffff822c1300 T dp_wait_for_training_aux_rd_interval +ffffffff822c1320 T dp_hw_to_dpcd_lane_settings +ffffffff822c1400 T get_dpcd_link_rate +ffffffff822c1470 T dp_translate_training_aux_read_interval +ffffffff822c14b0 T dp_get_cr_failure +ffffffff822c1520 T is_repeater +ffffffff822c1560 T dp_is_max_vs_reached +ffffffff822c15f0 T dp_is_cr_done +ffffffff822c16c0 T dp_is_ch_eq_done +ffffffff822c1770 T dp_is_symbol_locked +ffffffff822c1820 T dp_is_interlane_aligned +ffffffff822c1850 T dp_check_link_loss_status +ffffffff822c18f0 T dp_get_lane_status_and_lane_adjust +ffffffff822c1a40 T dp_get_lttpr_mode_override +ffffffff822c1b00 T override_training_settings +ffffffff822c1dc0 T decide_cr_training_pattern +ffffffff822c1e00 T decide_eq_training_pattern +ffffffff822c1ee0 T dp_decide_lttpr_mode +ffffffff822c1f80 T dp_decide_lane_settings +ffffffff822c2300 T dp_decide_training_settings +ffffffff822c2390 T configure_lttpr_mode_transparent +ffffffff822c23e0 T dpcd_configure_lttpr_mode +ffffffff822c25a0 T repeater_training_done +ffffffff822c25f0 T dpcd_configure_channel_coding +ffffffff822c2650 T dpcd_set_training_pattern +ffffffff822c2700 T dpcd_set_link_settings +ffffffff822c2860 T dpcd_set_lane_settings +ffffffff822c28a0 T dpcd_set_lt_pattern_and_lane_settings +ffffffff822c2a90 T start_clock_recovery_pattern_early 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perform_fixed_vs_pe_nontransparent_training_sequence +ffffffff822c9bd0 T dp_perform_fixed_vs_pe_training_sequence +ffffffff822cb000 T core_link_read_dpcd +ffffffff822cb1a0 T core_link_write_dpcd +ffffffff822cc000 T dp_set_panel_mode +ffffffff822cc120 T dp_get_panel_mode +ffffffff822cc1e0 T edp_set_backlight_level_nits +ffffffff822cc2e0 T edp_get_backlight_level_nits +ffffffff822cc370 T edp_backlight_enable_aux +ffffffff822cc3e0 T set_default_brightness_aux +ffffffff822cc4b0 T edp_is_ilr_optimization_enabled +ffffffff822cc4f0 T get_max_link_rate_from_ilr_table +ffffffff822cc5d0 T edp_is_ilr_optimization_required +ffffffff822cc770 T edp_panel_backlight_power_on +ffffffff822cc820 T edp_set_panel_power +ffffffff822cc920 T edp_wait_for_t12 +ffffffff822cc980 T edp_add_delay_for_T9 +ffffffff822cc9d0 T edp_receiver_ready_T9 +ffffffff822cca90 T edp_receiver_ready_T7 +ffffffff822ccc30 T edp_power_alpm_dpcd_enable +ffffffff822ccca0 T edp_set_backlight_level +ffffffff822cce10 T edp_set_psr_allow_active +ffffffff822ccff0 T edp_get_psr_state +ffffffff822cd0c0 T edp_setup_psr +ffffffff822cd4b0 T edp_get_psr_residency +ffffffff822cd550 T edp_set_sink_vtotal_in_psr_active +ffffffff822cd5d0 T edp_set_replay_allow_active +ffffffff822cd6f0 T edp_get_replay_state +ffffffff822cd7a0 T edp_setup_replay +ffffffff822cd980 T edp_set_coasting_vtotal +ffffffff822cda30 T edp_replay_residency +ffffffff822cdaf0 T edp_get_backlight_level +ffffffff822cdc50 T edp_get_target_backlight_pwm +ffffffff822ce000 T link_get_hpd_state +ffffffff822ce070 T link_enable_hpd +ffffffff822ce0c0 T link_disable_hpd +ffffffff822ce110 T link_enable_hpd_filter +ffffffff822ce280 T program_hpd_filter +ffffffff822ce430 T link_get_hpd_gpio +ffffffff822ce510 T query_hpd_status +ffffffff822ce630 T get_hpd_line +ffffffff822cf000 T virtual_link_encoder_construct +ffffffff822cf060 t virtual_link_encoder_validate_output_with_stream +ffffffff822cf090 t virtual_link_encoder_hw_init +ffffffff822cf0c0 t virtual_link_encoder_setup +ffffffff822cf0f0 t virtual_link_encoder_enable_tmds_output +ffffffff822cf120 t virtual_link_encoder_enable_dp_output +ffffffff822cf150 t virtual_link_encoder_enable_dp_mst_output +ffffffff822cf180 t virtual_link_encoder_disable_output +ffffffff822cf1b0 t virtual_link_encoder_dp_set_lane_settings +ffffffff822cf1e0 t virtual_link_encoder_dp_set_phy_pattern +ffffffff822cf210 t virtual_link_encoder_update_mst_stream_allocation_table +ffffffff822cf240 t virtual_link_encoder_connect_dig_be_to_fe +ffffffff822cf270 t virtual_link_encoder_destroy +ffffffff822cf2c0 t virtual_link_encoder_get_max_link_cap +ffffffff822d0000 T virtual_setup_stream_encoder +ffffffff822d0030 T virtual_setup_stream_attribute +ffffffff822d0060 T virtual_reset_stream_encoder +ffffffff822d0090 T get_virtual_link_hwss +ffffffff822d00c0 t virtual_disable_link_output +ffffffff822d1000 T virtual_stream_encoder_construct +ffffffff822d1050 T virtual_stream_encoder_create +ffffffff822d1110 t virtual_stream_encoder_dp_set_stream_attribute +ffffffff822d1140 t virtual_stream_encoder_hdmi_set_stream_attribute +ffffffff822d1170 t virtual_stream_encoder_dvi_set_stream_attribute +ffffffff822d11a0 t virtual_stream_encoder_set_throttled_vcp_size +ffffffff822d11d0 t virtual_stream_encoder_update_hdmi_info_packets +ffffffff822d1200 t virtual_stream_encoder_stop_hdmi_info_packets +ffffffff822d1230 t virtual_stream_encoder_update_dp_info_packets +ffffffff822d1260 t virtual_stream_encoder_stop_dp_info_packets +ffffffff822d1290 t virtual_stream_encoder_dp_blank +ffffffff822d12c0 t virtual_stream_encoder_dp_unblank +ffffffff822d12f0 t virtual_audio_mute_control +ffffffff822d1320 t virtual_setup_stereo_sync +ffffffff822d1350 t virtual_stream_encoder_set_avmute +ffffffff822d1380 t virtual_dig_connect_to_otg +ffffffff822d13b0 t virtual_stream_encoder_reset_hdmi_stream_attribute +ffffffff822d13e0 t virtual_stream_encoder_set_dsc_pps_info_packet +ffffffff822d1410 t virtual_enc_dp_set_odm_combine +ffffffff822d2000 T dmub_dcn20_use_cached_inbox +ffffffff822d2040 T dmub_dcn20_reset +ffffffff822d2210 T dmub_dcn20_reset_release +ffffffff822d22e0 T dmub_dcn20_backdoor_load +ffffffff822d2590 T dmub_dcn20_setup_windows +ffffffff822d2af0 T dmub_dcn20_setup_mailbox +ffffffff822d2b50 T dmub_dcn20_get_inbox1_wptr +ffffffff822d2b80 T dmub_dcn20_get_inbox1_rptr +ffffffff822d2bb0 T dmub_dcn20_set_inbox1_wptr +ffffffff822d2be0 T dmub_dcn20_setup_out_mailbox +ffffffff822d2c40 T dmub_dcn20_get_outbox1_wptr +ffffffff822d2c70 T dmub_dcn20_set_outbox1_rptr +ffffffff822d2ca0 T dmub_dcn20_setup_outbox0 +ffffffff822d2cf0 T dmub_dcn20_get_outbox0_wptr +ffffffff822d2d20 T dmub_dcn20_set_outbox0_rptr +ffffffff822d2d50 T dmub_dcn20_is_hw_init +ffffffff822d2db0 T dmub_dcn20_is_supported +ffffffff822d2e10 T dmub_dcn20_set_gpint +ffffffff822d2e40 T dmub_dcn20_is_gpint_acked +ffffffff822d2ea0 T dmub_dcn20_get_gpint_response +ffffffff822d2ed0 T dmub_dcn20_get_fw_boot_status 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mod_freesync_get_settings +ffffffff822e6670 T mod_freesync_calc_field_rate_from_timing +ffffffff822e66c0 T mod_freesync_get_freesync_enabled +ffffffff822e66f0 T mod_freesync_is_valid_range +ffffffff822e7000 T mod_hdcp_get_memory_size +ffffffff822e7030 T mod_hdcp_setup +ffffffff822e70b0 t reset_connection +ffffffff822e7220 t push_error_status +ffffffff822e7330 T mod_hdcp_teardown +ffffffff822e73b0 T mod_hdcp_add_display +ffffffff822e7660 t reset_authentication +ffffffff822e7850 t set_state_id +ffffffff822e78f0 T mod_hdcp_remove_display +ffffffff822e7af0 T mod_hdcp_update_display +ffffffff822e7e50 T mod_hdcp_query_display +ffffffff822e7fa0 T mod_hdcp_reset_connection +ffffffff822e8000 T mod_hdcp_process_event +ffffffff822e87e0 T mod_hdcp_signal_type_to_operation_mode +ffffffff822e9000 T mod_hdcp_execute_and_set +ffffffff822e90b0 T mod_hdcp_hdcp1_execution +ffffffff822e9300 t exchange_ksvs +ffffffff822e9660 t computations_validate_rx_test_for_repeater +ffffffff822e9930 t wait_for_ready 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mod_hdcp_hdcp2_transition +ffffffff822ee7b0 t set_state_id +ffffffff822ee850 T mod_hdcp_hdcp2_dp_transition +ffffffff822ef000 T mod_hdcp_read_bksv +ffffffff822ef080 T mod_hdcp_read_bcaps +ffffffff822ef100 T mod_hdcp_read_bstatus +ffffffff822ef180 T mod_hdcp_read_r0p +ffffffff822ef200 T mod_hdcp_read_ksvlist +ffffffff822ef350 T mod_hdcp_read_vp +ffffffff822ef520 T mod_hdcp_read_binfo +ffffffff822ef590 T mod_hdcp_write_aksv +ffffffff822ef630 T mod_hdcp_write_ainfo +ffffffff822ef6d0 T mod_hdcp_write_an +ffffffff822ef770 T mod_hdcp_read_hdcp2version +ffffffff822ef7e0 T mod_hdcp_read_rxcaps +ffffffff822ef850 T mod_hdcp_read_rxstatus +ffffffff822ef8e0 T mod_hdcp_read_ake_cert +ffffffff822ef9b0 T mod_hdcp_read_h_prime +ffffffff822efa70 T mod_hdcp_read_pairing_info +ffffffff822efb10 T mod_hdcp_read_l_prime +ffffffff822efbd0 T mod_hdcp_read_rx_id_list +ffffffff822efd40 T mod_hdcp_read_stream_ready +ffffffff822efe00 T mod_hdcp_write_ake_init +ffffffff822efeb0 T mod_hdcp_write_no_stored_km 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mod_hdcp_hdcp1_enable_dp_stream_encryption +ffffffff822f3fb0 T mod_hdcp_hdcp1_link_maintenance +ffffffff822f4070 T mod_hdcp_hdcp2_create_session +ffffffff822f41e0 T mod_hdcp_hdcp2_destroy_session +ffffffff822f4450 T mod_hdcp_hdcp2_prepare_ake_init +ffffffff822f4550 T mod_hdcp_hdcp2_validate_ake_cert +ffffffff822f4700 T mod_hdcp_hdcp2_validate_h_prime +ffffffff822f4880 T mod_hdcp_hdcp2_prepare_lc_init +ffffffff822f4980 T mod_hdcp_hdcp2_validate_l_prime +ffffffff822f4aa0 T mod_hdcp_hdcp2_prepare_eks +ffffffff822f4bf0 T mod_hdcp_hdcp2_enable_encryption +ffffffff822f4d60 T mod_hdcp_hdcp2_validate_rx_id_list +ffffffff822f4ee0 T mod_hdcp_hdcp2_enable_dp_stream_encryption +ffffffff822f5050 T mod_hdcp_hdcp2_prepare_stream_management +ffffffff822f5160 T mod_hdcp_hdcp2_validate_stream_ready +ffffffff822f6000 T mod_build_vsc_infopacket +ffffffff822f6270 T mod_build_hf_vsif_infopacket +ffffffff822f63e0 T mod_build_adaptive_sync_infopacket +ffffffff822f64a0 T mod_build_adaptive_sync_infopacket_v2 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amdgpu_dpm_handle_passthrough_sbr +ffffffff822fb650 T amdgpu_dpm_send_hbm_bad_pages_num +ffffffff822fb6d0 T amdgpu_dpm_send_hbm_bad_channel_flag +ffffffff822fb750 T amdgpu_dpm_get_dpm_freq_range +ffffffff822fb7f0 T amdgpu_dpm_set_soft_freq_range +ffffffff822fb890 T amdgpu_dpm_write_watermarks_table +ffffffff822fb910 T amdgpu_dpm_wait_for_event +ffffffff822fb9a0 T amdgpu_dpm_set_residency_gfxoff +ffffffff822fba20 T amdgpu_dpm_get_residency_gfxoff +ffffffff822fbaa0 T amdgpu_dpm_get_entrycount_gfxoff +ffffffff822fbb20 T amdgpu_dpm_get_status_gfxoff +ffffffff822fbba0 T amdgpu_dpm_get_thermal_throttling_counter +ffffffff822fbbf0 T amdgpu_dpm_gfx_state_change +ffffffff822fbc60 T amdgpu_dpm_get_ecc_info +ffffffff822fbce0 T amdgpu_dpm_get_vce_clock_state +ffffffff822fbd70 T amdgpu_dpm_get_current_power_state +ffffffff822fbde0 T amdgpu_dpm_set_power_state +ffffffff822fbf40 T amdgpu_dpm_dispatch_task +ffffffff822fbfe0 T amdgpu_dpm_get_performance_level +ffffffff822fc070 T amdgpu_dpm_force_performance_level +ffffffff822fc250 T amdgpu_dpm_get_pp_num_states +ffffffff822fc2e0 T amdgpu_dpm_get_pp_table +ffffffff822fc370 T amdgpu_dpm_set_fine_grain_clk_vol +ffffffff822fc410 T amdgpu_dpm_odn_edit_dpm_table +ffffffff822fc4b0 T amdgpu_dpm_print_clock_levels +ffffffff822fc540 T amdgpu_dpm_emit_clock_levels +ffffffff822fc5e0 T amdgpu_dpm_set_ppfeature_status +ffffffff822fc670 T amdgpu_dpm_get_ppfeature_status +ffffffff822fc700 T amdgpu_dpm_force_clock_level +ffffffff822fc790 T amdgpu_dpm_get_sclk_od +ffffffff822fc810 T amdgpu_dpm_set_sclk_od +ffffffff822fc990 T amdgpu_dpm_get_mclk_od +ffffffff822fca10 T amdgpu_dpm_set_mclk_od +ffffffff822fcb90 T amdgpu_dpm_get_power_profile_mode +ffffffff822fcc20 T amdgpu_dpm_set_power_profile_mode +ffffffff822fccc0 T amdgpu_dpm_get_gpu_metrics +ffffffff822fcd50 T amdgpu_dpm_get_fan_control_mode +ffffffff822fcde0 T amdgpu_dpm_set_fan_speed_pwm +ffffffff822fce70 T amdgpu_dpm_get_fan_speed_pwm +ffffffff822fcf00 T amdgpu_dpm_get_fan_speed_rpm +ffffffff822fcf90 T amdgpu_dpm_set_fan_speed_rpm +ffffffff822fd020 T amdgpu_dpm_set_fan_control_mode +ffffffff822fd0b0 T amdgpu_dpm_get_power_limit +ffffffff822fd160 T amdgpu_dpm_set_power_limit +ffffffff822fd1f0 T amdgpu_dpm_is_cclk_dpm_supported +ffffffff822fd260 T amdgpu_dpm_debugfs_print_current_performance_level +ffffffff822fd2f0 T amdgpu_dpm_get_smu_prv_buf_details +ffffffff822fd390 T amdgpu_dpm_is_overdrive_supported +ffffffff822fd400 T amdgpu_dpm_set_pp_table +ffffffff822fd4a0 T amdgpu_dpm_get_num_cpu_cores +ffffffff822fd4f0 T amdgpu_dpm_stb_debug_fs_init +ffffffff822fd540 T amdgpu_dpm_display_configuration_change +ffffffff822fd5d0 T amdgpu_dpm_get_clock_by_type +ffffffff822fd670 T amdgpu_dpm_get_display_mode_validation_clks +ffffffff822fd700 T amdgpu_dpm_get_clock_by_type_with_latency +ffffffff822fd7a0 T amdgpu_dpm_get_clock_by_type_with_voltage +ffffffff822fd840 T amdgpu_dpm_set_watermarks_for_clocks_ranges +ffffffff822fd8d0 T amdgpu_dpm_display_clock_voltage_request +ffffffff822fd960 T amdgpu_dpm_get_current_clocks +ffffffff822fd9f0 T amdgpu_dpm_notify_smu_enable_pwe +ffffffff822fda70 T amdgpu_dpm_set_active_display_count +ffffffff822fdb00 T amdgpu_dpm_set_min_deep_sleep_dcefclk +ffffffff822fdb90 T amdgpu_dpm_set_hard_min_dcefclk_by_freq +ffffffff822fdc30 T amdgpu_dpm_set_hard_min_fclk_by_freq +ffffffff822fdcd0 T amdgpu_dpm_display_disable_memory_clock_switch +ffffffff822fdd60 T amdgpu_dpm_get_max_sustainable_clocks_by_dc +ffffffff822fddf0 T amdgpu_dpm_get_uclk_dpm_states +ffffffff822fde90 T amdgpu_dpm_get_dpm_clock_table +ffffffff822fe000 T amdgpu_dpm_get_active_displays +ffffffff822fe0a0 T amdgpu_dpm_get_vblank_time +ffffffff822fe150 T amdgpu_dpm_get_vrefresh +ffffffff822ff000 T amdgpu_pm_sysfs_init +ffffffff822ff030 T amdgpu_pm_sysfs_fini +ffffffff822ff060 T amdgpu_debugfs_pm_init +ffffffff82300000 T amdgpu_dpm_print_class_info +ffffffff823002b0 T amdgpu_dpm_print_cap_info +ffffffff82300340 T amdgpu_dpm_print_ps_status +ffffffff823003d0 T amdgpu_pm_print_power_states +ffffffff82300460 T amdgpu_get_platform_caps +ffffffff82300500 T amdgpu_parse_extended_power_table +ffffffff823012d0 t amdgpu_parse_clk_voltage_dep_table +ffffffff82301380 T amdgpu_free_extended_power_table +ffffffff82301490 T amdgpu_add_thermal_controller +ffffffff823018e0 T amdgpu_get_vce_clock_state +ffffffff82301920 T amdgpu_legacy_dpm_compute_clocks +ffffffff82301db0 T amdgpu_dpm_thermal_work_handler +ffffffff82302000 t pp_early_init +ffffffff82302100 t pp_late_init +ffffffff82302220 t pp_sw_init +ffffffff823022b0 t pp_sw_fini +ffffffff82302300 t pp_hw_init +ffffffff82302360 t pp_hw_fini +ffffffff823023d0 t pp_late_fini +ffffffff82302430 t pp_suspend +ffffffff82302480 t pp_resume +ffffffff823024a0 t pp_is_idle +ffffffff823024d0 t pp_wait_for_idle +ffffffff82302500 t pp_sw_reset +ffffffff82302530 t pp_set_clockgating_state +ffffffff82302560 t pp_set_powergating_state +ffffffff82302590 t pp_dpm_set_fan_control_mode +ffffffff82302600 t pp_dpm_get_fan_control_mode +ffffffff82302670 t pp_dpm_set_fan_speed_pwm +ffffffff823026d0 t pp_dpm_get_fan_speed_pwm +ffffffff82302730 t pp_dpm_force_clock_level +ffffffff82302790 t pp_dpm_print_clock_levels +ffffffff823027f0 t pp_dpm_emit_clock_levels +ffffffff82302850 t pp_dpm_force_performance_level +ffffffff823028f0 t pp_dpm_get_sclk_od +ffffffff82302950 t pp_dpm_set_sclk_od +ffffffff823029b0 t pp_dpm_get_mclk_od +ffffffff82302a10 t pp_dpm_set_mclk_od +ffffffff82302a70 t pp_dpm_read_sensor +ffffffff82302b30 t pp_dpm_get_performance_level +ffffffff82302b70 t pp_dpm_get_current_power_state +ffffffff82302bf0 t pp_dpm_get_fan_speed_rpm +ffffffff82302c50 t pp_dpm_set_fan_speed_rpm +ffffffff82302cb0 t pp_dpm_get_pp_num_states +ffffffff82302df0 t pp_dpm_get_pp_table +ffffffff82302e40 t pp_dpm_set_pp_table +ffffffff82302f70 t pp_dpm_switch_power_profile +ffffffff823030b0 t pp_dpm_get_vce_clock_state +ffffffff82303100 t pp_dpm_dispatch_tasks +ffffffff82303140 t pp_dpm_load_fw +ffffffff823031b0 t pp_dpm_fw_loading_complete +ffffffff823031e0 t pp_set_powergating_by_smu +ffffffff82303360 t pp_set_clockgating_by_smu +ffffffff823033d0 t pp_set_power_limit +ffffffff82303490 t pp_get_power_limit +ffffffff82303530 t pp_get_power_profile_mode +ffffffff82303590 t pp_set_power_profile_mode +ffffffff823035f0 t pp_set_fine_grain_clk_vol +ffffffff82303650 t pp_odn_edit_dpm_table +ffffffff823036b0 t pp_dpm_set_mp1_state +ffffffff82303710 t pp_smu_i2c_bus_access +ffffffff82303770 t pp_gfx_state_change_set +ffffffff823037d0 t pp_dpm_get_sclk +ffffffff82303820 t pp_dpm_get_mclk +ffffffff82303870 t pp_display_configuration_change +ffffffff823038c0 t pp_get_display_power_level +ffffffff82303900 t pp_get_current_clocks +ffffffff82303a20 t pp_get_clock_by_type +ffffffff82303a70 t pp_get_clock_by_type_with_latency +ffffffff82303ac0 t pp_get_clock_by_type_with_voltage +ffffffff82303b10 t pp_set_watermarks_for_clocks_ranges +ffffffff82303b50 t pp_display_clock_voltage_request +ffffffff82303b90 t pp_get_display_mode_validation_clocks +ffffffff82303bf0 t pp_notify_smu_enable_pwe +ffffffff82303c50 t pp_enable_mgpu_fan_boost +ffffffff82303cb0 t pp_set_active_display_count +ffffffff82303cf0 t pp_set_hard_min_dcefclk_by_freq +ffffffff82303d50 t pp_set_hard_min_fclk_by_freq +ffffffff82303db0 t pp_set_min_deep_sleep_dcefclk +ffffffff82303e10 t pp_get_asic_baco_capability +ffffffff82303e80 t pp_get_asic_baco_state +ffffffff82303ee0 t pp_set_asic_baco_state +ffffffff82303f50 t pp_get_ppfeature_status +ffffffff82303fb0 t pp_set_ppfeature_status +ffffffff82304000 t pp_asic_reset_mode_2 +ffffffff82304060 t pp_set_df_cstate +ffffffff823040c0 t pp_set_xgmi_pstate +ffffffff82304120 t pp_get_gpu_metrics +ffffffff82304180 t pp_get_prv_buffer_details +ffffffff82304200 t pp_pm_compute_clocks +ffffffff823042c0 t pp_swctf_delayed_work_handler +ffffffff82304400 t __delayed_work_tick +ffffffff82305000 T ci_baco_set_state +ffffffff82306000 T baco_program_registers +ffffffff823060d0 t baco_cmd_handler +ffffffff82306250 T soc15_baco_program_registers +ffffffff82307000 T fiji_baco_set_state +ffffffff82308000 T phm_setup_asic +ffffffff82308050 T phm_power_down_asic +ffffffff823080a0 T phm_set_power_state +ffffffff82308110 T phm_enable_dynamic_state_management +ffffffff823081c0 T phm_disable_dynamic_state_management +ffffffff82308260 T phm_force_dpm_levels +ffffffff823082b0 T phm_apply_state_adjust_rules +ffffffff82308300 T phm_apply_clock_adjust_rules +ffffffff82308350 T phm_powerdown_uvd +ffffffff823083a0 T phm_disable_clock_power_gatings +ffffffff823083f0 T phm_pre_display_configuration_changed +ffffffff82308450 T phm_display_configuration_changed +ffffffff823084b0 T phm_notify_smc_display_config_after_ps_adjustment +ffffffff82308510 T phm_stop_thermal_controller +ffffffff82308570 T phm_register_irq_handlers +ffffffff823085c0 T phm_start_thermal_controller +ffffffff82308710 T phm_check_smc_update_required_for_display_configuration +ffffffff82308770 T phm_check_states_equal +ffffffff823087c0 T phm_store_dal_configuration_data +ffffffff82308910 T phm_get_dal_power_level +ffffffff82308970 T phm_set_cpu_power_state +ffffffff823089c0 T phm_get_performance_level +ffffffff82308a20 T phm_get_clock_info +ffffffff82308b90 T phm_get_current_shallow_sleep_clocks +ffffffff82308be0 T phm_get_clock_by_type +ffffffff82308c30 T phm_get_clock_by_type_with_latency +ffffffff82308c80 T phm_get_clock_by_type_with_voltage +ffffffff82308cd0 T phm_set_watermarks_for_clocks_ranges +ffffffff82308d20 T phm_display_clock_voltage_request +ffffffff82308d70 T phm_get_max_high_clocks +ffffffff82308dc0 T phm_disable_smc_firmware_ctf +ffffffff82308e20 T phm_set_active_display_count +ffffffff82309000 T hwmgr_early_init +ffffffff82309460 t polaris_set_asic_special_caps +ffffffff823094e0 T hwmgr_sw_init +ffffffff82309550 T hwmgr_sw_fini +ffffffff823095a0 T hwmgr_hw_init +ffffffff82309760 T hwmgr_hw_fini +ffffffff82309820 T hwmgr_suspend +ffffffff823098a0 T hwmgr_resume +ffffffff82309940 T hwmgr_handle_task +ffffffff8230a000 T polaris_baco_set_state +ffffffff8230b000 T pp_override_get_default_fuse_value +ffffffff8230c000 T psm_init_power_state_table +ffffffff8230c2a0 T psm_fini_power_state_table +ffffffff8230c360 T psm_set_boot_states +ffffffff8230c410 T psm_set_performance_states +ffffffff8230c4c0 T psm_set_user_performance_state +ffffffff8230c550 T psm_adjust_power_state_dynamic +ffffffff8230d000 T atomctrl_initialize_mc_reg_table +ffffffff8230d210 T atomctrl_initialize_mc_reg_table_v2_2 +ffffffff8230d420 T atomctrl_set_engine_dram_timings_rv770 +ffffffff8230d490 T atomctrl_get_memory_pll_dividers_si +ffffffff8230d570 T atomctrl_get_memory_pll_dividers_vi +ffffffff8230d5f0 T atomctrl_get_memory_pll_dividers_ai +ffffffff8230d6a0 T atomctrl_get_engine_pll_dividers_kong +ffffffff8230d720 T atomctrl_get_engine_pll_dividers_vi +ffffffff8230d7f0 T atomctrl_get_engine_pll_dividers_ai +ffffffff8230d8d0 T atomctrl_get_dfs_pll_dividers_vi +ffffffff8230d990 T atomctrl_get_reference_clock +ffffffff8230d9f0 T atomctrl_is_voltage_controlled_by_gpio_v3 +ffffffff8230dab0 T atomctrl_get_voltage_table_v3 +ffffffff8230dc10 T atomctrl_get_pp_assign_pin +ffffffff8230dcf0 T atomctrl_calculate_voltage_evv_on_sclk +ffffffff8230e0c0 t GetScaledFraction +ffffffff8230e150 t fDecodeLeakageID +ffffffff8230e1b0 t fSqrt +ffffffff8230e230 T atomctrl_get_voltage_evv_on_sclk +ffffffff8230e2b0 T atomctrl_get_voltage_evv +ffffffff8230e360 T atomctrl_get_mpll_reference_clock +ffffffff8230e3d0 T atomctrl_is_asic_internal_ss_supported +ffffffff8230e420 T atomctrl_get_memory_clock_spread_spectrum +ffffffff8230e520 T atomctrl_get_engine_clock_spread_spectrum +ffffffff8230e620 T atomctrl_read_efuse +ffffffff8230e6d0 T atomctrl_set_ac_timing_ai +ffffffff8230e730 T atomctrl_get_voltage_evv_on_sclk_ai +ffffffff8230e7b0 T atomctrl_get_smc_sclk_range_table +ffffffff8230e860 T atomctrl_get_vddc_shared_railinfo +ffffffff8230e8d0 T atomctrl_get_avfs_information +ffffffff8230ea60 T atomctrl_get_svi2_info +ffffffff8230eb40 T atomctrl_get_leakage_id_from_efuse +ffffffff8230eba0 T atomctrl_get_leakage_vddc_base_on_leakage +ffffffff8230ed40 T atomctrl_get_voltage_range +ffffffff8230ee00 T atomctrl_get_edc_hilo_leakage_offset_table +ffffffff8230ee80 T atomctrl_get_edc_leakage_table +ffffffff8230f000 T pp_atomfwctrl_is_voltage_controlled_by_gpio_v4 +ffffffff8230f0c0 T pp_atomfwctrl_get_voltage_table_v4 +ffffffff8230f280 T pp_atomfwctrl_get_pp_assign_pin +ffffffff8230f360 T pp_atomfwctrl_enter_self_refresh +ffffffff8230f390 T pp_atomfwctrl_get_gpu_pll_dividers_vega10 +ffffffff8230f440 T pp_atomfwctrl_get_avfs_information +ffffffff8230f780 T pp_atomfwctrl_get_gpio_information +ffffffff8230f820 T pp_atomfwctrl_get_clk_information_by_clkid +ffffffff8230f8b0 T pp_atomfwctrl_get_vbios_bootup_values +ffffffff8230fc30 T pp_atomfwctrl_get_smc_dpm_information +ffffffff82310000 T encode_pcie_lane_width +ffffffff82310030 T decode_pcie_lane_width +ffffffff82311000 t pp_tables_v1_0_initialize +ffffffff82312450 t pp_tables_v1_0_uninitialize +ffffffff82312600 T get_number_of_powerplay_table_entries_v1_0 +ffffffff823126b0 T get_powerplay_table_entry_v1_0 +ffffffff82313000 T pp_tables_get_response_times +ffffffff823130d0 T pp_tables_get_num_of_entries +ffffffff82313190 T pp_tables_get_entry +ffffffff823134a0 t init_non_clock_fields +ffffffff823135e0 t pp_tables_initialize +ffffffff82314760 t pp_tables_uninitialize +ffffffff82314960 t get_number_of_vce_state_table_entries +ffffffff82314a50 t get_vce_state_table_entry +ffffffff82315000 T smu10_init_function_pointers +ffffffff82315040 t smu10_hwmgr_backend_init +ffffffff823156e0 t smu10_hwmgr_backend_fini +ffffffff82315820 t smu10_setup_asic_task +ffffffff82315890 t smu10_get_power_state_size +ffffffff823158c0 t smu10_apply_state_adjust_rules +ffffffff823158f0 t smu10_dpm_force_dpm_level +ffffffff82315e70 t smu10_enable_dpm_tasks +ffffffff82315f30 t smu10_disable_dpm_tasks +ffffffff82315f60 t smu10_dpm_patch_boot_state +ffffffff82315f90 t smu10_dpm_get_pp_table_entry +ffffffff82315ff0 t smu10_dpm_get_num_of_pp_table_entries +ffffffff82316040 t smu10_powergate_vcn +ffffffff823160e0 t smu10_dpm_get_mclk +ffffffff82316140 t smu10_dpm_get_sclk +ffffffff82316190 t smu10_set_power_state_tasks +ffffffff82316200 t smu10_set_cpu_power_state +ffffffff82316230 t smu10_store_cc6_data +ffffffff823162a0 t smu10_get_dal_power_level +ffffffff823162d0 t smu10_get_performance_level +ffffffff82316370 t smu10_get_current_shallow_sleep_clocks +ffffffff823163d0 t smu10_get_clock_by_type_with_latency +ffffffff82316520 t smu10_get_clock_by_type_with_voltage +ffffffff82316630 t smu10_set_watermarks_for_clocks_ranges +ffffffff82316700 t smu10_display_clock_voltage_request +ffffffff823167a0 t smu10_get_max_high_clocks +ffffffff823167d0 t smu10_power_off_asic +ffffffff82316820 t smu10_force_clock_level +ffffffff823169e0 t smu10_print_clock_levels +ffffffff82316dd0 t smu10_gfx_off_control +ffffffff82316ee0 t smu10_read_sensor +ffffffff82317070 t smu10_set_active_display_count +ffffffff823170d0 t smu10_set_min_deep_sleep_dcefclk +ffffffff82317130 t smu10_get_power_profile_mode +ffffffff82317170 t smu10_set_power_profile_mode +ffffffff823172a0 t smu10_set_fine_grain_clk_vol +ffffffff823174b0 t smu10_powergate_mmhub +ffffffff823174d0 t smu10_smus_notify_pwe +ffffffff823174f0 t smu10_powergate_sdma +ffffffff82317510 t smu10_set_hard_min_dcefclk_by_freq +ffffffff82317570 t smu10_set_hard_min_fclk_by_freq +ffffffff823175d0 t smu10_set_hard_min_gfxclk_by_freq +ffffffff82317630 t smu10_set_soft_max_gfxclk_by_freq +ffffffff82317690 t smu10_asic_reset +ffffffff823176b0 t smu10_gfx_state_change +ffffffff823176f0 t smu10_dpm_get_pp_table_entry_callback +ffffffff82318000 T smu7_baco_get_capability +ffffffff82318060 T smu7_baco_get_state +ffffffff823180b0 T smu7_baco_set_state +ffffffff82319000 T smu7_powerdown_uvd +ffffffff82319050 T smu7_disable_clock_power_gating +ffffffff823190e0 T smu7_powergate_uvd +ffffffff823191d0 T smu7_powergate_vce +ffffffff823192c0 T smu7_update_clock_gatings +ffffffff82319670 T smu7_powergate_gfx +ffffffff8231a000 T smu7_get_sleep_divider_id_from_clock +ffffffff8231a0a0 T smu7_init_function_pointers +ffffffff8231a100 t smu7_hwmgr_backend_init +ffffffff8231bed0 t smu7_hwmgr_backend_fini +ffffffff8231bf40 t smu7_setup_asic_task +ffffffff8231c2b0 t smu7_get_power_state_size +ffffffff8231c2e0 t smu7_apply_state_adjust_rules +ffffffff8231c780 t smu7_force_dpm_level +ffffffff8231cc90 t smu7_enable_dpm_tasks +ffffffff8231f520 t smu7_disable_dpm_tasks +ffffffff8231fb60 t smu7_dpm_patch_boot_state +ffffffff8231fca0 t smu7_get_pp_table_entry +ffffffff823200a0 t smu7_get_number_of_powerplay_table_entries +ffffffff82320110 t smu7_dpm_get_mclk +ffffffff823201b0 t smu7_dpm_get_sclk +ffffffff82320250 t smu7_set_power_state_tasks +ffffffff82320f70 t smu7_notify_smc_display_config_after_ps_adjustment +ffffffff82320fa0 t smu7_display_configuration_changed_task +ffffffff82321160 t smu7_set_max_fan_rpm_output +ffffffff82321190 t smu7_set_max_fan_pwm_output +ffffffff823211b0 t smu7_set_fan_control_mode +ffffffff82321240 t smu7_get_fan_control_mode +ffffffff82321280 t smu7_register_irq_handlers +ffffffff82321330 t smu7_check_smc_update_required_for_display_configuration +ffffffff823213e0 t smu7_check_states_equal +ffffffff82321580 t smu7_get_performance_level +ffffffff82321610 t smu7_get_clock_by_type +ffffffff823217d0 t smu7_get_clock_by_type_with_latency +ffffffff823219a0 t smu7_set_watermarks_for_clocks_ranges +ffffffff82321bc0 t smu7_get_max_high_clocks +ffffffff82321c40 t smu7_power_off_asic +ffffffff82321ca0 t smu7_force_clock_level +ffffffff82321db0 t smu7_print_clock_levels +ffffffff823223a0 t smu7_get_sclk_od +ffffffff82322400 t smu7_set_sclk_od +ffffffff823224c0 t smu7_get_mclk_od +ffffffff82322520 t smu7_set_mclk_od +ffffffff823225e0 t smu7_read_sensor +ffffffff823228a0 t smu7_avfs_control +ffffffff82322970 t smu7_notify_cac_buffer_info +ffffffff82322b10 t smu7_get_thermal_temperature_range +ffffffff82322bb0 t smu7_get_power_profile_mode +ffffffff82322bf0 t smu7_set_power_profile_mode +ffffffff82322e50 t smu7_odn_edit_dpm_table +ffffffff82323000 t phm_add_voltage +ffffffff82323110 t smu7_copy_and_switch_arb_sets +ffffffff82323340 t smu7_check_dpm_table_updated +ffffffff823234a0 t smu7_odn_initial_default_setting +ffffffff823235d0 t smu7_set_dpm_event_sources +ffffffff823236f0 t smu7_get_pp_table_entry_callback_func_v0 +ffffffff82323bb0 t smu7_get_pp_table_entry_callback_func_v1 +ffffffff82325000 T smu7_enable_didt_config +ffffffff823253c0 t smu7_program_pt_config_registers +ffffffff82325590 t smu7_enable_didt +ffffffff82325780 T smu7_disable_didt_config +ffffffff82325850 T smu7_enable_smc_cac +ffffffff823258e0 T smu7_disable_smc_cac +ffffffff82325970 T smu7_set_power_limit +ffffffff823259d0 T smu7_enable_power_containment +ffffffff82325b60 T smu7_disable_power_containment +ffffffff82325c80 T smu7_power_control_set_level +ffffffff82326000 T smu7_fan_ctrl_get_fan_speed_info +ffffffff82326080 T smu7_fan_ctrl_get_fan_speed_pwm +ffffffff82326150 T smu7_fan_ctrl_get_fan_speed_rpm +ffffffff82326200 T smu7_fan_ctrl_set_static_mode +ffffffff82326330 T smu7_fan_ctrl_set_default_mode +ffffffff82326410 T smu7_fan_ctrl_start_smc_fan_control +ffffffff82326540 T smu7_fan_ctrl_stop_smc_fan_control +ffffffff82326560 T smu7_fan_ctrl_set_fan_speed_pwm +ffffffff82326740 T smu7_fan_ctrl_reset_fan_speed_to_default +ffffffff82326930 T smu7_fan_ctrl_set_fan_speed_rpm +ffffffff82326b10 T smu7_thermal_get_temperature +ffffffff82326b70 T smu7_thermal_disable_alert +ffffffff82326c10 T smu7_thermal_stop_thermal_controller +ffffffff82326d90 T smu7_start_thermal_controller +ffffffff82327120 T smu7_thermal_ctrl_uninitialize_thermal_controller +ffffffff82328000 T smu8_init_function_pointers +ffffffff82328040 t smu8_hwmgr_backend_init +ffffffff82328520 t smu8_hwmgr_backend_fini +ffffffff823285a0 t smu8_setup_asic_task +ffffffff82328ac0 t smu8_get_power_state_size +ffffffff82328af0 t smu8_apply_state_adjust_rules +ffffffff82328c40 t smu8_dpm_force_dpm_level +ffffffff82328f20 t smu8_enable_dpm_tasks +ffffffff823290b0 t smu8_disable_dpm_tasks +ffffffff82329190 t smu8_dpm_patch_boot_state +ffffffff823291f0 t smu8_dpm_get_pp_table_entry +ffffffff82329250 t smu8_dpm_get_num_of_pp_table_entries +ffffffff823292a0 t smu8_dpm_powerdown_uvd +ffffffff823292f0 t smu8_dpm_powergate_vce +ffffffff823294c0 t smu8_dpm_powergate_uvd +ffffffff823296d0 t smu8_dpm_powergate_acp +ffffffff82329730 t smu8_dpm_get_mclk +ffffffff82329760 t smu8_dpm_get_sclk +ffffffff823297d0 t smu8_set_power_state_tasks +ffffffff82329ad0 t smu8_set_cpu_power_state +ffffffff82329b50 t smu8_store_cc6_data +ffffffff82329bd0 t smu8_get_dal_power_level +ffffffff82329c50 t smu8_get_performance_level +ffffffff82329d50 t smu8_get_current_shallow_sleep_clocks +ffffffff82329db0 t smu8_get_clock_by_type +ffffffff82329ef0 t smu8_get_max_high_clocks +ffffffff82329fb0 t smu8_power_off_asic +ffffffff8232a030 t smu8_force_clock_level +ffffffff8232a0a0 t smu8_print_clock_levels +ffffffff8232a280 t smu8_read_sensor +ffffffff8232a590 t smu8_notify_cac_buffer_info +ffffffff8232a640 t smu8_get_thermal_temperature_range +ffffffff8232a6c0 t smu8_dpm_get_pp_table_entry_callback +ffffffff8232b000 T smu9_baco_get_capability +ffffffff8232b0e0 T smu9_baco_get_state +ffffffff8232c000 T convert_to_vid +ffffffff8232c050 T convert_to_vddc +ffffffff8232c090 T phm_copy_clock_limits_array +ffffffff8232c170 T phm_copy_overdrive_settings_limits_array +ffffffff8232c250 T phm_set_field_to_u32 +ffffffff8232c2b0 T phm_wait_on_register +ffffffff8232c3a0 T phm_wait_on_indirect_register +ffffffff8232c4b0 T phm_wait_for_register_unequal +ffffffff8232c580 T phm_wait_for_indirect_register_unequal +ffffffff8232c680 T phm_cf_want_uvd_power_gating +ffffffff8232c6c0 T phm_cf_want_vce_power_gating +ffffffff8232c700 T phm_trim_voltage_table +ffffffff8232c820 T phm_get_svi2_mvdd_voltage_table +ffffffff8232c9a0 T phm_get_svi2_vddci_voltage_table +ffffffff8232cb20 T phm_get_svi2_vdd_voltage_table +ffffffff8232cbc0 T phm_trim_voltage_table_to_fit_state_table +ffffffff8232ccb0 T phm_reset_single_dpm_table +ffffffff8232cd10 T phm_setup_pcie_table_entry +ffffffff8232cd50 T phm_get_dpm_level_enable_mask_value +ffffffff8232ce30 T phm_get_voltage_index +ffffffff8232ceb0 T phm_get_voltage_id +ffffffff8232cf30 T phm_find_closest_vddci +ffffffff8232cfa0 T phm_find_boot_level +ffffffff8232d010 T phm_get_sclk_for_voltage_evv +ffffffff8232d0d0 T phm_initializa_dynamic_state_adjustment_rule_settings +ffffffff8232d1e0 T phm_get_lowest_enabled_level +ffffffff8232d220 T phm_apply_dal_min_voltage_request +ffffffff8232d2f0 T phm_get_voltage_evv_on_sclk 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smu_set_residency_gfxoff +ffffffff8237a050 T smu_get_residency_gfxoff +ffffffff8237a0a0 T smu_get_entrycount_gfxoff +ffffffff8237a0f0 T smu_get_status_gfxoff +ffffffff8237a150 T smu_set_soft_freq_range +ffffffff8237a190 T smu_get_dpm_freq_range +ffffffff8237a1e0 T smu_set_gfx_power_up_by_imu +ffffffff8237a270 T is_support_sw_smu +ffffffff8237a2b0 T is_support_cclk_dpm +ffffffff8237a310 T smu_allow_xgmi_power_down +ffffffff8237a3d0 T smu_write_watermarks_table +ffffffff8237a440 T smu_set_ac_dc +ffffffff8237a540 t smu_early_init +ffffffff8237a7f0 t smu_late_init +ffffffff8237ab90 t smu_sw_init +ffffffff8237b260 t smu_sw_fini +ffffffff8237b4b0 t smu_hw_init +ffffffff8237b8d0 t smu_hw_fini +ffffffff8237b9d0 t smu_late_fini +ffffffff8237b9f0 t smu_suspend +ffffffff8237bac0 t smu_resume +ffffffff8237bd20 t smu_set_clockgating_state +ffffffff8237bd50 t smu_set_powergating_state +ffffffff8237bd80 T smu_get_power_limit +ffffffff8237bec0 T smu_mode1_reset_is_support +ffffffff8237bf10 T smu_mode2_reset_is_support +ffffffff8237bf60 T smu_mode1_reset +ffffffff8237bfb0 T smu_handle_passthrough_sbr +ffffffff8237c000 T smu_get_ecc_info +ffffffff8237c050 T smu_wait_for_event +ffffffff8237c0a0 T smu_stb_collect_info +ffffffff8237c100 T amdgpu_smu_stb_debug_fs_init +ffffffff8237c130 T smu_send_hbm_bad_pages_num +ffffffff8237c180 T smu_send_hbm_bad_channel_flag +ffffffff8237c1d0 t smu_set_fan_control_mode +ffffffff8237c290 t smu_get_fan_control_mode +ffffffff8237c310 t smu_set_fan_speed_pwm +ffffffff8237c3c0 t smu_get_fan_speed_pwm +ffffffff8237c420 t smu_force_ppclk_levels +ffffffff8237c4e0 t smu_print_ppclk_levels +ffffffff8237c550 t smu_emit_ppclk_levels +ffffffff8237c5c0 t smu_force_performance_level +ffffffff8237c860 t smu_read_sensor +ffffffff8237caa0 t smu_get_apu_thermal_limit +ffffffff8237caf0 t smu_set_apu_thermal_limit +ffffffff8237cb40 t smu_get_performance_level +ffffffff8237cbb0 t smu_get_current_power_state +ffffffff8237cc10 t smu_get_fan_speed_rpm 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smu_get_baco_capability +ffffffff8237dd40 t smu_baco_set_state +ffffffff8237de20 t smu_sys_get_pp_feature_mask +ffffffff8237de90 t smu_sys_set_pp_feature_mask +ffffffff8237df00 t smu_mode2_reset +ffffffff8237dfa0 t smu_enable_gfx_features +ffffffff8237e040 t smu_set_df_cstate +ffffffff8237e0f0 t smu_set_xgmi_pstate +ffffffff8237e1a0 t smu_sys_get_gpu_metrics +ffffffff8237e200 t smu_set_watermarks_for_clock_ranges +ffffffff8237e280 t smu_display_disable_memory_clock_switch +ffffffff8237e2e0 t smu_get_max_sustainable_clocks_by_dc +ffffffff8237e340 t smu_get_uclk_dpm_states +ffffffff8237e3a0 t smu_get_dpm_clock_table +ffffffff8237e400 t smu_get_prv_buffer_details +ffffffff8237e470 t smu_set_user_clk_dependencies +ffffffff8237e4f0 t smu_adjust_power_state_dynamic +ffffffff8237e740 t smu_apply_default_config_table_settings +ffffffff8237e7f0 t smu_restore_dpm_user_profile +ffffffff8237ec10 t smu_throttling_logging_work_fn +ffffffff8237ec60 t smu_interrupt_work_fn +ffffffff8237ecb0 t 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cyan_skillfish_set_ppt_funcs +ffffffff82384030 t cyan_skillfish_print_clk_levels +ffffffff82384150 t cyan_skillfish_od_edit_dpm_table +ffffffff82384430 t cyan_skillfish_read_sensor +ffffffff82384610 t cyan_skillfish_is_dpm_running +ffffffff823846b0 t cyan_skillfish_init_smc_tables +ffffffff82384790 t cyan_skillfish_get_enabled_mask +ffffffff823847d0 t cyan_skillfish_get_dpm_ultimate_freq +ffffffff82384890 t cyan_skillfish_get_gpu_metrics +ffffffff82384b30 t cyan_skillfish_get_smu_metrics_data +ffffffff82385000 T navi10_set_ppt_funcs +ffffffff82385050 t navi10_run_btc +ffffffff823850d0 t navi10_get_allowed_feature_mask +ffffffff823853a0 t navi10_set_default_dpm_table +ffffffff82385810 t navi10_populate_umd_state_clk +ffffffff823859d0 t navi10_print_clk_levels +ffffffff82385b60 t navi10_emit_clk_levels +ffffffff82385d80 t navi10_force_clk_levels +ffffffff82385eb0 t navi10_od_edit_dpm_table +ffffffff82386460 t navi10_get_clock_by_type_with_latency +ffffffff82386560 t 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sienna_cichlid_od_edit_dpm_table +ffffffff8238b270 t sienna_cichlid_restore_user_od_settings +ffffffff8238b300 t sienna_cichlid_get_power_profile_mode +ffffffff8238b560 t sienna_cichlid_set_power_profile_mode +ffffffff8238b830 t sienna_cichlid_dpm_set_vcn_enable +ffffffff8238b8f0 t sienna_cichlid_dpm_set_jpeg_enable +ffffffff8238b970 t sienna_cichlid_read_sensor +ffffffff8238c170 t sienna_cichlid_pre_display_config_changed +ffffffff8238c1a0 t sienna_cichlid_display_config_changed +ffffffff8238c200 t sienna_cichlid_notify_smc_display_config +ffffffff8238c380 t sienna_cichlid_is_dpm_running +ffffffff8238c3d0 t sienna_cichlid_get_fan_speed_rpm +ffffffff8238c4e0 t sienna_cichlid_set_watermarks_table +ffffffff8238c670 t sienna_cichlid_get_thermal_temperature_range +ffffffff8238c750 t sienna_cichlid_get_uclk_dpm_states +ffffffff8238c860 t sienna_cichlid_set_default_od_settings +ffffffff8238ca10 t sienna_cichlid_display_disable_memory_clock_switch +ffffffff8238ca90 t sienna_cichlid_dump_pptable +ffffffff8238cac0 t sienna_cichlid_get_power_limit +ffffffff8238cb90 t sienna_cichlid_update_pcie_parameters +ffffffff8238ccc0 t sienna_cichlid_i2c_control_init +ffffffff8238cdf0 t sienna_cichlid_i2c_control_fini +ffffffff8238ce30 t sienna_cichlid_get_unique_id +ffffffff8238cf80 t sienna_cichlid_init_smc_tables +ffffffff8238d2a0 t sienna_cichlid_set_mp1_state +ffffffff8238d2e0 t sienna_cichlid_setup_pptable +ffffffff8238d720 t sienna_cichlid_system_features_control +ffffffff8238d7b0 t sienna_cichlid_baco_enter +ffffffff8238d800 t sienna_cichlid_baco_exit +ffffffff8238d900 t sienna_cichlid_is_mode1_reset_supported +ffffffff8238d980 t sienna_cichlid_is_mode2_reset_supported +ffffffff8238d9b0 t sienna_cichlid_mode2_reset +ffffffff8238daf0 t sienna_cichlid_get_dpm_ultimate_freq +ffffffff8238db10 t sienna_cichlid_get_gpu_metrics +ffffffff8238e090 t sienna_cichlid_enable_mgpu_fan_boost +ffffffff8238e0e0 t sienna_cichlid_get_fan_parameters +ffffffff8238e120 t sienna_cichlid_gpo_control +ffffffff8238e1d0 t sienna_cichlid_get_ecc_info +ffffffff8238e2c0 t sienna_cichlid_stb_get_data_direct +ffffffff8238e360 t sienna_cichlid_get_default_config_table_settings +ffffffff8238e3d0 t sienna_cichlid_set_config_table +ffffffff8238e4a0 t sienna_cichlid_get_throttler_status_locked +ffffffff8238e600 t sienna_cichlid_get_smartshift_power_percentage +ffffffff8238e730 t sienna_cichlid_i2c_xfer +ffffffff8238e9d0 t sienna_cichlid_i2c_func +ffffffff8238f000 T smu_v11_0_init_microcode +ffffffff8238f140 T smu_v11_0_fini_microcode +ffffffff8238f190 T smu_v11_0_load_microcode +ffffffff8238f2d0 T smu_v11_0_check_fw_status +ffffffff8238f320 T smu_v11_0_check_fw_version +ffffffff8238f490 T smu_v11_0_setup_pptable +ffffffff8238f5b0 T smu_v11_0_init_smc_tables +ffffffff8238f710 T smu_v11_0_fini_smc_tables +ffffffff8238f940 T smu_v11_0_init_power +ffffffff8238f9d0 T smu_v11_0_fini_power +ffffffff8238fa30 T smu_v11_0_get_vbios_bootup_values +ffffffff8238fd90 T smu_v11_0_notify_memory_pool_location +ffffffff8238fe80 T smu_v11_0_set_min_deep_sleep_dcefclk +ffffffff8238ff00 T smu_v11_0_set_driver_table_location +ffffffff8238ff70 T smu_v11_0_set_tool_table_location +ffffffff8238ffe0 T smu_v11_0_init_display_count +ffffffff82390040 T smu_v11_0_set_allowed_mask +ffffffff82390110 T smu_v11_0_system_features_control +ffffffff82390130 T smu_v11_0_notify_display_change +ffffffff823901a0 T smu_v11_0_init_max_sustainable_clocks +ffffffff82390400 t smu_v11_0_get_max_sustainable_clock +ffffffff82390520 T smu_v11_0_get_current_power_limit +ffffffff823905f0 T smu_v11_0_set_power_limit +ffffffff82390730 T smu_v11_0_interrupt_work +ffffffff823907b0 T smu_v11_0_enable_thermal_alert +ffffffff82390850 T smu_v11_0_disable_thermal_alert +ffffffff82390870 T smu_v11_0_get_gfx_vdd +ffffffff82390930 T smu_v11_0_display_clock_voltage_request +ffffffff82390a80 T smu_v11_0_set_hard_freq_limited_range +ffffffff82390b60 T smu_v11_0_gfx_off_control +ffffffff82390bd0 T smu_v11_0_get_fan_control_mode +ffffffff82390c20 T smu_v11_0_set_fan_speed_pwm +ffffffff82390dd0 t smu_v11_0_set_fan_static_mode +ffffffff82390f90 T smu_v11_0_set_fan_speed_rpm +ffffffff823910d0 T smu_v11_0_get_fan_speed_pwm +ffffffff82391210 T smu_v11_0_get_fan_speed_rpm +ffffffff82391310 T smu_v11_0_set_fan_control_mode +ffffffff823914b0 T smu_v11_0_set_xgmi_pstate +ffffffff823914d0 T smu_v11_0_register_irq_handler +ffffffff82391590 T smu_v11_0_get_max_sustainable_clocks_by_dc +ffffffff82391620 T smu_v11_0_set_azalia_d3_pme +ffffffff82391640 T smu_v11_0_baco_set_armd3_sequence +ffffffff82391660 T smu_v11_0_baco_is_support +ffffffff823916f0 T smu_v11_0_baco_get_state +ffffffff82391720 T smu_v11_0_baco_set_state +ffffffff823919d0 T smu_v11_0_baco_enter +ffffffff82391ac0 T smu_v11_0_baco_exit +ffffffff82391bf0 T smu_v11_0_mode1_reset +ffffffff82391c70 T smu_v11_0_handle_passthrough_sbr +ffffffff82391c90 T smu_v11_0_get_dpm_ultimate_freq +ffffffff82391dd0 T smu_v11_0_set_soft_freq_limited_range +ffffffff82391ea0 T smu_v11_0_set_performance_level +ffffffff823921f0 T smu_v11_0_set_power_source +ffffffff82392250 T smu_v11_0_get_dpm_freq_by_index +ffffffff82392300 T smu_v11_0_get_dpm_level_count +ffffffff823923a0 T smu_v11_0_set_single_dpm_table +ffffffff82392600 T smu_v11_0_get_dpm_level_range +ffffffff82392760 T smu_v11_0_get_current_pcie_link_width_level +ffffffff823927b0 T smu_v11_0_get_current_pcie_link_width +ffffffff82392810 T smu_v11_0_get_current_pcie_link_speed_level +ffffffff82392860 T smu_v11_0_get_current_pcie_link_speed +ffffffff823928c0 T smu_v11_0_gfx_ulv_control +ffffffff82392930 T smu_v11_0_deep_sleep_control +ffffffff82392ae0 T smu_v11_0_restore_user_od_settings +ffffffff82392b70 T smu_v11_0_set_smu_mailbox_registers +ffffffff82392be0 t smu_v11_0_set_irq_state +ffffffff82393190 t smu_v11_0_irq_process +ffffffff82394000 T vangogh_set_ppt_funcs +ffffffff82394040 t vangogh_set_default_dpm_tables +ffffffff82394070 t vangogh_common_print_clk_levels +ffffffff823944e0 t vangogh_force_clk_levels +ffffffff82394710 t vangogh_od_edit_dpm_table +ffffffff82394c40 t vangogh_get_power_profile_mode +ffffffff82394d40 t vangogh_set_power_profile_mode +ffffffff82394e60 t vangogh_dpm_set_vcn_enable +ffffffff82394eb0 t vangogh_dpm_set_jpeg_enable +ffffffff82394f00 t vangogh_read_sensor +ffffffff82395530 t vangogh_get_apu_thermal_limit +ffffffff82395550 t vangogh_set_apu_thermal_limit +ffffffff82395570 t vangogh_is_dpm_running +ffffffff823955d0 t vangogh_set_watermarks_table +ffffffff82395750 t vangogh_set_performance_level +ffffffff82395f60 t vangogh_get_power_limit +ffffffff823960c0 t vangogh_get_ppt_limit +ffffffff82396130 t vangogh_get_dpm_clock_table +ffffffff823962a0 t vangogh_init_smc_tables +ffffffff823964e0 t vangogh_system_features_control +ffffffff82396530 t vangogh_set_power_limit +ffffffff82396680 t vangogh_get_gfxoff_status +ffffffff82396710 t vangogh_get_gfxoff_entrycount +ffffffff82396780 t vangogh_set_gfxoff_residency +ffffffff823967f0 t vangogh_get_gfxoff_residency +ffffffff82396830 t vangogh_mode2_reset +ffffffff82396970 t vangogh_common_get_gpu_metrics +ffffffff823970f0 t vangogh_post_smu_init +ffffffff82397280 t vangogh_set_fine_grain_gfx_freq_parameters +ffffffff823972f0 t vangogh_force_dpm_limit_value +ffffffff82397420 t vangogh_get_dpm_ultimate_freq +ffffffff823977e0 t vangogh_set_soft_freq_limited_range +ffffffff82397960 t vangogh_get_gpu_metrics_v2_3 +ffffffff82398000 T renoir_set_ppt_funcs +ffffffff823980a0 t renoir_get_current_power_state +ffffffff82398120 t renoir_print_clk_levels +ffffffff82398530 t renoir_force_clk_levels +ffffffff82398750 t renoir_od_edit_dpm_table +ffffffff82398a30 t renoir_get_power_profile_mode +ffffffff82398b00 t renoir_set_power_profile_mode +ffffffff82398c20 t renoir_dpm_set_vcn_enable +ffffffff82398ca0 t renoir_dpm_set_jpeg_enable +ffffffff82398d20 t renoir_read_sensor +ffffffff823990d0 t renoir_is_dpm_running +ffffffff82399110 t renoir_set_watermarks_table +ffffffff823992b0 t renoir_set_performance_level +ffffffff823997d0 t renoir_get_dpm_clock_table +ffffffff82399b20 t renoir_init_smc_tables +ffffffff82399c90 t renoir_get_enabled_mask +ffffffff82399cd0 t renoir_get_dpm_ultimate_freq +ffffffff82399f70 t renoir_get_gpu_metrics +ffffffff8239a190 t renoir_gfx_state_change_set +ffffffff8239a1c0 t renoir_set_fine_grain_gfx_freq_parameters +ffffffff8239a260 t renoir_force_dpm_limit_value +ffffffff8239b000 T smu_v12_0_check_fw_status +ffffffff8239b050 T smu_v12_0_check_fw_version +ffffffff8239b0c0 T smu_v12_0_powergate_sdma +ffffffff8239b110 T smu_v12_0_set_gfx_cgpg +ffffffff8239b170 T smu_v12_0_get_gfxoff_status +ffffffff8239b200 T smu_v12_0_gfx_off_control +ffffffff8239b320 T smu_v12_0_fini_smc_tables +ffffffff8239b3d0 T smu_v12_0_set_default_dpm_tables +ffffffff8239b400 T smu_v12_0_mode2_reset +ffffffff8239b420 T smu_v12_0_set_soft_freq_limited_range +ffffffff8239b560 T smu_v12_0_set_driver_table_location +ffffffff8239b5d0 T smu_v12_0_get_vbios_bootup_values +ffffffff8239c000 T aldebaran_set_ppt_funcs +ffffffff8239c050 t aldebaran_get_allowed_feature_mask +ffffffff8239c0a0 t aldebaran_set_default_dpm_table +ffffffff8239c2a0 t aldebaran_populate_umd_state_clk +ffffffff8239c3a0 t aldebaran_print_clk_levels +ffffffff8239c560 t aldebaran_force_clk_levels +ffffffff8239c720 t aldebaran_usr_edit_dpm_table +ffffffff8239c940 t aldebaran_read_sensor +ffffffff8239cb60 t aldebaran_is_dpm_running +ffffffff8239cbb0 t aldebaran_get_thermal_temperature_range +ffffffff8239cc80 t aldebaran_set_performance_level +ffffffff8239cd30 t aldebaran_get_power_limit +ffffffff8239cec0 t aldebaran_set_df_cstate +ffffffff8239cf40 t aldebaran_allow_xgmi_power_down +ffffffff8239cfe0 t aldebaran_i2c_control_init +ffffffff8239d0a0 t aldebaran_i2c_control_fini +ffffffff8239d0e0 t aldebaran_get_unique_id +ffffffff8239d1c0 t aldebaran_init_smc_tables +ffffffff8239d380 t aldebaran_set_mp1_state +ffffffff8239d3c0 t aldebaran_setup_pptable +ffffffff8239d490 t aldebaran_system_features_control +ffffffff8239d5f0 t aldebaran_set_power_limit +ffffffff8239d680 t aldebaran_is_baco_supported +ffffffff8239d6b0 t aldebaran_is_mode1_reset_supported +ffffffff8239d6e0 t aldebaran_is_mode2_reset_supported +ffffffff8239d710 t aldebaran_mode1_reset +ffffffff8239d7f0 t aldebaran_mode2_reset +ffffffff8239db10 t aldebaran_set_soft_freq_limited_range +ffffffff8239dd10 t aldebaran_log_thermal_throttling_event +ffffffff8239e020 t aldebaran_get_gpu_metrics +ffffffff8239e2a0 t aldebaran_smu_handle_passthrough_sbr +ffffffff8239e2c0 t aldebaran_smu_send_hbm_bad_page_num +ffffffff8239e340 t aldebaran_get_ecc_info +ffffffff8239e4a0 t aldebaran_send_hbm_bad_channel_flag +ffffffff8239e570 t aldebaran_get_current_clk_freq_by_table +ffffffff8239e6b0 t aldebaran_get_smu_metrics_data +ffffffff8239e920 t aldebaran_upload_dpm_level +ffffffff8239ea10 t aldebaran_i2c_xfer +ffffffff8239ecb0 t aldebaran_i2c_func +ffffffff8239f000 T smu_v13_0_init_microcode +ffffffff8239f120 T smu_v13_0_fini_microcode +ffffffff8239f170 T smu_v13_0_load_microcode +ffffffff8239f1a0 T smu_v13_0_init_pptable_microcode +ffffffff8239f350 T smu_v13_0_get_pptable_from_firmware +ffffffff8239f470 T smu_v13_0_check_fw_status +ffffffff8239f4e0 T smu_v13_0_check_fw_version +ffffffff8239f560 T smu_v13_0_setup_pptable +ffffffff8239f6f0 T smu_v13_0_init_smc_tables +ffffffff8239f870 T smu_v13_0_fini_smc_tables +ffffffff8239fa80 T smu_v13_0_init_power +ffffffff8239fb00 T smu_v13_0_fini_power +ffffffff8239fb80 T smu_v13_0_get_vbios_bootup_values +ffffffff8239fe20 T smu_v13_0_notify_memory_pool_location +ffffffff8239fee0 T smu_v13_0_set_min_deep_sleep_dcefclk +ffffffff8239ff60 T smu_v13_0_set_driver_table_location +ffffffff8239ffd0 T smu_v13_0_set_tool_table_location +ffffffff823a0040 T smu_v13_0_init_display_count +ffffffff823a0080 T smu_v13_0_set_allowed_mask +ffffffff823a0150 T smu_v13_0_gfx_off_control +ffffffff823a01d0 T smu_v13_0_system_features_control +ffffffff823a01f0 T smu_v13_0_notify_display_change +ffffffff823a0250 T smu_v13_0_init_max_sustainable_clocks +ffffffff823a04b0 t smu_v13_0_get_max_sustainable_clock +ffffffff823a05d0 T smu_v13_0_get_current_power_limit +ffffffff823a06a0 T smu_v13_0_set_power_limit +ffffffff823a07b0 T smu_v13_0_enable_thermal_alert +ffffffff823a0840 T smu_v13_0_disable_thermal_alert +ffffffff823a0880 T smu_v13_0_get_gfx_vdd +ffffffff823a0940 T smu_v13_0_display_clock_voltage_request +ffffffff823a0a90 T smu_v13_0_set_hard_freq_limited_range +ffffffff823a0b70 T smu_v13_0_get_fan_control_mode +ffffffff823a0bc0 T smu_v13_0_set_fan_speed_pwm +ffffffff823a0de0 t smu_v13_0_set_fan_static_mode +ffffffff823a0fb0 T smu_v13_0_set_fan_control_mode +ffffffff823a1110 T smu_v13_0_set_fan_speed_rpm +ffffffff823a12c0 T smu_v13_0_set_xgmi_pstate +ffffffff823a12e0 T smu_v13_0_register_irq_handler +ffffffff823a13b0 T smu_v13_0_get_max_sustainable_clocks_by_dc +ffffffff823a1440 T smu_v13_0_set_azalia_d3_pme +ffffffff823a1460 T smu_v13_0_wait_for_event +ffffffff823a14b0 T smu_v13_0_get_dpm_ultimate_freq +ffffffff823a1610 T smu_v13_0_set_soft_freq_limited_range +ffffffff823a16e0 T smu_v13_0_set_performance_level +ffffffff823a1e40 T smu_v13_0_set_power_source +ffffffff823a1ea0 T smu_v13_0_get_dpm_freq_by_index +ffffffff823a1f50 T smu_v13_0_set_single_dpm_table +ffffffff823a2240 T smu_v13_0_get_current_pcie_link_width_level +ffffffff823a2290 T smu_v13_0_get_current_pcie_link_width +ffffffff823a22f0 T smu_v13_0_get_current_pcie_link_speed_level +ffffffff823a2340 T smu_v13_0_get_current_pcie_link_speed +ffffffff823a2390 T smu_v13_0_set_vcn_enable +ffffffff823a2450 T smu_v13_0_set_jpeg_enable +ffffffff823a2470 T smu_v13_0_run_btc +ffffffff823a24f0 T smu_v13_0_gpo_control +ffffffff823a2580 T smu_v13_0_deep_sleep_control +ffffffff823a27e0 T smu_v13_0_gfx_ulv_control +ffffffff823a2850 T smu_v13_0_baco_set_armd3_sequence +ffffffff823a28c0 T smu_v13_0_baco_is_support +ffffffff823a2950 T smu_v13_0_baco_get_state +ffffffff823a2980 T smu_v13_0_baco_set_state +ffffffff823a2a50 T smu_v13_0_baco_enter +ffffffff823a2b70 T smu_v13_0_baco_exit +ffffffff823a2c10 T smu_v13_0_set_gfx_power_up_by_imu +ffffffff823a2c50 T smu_v13_0_od_edit_dpm_table +ffffffff823a2f00 T smu_v13_0_set_default_dpm_tables +ffffffff823a2f30 T smu_v13_0_set_smu_mailbox_registers +ffffffff823a2fa0 T smu_v13_0_mode1_reset +ffffffff823a3020 T smu_v13_0_update_pcie_parameters +ffffffff823a3290 t smu_v13_0_set_irq_state +ffffffff823a3840 t smu_v13_0_irq_process +ffffffff823a4000 T smu_v13_0_0_set_ppt_funcs +ffffffff823a40f0 t smu_v13_0_0_get_allowed_feature_mask +ffffffff823a4230 t smu_v13_0_0_set_default_dpm_table +ffffffff823a4650 t smu_v13_0_0_populate_umd_state_clk +ffffffff823a4790 t smu_v13_0_0_print_clk_levels +ffffffff823a48a0 t smu_v13_0_0_force_clk_levels +ffffffff823a4a20 t smu_v13_0_0_od_edit_dpm_table +ffffffff823a4ef0 t smu_v13_0_0_restore_user_od_settings +ffffffff823a4fb0 t smu_v13_0_0_get_power_profile_mode +ffffffff823a50b0 t smu_v13_0_0_set_power_profile_mode +ffffffff823a5300 t smu_v13_0_0_read_sensor +ffffffff823a5520 t smu_v13_0_0_is_dpm_running +ffffffff823a5570 t smu_v13_0_0_get_fan_speed_pwm +ffffffff823a5650 t smu_v13_0_0_get_fan_speed_rpm +ffffffff823a56c0 t smu_v13_0_0_get_thermal_temperature_range +ffffffff823a57c0 t smu_v13_0_0_set_default_od_settings +ffffffff823a58f0 t smu_v13_0_0_dump_pptable +ffffffff823a5920 t smu_v13_0_0_get_power_limit +ffffffff823a5a00 t smu_v13_0_0_set_df_cstate +ffffffff823a5a20 t smu_v13_0_0_i2c_control_init +ffffffff823a5b50 t smu_v13_0_0_i2c_control_fini +ffffffff823a5b90 t smu_v13_0_0_get_unique_id +ffffffff823a5c30 t smu_v13_0_0_init_smc_tables +ffffffff823a5e80 t smu_v13_0_0_set_mp1_state +ffffffff823a5ec0 t smu_v13_0_0_setup_pptable +ffffffff823a6020 t smu_v13_0_0_system_features_control +ffffffff823a6030 t smu_v13_0_0_baco_enter +ffffffff823a6090 t smu_v13_0_0_baco_exit +ffffffff823a60f0 t smu_v13_0_0_is_mode1_reset_supported +ffffffff823a6150 t smu_v13_0_0_mode1_reset +ffffffff823a6270 t smu_v13_0_0_mode2_reset +ffffffff823a62c0 t smu_v13_0_0_enable_gfx_features +ffffffff823a6310 t smu_v13_0_0_get_dpm_ultimate_freq +ffffffff823a6430 t smu_v13_0_0_get_gpu_metrics +ffffffff823a6870 t smu_v13_0_0_enable_mgpu_fan_boost +ffffffff823a68c0 t smu_v13_0_0_smu_send_bad_mem_page_num +ffffffff823a6940 t smu_v13_0_0_get_ecc_info +ffffffff823a6a40 t smu_v13_0_0_send_bad_mem_channel_flag +ffffffff823a6ac0 t smu_v13_0_0_i2c_xfer +ffffffff823a6d60 t smu_v13_0_0_i2c_func +ffffffff823a7000 T smu_v13_0_4_set_ppt_funcs +ffffffff823a70c0 t smu_v13_0_4_print_clk_levels +ffffffff823a7130 t smu_v13_0_4_force_clk_levels +ffffffff823a73f0 t smu_v13_0_4_read_sensor +ffffffff823a76d0 t smu_v13_0_4_is_dpm_running +ffffffff823a7720 t smu_v13_0_4_set_watermarks_table +ffffffff823a78a0 t smu_v13_0_4_set_performance_level +ffffffff823a8450 t smu_v13_0_4_init_smc_tables +ffffffff823a85c0 t smu_v13_0_4_fini_smc_tables +ffffffff823a8670 t smu_v13_0_4_system_features_control +ffffffff823a86c0 t smu_v13_0_4_mode2_reset +ffffffff823a86e0 t smu_v13_0_4_get_dpm_ultimate_freq +ffffffff823a8b00 t smu_v13_0_4_get_gpu_metrics +ffffffff823a8cd0 t smu_v13_0_4_set_fine_grain_gfx_freq_parameters +ffffffff823a8d30 t smu_v13_0_4_get_current_clk_freq +ffffffff823a9000 T smu_v13_0_5_set_ppt_funcs +ffffffff823a90a0 t smu_v13_0_5_set_default_dpm_tables +ffffffff823a90d0 t smu_v13_0_5_print_clk_levels +ffffffff823a9160 t smu_v13_0_5_force_clk_levels +ffffffff823a92d0 t smu_v13_0_5_od_edit_dpm_table +ffffffff823a9580 t smu_v13_0_5_dpm_set_vcn_enable +ffffffff823a95a0 t smu_v13_0_5_dpm_set_jpeg_enable +ffffffff823a95c0 t smu_v13_0_5_read_sensor +ffffffff823a97e0 t smu_v13_0_5_is_dpm_running +ffffffff823a9830 t smu_v13_0_5_set_watermarks_table +ffffffff823a99b0 t smu_v13_0_5_set_performance_level +ffffffff823a9f50 t smu_v13_0_5_init_smc_tables +ffffffff823aa0c0 t smu_v13_0_5_fini_smc_tables +ffffffff823aa170 t smu_v13_0_5_system_features_control +ffffffff823aa1c0 t smu_v13_0_5_mode2_reset +ffffffff823aa240 t smu_v13_0_5_get_dpm_ultimate_freq +ffffffff823aa680 t smu_v13_0_5_get_gpu_metrics +ffffffff823aa7d0 t smu_v13_0_5_set_fine_grain_gfx_freq_parameters +ffffffff823ab000 T smu_v13_0_6_set_ppt_funcs +ffffffff823ab050 t smu_v13_0_6_get_allowed_feature_mask +ffffffff823ab0a0 t smu_v13_0_6_set_default_dpm_table +ffffffff823ab5a0 t smu_v13_0_6_populate_umd_state_clk +ffffffff823ab6a0 t smu_v13_0_6_print_clk_levels +ffffffff823aba10 t smu_v13_0_6_force_clk_levels +ffffffff823abbd0 t smu_v13_0_6_usr_edit_dpm_table +ffffffff823abdf0 t smu_v13_0_6_read_sensor +ffffffff823ac380 t smu_v13_0_6_is_dpm_running +ffffffff823ac400 t smu_v13_0_6_get_thermal_temperature_range +ffffffff823ac550 t smu_v13_0_6_set_performance_level +ffffffff823ac660 t smu_v13_0_6_get_power_limit +ffffffff823ac730 t smu_v13_0_6_set_df_cstate +ffffffff823ac750 t smu_v13_0_6_allow_xgmi_power_down +ffffffff823ac770 t smu_v13_0_6_i2c_control_init +ffffffff823ac8a0 t smu_v13_0_6_i2c_control_fini +ffffffff823ac8e0 t smu_v13_0_6_get_unique_id +ffffffff823ac960 t smu_v13_0_6_init_smc_tables +ffffffff823acaf0 t smu_v13_0_6_check_fw_status +ffffffff823acb40 t smu_v13_0_6_setup_pptable +ffffffff823acb70 t smu_v13_0_6_system_features_control +ffffffff823acc10 t smu_v13_0_6_get_enabled_mask +ffffffff823acc80 t smu_v13_0_6_set_power_limit +ffffffff823acca0 t smu_v13_0_6_register_irq_handler +ffffffff823acd00 t smu_v13_0_6_is_baco_supported +ffffffff823acd30 t smu_v13_0_6_is_mode1_reset_supported +ffffffff823acd60 t smu_v13_0_6_is_mode2_reset_supported +ffffffff823acd90 t smu_v13_0_6_mode1_reset +ffffffff823ace40 t smu_v13_0_6_mode2_reset +ffffffff823ad0f0 t smu_v13_0_6_get_dpm_ultimate_freq +ffffffff823ad300 t smu_v13_0_6_set_soft_freq_limited_range +ffffffff823ad530 t smu_v13_0_6_log_thermal_throttling_event +ffffffff823ad820 t smu_v13_0_6_get_gpu_metrics +ffffffff823adb70 t smu_v13_0_6_smu_send_hbm_bad_page_num +ffffffff823adbf0 t smu_v13_0_6_get_smu_metrics_data +ffffffff823ade80 t smu_v13_0_6_upload_dpm_level +ffffffff823adf80 t smu_v13_0_6_i2c_xfer +ffffffff823ae280 t smu_v13_0_6_i2c_func +ffffffff823ae2b0 t smu_v13_0_6_set_irq_state +ffffffff823ae540 t smu_v13_0_6_irq_process +ffffffff823af000 T smu_v13_0_7_set_ppt_funcs +ffffffff823af060 t smu_v13_0_7_get_allowed_feature_mask +ffffffff823af1d0 t smu_v13_0_7_set_default_dpm_table +ffffffff823af5f0 t smu_v13_0_7_populate_umd_state_clk +ffffffff823af730 t smu_v13_0_7_print_clk_levels +ffffffff823af840 t smu_v13_0_7_force_clk_levels +ffffffff823af9c0 t smu_v13_0_7_od_edit_dpm_table +ffffffff823afe90 t smu_v13_0_7_restore_user_od_settings +ffffffff823aff50 t smu_v13_0_7_get_power_profile_mode +ffffffff823b0090 t smu_v13_0_7_set_power_profile_mode +ffffffff823b02d0 t smu_v13_0_7_read_sensor +ffffffff823b04e0 t smu_v13_0_7_is_dpm_running +ffffffff823b0530 t smu_v13_0_7_get_fan_speed_pwm +ffffffff823b0610 t smu_v13_0_7_get_fan_speed_rpm +ffffffff823b0680 t smu_v13_0_7_get_thermal_temperature_range +ffffffff823b0780 t smu_v13_0_7_set_default_od_settings +ffffffff823b08b0 t smu_v13_0_7_dump_pptable +ffffffff823b08e0 t smu_v13_0_7_get_power_limit +ffffffff823b09c0 t smu_v13_0_7_set_df_cstate +ffffffff823b09e0 t smu_v13_0_7_init_smc_tables +ffffffff823b0bd0 t smu_v13_0_7_check_fw_status +ffffffff823b0c20 t smu_v13_0_7_set_mp1_state +ffffffff823b0c60 t smu_v13_0_7_setup_pptable +ffffffff823b0dc0 t smu_v13_0_7_baco_enter +ffffffff823b0e20 t smu_v13_0_7_baco_exit +ffffffff823b0e80 t smu_v13_0_7_is_mode1_reset_supported +ffffffff823b0ec0 t smu_v13_0_7_get_dpm_ultimate_freq +ffffffff823b0fe0 t smu_v13_0_7_get_gpu_metrics +ffffffff823b1410 t smu_v13_0_7_enable_mgpu_fan_boost +ffffffff823b2000 T yellow_carp_set_ppt_funcs +ffffffff823b2050 t yellow_carp_set_default_dpm_tables +ffffffff823b2080 t yellow_carp_print_clk_levels +ffffffff823b2100 t yellow_carp_force_clk_levels +ffffffff823b23c0 t yellow_carp_od_edit_dpm_table +ffffffff823b2670 t yellow_carp_dpm_set_vcn_enable +ffffffff823b2690 t yellow_carp_dpm_set_jpeg_enable +ffffffff823b26b0 t yellow_carp_read_sensor +ffffffff823b2a20 t yellow_carp_is_dpm_running +ffffffff823b2a70 t yellow_carp_set_watermarks_table +ffffffff823b2bf0 t yellow_carp_set_performance_level +ffffffff823b3680 t yellow_carp_init_smc_tables +ffffffff823b37f0 t yellow_carp_fini_smc_tables +ffffffff823b38a0 t yellow_carp_system_features_control +ffffffff823b38f0 t yellow_carp_get_gfxoff_status +ffffffff823b3980 t yellow_carp_mode2_reset +ffffffff823b3a00 t yellow_carp_get_dpm_ultimate_freq +ffffffff823b3e40 t yellow_carp_get_gpu_metrics +ffffffff823b3ff0 t yellow_carp_post_smu_init +ffffffff823b4070 t yellow_carp_set_fine_grain_gfx_freq_parameters +ffffffff823b40d0 t yellow_carp_get_current_clk_freq +ffffffff823b41d0 t yellow_carp_get_dpm_profile_freq +ffffffff823b5000 T smu_cmn_send_msg_without_waiting +ffffffff823b5170 T smu_cmn_wait_for_response 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smu_cmn_get_metrics_table +ffffffff823b6870 T smu_cmn_get_combo_pptable +ffffffff823b6940 T smu_cmn_init_soft_gpu_metrics +ffffffff823b6a30 T smu_cmn_set_mp1_state +ffffffff823b6ad0 T smu_cmn_is_audio_func_enabled +ffffffff823b7000 T pci_mcfg_init +ffffffff823b7050 T pci_lookup_segment +ffffffff823b70b0 T pci_attach_hook +ffffffff823b70e0 T pci_bus_maxdevs +ffffffff823b7110 T pci_make_tag +ffffffff823b7180 T pci_decompose_tag +ffffffff823b71e0 T pci_conf_size +ffffffff823b7240 T pci_mcfg_map_bus +ffffffff823b72c0 T pci_conf_read +ffffffff823b7410 T pci_conf_write +ffffffff823b7550 T pci_msix_table_map +ffffffff823b7680 T pci_msix_table_unmap +ffffffff823b7720 T msi_hwmask +ffffffff823b7750 T msi_hwunmask +ffffffff823b7780 T msi_addroute +ffffffff823b7890 T msi_delroute +ffffffff823b7910 T msi_allocidtvec +ffffffff823b7a60 T pci_intr_enable_msivec +ffffffff823b7b40 T pci_intr_map_msi +ffffffff823b7bf0 T pci_intr_map_msivec +ffffffff823b7ca0 T msix_hwmask +ffffffff823b7cd0 T msix_hwunmask +ffffffff823b7d00 T msix_addroute +ffffffff823b7ef0 T msix_delroute +ffffffff823b8050 T pci_intr_map_msix +ffffffff823b8120 T pci_intr_map +ffffffff823b8350 T pci_intr_string +ffffffff823b8430 T pci_intr_establish +ffffffff823b8480 T pci_intr_establish_cpu +ffffffff823b85d0 T pci_intr_disestablish +ffffffff823b85f0 T pci_init_extents +ffffffff823b87d0 T pci_probe_device_hook +ffffffff823b8810 T pci_dev_postattach +ffffffff823b8820 T pci_min_powerstate +ffffffff823b8830 T pci_set_powerstate_md +ffffffff823b9000 T pciide_machdep_compat_intr_establish +ffffffff823b9060 T pciide_machdep_compat_intr_disestablish +ffffffff823ba000 T vga_post_init +ffffffff823ba310 t vm86_emu_inb +ffffffff823ba360 t vm86_emu_inw +ffffffff823ba3a0 t vm86_emu_inl +ffffffff823ba3e0 t vm86_emu_outb +ffffffff823ba430 t vm86_emu_outw +ffffffff823ba470 t vm86_emu_outl +ffffffff823ba4b0 T vga_post_call +ffffffff823ba520 T vga_post_free +ffffffff823ba590 T ddb_vgapost +ffffffff823bb000 T pchbmatch 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pcmcia_cis_read_1 +ffffffff823d90f0 T pcmcia_read_cis +ffffffff823d91e0 T pcmcia_scan_cis +ffffffff823dacd0 T pcmcia_parse_cis_tuple +ffffffff823dbe60 T pcmcia_print_cis +ffffffff823dd000 T pcmcia_check_cis_quirks +ffffffff823de000 T ep_pcmcia_match +ffffffff823de110 T ep_pcmcia_attach +ffffffff823de520 T ep_pcmcia_detach +ffffffff823de5c0 T ep_pcmcia_activate +ffffffff823de6a0 T ep_pcmcia_lookup +ffffffff823de7b0 T ep_pcmcia_enable1 +ffffffff823de860 T ep_pcmcia_get_enaddr +ffffffff823df000 T ne_pcmcia_match +ffffffff823df140 T ne_pcmcia_attach +ffffffff823df760 T ne_pcmcia_detach +ffffffff823df820 T ne_pcmcia_activate +ffffffff823df910 T ne_pcmcia_get_enaddr +ffffffff823dfaf0 T ne_pcmcia_dl10019_get_enaddr +ffffffff823dfd30 T ne_pcmcia_ax88190_set_iobase +ffffffff823e0000 T aic_pcmcia_match +ffffffff823e00b0 T aic_pcmcia_attach +ffffffff823e02b0 T aic_pcmcia_detach +ffffffff823e1000 T com_pcmcia_match +ffffffff823e1220 T com_pcmcia_attach +ffffffff823e1500 T com_pcmcia_detach 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pms_disable_synaptics +ffffffff824330d0 T pms_enable_alps +ffffffff824335f0 T pms_ioctl_alps +ffffffff824336a0 T pms_sync_alps +ffffffff82433750 T pms_proc_alps +ffffffff824339a0 T pms_enable_elantech_v1 +ffffffff82433bb0 T pms_ioctl_elantech +ffffffff82433c70 T pms_sync_elantech_v1 +ffffffff82433d50 T pms_proc_elantech_v1 +ffffffff82433ec0 T pms_enable_elantech_v2 +ffffffff82434060 T pms_sync_elantech_v2 +ffffffff82434150 T pms_proc_elantech_v2 +ffffffff824342c0 T pms_enable_elantech_v3 +ffffffff82434460 T pms_sync_elantech_v3 +ffffffff824344f0 T pms_proc_elantech_v3 +ffffffff824346e0 T pms_enable_elantech_v4 +ffffffff824348e0 T pms_sync_elantech_v4 +ffffffff824349b0 T pms_proc_elantech_v4 +ffffffff82434d00 T pms_enable_intelli +ffffffff82434ef0 T pms_cmd +ffffffff82434f60 T pms_spec_cmd +ffffffff824351f0 T pms_set_scaling +ffffffff82435280 T pms_set_resolution +ffffffff82435310 T pms_get_devid +ffffffff824353a0 T pms_get_status +ffffffff82435430 T pms_set_rate +ffffffff824354c0 T pms_reset +ffffffff82435550 T pms_dev_enable +ffffffff82435610 T pms_dev_disable +ffffffff824356d0 T pms_protocol_lookup +ffffffff824357d0 T pms_reset_detect +ffffffff82435850 T pms_reset_timo +ffffffff824358a0 T pms_reset_task +ffffffff82435960 T pms_change_state +ffffffff82435cf0 T pmsinput +ffffffff82435e90 T synaptics_set_mode +ffffffff82435f90 T synaptics_query +ffffffff82436080 T synaptics_get_hwinfo +ffffffff82436560 T synaptics_sec_proc +ffffffff82436630 T synaptics_knock +ffffffff82436890 T alps_sec_proc +ffffffff824369b0 T alps_get_hwinfo +ffffffff82436e20 T elantech_set_absolute_mode_v1 +ffffffff824370e0 T elantech_set_absolute_mode_v2 +ffffffff82437600 T elantech_ps2_cmd +ffffffff82437690 T elantech_set_absolute_mode_v3 +ffffffff82437b00 T elantech_set_absolute_mode_v4 +ffffffff82437d30 T elantech_get_hwinfo_v1 +ffffffff82437f30 T elantech_get_hwinfo_v2 +ffffffff82438240 T elantech_get_hwinfo_v3 +ffffffff82438450 T elantech_get_hwinfo_v4 +ffffffff824386c0 T elantech_knock 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T hidkbd_cngetc +ffffffff82440520 T hidkbd_hookup_bell +ffffffff82441000 T hidms_stylus_hid_parse +ffffffff82441320 T hidms_pad_buttons_hid_parse +ffffffff82441400 T hidms_wacom_setup +ffffffff82441710 T hidms_setup +ffffffff82441cb0 T hidms_attach +ffffffff82441e00 T hidms_detach +ffffffff82441e40 T hidms_input +ffffffff824420f0 T hidms_enable +ffffffff82442140 T hidms_ioctl +ffffffff82442310 T hidms_disable +ffffffff82443000 T hidmt_get_resolution +ffffffff82443110 T hidmt_setup +ffffffff824437b0 T hidmt_set_input_mode +ffffffff82443840 T hidmt_configure +ffffffff824438e0 T hidmt_attach +ffffffff824439f0 T hidmt_detach +ffffffff82443a30 T hidmt_input +ffffffff82443f10 T hidmt_enable +ffffffff82443f50 T hidmt_ioctl +ffffffff82444020 T hidmt_disable +ffffffff82445000 T hidcc_match +ffffffff824450e0 T hidcc_attach +ffffffff82445280 T hidcc_parse +ffffffff82445640 T hidcc_attach_wskbd +ffffffff824456f0 T hidcc_detach +ffffffff824457a0 T hidcc_intr +ffffffff82445ab0 T hidcc_intr_slice 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uaudio_copy_output +ffffffff82453ce0 T uaudio_underrun +ffffffff82453d00 T uaudio_set_blksz +ffffffff82453dc0 T uaudio_sign_expand +ffffffff82453e00 T uaudio_req +ffffffff82453e90 T uaudio_getnum +ffffffff82453fc0 T uaudio_getdesc +ffffffff82454040 T uaudio_unit_byid +ffffffff82454080 T uaudio_tname +ffffffff824541f0 T uaudio_clkname +ffffffff82454230 T uaudio_mkname +ffffffff82454350 T uaudio_feature_fixup +ffffffff82454490 T uaudio_ranges_init +ffffffff824544d0 T uaudio_ranges_add +ffffffff82454590 T uaudio_ranges_clear +ffffffff82454600 T uaudio_ranges_decode +ffffffff82454690 T uaudio_ranges_encode +ffffffff82454710 T uaudio_ranges_getrates +ffffffff82454810 T uaudio_rates_indexof +ffffffff824548a0 T uaudio_req_ranges +ffffffff82454ec0 T uaudio_alt_getrates +ffffffff82454fa0 T uaudio_clock_id +ffffffff82455020 T uaudio_getrates +ffffffff82455100 T uaudio_feature_addent +ffffffff824552c0 T uaudio_process_srcs +ffffffff824553a0 T uaudio_process_unit +ffffffff82455fa0 T uaudio_process_nch +ffffffff82456050 T uaudio_unit_getdesc +ffffffff82456110 T uaudio_setname_dsts +ffffffff824561c0 T uaudio_setname_srcs +ffffffff82456270 T uaudio_setname_middle +ffffffff82456330 T uaudio_mixer_nchan +ffffffff824563b0 T uaudio_mixer_skip +ffffffff82456420 T uaudio_mixer_byindex +ffffffff82456540 T uaudio_process_header +ffffffff824565f0 T uaudio_process_ac_ep +ffffffff824566d0 T uaudio_process_ac +ffffffff82456ff0 T uaudio_process_as_ep +ffffffff82457160 T uaudio_process_as_general +ffffffff82457270 T uaudio_process_as_format +ffffffff824577f0 T uaudio_process_as +ffffffff82457bd0 T uaudio_fixup_params +ffffffff82457d50 T uaudio_process_conf +ffffffff82457f50 T uaudio_xfer_alloc +ffffffff82457ff0 T uaudio_xfer_free +ffffffff82458070 T uaudio_stream_close +ffffffff82458210 T uaudio_stream_open +ffffffff82458940 T uaudio_adjspf +ffffffff82458a30 T uaudio_pdata_copy +ffffffff82458be0 T uaudio_pdata_calcsizes +ffffffff82458ce0 T uaudio_pdata_xfer +ffffffff82458de0 T uaudio_pdata_intr +ffffffff82459050 T uaudio_psync_xfer +ffffffff82459160 T uaudio_psync_intr +ffffffff82459280 T uaudio_rdata_xfer +ffffffff82459470 T uaudio_rdata_intr +ffffffff82459840 T uaudio_trigger +ffffffff82459a70 T uaudio_print +ffffffff82459c00 T uaudio_get_port_do +ffffffff82459f00 T uaudio_set_port_do +ffffffff8245a1d0 T uaudio_query_devinfo_do +ffffffff8245b000 T uvideo_match +ffffffff8245b0c0 T uvideo_attach +ffffffff8245b300 T uvideo_detach +ffffffff8245b400 T uvideo_open +ffffffff8245b4a0 T uvideo_close +ffffffff8245b630 T uvideo_querycap +ffffffff8245b740 T uvideo_enum_fmt +ffffffff8245b860 T uvideo_enum_fsizes +ffffffff8245b8e0 T uvideo_enum_fivals +ffffffff8245ba50 T uvideo_s_fmt +ffffffff8245bbf0 T uvideo_g_fmt +ffffffff8245bc60 T uvideo_s_parm +ffffffff8245bcd0 T uvideo_g_parm +ffffffff8245bd20 T uvideo_enum_input +ffffffff8245bd80 T uvideo_s_input +ffffffff8245bdb0 T uvideo_g_input +ffffffff8245bde0 T uvideo_reqbufs +ffffffff8245bf50 T uvideo_querybuf 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uvideo_vc_parse_desc_header +ffffffff8245e0c0 T uvideo_vc_parse_desc_pu +ffffffff8245e130 T uvideo_vc_get_ctrl +ffffffff8245e1b0 T uvideo_vc_set_ctrl +ffffffff8245e230 T uvideo_find_ctrl +ffffffff8245e300 T uvideo_has_ctrl +ffffffff8245e350 T uvideo_vs_parse_desc_input_header +ffffffff8245e3c0 T uvideo_vs_parse_desc_format +ffffffff8245e560 T uvideo_vs_parse_desc_frame +ffffffff8245e640 T uvideo_vs_parse_desc_alt +ffffffff8245e820 T uvideo_vs_parse_desc_format_mjpeg +ffffffff8245e900 T uvideo_vs_parse_desc_format_uncompressed +ffffffff8245eaa0 T uvideo_vs_parse_desc_frame_sub +ffffffff8245ebd0 T uvideo_vs_set_alt +ffffffff8245ed80 T uvideo_find_res +ffffffff8245ee70 T uvideo_vs_set_probe +ffffffff8245ef10 T uvideo_vs_get_probe +ffffffff8245efc0 T uvideo_vs_set_commit +ffffffff8245f060 T uvideo_vs_alloc_frame +ffffffff8245f130 T uvideo_vs_alloc_isoc +ffffffff8245f2c0 T uvideo_vs_alloc_bulk +ffffffff8245f380 T uvideo_vs_open +ffffffff8245f500 T uvideo_vs_init +ffffffff8245f680 T uvideo_vs_start_bulk +ffffffff8245f700 T uvideo_vs_start_bulk_thread +ffffffff8245f7b0 T uvideo_vs_start_isoc +ffffffff8245f9a0 T uvideo_vs_start_isoc_ixfer +ffffffff8245fa60 T uvideo_vs_cb +ffffffff8245fb90 T uvideo_mmap_queue +ffffffff8245fce0 T uvideo_read +ffffffff8245fd30 T uvideo_usb_control +ffffffff82460000 T utvfu_set_regs +ffffffff824600b0 T utvfu_max_frame_size +ffffffff824600f0 T utvfu_configure_for_norm +ffffffff82460180 T utvfu_select_input +ffffffff82460340 T utvfu_select_norm +ffffffff82460490 T utvfu_setup_capture +ffffffff82460550 T utvfu_chunk_to_vbuf +ffffffff82460610 T utvfu_image_chunk +ffffffff824607d0 T utvfu_mmap_queue +ffffffff82460900 T utvfu_read +ffffffff82460950 T utvfu_start_capture +ffffffff82460a80 T utvfu_audio_stop +ffffffff82460b70 T utvfu_audio_start +ffffffff82460d20 T utvfu_querycap +ffffffff82460e20 T utvfu_enum_input +ffffffff82460eb0 T utvfu_enum_fmt_vid_cap +ffffffff82460f10 T utvfu_enum_fsizes +ffffffff82460f80 T utvfu_g_fmt +ffffffff82460ff0 T utvfu_s_fmt +ffffffff82461030 T utvfu_g_std +ffffffff82461070 T utvfu_s_std +ffffffff824610b0 T utvfu_g_input +ffffffff824610e0 T utvfu_s_input +ffffffff824610f0 T utvfu_audio_decode +ffffffff82461260 T utvfu_audio_start_chip +ffffffff82461300 T utvfu_audio_stop_chip +ffffffff824613a0 T utvfu_match +ffffffff824614f0 T utvfu_attach +ffffffff82461620 T utvfu_detach +ffffffff82461700 T utvfu_open +ffffffff82461810 T utvfu_close +ffffffff82461850 T utvfu_s_parm +ffffffff82461890 T utvfu_g_parm +ffffffff82461910 T utvfu_reqbufs +ffffffff82461a80 T utvfu_querybuf +ffffffff82461ae0 T utvfu_qbuf +ffffffff82461b50 T utvfu_dqbuf +ffffffff82461c40 T utvfu_streamon +ffffffff82461c90 T utvfu_streamoff +ffffffff82461d00 T utvfu_queryctrl +ffffffff82461d30 T utvfu_mappage +ffffffff82461d80 T utvfu_get_bufsize +ffffffff82461dc0 T utvfu_start_read +ffffffff82461e20 T utvfu_audio_open +ffffffff82461f00 T utvfu_audio_close +ffffffff82461f80 T utvfu_audio_set_params +ffffffff82462020 T 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acpiprt_route_interrupt +ffffffff8259f000 T acpidmar_match +ffffffff8259f080 T acpidmar_attach +ffffffff8259f140 T acpidmar_activate +ffffffff8259f380 T dmar_bdf +ffffffff8259f400 T domain_map_check +ffffffff8259f580 T acpidmar_pci_attach +ffffffff8259f650 T dmar_ptmap +ffffffff8259f6d0 T domain_map_pthru +ffffffff8259f750 T domain_map_page_intel +ffffffff8259f8d0 T iommu_flush_cache +ffffffff8259f920 T iommu_alloc_page +ffffffff8259f9c0 T pte_lvl +ffffffff8259fae0 T domain_map_page_amd +ffffffff8259fbb0 T domain_unload_map +ffffffff8259fdc0 T dom_bdf +ffffffff8259fe90 T domain_load_map +ffffffff825a00c0 T iommu_enable_translation +ffffffff825a0340 T iommu_flush_tlb +ffffffff825a04c0 T iommu_flush_write_buffer +ffffffff825a0630 T iommu_set_rtaddr +ffffffff825a0760 T iommu_write_8 +ffffffff825a0790 T iommu_write_4 +ffffffff825a07c0 T iommu_read_4 +ffffffff825a07e0 T iommu_alloc_hwdte +ffffffff825a0930 T iommu_issue_qi +ffffffff825a0960 T iommu_flush_tlb_qi +ffffffff825a0990 T iommu_flush_ctx_qi +ffffffff825a09c0 T ivhd_invalidate_domain +ffffffff825a0a20 T iommu_read_8 +ffffffff825a0a40 T iommu_flush_ctx +ffffffff825a0b60 T iommu_enable_qi +ffffffff825a0c80 T iommu_showcfg +ffffffff825a0ea0 T iommu_init +ffffffff825a11e0 T acpidmar_intr_establish +ffffffff825a12f0 T acpidmar_intr +ffffffff825a1480 T acpidmar_match_devscope +ffffffff825a15c0 T domain_create +ffffffff825a1800 t dmar_dmamap_create +ffffffff825a1820 t dmar_dmamap_destroy +ffffffff825a1830 t dmar_dmamap_load +ffffffff825a18a0 t dmar_dmamap_load_mbuf +ffffffff825a1900 t dmar_dmamap_load_uio +ffffffff825a1960 t dmar_dmamap_load_raw +ffffffff825a19d0 t dmar_dmamap_unload +ffffffff825a1a00 t dmar_dmamap_sync +ffffffff825a1a20 t dmar_dmamem_alloc +ffffffff825a1a40 t dmar_dmamem_free +ffffffff825a1a60 t dmar_dmamem_map +ffffffff825a1a80 t dmar_dmamem_unmap +ffffffff825a1aa0 t dmar_dmamem_mmap +ffffffff825a1ac0 T domain_add_device +ffffffff825a1b40 T domain_remove_device +ffffffff825a1bf0 T domain_lookup +ffffffff825a1db0 T _iommu_map +ffffffff825a1e70 T _iommu_domain +ffffffff825a1ed0 T domain_map_device +ffffffff825a21d0 T ivhd_flush_devtab +ffffffff825a2230 T acpidmar_pci_hook +ffffffff825a23f0 T acpidmar_parse_devscope +ffffffff825a2510 T acpidmar_drhd +ffffffff825a26e0 T acpidmar_rmrr +ffffffff825a2970 T acpidmar_atsr +ffffffff825a2b10 T acpidmar_init +ffffffff825a2f60 T acpiivhd_intr +ffffffff825a3040 T ivhd_poll_events +ffffffff825a3100 T ivhd_intr_map +ffffffff825a31b0 T _dumppte +ffffffff825a32e0 T ivhd_showpage +ffffffff825a3420 T ivhd_show_event +ffffffff825a3cc0 T ivhd_showdte +ffffffff825a3da0 T ivhd_showcmd +ffffffff825a3e60 T _ivhd_issue_command +ffffffff825a3f40 T ivhd_issue_command +ffffffff825a4210 T ivhd_invalidate_iommu_all +ffffffff825a4300 T ivhd_invalidate_interrupt_table +ffffffff825a43f0 T ivhd_showreg +ffffffff825a4530 T ivhd_checkerr +ffffffff825a4770 T ivhd_iommu_init +ffffffff825a4c50 T acpiivrs_ivhd +ffffffff825a4cc0 T acpiivrs_init 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asmc_backlight +ffffffff825a8bc0 T asmc_init +ffffffff825a8dc0 T asmc_update +ffffffff825a8f60 T asmc_detach +ffffffff825a9110 t asmc_temp +ffffffff825a92a0 t asmc_fan +ffffffff825a9460 t asmc_light +ffffffff825aa000 T acpiasus_match +ffffffff825aa030 T acpiasus_attach +ffffffff825aa150 T acpiasus_activate +ffffffff825aa2e0 T acpiasus_init +ffffffff825aa3c0 T acpiasus_notify +ffffffff825ab000 T thinkpad_match +ffffffff825ab0b0 T thinkpad_attach +ffffffff825ab4c0 T thinkpad_activate +ffffffff825ab640 T thinkpad_sensor_attach +ffffffff825ab7b0 T thinkpad_get_temp +ffffffff825ab840 T thinkpad_sensor_refresh +ffffffff825ab9c0 T thinkpad_get_volume_mute +ffffffff825aba30 T thinkpad_attach_deferred +ffffffff825aba50 T thinkpad_enable_events +ffffffff825abc20 T thinkpad_get_kbd_backlight +ffffffff825abcb0 T thinkpad_set_kbd_backlight +ffffffff825abd80 T thinkpad_get_param +ffffffff825abde0 T thinkpad_set_param +ffffffff825abea0 T thinkpad_battery_setchargestart +ffffffff825abff0 T thinkpad_battery_setchargestop +ffffffff825ac140 T thinkpad_battery_setchargemode +ffffffff825ac710 T thinkpad_hotkey +ffffffff825acd40 T thinkpad_brightness_up +ffffffff825acee0 T thinkpad_brightness_down +ffffffff825ad090 T thinkpad_toggle_bluetooth +ffffffff825ad1b0 T thinkpad_volume_mute +ffffffff825ad260 T thinkpad_volume_down +ffffffff825ad310 T thinkpad_volume_up +ffffffff825ad3c0 T thinkpad_get_thinklight +ffffffff825ad410 T thinkpad_adaptive_change +ffffffff825ad530 T thinkpad_get_brightness +ffffffff825ad570 T thinkpad_toggle_wan +ffffffff825ad690 T thinkpad_cmos +ffffffff825ad740 T thinkpad_set_brightness +ffffffff825ad830 T thinkpad_set_thinklight +ffffffff825ad8f0 T thinkpad_battery_inhibit_charge +ffffffff825ada20 T thinkpad_battery_force_discharge +ffffffff825ae000 T toshiba_match +ffffffff825ae0a0 T toshiba_attach +ffffffff825ae180 T get_param_brightness +ffffffff825ae1e0 T acpitoshiba_get_param +ffffffff825ae240 T set_param_brightness +ffffffff825ae2d0 T toshiba_update_brightness +ffffffff825ae3d0 T acpitoshiba_set_param +ffffffff825ae470 T toshiba_set_brightness +ffffffff825ae590 T toshiba_enable_events +ffffffff825ae620 T toshiba_read_events +ffffffff825ae780 T toshiba_hotkey +ffffffff825ae9b0 T toshiba_get_brightness +ffffffff825aeb20 T toshiba_fn_key_brightness_up +ffffffff825aec70 T toshiba_fn_key_brightness_down +ffffffff825aedc0 T toshiba_fn_key_video_output +ffffffff825aef10 T toshiba_get_video_output +ffffffff825af080 T toshiba_set_video_output +ffffffff825b0000 T acpisony_match +ffffffff825b0070 T acpisony_attach +ffffffff825b00e0 T acpisony_activate +ffffffff825b0120 T acpisony_notify_setup +ffffffff825b0310 T acpisony_notify +ffffffff825b06b0 T acpisony_find_offset +ffffffff825b07c0 T acpisony_set_hotkey +ffffffff825b09b0 T acpisony_brightness_down +ffffffff825b0ac0 T acpisony_get_brightness +ffffffff825b0b40 T acpisony_set_brightness +ffffffff825b1000 T acpivideo_match +ffffffff825b1070 T acpivideo_attach +ffffffff825b11d0 T acpivideo_getpcibus +ffffffff825b1210 T acpivideo_notify +ffffffff825b1270 T acpivideo_set_policy +ffffffff825b1340 T acpi_foundvout +ffffffff825b1410 T acpivideo_print +ffffffff825b2000 T acpivout_match +ffffffff825b2070 T acpivout_attach +ffffffff825b21c0 T acpivout_notify +ffffffff825b2270 T acpivout_get_bcl +ffffffff825b2390 T acpivout_get_brightness +ffffffff825b2430 T acpivout_get_param +ffffffff825b24d0 T acpivout_set_param +ffffffff825b2630 T acpivout_select_brightness +ffffffff825b2700 T acpivout_find_brightness +ffffffff825b2790 T acpivout_set_brightness +ffffffff825b3000 T acpipwrres_match +ffffffff825b3070 T acpipwrres_attach +ffffffff825b32b0 T acpipwrres_foundcons +ffffffff825b3440 T acpipwrres_ref_incr +ffffffff825b34d0 T acpipwrres_hascons +ffffffff825b3520 T acpipwrres_ref_decr +ffffffff825b35b0 T acpipwrres_addcons +ffffffff825b4000 T aibs_match +ffffffff825b4030 T aibs_attach +ffffffff825b4140 T aibs_probe +ffffffff825b42a0 T aibs_attach_new +ffffffff825b43c0 T aibs_attach_sif +ffffffff825b4590 T aibs_notify +ffffffff825b4600 T aibs_add_sensor +ffffffff825b4850 T aibs_getpack +ffffffff825b48d0 T aibs_refresh +ffffffff825b4930 T aibs_refresh_r +ffffffff825b4a70 T aibs_getvalue +ffffffff825b4bc0 T aibs_find_cb +ffffffff825b5000 T aplgpio_match +ffffffff825b5060 T aplgpio_attach +ffffffff825b5310 T aplgpio_intr +ffffffff825b5460 T aplgpio_read_pin +ffffffff825b54b0 T aplgpio_write_pin +ffffffff825b5520 T aplgpio_intr_establish +ffffffff825b5640 T aplgpio_intr_enable +ffffffff825b56d0 T aplgpio_intr_disable +ffffffff825b6000 T bytgpio_match +ffffffff825b6060 T bytgpio_attach +ffffffff825b6320 T bytgpio_intr +ffffffff825b6450 T bytgpio_read_pin +ffffffff825b64b0 T bytgpio_write_pin +ffffffff825b6530 T bytgpio_intr_establish +ffffffff825b65a0 T bytgpio_intr_enable +ffffffff825b6690 T bytgpio_intr_disable +ffffffff825b7000 T chvgpio_match +ffffffff825b7060 T chvgpio_attach +ffffffff825b7300 T chvgpio_intr +ffffffff825b73d0 T chvgpio_read_pin +ffffffff825b7480 T chvgpio_write_pin +ffffffff825b7540 T chvgpio_intr_establish +ffffffff825b7710 T chvgpio_intr_enable +ffffffff825b77e0 T chvgpio_intr_disable +ffffffff825b78b0 T chvgpio_opreg_handler +ffffffff825b7930 T chvgpio_check_pin +ffffffff825b8000 T glkgpio_match +ffffffff825b8060 T glkgpio_attach +ffffffff825b8310 T glkgpio_intr +ffffffff825b8460 T glkgpio_read_pin +ffffffff825b84c0 T glkgpio_write_pin +ffffffff825b8530 T glkgpio_intr_establish +ffffffff825b8650 T glkgpio_intr_enable +ffffffff825b86e0 T glkgpio_intr_disable +ffffffff825b9000 T pchgpio_match +ffffffff825b9060 T pchgpio_attach +ffffffff825b9530 T pchgpio_activate +ffffffff825b95e0 T pchgpio_intr +ffffffff825b9800 T pchgpio_read_pin +ffffffff825b98f0 T pchgpio_write_pin +ffffffff825b9a00 T pchgpio_intr_establish +ffffffff825b9c20 T pchgpio_intr_enable +ffffffff825b9d50 T pchgpio_intr_disable +ffffffff825b9e80 T pchgpio_save +ffffffff825b9ef0 T pchgpio_restore +ffffffff825b9f60 T pchgpio_find_group +ffffffff825b9fe0 T pchgpio_intr_handle +ffffffff825ba0c0 T pchgpio_save_pin +ffffffff825ba280 T pchgpio_restore_pin +ffffffff825bb000 T tipmic_match +ffffffff825bb050 T tipmic_attach +ffffffff825bb250 T tipmic_write_1 +ffffffff825bb310 T tipmic_intr +ffffffff825bb470 T tipmic_get_lpat +ffffffff825bb580 T tipmic_read_pin +ffffffff825bb5b0 T tipmic_write_pin +ffffffff825bb5e0 T tipmic_thermal_opreg_handler +ffffffff825bbe60 T tipmic_power_opreg_handler +ffffffff825bc100 T tipmic_read_1 +ffffffff825bc1d0 T tipmic_raw_to_temp +ffffffff825bd000 T ccpmic_match +ffffffff825bd050 T ccpmic_attach +ffffffff825bd130 T ccpmic_get_lpat +ffffffff825bd240 T ccpmic_read_pin +ffffffff825bd3c0 T ccpmic_write_pin +ffffffff825bd520 T ccpmic_thermal_opreg_handler +ffffffff825bd770 T ccpmic_power_opreg_handler +ffffffff825bd960 T ccpmic_read_1 +ffffffff825bda30 T ccpmic_write_1 +ffffffff825bdaf0 T ccpmic_raw_to_temp +ffffffff825be000 T com_acpi_match +ffffffff825be120 T com_acpi_attach +ffffffff825be3a0 T com_acpi_is_designware +ffffffff825be400 T com_acpi_intr_designware +ffffffff825be430 T com_acpi_is_console +ffffffff825bf000 T sdhc_acpi_match +ffffffff825bf060 T sdhc_acpi_attach +ffffffff825bf370 T sdhc_acpi_parse_resources +ffffffff825bf420 T sdhc_acpi_card_detect_gpio +ffffffff825bf480 T sdhc_acpi_card_detect_intr +ffffffff825bf4c0 T sdhc_acpi_power_on +ffffffff825bf540 T sdhc_acpi_explore +ffffffff825bf570 T sdhc_acpi_card_detect_nonremovable +ffffffff825bf5a0 T sdhc_acpi_do_explore +ffffffff825c0000 T dwiic_acpi_match +ffffffff825c0050 T dwiic_acpi_attach +ffffffff825c0410 T dwiic_acpi_parse_crs +ffffffff825c0560 T dwiic_acpi_power +ffffffff825c0670 T dwiic_acpi_get_params +ffffffff825c07b0 T dwiic_i2c_intr_establish +ffffffff825c0830 T dwiic_i2c_intr_disestablish +ffffffff825c0850 T dwiic_i2c_intr_string +ffffffff825c08e0 T dwiic_acpi_acquire_bus +ffffffff825c0930 T dwiic_acpi_release_bus +ffffffff825c0960 T dwiic_acpi_bus_scan +ffffffff825c09a0 T dwiic_acpi_found_hid +ffffffff825c0d00 T dwiic_matchhids +ffffffff825c0d90 T dwiic_acpi_found_ihidev +ffffffff825c1000 T dwiic_acpi_found_iatp +ffffffff825c1160 T dwiic_acpi_found_ietp +ffffffff825c2000 T acpicbkbd_match +ffffffff825c2030 T acpicbkbd_attach +ffffffff825c20d0 T acpicbkbd_activate +ffffffff825c2120 T acpicbkbd_get_backlight +ffffffff825c21a0 T acpicbkbd_set_backlight +ffffffff825c2240 T acpicbkbd_write_backlight +ffffffff825c3000 T acpials_match +ffffffff825c3090 T acpials_attach +ffffffff825c3230 T acpials_read +ffffffff825c32b0 T acpials_addtask +ffffffff825c32f0 T acpials_notify +ffffffff825c3380 T acpials_update +ffffffff825c4000 T tpm_match +ffffffff825c4050 T tpm_attach +ffffffff825c4320 T tpm_activate +ffffffff825c4430 T tpm2_start_method +ffffffff825c44b0 T tpm_probe +ffffffff825c4560 T tpm_init_tis +ffffffff825c47d0 T tpm_init_crb +ffffffff825c4b10 T tpm_suspend +ffffffff825c4c00 T tpm_resume +ffffffff825c4c30 T tpm_write_tis +ffffffff825c4fc0 T tpm_read_tis +ffffffff825c5190 T tpm_write_crb +ffffffff825c5570 T tpm_read_crb +ffffffff825c5870 T tpm_request_locality_tis +ffffffff825c5960 T tpm_request_locality_crb +ffffffff825c5a60 T tpm_release_locality_crb +ffffffff825c5ab0 T tpm_release_locality_tis +ffffffff825c5b20 T tpm_getburst +ffffffff825c5bd0 T tpm_status +ffffffff825c5bf0 T tpm_waitfor +ffffffff825c5cd0 T tpm_waitfor_status +ffffffff825c6000 T acpihve_match +ffffffff825c60b0 T acpihve_attach +ffffffff825c7000 T acpisbs_match +ffffffff825c7030 T acpisbs_attach +ffffffff825c72b0 T acpisbs_activate +ffffffff825c7390 T acpisbs_read +ffffffff825c7450 T acpisbs_setup_sensors +ffffffff825c7550 T acpisbs_refresh_sensors +ffffffff825c76a0 T acpisbs_notify +ffffffff825c77e0 T acpi_smbus_read +ffffffff825c8000 T surface_match +ffffffff825c8060 T surface_attach +ffffffff825c80c0 T surface_hotkey +ffffffff825c9000 T ipmi_acpi_match +ffffffff825c9030 T ipmi_acpi_attach +ffffffff825c9260 T ipmi_acpi_parse_crs +ffffffff825ca000 T amdgpio_match +ffffffff825ca060 T amdgpio_attach +ffffffff825ca2a0 T amdgpio_activate +ffffffff825ca390 T amdgpio_intr +ffffffff825ca530 T amdgpio_read_pin +ffffffff825ca580 T amdgpio_write_pin +ffffffff825ca5f0 T amdgpio_intr_establish +ffffffff825ca6e0 T amdgpio_intr_enable +ffffffff825ca760 T amdgpio_intr_disable +ffffffff825ca7e0 T amdgpio_save +ffffffff825ca860 T amdgpio_restore +ffffffff825ca8f0 T amdgpio_save_pin +ffffffff825ca960 T amdgpio_restore_pin +ffffffff825ca9d0 T amdgpio_pin_intr +ffffffff825cb000 T acpihid_match +ffffffff825cb030 T acpihid_attach +ffffffff825cb210 T acpihid_init_dsm +ffffffff825cb370 T acpihid_eval +ffffffff825cb590 T acpihid_notify +ffffffff825cb5f0 T acpihid_button_array_enable +ffffffff825cc000 t iosf_acpi_match +ffffffff825cc050 t iosf_acpi_attach +ffffffff825cc150 t iosf_acpi_mbi_mdr_rd +ffffffff825cc1c0 t iosf_acpi_mbi_mdr_wr +ffffffff825cd000 T acpi_match +ffffffff825cd060 T acpi_attach +ffffffff825cd0a0 T acpi_probe +ffffffff825cd240 T acpi_map +ffffffff825cd330 T acpi_unmap +ffffffff825cd380 T acpi_bus_space_map +ffffffff825cd3a0 T acpi_bus_space_unmap +ffffffff825cd3c0 T acpi_intr_establish +ffffffff825cd500 T acpi_intr_disestablish +ffffffff825cd510 T acpi_scan +ffffffff825cd6b0 T acpi_acquire_glk +ffffffff825cd710 T acpi_release_glk +ffffffff825cd760 T acpi_attach_machdep +ffffffff825cd8f0 T acpi_sleep_cpu +ffffffff825cda90 T acpi_resume_cpu +ffffffff825cdb90 T sleep_mp +ffffffff825cdc80 T resume_mp +ffffffff825cdd70 T acpi_iommu_device_map +ffffffff825ce000 T hibernate_resume_machdep +ffffffff825ce050 T hibernate_drop_to_real_mode +ffffffff825ce060 T hibernate_activate_resume_pt_machdep +ffffffff825ce0a0 T hibernate_switch_stack_machdep +ffffffff825ce0e0 T hibernate_flush +ffffffff825ce110 T acpi_savecpu +ffffffff825cf000 T sleep_showstate +ffffffff825cf0f0 T sleep_setstate +ffffffff825cf150 T gosleep +ffffffff825cf210 T sleep_abort +ffffffff825cf240 T sleep_resume +ffffffff825cf2b0 T suspend_finish +ffffffff825d0000 T acpiopen +ffffffff825d00d0 T acpiclose +ffffffff825d0160 T acpiioctl +ffffffff825d02b0 T request_sleep +ffffffff825d0330 T acpi_filtdetach +ffffffff825d0380 T acpi_filtread +ffffffff825d03c0 T acpikqfilter +ffffffff825d1000 T acpipci_match +ffffffff825d1030 T acpipci_attach +ffffffff825d12f0 T acpipci_osc +ffffffff825d1430 T acpipci_parse_resources +ffffffff825d1560 T acpipci_attach_bus +ffffffff825d1730 T acpipci_print +ffffffff825d17a0 T acpipci_attach_busses +ffffffff825d2000 T efiopen +ffffffff825d2040 T eficlose +ffffffff825d2070 T efiioctl +ffffffff825d2110 T efiioc_get_table +ffffffff825d2280 T efiioc_var_get +ffffffff825d2500 T efiioc_var_next +ffffffff825d2720 T efiioc_var_set +ffffffff825d28a0 T efi_adapt_error +ffffffff825d3000 T efi_match +ffffffff825d3060 T efi_attach +ffffffff825d3330 T efi_map_runtime +ffffffff825d34b0 T efi_enter +ffffffff825d3550 T efi_leave +ffffffff825d35d0 T efi_fault +ffffffff825d4000 T vmm_probe +ffffffff825d4050 T vmm_attach +ffffffff825d4170 T vmm_activate +ffffffff825d42b0 T vmmopen +ffffffff825d4300 T vmmclose +ffffffff825d4330 T vm_find +ffffffff825d4450 T vmmioctl +ffffffff825d46d0 T vm_create +ffffffff825d49a0 T vm_get_info +ffffffff825d4bf0 T vm_terminate +ffffffff825d4d60 T vm_resetcpu +ffffffff825d4e80 T vm_share_mem +ffffffff825d4fd0 T pledge_ioctl_vmm +ffffffff825d50c0 T vm_find_vcpu +ffffffff825d5120 T vm_create_check_mem_ranges +ffffffff825d52e0 T vm_teardown +ffffffff825d5420 T vcpu_must_stop +ffffffff825d6000 T vmm_enabled +ffffffff825d6080 T vmm_attach_machdep +ffffffff825d6230 T vmm_quiesce_vmx +ffffffff825d6400 T vmm_activate_machdep +ffffffff825d6520 T vmm_stop +ffffffff825d6650 T vmm_start +ffffffff825d6730 T vmmioctl_machdep +ffffffff825d6800 T vm_intr_pending +ffffffff825d68a0 T vm_mprotect_ept +ffffffff825d6b20 T pledge_ioctl_vmm_machdep +ffffffff825d6b70 T vm_rwvmparams +ffffffff825d6d00 T vmm_init_pvclock +ffffffff825d6dd0 T vm_rwregs +ffffffff825d6ee0 T vcpu_readregs_vmx +ffffffff825d7310 T vcpu_writeregs_vmx +ffffffff825d7780 T vcpu_readregs_svm +ffffffff825d7c30 T vcpu_writeregs_svm +ffffffff825d8100 T vmm_get_guest_memtype +ffffffff825d8180 T vmx_mprotect_ept +ffffffff825d83e0 T vmx_pmap_find_pte_ept +ffffffff825d84b0 T start_vmm_on_cpu +ffffffff825d85d0 T stop_vmm_on_cpu +ffffffff825d8670 T vmclear_on_cpu +ffffffff825d86f0 T vm_impl_init_vmx +ffffffff825d8800 T vm_impl_init_svm +ffffffff825d8910 T vm_impl_init +ffffffff825d89b0 T vm_impl_deinit +ffffffff825d89e0 T vcpu_reload_vmcs_vmx +ffffffff825d8b20 T vcpu_reset_regs_svm +ffffffff825d8eb0 T svm_setmsrbrw +ffffffff825d8fc0 T svm_setmsrbr +ffffffff825d9090 T vmm_alloc_vpid +ffffffff825d91a0 T svm_setmsrbw +ffffffff825d9280 T vmx_setmsrbr +ffffffff825d9330 T vmx_setmsrbw +ffffffff825d93e0 T vmx_setmsrbrw +ffffffff825d94f0 T svm_set_clean +ffffffff825d9540 T svm_set_dirty +ffffffff825d9590 T vcpu_reset_regs_vmx +ffffffff825d9fd0 T vcpu_vmx_check_cap +ffffffff825da0d0 T vcpu_vmx_compute_ctrl +ffffffff825da2b0 T vcpu_init_vmx +ffffffff825da650 T vcpu_deinit_vmx +ffffffff825da7d0 T vcpu_reset_regs +ffffffff825da810 T vcpu_init_svm +ffffffff825da9a0 T vcpu_deinit_svm +ffffffff825daae0 T vcpu_init +ffffffff825daba0 T vmm_free_vpid +ffffffff825dac10 T vcpu_deinit +ffffffff825dac50 T vm_run +ffffffff825dae10 T vcpu_run_vmx +ffffffff825db600 T vcpu_run_svm +ffffffff825dbbf0 T vmm_fpurestore +ffffffff825dbcb0 T vmm_fpusave +ffffffff825dbd30 T vmm_translate_gva +ffffffff825dc040 T vmm_update_pvclock +ffffffff825dc140 T vmx_get_exit_info +ffffffff825dc1a0 T vmx_handle_exit +ffffffff825dc5d0 T vmx_instruction_error_decode +ffffffff825dc7a0 T vmm_get_guest_cpu_cpl +ffffffff825dc890 T vmx_handle_intr +ffffffff825dc920 T svm_handle_hlt +ffffffff825dc970 T vmx_handle_hlt +ffffffff825dca20 T svm_handle_exit +ffffffff825dcd40 T svm_handle_np_fault +ffffffff825dcee0 T vmm_handle_cpuid +ffffffff825dd580 T svm_handle_msr +ffffffff825dd850 T svm_handle_xsetbv +ffffffff825dd8f0 T svm_handle_inout +ffffffff825dd9f0 T vmm_inject_ud +ffffffff825dda20 T vmm_inject_db +ffffffff825dda50 T vmx_handle_np_fault +ffffffff825ddbb0 T vmx_handle_inout +ffffffff825ddd30 T vmx_handle_cr +ffffffff825ddf30 T vmx_handle_rdmsr +ffffffff825de000 T vmx_handle_wrmsr +ffffffff825de270 T vmx_handle_xsetbv +ffffffff825de340 T vmm_inject_gp +ffffffff825de370 T vmx_get_exit_qualification +ffffffff825de3d0 T vmx_get_guest_faulttype +ffffffff825de470 T svm_get_guest_faulttype +ffffffff825de4a0 T svm_fault_page +ffffffff825de530 T vmx_fault_page +ffffffff825de680 T vmm_get_guest_cpu_mode +ffffffff825de780 T vmx_load_pdptes +ffffffff825dea00 T vmx_handle_cr0_write +ffffffff825dec10 T vmx_handle_cr4_write +ffffffff825decb0 T vmm_handle_xsetbv +ffffffff825ded40 T vmx_handle_misc_enable_msr +ffffffff825deda0 T vmm_pat_is_valid +ffffffff825dee80 T vmm_gpa_is_valid +ffffffff825deef0 T vmx_exit_reason_decode +ffffffff825def30 T svm_exit_reason_decode +ffffffff825dfd40 T vcpu_state_decode +ffffffff825e0000 T vmm_dispatch_intr +ffffffff825e0020 T vmxon +ffffffff825e0050 T vmxoff +ffffffff825e0080 T vmclear +ffffffff825e00b0 T vmptrld +ffffffff825e00e0 T vmptrst +ffffffff825e0110 T vmwrite +ffffffff825e0140 T vmread +ffffffff825e0170 T invvpid +ffffffff825e018b t invvpid_fail +ffffffff825e0192 t invvpid_ret +ffffffff825e01b0 T invept +ffffffff825e01cb t invept_fail +ffffffff825e01d2 t invept_ret +ffffffff825e01f0 T vmx_enter_guest +ffffffff825e021b t skip_init +ffffffff825e02e8 t no_l1df_msr +ffffffff825e02eb t l1df_tlb_loop +ffffffff825e0304 t l1df_tlb_done +ffffffff825e030c t l1df_load_cache +ffffffff825e0323 t done_flush +ffffffff825e03b6 t do_resume +ffffffff825e043b t fail_launch_or_resume +ffffffff825e047d t fail_launch_unknown +ffffffff825e048a t fail_launch_invalid_vmcs +ffffffff825e0497 t fail_launch_valid_vmcs +ffffffff825e04b4 t vmx_exit_handler_asm +ffffffff825e0579 t restore_host +ffffffff825e0610 T svm_enter_guest +ffffffff825e07a0 t restore_host_svm +ffffffff825e1000 T sdmmc_match +ffffffff825e1050 T sdmmc_attach +ffffffff825e1390 T sdmmc_detach +ffffffff825e1440 T sdmmc_activate +ffffffff825e1510 T sdmmc_discover_task +ffffffff825e15d0 T sdmmc_create_thread +ffffffff825e1640 T sdmmc_holds_root_device +ffffffff825e16a0 T sdmmc_task_thread +ffffffff825e1890 T sdmmc_needs_discover +ffffffff825e1940 T sdmmc_del_task +ffffffff825e19f0 T sdmmc_card_detach +ffffffff825e1ad0 T sdmmc_add_task +ffffffff825e1b50 T sdmmc_card_attach +ffffffff825e1c60 T sdmmc_enable +ffffffff825e1db0 T sdmmc_scan +ffffffff825e1e40 T sdmmc_init +ffffffff825e1f40 T sdmmc_disable +ffffffff825e20a0 T sdmmc_function_free +ffffffff825e20c0 T sdmmc_delay +ffffffff825e2110 T sdmmc_select_card +ffffffff825e2330 T sdmmc_set_bus_power +ffffffff825e24e0 T sdmmc_function_alloc +ffffffff825e2570 T sdmmc_app_command +ffffffff825e2700 T sdmmc_mmc_command +ffffffff825e2780 T sdmmc_go_idle_state +ffffffff825e2890 T sdmmc_send_if_cond +ffffffff825e29e0 T sdmmc_set_relative_addr +ffffffff825e3000 T sdmmc_cisptr +ffffffff825e30a0 T sdmmc_read_cis +ffffffff825e33e0 T sdmmc_print_cis +ffffffff825e3550 T sdmmc_check_cis_quirks +ffffffff825e4000 T sdmmc_io_enable +ffffffff825e42a0 T sdmmc_io_reset +ffffffff825e43d0 T sdmmc_io_send_op_cond +ffffffff825e4540 T sdmmc_io_scan +ffffffff825e4690 T sdmmc_io_init +ffffffff825e47c0 T sdmmc_io_set_highspeed +ffffffff825e4a60 T sdmmc_io_set_bus_width +ffffffff825e4cf0 T sdmmc_io_function_ready +ffffffff825e4e70 T sdmmc_io_read_1 +ffffffff825e4fc0 T sdmmc_io_function_enable +ffffffff825e5390 T sdmmc_io_write_1 +ffffffff825e5510 T sdmmc_io_function_disable +ffffffff825e5790 T sdmmc_io_attach +ffffffff825e5880 T sdmmc_print +ffffffff825e5ad0 T sdmmc_submatch +ffffffff825e5b50 T sdmmc_io_detach +ffffffff825e5c00 T sdmmc_io_rw_direct +ffffffff825e5da0 T sdmmc_io_rw_extended_subr +ffffffff825e5f40 T sdmmc_io_rw_extended +ffffffff825e6340 T sdmmc_io_read_2 +ffffffff825e64a0 T sdmmc_io_write_2 +ffffffff825e6600 T sdmmc_io_read_4 +ffffffff825e6760 T sdmmc_io_write_4 +ffffffff825e68c0 T sdmmc_io_read_multi_1 +ffffffff825e69b0 T sdmmc_io_write_multi_1 +ffffffff825e6aa0 T sdmmc_io_read_region_1 +ffffffff825e6b90 T sdmmc_io_write_region_1 +ffffffff825e6c80 T sdmmc_io_xchg +ffffffff825e6e10 T sdmmc_intr_enable +ffffffff825e7080 T sdmmc_intr_disable +ffffffff825e72f0 T sdmmc_intr_establish +ffffffff825e73f0 T sdmmc_intr_disestablish +ffffffff825e74e0 T sdmmc_card_intr +ffffffff825e7530 T sdmmc_intr_task +ffffffff825e75c0 T sdmmc_io_set_blocklen +ffffffff825e8000 T sdmmc_mem_enable +ffffffff825e8450 T sdmmc_mem_send_op_cond +ffffffff825e8600 T sdmmc_mem_signal_voltage +ffffffff825e86c0 T sdmmc_mem_scan +ffffffff825e89d0 T sdmmc_decode_csd +ffffffff825e8e00 T sdmmc_decode_cid +ffffffff825e92a0 T sdmmc_mem_send_scr +ffffffff825e93e0 T sdmmc_mem_decode_scr +ffffffff825e9440 T sdmmc_mem_send_cxd_data +ffffffff825e95b0 T sdmmc_mem_set_bus_width +ffffffff825e96c0 T sdmmc_mem_sd_switch +ffffffff825e9970 T sdmmc_be512_to_bitfield512 +ffffffff825e9a20 T sdmmc_mem_mmc_switch +ffffffff825e9b10 T sdmmc_mem_init +ffffffff825e9c60 T sdmmc_mem_set_blocklen +ffffffff825e9d60 T sdmmc_mem_sd_init +ffffffff825ea140 T sdmmc_mem_mmc_init +ffffffff825ea800 T sdmmc_mem_select_transfer_mode +ffffffff825ea880 T sdmmc_mem_execute_tuning +ffffffff825ea910 T sdmmc_mem_read_block_subr +ffffffff825eac70 T sdmmc_mem_single_read_block +ffffffff825ead40 T sdmmc_mem_read_block +ffffffff825eaef0 T sdmmc_mem_write_block_subr +ffffffff825eb240 T sdmmc_mem_single_write_block +ffffffff825eb310 T sdmmc_mem_write_block +ffffffff825eb4c0 T sdmmc_mem_hibernate_write +ffffffff825ec000 T sdmmc_scsi_cmd +ffffffff825ec1f0 T sdmmc_minphys +ffffffff825ec270 T sdmmc_scsi_attach +ffffffff825ec460 T sdmmc_alloc_ccbs +ffffffff825ec5a0 T sdmmc_free_ccbs +ffffffff825ec600 T sdmmc_scsi_detach +ffffffff825ec760 T sdmmc_stimeout +ffffffff825ec7e0 T sdmmc_ccb_alloc +ffffffff825ec890 T sdmmc_ccb_free +ffffffff825ec970 T sdmmc_inquiry +ffffffff825ecbe0 T sdmmc_start_xs +ffffffff825eccd0 T sdmmc_complete_xs +ffffffff825ecda0 T sdmmc_done_xs +ffffffff825ecdf0 T sdmmc_scsi_hibernate_io +ffffffff825ed000 T bwfm_sdio_preinit +ffffffff825ed4a0 T bwfm_sdio_txcheck +ffffffff825ed4e0 T bwfm_sdio_txdata +ffffffff825ed550 T bwfm_sdio_txctl +ffffffff825ed6a0 T bwfm_sdio_buscore_read +ffffffff825ed6b0 T bwfm_sdio_buscore_write +ffffffff825ed6d0 T bwfm_sdio_buscore_prepare +ffffffff825ed810 T bwfm_sdio_buscore_activate +ffffffff825ed890 T bwfm_sdio_match +ffffffff825ed940 T bwfm_sdio_attach +ffffffff825edc00 T bwfm_sdio_detach +ffffffff825edc60 T bwfm_sdio_task +ffffffff825eddc0 T bwfm_sdio_write_1 +ffffffff825eddf0 T bwfm_sdio_read_1 +ffffffff825ede20 T bwfm_sdio_write_4 +ffffffff825eded0 T bwfm_sdio_read_4 +ffffffff825edf80 T bwfm_sdio_load_microcode +ffffffff825ee1e0 T bwfm_sdio_clkctl +ffffffff825ee310 T bwfm_sdio_dev_write +ffffffff825ee360 T bwfm_sdio_intr +ffffffff825ee3a0 T bwfm_sdio_ram_read_write +ffffffff825ee5d0 T bwfm_sdio_htclk +ffffffff825ee840 T bwfm_sdio_readshared +ffffffff825ee910 T bwfm_sdio_dev_read +ffffffff825ee950 T bwfm_sdio_rx_frames +ffffffff825eed00 T bwfm_sdio_tx_frames +ffffffff825eee00 T bwfm_sdio_backplane +ffffffff825eeeb0 T bwfm_sdio_buf_read +ffffffff825eef90 T bwfm_sdio_buf_write +ffffffff825ef040 T bwfm_sdio_frame_read_write +ffffffff825ef1c0 T bwfm_sdio_newbuf +ffffffff825ef240 T bwfm_sdio_tx_ok +ffffffff825ef2a0 T bwfm_sdio_tx_ctrlframe +ffffffff825ef3a0 T bwfm_sdio_tx_dataframe +ffffffff825ef4f0 T bwfm_sdio_rx_glom +ffffffff825f0000 T onewire_match +ffffffff825f0050 T onewire_attach +ffffffff825f00f0 T onewire_detach +ffffffff825f0160 T onewire_activate +ffffffff825f0180 T onewire_scan +ffffffff825f03a0 T onewire_createthread +ffffffff825f0410 T onewire_print +ffffffff825f04e0 T onewirebus_print +ffffffff825f0530 T onewire_lock +ffffffff825f0550 T onewire_unlock +ffffffff825f0570 T onewire_reset +ffffffff825f0590 T onewire_bit +ffffffff825f05b0 T onewire_read_byte +ffffffff825f06f0 T onewire_write_byte +ffffffff825f07d0 T onewire_read_block +ffffffff825f0870 T onewire_write_block +ffffffff825f0910 T onewire_triplet +ffffffff825f09f0 T onewire_matchrom +ffffffff825f0b40 T onewire_search +ffffffff825f0ee0 T onewire_thread +ffffffff825f1000 T onewire_crc +ffffffff825f10b0 T onewire_crc16 +ffffffff825f1170 T onewire_famname +ffffffff825f11b0 T onewire_matchbyfam +ffffffff825f2000 T owid_match +ffffffff825f2030 T owid_attach +ffffffff825f2100 T owid_detach +ffffffff825f2140 T owid_activate +ffffffff825f3000 T owsbm_match +ffffffff825f3030 T owsbm_attach +ffffffff825f31d0 T owsbm_detach +ffffffff825f3240 T owsbm_activate +ffffffff825f3270 T owsbm_update +ffffffff825f4000 T owtemp_match +ffffffff825f4030 T owtemp_attach +ffffffff825f4130 T owtemp_detach +ffffffff825f41a0 T owtemp_activate +ffffffff825f41d0 T owtemp_update +ffffffff825f5000 T owctr_match +ffffffff825f5030 T owctr_attach +ffffffff825f5180 T owctr_detach +ffffffff825f51f0 T owctr_activate +ffffffff825f5220 T owctr_update +ffffffff825f5250 T owctr_update_counter +ffffffff825f6000 A __text_page_start +ffffffff825f6000 T Xsyscall_meltdown +ffffffff825f600c T Xsyscall +ffffffff825f626e t Xsyscall_trampback +ffffffff825f6280 T intr_user_exit +ffffffff825f62c2 t intr_user_exit_post_ast +ffffffff825f63ee t Xiretq_trampback +ffffffff825f63fa T doreti_iret +ffffffff825f7000 T alltraps +ffffffff825f7138 T recall_trap +ffffffff825f7150 T alltraps_kern +ffffffff825f7153 T alltraps_kern_meltdown +ffffffff825f8000 ? Xsyscall32 +ffffffff825f8000 A __kutext_start +ffffffff825f8000 A __text_page_end +ffffffff825f9000 ? Xtrap00 +ffffffff825f9010 ? Xtrap01 +ffffffff825f9020 ? Xtrap02 +ffffffff825f9028 c calltrap_specstk +ffffffff825f90f0 ? calltrap_specstk_tramp +ffffffff825f9110 ? Xtrap03 +ffffffff825f9120 ? Xtrap04 +ffffffff825f9130 ? Xtrap05 +ffffffff825f9140 ? Xtrap06 +ffffffff825f9150 ? Xtrap07 +ffffffff825f9160 ? Xtrap08 +ffffffff825f9170 ? Xtrap09 +ffffffff825f9180 ? Xtrap0a +ffffffff825f9190 ? Xtrap0b +ffffffff825f91a0 ? Xtrap0c +ffffffff825f91b0 ? Xtrap0d +ffffffff825f9240 ? Xtrap0e +ffffffff825f9250 ? Xintrspurious +ffffffff825f9250 ? Xtrap0f +ffffffff825f9260 ? Xtrap10 +ffffffff825f9270 ? Xtrap11 +ffffffff825f9280 ? Xtrap12 +ffffffff825f9290 ? Xtrap13 +ffffffff825f92a0 ? Xtrap14 +ffffffff825f92b0 ? Xtrap15 +ffffffff825f92c0 ? Xtrap16 +ffffffff825f92c0 ? Xtrap17 +ffffffff825f92c0 ? Xtrap18 +ffffffff825f92c0 ? Xtrap19 +ffffffff825f92c0 ? Xtrap1a +ffffffff825f92c0 ? Xtrap1b +ffffffff825f92c0 ? Xtrap1c +ffffffff825f92c0 ? Xtrap1d +ffffffff825f92c0 ? Xtrap1e +ffffffff825f92c0 ? Xtrap1f +ffffffff825f92d0 ? x2apic_eoi +ffffffff825f92f0 ? Xintr_lapic_ipi +ffffffff825f9330 ? Xipi_invltlb +ffffffff825f9360 ? Xipi_invlpg +ffffffff825f9390 ? Xipi_invlrange +ffffffff825f93d0 ? Xipi_invltlb_pcid +ffffffff825f9410 ? Xipi_invlpg_pcid +ffffffff825f9460 ? Xipi_invlrange_pcid +ffffffff825f94d0 ? Xintr_lapic_ltimer +ffffffff825f9510 ? Xintr_xen_upcall +ffffffff825f9550 ? Xintr_hyperv_upcall +ffffffff825f9590 ? Xintr_legacy0 +ffffffff825f95d0 ? Xintr_legacy1 +ffffffff825f9610 ? Xintr_legacy2 +ffffffff825f9650 ? Xintr_legacy3 +ffffffff825f9690 ? Xintr_legacy4 +ffffffff825f96d0 ? Xintr_legacy5 +ffffffff825f9710 ? Xintr_legacy6 +ffffffff825f9750 ? Xintr_legacy7 +ffffffff825f9790 ? Xintr_legacy8 +ffffffff825f97d0 ? Xintr_legacy9 +ffffffff825f9810 ? Xintr_legacy10 +ffffffff825f9850 ? Xintr_legacy11 +ffffffff825f9890 ? Xintr_legacy12 +ffffffff825f98d0 ? Xintr_legacy13 +ffffffff825f9910 ? Xintr_legacy14 +ffffffff825f9950 ? Xintr_legacy15 +ffffffff825f9990 ? Xintr_ioapic_edge0 +ffffffff825f99d0 ? Xintr_ioapic_edge1 +ffffffff825f9a10 ? Xintr_ioapic_edge2 +ffffffff825f9a50 ? Xintr_ioapic_edge3 +ffffffff825f9a90 ? Xintr_ioapic_edge4 +ffffffff825f9ad0 ? Xintr_ioapic_edge5 +ffffffff825f9b10 ? Xintr_ioapic_edge6 +ffffffff825f9b50 ? Xintr_ioapic_edge7 +ffffffff825f9b90 ? Xintr_ioapic_edge8 +ffffffff825f9bd0 ? Xintr_ioapic_edge9 +ffffffff825f9c10 ? Xintr_ioapic_edge10 +ffffffff825f9c50 ? Xintr_ioapic_edge11 +ffffffff825f9c90 ? Xintr_ioapic_edge12 +ffffffff825f9cd0 ? Xintr_ioapic_edge13 +ffffffff825f9d10 ? Xintr_ioapic_edge14 +ffffffff825f9d50 ? Xintr_ioapic_edge15 +ffffffff825f9d90 ? Xintr_ioapic_edge16 +ffffffff825f9dd0 ? Xintr_ioapic_edge17 +ffffffff825f9e10 ? Xintr_ioapic_edge18 +ffffffff825f9e50 ? Xintr_ioapic_edge19 +ffffffff825f9e90 ? Xintr_ioapic_edge20 +ffffffff825f9ed0 ? Xintr_ioapic_edge21 +ffffffff825f9f10 ? Xintr_ioapic_edge22 +ffffffff825f9f50 ? Xintr_ioapic_edge23 +ffffffff825f9f90 ? Xintr_ioapic_edge24 +ffffffff825f9fd0 ? Xintr_ioapic_edge25 +ffffffff825fa010 ? Xintr_ioapic_edge26 +ffffffff825fa050 ? Xintr_ioapic_edge27 +ffffffff825fa090 ? Xintr_ioapic_edge28 +ffffffff825fa0d0 ? Xintr_ioapic_edge29 +ffffffff825fa110 ? Xintr_ioapic_edge30 +ffffffff825fa150 ? Xintr_ioapic_edge31 +ffffffff825fa190 ? Xintr_ioapic_edge32 +ffffffff825fa1d0 ? Xintr_ioapic_edge33 +ffffffff825fa210 ? Xintr_ioapic_edge34 +ffffffff825fa250 ? Xintr_ioapic_edge35 +ffffffff825fa290 ? Xintr_ioapic_edge36 +ffffffff825fa2d0 ? Xintr_ioapic_edge37 +ffffffff825fa310 ? Xintr_ioapic_edge38 +ffffffff825fa350 ? Xintr_ioapic_edge39 +ffffffff825fa390 ? Xintr_ioapic_edge40 +ffffffff825fa3d0 ? Xintr_ioapic_edge41 +ffffffff825fa410 ? Xintr_ioapic_edge42 +ffffffff825fa450 ? Xintr_ioapic_edge43 +ffffffff825fa490 ? Xintr_ioapic_edge44 +ffffffff825fa4d0 ? Xintr_ioapic_edge45 +ffffffff825fa510 ? Xintr_ioapic_edge46 +ffffffff825fa550 ? Xintr_ioapic_edge47 +ffffffff825fa590 ? Xintr_ioapic_edge48 +ffffffff825fa5d0 ? Xintr_ioapic_edge49 +ffffffff825fa610 ? Xintr_ioapic_edge50 +ffffffff825fa650 ? Xintr_ioapic_edge51 +ffffffff825fa690 ? Xintr_ioapic_edge52 +ffffffff825fa6d0 ? Xintr_ioapic_edge53 +ffffffff825fa710 ? Xintr_ioapic_edge54 +ffffffff825fa750 ? Xintr_ioapic_edge55 +ffffffff825fa790 ? Xintr_ioapic_edge56 +ffffffff825fa7d0 ? Xintr_ioapic_edge57 +ffffffff825fa810 ? Xintr_ioapic_edge58 +ffffffff825fa850 ? Xintr_ioapic_edge59 +ffffffff825fa890 ? Xintr_ioapic_edge60 +ffffffff825fa8d0 ? Xintr_ioapic_edge61 +ffffffff825fa910 ? Xintr_ioapic_edge62 +ffffffff825fa950 ? Xintr_ioapic_edge63 +ffffffff825fa990 ? Xintr_ioapic_level0 +ffffffff825fa9d0 ? Xintr_ioapic_level1 +ffffffff825faa10 ? Xintr_ioapic_level2 +ffffffff825faa50 ? Xintr_ioapic_level3 +ffffffff825faa90 ? Xintr_ioapic_level4 +ffffffff825faad0 ? Xintr_ioapic_level5 +ffffffff825fab10 ? Xintr_ioapic_level6 +ffffffff825fab50 ? Xintr_ioapic_level7 +ffffffff825fab90 ? Xintr_ioapic_level8 +ffffffff825fabd0 ? Xintr_ioapic_level9 +ffffffff825fac10 ? Xintr_ioapic_level10 +ffffffff825fac50 ? Xintr_ioapic_level11 +ffffffff825fac90 ? Xintr_ioapic_level12 +ffffffff825facd0 ? Xintr_ioapic_level13 +ffffffff825fad10 ? Xintr_ioapic_level14 +ffffffff825fad50 ? Xintr_ioapic_level15 +ffffffff825fad90 ? Xintr_ioapic_level16 +ffffffff825fadd0 ? Xintr_ioapic_level17 +ffffffff825fae10 ? Xintr_ioapic_level18 +ffffffff825fae50 ? Xintr_ioapic_level19 +ffffffff825fae90 ? Xintr_ioapic_level20 +ffffffff825faed0 ? Xintr_ioapic_level21 +ffffffff825faf10 ? Xintr_ioapic_level22 +ffffffff825faf50 ? Xintr_ioapic_level23 +ffffffff825faf90 ? Xintr_ioapic_level24 +ffffffff825fafd0 ? Xintr_ioapic_level25 +ffffffff825fb010 ? Xintr_ioapic_level26 +ffffffff825fb050 ? Xintr_ioapic_level27 +ffffffff825fb090 ? Xintr_ioapic_level28 +ffffffff825fb0d0 ? Xintr_ioapic_level29 +ffffffff825fb110 ? Xintr_ioapic_level30 +ffffffff825fb150 ? Xintr_ioapic_level31 +ffffffff825fb190 ? Xintr_ioapic_level32 +ffffffff825fb1d0 ? Xintr_ioapic_level33 +ffffffff825fb210 ? Xintr_ioapic_level34 +ffffffff825fb250 ? Xintr_ioapic_level35 +ffffffff825fb290 ? Xintr_ioapic_level36 +ffffffff825fb2d0 ? Xintr_ioapic_level37 +ffffffff825fb310 ? Xintr_ioapic_level38 +ffffffff825fb350 ? Xintr_ioapic_level39 +ffffffff825fb390 ? Xintr_ioapic_level40 +ffffffff825fb3d0 ? Xintr_ioapic_level41 +ffffffff825fb410 ? Xintr_ioapic_level42 +ffffffff825fb450 ? Xintr_ioapic_level43 +ffffffff825fb490 ? Xintr_ioapic_level44 +ffffffff825fb4d0 ? Xintr_ioapic_level45 +ffffffff825fb510 ? Xintr_ioapic_level46 +ffffffff825fb550 ? Xintr_ioapic_level47 +ffffffff825fb590 ? Xintr_ioapic_level48 +ffffffff825fb5d0 ? Xintr_ioapic_level49 +ffffffff825fb610 ? Xintr_ioapic_level50 +ffffffff825fb650 ? Xintr_ioapic_level51 +ffffffff825fb690 ? Xintr_ioapic_level52 +ffffffff825fb6d0 ? Xintr_ioapic_level53 +ffffffff825fb710 ? Xintr_ioapic_level54 +ffffffff825fb750 ? Xintr_ioapic_level55 +ffffffff825fb790 ? Xintr_ioapic_level56 +ffffffff825fb7d0 ? Xintr_ioapic_level57 +ffffffff825fb810 ? Xintr_ioapic_level58 +ffffffff825fb850 ? Xintr_ioapic_level59 +ffffffff825fb890 ? Xintr_ioapic_level60 +ffffffff825fb8d0 ? Xintr_ioapic_level61 +ffffffff825fb910 ? Xintr_ioapic_level62 +ffffffff825fb950 ? Xintr_ioapic_level63 +ffffffff825fc000 ? codepatch_fill_nop +ffffffff825fc000 A __cptext_start +ffffffff825fc000 A __kutext_end +ffffffff825fc0b0 ? codepatch_maprw +ffffffff825fc190 ? codepatch_unmaprw +ffffffff825fc200 ? codepatch_nop +ffffffff825fc360 ? codepatch_replace +ffffffff825fc510 ? codepatch_call +ffffffff825fc530 ? codepatch_jmp +ffffffff825fd000 A __cptext_end +ffffffff825fd000 A __rodata_start +ffffffff825fd000 C _etext +ffffffff825fd000 C etext +ffffffff825fe000 r seeprom_read +ffffffff825fe004 r icl_mg_pll_find_divisors.div1_vals +ffffffff825fe034 r athn_ac2qid +ffffffff825fe034 r athn_ac2qid +ffffffff825fe034 r athn_ac2qid +ffffffff825fe040 r rtwn_get_rssi.cckoff +ffffffff825fe068 r rsu_ac2qid +ffffffff825fe078 r pckbc_portcmd +ffffffff825fe07c r tht_fifo_write_pad.pad +ffffffff825fe084 r rsu_get_rssi.cckoff +ffffffff825fe0a4 r adlp_n_revids +ffffffff825fe0e8 r apple_iso_trans +ffffffff825fe0f0 r wihap_check_tx.txratetable +ffffffff825fe0f4 r dmamode +ffffffff825fe118 r gen9_edram_size_mb.sets +ffffffff825fe12c r dg2_g12_revid_step_tbl +ffffffff825ff000 r isomappings +ffffffff825ff080 r unimappings +ffffffff825ff230 r replacements +ffffffff8260293f r apollo_pio_rec +ffffffff8264ef3a r apollo_udma33_tim +ffffffff82664049 r pp_r600_decoded_lanes +ffffffff8269a1a5 r cmd680_setup_channel.udma_tbl +ffffffff826a2657 r apollo_udma100_tim +ffffffff826a265d r cmd0646_9_tim_udma +ffffffff826b0ade r substchar +ffffffff82706684 r apollo_udma133_tim +ffffffff8270668b r apollo_udma66_tim +ffffffff827066b5 r cy_pio_rec +ffffffff8270bda0 R drm_ca +ffffffff8270bdc8 R drm_filtops +ffffffff8270bdf8 R drmread_filtops +ffffffff8270c000 r vga_emulops +ffffffff8270c048 R vga_stdscreen +ffffffff8270c078 R vga_stdscreen_mono +ffffffff8270c0a8 R vga_stdscreen_bf +ffffffff8270c0d8 R vga_40lscreen +ffffffff8270c108 R vga_40lscreen_mono +ffffffff8270c138 R vga_40lscreen_bf +ffffffff8270c168 R vga_50lscreen +ffffffff8270c198 R vga_50lscreen_mono +ffffffff8270c1c8 R vga_50lscreen_bf +ffffffff8270c1f8 R vga_screenlist +ffffffff8270c208 R vga_screenlist_mono +ffffffff8270c218 R vga_accessops +ffffffff8270c278 r i945_wm_info +ffffffff8270c2b8 r bgansitopc +ffffffff8270c2c0 r pctoansi +ffffffff8270c300 r sdma_offsets +ffffffff8270c300 r sdma_offsets +ffffffff8270c338 r iha_rate_tbl +ffffffff8270c370 r i830_a_wm_info +ffffffff8270c3a8 r gen9_edram_size_mb.ways +ffffffff8270c408 r aggr_periodic_times +ffffffff8270c500 r michael_final.pad +ffffffff8270c528 r rt_copysa.maskarray +ffffffff8270c530 r i915_wm_info +ffffffff8270c538 r amdgpu_ih_clientid_jpeg +ffffffff8270c538 r amdgpu_ih_clientid_uvds +ffffffff8270c538 r amdgpu_ih_clientid_vcns +ffffffff8270c538 r amdgpu_ih_clientid_vcns +ffffffff8270c538 r amdgpu_ih_clientid_vcns +ffffffff8270c568 r jsl_ehl_revids +ffffffff8270c578 r vga_setfontset.cmaptabb +ffffffff8270c5e8 r i830_bc_wm_info +ffffffff8270c650 r hsw_activate_psr2.map +ffffffff8270c658 r tgl_revids +ffffffff8270c690 r __drm_universal_plane_init.default_modifiers +ffffffff8270c6a0 r iwn_tid2fifo +ffffffff8270c6b8 r vga_setfontset.cmaptaba +ffffffff8270c6c0 r crtc_offsets +ffffffff8270c6c0 r crtc_offsets +ffffffff8270c6c0 r crtc_offsets +ffffffff8270c768 r rtwn_r88e_get_rssi.cckoff +ffffffff8270d000 R edid_vendors +ffffffff8270d2c0 R edid_nvendors +ffffffff8270d2d0 R edid_products +ffffffff8270d330 R edid_nproducts +ffffffff8270d340 r _edid_modes +ffffffff8270e000 R videomode_list +ffffffff8270f080 R videomode_count +ffffffff82710000 r ahc_hard_errors +ffffffff82710080 r critical_sections +ffffffff827100b0 r patches +ffffffff82710d50 r seqprog +ffffffff82712000 r ahc_switch +ffffffff82713000 r termstat_strings +ffffffff82713020 r critical_sections +ffffffff82713060 r seqprog +ffffffff82713d50 r patches +ffffffff82715000 r ahd_switch +ffffffff82716000 R aic_switch +ffffffff82717000 R adw_switch +ffffffff82718000 R gdt_switch +ffffffff82719000 R twe_switch +ffffffff8271a000 R ciss_switch +ffffffff8271a030 R ciss_level +ffffffff8271a050 R ciss_stat +ffffffff8271b000 R ami_switch +ffffffff8271b028 R ami_raw_switch +ffffffff8271c000 R mfi_switch +ffffffff8271c028 R mfi_pd_switch +ffffffff8271c050 r mfi_iop_xscale +ffffffff8271c080 r mfi_iop_ppc +ffffffff8271c0b0 r mfi_iop_gen2 +ffffffff8271c0e0 r mfi_iop_skinny +ffffffff8271c110 r mfi_bbu_indicators +ffffffff8271d000 R qlw_switch +ffffffff8271e000 R isp_2100_risc_code +ffffffff82730bf0 R isp_2200_risc_code +ffffffff82743990 R isp_2300_risc_code +ffffffff8275d408 R qla_switch +ffffffff8275d430 r qla_regs_2100 +ffffffff8275d460 r qla_regs_2200 +ffffffff8275d490 r qla_regs_23XX +ffffffff8275e000 R ahci_atascsi_methods +ffffffff8275f000 R nvme_switch +ffffffff8275f028 r nvme_ops +ffffffff82760000 R mpi_switch +ffffffff82760060 r bwi_rf_calc_nrssi_slope_11b.save_phy_regs +ffffffff82760090 r chv_oa_mux_regs +ffffffff827600b0 r fiji_clock_stretcher_lookup_table +ffffffff827600b0 r tonga_clock_stretcher_lookup_table +ffffffff827600d0 r iosf_pci_devices +ffffffff827600f0 r link_speed +ffffffff827600f0 r link_speed +ffffffff82760130 r drm_fb_xfrm.default_dst_pitch +ffffffff82760130 r non_supported_protection +ffffffff82760140 r tgl_uy_revids +ffffffff827602a0 r bwi_phy_noise_11g_rev1 +ffffffff82760310 r cardslot_process_event.antonym_ev +ffffffff827603a0 r gen11_oa_mux_regs +ffffffff82760440 r dpia_to_preferred_enc_id_table +ffffffff827604b0 r ddr2_cycle_tenths +ffffffff82760520 r rtw_intr_rx.ratetbl +ffffffff827605a0 r abm_config +ffffffff82760620 r getbootinfo.ports +ffffffff82760670 r reg_offsets +ffffffff82760680 r bwi_rf_lo_measure_11g.rf_lo_adjust +ffffffff82760690 r glk_revids +ffffffff827606a0 r init_non_clock_fields.look_up +ffffffff827606b0 r uftdi_8u232am_getrate.roundoff +ffffffff82760710 r zyd_rx_data.rates +ffffffff82760730 r ieee80211_ra_valid_tx_mcs.max_mcs +ffffffff82760760 r intel_engine_init_tlb_invalidation.gen8_regs +ffffffff82760790 r bwi_phy_noise_11g +ffffffff827607a0 r hpt366_pio +ffffffff82760800 r bwi_rf_calc_nrssi_slope_11g.save_phy3_regs +ffffffff82760820 r ether_crc32_be_update.rev +ffffffff82760820 r rtw_grf5101_mac_crypt.caesar +ffffffff82760870 r snb_b_fdi_train_param +ffffffff82760940 r intel_hpll_vco.elk_vco +ffffffff82760960 r icl_revids +ffffffff827609c0 r pin_offsets +ffffffff827609e0 r amdgpu_ih_srcid_jpeg +ffffffff82760a20 r firmware_list +ffffffff82760a80 r atom_arg_shift +ffffffff82760a80 r atom_arg_shift +ffffffff82760ac0 r pf_syncookie_wstab +ffffffff82760ae0 r ieee80211_media_init.mopts +ffffffff82760b40 r add_entropy_words.twist_table +ffffffff82760be0 r urtw_8225v2_txpwr_cck +ffffffff82760c00 r bwfm_pci_prio2fifo +ffffffff82760c00 r ieee80211_up_to_ac.up_to_ac +ffffffff82760cc0 r paritytab +ffffffff82760cc0 r x86emu_parity_tab +ffffffff82760ce0 r legacy_connector_convert +ffffffff82760d20 r gen7_oa_mux_regs +ffffffff82760d40 r hsw_oa_mux_regs +ffffffff82760d60 r notetab +ffffffff82760d80 r urtw_8225v2_txpwr_cck_ch14 +ffffffff82760da0 r bwi_rf_calibval.rf_calibvals +ffffffff82760e40 r pf_syncookie_msstab +ffffffff82760ea0 r xgmi3x16_pcs_err_status_reg_aldebaran +ffffffff82760f00 r uath_wme_init.uath_wme_11g +ffffffff82760f40 r gen7_oa_b_counters +ffffffff82761140 r rtwn_iq_calib_run.reg_adda +ffffffff82761180 r atom_def_dst +ffffffff82761180 r atom_def_dst +ffffffff827611c0 r sha256_initial_hash_value +ffffffff82761220 r otus_edca_def +ffffffff82761240 r intel_hpll_vco.blb_vco +ffffffff82761320 r epic_pci_subsys_info +ffffffff82761340 r kbl_revids +ffffffff82761360 r atom_arg_mask +ffffffff82761360 r atom_arg_mask +ffffffff827613c0 r butmap +ffffffff82761400 r GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS +ffffffff82761440 r comsoft.lsrmap +ffffffff82761480 r xgmi3x16_pcs_err_noncorrectable_mask_reg_aldebaran +ffffffff827614a0 r tulip_mii_phy_readspecific.table +ffffffff82761540 r intel_hpll_vco.pnv_vco +ffffffff827615a0 r dmapageport +ffffffff82761660 r intel_hpll_vco.ctg_vco +ffffffff82761720 r drm_calculate_luminance_range.pre_computed_values +ffffffff82762000 R sili_atascsi_methods +ffffffff82763000 R ncr53c9x_switch +ffffffff82764000 r scf_period +ffffffff82765000 R siop_script +ffffffff827655a0 R lun_switch +ffffffff827655d0 R tag_switch +ffffffff82765660 R load_dsa +ffffffff827656c4 R siop_led_on +ffffffff827656cc R siop_led_off +ffffffff827656d8 R siop_switch +ffffffff82766000 R ep_vortex_media +ffffffff82766100 R ep_default_to_media +ffffffff82767000 R wi_card_ident +ffffffff82769000 R ucode_table +ffffffff8276a000 r re_revisions +ffffffff8276a290 r re_kstats_tpl +ffffffff8276c000 R smc91cxx_media +ffffffff8276c010 R smc91cxx_mii_bitbang_ops +ffffffff8276d000 R dl10019_mii_bitbang_ops +ffffffff8276d028 R dl10022_mii_bitbang_ops +ffffffff8276e000 R ax88190_mii_bitbang_ops +ffffffff82770000 R ac97_audio_default +ffffffff82770020 R ac97_on_off +ffffffff82770324 R ac97_mic_select +ffffffff82770628 R ac97_mono_select +ffffffff8277092c R ac97_source +ffffffff82770c30 R ac97_volume_stereo +ffffffff82770c4c R ac97_volume_mono +ffffffff82770c70 R source_info +ffffffff82771470 R ac97_ad +ffffffff82771580 R ac97_ak +ffffffff82771610 R ac97_av +ffffffff82771750 R ac97_rl +ffffffff827717a0 R ac97_cm +ffffffff82771820 R ac97_cr +ffffffff82771840 R ac97_cs +ffffffff82771920 R ac97_cx +ffffffff82771980 R ac97_dt +ffffffff827719a0 R ac97_em +ffffffff827719d0 R ac97_es +ffffffff827719f0 R ac97_is +ffffffff82771a10 R ac97_ic +ffffffff82771a90 R ac97_it +ffffffff82771ac0 R ac97_ns +ffffffff82771b80 R ac97_ps +ffffffff82771bb0 R ac97_sl +ffffffff82771bd0 R ac97_st +ffffffff82771d20 R ac97_vi +ffffffff82771d50 R ac97_tt +ffffffff82771dd0 R ac97_ti +ffffffff82771df0 R ac97_wb +ffffffff82771e10 R ac97_wo +ffffffff82771ea0 R ac97_ym +ffffffff82771ef0 R ac97_vendors +ffffffff827721f0 R ac97enhancement +ffffffff827722f0 R ac97feature +ffffffff82773000 R lm_chips +ffffffff82773020 R lm78_sensors +ffffffff827731a0 R w83627hf_sensors +ffffffff827733a0 R w83627ehf_sensors +ffffffff827735c0 R w83627dhg_sensors +ffffffff827737c0 R nct6776f_sensors +ffffffff82773a00 R nct6779d_sensors +ffffffff82773d60 R w83637hf_sensors +ffffffff82773f20 R w83697hf_sensors +ffffffff827740c0 R w83781d_sensors +ffffffff82774280 R w83782d_sensors +ffffffff82774480 R w83783s_sensors +ffffffff82774600 R w83791d_sensors +ffffffff82774860 R w83792d_sensors +ffffffff82774ae0 R as99127f_sensors +ffffffff82775000 r ar5k_known_products +ffffffff82775110 r ar5111_gain_opt +ffffffff827751e0 r ar5112_gain_opt +ffffffff827752b0 r ar5k_5ghz_channels +ffffffff82775a00 r ar5k_2ghz_channels +ffffffff82775f10 r ar5111_rf +ffffffff82776350 r ar5112a_rf +ffffffff82776890 r ar5112_rf +ffffffff82776da0 r ar5413_rf +ffffffff827771b0 r ar2413_rf +ffffffff827774d0 r ar2425_rf +ffffffff82777830 r ar5111_rfg +ffffffff82777b30 r ar5112_rfg +ffffffff82777e30 r ar5413_rfg +ffffffff82778130 r ar2413_rfg +ffffffff82778430 r ar5k_rt_11a +ffffffff82778552 r ar5k_rt_11b +ffffffff82778674 r ar5k_rt_11g +ffffffff82778796 r ar5k_rt_xr +ffffffff82779000 r ar5210_ini +ffffffff8277a000 r ar5211_mode +ffffffff8277a2c0 r ar5211_ini +ffffffff8277aad0 r ar5211_rf +ffffffff8277b000 r ar5212_pcie +ffffffff8277b080 r ar5212_mode +ffffffff8277b310 r ar5212_ini +ffffffff8277bc80 r ar5212_ar5111_mode +ffffffff8277bf20 r ar5212_ar5112_mode +ffffffff8277c1b0 r ar5413_mode +ffffffff8277cb10 r ar2413_mode +ffffffff8277d430 r ar2425_mode +ffffffff8277dd90 r ar5111_bbgain +ffffffff8277e090 r ar5112_bbgain +ffffffff8277f000 r athn_5ghz_chans +ffffffff8277f020 r athn_rates +ffffffff82780000 r athn_rates +ffffffff82781000 r ar9160_ini +ffffffff82781068 r ar5416_ini +ffffffff827810d0 r ar5416_serdes +ffffffff827810e8 r ar9160_1_1_addac +ffffffff827810f8 r ar9160_1_0_addac +ffffffff82781108 r ar5416_2_2_addac +ffffffff82781118 r ar5416_2_1_addac +ffffffff82781128 r ar5416_set_power_calib.chainoffset +ffffffff82781140 r ar9160_bank6tpc_vals +ffffffff827811c0 r ar5416_bank6tpc_vals +ffffffff82781240 r ar5416_bb_rfgain_vals_2g +ffffffff82781340 r ar5416_bb_rfgain_vals_5g +ffffffff82781440 r ar5416_bank6_vals +ffffffff827814c0 r ar9160_regs +ffffffff82781540 r ar9160_vals_5g20 +ffffffff82781640 r ar9160_vals_5g40 +ffffffff82781740 r ar9160_vals_2g40 +ffffffff82781840 r ar9160_vals_2g20 +ffffffff82781940 r ar9160_cm_regs +ffffffff82781c30 r ar9160_cm_vals +ffffffff82782210 r ar5416_regs +ffffffff82782290 r ar5416_vals_5g20 +ffffffff82782390 r ar5416_vals_5g40 +ffffffff82782490 r ar5416_vals_2g40 +ffffffff82782590 r ar5416_vals_2g20 +ffffffff82782690 r ar5416_cm_regs +ffffffff82782980 r ar5416_cm_vals +ffffffff82782f60 r ar5416_serdes_regs +ffffffff82782f90 r ar5416_serdes_vals +ffffffff82782fc0 r ar9160_1_1_addac_vals +ffffffff82783040 r ar9160_1_0_addac_vals +ffffffff827830c0 r ar5416_2_2_addac_vals +ffffffff82783150 r ar5416_2_1_addac_vals +ffffffff82784000 r ar9280_2_0_ini +ffffffff82784068 r ar9280_2_0_serdes +ffffffff82784080 r ar9280_2_0_rx_gain_23db_backoff +ffffffff827840a0 r ar9280_2_0_rx_gain_13db_backoff +ffffffff827840c0 r ar9280_2_0_rx_gain +ffffffff827840e0 r ar9280_2_0_tx_gain_high_power +ffffffff82784100 r ar9280_2_0_tx_gain +ffffffff82784120 r ar9280_init_from_rom.chainoffset +ffffffff82784130 r ar9280_2_0_regs +ffffffff82784190 r ar9280_2_0_vals_5g20 +ffffffff82784250 r ar9280_2_0_vals_5g40 +ffffffff82784310 r ar9280_2_0_vals_2g40 +ffffffff827843d0 r ar9280_2_0_vals_2g20 +ffffffff82784490 r ar9280_2_0_cm_regs +ffffffff82784740 r ar9280_2_0_cm_vals +ffffffff82784c90 r ar9280_2_0_fast_clock_regs +ffffffff82784cb0 r ar9280_2_0_fast_clock_vals_5g20 +ffffffff82784cf0 r ar9280_2_0_fast_clock_vals_5g40 +ffffffff82784d30 r ar9280_2_0_serdes_regs +ffffffff82784d60 r ar9280_2_0_serdes_vals +ffffffff82784d90 r ar9280_2_0_rx_gain_regs +ffffffff82784ea0 r ar9280_2_0_rx_gain_23db_backoff_vals_5g +ffffffff827850b0 r ar9280_2_0_rx_gain_23db_backoff_vals_2g +ffffffff827852c0 r ar9280_2_0_rx_gain_13db_backoff_vals_5g +ffffffff827854d0 r ar9280_2_0_rx_gain_13db_backoff_vals_2g +ffffffff827856e0 r ar9280_2_0_rx_gain_vals_5g +ffffffff827858f0 r ar9280_2_0_rx_gain_vals_2g +ffffffff82785b00 r ar9280_2_0_tx_gain_regs +ffffffff82785b40 r ar9280_2_0_tx_gain_high_power_vals_5g +ffffffff82785bc0 r ar9280_2_0_tx_gain_high_power_vals_2g +ffffffff82785c40 r ar9280_2_0_tx_gain_vals_5g +ffffffff82785cc0 r ar9280_2_0_tx_gain_vals_2g +ffffffff82786000 r ar9271_ini +ffffffff82786068 r ar9285_1_2_ini +ffffffff827860d0 r ar9280_2_0_serdes +ffffffff827860e8 r ar9271_tx_gain_high_power +ffffffff82786108 r ar9271_tx_gain +ffffffff82786128 r ar9285_2_0_tx_gain_high_power +ffffffff82786148 r ar9285_2_0_tx_gain +ffffffff82786168 r ar9285_1_2_tx_gain_high_power +ffffffff82786188 r ar9285_1_2_tx_gain +ffffffff827861b0 r ar9271_regs +ffffffff82786410 r ar9271_vals_2g40 +ffffffff827868d0 r ar9271_vals_2g20 +ffffffff82786d90 r ar9271_cm_regs +ffffffff82787020 r ar9271_cm_vals +ffffffff82787540 r ar9285_1_2_regs +ffffffff827877a0 r ar9285_1_2_vals_2g40 +ffffffff82787c60 r ar9285_1_2_vals_2g20 +ffffffff82788120 r ar9285_1_2_cm_regs +ffffffff827883a0 r ar9285_1_2_cm_vals +ffffffff82788890 r ar9280_2_0_serdes_regs +ffffffff827888c0 r ar9280_2_0_serdes_vals +ffffffff827888f0 r ar9271_tx_gain_regs +ffffffff82788940 r ar9271_tx_gain_high_power_vals_2g +ffffffff827889d0 r ar9271_tx_gain_vals_2g +ffffffff82788a60 r ar9285_1_2_tx_gain_regs +ffffffff82788ab0 r ar9285_2_0_tx_gain_high_power_vals_2g +ffffffff82788b50 r ar9285_2_0_tx_gain_vals_2g +ffffffff82788bf0 r ar9285_1_2_tx_gain_high_power_vals_2g +ffffffff82788c90 r ar9285_1_2_tx_gain_vals_2g +ffffffff82789000 r ar9287_1_1_ini +ffffffff82789068 r ar9280_2_0_serdes +ffffffff82789080 r ar9287_1_1_rx_gain +ffffffff827890a0 r ar9287_1_1_tx_gain +ffffffff827890c0 r ar9287_1_1_regs +ffffffff82789120 r ar9287_1_1_vals_2g40 +ffffffff827891d0 r ar9287_1_1_vals_2g20 +ffffffff82789280 r ar9287_1_1_cm_regs +ffffffff82789560 r ar9287_1_1_cm_vals +ffffffff82789b20 r ar9280_2_0_serdes_regs +ffffffff82789b50 r ar9280_2_0_serdes_vals +ffffffff82789b80 r ar9287_1_1_rx_gain_regs +ffffffff82789d90 r ar9287_1_1_rx_gain_vals_2g +ffffffff8278a1a0 r ar9287_1_1_tx_gain_regs +ffffffff8278a200 r ar9287_1_1_tx_gain_vals_2g +ffffffff8278b000 r athn_rates +ffffffff8278c000 r ar9485_1_1_ini +ffffffff8278c068 r ar9485_1_1_serdes +ffffffff8278c080 r ar9380_2_2_ini +ffffffff8278c0e8 r ar9380_2_2_serdes +ffffffff8278c100 r ar9380_2_2_rx_gain_wo_xlna +ffffffff8278c120 r ar9380_2_2_rx_gain +ffffffff8278c140 r ar9485_1_1_rx_gain +ffffffff8278c160 r ar9380_2_2_tx_gain_high_ob_db +ffffffff8278c180 r ar9380_2_2_tx_gain_low_ob_db +ffffffff8278c1a0 r ar9380_2_2_tx_gain_high_power +ffffffff8278c1c0 r ar9380_2_2_tx_gain +ffffffff8278c1e0 r ar9485_1_1_tx_gain +ffffffff8278c200 r ar9485_1_1_regs +ffffffff8278c270 r ar9485_1_1_vals_2g40 +ffffffff8278c350 r ar9485_1_1_vals_2g20 +ffffffff8278c430 r ar9485_1_1_cm_regs +ffffffff8278c720 r ar9485_1_1_cm_vals +ffffffff8278cd00 r ar9485_1_1_serdes_regs +ffffffff8278cd0c r ar9485_1_1_serdes_vals +ffffffff8278cd20 r ar9380_2_2_regs +ffffffff8278cdb0 r ar9380_2_2_vals_5g20 +ffffffff8278ced0 r ar9380_2_2_vals_5g40 +ffffffff8278cff0 r ar9380_2_2_vals_2g40 +ffffffff8278d110 r ar9380_2_2_vals_2g20 +ffffffff8278d230 r ar9380_2_2_cm_regs +ffffffff8278d5d0 r ar9380_2_2_cm_vals +ffffffff8278dd00 r ar9380_2_2_fast_clock_regs +ffffffff8278dd20 r ar9380_2_2_fast_clock_vals_5g20 +ffffffff8278dd50 r ar9380_2_2_fast_clock_vals_5g40 +ffffffff8278dd74 r ar9380_2_2_serdes_regs +ffffffff8278dd80 r ar9380_2_2_serdes_vals +ffffffff8278dd90 r ar9380_2_2_rx_gain_regs +ffffffff8278df90 r ar9380_2_2_rx_gain_wo_xlna_vals +ffffffff8278e390 r ar9380_2_2_rx_gain_vals +ffffffff8278e790 r ar9485_1_1_rx_gain_regs +ffffffff8278e890 r ar9485_1_1_rx_gain_vals +ffffffff8278ea90 r ar9380_2_2_tx_gain_regs +ffffffff8278eb60 r ar9380_2_2_tx_gain_high_ob_db_vals_5g +ffffffff8278ed00 r ar9380_2_2_tx_gain_high_ob_db_vals_2g +ffffffff8278eea0 r ar9380_2_2_tx_gain_low_ob_db_vals_5g +ffffffff8278f040 r ar9380_2_2_tx_gain_low_ob_db_vals_2g +ffffffff8278f1e0 r ar9380_2_2_tx_gain_high_power_vals_5g +ffffffff8278f380 r ar9380_2_2_tx_gain_high_power_vals_2g +ffffffff8278f520 r ar9380_2_2_tx_gain_vals_5g +ffffffff8278f6c0 r ar9380_2_2_tx_gain_vals_2g +ffffffff8278f860 r ar9485_1_1_tx_gain_regs +ffffffff8278f8f0 r ar9485_1_1_tx_gain_vals_2g +ffffffff8278fa10 r ar9380_def_rom +ffffffff8278fe50 r ar9380_def_rom_h112 +ffffffff82790290 r ar9380_def_rom_h116 +ffffffff827906d0 r ar9380_def_rom_x112 +ffffffff82790b10 r ar9380_def_rom_x113 +ffffffff82791000 R atw_txthresh_tab_lo +ffffffff82791050 R atw_txthresh_tab_hi +ffffffff827910a0 r atw_attach.empty_macaddr +ffffffff827910b0 r atw_attach.type_strings +ffffffff827910d0 r atw_rfmd2958_ifn +ffffffff82791110 r atw_rfmd2958_rf1r +ffffffff82791150 r atw_rxintr.rate_tbl +ffffffff82792000 r rtw_identify_sta.empty_macaddr +ffffffff82793000 r rtwn_set_key.etherzeroaddr +ffffffff82793010 r rtl8188eu_rf_prog +ffffffff82793030 r rtl8188ftv_rf_prog +ffffffff82793050 r rtl8192e_rf_prog +ffffffff82793080 r rtl8188ce_rf_prog +ffffffff827930a0 r rtl8188ru_rf_prog +ffffffff827930c0 r rtl8188cu_rf_prog +ffffffff827930e0 r rtl8192ce_rf_prog +ffffffff82793110 r rtl8188ru_txagc +ffffffff82793170 r rtl8188eu_rf_regs +ffffffff82793230 r rtl8188eu_rf_vals +ffffffff827933b0 r rtl8188ftv_rf_regs +ffffffff82793490 r rtl8188ftv_rf_vals +ffffffff82793640 r rtl8192e_rf_regs +ffffffff82793710 r rtl8192e_rf_vals +ffffffff827938b0 r rtl8192e_rf2_regs +ffffffff82793950 r rtl8192e_rf2_vals +ffffffff82793a90 r rtl8192ce_rf1_regs +ffffffff82793bb0 r rtl8188ce_rf_vals +ffffffff82793df0 r rtl8188ru_rf_vals +ffffffff82794030 r rtl8188cu_rf_vals +ffffffff82794270 r rtl8192ce_rf1_vals +ffffffff827944b0 r rtl8192ce_rf2_regs +ffffffff82794500 r rtl8192ce_rf2_vals +ffffffff827945a0 r rtl8192cu_txagc +ffffffff82795000 r rt2560_rf2522_r2 +ffffffff82795040 r rt2560_rf2524_r2 +ffffffff82795080 r rt2560_rf2525_hi_r2 +ffffffff827950c0 r rt2560_rf2525_r2 +ffffffff82795100 r rt2560_rf2525e_r2 +ffffffff82795140 r rt2560_rf2526_hi_r2 +ffffffff82795180 r rt2560_rf2526_r2 +ffffffff827951c0 r rt2560_def_bbp +ffffffff82795200 r rt2560_def_mac +ffffffff82796000 r rt2661_rf5225_1 +ffffffff82796300 r rt2661_rf5225_2 +ffffffff82796600 r rt2661_def_bbp +ffffffff82796640 r rt2661_def_mac +ffffffff82797000 r rt2860_rf2850 +ffffffff82797430 r rt2860_rates +ffffffff827974f0 r rt3572_def_rf +ffffffff82797530 r rt3090_def_rf +ffffffff82797560 r rt5392_def_rf +ffffffff827975e0 r rt3290_def_rf +ffffffff82797640 r rt5390_def_rf +ffffffff827976c0 r rt5390_def_bbp +ffffffff827976f0 r rt2860_def_mac +ffffffff82799000 r acx111_reg +ffffffff82799040 r acx111_rate_map +ffffffff8279a000 r acx100_reg +ffffffff8279a040 r acx100_txpower_rfmd +ffffffff8279a060 r gen8_rcs_offsets +ffffffff8279a090 r acx100_txpower_maxim +ffffffff8279a0b0 r mtl_rcs_offsets +ffffffff8279a0f0 r digits +ffffffff8279a0f0 r pppdumpb.digits +ffffffff8279a0f0 r pppdumpm.digits +ffffffff8279a140 r hangpic +ffffffff8279a180 r gen11_rcs_offsets +ffffffff8279a1b0 r xehp_rcs_offsets +ffffffff8279a1e0 r dg2_rcs_offsets +ffffffff8279a220 r dg2_xcs_offsets +ffffffff8279a250 r gen12_xcs_offsets +ffffffff8279b000 r trinity_override_mgpg_sequences +ffffffff8279b3c0 r voltage_swing_to_pre_emphasis +ffffffff8279b3d0 r sgpr_init_compute_shader +ffffffff8279b4a0 r intel_hpll_vco.cl_vco +ffffffff8279b4c0 r vgpr_init_compute_shader +ffffffff8279c000 r malo_cmd_string.cmds +ffffffff8279c0b0 r malo_cmd_string_result.results +ffffffff8279d000 R bwi_vendor_led_act +ffffffff8279d00c R bwi_default_led_act +ffffffff8279d010 R bwi_led_duration +ffffffff8279d380 r bwi_sup_bphy +ffffffff8279d3c0 r bwi_phy_freq_11g_rev1 +ffffffff8279d5c0 r bwi_phy_rotor_11g_rev1 +ffffffff8279d6a0 r bwi_phy_noise_scale_11g_rev2 +ffffffff8279d6e0 r bwi_phy_noise_scale_11g_rev7 +ffffffff8279d720 r bwi_phy_noise_scale_11g +ffffffff8279d760 r bwi_phy_sigma_sq_11g_rev2 +ffffffff8279d7d0 r bwi_phy_sigma_sq_11g_rev7 +ffffffff8279d840 r bwi_phy_delay_11g_rev1 +ffffffff8279d920 r bwi_rf_get_gains.save_phy_regs +ffffffff8279d940 r bwi_rf_lo_find.map +ffffffff8279d960 r bwi_txpower_map_11b +ffffffff8279d9a0 r bwi_txpower_map_11g +ffffffff8279d9e0 r _bwi_rf_lo_update_11g.rf_atten_list +ffffffff8279da20 r _bwi_rf_lo_update_11g.rf_atten_init_list +ffffffff8279da60 r _bwi_rf_lo_update_11g.rf_lo_measure_order +ffffffff8279daa0 r bwi_rf_set_nrssi_ofs_11g.save_phy_comm_regs +ffffffff8279dac0 r bwi_bbpid_map +ffffffff8279daf0 r bwi_regwin_count +ffffffff8279db40 r bwi_clkfreq +ffffffff8279db58 r bwi_zero_addr +ffffffff8279e000 R uhci_bus_methods +ffffffff8279e030 R uhci_root_ctrl_methods +ffffffff8279e060 R uhci_root_intr_methods +ffffffff8279e090 R uhci_device_ctrl_methods +ffffffff8279e0c0 R uhci_device_intr_methods +ffffffff8279e0f0 R uhci_device_bulk_methods +ffffffff8279e120 R uhci_device_isoc_methods +ffffffff8279e150 R uhci_devd +ffffffff8279e162 R uhci_confd +ffffffff8279e16b R uhci_ifcd +ffffffff8279e174 R uhci_endpd +ffffffff8279e17b R uhci_hubd_piix +ffffffff8279f000 R revbits +ffffffff8279f020 R ohci_bus_methods +ffffffff8279f050 R ohci_root_ctrl_methods +ffffffff8279f080 R ohci_root_intr_methods +ffffffff8279f0b0 R ohci_device_ctrl_methods +ffffffff8279f0e0 R ohci_device_intr_methods +ffffffff8279f110 R ohci_device_bulk_methods +ffffffff8279f140 R ohci_device_isoc_methods +ffffffff8279f170 R ohci_devd +ffffffff8279f182 R ohci_confd +ffffffff8279f18b R ohci_ifcd +ffffffff8279f194 R ohci_endpd +ffffffff8279f19b R ohci_hubd +ffffffff827a0000 R ehci_bus_methods +ffffffff827a0030 R ehci_root_ctrl_methods +ffffffff827a0060 R ehci_root_intr_methods +ffffffff827a0090 R ehci_device_ctrl_methods +ffffffff827a00c0 R ehci_device_intr_methods +ffffffff827a00f0 R ehci_device_bulk_methods +ffffffff827a0120 R ehci_device_isoc_methods +ffffffff827a0150 R ehci_devd +ffffffff827a0162 R ehci_odevd +ffffffff827a016c R ehci_confd +ffffffff827a0175 R ehci_ifcd +ffffffff827a017e R ehci_endpd +ffffffff827a0185 R ehci_hubd +ffffffff827a1000 R xhci_bus_methods +ffffffff827a1030 R xhci_root_ctrl_methods +ffffffff827a1060 R xhci_root_intr_methods +ffffffff827a1090 R xhci_device_ctrl_methods +ffffffff827a10c0 R xhci_device_intr_methods +ffffffff827a10f0 R xhci_device_bulk_methods +ffffffff827a1120 R xhci_device_isoc_methods +ffffffff827a1150 R xhci_devd +ffffffff827a1162 R xhci_confd +ffffffff827a116b R xhci_ifcd +ffffffff827a1174 R xhci_endpd +ffffffff827a117b R xhci_endpcd +ffffffff827a1181 R xhci_hubd +ffffffff827a4000 R radio_ca +ffffffff827a5000 R ipmi_ca +ffffffff827a6000 R vscsi_ca +ffffffff827a6028 R vscsi_switch +ffffffff827a6050 R vscsi_filtops +ffffffff827a7000 R mpath_ca +ffffffff827a7028 R mpath_switch +ffffffff827a8000 R softraid_ca +ffffffff827a8028 R sr_switch +ffffffff827a9000 r spdmem_basic_types +ffffffff827a90a0 r spdmem_parity_types +ffffffff827a90e0 r spdmem_ddr4_decode.ddr4_chipsize +ffffffff827aa000 R kstat_rlock_ops +ffffffff827aa010 R kstat_wlock_ops +ffffffff827aa020 R kstat_mutex_ops +ffffffff827aa030 R kstat_cpu_ops +ffffffff827aa040 r kstat_id_tree_RBT_INFO +ffffffff827aa058 R kstat_id_tree_RBT_TYPE +ffffffff827aa060 r kstat_pv_tree_RBT_INFO +ffffffff827aa078 R kstat_pv_tree_RBT_TYPE +ffffffff827aa080 r kstat_nm_tree_RBT_INFO +ffffffff827aa098 R kstat_nm_tree_RBT_TYPE +ffffffff827ab000 r fuse_rd_filtops +ffffffff827ac000 R fusefs_vfsops +ffffffff827ac070 R fusefs_vars +ffffffff827ad000 R fusefs_vops +ffffffff827ad110 R fusefsread_filtops +ffffffff827ad140 R fusefswrite_filtops +ffffffff827ad170 R fusefsvnode_filtops +ffffffff827ae000 r pf_state_tree_RBT_INFO +ffffffff827ae018 R pf_state_tree_RBT_TYPE +ffffffff827ae020 r pf_state_tree_id_RBT_INFO +ffffffff827ae038 R pf_state_tree_id_RBT_TYPE +ffffffff827ae040 r pf_translate_af.zero +ffffffff827af000 R hfsc_ops +ffffffff827af038 R ifq_hfsc_ops +ffffffff827af040 R hfsc_pf_ops +ffffffff827af088 R pfq_hfsc_ops +ffffffff827b0000 r fqcodel_ops +ffffffff827b0038 R ifq_fqcodel_ops +ffffffff827b0040 r fqcodel_pf_ops +ffffffff827b0088 R pfq_fqcodel_ops +ffffffff827b0090 r codel_intervals +ffffffff827b1000 r pfsync_bulk_req_state_names +ffffffff827b1030 r pfsync_bulk_req_event_names +ffffffff827b1060 r pfsync_qs +ffffffff827b10d8 r pfsync_kstat_tpl +ffffffff827b12e0 r pfsync_acts +ffffffff827b2000 r bio_mappings_RBT_INFO +ffffffff827b2018 R bio_mappings_RBT_TYPE +ffffffff827b3000 R hotplugread_filtops +ffffffff827b4000 R dtps_static +ffffffff827b5000 R db_show_all_cmds +ffffffff827b5180 R db_show_cmds +ffffffff827b54c0 R db_boot_cmds +ffffffff827b55a0 R db_command_table +ffffffff827b6000 R ddb_vars +ffffffff827b7000 R audio_ca +ffffffff827b7028 R audioctlread_filtops +ffffffff827b7058 R audiowrite_filtops +ffffffff827b7088 R audioread_filtops +ffffffff827b8000 R midi_ca +ffffffff827b8028 R midiwrite_filtops +ffffffff827b8058 R midiread_filtops +ffffffff827b9000 r mulawtolin16 +ffffffff827b9200 r lintomulaw +ffffffff827ba000 R randomread_filtops +ffffffff827ba030 R randomwrite_filtops +ffffffff827bb000 R video_ca +ffffffff827bb028 R video_filtops +ffffffff827bc000 R cd9660_vfsops +ffffffff827bd000 R cd9660_vops +ffffffff827bd110 R cd9660_specvops +ffffffff827bd220 R cd9660_fifovops +ffffffff827bd330 R cd9660read_filtops +ffffffff827bd360 R cd9660write_filtops +ffffffff827bd390 R cd9660vnode_filtops +ffffffff827be000 R udf_vfsops +ffffffff827bf000 R udf_vops +ffffffff827bf110 r mon_lens +ffffffff827c0000 r month_days +ffffffff827c1000 R execsw +ffffffff827c2000 r shstrtab +ffffffff827c3000 R copyright +ffffffff827c30c0 r initpaths +ffffffff827c4000 R sysent +ffffffff827c6000 R bufq_impls +ffffffff827c7000 R kqueueops +ffffffff827c7038 R kqread_filtops +ffffffff827c7068 R proc_filtops +ffffffff827c7098 R file_filtops +ffffffff827c70c8 R timer_filtops +ffffffff827c7100 R sysfilt_ops +ffffffff827c7148 R seltrue_filtops +ffffffff827c7178 R dead_filtops +ffffffff827c71a8 R badfd_filtops +ffffffff827c71d8 r mutex_klistops +ffffffff827c71f0 r rwlock_klistops +ffffffff827c8000 R kv_exec +ffffffff827c9000 R addrmask +ffffffff827ca000 r rw_ops +ffffffff827cb000 r proc_printit.pstat +ffffffff827cc000 R pledge_syscalls +ffffffff827cca60 r pledgenames +ffffffff827cccb0 r pledgereq +ffffffff827cd000 r unvname_rbt_RBT_INFO +ffffffff827cd018 R unvname_rbt_RBT_TYPE +ffffffff827ce000 R sig_filtops +ffffffff827ce030 R sigprop +ffffffff827cf000 R kern_vars +ffffffff827cf2f0 R hw_vars +ffffffff827d0000 R tc_vars +ffffffff827d1000 r sys_gettimeofday.zerotz +ffffffff827d2000 r taskq_sys_name +ffffffff827d2006 r taskq_sys_mp_name +ffffffff827d2010 R systq +ffffffff827d2018 R systqmp +ffffffff827d4000 r gpt_get_fstype.gpt_uuid_openbsd +ffffffff827d4010 r gpt_get_fstype.gpt_uuid_msdos +ffffffff827d4020 r gpt_get_fstype.gpt_uuid_chromerootfs +ffffffff827d4030 r gpt_get_fstype.gpt_uuid_linux +ffffffff827d4040 r gpt_get_fstype.gpt_uuid_hfs +ffffffff827d4050 r gpt_get_fstype.gpt_uuid_unused +ffffffff827d4060 r gpt_get_fstype.gpt_uuid_efi_system +ffffffff827d4070 r gpt_get_fstype.gpt_uuid_bios_boot +ffffffff827d5000 r hiballoc_addr_RBT_INFO +ffffffff827d5018 R hiballoc_addr_RBT_TYPE +ffffffff827d6000 R logread_filtops +ffffffff827d7000 r phtree_RBT_INFO +ffffffff827d7018 R phtree_RBT_TYPE +ffffffff827d7020 r pool_lock_ops_rw +ffffffff827d7058 r pool_lock_ops_mtx +ffffffff827d8000 r pselregister.evf +ffffffff827d800c r pselregister.evff +ffffffff827d9000 R pipe_rfiltops +ffffffff827d9030 R pipe_wfiltops +ffffffff827d9060 R pipe_efiltops +ffffffff827d9090 r pipeops +ffffffff827da000 R socketops +ffffffff827db000 R sysvsem_vars +ffffffff827dc000 R char_type +ffffffff827dc100 R ttyread_filtops +ffffffff827dc130 R ttywrite_filtops +ffffffff827dc160 R ttyexcept_filtops +ffffffff827dd000 R ptcread_filtops +ffffffff827dd030 R ptcwrite_filtops +ffffffff827dd060 R ptcexcept_filtops +ffffffff827df000 R domains +ffffffff827e0000 R unixdomain +ffffffff827e0050 R unixsw +ffffffff827e1000 R solisten_filtops +ffffffff827e1030 R soread_filtops +ffffffff827e1060 R sowrite_filtops +ffffffff827e1090 R soexcept_filtops +ffffffff827e10c0 R socket_klistops +ffffffff827e2000 R sun_noname +ffffffff827e2010 R uipc_usrreqs +ffffffff827e20b0 R uipc_dgram_usrreqs +ffffffff827e2150 R unpstctl_vars +ffffffff827e2180 R unpsqctl_vars +ffffffff827e21b0 R unpdgctl_vars +ffffffff827e3000 r namecache_rb_cache_RBT_INFO +ffffffff827e3018 R namecache_rb_cache_RBT_TYPE +ffffffff827e4000 R generic_filtops +ffffffff827e5000 r buf_rb_bufs_RBT_INFO +ffffffff827e5018 R buf_rb_bufs_RBT_TYPE +ffffffff827e5020 r typename +ffffffff827e6000 R sync_vops +ffffffff827e7000 R vnops +ffffffff827e8000 R spec_vops +ffffffff827e9000 R dead_vops +ffffffff827ea000 R fifo_vops +ffffffff827ea110 R fiforead_filtops +ffffffff827ea140 R fifowrite_filtops +ffffffff827ea170 R fifoexcept_filtops +ffffffff827eb000 R regyear +ffffffff827eb020 R leapyear +ffffffff827eb040 r dos2unix +ffffffff827eb140 r u2l +ffffffff827eb240 r unix2dos +ffffffff827ec008 R msdosfs_vfsops +ffffffff827ed000 R msdosfs_vops +ffffffff827ed110 R msdosfsread_filtops +ffffffff827ed140 R msdosfswrite_filtops +ffffffff827ed170 R msdosfsvnode_filtops +ffffffff827ee000 r _utf_count +ffffffff827ef000 R ntfs_vfsops +ffffffff827f0000 R ntfs_vops +ffffffff827f1000 R bpfread_filtops +ffffffff827f1030 R bpf_mbuf_ops +ffffffff827f2000 r bpf_mem_ops +ffffffff827f3000 R priq_ops +ffffffff827f3038 R ifq_priq_ops +ffffffff827f3040 r ifq_kstat_tpl +ffffffff827f3180 r ifiq_kstat_tpl +ffffffff827f4000 r ether_crc32_le_update.crctab +ffffffff827f4040 r ether_crc32_be_update.crctab +ffffffff827f5000 r lcp +ffffffff827f5078 r ipcp +ffffffff827f50f0 r ipv6cp +ffffffff827f5168 r chap +ffffffff827f51e0 r pap +ffffffff827f6000 R ifmedia_baudrate_descriptions +ffffffff827f7000 r fcstab +ffffffff827f9000 R tunread_filtops +ffffffff827f9030 R tunwrite_filtops +ffffffff827fa000 R bridge_brport +ffffffff827fb000 R bstp_etheraddr +ffffffff827fc000 r eb_tree_RBT_INFO +ffffffff827fc018 R eb_tree_RBT_TYPE +ffffffff827fd000 r veb_etherbridge_ops +ffffffff827fd028 r veb_pf_ipv4 +ffffffff827fd040 r veb_pf_ipv6 +ffffffff827fe000 r pipex_pppoe_padding +ffffffff827ff000 r rn_addmask.normal_chars +ffffffff82800000 R route_src +ffffffff82800010 R route_usrreqs +ffffffff828000b0 R routedomain +ffffffff82800100 R routesw +ffffffff82801000 R gre_vars +ffffffff82801030 r mgre_tree_RBT_INFO +ffffffff82801048 R mgre_tree_RBT_TYPE +ffffffff82801050 r egre_tree_RBT_INFO +ffffffff82801068 R egre_tree_RBT_TYPE +ffffffff82801070 r nvgre_ucast_tree_RBT_INFO +ffffffff82801088 R nvgre_ucast_tree_RBT_TYPE +ffffffff82801090 r nvgre_mcast_tree_RBT_INFO +ffffffff828010a8 R nvgre_mcast_tree_RBT_TYPE +ffffffff828010b0 r eoip_tree_RBT_INFO +ffffffff828010c8 R eoip_tree_RBT_TYPE +ffffffff828010d0 r nvgre_etherbridge_ops +ffffffff82802000 r trunk_protos +ffffffff82803000 R ethermulticastaddr_slowprotocols +ffffffff82803006 R lacp_info_tlv_template +ffffffff8280300e R marker_info_tlv_template +ffffffff82803012 R marker_response_tlv_template +ffffffff82803020 R lacp_timer_funcs +ffffffff82804000 r lacp_rxm_state_names +ffffffff82804040 r lacp_rxm_event_names +ffffffff82804090 r aggr_port_selected_names +ffffffff828040b0 r lacp_mux_state_names +ffffffff828040e0 r lacp_mux_event_names +ffffffff82804128 r lacp_address_slow +ffffffff82805000 r tpmr_pf_ipv4 +ffffffff82805018 r tpmr_pf_ipv6 +ffffffff82806000 r bpe_tree_RBT_INFO +ffffffff82806018 R bpe_tree_RBT_TYPE +ffffffff82806020 r bpe_etherbridge_ops +ffffffff82807000 R pppx_rd_filtops +ffffffff82807030 R pppx_wr_filtops +ffffffff82807060 r pppx_ifs_RBT_INFO +ffffffff82807078 R pppx_ifs_RBT_TYPE +ffffffff82807080 r pppac_rd_filtops +ffffffff828070b0 r pppac_wr_filtops +ffffffff82808000 r vxlan_peers_RBT_INFO +ffffffff82808018 R vxlan_peers_RBT_TYPE +ffffffff82808020 r vxlan_etherbridge_ops +ffffffff82809000 R stoeplitz_cache +ffffffff8280a000 R ieee80211_std_rateset_11a +ffffffff8280a010 R ieee80211_std_rateset_11b +ffffffff8280a020 R ieee80211_std_rateset_11g +ffffffff8280a030 R ieee80211_std_ratesets_11n +ffffffff8280a3b0 R ieee80211_std_ratesets_11ac +ffffffff8280a6b0 r ieee80211_setbasicrates.basic +ffffffff8280a710 r ieee80211_setmode.chanflags +ffffffff8280a730 r ieee80211_rate2media.rates +ffffffff8280a8c0 r ieee80211_media2rate.ieeerates +ffffffff8280b000 r Sbox +ffffffff8280d000 r ieee80211_ioctl.empty_macaddr +ffffffff8280e000 r ieee80211_find_rxnode.zero +ffffffff8280e008 r ieee80211_tree_RBT_INFO +ffffffff8280e020 R ieee80211_tree_RBT_TYPE +ffffffff8280e028 r ieee80211_ess_tree_RBT_INFO +ffffffff8280e040 R ieee80211_ess_tree_RBT_TYPE +ffffffff8280e048 r ieee80211_do_slow_print.merge_print_intvl +ffffffff8280f020 R ieee80211_edca_table +ffffffff8280f0e0 R ieee80211_qap_edca_table +ffffffff82810000 R ieee80211_mgt_subtype_name +ffffffff82810080 R ieee80211_state_name +ffffffff828100b0 R ieee80211_phymode_name +ffffffff82811000 r ieee80211_r_ctry +ffffffff82811ae0 r ieee80211_r_names +ffffffff82811f80 r ieee80211_r_map +ffffffff82813000 R zeroin46_addr +ffffffff82813010 R zeroin_addr +ffffffff82814000 R inetdomain +ffffffff82814050 R inetsw +ffffffff82815000 R divertctl_vars +ffffffff82815030 R divert_usrreqs +ffffffff82816000 R icmpctl_vars +ffffffff82817000 R ipctl_vars +ffffffff82817150 R inetctlerrmap +ffffffff82818000 R rip_usrreqs +ffffffff82819000 R tcp_timer_funcs +ffffffff8281a000 R tcp_usrreqs +ffffffff8281a0a0 R tcp6_usrreqs +ffffffff8281a140 R tcpctl_vars +ffffffff8281b000 R udp_usrreqs +ffffffff8281b0a0 R udp6_usrreqs +ffffffff8281b140 R udpctl_vars +ffffffff8281c000 R gre_usrreqs +ffffffff8281d000 r ipsec_ids_tree_RBT_INFO +ffffffff8281d018 R ipsec_ids_tree_RBT_TYPE +ffffffff8281d020 r ipsec_ids_flows_RBT_INFO +ffffffff8281d038 R ipsec_ids_flows_RBT_TYPE +ffffffff8281d040 R xformsw +ffffffff8281d158 R xformswNXFORMSW +ffffffff8281e000 R espctl_vars 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hmac_ipad_buffer +ffffffff8282d080 R hmac_opad_buffer +ffffffff8282e000 R enc_xform_3des +ffffffff8282e040 R enc_xform_blf +ffffffff8282e080 R enc_xform_cast5 +ffffffff8282e0c0 R enc_xform_aes +ffffffff8282e100 R enc_xform_aes_ctr +ffffffff8282e140 R enc_xform_aes_gcm +ffffffff8282e180 R enc_xform_aes_gmac +ffffffff8282e1c0 R enc_xform_aes_xts +ffffffff8282e200 R enc_xform_chacha20_poly1305 +ffffffff8282e240 R enc_xform_null +ffffffff8282e280 R auth_hash_hmac_md5_96 +ffffffff8282e2c8 R auth_hash_hmac_sha1_96 +ffffffff8282e310 R auth_hash_hmac_ripemd_160_96 +ffffffff8282e358 R auth_hash_hmac_sha2_256_128 +ffffffff8282e3a0 R auth_hash_hmac_sha2_384_192 +ffffffff8282e3e8 R auth_hash_hmac_sha2_512_256 +ffffffff8282e430 R auth_hash_gmac_aes_128 +ffffffff8282e478 R auth_hash_gmac_aes_192 +ffffffff8282e4c0 R auth_hash_gmac_aes_256 +ffffffff8282e508 R auth_hash_chacha20_poly1305 +ffffffff8282e550 R comp_algo_deflate +ffffffff8282f000 r IV +ffffffff82830000 r idgen32_ftable +ffffffff82831000 r Chacha20_Poly1305_Update.zeroes +ffffffff82831010 r pad0 +ffffffff82832000 r null_point +ffffffff82832020 r base_point +ffffffff82833000 R mplsdomain +ffffffff82834000 R mplsctl_vars +ffffffff82835000 r nfs_nodetree_RBT_INFO +ffffffff82835018 R nfs_nodetree_RBT_TYPE +ffffffff82836000 r nfsread_filtops +ffffffff82836030 r nfswrite_filtops +ffffffff82836060 r nfsvnode_filtops +ffffffff82837000 r nfsrv_v3errmap +ffffffff828370b0 r nfsrv_v2errmap +ffffffff82838000 R nfs_vfsops +ffffffff82839000 R nfs_vops +ffffffff82839110 R nfs_specvops +ffffffff82839220 R nfs_fifovops +ffffffff8283a000 r fserr_interval +ffffffff8283b000 R around +ffffffff8283b030 R inside +ffffffff8283b060 R fragtbl124 +ffffffff8283b160 R fragtbl8 +ffffffff8283c000 R ffs_vfsops +ffffffff8283c070 R sbtry +ffffffff8283c080 R ffs_vars +ffffffff8283d000 R ffs_vops +ffffffff8283d110 R ffs_specvops +ffffffff8283d220 R ffs_fifovops +ffffffff8283f000 R mfs_vfsops +ffffffff82840000 R mfs_vops +ffffffff82841000 r quotatypes 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kd_nowait +ffffffff82849190 R kd_trylock +ffffffff8284a000 R vmmapbsy +ffffffff8284a010 r page_flagbits +ffffffff8284a0a8 r uvm_map_addr_RBT_INFO +ffffffff8284a0c0 R uvm_map_addr_RBT_TYPE +ffffffff8284b000 R pmap_pager +ffffffff8284b048 R bufcache_pager +ffffffff8284c000 r uvm_objtree_RBT_INFO +ffffffff8284c018 R uvm_objtree_RBT_TYPE +ffffffff8284d000 r uvm_pmr_addr_RBT_INFO +ffffffff8284d018 R uvm_pmr_addr_RBT_TYPE +ffffffff8284d020 r uvm_pmr_size_RBT_INFO +ffffffff8284d038 R uvm_pmr_size_RBT_TYPE +ffffffff8284d040 r uvm_pmemrange_addr_RBT_INFO +ffffffff8284d058 R uvm_pmemrange_addr_RBT_TYPE +ffffffff8284e000 R uvm_vnodeops +ffffffff8284e048 r uvn_flush.interval +ffffffff8284f000 R zeroin6_addr +ffffffff82850000 R in6addr_any +ffffffff82850010 R in6addr_loopback +ffffffff82850020 R in6addr_intfacelocal_allnodes +ffffffff82850030 R in6addr_linklocal_allnodes +ffffffff82850040 R in6addr_linklocal_allrouters +ffffffff82850050 R in6mask0 +ffffffff82850060 R in6mask32 +ffffffff82850070 R in6mask64 +ffffffff82850080 R in6mask96 +ffffffff82850090 R in6mask128 +ffffffff828500a0 R sa6_any +ffffffff82851000 R divert6ctl_vars +ffffffff82851030 R divert6_usrreqs +ffffffff82852000 R inet6domain +ffffffff82852050 R inet6sw +ffffffff82853000 R icmpv6ctl_vars +ffffffff82854000 R inet6ctlerrmap +ffffffff82854020 R ipv6ctl_vars +ffffffff82855000 R rip6_usrreqs +ffffffff82856000 R pfkey_addr +ffffffff82856010 R pfkeyv2_usrreqs +ffffffff828560b0 R pfkeydomain +ffffffff82856100 R pfkeysw +ffffffff82856160 r ealgs +ffffffff82856190 r aalgs +ffffffff828561c0 r calgs +ffffffff82857000 R sadb_exts_allowed_out +ffffffff82857090 R sadb_exts_required_out +ffffffff82859000 r opc82_byte_operation +ffffffff82859040 r opc83_long_operation +ffffffff82859080 r opc83_word_operation +ffffffff828590c0 r opcD0_byte_operation +ffffffff82859100 r opcD1_long_operation +ffffffff82859140 r opcD1_word_operation +ffffffff8285a000 r crc_table +ffffffff8285a400 r crc_braid_table +ffffffff8285c400 r x2n_table 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cpuctl_vars +ffffffff82867000 R cpu_cpuid_features +ffffffff828671d0 R cpu_ecpuid_features +ffffffff82867260 R cpu_cpuid_ecxfeatures +ffffffff82867450 R cpu_ecpuid_ecxfeatures +ffffffff828675d0 R cpu_seff0_ebxfeatures +ffffffff828677a0 R cpu_seff0_ecxfeatures +ffffffff82867800 R cpu_seff0_edxfeatures +ffffffff828678a0 R cpu_tpm_eaxfeatures +ffffffff828678c0 R cpu_cpuid_perf_eax +ffffffff828678d0 R cpu_cpuid_apmi_edx +ffffffff828678f0 R cpu_amdspec_ebxfeatures +ffffffff828679a0 R cpu_xsave_extfeatures +ffffffff828679f0 R cpu_arch_cap_features +ffffffff82868000 R sigcode +ffffffff82868014 R sigcodecall +ffffffff82868016 R sigcoderet +ffffffff82868038 R esigcode +ffffffff82868038 R sigfill +ffffffff82868039 R sigfillsiz +ffffffff82868039 r esigfill +ffffffff8286803d r bogus_proc_pmap +ffffffff82868070 r spl_lowered +ffffffff828680a6 r intr_spl_lowered +ffffffff82868113 R _xrstor +ffffffff82868117 R _xrstors +ffffffff8286811b R _xsave +ffffffff8286811f R _xsaves +ffffffff82868123 R _xsaveopt +ffffffff82868127 R _pcid_set_reuse +ffffffff82868133 R _jmprax +ffffffff82868136 R _jmprax_len +ffffffff82868138 R _jmpr11 +ffffffff8286813c R _jmpr11_len +ffffffff8286813e R _jmpr13 +ffffffff82868142 R _jmpr13_len +ffffffff8286a000 r cpurevs +ffffffff8286a16c r amd64_errata_set5 +ffffffff8286a16e r amd64_errata_set1 +ffffffff8286a180 r amd64_errata_set8 +ffffffff8286a19f r amd64_errata_set6 +ffffffff8286a1a4 r amd64_errata_set7 +ffffffff8286a1ac r amd64_errata_set3 +ffffffff8286a1af r amd64_errata_set2 +ffffffff8286a1b8 r amd64_errata_set9 +ffffffff8286b000 R ptp_masks +ffffffff8286b020 R ptp_shifts +ffffffff8286b030 R nkptpmax +ffffffff8286b050 R nbpd +ffffffff8286b070 R normal_pdes +ffffffff8286c000 R trap_type +ffffffff8286c0b0 R trap_types +ffffffff8286d000 r x86fpflags_to_siginfo.x86fp_siginfo_table +ffffffff8286e000 R x86_soft_intr_to_ssir +ffffffff82870000 R Xexceptions +ffffffff82870100 r spl_lowered +ffffffff8287012d R i8259_stubs +ffffffff828702ad R ioapic_edge_stubs +ffffffff828708ad R ioapic_level_stubs +ffffffff82871000 R _stac +ffffffff82871003 R _clac +ffffffff82872000 R x86_bus_space_io_ops +ffffffff82872130 R x86_bus_space_mem_ops +ffffffff82873000 ? cpu_spinup_trampoline +ffffffff828730b6 R cpu_spinup_trampoline_end +ffffffff828730b6 R mp_tramp_data_start +ffffffff828730fc R mp_tramp_data_end +ffffffff82875000 R db_acpi_cmds +ffffffff828750a0 R db_machine_command_table +ffffffff82876000 r i8254_delay.delaytab +ffffffff82877000 R rasops_cmap +ffffffff82878000 r reverse +ffffffff82878100 r ibm437_level1 +ffffffff82878230 r ibm437_level2_0 +ffffffff82878248 r ibm437_level2_1 +ffffffff82878260 r ibm437_level2_3 +ffffffff82878278 r ibm437_level2_32 +ffffffff82878290 r ibm437_level2_34 +ffffffff828782a8 r ibm437_level2_35 +ffffffff828782c0 r ibm437_level2_37 +ffffffff828782e0 r ibm437_chars_0 +ffffffff828783e0 r ibm437_chars_1 +ffffffff828783f0 r ibm437_chars_3 +ffffffff82878430 r ibm437_chars_32 +ffffffff82878460 r ibm437_chars_34 +ffffffff828784d0 r ibm437_chars_35 +ffffffff828784f0 r ibm437_chars_37 +ffffffff82879000 R mii_media_table +ffffffff8287a000 R nsphy_ca +ffffffff8287a028 R nsphy_funcs +ffffffff8287a040 r nsphys +ffffffff8287b000 R nsphyter_ca +ffffffff8287b028 R nsphyter_funcs +ffffffff8287b040 r nsphyterphys +ffffffff8287c000 R gentbi_ca +ffffffff8287c028 R gentbi_funcs +ffffffff8287d000 R qsphy_ca +ffffffff8287d028 R qsphy_funcs +ffffffff8287d040 r qsphys +ffffffff8287e000 R inphy_ca +ffffffff8287e028 R inphy_funcs +ffffffff8287e040 r inphys +ffffffff8287f000 R iophy_ca +ffffffff8287f028 R iophy_funcs +ffffffff8287f040 r iophys +ffffffff82880000 R eephy_ca +ffffffff82880028 R eephy_funcs +ffffffff82880040 r eephys +ffffffff82881000 R exphy_ca +ffffffff82881028 R exphy_funcs +ffffffff82882000 R rlphy_ca +ffffffff82882028 R rlphy_funcs +ffffffff82882040 r rlphys +ffffffff82883000 R lxtphy_ca +ffffffff82883028 R lxtphy_funcs +ffffffff82883040 R lxtphy971_funcs +ffffffff82883060 r lxtphys +ffffffff82884000 R luphy_ca +ffffffff82884028 R luphy_funcs +ffffffff82884040 r luphys +ffffffff82885000 R mtdphy_ca +ffffffff82885028 R mtdphy_funcs +ffffffff82885040 r mtdphys +ffffffff82886000 R icsphy_ca +ffffffff82886028 R icsphy_funcs +ffffffff82886040 r icsphys +ffffffff82887000 R sqphy_ca +ffffffff82887028 R sqphy_funcs +ffffffff82887040 r sqphys +ffffffff82888000 R tqphy_ca +ffffffff82888028 R tqphy_funcs +ffffffff82888040 r tqphys +ffffffff82889000 R ukphy_ca +ffffffff82889028 R ukphy_funcs +ffffffff8288a000 R dcphy_ca +ffffffff8288a028 R dcphy_funcs +ffffffff8288b000 R bmtphy_ca +ffffffff8288b028 R bmtphy_funcs +ffffffff8288b040 r bmtphys +ffffffff8288c000 R brgphy_ca +ffffffff8288c028 R brgphy_copper_funcs +ffffffff8288c040 R brgphy_fiber_funcs +ffffffff8288c058 R brgphy_5708s_funcs +ffffffff8288c070 R brgphy_5709s_funcs +ffffffff8288c090 r brgphys +ffffffff8288c300 r brgphy_bcm5401_dspcode.dspcode +ffffffff8288d000 R xmphy_ca +ffffffff8288d028 R xmphy_funcs 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R scsi_readsafe_cmd +ffffffff8289c000 R scsibus_ca +ffffffff8289c030 R scsi_quirk_patterns +ffffffff8289d000 R cd_ca +ffffffff8289d030 R cd_patterns +ffffffff8289e000 R ch_ca +ffffffff8289e030 R ch_patterns +ffffffff8289f000 R sd_ca +ffffffff8289f030 R sd_patterns +ffffffff828a0000 R st_quirk_patterns +ffffffff828a0210 R st_ca +ffffffff828a0240 R st_patterns +ffffffff828a1000 R uk_ca +ffffffff828a2000 R safte_ca +ffffffff828a3000 R ses_ca +ffffffff828a4000 R sym_ca +ffffffff828a4028 R sym_mpath_sym_ops +ffffffff828a4048 R sym_mpath_asym_ops +ffffffff828a5000 R rdac_ca +ffffffff828a5028 R rdac_mpath_ops +ffffffff828a6000 R emc_ca +ffffffff828a6028 R emc_mpath_ops +ffffffff828a7000 R hds_ca +ffffffff828a7028 R hds_mpath_ops +ffffffff828a8000 R atapiscsi_ca +ffffffff828a8028 r atapiscsi_switch +ffffffff828a9000 R wd_ca +ffffffff828aa000 R atascsi_switch +ffffffff828ab000 R mainbus_ca +ffffffff828ac000 R bios_ca +ffffffff828ad000 R mpbios_ca +ffffffff828ad030 r loc_where +ffffffff828ae000 R mpbios_icu_table +ffffffff828af000 R cpu_ca +ffffffff828b0000 R lapic_timer_intrclock +ffffffff828b1000 R ioapic_ca +ffffffff828b2000 R efifb_ca +ffffffff828b2028 R efifb_screen_list +ffffffff828b3000 R pvbus_ca +ffffffff828b4000 R pvclock_ca +ffffffff828b5000 R vmt_ca +ffffffff828b6000 R xen_ca +ffffffff828b7000 R xs_errors +ffffffff828b8000 R xnf_ca +ffffffff828b9000 R xbf_ca +ffffffff828b9028 R xbf_switch +ffffffff828ba000 R hyperv_ca +ffffffff828ba028 R hv_guid_network +ffffffff828ba038 R hv_guid_ide +ffffffff828ba048 R hv_guid_scsi +ffffffff828ba058 R hv_guid_shutdown +ffffffff828ba068 R hv_guid_timesync +ffffffff828ba078 R hv_guid_heartbeat +ffffffff828ba088 R hv_guid_kvp +ffffffff828bb000 r kvp_pools +ffffffff828bc000 R hvn_ca +ffffffff828bd000 R hvs_ca +ffffffff828bd028 R hvs_switch +ffffffff828be000 r virtio_device_name +ffffffff828bf000 R vio_ca +ffffffff828bf030 r virtio_net_feature_names +ffffffff828c0000 R vioblk_ca +ffffffff828c0028 R vioblk_switch +ffffffff828c1000 R viomb_ca +ffffffff828c1030 r viomb_feature_names +ffffffff828c2000 R viornd_ca +ffffffff828c3000 R vioscsi_ca +ffffffff828c3028 R vioscsi_switch +ffffffff828c3050 R vioscsi_vq_names +ffffffff828c4000 R vmmci_ca +ffffffff828c5000 R pci_ca +ffffffff828c6000 r pci_quirks +ffffffff828c7000 R pci_subclass_prehistoric +ffffffff828c7050 R pci_subclass_mass_storage +ffffffff828c7160 R pci_subclass_network +ffffffff828c7250 R pci_subclass_display +ffffffff828c72d0 R pci_subclass_multimedia +ffffffff828c7360 R pci_subclass_memory +ffffffff828c73c0 R pci_subclass_bridge +ffffffff828c7510 R pci_subclass_communications +ffffffff828c75d0 R pci_subclass_system +ffffffff828c76c0 R pci_subclass_input +ffffffff828c7770 R pci_subclass_dock +ffffffff828c77c0 R pci_subclass_processor +ffffffff828c7880 R pci_subclass_serialbus +ffffffff828c7990 R pci_subclass_wireless +ffffffff828c7a70 R pci_subclass_i2o +ffffffff828c7aa0 R pci_subclass_satcom +ffffffff828c7b20 R pci_subclass_crypto +ffffffff828c7b80 R pci_subclass_dasp +ffffffff828c7c10 R pci_class +ffffffff828c7e20 r pci_known_vendors +ffffffff828c93e0 r pci_known_products +ffffffff828ec000 R vga_pci_ca +ffffffff828ec030 r vga_devs +ffffffff828ed000 R ahc_pci_ident_table +ffffffff828ed5d0 R ahc_pci_ca +ffffffff828ee000 R ahd_pci_ident_table +ffffffff828ee198 R ahd_num_pci_devs +ffffffff828ee1a0 R ahd_pci_ca +ffffffff828ee1d0 r pci_bus_modes +ffffffff828ee210 r pci_status_strings +ffffffff828ee250 r pci_status_source +ffffffff828ee290 r split_status_strings +ffffffff828ef000 R adw_pci_ca +ffffffff828ef028 R adw_pci_devices +ffffffff828f0000 r adw_3550_Default_EEPROM +ffffffff828f0080 r adw_38C0800_Default_EEPROM +ffffffff828f0100 r adw_38C1600_Default_EEPROM +ffffffff828f1000 R adw_asc3550_mcode +ffffffff828f23a0 R adw_asc3550_mcode_data +ffffffff828f23b0 R adw_asc38C0800_mcode +ffffffff828f3888 R adw_asc38C0800_mcode_data +ffffffff828f38a0 R adw_asc38C1600_mcode +ffffffff828f5160 R adw_asc38C1600_mcode_data +ffffffff828f6000 R twe_pci_ca +ffffffff828f6028 R twe_pci_devices +ffffffff828f7000 R arc_ca +ffffffff828f7028 R arc_switch +ffffffff828f7050 r arc_devices +ffffffff828f7190 r arc_intel +ffffffff828f7198 r arc_marvell +ffffffff828f71a0 r arc_lsi +ffffffff828f71a8 r arc_marvell2 +ffffffff828f8000 R jmb_ca +ffffffff828f8030 r jmb_devices +ffffffff828f9000 R ahci_pci_ca +ffffffff828f9028 R ahci_jmb_ca +ffffffff828f9050 r ahci_devices +ffffffff828fa000 R nvme_pci_ca +ffffffff828fa028 r nvme_msi_blacklist +ffffffff828fb000 R ami_pci_ca +ffffffff828fb030 r ami_pci_subsys +ffffffff828fb270 r ami_pci_vendors +ffffffff828fc000 R mfi_pci_ca +ffffffff828fc030 r mfi_pci_devices +ffffffff828fd000 R mfii_ca +ffffffff828fd028 R mfii_switch +ffffffff828fd050 R mfii_pd_switch +ffffffff828fd078 R mfii_iop_thunderbolt +ffffffff828fd088 R mfii_iop_25 +ffffffff828fd098 R mfii_iop_35 +ffffffff828fd0b0 R mfii_devices +ffffffff828fd140 r mfi_bbu_indicators +ffffffff828fe000 R ips_ca +ffffffff828fe028 r ips_ids +ffffffff828fe040 r ips_chips +ffffffff828fe090 r ips_names +ffffffff828fe128 r ips_switch +ffffffff828fe150 r ips_pt_switch +ffffffff828ff000 R eap_ca +ffffffff828ff028 R eap1370_hw_if +ffffffff828ff0e0 R eap1371_hw_if +ffffffff828ff198 R eap_midi_hw_if +ffffffff828ff1d0 R eap_devices +ffffffff82900000 R auacer_pci_devices +ffffffff82900008 R auacer_ca +ffffffff82900030 R auacer_hw_if +ffffffff82901000 R auich_ca +ffffffff82901028 R auich_hw_if +ffffffff829010e0 r auich_devices +ffffffff82902000 R azalia_ca +ffffffff82902028 R azalia_hw_if +ffffffff829020e0 R azalia_pci_devices +ffffffff82902120 r pin_devices +ffffffff829021a0 r line_colors +ffffffff82902220 r wtypes +ffffffff82903000 r azalia_codec_init_dolby_atmos.atmos_init +ffffffff82903050 r azalia_codec_init_dolby_atmos.atmos_v23_v25 +ffffffff82904000 R envy_ca +ffffffff82904028 R envy_hw_if +ffffffff829040e0 R envy_midi_hw_if +ffffffff82905000 R emuxki_devices +ffffffff82905010 R emu_ca +ffffffff82905038 R emuxki_hw_if +ffffffff829050f0 r emuxki_recbuf_sz +ffffffff82905170 r emuxki_recsrc_szreg +ffffffff8290517c r emuxki_recsrc_bufaddrreg +ffffffff82905190 r emuxki_rate_to_pitch.logMagTable +ffffffff82905390 r emuxki_rate_to_pitch.logSlopeTable +ffffffff82906000 R auixp_pci_devices +ffffffff82906010 R auixp_ca +ffffffff82906038 R auixp_hw_if +ffffffff82907000 R clcs_ca +ffffffff82907028 R cs4280_hw_if +ffffffff829070e0 R cs4280_devices +ffffffff82908000 R yds_ca +ffffffff82908028 r yds_hw_if +ffffffff829080e0 r yds_chip_capability_list +ffffffff82908120 r yds_get_lpfk.lpfkt +ffffffff82908160 r yds_get_lpfq.lpfqt +ffffffff82909000 R auvia_ca +ffffffff82909028 R auvia_hw_if +ffffffff829090e0 R auvia_devices +ffffffff829090f0 r auvia_set_params_sub.slottab +ffffffff8290a000 R gdt_pci_ca +ffffffff8290b000 R ciss_pci_ca +ffffffff8290b030 R ciss_pci_devices +ffffffff8290c000 R qlw_pci_ca +ffffffff8290c030 r qlw_devices +ffffffff8290c050 r isp_1040_risc_code +ffffffff829119f0 r isp_1080_risc_code +ffffffff82919470 r isp_12160_risc_code +ffffffff82921000 R qla_pci_ca +ffffffff82921030 r qla_devices +ffffffff82922000 R qle_ca +ffffffff82922028 R qle_switch +ffffffff82922050 r qle_devices +ffffffff82922070 r isp_2400_risc_code +ffffffff82951a50 r isp_2500_risc_code +ffffffff82984000 R mpi_pci_ca +ffffffff82984030 r mpi_devices +ffffffff82985000 R mpii_ca +ffffffff82985028 R mpii_switch +ffffffff82985050 r mpii_devices +ffffffff82986000 R sili_pci_ca +ffffffff82986030 r sili_devices +ffffffff82987000 R aq_devices +ffffffff82987060 R aq_products +ffffffff829871d0 R aq_fw1x_ops +ffffffff829871f8 R aq_fw2x_ops +ffffffff82987220 R aq2_fw_ops +ffffffff82987248 R aq_ca +ffffffff82988000 R de_ca +ffffffff82988030 r tulip_srom_conninfo +ffffffff82988120 r tulip_mii_phy_attrlist +ffffffff829881e0 r tulip_21140_znyx_zx34x_boardsw +ffffffff82988208 r tulip_21040_10baset_only_boardsw +ffffffff82988230 r tulip_21040_boardsw +ffffffff82988258 r tulip_2114x_isv_boardsw +ffffffff82988280 r tulip_21140_smc9332_boardsw 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R rdcide_udmaclk +ffffffff8298d028 R default_product_desc +ffffffff8298d040 R pciide_intel_products +ffffffff8298d630 R pciide_amd_products +ffffffff8298d690 R pciide_cmd_products +ffffffff8298d730 R pciide_via_products +ffffffff8298d810 R pciide_cypress_products +ffffffff8298d820 R pciide_sis_products +ffffffff8298d870 R pciide_natsemi_products +ffffffff8298d890 R pciide_acer_products +ffffffff8298d8a0 R pciide_triones_products +ffffffff8298d8f0 R pciide_promise_products +ffffffff8298dac0 R pciide_acard_products +ffffffff8298db10 R pciide_serverworks_products +ffffffff8298dbb0 R pciide_nvidia_products +ffffffff8298de80 R pciide_ite_products +ffffffff8298dea0 R pciide_ati_products +ffffffff8298df20 R pciide_jmicron_products +ffffffff8298df70 R pciide_phison_products +ffffffff8298df80 R pciide_rdc_products +ffffffff8298df90 R pciide_vendors +ffffffff8298e140 R pciide_pci_ca +ffffffff8298e168 R pciide_jmb_ca +ffffffff8298e190 r piix_isp_dma +ffffffff8298e193 r piix_rtc_dma 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cy_pci_ca +ffffffff82990030 R cy_pci_devices +ffffffff82991000 R rl_pci_ca +ffffffff82991030 R rl_pci_devices +ffffffff82992000 R re_pci_devices +ffffffff82992030 R re_pci_ca +ffffffff82993000 R vr_ca +ffffffff82994000 R txp_ca +ffffffff82994030 R txp_devices +ffffffff82995000 r cards +ffffffff82996000 r format_params +ffffffff829961a0 r pixfmt_table +ffffffff82996320 r meteor_pixfmt_table +ffffffff82997000 R bktr_ca +ffffffff82997028 R bktr_hw_if +ffffffff82998000 r tuners +ffffffff82998170 r freqTable +ffffffff82998260 r nabcst +ffffffff829982a0 r irccable +ffffffff82998310 r hrccable +ffffffff82998380 r weurope +ffffffff82998420 r jpnbcst +ffffffff82998460 r jpncable +ffffffff829984c0 r xussr +ffffffff82998530 r australia +ffffffff82998590 r france +ffffffff82999000 R xl_pci_ca +ffffffff82999030 R xl_pci_devices +ffffffff8299a000 R fxp_pci_ca +ffffffff8299a030 R fxp_pci_devices +ffffffff8299b000 R em_devices +ffffffff8299b308 R em_ca +ffffffff8299b330 r em_counters +ffffffff8299c000 r em_igp_cable_length_table +ffffffff8299c100 r em_igp_2_cable_length_table +ffffffff8299d000 R ixgb_devices +ffffffff8299d010 R ixgb_ca +ffffffff8299e000 R ixgbe_devices +ffffffff8299e0b8 R ix_ca +ffffffff8299e0e0 r ix_counters +ffffffff8299e3e0 r ix_rxq_kstats_tpl +ffffffff8299e458 r ix_txq_kstats_tpl +ffffffff8299f000 r ixgbe_mvals_base +ffffffff8299f060 r ixgbe_mvals_X540 +ffffffff8299f0c0 r ixgbe_mvals_X550 +ffffffff8299f120 r ixgbe_mvals_X550EM_x +ffffffff8299f180 r ixgbe_mvals_X550EM_a +ffffffff829a2000 R ixl_ca +ffffffff829a2030 R ixl_port_counters +ffffffff829a22c0 R ixl_vsi_counters +ffffffff829a2380 r ixl_devices +ffffffff829a24c0 r ixl_710 +ffffffff829a24e8 r ixl_722 +ffffffff829a2510 r ixl_pf_aq_regs +ffffffff829a2578 r ixl_710_decrepit +ffffffff829a25a0 r ixl_phy_type_map +ffffffff829a2770 r ixl_speed_type_map +ffffffff829a27b0 r ixl_hmc_pack_rxq +ffffffff829a2830 r ixl_hmc_pack_txq +ffffffff829a28a0 r ixl_sfp_ops +ffffffff829a28b8 r ixl_qsfp_ops +ffffffff829a3000 r dwqe_pci_devices +ffffffff829a3018 R dwqe_pci_ca +ffffffff829a4000 R xge_ca +ffffffff829a4028 R xge_devices +ffffffff829a4030 r xge_fix_mac +ffffffff829a4110 r xge_xena_dtx_cfg +ffffffff829a4170 r xge_herc_dtx_cfg +ffffffff829a5000 R thtc_ca +ffffffff829a5028 R tht_ca +ffffffff829a5050 r thtc_devices +ffffffff829a5068 r tht_link_state.interval +ffffffff829a6000 R myx_ca +ffffffff829a6028 R myx_devices +ffffffff829a7000 R oce_ca +ffffffff829a7030 R oce_devices +ffffffff829a8000 R dc_pci_ca +ffffffff829a9000 R epic_pci_ca +ffffffff829a9028 R epic_pci_devices +ffffffff829aa000 R ti_pci_ca +ffffffff829aa030 R ti_devices +ffffffff829ab000 R ne_pci_ca +ffffffff829ab030 R ne_pci_prod +ffffffff829ac000 R gem_pci_ca +ffffffff829ac030 R gem_pci_devices +ffffffff829ac050 r gem_promhdr +ffffffff829ac052 r gem_promdat +ffffffff829ac05a r gem_promdat2 +ffffffff829ad000 R cas_ca +ffffffff829ad028 R cas_pci_devices +ffffffff829ad030 r cas_promhdr +ffffffff829ad032 r cas_promdat_sun +ffffffff829ad03a r cas_promdat_ns +ffffffff829ad042 r cas_promdat2 +ffffffff829ae000 R sf_pci_ca +ffffffff829ae028 R sf_pci_products +ffffffff829af000 R sis_ca +ffffffff829af028 R sis_devices +ffffffff829b0000 R se_devices +ffffffff829b0008 R se_ca +ffffffff829b1000 R mbg_ca +ffffffff829b1030 R mbg_devices +ffffffff829b2000 R uhci_pci_ca +ffffffff829b3000 R ohci_pci_ca +ffffffff829b4000 R ehci_pci_ca +ffffffff829b5000 R xhci_pci_ca +ffffffff829b6000 R cbb_pci_ca +ffffffff829b6028 r pccbb_pcmcia_do_io_map.pcic_iowidth +ffffffff829b7000 R skc_devices +ffffffff829b7030 R skc_ca +ffffffff829b7058 R sk_ca +ffffffff829b8000 R mskc_devices +ffffffff829b80a8 R mskc_ca +ffffffff829b80d0 R msk_ca +ffffffff829b8100 r msk_mib +ffffffff829b9000 R puc_pci_ca +ffffffff829ba000 R puc_devs +ffffffff829bf000 R com_puc_ca +ffffffff829bf030 r puc_port_types +ffffffff829c0000 R lpt_puc_ca +ffffffff829c1000 R wi_pci_ca +ffffffff829c1030 r wi_pci_products +ffffffff829c2000 R an_pci_ca +ffffffff829c2030 R an_pci_devices +ffffffff829c3000 R iwi_devices +ffffffff829c3010 R iwi_ca +ffffffff829c4000 R wpi_ca +ffffffff829c4028 r wpi_devices +ffffffff829c4030 r wpi_rates +ffffffff829c4050 r wpi_rf_gain_5ghz +ffffffff829c40a0 r wpi_dsp_gain_5ghz +ffffffff829c40f0 r wpi_rf_gain_2ghz +ffffffff829c4140 r wpi_dsp_gain_2ghz +ffffffff829c4190 r wpi_pmgt +ffffffff829c4310 r wpi_bands +ffffffff829c5000 R iwn_mcs2ridx +ffffffff829c5020 R iwn_ca +ffffffff829c5050 r iwn_devices +ffffffff829c50e8 r iwn4965_sensitivity_limits +ffffffff829c5124 r iwn5000_sensitivity_limits +ffffffff829c5160 r iwn5150_sensitivity_limits +ffffffff829c519c r iwn1000_sensitivity_limits +ffffffff829c51d8 r iwn6000_sensitivity_limits +ffffffff829c5214 r iwn2000_sensitivity_limits +ffffffff829c5250 r iwn_fw_errmsg +ffffffff829c5340 r iwn4965_set_txpower.tdiv +ffffffff829c5360 r iwn4965_rf_gain_5ghz +ffffffff829c53d0 r iwn4965_dsp_gain_5ghz +ffffffff829c5440 r iwn4965_dsp_gain_2ghz +ffffffff829c54b0 r iwn_pmgt +ffffffff829c56f0 r iwn4965_post_alive.qid2fifo +ffffffff829c5700 r iwn_bands +ffffffff829c5770 r iwn_rates +ffffffff829c5820 r iwn4965_rf_gain_2ghz +ffffffff829c6000 R iwm_nvm_channels +ffffffff829c6030 R iwm_nvm_channels_8000 +ffffffff829c6070 R iwm_rates +ffffffff829c60d0 R iwm_ht_mcs2ridx +ffffffff829c6110 R iwm_tid_to_ac +ffffffff829c6118 R iwm_ac_to_tx_fifo +ffffffff829c6120 R iwm_nvm_to_read +ffffffff829c6144 r iwm_set_hw_address_8000.reserved_mac +ffffffff829c6180 r iwm_sf_full_timeout +ffffffff829c61b0 r iwm_sf_full_timeout_def +ffffffff829c61e0 r advanced_lookup +ffffffff829c6320 r iwm_devices +ffffffff829c6360 R iwm_ca +ffffffff829c7000 R iwx_9560_quz_a0_jf_b0_cfg +ffffffff829c7020 R iwx_9560_qu_c0_jf_b0_cfg +ffffffff829c7040 R iwx_qu_b0_hr1_b0 +ffffffff829c7060 R iwx_qu_b0_hr_b0 +ffffffff829c7080 R iwx_ax201_cfg_qu_hr +ffffffff829c70a0 R iwx_qu_c0_hr1_b0 +ffffffff829c70c0 R iwx_qu_c0_hr_b0 +ffffffff829c70e0 R iwx_ax201_cfg_qu_c0_hr_b0 +ffffffff829c7100 R iwx_quz_a0_hr1_b0 +ffffffff829c7120 R iwx_ax201_cfg_quz_hr +ffffffff829c7140 R iwx_cfg_so_a0_hr_b0 +ffffffff829c7160 R iwx_cfg_quz_a0_hr_b0 +ffffffff829c7180 R iwx_2ax_cfg_so_gf_a0 +ffffffff829c71a0 R iwx_2ax_cfg_so_gf_a0_long +ffffffff829c71c0 R iwx_2ax_cfg_so_gf4_a0 +ffffffff829c71e0 R iwx_2ax_cfg_so_gf4_a0_long +ffffffff829c7200 R iwx_2ax_cfg_ty_gf_a0 +ffffffff829c7220 R iwx_2ax_cfg_so_jf_b0 +ffffffff829c7240 R iwx_nvm_channels_8000 +ffffffff829c7280 R iwx_rates +ffffffff829c72e0 R iwx_mcs2ridx +ffffffff829c7320 R iwx_tid_to_ac +ffffffff829c7328 R iwx_ac_to_tx_fifo +ffffffff829c7330 r iwx_nvm_channels_uhb +ffffffff829c739e r iwx_is_valid_mac_addr.reserved_mac +ffffffff829c73b0 r iwx_sf_full_timeout +ffffffff829c73e0 r iwx_sf_full_timeout_def +ffffffff829c7410 r advanced_lookup +ffffffff829c7550 r iwx_devices +ffffffff829c7590 r iwx_dev_info_table +ffffffff829c7e18 R iwx_ca +ffffffff829c8000 R cmpci_ca +ffffffff829c8028 R cmpci_hw_if +ffffffff829c80e0 r cmpci_rate_table +ffffffff829c8120 R cmpci_devices +ffffffff829c8130 r cmpci_query_devinfo.mixer_port_names +ffffffff829c8160 r cmpci_query_devinfo.mixer_classes +ffffffff829c9000 R iha_pci_ca +ffffffff829c9028 R iha_switch +ffffffff829ca000 R pcscp_ca +ffffffff829cb000 R bge_ca +ffffffff829cb030 R bge_devices +ffffffff829cb1b0 r bge_revisions +ffffffff829cb610 r bge_majorrevs +ffffffff829cb790 r bge_kstat_tpl +ffffffff829cc000 R bnx_devices +ffffffff829cc020 R bnx_ca +ffffffff829cd000 R vge_ca +ffffffff829cd028 R vge_devices +ffffffff829ce000 R stge_ca +ffffffff829ce028 R stge_mii_bitbang_ops +ffffffff829ce050 R stge_devices +ffffffff829cf000 R nfe_ca +ffffffff829cf030 R nfe_devices +ffffffff829d0000 R et_devices +ffffffff829d0008 R et_ca +ffffffff829d1000 R jme_devices +ffffffff829d1008 R jme_ca +ffffffff829d2000 R age_devices +ffffffff829d2008 R age_ca +ffffffff829d3000 R alc_devices +ffffffff829d3038 R alc_ca +ffffffff829d4000 R ale_devices +ffffffff829d4008 R ale_ca +ffffffff829d5000 R amdpm_ca +ffffffff829d5030 R amdpm_ids +ffffffff829d6000 R bce_ca +ffffffff829d6028 R bce_devices +ffffffff829d7000 R ath_pci_ca +ffffffff829d8000 R athn_pci_ca +ffffffff829d8030 r athn_pci_devices +ffffffff829d9000 R atw_pci_ca +ffffffff829d9028 R atw_pci_devices +ffffffff829da000 R rtw_pci_ca +ffffffff829da030 R rtw_pci_products +ffffffff829db000 R rtwn_pci_ca +ffffffff829db030 r rtwn_pci_devices +ffffffff829db040 r rtl8188eu_mac +ffffffff829db1b0 r rtl8192cu_mac +ffffffff829db310 r rtl8192ce_mac +ffffffff829db458 r rtl8188eu_bb_prog +ffffffff829db480 r rtl8723a_bb_prog +ffffffff829db4a8 r rtl8192ce_bb_prog_1t +ffffffff829db4d0 r rtl8192ce_bb_prog_2t +ffffffff829db500 r rtl8188eu_bb_regs +ffffffff829db680 r rtl8188eu_bb_vals +ffffffff829db980 r rtl8188eu_agc_vals +ffffffff829dbb80 r rtl8723a_bb_regs +ffffffff829dbd00 r rtl8723a_bb_vals +ffffffff829dbff0 r rtl8192ce_agc_vals +ffffffff829dc270 r rtl8192ce_bb_regs +ffffffff829dc3f0 r rtl8192ce_bb_vals_1t +ffffffff829dc6e0 r rtl8192ce_bb_vals_2t +ffffffff829dd000 R ral_pci_ca +ffffffff829dd030 R ral_pci_devices +ffffffff829de000 R acx_pci_ca +ffffffff829de028 R acx_pci_devices +ffffffff829df000 R pgt_pci_ca +ffffffff829df028 R pgt_pci_devices +ffffffff829e0000 R malo_pci_ca +ffffffff829e0028 R malo_pci_devices +ffffffff829e1000 R bwi_pci_ca +ffffffff829e1030 R bwi_pci_devices +ffffffff829e2000 R piixpm_ca +ffffffff829e2030 R piixpm_ids +ffffffff829e3000 R vic_ca +ffffffff829e3028 R vic_devices +ffffffff829e4000 R vmx_devices +ffffffff829e4008 R vmx_ca +ffffffff829e4030 r vmx_tx_kstat_tpl +ffffffff829e40d0 r vmx_kstat_rate +ffffffff829e40e0 r vmx_rx_kstat_tpl +ffffffff829e5000 R vmwpvs_ca +ffffffff829e5028 R vmwpvs_switch +ffffffff829e6000 R lii_ca +ffffffff829e6028 R lii_devices +ffffffff829e7000 R ichiic_ca +ffffffff829e7030 R ichiic_ids +ffffffff829e8000 R viapm_ca +ffffffff829e8030 R viapm_ids +ffffffff829e8070 r val_to_temp +ffffffff829e8870 r val_to_uV.mult +ffffffff829e9000 R amdiic_ca +ffffffff829e9028 R amdiic_ids +ffffffff829ea000 R nviic_ca +ffffffff829ea030 R nviic_ids +ffffffff829eb000 R sdhc_pci_ca +ffffffff829ec000 R kate_ca +ffffffff829ec030 r kate_proc +ffffffff829ed000 R km_ca +ffffffff829ed030 r km_devices +ffffffff829ee000 R ksmn_ca +ffffffff829ee030 r ksmn_devices +ffffffff829ef000 R iosf_pci_ca +ffffffff829f0000 R itherm_devices +ffffffff829f0008 R itherm_ca +ffffffff829f1000 R pchtemp_ca +ffffffff829f1030 R pchtemp_devices +ffffffff829f2000 R rtsx_pci_ca +ffffffff829f3000 R xspd_ca +ffffffff829f3028 R xspd_devices +ffffffff829f4000 R virtio_pci_ca +ffffffff829f5000 R dwiic_pci_ca +ffffffff829f5030 R dwiic_pci_ids +ffffffff829f6000 R bwfm_pci_ca +ffffffff829f6030 r bwfm_pci_devices +ffffffff829f7000 R ccp_pci_ca +ffffffff829f7030 r ccp_pci_devices +ffffffff829f8000 R bnxt_devices +ffffffff829f8040 R bnxt_ca +ffffffff829f9000 R mcx_ca +ffffffff829f9030 r mcx_devices +ffffffff829f9060 r mcx_rss_config +ffffffff829f90d0 r mcx_eth_cap_map +ffffffff829f92d0 r mcx_kstat_ppcnt_ieee8023 +ffffffff829f92e8 r mcx_kstat_ppcnt_rfc2863 +ffffffff829f9300 r mcx_kstat_ppcnt_rfc2819 +ffffffff829f9318 r mcx_kstat_ppcnt_rfc3635 +ffffffff829f9330 r mcx_ppcnt_ieee8023_tpl +ffffffff829f94b0 r mcx_ppcnt_rfc2863_tpl +ffffffff829f95c0 r mcx_ppcnt_rfc2819_tpl +ffffffff829f9770 r mcx_ppcnt_rfc3635_tpl +ffffffff829f98b0 r mcx_kstat_mtmp_tpl +ffffffff829f9950 r mcx_kstat_mtmp_rate +ffffffff829f9960 r mcx_queue_kstat_tpl +ffffffff829fa000 R iavf_ca +ffffffff829fa030 r iavf_devices +ffffffff829fa040 r iavf_aq_regs +ffffffff829fa0b0 r iavf_link_speeds +ffffffff829fb000 R rge_ca +ffffffff829fb028 R rge_devices +ffffffff829fb030 r rge_phy_config_mac_cfg3.mac_cfg3_a438_value +ffffffff829fb050 r rge_phy_config_mac_cfg3.mac_cfg3_b88e_value +ffffffff829fb0b0 r rtl8125_mac_cfg3_mcu +ffffffff829fb950 r rtl8125_mac_cfg5_mcu +ffffffff829fc970 r rtl8125_mac_bps +ffffffff829fcd70 r rtl8125b_mac_bps +ffffffff829fcf98 r rge_kstats_tpl +ffffffff829fe000 R igc_devices +ffffffff829fe040 R igc_ca +ffffffff829ff000 R ngbe_devices +ffffffff829ff008 R ngbe_ca +ffffffff82a00000 R com_pci_ca +ffffffff82a00030 R com_pci_ids +ffffffff82a01000 r agp_attach.agp_max +ffffffff82a01048 R agp_ca +ffffffff82a02000 R intagp_ca +ffffffff82a03000 r drm_plane_create_rotation_property.props +ffffffff82a04000 r drm_bridge_priv_state_funcs +ffffffff82a06000 r color_encoding_name +ffffffff82a06020 r color_range_name +ffffffff82a07000 r drm_subpixel_enum_list +ffffffff82a07060 r drm_dpms_enum_list +ffffffff82a070a0 r drm_dvi_i_select_enum_list +ffffffff82a070d0 r drm_dvi_i_subconnector_enum_list +ffffffff82a07100 r drm_tv_mode_enum_list +ffffffff82a07170 r drm_tv_select_enum_list +ffffffff82a071c0 r drm_tv_subconnector_enum_list +ffffffff82a07210 r drm_dp_subconnector_enum_list +ffffffff82a07280 r colorspace_names +ffffffff82a07300 r drm_link_status_enum_list +ffffffff82a07320 r drm_scaling_mode_enum_list +ffffffff82a07360 r drm_aspect_ratio_enum_list +ffffffff82a07390 r drm_content_type_enum_list +ffffffff82a073e0 r drm_panel_orientation_enum_list +ffffffff82a07420 r privacy_screen_enum +ffffffff82a08000 r drm_crtc_fence_ops +ffffffff82a09000 r drm_dmt_modes +ffffffff82a0b940 r edid_cea_modes_1 +ffffffff82a0f4d0 r edid_cea_modes_193 +ffffffff82a10180 r edid_quirk_list +ffffffff82a10360 r drm_mode_do_interlace_quirk.cea_interlaced +ffffffff82a103a0 r edid_4k_modes +ffffffff82a10600 r edid_est_modes +ffffffff82a10e00 r est3_modes +ffffffff82a10f60 r stereo_mandatory_modes +ffffffff82a10fe0 r extra_modes +ffffffff82a12000 r drm_encoder_enum_list +ffffffff82a14000 r drm_fbdev_dma_helper_funcs +ffffffff82a14010 r drm_fbdev_dma_client_funcs +ffffffff82a14030 r drm_fbdev_dma_fb_ops +ffffffff82a15000 r drm_fbdev_generic_helper_funcs +ffffffff82a15010 r drm_fbdev_generic_client_funcs +ffffffff82a15030 r drm_fbdev_generic_fb_ops +ffffffff82a17000 r drm_fb_xrgb8888_to_rgb332.dst_pixsize +ffffffff82a17004 r drm_fb_xrgb8888_to_rgb565.dst_pixsize +ffffffff82a17008 r drm_fb_xrgb8888_to_xrgb1555.dst_pixsize +ffffffff82a1700c r drm_fb_xrgb8888_to_argb1555.dst_pixsize +ffffffff82a17010 r drm_fb_xrgb8888_to_rgba5551.dst_pixsize +ffffffff82a17014 r drm_fb_xrgb8888_to_rgb888.dst_pixsize +ffffffff82a17018 r drm_fb_xrgb8888_to_argb8888.dst_pixsize +ffffffff82a1701c r drm_fb_xrgb8888_to_xrgb2101010.dst_pixsize +ffffffff82a17020 r drm_fb_xrgb8888_to_argb2101010.dst_pixsize +ffffffff82a17024 r drm_fb_xrgb8888_to_gray8.dst_pixsize +ffffffff82a17028 r drm_fb_xrgb8888_to_xbgr8888.dst_pixsize +ffffffff82a1702c r drm_fb_xrgb8888_to_abgr8888.dst_pixsize +ffffffff82a18000 r __drm_format_info.formats +ffffffff82a19000 R drm_pgops +ffffffff82a1a000 r drm_gem_dma_default_funcs +ffffffff82a1b000 R drm_gem_fb_funcs +ffffffff82a1c000 r drm_ioctls +ffffffff82a1e000 r dma_fence_stub_ops +ffffffff82a1e040 R dma_fence_array_ops +ffffffff82a1e080 R dma_fence_chain_ops +ffffffff82a1e0c0 R dmabufops +ffffffff82a1e0f8 R syncfileops +ffffffff82a1f000 r drm_plane_type_enum_list +ffffffff82a20000 r tv_modes_parameters +ffffffff82a200c0 r drm_mode_status_names +ffffffff82a20200 r drm_named_modes +ffffffff82a21000 r primary_plane_funcs +ffffffff82a21068 r safe_modeset_formats +ffffffff82a22000 r orientation_data +ffffffff82a25718 r lcd800x1280_rightside_up +ffffffff82a25730 r lcd720x1280_rightside_up +ffffffff82a25748 r lcd800x1280_leftside_up +ffffffff82a25760 r lcd1080x1920_leftside_up +ffffffff82a25778 r lcd1200x1920_rightside_up +ffffffff82a25790 r gpd_micropc +ffffffff82a257a8 r gpd_pocket +ffffffff82a257c0 r gpd_pocket2 +ffffffff82a257d8 r gpd_win +ffffffff82a257f0 r gpd_win2 +ffffffff82a25808 r itworks_tw891 +ffffffff82a25820 r lcd1600x2560_rightside_up +ffffffff82a25838 r onegx1_pro +ffffffff82a25850 r lcd1600x2560_leftside_up +ffffffff82a25868 r lcd1280x1920_rightside_up +ffffffff82a25880 r gpd_onemix2s +ffffffff82a25898 r .compoundliteral +ffffffff82a258a8 r .compoundliteral.5 +ffffffff82a258d0 r .compoundliteral.9 +ffffffff82a258f0 r .compoundliteral.17 +ffffffff82a25930 r .compoundliteral.21 +ffffffff82a25950 r .compoundliteral.23 +ffffffff82a25960 r .compoundliteral.25 +ffffffff82a25970 r .compoundliteral.29 +ffffffff82a26000 r drm_gem_prime_dmabuf_ops +ffffffff82a28000 r is_hdmi_adaptor.dp_dual_mode_hdmi_id +ffffffff82a29000 r drm_dp_phy_name.phy_names +ffffffff82a29048 r drm_dp_i2c_algo +ffffffff82a29058 r drm_dp_i2c_lock_ops +ffffffff82a29070 r dp_aux_bl_ops +ffffffff82a29090 r dpcd_quirk_list +ffffffff82a29320 r drm_dp_psr_setup_time.psr_setup_time_us +ffffffff82a2a000 R drm_dp_mst_topology_state_funcs +ffffffff82a2a020 r drm_dp_mst_req_type_str.req_type_str +ffffffff82a2a1f0 r drm_dp_mst_sideband_tx_state_str.sideband_reason_str +ffffffff82a2a220 r drm_dp_mst_nak_reason_str.nak_reason_str +ffffffff82a2a278 r drm_dp_mst_i2c_algo +ffffffff82a2b000 r rc_parameters_1_2_444 +ffffffff82a2b5f0 r rc_parameters_pre_scr +ffffffff82a2b920 r rc_parameters_1_2_422 +ffffffff82a2bdf0 r rc_parameters_1_2_420 +ffffffff82a2d000 r hdmi_colorimetry_val +ffffffff82a2e018 R ttm_bo_vm_ops +ffffffff82a2f000 r ttm_range_manager_func +ffffffff82a30018 r ttm_kmap_iter_io_ops +ffffffff82a30030 r ttm_kmap_iter_linear_io_ops +ffffffff82a31000 r ttm_sys_manager_func +ffffffff82a32000 r ttm_kmap_iter_tt_ops +ffffffff82a33000 r drm_sched_fence_ops_scheduled +ffffffff82a33040 r drm_sched_fence_ops_finished +ffffffff82a34000 R ch7017_ops +ffffffff82a35000 R ch7xxx_ops +ffffffff82a35060 r ch7xxx_ids +ffffffff82a36000 R ivch_ops +ffffffff82a36060 r backup_addresses +ffffffff82a37000 R ns2501_ops +ffffffff82a37060 r mode_agnostic_values +ffffffff82a370e0 r ns2501_modes +ffffffff82a38000 R sil164_ops +ffffffff82a39000 R tfp410_ops +ffffffff82a3a000 r chv_dpll +ffffffff82a3a050 r vlv_dpll +ffffffff82a3a0a0 r g4x_dpll +ffffffff82a3a0f0 r pch_dpll +ffffffff82a3a138 r intel_dp_enc_funcs +ffffffff82a3b000 r intel_hdmi_enc_funcs +ffffffff82a3c000 r vlv_primary_formats +ffffffff82a3c030 r ivb_primary_formats +ffffffff82a3c050 r i965_primary_formats +ffffffff82a3c070 r i8xx_primary_formats +ffffffff82a3c080 r i965_plane_funcs +ffffffff82a3c0e8 r i8xx_plane_funcs +ffffffff82a3d000 r ilk_wm_funcs +ffffffff82a3d040 r vlv_wm_funcs +ffffffff82a3d080 r g4x_wm_funcs +ffffffff82a3d0c0 r nop_funcs +ffffffff82a3d100 r pnv_wm_funcs +ffffffff82a3d140 r i965_wm_funcs +ffffffff82a3d180 r i9xx_wm_funcs +ffffffff82a3d1c0 r i845_wm_funcs +ffffffff82a3d200 r cxsr_latency_table +ffffffff82a3e000 r gen11_dsi_encoder_funcs +ffffffff82a3e020 r gen11_dsi_connector_funcs +ffffffff82a3e098 r gen11_dsi_connector_helper_funcs +ffffffff82a3e0f8 r gen11_dsi_host_ops +ffffffff82a3f000 r intel_plane_helper_funcs +ffffffff82a40000 r g4x_audio_funcs +ffffffff82a40018 r ibx_audio_funcs +ffffffff82a40030 r hsw_audio_funcs +ffffffff82a40050 r hdmi_audio_clock +ffffffff82a400c0 r dp_aud_n_m +ffffffff82a40270 r hdmi_aud_ncts_36bpp +ffffffff82a40350 r hdmi_aud_ncts_30bpp +ffffffff82a40430 r hdmi_aud_ncts_24bpp +ffffffff82a41000 r intel_backlight_device_ops +ffffffff82a41018 r bxt_pwm_funcs +ffffffff82a41048 r cnp_pwm_funcs +ffffffff82a41078 r lpt_pwm_funcs +ffffffff82a410a8 r spt_pwm_funcs +ffffffff82a410d8 r pch_pwm_funcs +ffffffff82a41108 r ext_pwm_funcs +ffffffff82a41138 r vlv_pwm_funcs +ffffffff82a41168 r i965_pwm_funcs +ffffffff82a41198 r i9xx_pwm_funcs +ffffffff82a411c8 r pwm_bl_funcs +ffffffff82a42000 r bdb_blocks +ffffffff82a42160 r adlp_aux_ch_map +ffffffff82a42169 r adls_aux_ch_map +ffffffff82a42170 r rkl_aux_ch_map +ffffffff82a42175 r direct_aux_ch_map +ffffffff82a4217e r translate_iboost.mapping +ffffffff82a42181 r adlp_ddc_pin_map +ffffffff82a4218e r adls_ddc_pin_map +ffffffff82a4219b r rkl_pch_tgp_ddc_pin_map +ffffffff82a421a6 r gen9bc_tgp_ddc_pin_map +ffffffff82a421b1 r icp_ddc_pin_map +ffffffff82a421c0 r cnp_ddc_pin_map +ffffffff82a43000 r mtl_sa_info +ffffffff82a43006 r adlp_sa_info +ffffffff82a4300c r adls_sa_info +ffffffff82a43012 r rkl_sa_info +ffffffff82a43018 r tgl_sa_info +ffffffff82a43020 r intel_bw_funcs +ffffffff82a44000 r intel_cdclk_funcs +ffffffff82a44010 r mtl_cdclk_funcs +ffffffff82a44030 r mtl_cdclk_table +ffffffff82a44088 r tgl_cdclk_funcs +ffffffff82a440b0 r dg2_cdclk_table +ffffffff82a44160 r adlp_a_step_cdclk_table +ffffffff82a441e0 r rplu_cdclk_table +ffffffff82a442c8 r rplu_cdclk_funcs +ffffffff82a442f0 r adlp_cdclk_table +ffffffff82a443b0 r rkl_cdclk_table +ffffffff82a444a0 r icl_cdclk_table +ffffffff82a44588 r ehl_cdclk_funcs +ffffffff82a445a8 r icl_cdclk_funcs +ffffffff82a445c8 r bxt_cdclk_funcs +ffffffff82a445f0 r glk_cdclk_table +ffffffff82a44620 r bxt_cdclk_table +ffffffff82a44668 r skl_cdclk_funcs +ffffffff82a44688 r bdw_cdclk_funcs +ffffffff82a446a8 r hsw_cdclk_funcs +ffffffff82a446c8 r chv_cdclk_funcs +ffffffff82a446e8 r vlv_cdclk_funcs +ffffffff82a44708 r fixed_400mhz_cdclk_funcs +ffffffff82a44728 r ilk_cdclk_funcs +ffffffff82a44748 r gm45_cdclk_funcs +ffffffff82a44768 r g33_cdclk_funcs +ffffffff82a44788 r i965gm_cdclk_funcs +ffffffff82a447a8 r pnv_cdclk_funcs +ffffffff82a447c8 r i945gm_cdclk_funcs +ffffffff82a447e8 r i915gm_cdclk_funcs +ffffffff82a44808 r i915g_cdclk_funcs +ffffffff82a44828 r i865g_cdclk_funcs +ffffffff82a44848 r i85x_cdclk_funcs +ffffffff82a44868 r i845g_cdclk_funcs +ffffffff82a44888 r i830_cdclk_funcs +ffffffff82a448a8 r g33_get_cdclk.div_3200 +ffffffff82a448ae r g33_get_cdclk.div_4000 +ffffffff82a448b4 r g33_get_cdclk.div_4800 +ffffffff82a448ba r g33_get_cdclk.div_5333 +ffffffff82a448c0 r i965gm_get_cdclk.div_3200 +ffffffff82a448c3 r i965gm_get_cdclk.div_4000 +ffffffff82a448c6 r i965gm_get_cdclk.div_5333 +ffffffff82a45000 r chv_color_funcs +ffffffff82a45040 r vlv_color_funcs +ffffffff82a45080 r i965_color_funcs +ffffffff82a450c0 r i9xx_color_funcs +ffffffff82a45100 r tgl_color_funcs +ffffffff82a45140 r icl_color_funcs +ffffffff82a45180 r glk_color_funcs +ffffffff82a451c0 r skl_color_funcs +ffffffff82a45200 r bdw_color_funcs +ffffffff82a45240 r hsw_color_funcs +ffffffff82a45280 r ivb_color_funcs +ffffffff82a452c0 r ilk_color_funcs +ffffffff82a45300 r chv_cgm_csc_matrix_identity +ffffffff82a4531e r ilk_csc_matrix_rgb_to_ycbcr +ffffffff82a4533c r ilk_csc_matrix_limited_range +ffffffff82a4535a r ilk_csc_matrix_identity +ffffffff82a46000 r icl_procmon_values +ffffffff82a47000 r force_audio_names +ffffffff82a47040 r broadcast_rgb_names +ffffffff82a48000 r intel_crt_connector_funcs +ffffffff82a48078 r intel_crt_enc_funcs +ffffffff82a480a0 r intel_spurious_crt_detect +ffffffff82a484a8 r intel_crt_connector_helper_funcs +ffffffff82a49000 r g4x_crtc_funcs +ffffffff82a490c0 r i965_crtc_funcs +ffffffff82a49180 r i915gm_crtc_funcs +ffffffff82a49240 r i915_crtc_funcs +ffffffff82a49300 r i8xx_crtc_funcs +ffffffff82a493c0 r bdw_crtc_funcs +ffffffff82a49480 r ilk_crtc_funcs +ffffffff82a4a000 r output_format_str +ffffffff82a4a020 r output_type_str +ffffffff82a4b000 r intel_cursor_plane_funcs +ffffffff82a4b068 r intel_cursor_formats +ffffffff82a4c000 r mtl_c10_hdmi_tables +ffffffff82a4c170 r mtl_c10_hdmi_25_2 +ffffffff82a4c18c r mtl_c10_hdmi_27_0 +ffffffff82a4c1a8 r mtl_c10_hdmi_27027 +ffffffff82a4c1c4 r mtl_c10_hdmi_28320 +ffffffff82a4c1e0 r mtl_c10_hdmi_30240 +ffffffff82a4c1fc r mtl_c10_hdmi_31500 +ffffffff82a4c218 r mtl_c10_hdmi_36000 +ffffffff82a4c234 r mtl_c10_hdmi_40000 +ffffffff82a4c250 r mtl_c10_hdmi_49500 +ffffffff82a4c26c r mtl_c10_hdmi_50000 +ffffffff82a4c288 r mtl_c10_hdmi_57284 +ffffffff82a4c2a4 r mtl_c10_hdmi_58000 +ffffffff82a4c2c0 r mtl_c10_hdmi_65000 +ffffffff82a4c2dc r mtl_c10_hdmi_71000 +ffffffff82a4c2f8 r mtl_c10_hdmi_74176 +ffffffff82a4c314 r mtl_c10_hdmi_74_25 +ffffffff82a4c330 r mtl_c10_hdmi_75000 +ffffffff82a4c34c r mtl_c10_hdmi_78750 +ffffffff82a4c368 r mtl_c10_hdmi_85500 +ffffffff82a4c384 r mtl_c10_hdmi_88750 +ffffffff82a4c3a0 r mtl_c10_hdmi_106500 +ffffffff82a4c3bc r mtl_c10_hdmi_108000 +ffffffff82a4c3d8 r mtl_c10_hdmi_115500 +ffffffff82a4c3f4 r mtl_c10_hdmi_119000 +ffffffff82a4c410 r mtl_c10_hdmi_135000 +ffffffff82a4c42c r mtl_c10_hdmi_138500 +ffffffff82a4c448 r mtl_c10_hdmi_147160 +ffffffff82a4c464 r mtl_c10_hdmi_148352 +ffffffff82a4c480 r mtl_c10_hdmi_148_5 +ffffffff82a4c49c r mtl_c10_hdmi_154000 +ffffffff82a4c4b8 r mtl_c10_hdmi_162000 +ffffffff82a4c4d4 r mtl_c10_hdmi_167000 +ffffffff82a4c4f0 r mtl_c10_hdmi_197802 +ffffffff82a4c50c r mtl_c10_hdmi_198000 +ffffffff82a4c528 r mtl_c10_hdmi_209800 +ffffffff82a4c544 r mtl_c10_hdmi_241500 +ffffffff82a4c560 r mtl_c10_hdmi_262750 +ffffffff82a4c57c r mtl_c10_hdmi_268500 +ffffffff82a4c598 r mtl_c10_hdmi_296703 +ffffffff82a4c5b4 r mtl_c10_hdmi_297000 +ffffffff82a4c5d0 r mtl_c10_hdmi_319750 +ffffffff82a4c5ec r mtl_c10_hdmi_497750 +ffffffff82a4c608 r mtl_c10_hdmi_592000 +ffffffff82a4c624 r mtl_c10_hdmi_593407 +ffffffff82a4c640 r mtl_c10_hdmi_594 +ffffffff82a4c660 r mtl_c20_hdmi_tables +ffffffff82a4c6b8 r mtl_c20_hdmi_25_175 +ffffffff82a4c6e4 r mtl_c20_hdmi_27_0 +ffffffff82a4c710 r mtl_c20_hdmi_74_25 +ffffffff82a4c73c r mtl_c20_hdmi_148_5 +ffffffff82a4c768 r mtl_c20_hdmi_594 +ffffffff82a4c794 r mtl_c20_hdmi_300 +ffffffff82a4c7c0 r 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tgl_combo_phy_trans_edp_hbr2_hobl +ffffffff82a4e010 r _tgl_combo_phy_trans_edp_hbr2_hobl +ffffffff82a4e080 r mtl_c20_trans_uhbr +ffffffff82a4e090 r mtl_c20_trans_hdmi +ffffffff82a4e0a0 r mtl_c20_trans_dp14 +ffffffff82a4e0b0 r mtl_c10_trans_dp14 +ffffffff82a4e0c0 r _mtl_c20_trans_uhbr +ffffffff82a4e180 r _mtl_c20_trans_hdmi +ffffffff82a4e1c0 r _mtl_c20_trans_dp14 +ffffffff82a4e240 r _mtl_c10_trans_dp14 +ffffffff82a4e2b8 r dg2_snps_trans_uhbr +ffffffff82a4e2c8 r dg2_snps_trans +ffffffff82a4e2e0 r _dg2_snps_trans_uhbr +ffffffff82a4e3a0 r _dg2_snps_trans +ffffffff82a4e418 r icl_combo_phy_trans_hdmi +ffffffff82a4e430 r _icl_combo_phy_trans_hdmi +ffffffff82a4e488 r adlp_combo_phy_trans_edp_hbr3 +ffffffff82a4e498 r adlp_combo_phy_trans_edp_up_to_hbr2 +ffffffff82a4e4b0 r _adlp_combo_phy_trans_dp_hbr2_edp_hbr3 +ffffffff82a4e530 r _adlp_combo_phy_trans_edp_hbr2 +ffffffff82a4e5a8 r adlp_combo_phy_trans_dp_hbr2_hbr3 +ffffffff82a4e5b8 r adlp_combo_phy_trans_dp_hbr +ffffffff82a4e5d0 r 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intel_region_map +ffffffff82ac2000 r dg2_g10_revid_step_tbl +ffffffff82ac2030 r dg2_g11_revid_step_tbl +ffffffff82ac2050 r xehpsdv_revids +ffffffff82ac2080 r adlp_rplp_revids +ffffffff82ac20a0 r adlp_revids +ffffffff82ac20e0 r adls_rpls_revids +ffffffff82ac2120 r adls_revids +ffffffff82ac2160 r rkl_revids +ffffffff82ac2180 r bxt_revids +ffffffff82ac21c0 r skl_revids +ffffffff82ac21f0 r pvc_bd_subids +ffffffff82ac2210 r pvc_ct_subids +ffffffff82ac4000 r forcewake_domain_names +ffffffff82ac4080 r __mtl_fw_ranges +ffffffff82ac41f0 r mtl_shadowed_regs +ffffffff82ac4270 r __pvc_fw_ranges +ffffffff82ac4420 r pvc_shadowed_regs +ffffffff82ac4540 r __dg2_fw_ranges +ffffffff82ac4810 r dg2_shadowed_regs +ffffffff82ac4930 r __xehp_fw_ranges +ffffffff82ac4c00 r gen12_shadowed_regs +ffffffff82ac4d20 r __gen12_fw_ranges +ffffffff82ac4f30 r __gen11_fw_ranges +ffffffff82ac50e0 r gen11_shadowed_regs +ffffffff82ac51a0 r __gen9_fw_ranges +ffffffff82ac5320 r gen8_shadowed_regs +ffffffff82ac5350 r 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radeon_dp_connector_funcs +ffffffff82af6078 r radeon_dp_connector_helper_funcs +ffffffff82af60d8 r radeon_lvds_bridge_connector_funcs +ffffffff82af6150 r radeon_vga_connector_funcs +ffffffff82af61c8 r radeon_vga_connector_helper_funcs +ffffffff82af6228 r radeon_dvi_connector_funcs +ffffffff82af62a0 r radeon_dvi_connector_helper_funcs +ffffffff82af6300 r radeon_edp_connector_funcs +ffffffff82af6378 r radeon_tv_connector_funcs +ffffffff82af63f0 r radeon_tv_connector_helper_funcs +ffffffff82af6450 r radeon_lvds_connector_funcs +ffffffff82af64c8 r radeon_lvds_connector_helper_funcs +ffffffff82af7000 r radeon_family_name +ffffffff82af73f0 r radeon_px_quirk_list +ffffffff82af8000 r radeon_fb_funcs +ffffffff82af8018 r radeon_mode_funcs +ffffffff82af8060 r radeon_tmds_pll_enum_list +ffffffff82af8080 r radeon_tv_std_enum_list +ffffffff82af8100 r radeon_underscan_enum_list +ffffffff82af8130 r radeon_audio_enum_list +ffffffff82af8160 r radeon_dither_enum_list +ffffffff82af8180 r radeon_output_csc_enum_list +ffffffff82af81c0 r radeon_crtc_funcs +ffffffff82af8280 r hpd_names +ffffffff82af82b0 r encoder_names +ffffffff82af83e0 r radeon_afmt_init.eg_offsets +ffffffff82af9000 r aux_offset +ffffffff82afa000 R radeondrm_ca +ffffffff82afa030 r pciidlist +ffffffff82afe1d0 r kms_driver +ffffffff82afe2c0 r radeon_ioctls_kms +ffffffff82aff000 r radeon_fbdev_fb_helper_funcs +ffffffff82aff010 r radeon_fbdev_client_funcs +ffffffff82aff030 r radeon_fbdev_fb_ops +ffffffff82b00000 R radeon_fence_ops +ffffffff82b02000 R radeon_gem_object_funcs +ffffffff82b02070 r radeon_gem_vm_ops +ffffffff82b03000 r radeon_i2c_algo +ffffffff82b03010 r radeon_atom_i2c_algo +ffffffff82b04000 r legacy_helper_funcs +ffffffff82b05000 r radeon_backlight_ops +ffffffff82b05018 r radeon_legacy_lvds_enc_funcs +ffffffff82b05038 r radeon_legacy_lvds_helper_funcs +ffffffff82b050a0 r radeon_legacy_tmds_int_enc_funcs +ffffffff82b050c0 r radeon_legacy_tmds_int_helper_funcs +ffffffff82b05128 r radeon_legacy_primary_dac_enc_funcs +ffffffff82b05148 r radeon_legacy_primary_dac_helper_funcs +ffffffff82b051b0 r radeon_legacy_tv_dac_enc_funcs +ffffffff82b051d0 r radeon_legacy_tv_dac_helper_funcs +ffffffff82b05238 r radeon_legacy_tmds_ext_enc_funcs +ffffffff82b05258 r radeon_legacy_tmds_ext_helper_funcs +ffffffff82b06000 r SLOPE_value +ffffffff82b06030 r YCOEF_EN_value +ffffffff82b06060 r YCOEF_value +ffffffff82b06090 r available_tv_modes +ffffffff82b06110 r hor_timing_NTSC +ffffffff82b06150 r vert_timing_NTSC +ffffffff82b06190 r hor_timing_PAL +ffffffff82b061d0 r vert_timing_PAL +ffffffff82b08000 r radeon_pm_state_type_name +ffffffff82b09000 r radeon_evict_flags.placements +ffffffff82b0c000 r rs600_reg_safe_bm +ffffffff82b0e000 r rv515_reg_safe_bm +ffffffff82b0f000 r dll_speed_table +ffffffff82b10000 r r7xx_golden_registers +ffffffff82b10090 r r7xx_golden_dyn_gpr_registers +ffffffff82b10100 r rv770ce_golden_registers +ffffffff82b10160 r rv770_golden_registers +ffffffff82b101b0 r rv770_mgcg_init +ffffffff82b108f0 r rv730_golden_registers +ffffffff82b10950 r rv730_mgcg_init +ffffffff82b10ee0 r rv710_golden_registers +ffffffff82b10f30 r rv710_mgcg_init +ffffffff82b111d0 r rv740_golden_registers +ffffffff82b11360 r rv740_mgcg_init +ffffffff82b13000 r rv730_smc_int_vectors +ffffffff82b13040 r rv710_smc_int_vectors +ffffffff82b13080 r rv740_smc_int_vectors +ffffffff82b130c0 r cypress_smc_int_vectors +ffffffff82b13100 r caicos_smc_int_vectors +ffffffff82b13140 r cayman_smc_int_vectors +ffffffff82b14000 r tahiti_io_mc_regs +ffffffff82b14120 r pitcairn_io_mc_regs +ffffffff82b14240 r verde_io_mc_regs +ffffffff82b14360 r oland_io_mc_regs +ffffffff82b14480 r hainan_io_mc_regs +ffffffff82b145a0 r crtc_offsets +ffffffff82b145c0 r si_disp_int_status +ffffffff82b145e0 r tahiti_golden_registers +ffffffff82b14760 r tahiti_golden_rlc_registers +ffffffff82b147b0 r tahiti_mgcg_cgcg_init +ffffffff82b14d98 r tahiti_golden_registers2 +ffffffff82b14db0 r pitcairn_golden_registers +ffffffff82b14f00 r pitcairn_golden_rlc_registers +ffffffff82b14f40 r pitcairn_mgcg_cgcg_init +ffffffff82b153b0 r verde_golden_registers +ffffffff82b15620 r verde_golden_rlc_registers +ffffffff82b15660 r verde_mgcg_cgcg_init +ffffffff82b15ae0 r oland_golden_registers +ffffffff82b15c30 r oland_golden_rlc_registers +ffffffff82b15c70 r oland_mgcg_cgcg_init +ffffffff82b16000 r hainan_golden_registers +ffffffff82b1612c r hainan_golden_registers2 +ffffffff82b16140 r hainan_mgcg_cgcg_init +ffffffff82b164b0 r verde_rlc_save_restore_register_list +ffffffff82b16820 r si_cs_data +ffffffff82b16840 r si_SECT_CONTEXT_defs +ffffffff82b168c0 r si_SECT_CONTEXT_def_1 +ffffffff82b16c10 r si_SECT_CONTEXT_def_3 +ffffffff82b16c30 r si_SECT_CONTEXT_def_4 +ffffffff82b16ea4 r si_SECT_CONTEXT_def_5 +ffffffff82b16ea8 r si_SECT_CONTEXT_def_6 +ffffffff82b16eb0 r si_SECT_CONTEXT_def_2 +ffffffff82b172f0 r si_SECT_CONTEXT_def_7 +ffffffff82b176a0 r mc_cg_registers +ffffffff82b176d0 r si_default_state +ffffffff82b18000 r cac_weights_tahiti +ffffffff82b184d0 r lcac_tahiti +ffffffff82b18ba0 r cac_override_tahiti +ffffffff82b18bb4 r powertune_data_tahiti +ffffffff82b18bf0 r dte_data_tahiti +ffffffff82b18cc0 r dte_data_new_zealand +ffffffff82b18d90 r dte_data_malta +ffffffff82b18e60 r lcac_pitcairn +ffffffff82b19530 r cac_override_pitcairn +ffffffff82b19544 r powertune_data_pitcairn +ffffffff82b19580 r lcac_cape_verde +ffffffff82b199d0 r cac_override_cape_verde +ffffffff82b199e4 r powertune_data_cape_verde +ffffffff82b19a20 r cac_weights_cape_verde_pro +ffffffff82b19ef0 r cac_weights_heathrow +ffffffff82b1a3c0 r cac_weights_chelsea_xt +ffffffff82b1a890 r cac_weights_chelsea_pro +ffffffff82b1ad60 r cac_weights_cape_verde +ffffffff82b1b230 r cac_weights_mars_pro +ffffffff82b1b700 r lcac_mars_pro +ffffffff82b1ba60 r cac_override_oland +ffffffff82b1ba74 r powertune_data_mars_pro +ffffffff82b1bab0 r cac_weights_mars_xt +ffffffff82b1bf80 r cac_weights_oland_pro +ffffffff82b1c450 r cac_weights_oland_xt +ffffffff82b1c920 r lcac_oland +ffffffff82b1cc7c r powertune_data_oland +ffffffff82b1ccc0 r cac_weights_hainan +ffffffff82b1d184 r powertune_data_hainan +ffffffff82b1d1c0 r dte_data_aruba_pro +ffffffff82b1d290 r dte_data_tahiti_pro +ffffffff82b1d360 r dte_data_curacao_pro +ffffffff82b1d430 r dte_data_neptune_xt +ffffffff82b1d500 r dte_data_sun_xt +ffffffff82b1d5d0 r dte_data_venus_xtx +ffffffff82b1d6a0 r dte_data_venus_xt +ffffffff82b1d770 r dte_data_venus_pro +ffffffff82b1d840 r dte_data_mars_pro +ffffffff82b1e000 r si_program_jump_on_start.data +ffffffff82b1f000 r sumo_dtc +ffffffff82b20000 r trinity_mgcg_shls_default +ffffffff82b20380 r trinity_sysls_enable +ffffffff82b20450 r trinity_sysls_disable +ffffffff82b22000 r GC_BASE +ffffffff82b220a8 r HDP_BASE +ffffffff82b22150 r MMHUB_BASE +ffffffff82b221f8 r ATHUB_BASE +ffffffff82b222a0 r NBIO_BASE +ffffffff82b22348 r MP0_BASE +ffffffff82b223f0 r MP1_BASE +ffffffff82b22498 r DF_BASE +ffffffff82b22540 r OSSSYS_BASE +ffffffff82b225e8 r SDMA0_BASE +ffffffff82b22690 r SDMA1_BASE +ffffffff82b22738 r SDMA2_BASE +ffffffff82b227e0 r SDMA3_BASE +ffffffff82b22888 r SDMA4_BASE +ffffffff82b22930 r SMUIO_BASE +ffffffff82b229d8 r THM_BASE +ffffffff82b22a80 r UMC_BASE +ffffffff82b22b28 r VCN_BASE +ffffffff82b23000 r amdgpu_afmt_predefined_acr +ffffffff82b24000 r atom_op_names +ffffffff82b243e0 r opcode_table +ffffffff82b24bd0 r atom_dst_to_src +ffffffff82b24c50 r atom_io_names +ffffffff82b24c80 r atom_table_names +ffffffff82b24ed0 r atom_iio_len +ffffffff82b25000 r object_connector_convert +ffffffff82b25058 R amdgpu_vbios_version_attr_group +ffffffff82b26000 r voltage_names +ffffffff82b26020 r pre_emph_names +ffffffff82b27000 r amdgpu_atombios_encoder_backlight_ops +ffffffff82b29000 r amdgpu_benchmark.common_modes +ffffffff82b2a000 r amdgpu_cgs_ops +ffffffff82b2b000 r amdgpu_connector_dp_funcs +ffffffff82b2b078 r amdgpu_connector_dp_helper_funcs +ffffffff82b2b0d8 r amdgpu_connector_edp_funcs +ffffffff82b2b150 r amdgpu_connector_vga_funcs +ffffffff82b2b1c8 r amdgpu_connector_vga_helper_funcs +ffffffff82b2b228 r amdgpu_connector_dvi_funcs +ffffffff82b2b2a0 r amdgpu_connector_dvi_helper_funcs +ffffffff82b2b300 r amdgpu_connector_lvds_funcs +ffffffff82b2b378 r amdgpu_connector_lvds_helper_funcs +ffffffff82b2b3e0 r amdgpu_connector_add_common_modes.common_modes +ffffffff82b2d000 R amdgpu_ctx_num_entities +ffffffff82b2e000 r amdgpu_kms_driver +ffffffff82b2e0f0 r amdgpu_device_ip_reinit_late_sriov.ip_order +ffffffff82b2f000 r hw_id_map +ffffffff82b2f090 r hw_id_names +ffffffff82b30000 r hpd_names +ffffffff82b30030 r encoder_names +ffffffff82b30180 r dcc_retile_formats +ffffffff82b30270 r dcc_formats +ffffffff82b30360 R amdgpu_mode_funcs +ffffffff82b303b0 r amdgpu_underscan_enum_list +ffffffff82b303e0 r amdgpu_audio_enum_list +ffffffff82b30410 r amdgpu_dither_enum_list +ffffffff82b30430 r amdgpu_fb_funcs_atomic +ffffffff82b30448 r amdgpu_fb_funcs +ffffffff82b31000 R amdgpu_dmabuf_ops +ffffffff82b32000 R amdgpu_ioctls_kms +ffffffff82b32210 R amdgpu_partition_driver +ffffffff82b322f8 R amdgpu_ca +ffffffff82b32320 r pciidlist +ffffffff82b331f0 r amdgpu_unsupported_pciidlist +ffffffff82b33770 r amdgpu_kms_driver +ffffffff82b34000 r amdgpu_job_fence_ops +ffffffff82b34040 r amdgpu_fence_ops +ffffffff82b35000 r amdgpu_gem_object_funcs +ffffffff82b35070 r amdgpu_gem_vm_ops +ffffffff82b36000 R amdgpu_gtt_mgr_attr_group +ffffffff82b36018 r amdgpu_gtt_mgr_func +ffffffff82b37000 r amdgpu_atombios_i2c_algo +ffffffff82b38000 R node_id_to_phys_map +ffffffff82b39000 R amdgpu_sched_ops +ffffffff82b3b000 r amdgpu_vram_names +ffffffff82b3c000 r amdgpu_preempt_mgr_func +ffffffff82b3d000 R psp_ip_funcs +ffffffff82b3d0a0 R psp_v3_1_ip_block +ffffffff82b3d0b8 R psp_v10_0_ip_block +ffffffff82b3d0d0 R psp_v11_0_ip_block +ffffffff82b3d0e8 R psp_v11_0_8_ip_block +ffffffff82b3d100 R psp_v12_0_ip_block +ffffffff82b3d118 R psp_v13_0_ip_block +ffffffff82b3d130 R psp_v13_0_4_ip_block +ffffffff82b3f000 r sw_ring_info +ffffffff82b40000 r amdgpu_evict_flags.placements +ffffffff82b44000 R amdgpu_vkms_ip_block +ffffffff82b45000 R amdgpu_vm_cpu_funcs +ffffffff82b47000 R amdgpu_vm_sdma_funcs +ffffffff82b48000 R amdgpu_vram_mgr_attr_group +ffffffff82b48018 r amdgpu_vram_mgr_func +ffffffff82b48040 r amdgpu_dummy_vram_mgr_func +ffffffff82b49000 r xgmi_pcs_err_status_reg_arct +ffffffff82b49020 r xgmi3x16_pcs_ras_fields +ffffffff82b491f0 r xgmi_pcs_ras_fields +ffffffff82b49310 r wafl_pcs_ras_fields +ffffffff82b4a000 r GC_BASE +ffffffff82b4a0c0 r HDP_BASE +ffffffff82b4a180 r MMHUB_BASE +ffffffff82b4a240 r ATHUB_BASE +ffffffff82b4a300 r NBIF0_BASE +ffffffff82b4a3c0 r MP0_BASE +ffffffff82b4a480 r MP1_BASE +ffffffff82b4a540 r UVD_BASE +ffffffff82b4a600 r DF_BASE +ffffffff82b4a6c0 r OSSSYS_BASE +ffffffff82b4a780 r SDMA0_BASE +ffffffff82b4a840 r SDMA1_BASE +ffffffff82b4a900 r SDMA2_BASE +ffffffff82b4a9c0 r SDMA3_BASE +ffffffff82b4aa80 r SDMA4_BASE +ffffffff82b4ab40 r SDMA5_BASE +ffffffff82b4ac00 r SDMA6_BASE +ffffffff82b4acc0 r SDMA7_BASE +ffffffff82b4ad80 r SMUIO_BASE +ffffffff82b4ae40 r THM_BASE +ffffffff82b4af00 r UMC_BASE +ffffffff82b4afc0 r RSMU_BASE +ffffffff82b4c000 r cz_ih_ip_funcs +ffffffff82b4c0a0 R cz_ih_ip_block +ffffffff82b4c0b8 r cz_ih_funcs +ffffffff82b4d000 r crtc_offsets +ffffffff82b4d020 r dce_v10_0_ip_funcs +ffffffff82b4d0c0 R dce_v10_0_ip_block +ffffffff82b4d0d8 R dce_v10_1_ip_block +ffffffff82b4d0f0 r dce_v10_0_display_funcs +ffffffff82b4d150 r hpd_offsets +ffffffff82b4d168 r dce_v10_0_encoder_funcs +ffffffff82b4d188 r dce_v10_0_dac_helper_funcs +ffffffff82b4d1f0 r dce_v10_0_dig_helper_funcs +ffffffff82b4d258 r dce_v10_0_ext_helper_funcs +ffffffff82b4d2c0 r dce_v10_0_audio_write_sad_regs.eld_reg_to_type +ffffffff82b4d2f0 r dce_v10_0_crtc_irq_funcs +ffffffff82b4d300 r dce_v10_0_pageflip_irq_funcs +ffffffff82b4d310 r dce_v10_0_hpd_irq_funcs +ffffffff82b4d320 r interrupt_status_offsets +ffffffff82b4d380 r dce_v10_0_crtc_funcs +ffffffff82b4d440 r dce_v10_0_crtc_helper_funcs +ffffffff82b4d4c0 r vga_control_regs +ffffffff82b4d4e0 r dig_offsets +ffffffff82b4d500 r pin_offsets +ffffffff82b4d520 r fiji_mgcg_cgcg_init +ffffffff82b4d540 r golden_settings_fiji_a10 +ffffffff82b4d570 r tonga_mgcg_cgcg_init +ffffffff82b4d590 r golden_settings_tonga_a11 +ffffffff82b4e000 r crtc_offsets +ffffffff82b4e020 r dce_v11_0_ip_funcs +ffffffff82b4e0c0 R dce_v11_0_ip_block +ffffffff82b4e0d8 R dce_v11_2_ip_block +ffffffff82b4e0f0 r dce_v11_0_display_funcs +ffffffff82b4e150 r hpd_offsets +ffffffff82b4e168 r dce_v11_0_encoder_funcs +ffffffff82b4e188 r dce_v11_0_dac_helper_funcs +ffffffff82b4e1f0 r dce_v11_0_dig_helper_funcs +ffffffff82b4e258 r dce_v11_0_ext_helper_funcs +ffffffff82b4e2c0 r dce_v11_0_audio_write_sad_regs.eld_reg_to_type +ffffffff82b4e2f0 r dce_v11_0_crtc_irq_funcs +ffffffff82b4e300 r dce_v11_0_pageflip_irq_funcs +ffffffff82b4e310 r dce_v11_0_hpd_irq_funcs +ffffffff82b4e320 r interrupt_status_offsets +ffffffff82b4e380 r dce_v11_0_crtc_funcs +ffffffff82b4e440 r dce_v11_0_crtc_helper_funcs +ffffffff82b4e4c0 r vga_control_regs +ffffffff82b4e4e0 r dig_offsets +ffffffff82b4e510 r cz_mgcg_cgcg_init +ffffffff82b4e530 r cz_golden_settings_a11 +ffffffff82b4e550 r stoney_golden_settings_a11 +ffffffff82b4e570 r polaris11_golden_settings_a11 +ffffffff82b4e5b0 r polaris10_golden_settings_a11 +ffffffff82b4f000 R df_v1_7_funcs +ffffffff82b4f070 r df_v1_7_channel_number +ffffffff82b50000 R df_v3_6_funcs +ffffffff82b50070 r df_v3_6_channel_number +ffffffff82b51000 R df_v4_3_funcs +ffffffff82b52000 r GC_BASE +ffffffff82b520a8 r HDP_BASE +ffffffff82b52150 r MMHUB_BASE +ffffffff82b521f8 r ATHUB_BASE +ffffffff82b522a0 r NBIO_BASE +ffffffff82b52348 r MP0_BASE +ffffffff82b523f0 r MP1_BASE +ffffffff82b52498 r VCN0_BASE +ffffffff82b52540 r DF_BASE +ffffffff82b525e8 r DCN_BASE +ffffffff82b52690 r OSSSYS_BASE +ffffffff82b52738 r SMUIO_BASE +ffffffff82b527e0 r THM_BASE +ffffffff82b53000 r gfx_v10_0_ip_funcs +ffffffff82b530a0 R gfx_v10_0_ip_block +ffffffff82b530b8 r gfx_v10_0_gfx_funcs +ffffffff82b53120 r golden_settings_gc_rlc_spm_10_0_nv10 +ffffffff82b593c0 r golden_settings_gc_rlc_spm_10_1_nv14 +ffffffff82b5cde0 r golden_settings_gc_rlc_spm_10_1_2_nv12 +ffffffff82b63080 r gfx_v10_0_kiq_pm4_funcs +ffffffff82b630c0 r gfx_v10_0_ring_funcs_kiq +ffffffff82b63200 r gfx_v10_0_ring_funcs_gfx +ffffffff82b63340 r gfx_v10_0_ring_funcs_compute +ffffffff82b63480 r gfx_v10_0_eop_irq_funcs +ffffffff82b63490 r gfx_v10_0_kiq_irq_funcs +ffffffff82b634a0 r gfx_v10_0_priv_reg_irq_funcs +ffffffff82b634b0 r gfx_v10_0_priv_inst_irq_funcs +ffffffff82b634c0 r gfx_v10_0_rlc_funcs +ffffffff82b63528 r gfx_v10_0_rlc_funcs_sriov +ffffffff82b63590 r gfx10_cs_data +ffffffff82b635b0 r gfx10_SECT_CONTEXT_defs +ffffffff82b63640 r gfx10_SECT_CONTEXT_def_1 +ffffffff82b639a0 r gfx10_SECT_CONTEXT_def_3 +ffffffff82b639b0 r gfx10_SECT_CONTEXT_def_4 +ffffffff82b63c28 r gfx10_SECT_CONTEXT_def_5 +ffffffff82b63c30 r gfx10_SECT_CONTEXT_def_6 +ffffffff82b63c40 r gfx10_SECT_CONTEXT_def_2 +ffffffff82b64080 r gfx10_SECT_CONTEXT_def_7 +ffffffff82b64190 r gfx10_SECT_CONTEXT_def_8 +ffffffff82b644c0 r golden_settings_gc_10_1 +ffffffff82b64880 r golden_settings_gc_10_0_nv10 +ffffffff82b64880 r golden_settings_gc_10_1_1 +ffffffff82b64c10 r golden_settings_gc_10_1_2 +ffffffff82b64c10 r golden_settings_gc_10_1_nv14 +ffffffff82b65000 r golden_settings_gc_10_1_2_nv12 +ffffffff82b65000 r golden_settings_gc_10_3 +ffffffff82b65408 r golden_settings_gc_10_3_sienna_cichlid +ffffffff82b65410 r golden_settings_gc_10_3_2 +ffffffff82b65800 r golden_settings_gc_10_3_vangogh +ffffffff82b65a60 r golden_settings_gc_10_3_3 +ffffffff82b65c40 r golden_settings_gc_10_3_4 +ffffffff82b65fa0 r golden_settings_gc_10_3_5 +ffffffff82b662a0 r golden_settings_gc_10_0_cyan_skillfish +ffffffff82b665d0 r golden_settings_gc_10_3_6 +ffffffff82b667e0 r golden_settings_gc_10_3_7 +ffffffff82b67000 r gfx_v11_0_ip_funcs +ffffffff82b670a0 R gfx_v11_0_ip_block +ffffffff82b670b8 r gfx_v11_0_gfx_funcs +ffffffff82b67118 r gfx_v11_0_kiq_pm4_funcs +ffffffff82b67158 r gfx_v11_0_ring_funcs_kiq +ffffffff82b67298 r gfx_v11_0_ring_funcs_gfx +ffffffff82b673d8 r gfx_v11_0_ring_funcs_compute +ffffffff82b67518 r gfx_v11_0_eop_irq_funcs +ffffffff82b67528 r gfx_v11_0_priv_reg_irq_funcs +ffffffff82b67538 r gfx_v11_0_priv_inst_irq_funcs +ffffffff82b67548 r gfx_v11_0_rlc_gc_fed_irq_funcs +ffffffff82b67558 r gfx_v11_0_rlc_funcs +ffffffff82b675c0 r gfx11_cs_data +ffffffff82b675e0 r gfx11_SECT_CONTEXT_defs +ffffffff82b67660 r gfx11_SECT_CONTEXT_def_1 +ffffffff82b679c0 r gfx11_SECT_CONTEXT_def_3 +ffffffff82b679d0 r gfx11_SECT_CONTEXT_def_5 +ffffffff82b679d8 r gfx11_SECT_CONTEXT_def_6 +ffffffff82b679e0 r gfx11_SECT_CONTEXT_def_2 +ffffffff82b67e20 r gfx11_SECT_CONTEXT_def_4 +ffffffff82b680a0 r gfx11_SECT_CONTEXT_def_7 +ffffffff82b68510 r golden_settings_gc_11_0_1 +ffffffff82b685f0 r golden_settings_gc_11_0 +ffffffff82b69000 r gfx_v8_0_ip_funcs +ffffffff82b690a0 R gfx_v8_0_ip_block +ffffffff82b690b8 R gfx_v8_1_ip_block +ffffffff82b690d0 r gfx_v8_0_gfx_funcs +ffffffff82b69130 r gfx_v8_0_ring_funcs_kiq +ffffffff82b69270 r gfx_v8_0_ring_funcs_gfx +ffffffff82b693b0 r gfx_v8_0_ring_funcs_compute +ffffffff82b694f0 r amdgpu_gds_reg_offset +ffffffff82b695f0 r gfx_v8_0_eop_irq_funcs +ffffffff82b69600 r gfx_v8_0_priv_reg_irq_funcs +ffffffff82b69610 r gfx_v8_0_priv_inst_irq_funcs +ffffffff82b69620 r gfx_v8_0_cp_ecc_error_irq_funcs +ffffffff82b69630 r gfx_v8_0_sq_irq_funcs +ffffffff82b69640 r sq_edc_source_names +ffffffff82b69678 r iceland_rlc_funcs +ffffffff82b696e0 r vi_cs_data +ffffffff82b69700 r vi_SECT_CONTEXT_defs +ffffffff82b69780 r vi_SECT_CONTEXT_def_1 +ffffffff82b69ad0 r vi_SECT_CONTEXT_def_3 +ffffffff82b69af0 r vi_SECT_CONTEXT_def_4 +ffffffff82b69d64 r vi_SECT_CONTEXT_def_5 +ffffffff82b69d6c r vi_SECT_CONTEXT_def_6 +ffffffff82b69d70 r vi_SECT_CONTEXT_def_2 +ffffffff82b6a1c0 r vi_SECT_CONTEXT_def_7 +ffffffff82b6a570 r vgpr_init_compute_shader +ffffffff82b6a680 r vgpr_init_regs +ffffffff82b6a710 r sgpr1_init_regs +ffffffff82b6a7a0 r sgpr2_init_regs +ffffffff82b6a830 r sec_ded_counter_registers +ffffffff82b6a8a0 r iceland_mgcg_cgcg_init +ffffffff82b6aba0 r golden_settings_iceland_a11 +ffffffff82b6ac60 r iceland_golden_common_all +ffffffff82b6acc0 r fiji_mgcg_cgcg_init +ffffffff82b6ae70 r golden_settings_fiji_a10 +ffffffff82b6af00 r fiji_golden_common_all +ffffffff82b6af80 r tonga_mgcg_cgcg_init +ffffffff82b6b310 r golden_settings_tonga_a11 +ffffffff82b6b3d0 r tonga_golden_common_all +ffffffff82b6b430 r golden_settings_vegam_a11 +ffffffff82b6b500 r vegam_golden_common_all +ffffffff82b6b550 r golden_settings_polaris11_a11 +ffffffff82b6b620 r polaris11_golden_common_all +ffffffff82b6b670 r golden_settings_polaris10_a11 +ffffffff82b6b740 r polaris10_golden_common_all +ffffffff82b6b7a0 r cz_mgcg_cgcg_init +ffffffff82b6bb30 r cz_golden_settings_a11 +ffffffff82b6bbc0 r cz_golden_common_all +ffffffff82b6bc20 r stoney_mgcg_cgcg_init +ffffffff82b6bc60 r stoney_golden_settings_a11 +ffffffff82b6bce0 r stoney_golden_common_all +ffffffff82b6c000 R gfx_v9_0_ras_ops +ffffffff82b6c040 r gfx_v9_0_ip_funcs +ffffffff82b6c0e0 R gfx_v9_0_ip_block +ffffffff82b6c100 r ras_gfx_subblocks +ffffffff82b6cb80 r gfx_v9_0_edc_counter_regs +ffffffff82b6cf20 r gfx_v9_0_ras_fields +ffffffff82b6e000 r gfx_v9_0_gfx_funcs +ffffffff82b6e060 r gfx_v9_0_kiq_pm4_funcs +ffffffff82b6e0a0 r gfx_v9_0_ring_funcs_kiq +ffffffff82b6e1e0 r gfx_v9_0_ring_funcs_gfx +ffffffff82b6e320 r gfx_v9_0_sw_ring_funcs_gfx +ffffffff82b6e460 r gfx_v9_0_ring_funcs_compute +ffffffff82b6e5a0 r gfx_v9_0_eop_irq_funcs +ffffffff82b6e5b0 r gfx_v9_0_priv_reg_irq_funcs +ffffffff82b6e5c0 r gfx_v9_0_priv_inst_irq_funcs +ffffffff82b6e5d0 r gfx_v9_0_cp_ecc_error_irq_funcs +ffffffff82b6e5e0 r gfx_v9_0_rlc_funcs +ffffffff82b6e650 r gfx9_cs_data +ffffffff82b6e670 r gfx9_SECT_CONTEXT_defs +ffffffff82b6e700 r gfx9_SECT_CONTEXT_def_1 +ffffffff82b6ea50 r gfx9_SECT_CONTEXT_def_3 +ffffffff82b6ea60 r gfx9_SECT_CONTEXT_def_4 +ffffffff82b6ecd4 r gfx9_SECT_CONTEXT_def_5 +ffffffff82b6ecdc r gfx9_SECT_CONTEXT_def_6 +ffffffff82b6ece0 r gfx9_SECT_CONTEXT_def_7 +ffffffff82b6edf0 r gfx9_SECT_CONTEXT_def_2 +ffffffff82b6f260 r gfx9_SECT_CONTEXT_def_8 +ffffffff82b6f4d0 r vgpr_init_compute_shader_arcturus +ffffffff82b6fd60 r vgpr_init_regs_arcturus +ffffffff82b6fef0 r vgpr_init_regs +ffffffff82b70080 r sgpr1_init_regs +ffffffff82b70210 r sgpr2_init_regs +ffffffff82b703a0 r golden_settings_gc_9_0 +ffffffff82b70580 r golden_settings_gc_9_0_vg10 +ffffffff82b70730 r golden_settings_gc_9_2_1 +ffffffff82b708b0 r golden_settings_gc_9_2_1_vg12 +ffffffff82b709f0 r golden_settings_gc_9_0_vg20 +ffffffff82b70b00 r golden_settings_gc_9_4_1_arct +ffffffff82b70c10 r golden_settings_gc_9_1 +ffffffff82b70e50 r golden_settings_gc_9_1_rv2 +ffffffff82b71020 r golden_settings_gc_9_1_rv1 +ffffffff82b710d0 r golden_settings_gc_9_1_rn +ffffffff82b711f0 r golden_settings_gc_9_x_common +ffffffff82b72000 R gfx_v9_4_ras_ops +ffffffff82b72040 r gfx_v9_4_edc_counter_regs +ffffffff82b72420 r gfx_v9_4_ras_fields +ffffffff82b74000 R vgpr_init_regs_aldebaran +ffffffff82b741b0 R sgpr112_init_regs_aldebaran +ffffffff82b74360 R sgpr96_init_regs_aldebaran +ffffffff82b74510 R sgpr64_init_regs_aldebaran +ffffffff82b746c0 r golden_settings_gc_9_4_2_alde +ffffffff82b74720 r golden_settings_gc_9_4_2_alde_die_0 +ffffffff82b747b0 r golden_settings_gc_9_4_2_alde_die_1 +ffffffff82b74840 r sgpr112_init_compute_shader_aldebaran +ffffffff82b74a60 r sgpr96_init_compute_shader_aldebaran +ffffffff82b74c50 r sgpr64_init_compute_shader_aldebaran +ffffffff82b74dc0 r vgpr_init_compute_shader_aldebaran +ffffffff82b756a0 r gfx_v9_4_2_edc_counter_regs +ffffffff82b75a20 r gfx_v9_4_2_ras_fields +ffffffff82b773c0 r gfx_v9_4_2_utc_blocks +ffffffff82b78000 r gfx_v9_4_3_ip_funcs +ffffffff82b780a0 R gfx_v9_4_3_ip_block +ffffffff82b780b8 r gfx_v9_4_3_kiq_pm4_funcs +ffffffff82b780f8 r gfx_v9_4_3_ring_funcs_kiq +ffffffff82b78238 r gfx_v9_4_3_ring_funcs_compute +ffffffff82b78378 r gfx_v9_4_3_eop_irq_funcs +ffffffff82b78388 r gfx_v9_4_3_priv_reg_irq_funcs +ffffffff82b78398 r gfx_v9_4_3_priv_inst_irq_funcs +ffffffff82b783a8 r gfx_v9_4_3_rlc_funcs +ffffffff82b78410 r gfx_v9_4_3_gfx_funcs +ffffffff82b78470 r gfx_v9_4_3_ce_reg_list +ffffffff82b78800 r gfx_v9_4_3_ras_mem_list_array +ffffffff82b78960 r gfx_v9_4_3_ue_reg_list +ffffffff82b78d20 r gfx_v9_4_3_ras_cp_mem_list +ffffffff82b78d70 r gfx_v9_4_3_ras_gcea_mem_list +ffffffff82b78eb0 r gfx_v9_4_3_ras_gc_cane_mem_list +ffffffff82b78ec0 r gfx_v9_4_3_ras_gcutcl2_mem_list +ffffffff82b78ed0 r gfx_v9_4_3_ras_gds_mem_list +ffffffff82b78ee0 r gfx_v9_4_3_ras_lds_mem_list +ffffffff82b79100 r gfx_v9_4_3_ras_rlc_mem_list +ffffffff82b79180 r gfx_v9_4_3_ras_sp_mem_list +ffffffff82b79190 r gfx_v9_4_3_ras_spi_mem_list +ffffffff82b791d0 r gfx_v9_4_3_ras_sqc_mem_list +ffffffff82b79340 r gfx_v9_4_3_ras_sq_mem_list +ffffffff82b79380 r gfx_v9_4_3_ras_ta_mem_list +ffffffff82b793d0 r gfx_v9_4_3_ras_tcc_mem_list +ffffffff82b793e0 r gfx_v9_4_3_ras_tca_mem_list +ffffffff82b793f0 r gfx_v9_4_3_ras_tci_mem_list +ffffffff82b79400 r gfx_v9_4_3_ras_tcp_mem_list +ffffffff82b79590 r gfx_v9_4_3_ras_td_mem_list +ffffffff82b795c0 r gfx_v9_4_3_ras_tcx_mem_list +ffffffff82b79b40 r gfx_v9_4_3_ras_atc_l2_mem_list +ffffffff82b79b50 r gfx_v9_4_3_ras_utcl2_mem_list +ffffffff82b79b60 r gfx_v9_4_3_ras_vml2_mem_list +ffffffff82b79b70 r gfx_v9_4_3_ras_vml2_walker_mem_list +ffffffff82b7a000 R gfxhub_v1_0_funcs +ffffffff82b7b000 R gfxhub_v1_2_funcs +ffffffff82b7c000 R gfxhub_v2_0_funcs +ffffffff82b7c060 r gfxhub_v2_0_vmhub_funcs ffffffff82b7c070 r gfxhub_client_ids -ffffffff82b7d000 R gfxhub_v3_0_3_funcs -ffffffff82b7d060 r gfxhub_v3_0_3_vmhub_funcs +ffffffff82b7d000 R gfxhub_v2_1_funcs +ffffffff82b7d060 r gfxhub_v2_1_vmhub_funcs ffffffff82b7d070 r gfxhub_client_ids -ffffffff82b7e000 R gmc_v10_0_ip_funcs -ffffffff82b7e0a0 R gmc_v10_0_ip_block -ffffffff82b7e0b8 r gmc_v10_0_gmc_funcs -ffffffff82b7e110 r gmc_v10_0_irq_funcs -ffffffff82b7e120 r gmc_v10_0_ecc_funcs -ffffffff82b7f000 R gmc_v11_0_ip_funcs -ffffffff82b7f0a0 R gmc_v11_0_ip_block -ffffffff82b7f0b8 r gmc_v11_0_gmc_funcs -ffffffff82b7f110 r gmc_v11_0_irq_funcs -ffffffff82b7f120 r gmc_v11_0_ecc_funcs -ffffffff82b80000 r gmc_v7_0_ip_funcs -ffffffff82b800a0 R gmc_v7_0_ip_block -ffffffff82b800b8 R gmc_v7_4_ip_block -ffffffff82b800d0 r gmc_v7_0_gmc_funcs -ffffffff82b80128 r gmc_v7_0_irq_funcs -ffffffff82b80138 r iceland_mgcg_cgcg_init -ffffffff82b80150 r golden_settings_iceland_a11 -ffffffff82b80180 r mc_cg_registers -ffffffff82b801b0 r mc_cg_en -ffffffff82b801e0 r mc_cg_ls_en -ffffffff82b81000 r gmc_v8_0_ip_funcs -ffffffff82b810a0 R gmc_v8_0_ip_block -ffffffff82b810b8 R gmc_v8_1_ip_block -ffffffff82b810d0 R gmc_v8_5_ip_block -ffffffff82b810e8 r gmc_v8_0_gmc_funcs -ffffffff82b81140 r gmc_v8_0_irq_funcs -ffffffff82b81150 r fiji_mgcg_cgcg_init -ffffffff82b81160 r golden_settings_fiji_a10 -ffffffff82b81190 r tonga_mgcg_cgcg_init -ffffffff82b811a0 r golden_settings_tonga_a11 -ffffffff82b81200 r golden_settings_polaris11_a11 -ffffffff82b81230 r golden_settings_polaris10_a11 -ffffffff82b8126c r cz_mgcg_cgcg_init -ffffffff82b81280 r stoney_mgcg_cgcg_init -ffffffff82b812a0 r golden_settings_stoney_common -ffffffff82b82000 R gmc_v9_0_ip_funcs -ffffffff82b820a0 R gmc_v9_0_ip_block -ffffffff82b820b8 r gmc_v9_0_gmc_funcs -ffffffff82b82110 r gmc_v9_0_irq_funcs -ffffffff82b82120 r gmc_v9_0_ecc_funcs -ffffffff82b82130 r gfxhub_client_ids -ffffffff82b821a0 r mmhub_client_ids_vega10 -ffffffff82b82490 r mmhub_client_ids_vega12 -ffffffff82b82790 r mmhub_client_ids_vega20 -ffffffff82b82a80 r mmhub_client_ids_arcturus -ffffffff82b84290 r mmhub_client_ids_raven -ffffffff82b84450 r mmhub_client_ids_renoir -ffffffff82b84640 r mmhub_client_ids_aldebaran -ffffffff82b85e50 r ecc_umc_mcumc_ctrl_addrs -ffffffff82b85ed0 r ecc_umc_mcumc_ctrl_mask_addrs -ffffffff82b85f50 r golden_settings_mmhub_1_0_0 -ffffffff82b85f80 r golden_settings_athub_1_0_0 -ffffffff82b86000 R hdp_v4_0_funcs -ffffffff82b87000 R hdp_v5_0_funcs -ffffffff82b88000 R hdp_v5_2_funcs -ffffffff82b89000 R hdp_v6_0_funcs -ffffffff82b8a000 r iceland_ih_ip_funcs -ffffffff82b8a0a0 R iceland_ih_ip_block -ffffffff82b8a0b8 r iceland_ih_funcs -ffffffff82b8b000 r ih_v6_0_ip_funcs -ffffffff82b8b0a0 R ih_v6_0_ip_block -ffffffff82b8b0b8 r ih_v6_0_funcs -ffffffff82b8b0d8 r ih_v6_0_self_irq_funcs -ffffffff82b8c000 r ih_v6_1_ip_funcs -ffffffff82b8c0a0 R ih_v6_1_ip_block -ffffffff82b8c0b8 r ih_v6_1_funcs -ffffffff82b8c0d8 r ih_v6_1_self_irq_funcs -ffffffff82b8d000 R gfx_v11_0_imu_funcs -ffffffff82b8d030 r imu_rlc_ram_golden_11 -ffffffff82b8d680 r imu_rlc_ram_golden_11_0_2 -ffffffff82b8e000 r imu_rlc_ram_golden_11_0_3 -ffffffff82b8f000 r jpeg_v1_0_decode_ring_vm_funcs -ffffffff82b8f140 r jpeg_v1_0_irq_funcs -ffffffff82b90000 r jpeg_v2_0_ip_funcs -ffffffff82b900a0 R jpeg_v2_0_ip_block -ffffffff82b900b8 r jpeg_v2_0_dec_ring_vm_funcs -ffffffff82b901f8 r jpeg_v2_0_irq_funcs -ffffffff82b91000 r jpeg_v2_5_ip_funcs -ffffffff82b910a0 R jpeg_v2_5_ip_block -ffffffff82b910b8 r jpeg_v2_6_ip_funcs -ffffffff82b91158 R jpeg_v2_6_ip_block -ffffffff82b91170 R jpeg_v2_6_ras_hw_ops -ffffffff82b911b0 r jpeg_v2_5_dec_ring_vm_funcs -ffffffff82b912f0 r jpeg_v2_6_dec_ring_vm_funcs -ffffffff82b91430 r jpeg_v2_5_irq_funcs -ffffffff82b91440 r jpeg_v2_6_ras_irq_funcs -ffffffff82b92000 r jpeg_v3_0_ip_funcs -ffffffff82b920a0 R jpeg_v3_0_ip_block -ffffffff82b920b8 r jpeg_v3_0_dec_ring_vm_funcs -ffffffff82b921f8 r jpeg_v3_0_irq_funcs -ffffffff82b93000 r jpeg_v4_0_ip_funcs -ffffffff82b930a0 R jpeg_v4_0_ip_block -ffffffff82b930b8 R jpeg_v4_0_ras_hw_ops -ffffffff82b930f8 r jpeg_v4_0_dec_ring_vm_funcs -ffffffff82b93238 r jpeg_v4_0_irq_funcs -ffffffff82b93248 r jpeg_v4_0_ras_irq_funcs -ffffffff82b94000 r jpeg_v4_0_3_ip_funcs -ffffffff82b940a0 R jpeg_v4_0_3_ip_block -ffffffff82b940b8 r jpeg_v4_0_3_dec_ring_vm_funcs -ffffffff82b941f8 r jpeg_v4_0_3_irq_funcs -ffffffff82b94208 r jpeg_v4_0_3_ras_hw_ops -ffffffff82b94250 r jpeg_v4_0_3_ue_reg_list -ffffffff82b95000 R lsdma_v6_0_funcs -ffffffff82b96000 r mca_v3_0_mp0_hw_ops -ffffffff82b96040 r mca_v3_0_mp1_hw_ops -ffffffff82b96080 r mca_v3_0_mpio_hw_ops -ffffffff82b97000 r mes_v10_1_ip_funcs -ffffffff82b970a0 R mes_v10_1_ip_block -ffffffff82b970b8 r mes_v10_1_funcs -ffffffff82b970e8 r mes_v10_1_ring_funcs -ffffffff82b98000 r mes_v11_0_ip_funcs -ffffffff82b980a0 R mes_v11_0_ip_block -ffffffff82b980b8 r mes_v11_0_funcs -ffffffff82b980e8 r mes_v11_0_ring_funcs -ffffffff82b99000 R mmhub_v1_0_funcs -ffffffff82b99050 r mmhub_v1_0_edc_cnt_regs -ffffffff82b990c0 r mmhub_v1_0_ras_fields -ffffffff82b9a000 R mmhub_v1_7_funcs -ffffffff82b9a050 r mmhub_v1_7_edc_cnt_regs -ffffffff82b9a250 r mmhub_v1_7_ras_fields -ffffffff82b9b9c0 r mmhub_v1_7_ea_err_status_regs -ffffffff82b9c000 R mmhub_v1_8_funcs -ffffffff82b9c050 r mmhub_v1_8_ras_hw_ops -ffffffff82b9c090 r mmhub_v1_8_ce_reg_list -ffffffff82b9c180 r mmhub_v1_8_ras_memory_list -ffffffff82b9c2b0 r mmhub_v1_8_ue_reg_list -ffffffff82b9d000 R mmhub_v2_0_funcs -ffffffff82b9d050 r mmhub_v2_0_vmhub_funcs -ffffffff82b9d060 r mmhub_client_ids_navi1x -ffffffff82b9d190 r mmhub_client_ids_sienna_cichlid -ffffffff82b9d450 r mmhub_client_ids_beige_goby -ffffffff82b9e000 R mmhub_v2_3_funcs -ffffffff82b9e050 r mmhub_v2_3_vmhub_funcs -ffffffff82b9e060 r mmhub_client_ids_vangogh -ffffffff82b9f000 R mmhub_v3_0_funcs -ffffffff82b9f050 r mmhub_v3_0_vmhub_funcs -ffffffff82b9f060 r mmhub_client_ids_v3_0_0 -ffffffff82ba0000 R mmhub_v3_0_1_funcs -ffffffff82ba0050 r mmhub_v3_0_1_vmhub_funcs -ffffffff82ba0060 r mmhub_client_ids_v3_0_1 -ffffffff82ba1000 R mmhub_v3_0_2_funcs -ffffffff82ba1050 r mmhub_v3_0_2_vmhub_funcs -ffffffff82ba1060 r mmhub_client_ids_v3_0_2 -ffffffff82ba2000 R mmhub_v9_4_ras_hw_ops -ffffffff82ba2040 R mmhub_v9_4_funcs -ffffffff82ba2090 r mmhub_v9_4_edc_cnt_regs -ffffffff82ba2330 r mmhub_v9_4_ras_fields -ffffffff82ba43b0 r mmhub_v9_4_err_status_regs -ffffffff82ba5000 r xgpu_ai_mailbox_ack_irq_funcs -ffffffff82ba5010 r xgpu_ai_mailbox_rcv_irq_funcs -ffffffff82ba5020 R xgpu_ai_virt_ops -ffffffff82ba6000 r xgpu_nv_mailbox_ack_irq_funcs -ffffffff82ba6010 r xgpu_nv_mailbox_rcv_irq_funcs -ffffffff82ba6020 R xgpu_nv_virt_ops -ffffffff82ba7000 r xgpu_fiji_mgcg_cgcg_init -ffffffff82ba7240 r xgpu_fiji_golden_settings_a10 -ffffffff82ba7370 r xgpu_fiji_golden_common_all -ffffffff82ba73f0 r xgpu_tonga_mgcg_cgcg_init -ffffffff82ba7810 r xgpu_tonga_golden_settings_a11 -ffffffff82ba79d0 r xgpu_tonga_golden_common_all -ffffffff82ba7a28 r xgpu_vi_mailbox_ack_irq_funcs -ffffffff82ba7a38 r xgpu_vi_mailbox_rcv_irq_funcs -ffffffff82ba7a48 R xgpu_vi_virt_ops -ffffffff82ba8000 r navi10_ih_ip_funcs -ffffffff82ba80a0 R navi10_ih_ip_block -ffffffff82ba80b8 r navi10_ih_funcs -ffffffff82ba80d8 r navi10_ih_self_irq_funcs -ffffffff82ba9000 R nbio_v2_3_hdp_flush_reg -ffffffff82ba9048 R nbio_v2_3_funcs -ffffffff82baa000 R nbio_v4_3_hdp_flush_reg -ffffffff82baa048 R nbio_v4_3_funcs -ffffffff82baa158 R nbio_v4_3_sriov_funcs -ffffffff82baa268 r nbio_v4_3_ras_err_event_athub_irq_funcs -ffffffff82bab000 R nbio_v6_1_hdp_flush_reg -ffffffff82bab048 R nbio_v6_1_funcs -ffffffff82bac000 R nbio_v7_0_hdp_flush_reg -ffffffff82bac048 R nbio_v7_0_funcs -ffffffff82bad000 R nbio_v7_2_hdp_flush_reg -ffffffff82bad048 R nbio_v7_2_funcs -ffffffff82bae000 R nbio_v7_4_hdp_flush_reg -ffffffff82bae048 R nbio_v7_4_ras_hw_ops -ffffffff82bae088 R nbio_v7_4_funcs -ffffffff82bae198 r nbio_v7_4_ras_controller_irq_funcs -ffffffff82bae1a8 r nbio_v7_4_ras_err_event_athub_irq_funcs -ffffffff82baf000 R nbio_v7_7_hdp_flush_reg -ffffffff82baf048 R nbio_v7_7_funcs -ffffffff82bb0000 R nbio_v7_9_hdp_flush_reg -ffffffff82bb0048 R nbio_v7_9_funcs -ffffffff82bb0158 R nbio_v7_9_ras_hw_ops -ffffffff82bb0198 r nbio_v7_9_ras_controller_irq_funcs -ffffffff82bb01a8 r nbio_v7_9_ras_err_event_athub_irq_funcs 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psp_v12_0_funcs -ffffffff82bb6000 r psp_v13_0_funcs -ffffffff82bb7000 r psp_v13_0_4_funcs -ffffffff82bb8000 r psp_v3_1_funcs -ffffffff82bb9000 r sdma_v2_4_ip_funcs -ffffffff82bb90a0 R sdma_v2_4_ip_block -ffffffff82bb90b8 r sdma_v2_4_ring_funcs -ffffffff82bb91f8 r sdma_v2_4_buffer_funcs -ffffffff82bb9218 r sdma_v2_4_vm_pte_funcs -ffffffff82bb9238 r sdma_v2_4_trap_irq_funcs -ffffffff82bb9248 r sdma_v2_4_illegal_inst_irq_funcs -ffffffff82bb9260 r iceland_mgcg_cgcg_init -ffffffff82bb9280 r golden_settings_iceland_a11 -ffffffff82bba000 r sdma_v3_0_ip_funcs -ffffffff82bba0a0 R sdma_v3_0_ip_block -ffffffff82bba0b8 R sdma_v3_1_ip_block -ffffffff82bba0d0 r sdma_v3_0_ring_funcs -ffffffff82bba210 r sdma_v3_0_buffer_funcs -ffffffff82bba230 r sdma_v3_0_vm_pte_funcs -ffffffff82bba250 r sdma_v3_0_trap_irq_funcs -ffffffff82bba260 r sdma_v3_0_illegal_inst_irq_funcs -ffffffff82bba270 r fiji_mgcg_cgcg_init -ffffffff82bba290 r golden_settings_fiji_a10 -ffffffff82bba2f0 r tonga_mgcg_cgcg_init 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golden_settings_sdma_4 -ffffffff82bbb690 r golden_settings_sdma_vg10 -ffffffff82bbb740 r golden_settings_sdma_vg12 -ffffffff82bbb7f0 r golden_settings_sdma0_4_2_init -ffffffff82bbb810 r golden_settings_sdma0_4_2 -ffffffff82bbbaa0 r golden_settings_sdma1_4_2 -ffffffff82bbbd30 r golden_settings_sdma_arct -ffffffff82bbc030 r golden_settings_sdma_aldebaran -ffffffff82bbc1a0 r golden_settings_sdma_4_1 -ffffffff82bbc2b0 r golden_settings_sdma_rv2 -ffffffff82bbc2e0 r golden_settings_sdma_rv1 -ffffffff82bbc310 r golden_settings_sdma_4_3 -ffffffff82bbc400 r sdma_v4_0_ras_fields -ffffffff82bbd000 R sdma_v4_4_ras_hw_ops -ffffffff82bbd040 r sdma_v4_4_ras_fields -ffffffff82bbe000 R sdma_v4_4_2_ip_funcs -ffffffff82bbe0a0 R sdma_v4_4_2_ip_block -ffffffff82bbe0b8 r sdma_v4_4_2_ring_funcs -ffffffff82bbe1f8 r sdma_v4_4_2_page_ring_funcs -ffffffff82bbe338 r sdma_v4_4_2_buffer_funcs -ffffffff82bbe358 r sdma_v4_4_2_vm_pte_funcs -ffffffff82bbe378 r sdma_v4_4_2_trap_irq_funcs -ffffffff82bbe388 r sdma_v4_4_2_illegal_inst_irq_funcs -ffffffff82bbe398 r sdma_v4_4_2_ecc_irq_funcs -ffffffff82bbe3a8 r sdma_v4_4_2_vm_hole_irq_funcs -ffffffff82bbe3b8 r sdma_v4_4_2_doorbell_invalid_irq_funcs -ffffffff82bbe3c8 r sdma_v4_4_2_pool_timeout_irq_funcs -ffffffff82bbe3d8 r sdma_v4_4_2_srbm_write_irq_funcs -ffffffff82bbe3e8 r sdma_v4_4_2_ras_hw_ops -ffffffff82bbe430 r sdma_v4_2_2_ue_reg_list -ffffffff82bbe460 r sdma_v4_4_2_ras_memory_list -ffffffff82bbf000 R sdma_v5_0_ip_funcs -ffffffff82bbf0a0 R sdma_v5_0_ip_block -ffffffff82bbf0b8 r sdma_v5_0_ring_funcs -ffffffff82bbf1f8 r sdma_v5_0_buffer_funcs -ffffffff82bbf218 r sdma_v5_0_vm_pte_funcs -ffffffff82bbf238 r sdma_v5_0_trap_irq_funcs -ffffffff82bbf248 r sdma_v5_0_illegal_inst_irq_funcs -ffffffff82bbf260 r golden_settings_sdma_5 -ffffffff82bbf4a0 r golden_settings_sdma_nv10 -ffffffff82bbf4d0 r golden_settings_sdma_nv14 -ffffffff82bbf500 r golden_settings_sdma_5_sriov -ffffffff82bbf6e0 r golden_settings_sdma_nv12 -ffffffff82bbf770 r golden_settings_sdma_cyan_skillfish -ffffffff82bc0000 R sdma_v5_2_ip_funcs -ffffffff82bc00a0 R sdma_v5_2_ip_block -ffffffff82bc00b8 r sdma_v5_2_ring_funcs -ffffffff82bc01f8 r sdma_v5_2_buffer_funcs -ffffffff82bc0218 r sdma_v5_2_vm_pte_funcs -ffffffff82bc0238 r sdma_v5_2_trap_irq_funcs -ffffffff82bc0248 r sdma_v5_2_illegal_inst_irq_funcs -ffffffff82bc1000 R sdma_v6_0_ip_funcs -ffffffff82bc10a0 R sdma_v6_0_ip_block -ffffffff82bc10b8 r sdma_v6_0_ring_funcs -ffffffff82bc11f8 r sdma_v6_0_buffer_funcs -ffffffff82bc1218 r sdma_v6_0_vm_pte_funcs -ffffffff82bc1238 r sdma_v6_0_trap_irq_funcs -ffffffff82bc1248 r sdma_v6_0_illegal_inst_irq_funcs -ffffffff82bc2000 r smu_v11_0_i2c_algo -ffffffff82bc2010 r smu_v11_0_i2c_i2c_lock_ops -ffffffff82bc2028 r smu_v11_0_i2c_control_quirks -ffffffff82bc3000 R smuio_v11_0_funcs -ffffffff82bc4000 R smuio_v11_0_6_funcs -ffffffff82bc5000 R smuio_v13_0_funcs -ffffffff82bc6000 R smuio_v13_0_3_funcs -ffffffff82bc7000 R smuio_v13_0_6_funcs -ffffffff82bc8000 R smuio_v9_0_funcs -ffffffff82bc9000 r soc15_common_ip_funcs -ffffffff82bc90a0 R vega10_common_ip_block -ffffffff82bc90b8 r soc15_asic_funcs -ffffffff82bc9178 r vega20_asic_funcs -ffffffff82bc9238 r aqua_vanjaram_asic_funcs -ffffffff82bc9300 r soc15_allowed_read_registers -ffffffff82bc9490 r vega_video_codecs_encode -ffffffff82bc94a0 r vega_video_codecs_decode -ffffffff82bc94b0 r rv_video_codecs_decode -ffffffff82bc94c0 r rn_video_codecs_decode -ffffffff82bc94d0 r vcn_4_0_3_video_codecs_encode -ffffffff82bc94e0 r vcn_4_0_3_video_codecs_decode -ffffffff82bc94f0 r vega_video_codecs_encode_array -ffffffff82bc9520 r vega_video_codecs_decode_array -ffffffff82bc95a0 r rv_video_codecs_decode_array -ffffffff82bc9630 r rn_video_codecs_decode_array -ffffffff82bc96c0 r vcn_4_0_3_video_codecs_decode_array -ffffffff82bca000 r soc21_common_ip_funcs -ffffffff82bca0a0 R soc21_common_ip_block -ffffffff82bca0b8 r soc21_asic_funcs -ffffffff82bca180 r soc21_allowed_read_registers -ffffffff82bca300 r vcn_4_0_0_video_codecs_encode_vcn1 -ffffffff82bca310 r vcn_4_0_0_video_codecs_decode_vcn1 -ffffffff82bca320 r vcn_4_0_0_video_codecs_encode_vcn0 -ffffffff82bca330 r vcn_4_0_0_video_codecs_decode_vcn0 -ffffffff82bca340 r vcn_4_0_0_video_codecs_encode_array_vcn1 -ffffffff82bca370 r vcn_4_0_0_video_codecs_decode_array_vcn1 -ffffffff82bca3c0 r vcn_4_0_0_video_codecs_encode_array_vcn0 -ffffffff82bca400 r vcn_4_0_0_video_codecs_decode_array_vcn0 -ffffffff82bcb000 r tonga_ih_ip_funcs -ffffffff82bcb0a0 R tonga_ih_ip_block -ffffffff82bcb0b8 r tonga_ih_funcs -ffffffff82bcc000 R umc_v6_0_funcs -ffffffff82bcd000 R umc_v6_1_channel_idx_tbl -ffffffff82bcd080 R umc_v6_1_ras_hw_ops -ffffffff82bce000 R umc_v6_7_channel_idx_tbl_second -ffffffff82bce080 R umc_v6_7_channel_idx_tbl_first -ffffffff82bce100 R umc_v6_7_ras_hw_ops -ffffffff82bcf000 R umc_v8_10_channelnum_map_colbit_table -ffffffff82bcf040 R umc_v8_10_channel_idx_tbl_ext0 -ffffffff82bcf080 R umc_v8_10_channel_idx_tbl -ffffffff82bcf0e0 R umc_v8_10_ras_hw_ops -ffffffff82bd0000 R umc_v8_7_channel_idx_tbl -ffffffff82bd0040 R umc_v8_7_ras_hw_ops -ffffffff82bd1000 r uvd_v5_0_ip_funcs -ffffffff82bd10a0 R uvd_v5_0_ip_block -ffffffff82bd10b8 r uvd_v5_0_ring_funcs -ffffffff82bd11f8 r uvd_v5_0_irq_funcs -ffffffff82bd2000 r uvd_v6_0_ip_funcs -ffffffff82bd20a0 R uvd_v6_0_ip_block -ffffffff82bd20b8 R uvd_v6_2_ip_block -ffffffff82bd20d0 R uvd_v6_3_ip_block -ffffffff82bd20e8 r uvd_v6_0_ring_vm_funcs -ffffffff82bd2228 r uvd_v6_0_ring_phys_funcs -ffffffff82bd2368 r uvd_v6_0_enc_ring_vm_funcs -ffffffff82bd24a8 r uvd_v6_0_irq_funcs -ffffffff82bd3000 R uvd_v7_0_ip_funcs -ffffffff82bd30a0 R uvd_v7_0_ip_block -ffffffff82bd30b8 r uvd_v7_0_ring_vm_funcs -ffffffff82bd31f8 r uvd_v7_0_enc_ring_vm_funcs -ffffffff82bd3338 r uvd_v7_0_irq_funcs -ffffffff82bd4000 r vce_v3_0_ip_funcs -ffffffff82bd40a0 R vce_v3_0_ip_block -ffffffff82bd40b8 R vce_v3_1_ip_block -ffffffff82bd40d0 R vce_v3_4_ip_block -ffffffff82bd40e8 r vce_v3_0_ring_vm_funcs -ffffffff82bd4228 r vce_v3_0_ring_phys_funcs -ffffffff82bd4368 r vce_v3_0_irq_funcs -ffffffff82bd5000 R vce_v4_0_ip_funcs -ffffffff82bd50a0 R vce_v4_0_ip_block -ffffffff82bd50b8 r vce_v4_0_ring_vm_funcs -ffffffff82bd51f8 r vce_v4_0_irq_funcs -ffffffff82bd6000 r vcn_v1_0_ip_funcs -ffffffff82bd60a0 R vcn_v1_0_ip_block -ffffffff82bd60b8 r vcn_v1_0_dec_ring_vm_funcs -ffffffff82bd61f8 r vcn_v1_0_enc_ring_vm_funcs -ffffffff82bd6338 r vcn_v1_0_irq_funcs -ffffffff82bd7000 r vcn_v2_0_ip_funcs -ffffffff82bd70a0 R vcn_v2_0_ip_block -ffffffff82bd70b8 r vcn_v2_0_dec_ring_vm_funcs -ffffffff82bd71f8 r vcn_v2_0_enc_ring_vm_funcs -ffffffff82bd7338 r vcn_v2_0_irq_funcs -ffffffff82bd8000 r vcn_v2_5_ip_funcs -ffffffff82bd80a0 R vcn_v2_5_ip_block -ffffffff82bd80b8 r vcn_v2_6_ip_funcs -ffffffff82bd8158 R vcn_v2_6_ip_block -ffffffff82bd8170 R vcn_v2_6_ras_hw_ops -ffffffff82bd81b0 r vcn_v2_5_dec_ring_vm_funcs -ffffffff82bd82f0 r vcn_v2_5_enc_ring_vm_funcs -ffffffff82bd8430 r vcn_v2_5_irq_funcs -ffffffff82bd8440 r vcn_v2_6_ras_irq_funcs -ffffffff82bd9000 r vcn_v3_0_ip_funcs -ffffffff82bd90a0 R vcn_v3_0_ip_block -ffffffff82bd90b8 r vcn_v3_0_dec_ring_vm_funcs -ffffffff82bd91f8 r vcn_v3_0_enc_ring_vm_funcs -ffffffff82bd9338 r vcn_v3_0_irq_funcs -ffffffff82bda000 r vcn_v4_0_ip_funcs -ffffffff82bda0a0 R vcn_v4_0_ip_block -ffffffff82bda0b8 R vcn_v4_0_ras_hw_ops -ffffffff82bda0f8 r vcn_v4_0_irq_funcs -ffffffff82bda108 r vcn_v4_0_ras_irq_funcs -ffffffff82bdb000 r vcn_v4_0_3_ip_funcs -ffffffff82bdb0a0 R vcn_v4_0_3_ip_block -ffffffff82bdb0b8 r vcn_v4_0_3_unified_ring_vm_funcs -ffffffff82bdb1f8 r vcn_v4_0_3_irq_funcs -ffffffff82bdb208 r vcn_v4_0_3_ras_hw_ops -ffffffff82bdb250 r vcn_v4_0_3_ue_reg_list -ffffffff82bdc000 R vega10_ih_ip_funcs -ffffffff82bdc0a0 R vega10_ih_ip_block -ffffffff82bdc0b8 r vega10_ih_funcs -ffffffff82bdc0d8 r vega10_ih_self_irq_funcs -ffffffff82bdd000 r GC_BASE -ffffffff82bdd064 r HDP_BASE -ffffffff82bdd0c8 r MMHUB_BASE -ffffffff82bdd12c r ATHUB_BASE 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gmc_v10_0_irq_funcs +ffffffff82b80120 r gmc_v10_0_ecc_funcs +ffffffff82b81000 R gmc_v11_0_ip_funcs +ffffffff82b810a0 R gmc_v11_0_ip_block +ffffffff82b810b8 r gmc_v11_0_gmc_funcs +ffffffff82b81110 r gmc_v11_0_irq_funcs +ffffffff82b81120 r gmc_v11_0_ecc_funcs +ffffffff82b82000 r gmc_v7_0_ip_funcs +ffffffff82b820a0 R gmc_v7_0_ip_block +ffffffff82b820b8 R gmc_v7_4_ip_block +ffffffff82b820d0 r gmc_v7_0_gmc_funcs +ffffffff82b82128 r gmc_v7_0_irq_funcs +ffffffff82b82138 r iceland_mgcg_cgcg_init +ffffffff82b82150 r golden_settings_iceland_a11 +ffffffff82b82180 r mc_cg_registers +ffffffff82b821b0 r mc_cg_en +ffffffff82b821e0 r mc_cg_ls_en +ffffffff82b83000 r gmc_v8_0_ip_funcs +ffffffff82b830a0 R gmc_v8_0_ip_block +ffffffff82b830b8 R gmc_v8_1_ip_block +ffffffff82b830d0 R gmc_v8_5_ip_block +ffffffff82b830e8 r gmc_v8_0_gmc_funcs +ffffffff82b83140 r gmc_v8_0_irq_funcs +ffffffff82b83150 r fiji_mgcg_cgcg_init +ffffffff82b83160 r golden_settings_fiji_a10 +ffffffff82b83190 r tonga_mgcg_cgcg_init +ffffffff82b831a0 r golden_settings_tonga_a11 +ffffffff82b83200 r golden_settings_polaris11_a11 +ffffffff82b83230 r golden_settings_polaris10_a11 +ffffffff82b8326c r cz_mgcg_cgcg_init +ffffffff82b83280 r stoney_mgcg_cgcg_init +ffffffff82b832a0 r golden_settings_stoney_common +ffffffff82b84000 R gmc_v9_0_ip_funcs +ffffffff82b840a0 R gmc_v9_0_ip_block +ffffffff82b840b8 r gmc_v9_0_gmc_funcs +ffffffff82b84110 r gmc_v9_0_irq_funcs +ffffffff82b84120 r gmc_v9_0_ecc_funcs +ffffffff82b84130 r gfxhub_client_ids +ffffffff82b841a0 r mmhub_client_ids_vega10 +ffffffff82b84490 r mmhub_client_ids_vega12 +ffffffff82b84790 r mmhub_client_ids_vega20 +ffffffff82b84a80 r mmhub_client_ids_arcturus +ffffffff82b86290 r mmhub_client_ids_raven +ffffffff82b86450 r mmhub_client_ids_renoir +ffffffff82b86640 r mmhub_client_ids_aldebaran +ffffffff82b87e50 r ecc_umc_mcumc_ctrl_addrs +ffffffff82b87ed0 r ecc_umc_mcumc_ctrl_mask_addrs +ffffffff82b87f50 r golden_settings_mmhub_1_0_0 +ffffffff82b87f80 r golden_settings_athub_1_0_0 +ffffffff82b88000 R hdp_v4_0_funcs +ffffffff82b89000 R hdp_v5_0_funcs +ffffffff82b8a000 R hdp_v5_2_funcs +ffffffff82b8b000 R hdp_v6_0_funcs +ffffffff82b8c000 r iceland_ih_ip_funcs +ffffffff82b8c0a0 R iceland_ih_ip_block +ffffffff82b8c0b8 r iceland_ih_funcs +ffffffff82b8d000 r ih_v6_0_ip_funcs +ffffffff82b8d0a0 R ih_v6_0_ip_block +ffffffff82b8d0b8 r ih_v6_0_funcs +ffffffff82b8d0d8 r ih_v6_0_self_irq_funcs +ffffffff82b8e000 r ih_v6_1_ip_funcs +ffffffff82b8e0a0 R ih_v6_1_ip_block +ffffffff82b8e0b8 r ih_v6_1_funcs +ffffffff82b8e0d8 r ih_v6_1_self_irq_funcs +ffffffff82b8f000 R gfx_v11_0_imu_funcs +ffffffff82b8f030 r imu_rlc_ram_golden_11 +ffffffff82b8f680 r imu_rlc_ram_golden_11_0_2 +ffffffff82b90000 r imu_rlc_ram_golden_11_0_3 +ffffffff82b91000 r jpeg_v1_0_decode_ring_vm_funcs +ffffffff82b91140 r jpeg_v1_0_irq_funcs +ffffffff82b92000 r jpeg_v2_0_ip_funcs +ffffffff82b920a0 R jpeg_v2_0_ip_block +ffffffff82b920b8 r jpeg_v2_0_dec_ring_vm_funcs +ffffffff82b921f8 r jpeg_v2_0_irq_funcs +ffffffff82b93000 r jpeg_v2_5_ip_funcs +ffffffff82b930a0 R jpeg_v2_5_ip_block +ffffffff82b930b8 r jpeg_v2_6_ip_funcs +ffffffff82b93158 R jpeg_v2_6_ip_block +ffffffff82b93170 R jpeg_v2_6_ras_hw_ops +ffffffff82b931b0 r jpeg_v2_5_dec_ring_vm_funcs +ffffffff82b932f0 r jpeg_v2_6_dec_ring_vm_funcs +ffffffff82b93430 r jpeg_v2_5_irq_funcs +ffffffff82b93440 r jpeg_v2_6_ras_irq_funcs +ffffffff82b94000 r jpeg_v3_0_ip_funcs +ffffffff82b940a0 R jpeg_v3_0_ip_block +ffffffff82b940b8 r jpeg_v3_0_dec_ring_vm_funcs +ffffffff82b941f8 r jpeg_v3_0_irq_funcs +ffffffff82b95000 r jpeg_v4_0_ip_funcs +ffffffff82b950a0 R jpeg_v4_0_ip_block +ffffffff82b950b8 R jpeg_v4_0_ras_hw_ops +ffffffff82b950f8 r jpeg_v4_0_dec_ring_vm_funcs +ffffffff82b95238 r jpeg_v4_0_irq_funcs +ffffffff82b95248 r jpeg_v4_0_ras_irq_funcs +ffffffff82b96000 r jpeg_v4_0_3_ip_funcs +ffffffff82b960a0 R jpeg_v4_0_3_ip_block +ffffffff82b960b8 r jpeg_v4_0_3_dec_ring_vm_funcs +ffffffff82b961f8 r jpeg_v4_0_3_irq_funcs +ffffffff82b96208 r jpeg_v4_0_3_ras_hw_ops +ffffffff82b96250 r jpeg_v4_0_3_ue_reg_list +ffffffff82b97000 R lsdma_v6_0_funcs +ffffffff82b98000 r mca_v3_0_mp0_hw_ops +ffffffff82b98040 r mca_v3_0_mp1_hw_ops +ffffffff82b98080 r mca_v3_0_mpio_hw_ops +ffffffff82b99000 r mes_v10_1_ip_funcs +ffffffff82b990a0 R mes_v10_1_ip_block +ffffffff82b990b8 r mes_v10_1_funcs +ffffffff82b990e8 r mes_v10_1_ring_funcs +ffffffff82b9a000 r mes_v11_0_ip_funcs +ffffffff82b9a0a0 R mes_v11_0_ip_block +ffffffff82b9a0b8 r mes_v11_0_funcs +ffffffff82b9a0e8 r mes_v11_0_ring_funcs +ffffffff82b9b000 R mmhub_v1_0_funcs +ffffffff82b9b050 r mmhub_v1_0_edc_cnt_regs +ffffffff82b9b0c0 r mmhub_v1_0_ras_fields +ffffffff82b9c000 R mmhub_v1_7_funcs +ffffffff82b9c050 r mmhub_v1_7_edc_cnt_regs +ffffffff82b9c250 r mmhub_v1_7_ras_fields +ffffffff82b9d9c0 r mmhub_v1_7_ea_err_status_regs +ffffffff82b9e000 R mmhub_v1_8_funcs +ffffffff82b9e050 r mmhub_v1_8_ras_hw_ops +ffffffff82b9e090 r mmhub_v1_8_ce_reg_list +ffffffff82b9e180 r mmhub_v1_8_ras_memory_list +ffffffff82b9e2b0 r mmhub_v1_8_ue_reg_list +ffffffff82b9f000 R mmhub_v2_0_funcs +ffffffff82b9f050 r mmhub_v2_0_vmhub_funcs +ffffffff82b9f060 r mmhub_client_ids_navi1x +ffffffff82b9f190 r mmhub_client_ids_sienna_cichlid +ffffffff82b9f450 r mmhub_client_ids_beige_goby +ffffffff82ba0000 R mmhub_v2_3_funcs +ffffffff82ba0050 r mmhub_v2_3_vmhub_funcs +ffffffff82ba0060 r mmhub_client_ids_vangogh +ffffffff82ba1000 R mmhub_v3_0_funcs +ffffffff82ba1050 r mmhub_v3_0_vmhub_funcs +ffffffff82ba1060 r mmhub_client_ids_v3_0_0 +ffffffff82ba2000 R mmhub_v3_0_1_funcs +ffffffff82ba2050 r mmhub_v3_0_1_vmhub_funcs +ffffffff82ba2060 r mmhub_client_ids_v3_0_1 +ffffffff82ba3000 R mmhub_v3_0_2_funcs +ffffffff82ba3050 r mmhub_v3_0_2_vmhub_funcs +ffffffff82ba3060 r mmhub_client_ids_v3_0_2 +ffffffff82ba4000 R mmhub_v9_4_ras_hw_ops +ffffffff82ba4040 R mmhub_v9_4_funcs +ffffffff82ba4090 r mmhub_v9_4_edc_cnt_regs +ffffffff82ba4330 r mmhub_v9_4_ras_fields +ffffffff82ba63b0 r mmhub_v9_4_err_status_regs +ffffffff82ba7000 r xgpu_ai_mailbox_ack_irq_funcs +ffffffff82ba7010 r xgpu_ai_mailbox_rcv_irq_funcs +ffffffff82ba7020 R xgpu_ai_virt_ops +ffffffff82ba8000 r xgpu_nv_mailbox_ack_irq_funcs +ffffffff82ba8010 r xgpu_nv_mailbox_rcv_irq_funcs +ffffffff82ba8020 R xgpu_nv_virt_ops +ffffffff82ba9000 r xgpu_fiji_mgcg_cgcg_init +ffffffff82ba9240 r xgpu_fiji_golden_settings_a10 +ffffffff82ba9370 r xgpu_fiji_golden_common_all +ffffffff82ba93f0 r xgpu_tonga_mgcg_cgcg_init +ffffffff82ba9810 r xgpu_tonga_golden_settings_a11 +ffffffff82ba99d0 r xgpu_tonga_golden_common_all +ffffffff82ba9a28 r xgpu_vi_mailbox_ack_irq_funcs +ffffffff82ba9a38 r xgpu_vi_mailbox_rcv_irq_funcs +ffffffff82ba9a48 R xgpu_vi_virt_ops +ffffffff82baa000 r navi10_ih_ip_funcs +ffffffff82baa0a0 R navi10_ih_ip_block +ffffffff82baa0b8 r navi10_ih_funcs +ffffffff82baa0d8 r navi10_ih_self_irq_funcs +ffffffff82bab000 R nbio_v2_3_hdp_flush_reg +ffffffff82bab048 R nbio_v2_3_funcs +ffffffff82bac000 R nbio_v4_3_hdp_flush_reg +ffffffff82bac048 R nbio_v4_3_funcs +ffffffff82bac158 R nbio_v4_3_sriov_funcs +ffffffff82bac268 r nbio_v4_3_ras_err_event_athub_irq_funcs +ffffffff82bad000 R nbio_v6_1_hdp_flush_reg +ffffffff82bad048 R nbio_v6_1_funcs +ffffffff82bae000 R nbio_v7_0_hdp_flush_reg +ffffffff82bae048 R nbio_v7_0_funcs +ffffffff82baf000 R nbio_v7_2_hdp_flush_reg +ffffffff82baf048 R nbio_v7_2_funcs +ffffffff82bb0000 R nbio_v7_4_hdp_flush_reg +ffffffff82bb0048 R nbio_v7_4_ras_hw_ops +ffffffff82bb0088 R nbio_v7_4_funcs +ffffffff82bb0198 r nbio_v7_4_ras_controller_irq_funcs +ffffffff82bb01a8 r nbio_v7_4_ras_err_event_athub_irq_funcs +ffffffff82bb1000 R nbio_v7_7_hdp_flush_reg +ffffffff82bb1048 R nbio_v7_7_funcs +ffffffff82bb2000 R nbio_v7_9_hdp_flush_reg +ffffffff82bb2048 R nbio_v7_9_funcs +ffffffff82bb2158 R nbio_v7_9_ras_hw_ops +ffffffff82bb2198 r nbio_v7_9_ras_controller_irq_funcs +ffffffff82bb21a8 r nbio_v7_9_ras_err_event_athub_irq_funcs +ffffffff82bb3000 r nv_common_ip_funcs +ffffffff82bb30a0 R nv_common_ip_block +ffffffff82bb30b8 r nv_asic_funcs +ffffffff82bb3180 r nv_allowed_read_registers +ffffffff82bb3300 r sc_video_codecs_encode +ffffffff82bb3310 r sc_video_codecs_decode_vcn1 +ffffffff82bb3320 r sc_video_codecs_decode_vcn0 +ffffffff82bb3330 r yc_video_codecs_decode +ffffffff82bb3340 r bg_video_codecs_encode +ffffffff82bb3350 r bg_video_codecs_decode +ffffffff82bb3360 r nv_video_codecs_encode +ffffffff82bb3370 r nv_video_codecs_decode +ffffffff82bb3380 r sc_video_codecs_encode_array +ffffffff82bb33b0 r sc_video_codecs_decode_array_vcn1 +ffffffff82bb3440 r sc_video_codecs_decode_array_vcn0 +ffffffff82bb34e0 r yc_video_codecs_decode_array +ffffffff82bb3550 r bg_video_codecs_decode_array +ffffffff82bb3590 r nv_video_codecs_encode_array +ffffffff82bb35c0 r nv_video_codecs_decode_array +ffffffff82bb4000 r psp_v10_0_funcs +ffffffff82bb5000 r psp_v11_0_funcs +ffffffff82bb6000 r psp_v11_0_8_funcs +ffffffff82bb7000 r psp_v12_0_funcs +ffffffff82bb8000 r psp_v13_0_funcs +ffffffff82bb9000 r psp_v13_0_4_funcs +ffffffff82bba000 r psp_v3_1_funcs +ffffffff82bbb000 r sdma_v2_4_ip_funcs +ffffffff82bbb0a0 R sdma_v2_4_ip_block +ffffffff82bbb0b8 r sdma_v2_4_ring_funcs +ffffffff82bbb1f8 r sdma_v2_4_buffer_funcs +ffffffff82bbb218 r sdma_v2_4_vm_pte_funcs +ffffffff82bbb238 r sdma_v2_4_trap_irq_funcs +ffffffff82bbb248 r sdma_v2_4_illegal_inst_irq_funcs +ffffffff82bbb260 r iceland_mgcg_cgcg_init +ffffffff82bbb280 r golden_settings_iceland_a11 +ffffffff82bbc000 r sdma_v3_0_ip_funcs +ffffffff82bbc0a0 R sdma_v3_0_ip_block +ffffffff82bbc0b8 R sdma_v3_1_ip_block +ffffffff82bbc0d0 r sdma_v3_0_ring_funcs +ffffffff82bbc210 r sdma_v3_0_buffer_funcs +ffffffff82bbc230 r sdma_v3_0_vm_pte_funcs +ffffffff82bbc250 r sdma_v3_0_trap_irq_funcs +ffffffff82bbc260 r sdma_v3_0_illegal_inst_irq_funcs +ffffffff82bbc270 r fiji_mgcg_cgcg_init +ffffffff82bbc290 r golden_settings_fiji_a10 +ffffffff82bbc2f0 r tonga_mgcg_cgcg_init +ffffffff82bbc310 r golden_settings_tonga_a11 +ffffffff82bbc390 r golden_settings_polaris11_a11 +ffffffff82bbc410 r golden_settings_polaris10_a11 +ffffffff82bbc490 r cz_mgcg_cgcg_init +ffffffff82bbc4b0 r cz_golden_settings_a11 +ffffffff82bbc540 r stoney_mgcg_cgcg_init +ffffffff82bbc550 r stoney_golden_settings_a11 +ffffffff82bbd000 R sdma_v4_0_ip_funcs +ffffffff82bbd0a0 R sdma_v4_0_ras_hw_ops +ffffffff82bbd0e0 R sdma_v4_0_ip_block +ffffffff82bbd0f8 r sdma_v4_0_ring_funcs +ffffffff82bbd238 r sdma_v4_0_page_ring_funcs +ffffffff82bbd378 r sdma_v4_0_buffer_funcs +ffffffff82bbd398 r sdma_v4_0_vm_pte_funcs +ffffffff82bbd3b8 r sdma_v4_0_trap_irq_funcs +ffffffff82bbd3c8 r sdma_v4_0_illegal_inst_irq_funcs +ffffffff82bbd3d8 r sdma_v4_0_ecc_irq_funcs +ffffffff82bbd3e8 r sdma_v4_0_vm_hole_irq_funcs +ffffffff82bbd3f8 r sdma_v4_0_doorbell_invalid_irq_funcs +ffffffff82bbd408 r sdma_v4_0_pool_timeout_irq_funcs +ffffffff82bbd418 r sdma_v4_0_srbm_write_irq_funcs +ffffffff82bbd430 r golden_settings_sdma_4 +ffffffff82bbd690 r golden_settings_sdma_vg10 +ffffffff82bbd740 r golden_settings_sdma_vg12 +ffffffff82bbd7f0 r golden_settings_sdma0_4_2_init +ffffffff82bbd810 r golden_settings_sdma0_4_2 +ffffffff82bbdaa0 r golden_settings_sdma1_4_2 +ffffffff82bbdd30 r golden_settings_sdma_arct +ffffffff82bbe030 r golden_settings_sdma_aldebaran +ffffffff82bbe1a0 r golden_settings_sdma_4_1 +ffffffff82bbe2b0 r golden_settings_sdma_rv2 +ffffffff82bbe2e0 r golden_settings_sdma_rv1 +ffffffff82bbe310 r golden_settings_sdma_4_3 +ffffffff82bbe400 r sdma_v4_0_ras_fields +ffffffff82bbf000 R sdma_v4_4_ras_hw_ops +ffffffff82bbf040 r sdma_v4_4_ras_fields +ffffffff82bc0000 R sdma_v4_4_2_ip_funcs +ffffffff82bc00a0 R sdma_v4_4_2_ip_block +ffffffff82bc00b8 r sdma_v4_4_2_ring_funcs +ffffffff82bc01f8 r sdma_v4_4_2_page_ring_funcs +ffffffff82bc0338 r sdma_v4_4_2_buffer_funcs +ffffffff82bc0358 r sdma_v4_4_2_vm_pte_funcs +ffffffff82bc0378 r sdma_v4_4_2_trap_irq_funcs +ffffffff82bc0388 r sdma_v4_4_2_illegal_inst_irq_funcs +ffffffff82bc0398 r sdma_v4_4_2_ecc_irq_funcs +ffffffff82bc03a8 r sdma_v4_4_2_vm_hole_irq_funcs +ffffffff82bc03b8 r sdma_v4_4_2_doorbell_invalid_irq_funcs +ffffffff82bc03c8 r sdma_v4_4_2_pool_timeout_irq_funcs +ffffffff82bc03d8 r sdma_v4_4_2_srbm_write_irq_funcs +ffffffff82bc03e8 r sdma_v4_4_2_ras_hw_ops +ffffffff82bc0430 r sdma_v4_2_2_ue_reg_list +ffffffff82bc0460 r sdma_v4_4_2_ras_memory_list +ffffffff82bc1000 R sdma_v5_0_ip_funcs +ffffffff82bc10a0 R sdma_v5_0_ip_block +ffffffff82bc10b8 r sdma_v5_0_ring_funcs +ffffffff82bc11f8 r sdma_v5_0_buffer_funcs +ffffffff82bc1218 r sdma_v5_0_vm_pte_funcs +ffffffff82bc1238 r sdma_v5_0_trap_irq_funcs +ffffffff82bc1248 r sdma_v5_0_illegal_inst_irq_funcs +ffffffff82bc1260 r golden_settings_sdma_5 +ffffffff82bc14a0 r golden_settings_sdma_nv10 +ffffffff82bc14d0 r golden_settings_sdma_nv14 +ffffffff82bc1500 r golden_settings_sdma_5_sriov +ffffffff82bc16e0 r golden_settings_sdma_nv12 +ffffffff82bc1770 r golden_settings_sdma_cyan_skillfish +ffffffff82bc2000 R sdma_v5_2_ip_funcs +ffffffff82bc20a0 R sdma_v5_2_ip_block +ffffffff82bc20b8 r sdma_v5_2_ring_funcs +ffffffff82bc21f8 r sdma_v5_2_buffer_funcs +ffffffff82bc2218 r sdma_v5_2_vm_pte_funcs +ffffffff82bc2238 r sdma_v5_2_trap_irq_funcs +ffffffff82bc2248 r sdma_v5_2_illegal_inst_irq_funcs +ffffffff82bc3000 R sdma_v6_0_ip_funcs +ffffffff82bc30a0 R sdma_v6_0_ip_block +ffffffff82bc30b8 r sdma_v6_0_ring_funcs +ffffffff82bc31f8 r sdma_v6_0_buffer_funcs +ffffffff82bc3218 r sdma_v6_0_vm_pte_funcs +ffffffff82bc3238 r sdma_v6_0_trap_irq_funcs +ffffffff82bc3248 r sdma_v6_0_illegal_inst_irq_funcs +ffffffff82bc4000 r smu_v11_0_i2c_algo +ffffffff82bc4010 r smu_v11_0_i2c_i2c_lock_ops +ffffffff82bc4028 r smu_v11_0_i2c_control_quirks +ffffffff82bc5000 R smuio_v11_0_funcs +ffffffff82bc6000 R smuio_v11_0_6_funcs +ffffffff82bc7000 R smuio_v13_0_funcs +ffffffff82bc8000 R smuio_v13_0_3_funcs +ffffffff82bc9000 R smuio_v13_0_6_funcs +ffffffff82bca000 R smuio_v9_0_funcs +ffffffff82bcb000 r soc15_common_ip_funcs +ffffffff82bcb0a0 R vega10_common_ip_block +ffffffff82bcb0b8 r soc15_asic_funcs +ffffffff82bcb178 r vega20_asic_funcs +ffffffff82bcb238 r aqua_vanjaram_asic_funcs +ffffffff82bcb300 r soc15_allowed_read_registers +ffffffff82bcb490 r vega_video_codecs_encode +ffffffff82bcb4a0 r vega_video_codecs_decode +ffffffff82bcb4b0 r rv_video_codecs_decode +ffffffff82bcb4c0 r rn_video_codecs_decode +ffffffff82bcb4d0 r vcn_4_0_3_video_codecs_encode +ffffffff82bcb4e0 r vcn_4_0_3_video_codecs_decode +ffffffff82bcb4f0 r vega_video_codecs_encode_array +ffffffff82bcb520 r vega_video_codecs_decode_array +ffffffff82bcb5a0 r rv_video_codecs_decode_array +ffffffff82bcb630 r rn_video_codecs_decode_array +ffffffff82bcb6c0 r vcn_4_0_3_video_codecs_decode_array +ffffffff82bcc000 r soc21_common_ip_funcs +ffffffff82bcc0a0 R soc21_common_ip_block +ffffffff82bcc0b8 r soc21_asic_funcs +ffffffff82bcc180 r soc21_allowed_read_registers +ffffffff82bcc300 r vcn_4_0_0_video_codecs_encode_vcn1 +ffffffff82bcc310 r vcn_4_0_0_video_codecs_decode_vcn1 +ffffffff82bcc320 r vcn_4_0_0_video_codecs_encode_vcn0 +ffffffff82bcc330 r vcn_4_0_0_video_codecs_decode_vcn0 +ffffffff82bcc340 r vcn_4_0_0_video_codecs_encode_array_vcn1 +ffffffff82bcc370 r vcn_4_0_0_video_codecs_decode_array_vcn1 +ffffffff82bcc3c0 r vcn_4_0_0_video_codecs_encode_array_vcn0 +ffffffff82bcc400 r vcn_4_0_0_video_codecs_decode_array_vcn0 +ffffffff82bcd000 r tonga_ih_ip_funcs +ffffffff82bcd0a0 R tonga_ih_ip_block +ffffffff82bcd0b8 r tonga_ih_funcs +ffffffff82bce000 R umc_v6_0_funcs +ffffffff82bcf000 R umc_v6_1_channel_idx_tbl +ffffffff82bcf080 R umc_v6_1_ras_hw_ops +ffffffff82bd0000 R umc_v6_7_channel_idx_tbl_second +ffffffff82bd0080 R umc_v6_7_channel_idx_tbl_first +ffffffff82bd0100 R umc_v6_7_ras_hw_ops +ffffffff82bd1000 R umc_v8_10_channelnum_map_colbit_table +ffffffff82bd1040 R umc_v8_10_channel_idx_tbl_ext0 +ffffffff82bd1080 R umc_v8_10_channel_idx_tbl +ffffffff82bd10e0 R umc_v8_10_ras_hw_ops +ffffffff82bd2000 R umc_v8_7_channel_idx_tbl +ffffffff82bd2040 R umc_v8_7_ras_hw_ops +ffffffff82bd3000 r uvd_v5_0_ip_funcs +ffffffff82bd30a0 R uvd_v5_0_ip_block +ffffffff82bd30b8 r uvd_v5_0_ring_funcs +ffffffff82bd31f8 r uvd_v5_0_irq_funcs +ffffffff82bd4000 r uvd_v6_0_ip_funcs +ffffffff82bd40a0 R uvd_v6_0_ip_block +ffffffff82bd40b8 R uvd_v6_2_ip_block +ffffffff82bd40d0 R uvd_v6_3_ip_block +ffffffff82bd40e8 r uvd_v6_0_ring_vm_funcs +ffffffff82bd4228 r uvd_v6_0_ring_phys_funcs +ffffffff82bd4368 r uvd_v6_0_enc_ring_vm_funcs +ffffffff82bd44a8 r uvd_v6_0_irq_funcs +ffffffff82bd5000 R uvd_v7_0_ip_funcs +ffffffff82bd50a0 R uvd_v7_0_ip_block +ffffffff82bd50b8 r uvd_v7_0_ring_vm_funcs +ffffffff82bd51f8 r uvd_v7_0_enc_ring_vm_funcs +ffffffff82bd5338 r uvd_v7_0_irq_funcs +ffffffff82bd6000 r vce_v3_0_ip_funcs +ffffffff82bd60a0 R vce_v3_0_ip_block +ffffffff82bd60b8 R vce_v3_1_ip_block +ffffffff82bd60d0 R vce_v3_4_ip_block +ffffffff82bd60e8 r vce_v3_0_ring_vm_funcs +ffffffff82bd6228 r vce_v3_0_ring_phys_funcs +ffffffff82bd6368 r vce_v3_0_irq_funcs +ffffffff82bd7000 R vce_v4_0_ip_funcs +ffffffff82bd70a0 R vce_v4_0_ip_block +ffffffff82bd70b8 r vce_v4_0_ring_vm_funcs +ffffffff82bd71f8 r vce_v4_0_irq_funcs +ffffffff82bd8000 r vcn_v1_0_ip_funcs +ffffffff82bd80a0 R vcn_v1_0_ip_block +ffffffff82bd80b8 r vcn_v1_0_dec_ring_vm_funcs +ffffffff82bd81f8 r vcn_v1_0_enc_ring_vm_funcs +ffffffff82bd8338 r vcn_v1_0_irq_funcs +ffffffff82bd9000 r vcn_v2_0_ip_funcs +ffffffff82bd90a0 R vcn_v2_0_ip_block +ffffffff82bd90b8 r vcn_v2_0_dec_ring_vm_funcs +ffffffff82bd91f8 r vcn_v2_0_enc_ring_vm_funcs +ffffffff82bd9338 r vcn_v2_0_irq_funcs +ffffffff82bda000 r vcn_v2_5_ip_funcs +ffffffff82bda0a0 R vcn_v2_5_ip_block +ffffffff82bda0b8 r vcn_v2_6_ip_funcs +ffffffff82bda158 R vcn_v2_6_ip_block +ffffffff82bda170 R vcn_v2_6_ras_hw_ops +ffffffff82bda1b0 r vcn_v2_5_dec_ring_vm_funcs +ffffffff82bda2f0 r vcn_v2_5_enc_ring_vm_funcs +ffffffff82bda430 r vcn_v2_5_irq_funcs +ffffffff82bda440 r vcn_v2_6_ras_irq_funcs +ffffffff82bdb000 r vcn_v3_0_ip_funcs +ffffffff82bdb0a0 R vcn_v3_0_ip_block +ffffffff82bdb0b8 r vcn_v3_0_dec_ring_vm_funcs +ffffffff82bdb1f8 r vcn_v3_0_enc_ring_vm_funcs +ffffffff82bdb338 r vcn_v3_0_irq_funcs +ffffffff82bdc000 r vcn_v4_0_ip_funcs +ffffffff82bdc0a0 R vcn_v4_0_ip_block +ffffffff82bdc0b8 R vcn_v4_0_ras_hw_ops +ffffffff82bdc0f8 r vcn_v4_0_irq_funcs +ffffffff82bdc108 r vcn_v4_0_ras_irq_funcs +ffffffff82bdd000 r vcn_v4_0_3_ip_funcs +ffffffff82bdd0a0 R vcn_v4_0_3_ip_block +ffffffff82bdd0b8 r vcn_v4_0_3_unified_ring_vm_funcs +ffffffff82bdd1f8 r vcn_v4_0_3_irq_funcs +ffffffff82bdd208 r vcn_v4_0_3_ras_hw_ops +ffffffff82bdd250 r vcn_v4_0_3_ue_reg_list +ffffffff82bde000 R vega10_ih_ip_funcs +ffffffff82bde0a0 R vega10_ih_ip_block +ffffffff82bde0b8 r vega10_ih_funcs +ffffffff82bde0d8 r vega10_ih_self_irq_funcs ffffffff82bdf000 r GC_BASE -ffffffff82bdf090 r HDP_BASE -ffffffff82bdf120 r MMHUB_BASE -ffffffff82bdf1b0 r ATHUB_BASE -ffffffff82bdf240 r NBIO_BASE -ffffffff82bdf2d0 r MP0_BASE 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cz_video_codecs_decode_array -ffffffff82be0560 r iceland_mgcg_cgcg_init -ffffffff82be05a0 r fiji_mgcg_cgcg_init -ffffffff82be0600 r tonga_mgcg_cgcg_init -ffffffff82be0660 r cz_mgcg_cgcg_init -ffffffff82be06a0 r stoney_mgcg_cgcg_init -ffffffff82be1000 r amdgpu_dm_funcs -ffffffff82be10a0 R dm_ip_block -ffffffff82be10b8 R amdgpu_dm_encoder_helper_funcs -ffffffff82be1120 r dm_display_funcs -ffffffff82be1180 r hpd_disconnect_quirk_table -ffffffff82be1ef0 r amdgpu_dm_mode_funcs -ffffffff82be1f38 r amdgpu_dm_audio_component_bind_ops -ffffffff82be1f48 r amdgpu_dm_audio_component_ops -ffffffff82be1f80 r amdgpu_dm_encoder_funcs -ffffffff82be1fa0 r amdgpu_dm_connector_funcs -ffffffff82be2018 r amdgpu_dm_connector_helper_funcs -ffffffff82be2078 r amdgpu_dm_i2c_algo -ffffffff82be2088 r amdgpu_dm_backlight_ops -ffffffff82be2260 r add_fs_modes.common_rates -ffffffff82be3000 r amdgpu_dm_crtc_funcs -ffffffff82be30c0 r amdgpu_dm_crtc_helper_funcs -ffffffff82be4000 r dm_dtn_log_begin.msg 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+ffffffff82bfb054 r clk_mgr_shift +ffffffff82bfb060 r clk_mgr_mask ffffffff82bfc000 r lpddr5_wm_table ffffffff82bfc0c0 r ddr5_wm_table ffffffff82bfd000 r lpddr5_wm_table -ffffffff82bfd0c0 r ddr4_wm_table -ffffffff82bfe000 r clk_mgr_regs_dcn321 -ffffffff82bfe054 r clk_mgr_shift_dcn321 -ffffffff82bfe060 r clk_mgr_mask_dcn321 -ffffffff82bfe084 r clk_mgr_regs_dcn32 -ffffffff82bfe0d8 r clk_mgr_shift_dcn32 -ffffffff82bfe0e4 r clk_mgr_mask_dcn32 -ffffffff82bff000 r DC_BUILD_ID -ffffffff82c01000 r output_csc_matrix -ffffffff82c010e0 r black_color_format -ffffffff82c04000 r dce_funcs -ffffffff82c05000 r funcs -ffffffff82c06000 R video_optimized_pixel_rates -ffffffff82c061c0 r dce110_clk_src_funcs -ffffffff82c061e8 r dce112_clk_src_funcs -ffffffff82c06210 r dcn20_clk_src_funcs -ffffffff82c06238 r dcn3_clk_src_funcs -ffffffff82c06260 r dcn31_clk_src_funcs -ffffffff82c07000 r dce_funcs -ffffffff82c07068 r dcn10_funcs -ffffffff82c070d0 r dcn20_funcs -ffffffff82c07138 r dcn21_funcs -ffffffff82c08000 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qp_table_422_12bpc_min -ffffffff82d0b500 r qp_table_420_8bpc_max -ffffffff82d0b940 r qp_table_420_8bpc_min -ffffffff82d0bd80 r qp_table_420_10bpc_max -ffffffff82d0c340 r qp_table_420_10bpc_min -ffffffff82d0c900 r qp_table_420_12bpc_max -ffffffff82d0d040 r qp_table_420_12bpc_min -ffffffff82d0f000 r funcs -ffffffff82d0f050 r hpd_regs -ffffffff82d0f1a0 r hpd_shift -ffffffff82d0f1b0 r hpd_mask -ffffffff82d0f1c0 r ddc_data_regs -ffffffff82d0f3a0 r ddc_clk_regs -ffffffff82d0f580 r ddc_shift -ffffffff82d0f5a8 r ddc_mask -ffffffff82d10000 r funcs +ffffffff82bfd0c0 r ddr5_wm_table +ffffffff82bfe000 r ddr5_wm_table +ffffffff82bff000 r lpddr5_wm_table +ffffffff82bff0c0 r ddr4_wm_table +ffffffff82c00000 r clk_mgr_regs_dcn321 +ffffffff82c00054 r clk_mgr_shift_dcn321 +ffffffff82c00060 r clk_mgr_mask_dcn321 +ffffffff82c00084 r clk_mgr_regs_dcn32 +ffffffff82c000d8 r clk_mgr_shift_dcn32 +ffffffff82c000e4 r clk_mgr_mask_dcn32 +ffffffff82c01000 r DC_BUILD_ID +ffffffff82c03000 r output_csc_matrix +ffffffff82c030e0 r black_color_format +ffffffff82c06000 r dce_funcs +ffffffff82c07000 r funcs +ffffffff82c08000 R video_optimized_pixel_rates +ffffffff82c081c0 r dce110_clk_src_funcs +ffffffff82c081e8 r dce112_clk_src_funcs +ffffffff82c08210 r dcn20_clk_src_funcs +ffffffff82c08238 r dcn3_clk_src_funcs +ffffffff82c08260 r dcn31_clk_src_funcs +ffffffff82c09000 r dce_funcs +ffffffff82c09068 r dcn10_funcs +ffffffff82c090d0 r dcn20_funcs +ffffffff82c09138 r dcn21_funcs +ffffffff82c0a000 r dce_ipp_funcs +ffffffff82c0b000 r dce110_lnk_enc_funcs +ffffffff82c0c000 r dce_mi_funcs +ffffffff82c0c090 r dce112_mi_funcs +ffffffff82c0c120 r dce120_mi_funcs +ffffffff82c0c1b0 r pte_settings +ffffffff82c0d000 r funcs +ffffffff82c0e000 r dce_link_panel_cntl_funcs +ffffffff82c0f000 r filter_3tap_16p_upscale +ffffffff82c0f040 r filter_3tap_16p_116 +ffffffff82c0f080 r filter_3tap_16p_149 +ffffffff82c0f0c0 r filter_3tap_16p_183 +ffffffff82c0f100 r filter_3tap_64p_upscale +ffffffff82c0f1d0 r filter_3tap_64p_116 +ffffffff82c0f2a0 r filter_3tap_64p_149 +ffffffff82c0f370 r filter_3tap_64p_183 +ffffffff82c0f440 r filter_4tap_16p_upscale +ffffffff82c0f490 r filter_4tap_16p_116 +ffffffff82c0f4e0 r filter_4tap_16p_149 +ffffffff82c0f530 r filter_4tap_16p_183 +ffffffff82c0f580 r filter_4tap_64p_upscale +ffffffff82c0f690 r filter_4tap_64p_116 +ffffffff82c0f7a0 r filter_4tap_64p_149 +ffffffff82c0f8b0 r filter_4tap_64p_183 +ffffffff82c0f9c0 r filter_5tap_64p_upscale +ffffffff82c0fb10 r filter_5tap_64p_116 +ffffffff82c0fc60 r filter_5tap_64p_149 +ffffffff82c0fdb0 r filter_5tap_64p_183 +ffffffff82c0ff00 r filter_6tap_64p_upscale +ffffffff82c10090 r filter_6tap_64p_116 +ffffffff82c10220 r filter_6tap_64p_149 +ffffffff82c103b0 r filter_6tap_64p_183 +ffffffff82c10540 r filter_7tap_64p_upscale +ffffffff82c10710 r filter_7tap_64p_116 +ffffffff82c108e0 r filter_7tap_64p_149 +ffffffff82c10ab0 r filter_7tap_64p_183 +ffffffff82c10c80 r filter_8tap_64p_upscale +ffffffff82c10e90 r filter_8tap_64p_116 +ffffffff82c110a0 r filter_8tap_64p_149 +ffffffff82c112b0 r filter_8tap_64p_183 +ffffffff82c114c0 r filter_2tap_16p +ffffffff82c114f0 r filter_2tap_64p +ffffffff82c12000 r dce110_str_enc_funcs +ffffffff82c12120 r audio_clock_info_table_48bpc +ffffffff82c122b0 r audio_clock_info_table_36bpc +ffffffff82c12440 r audio_clock_info_table +ffffffff82c13000 r global_color_matrix +ffffffff82c130a8 r dce_transform_funcs +ffffffff82c14000 r abm_funcs +ffffffff82c15000 r psr_funcs +ffffffff82c15040 r DP_SINK_DEVICE_STR_ID_1 +ffffffff82c15045 r DP_SINK_DEVICE_STR_ID_2 +ffffffff82c16000 r replay_funcs +ffffffff82c17000 r reg_offsets +ffffffff82c18000 r bios_regs +ffffffff82c18008 r res_cap +ffffffff82c18048 r dce100_res_pool_funcs +ffffffff82c18140 r clk_src_regs +ffffffff82c1823c r dmcu_regs +ffffffff82c18298 r dmcu_shift +ffffffff82c182ac r dmcu_mask +ffffffff82c182f8 r abm_regs +ffffffff82c18360 r abm_shift +ffffffff82c18384 r abm_mask +ffffffff82c18410 r debug_defaults +ffffffff82c185c0 r dce100_tg_offsets +ffffffff82c18608 r plane_cap +ffffffff82c18638 r res_create_funcs +ffffffff82c18670 r panel_cntl_regs +ffffffff82c18690 r panel_cntl_shift +ffffffff82c186a0 r panel_cntl_mask +ffffffff82c186e0 r link_enc_regs +ffffffff82c18aa0 r link_enc_aux_regs +ffffffff82c18af0 r link_enc_hpd_regs +ffffffff82c18b08 r link_enc_feature +ffffffff82c18b18 r cs_shift +ffffffff82c18b24 r cs_mask +ffffffff82c18b50 r mi_regs +ffffffff82c18e68 r mi_shifts +ffffffff82c18eb0 r mi_masks +ffffffff82c18fd0 r ipp_regs +ffffffff82c191c8 r ipp_shift +ffffffff82c191f0 r ipp_mask +ffffffff82c19290 r xfm_regs +ffffffff82c19830 r xfm_shift +ffffffff82c19890 r xfm_mask +ffffffff82c19a10 r opp_regs +ffffffff82c19b60 r opp_shift +ffffffff82c19b8c r opp_mask +ffffffff82c19c40 r aux_engine_regs +ffffffff82c19d30 r aux_mask +ffffffff82c19d90 r aux_shift +ffffffff82c19db0 r i2c_hw_regs +ffffffff82c19f00 r i2c_shifts +ffffffff82c19f2c r i2c_masks +ffffffff82c19fd0 r audio_regs +ffffffff82c1a104 r audio_shift +ffffffff82c1a11c r audio_mask +ffffffff82c1a160 r stream_enc_regs +ffffffff82c1a80c r se_shift +ffffffff82c1a890 r se_mask +ffffffff82c1aa94 r hwseq_reg +ffffffff82c1acb0 r hwseq_shift +ffffffff82c1ad30 r hwseq_mask +ffffffff82c1b000 r reg_offsets +ffffffff82c1b018 r dce110_compressor_funcs +ffffffff82c1c000 r dce110_funcs +ffffffff82c1c2e8 r dce110_private_funcs +ffffffff82c1d000 r dce110_mem_input_v_funcs +ffffffff82c1d090 r dvmm_Hw_Setting_1DTiling +ffffffff82c1d120 r dvmm_Hw_Setting_2DTiling +ffffffff82c1d1b0 r dvmm_Hw_Setting_Linear +ffffffff82c1e000 r global_color_matrix +ffffffff82c1e0b0 r input_csc_matrix +ffffffff82c1f000 r funcs +ffffffff82c20000 r bios_regs +ffffffff82c20008 r dce110_res_pool_funcs +ffffffff82c20100 r debug_defaults +ffffffff82c202b0 r clk_src_regs +ffffffff82c203ac r dmcu_regs +ffffffff82c20408 r dmcu_shift +ffffffff82c2041c r dmcu_mask +ffffffff82c20468 r abm_regs +ffffffff82c204d0 r abm_shift +ffffffff82c204f4 r abm_mask +ffffffff82c20580 r dce110_tg_offsets +ffffffff82c205c8 r res_create_funcs +ffffffff82c205f8 r plane_cap +ffffffff82c20624 r underlay_plane_cap +ffffffff82c20650 r stoney_resource_cap +ffffffff82c2068c r carrizo_resource_cap +ffffffff82c206d0 r panel_cntl_regs +ffffffff82c206f0 r panel_cntl_shift +ffffffff82c20700 r panel_cntl_mask +ffffffff82c20740 r link_enc_regs +ffffffff82c20b00 r link_enc_aux_regs +ffffffff82c20b50 r link_enc_hpd_regs +ffffffff82c20b68 r link_enc_feature +ffffffff82c20b78 r cs_shift +ffffffff82c20b84 r cs_mask +ffffffff82c20bb0 r mi_regs +ffffffff82c20d3c r mi_shifts +ffffffff82c20d84 r mi_masks +ffffffff82c20ea0 r ipp_regs +ffffffff82c20f9c r ipp_shift +ffffffff82c20fc4 r ipp_mask +ffffffff82c21060 r xfm_regs +ffffffff82c21330 r xfm_shift +ffffffff82c21390 r xfm_mask +ffffffff82c21510 r opp_regs +ffffffff82c21660 r opp_shift +ffffffff82c2168c r opp_mask +ffffffff82c21740 r aux_engine_regs +ffffffff82c21830 r aux_mask +ffffffff82c21890 r aux_shift +ffffffff82c218b0 r i2c_hw_regs +ffffffff82c21a00 r i2c_shifts +ffffffff82c21a2c r i2c_masks +ffffffff82c21ad0 r audio_regs +ffffffff82c21c04 r audio_shift +ffffffff82c21c1c r audio_mask +ffffffff82c21c60 r stream_enc_regs +ffffffff82c21f3c r se_shift +ffffffff82c21fc0 r se_mask +ffffffff82c221c4 r hwseq_stoney_reg +ffffffff82c223e0 r hwseq_cz_reg +ffffffff82c225fc r hwseq_shift +ffffffff82c2267c r hwseq_mask +ffffffff82c23000 r dce110_tg_funcs +ffffffff82c24000 r dce110_tg_v_funcs +ffffffff82c25000 r dce110_xfmv_funcs +ffffffff82c26000 r reg_offsets +ffffffff82c27000 r reg_offsets +ffffffff82c28000 r bios_regs +ffffffff82c28008 r dce112_res_pool_funcs +ffffffff82c28100 r debug_defaults +ffffffff82c282b0 r clk_src_regs +ffffffff82c284a8 r dmcu_regs +ffffffff82c28504 r dmcu_shift +ffffffff82c28518 r dmcu_mask +ffffffff82c28564 r abm_regs +ffffffff82c285cc r abm_shift +ffffffff82c285f0 r abm_mask +ffffffff82c28680 r dce112_tg_offsets +ffffffff82c286c8 r res_create_funcs +ffffffff82c286f8 r plane_cap +ffffffff82c28724 r polaris_11_resource_cap +ffffffff82c28760 r polaris_10_resource_cap +ffffffff82c287a0 r panel_cntl_regs +ffffffff82c287c0 r panel_cntl_shift +ffffffff82c287d0 r panel_cntl_mask +ffffffff82c28810 r link_enc_regs +ffffffff82c28bd0 r link_enc_aux_regs +ffffffff82c28c20 r link_enc_hpd_regs +ffffffff82c28c38 r link_enc_feature +ffffffff82c28c48 r cs_shift +ffffffff82c28c54 r cs_mask +ffffffff82c28c80 r mi_regs +ffffffff82c28f98 r mi_shifts +ffffffff82c28fe0 r mi_masks +ffffffff82c29100 r ipp_regs +ffffffff82c292f8 r ipp_shift +ffffffff82c29320 r ipp_mask +ffffffff82c293c0 r xfm_regs +ffffffff82c29960 r xfm_shift +ffffffff82c299c0 r xfm_mask +ffffffff82c29b40 r opp_regs +ffffffff82c29c90 r opp_shift +ffffffff82c29cbc r opp_mask +ffffffff82c29d70 r aux_engine_regs +ffffffff82c29e60 r aux_mask +ffffffff82c29ec0 r aux_shift +ffffffff82c29ee0 r i2c_hw_regs +ffffffff82c2a030 r i2c_shifts +ffffffff82c2a05c r i2c_masks +ffffffff82c2a100 r audio_regs +ffffffff82c2a208 r audio_shift +ffffffff82c2a220 r audio_mask +ffffffff82c2a260 r stream_enc_regs +ffffffff82c2a818 r se_shift +ffffffff82c2a89c r se_mask +ffffffff82c2aaa0 r hwseq_reg +ffffffff82c2acbc r hwseq_shift +ffffffff82c2ad3c r hwseq_mask +ffffffff82c2b000 r bios_regs +ffffffff82c2b008 r res_cap +ffffffff82c2b048 r dce120_res_pool_funcs +ffffffff82c2b140 r debug_defaults +ffffffff82c2b2f0 r clk_src_regs +ffffffff82c2b4e8 r dmcu_regs +ffffffff82c2b544 r dmcu_shift +ffffffff82c2b558 r dmcu_mask +ffffffff82c2b5a4 r abm_regs +ffffffff82c2b60c r abm_shift +ffffffff82c2b630 r abm_mask +ffffffff82c2b6c0 r dce120_tg_offsets +ffffffff82c2b708 r dce121_res_create_funcs +ffffffff82c2b738 r res_create_funcs +ffffffff82c2b768 r plane_cap +ffffffff82c2b7a0 r panel_cntl_regs +ffffffff82c2b7c0 r panel_cntl_shift +ffffffff82c2b7d0 r panel_cntl_mask +ffffffff82c2b810 r link_enc_regs +ffffffff82c2bbd0 r link_enc_aux_regs +ffffffff82c2bc20 r link_enc_hpd_regs +ffffffff82c2bc38 r link_enc_feature +ffffffff82c2bc48 r cs_shift +ffffffff82c2bc54 r cs_mask +ffffffff82c2bc80 r mi_regs +ffffffff82c2bf98 r mi_shifts +ffffffff82c2bfe0 r mi_masks +ffffffff82c2c100 r ipp_regs +ffffffff82c2c2f8 r ipp_shift +ffffffff82c2c320 r ipp_mask +ffffffff82c2c3c0 r xfm_regs +ffffffff82c2c960 r xfm_shift +ffffffff82c2c9c0 r xfm_mask +ffffffff82c2cb40 r opp_regs +ffffffff82c2cc90 r opp_shift +ffffffff82c2ccbc r opp_mask +ffffffff82c2cd70 r aux_engine_regs +ffffffff82c2ce60 r aux_mask +ffffffff82c2cec0 r aux_shift +ffffffff82c2cee0 r i2c_hw_regs +ffffffff82c2d030 r i2c_shifts +ffffffff82c2d05c r i2c_masks +ffffffff82c2d100 r audio_regs +ffffffff82c2d234 r audio_shift +ffffffff82c2d24c r audio_mask +ffffffff82c2d290 r stream_enc_regs +ffffffff82c2d848 r se_shift +ffffffff82c2d8cc r se_mask +ffffffff82c2dad0 r dce121_hwseq_reg +ffffffff82c2dcec r dce121_hwseq_shift +ffffffff82c2dd6c r dce121_hwseq_mask +ffffffff82c2df60 r hwseq_reg +ffffffff82c2e17c r hwseq_shift +ffffffff82c2e1fc r hwseq_mask +ffffffff82c2f000 r dce120_tg_funcs +ffffffff82c30000 r bios_regs +ffffffff82c30008 r res_cap +ffffffff82c30048 r dce80_res_pool_funcs +ffffffff82c30140 r debug_defaults +ffffffff82c302f0 r clk_src_regs +ffffffff82c303ec r dmcu_regs +ffffffff82c30448 r dmcu_shift +ffffffff82c3045c r dmcu_mask +ffffffff82c304a8 r abm_regs +ffffffff82c30510 r abm_shift +ffffffff82c30534 r abm_mask +ffffffff82c305c0 r dce80_tg_offsets +ffffffff82c30608 r plane_cap +ffffffff82c30638 r res_create_funcs +ffffffff82c30670 r panel_cntl_regs +ffffffff82c30690 r panel_cntl_shift +ffffffff82c306a0 r panel_cntl_mask +ffffffff82c306e0 r link_enc_regs +ffffffff82c30aa0 r link_enc_aux_regs +ffffffff82c30af0 r link_enc_hpd_regs +ffffffff82c30b08 r link_enc_feature +ffffffff82c30b18 r cs_shift +ffffffff82c30b24 r cs_mask +ffffffff82c30b50 r mi_regs +ffffffff82c30e68 r mi_shifts +ffffffff82c30eb0 r mi_masks +ffffffff82c30fd0 r ipp_regs +ffffffff82c311c8 r ipp_shift +ffffffff82c311f0 r ipp_mask +ffffffff82c31290 r xfm_regs +ffffffff82c31830 r xfm_shift +ffffffff82c31890 r xfm_mask +ffffffff82c31a10 r opp_regs +ffffffff82c31b60 r opp_shift +ffffffff82c31b8c r opp_mask +ffffffff82c31c40 r aux_engine_regs +ffffffff82c31d30 r aux_mask +ffffffff82c31d90 r aux_shift +ffffffff82c31db0 r i2c_hw_regs +ffffffff82c31f00 r i2c_shifts +ffffffff82c31f2c r i2c_masks +ffffffff82c31fd0 r audio_regs +ffffffff82c32104 r audio_shift +ffffffff82c3211c r audio_mask +ffffffff82c32160 r stream_enc_regs +ffffffff82c3280c r se_shift +ffffffff82c32890 r se_mask +ffffffff82c32a94 r hwseq_reg +ffffffff82c32cb0 r hwseq_shift +ffffffff82c32d30 r hwseq_mask +ffffffff82c32f24 r res_cap_81 +ffffffff82c32f60 r res_cap_83 +ffffffff82c33000 r reg_offsets +ffffffff82c33048 r dce80_tg_funcs +ffffffff82c34000 r dcn10_dpp_funcs +ffffffff82c35000 r dpp_input_csc_matrix +ffffffff82c37000 R dcn10_dwbc_funcs +ffffffff82c38000 r hubbub1_funcs +ffffffff82c39000 r dcn10_hubp_funcs +ffffffff82c3a000 r reduceSizeAndFraction.prime_numbers +ffffffff82c3c000 r dcn10_funcs +ffffffff82c3c2e8 r dcn10_private_funcs +ffffffff82c3d000 r dcn10_ipp_funcs +ffffffff82c3d048 r dcn20_ipp_funcs +ffffffff82c3e000 r dcn10_lnk_enc_funcs +ffffffff82c3f000 r dcn10_mpc_funcs +ffffffff82c40000 r dcn10_opp_funcs +ffffffff82c41000 r dcn10_tg_funcs +ffffffff82c42000 r bios_regs +ffffffff82c42008 r rv2_res_cap +ffffffff82c42044 r res_cap +ffffffff82c42080 r dcn10_res_pool_funcs +ffffffff82c42178 r debug_defaults_drv +ffffffff82c42320 r debug_defaults_diags +ffffffff82c424d0 r clk_src_regs +ffffffff82c42620 r dmcu_regs +ffffffff82c4267c r dmcu_shift +ffffffff82c42690 r dmcu_mask +ffffffff82c426dc r abm_regs +ffffffff82c42744 r abm_shift +ffffffff82c42768 r abm_mask +ffffffff82c427f8 r res_create_funcs +ffffffff82c42828 r plane_cap +ffffffff82c42860 r panel_cntl_regs +ffffffff82c42880 r panel_cntl_shift +ffffffff82c42890 r panel_cntl_mask +ffffffff82c428d0 r link_enc_regs +ffffffff82c42de0 r link_enc_aux_regs +ffffffff82c42e20 r link_enc_hpd_regs +ffffffff82c42e30 r le_shift +ffffffff82c42f20 r le_mask +ffffffff82c432d8 r link_enc_feature +ffffffff82c432e8 r cs_shift +ffffffff82c432f4 r cs_mask +ffffffff82c43320 r hubp_regs +ffffffff82c439d0 r hubp_shift +ffffffff82c43a94 r hubp_mask +ffffffff82c43da0 r ipp_regs +ffffffff82c43e80 r ipp_shift +ffffffff82c43e9c r ipp_mask +ffffffff82c43f10 r tf_regs +ffffffff82c44e80 r tf_shift +ffffffff82c450e8 r tf_mask +ffffffff82c45a80 r opp_regs +ffffffff82c45b50 r opp_shift +ffffffff82c45b70 r opp_mask +ffffffff82c45bf0 r tg_regs +ffffffff82c46190 r tg_shift +ffffffff82c46264 r tg_mask +ffffffff82c465b0 r aux_engine_regs +ffffffff82c466a0 r aux_mask +ffffffff82c46700 r aux_shift +ffffffff82c46720 r i2c_hw_regs +ffffffff82c46870 r i2c_shifts +ffffffff82c4689c r i2c_masks +ffffffff82c46940 r mpc_regs +ffffffff82c46a60 r mpc_shift +ffffffff82c46a78 r mpc_mask +ffffffff82c46ad4 r hubbub_reg +ffffffff82c46c5c r hubbub_shift +ffffffff82c46cec r hubbub_mask +ffffffff82c46f30 r audio_regs +ffffffff82c46fe0 r audio_shift +ffffffff82c46ff8 r audio_mask +ffffffff82c47040 r stream_enc_regs +ffffffff82c47590 r se_shift +ffffffff82c4766c r se_mask +ffffffff82c479d8 r hwseq_reg +ffffffff82c47bf4 r hwseq_shift +ffffffff82c47c74 r hwseq_mask +ffffffff82c48000 r audio_clock_info_table_48bpc +ffffffff82c48190 r audio_clock_info_table_36bpc +ffffffff82c48320 r audio_clock_info_table +ffffffff82c484e0 r dcn10_str_enc_funcs +ffffffff82c49000 r dccg2_funcs +ffffffff82c4b000 r dpp_input_csc_matrix +ffffffff82c4c000 r dcn20_dsc_funcs +ffffffff82c4d000 r dcn20_dwbc_funcs +ffffffff82c4e000 r filter_12tap_16p_upscale +ffffffff82c4e0e0 r filter_12tap_16p_117 +ffffffff82c4e1c0 r filter_12tap_16p_150 +ffffffff82c4e2a0 r filter_12tap_16p_183 +ffffffff82c4e380 r filter_11tap_16p_upscale +ffffffff82c4e450 r filter_11tap_16p_117 +ffffffff82c4e520 r filter_11tap_16p_150 +ffffffff82c4e5f0 r filter_11tap_16p_183 +ffffffff82c4e6c0 r filter_10tap_16p_upscale +ffffffff82c4e780 r filter_10tap_16p_117 +ffffffff82c4e840 r filter_10tap_16p_150 +ffffffff82c4e900 r filter_10tap_16p_183 +ffffffff82c4e9c0 r filter_9tap_16p_upscale +ffffffff82c4ea70 r filter_9tap_16p_117 +ffffffff82c4eb20 r filter_9tap_16p_150 +ffffffff82c4ebd0 r filter_9tap_16p_183 +ffffffff82c4ec80 r filter_8tap_16p_upscale +ffffffff82c4ed10 r filter_8tap_16p_117 +ffffffff82c4eda0 r filter_8tap_16p_150 +ffffffff82c4ee30 r filter_8tap_16p_183 +ffffffff82c4eec0 r filter_7tap_16p_upscale +ffffffff82c4ef40 r filter_7tap_16p_117 +ffffffff82c4efc0 r filter_7tap_16p_150 +ffffffff82c4f040 r filter_7tap_16p_183 +ffffffff82c4f0c0 r filter_6tap_16p_upscale +ffffffff82c4f130 r filter_6tap_16p_117 +ffffffff82c4f1a0 r filter_6tap_16p_150 +ffffffff82c4f210 r filter_6tap_16p_183 +ffffffff82c4f280 r filter_5tap_16p_upscale +ffffffff82c4f2e0 r filter_5tap_16p_117 +ffffffff82c4f340 r filter_5tap_16p_150 +ffffffff82c4f3a0 r filter_5tap_16p_183 +ffffffff82c4f400 r filter_4tap_16p_upscale +ffffffff82c4f450 r filter_4tap_16p_117 +ffffffff82c4f4a0 r filter_4tap_16p_150 +ffffffff82c4f4f0 r filter_4tap_16p_183 +ffffffff82c4f540 r filter_3tap_16p_upscale +ffffffff82c4f580 r filter_3tap_16p_117 +ffffffff82c4f5c0 r filter_3tap_16p_150 +ffffffff82c4f600 r filter_3tap_16p_183 +ffffffff82c50000 r hubbub2_funcs +ffffffff82c51000 r dcn20_funcs +ffffffff82c512e8 r dcn20_private_funcs +ffffffff82c52000 r dcn20_link_enc_funcs +ffffffff82c520e0 r dcn2_mpll_cfg +ffffffff82c53000 r dcn20_mmhubbub_funcs +ffffffff82c54000 r dcn20_mpc_funcs +ffffffff82c55000 r tf_regs +ffffffff82c56938 r tf_shift +ffffffff82c56bc0 r tf_mask +ffffffff82c575e0 r ipp_regs +ffffffff82c57730 r ipp_shift +ffffffff82c5774c r ipp_mask +ffffffff82c577c0 r opp_regs +ffffffff82c579d0 r opp_shift +ffffffff82c57a08 r opp_mask +ffffffff82c57ae0 r aux_engine_regs +ffffffff82c57bd0 r aux_mask +ffffffff82c57c30 r aux_shift +ffffffff82c57c50 r i2c_hw_regs +ffffffff82c57da0 r i2c_shifts +ffffffff82c57dcc r i2c_masks +ffffffff82c57e70 r mpc_regs +ffffffff82c583b8 r mpc_shift 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+ffffffff82cad99c r vpg_shift +ffffffff82cad9c4 r vpg_mask +ffffffff82cada60 r afmt_regs +ffffffff82cadacc r afmt_shift +ffffffff82cadae0 r afmt_mask +ffffffff82cadb24 r hwseq_reg +ffffffff82cadd40 r hwseq_shift +ffffffff82caddc0 r hwseq_mask +ffffffff82cae000 r dccg31_funcs +ffffffff82caf000 r dcn31_link_enc_funcs +ffffffff82cb0000 r dcn30_str_enc_funcs +ffffffff82cb1000 r hubbub31_funcs +ffffffff82cb2000 r dcn31_funcs +ffffffff82cb22e8 r dcn31_private_funcs +ffffffff82cb3000 r dcn31_link_panel_cntl_funcs +ffffffff82cb4000 r bios_regs +ffffffff82cb4008 r res_cap_dcn31 +ffffffff82cb4050 r clk_src_regs +ffffffff82cb4200 r clk_src_regs_b0 +ffffffff82cb43a4 r dccg_regs +ffffffff82cb4494 r dccg_shift +ffffffff82cb4534 r dccg_mask +ffffffff82cb47b0 r abm_regs +ffffffff82cb4950 r abm_shift +ffffffff82cb4974 r abm_mask +ffffffff82cb4a00 r res_create_funcs +ffffffff82cb4a30 r plane_cap +ffffffff82cb4a60 r link_enc_regs +ffffffff82cb50c0 r link_enc_aux_regs +ffffffff82cb5110 r link_enc_hpd_regs +ffffffff82cb5124 r le_shift +ffffffff82cb5214 r le_mask +ffffffff82cb55cc r link_enc_feature +ffffffff82cb55dc r panel_config_defaults +ffffffff82cb5630 r debug_defaults_drv +ffffffff82cb57d8 r cs_shift +ffffffff82cb57e4 r cs_mask +ffffffff82cb580c r hubbub_reg +ffffffff82cb5994 r hubbub_shift +ffffffff82cb5a24 r hubbub_mask +ffffffff82cb5c60 r vmid_regs +ffffffff82cb5e20 r vmid_shifts +ffffffff82cb5e28 r vmid_masks +ffffffff82cb5e50 r hubp_regs +ffffffff82cb6680 r hubp_shift +ffffffff82cb677c r hubp_mask +ffffffff82cb6b70 r dpp_regs +ffffffff82cb8080 r tf_shift +ffffffff82cb8354 r tf_mask +ffffffff82cb8ea0 r opp_regs +ffffffff82cb9000 r opp_shift +ffffffff82cb9038 r opp_mask +ffffffff82cb9110 r optc_regs +ffffffff82cb96b0 r optc_shift +ffffffff82cb9784 r optc_mask +ffffffff82cb9acc r mpc_regs +ffffffff82cbb2b8 r mpc_shift +ffffffff82cbb394 r mpc_mask +ffffffff82cbb700 r dsc_regs +ffffffff82cbb94c r dsc_shift +ffffffff82cbba04 r dsc_mask +ffffffff82cbbce0 r dwbc30_regs +ffffffff82cbbebc r dwbc30_shift +ffffffff82cbbff0 r dwbc30_mask +ffffffff82cbc4c0 r mcif_wb30_regs +ffffffff82cbc5bc r mcif_wb30_shift +ffffffff82cbc668 r mcif_wb30_mask +ffffffff82cbc920 r aux_engine_regs +ffffffff82cbc9e8 r aux_mask +ffffffff82cbca48 r aux_shift +ffffffff82cbca60 r i2c_hw_regs +ffffffff82cbcb78 r i2c_shifts +ffffffff82cbcba4 r i2c_masks +ffffffff82cbcc50 r audio_regs +ffffffff82cbcd84 r audio_shift +ffffffff82cbcd9c r audio_mask +ffffffff82cbcdd8 r se_shift +ffffffff82cbceb4 r se_mask +ffffffff82cbd220 r vpg_regs +ffffffff82cbd310 r vpg_shift +ffffffff82cbd338 r vpg_mask +ffffffff82cbd3e0 r afmt_regs +ffffffff82cbd4b8 r afmt_shift +ffffffff82cbd4cc r afmt_mask +ffffffff82cbd520 r stream_enc_regs +ffffffff82cbebc0 r hpo_dp_stream_enc_regs +ffffffff82cbedf0 r hpo_dp_se_shift +ffffffff82cbee18 r hpo_dp_se_mask +ffffffff82cbeec0 r apg_regs +ffffffff82cbef00 r apg_shift +ffffffff82cbef08 r apg_mask +ffffffff82cbef20 r hpo_dp_link_enc_regs +ffffffff82cbf030 r hpo_dp_le_shift +ffffffff82cbf04c r hpo_dp_le_mask +ffffffff82cbf0b0 r hwseq_reg +ffffffff82cbf2cc r hwseq_shift +ffffffff82cbf34c r hwseq_mask +ffffffff82cc0000 r dccg314_funcs +ffffffff82cc1000 r dcn314_str_enc_funcs +ffffffff82cc2000 r dcn314_funcs +ffffffff82cc22e8 r dcn314_private_funcs +ffffffff82cc3000 r bios_regs +ffffffff82cc3008 r res_cap_dcn314 +ffffffff82cc3048 r debug_defaults_diags +ffffffff82cc31f0 r clk_src_regs +ffffffff82cc3394 r dccg_regs +ffffffff82cc3484 r dccg_shift +ffffffff82cc3524 r dccg_mask +ffffffff82cc37a0 r abm_regs +ffffffff82cc3940 r abm_shift +ffffffff82cc3964 r abm_mask +ffffffff82cc39f0 r res_create_funcs +ffffffff82cc3a20 r plane_cap +ffffffff82cc3a50 r link_enc_regs +ffffffff82cc40b0 r link_enc_aux_regs +ffffffff82cc4100 r link_enc_hpd_regs +ffffffff82cc4114 r le_shift +ffffffff82cc4204 r le_mask +ffffffff82cc45bc r link_enc_feature +ffffffff82cc45cc r panel_config_defaults +ffffffff82cc4620 r debug_defaults_drv +ffffffff82cc47c8 r cs_shift +ffffffff82cc47d4 r cs_mask +ffffffff82cc47fc r hubbub_reg +ffffffff82cc4984 r hubbub_shift +ffffffff82cc4a14 r hubbub_mask +ffffffff82cc4c50 r vmid_regs +ffffffff82cc4e10 r vmid_shifts +ffffffff82cc4e18 r vmid_masks +ffffffff82cc4e40 r hubp_regs +ffffffff82cc5670 r hubp_shift +ffffffff82cc576c r hubp_mask +ffffffff82cc5b60 r dpp_regs +ffffffff82cc7070 r tf_shift +ffffffff82cc7344 r tf_mask +ffffffff82cc7e90 r opp_regs +ffffffff82cc7ff0 r opp_shift +ffffffff82cc8028 r opp_mask +ffffffff82cc8100 r optc_regs +ffffffff82cc86a0 r optc_shift +ffffffff82cc8774 r optc_mask +ffffffff82cc8abc r mpc_regs +ffffffff82cca2a8 r mpc_shift +ffffffff82cca384 r mpc_mask +ffffffff82cca6f0 r dsc_regs +ffffffff82ccaa00 r dsc_shift +ffffffff82ccaab8 r dsc_mask +ffffffff82ccad90 r dwbc30_regs +ffffffff82ccaf6c r dwbc30_shift +ffffffff82ccb0a0 r dwbc30_mask +ffffffff82ccb570 r mcif_wb30_regs +ffffffff82ccb66c r mcif_wb30_shift +ffffffff82ccb718 r mcif_wb30_mask +ffffffff82ccb9d0 r aux_engine_regs +ffffffff82ccba98 r aux_mask +ffffffff82ccbaf8 r aux_shift +ffffffff82ccbb10 r i2c_hw_regs +ffffffff82ccbc28 r i2c_shifts +ffffffff82ccbc54 r i2c_masks +ffffffff82ccbd00 r audio_regs +ffffffff82ccbe34 r audio_shift +ffffffff82ccbe4c r audio_mask +ffffffff82ccbe90 r stream_enc_regs +ffffffff82ccc534 r se_shift +ffffffff82ccc610 r se_mask +ffffffff82ccc980 r vpg_regs +ffffffff82ccca70 r vpg_shift +ffffffff82ccca98 r vpg_mask +ffffffff82cccb40 r afmt_regs +ffffffff82cccc18 r afmt_shift +ffffffff82cccc2c r afmt_mask +ffffffff82cccc80 r hpo_dp_stream_enc_regs +ffffffff82ccceb0 r hpo_dp_se_shift +ffffffff82ccced8 r hpo_dp_se_mask +ffffffff82cccf80 r apg_regs +ffffffff82cccfc0 r apg_shift +ffffffff82cccfc8 r apg_mask +ffffffff82cccfe0 r hpo_dp_link_enc_regs +ffffffff82ccd0f0 r hpo_dp_le_shift +ffffffff82ccd10c r hpo_dp_le_mask +ffffffff82ccd170 r hwseq_reg +ffffffff82ccd38c r hwseq_shift +ffffffff82ccd40c r hwseq_mask +ffffffff82cce000 r bios_regs +ffffffff82cce008 r res_cap_dcn31 +ffffffff82cce050 r clk_src_regs +ffffffff82cce1f4 r dccg_regs +ffffffff82cce2e4 r dccg_shift +ffffffff82cce384 r dccg_mask +ffffffff82cce600 r abm_regs +ffffffff82cce7a0 r abm_shift +ffffffff82cce7c4 r abm_mask +ffffffff82cce850 r res_create_funcs +ffffffff82cce880 r plane_cap +ffffffff82cce8b0 r link_enc_regs +ffffffff82ccef10 r link_enc_aux_regs +ffffffff82ccef60 r link_enc_hpd_regs +ffffffff82ccef74 r le_shift +ffffffff82ccf064 r le_mask +ffffffff82ccf41c r link_enc_feature +ffffffff82ccf42c r panel_config_defaults +ffffffff82ccf480 r debug_defaults_drv +ffffffff82ccf628 r cs_shift +ffffffff82ccf634 r cs_mask +ffffffff82ccf65c r hubbub_reg +ffffffff82ccf7e4 r hubbub_shift +ffffffff82ccf874 r hubbub_mask +ffffffff82ccfab0 r vmid_regs +ffffffff82ccfc70 r vmid_shifts +ffffffff82ccfc78 r vmid_masks +ffffffff82ccfca0 r hubp_regs +ffffffff82cd04d0 r hubp_shift +ffffffff82cd05cc r hubp_mask +ffffffff82cd09c0 r dpp_regs +ffffffff82cd1ed0 r tf_shift +ffffffff82cd21a4 r tf_mask +ffffffff82cd2cf0 r opp_regs +ffffffff82cd2e50 r opp_shift +ffffffff82cd2e88 r opp_mask +ffffffff82cd2f60 r optc_regs +ffffffff82cd3500 r optc_shift +ffffffff82cd35d4 r optc_mask +ffffffff82cd391c r mpc_regs +ffffffff82cd5108 r mpc_shift +ffffffff82cd51e4 r mpc_mask +ffffffff82cd5550 r dsc_regs +ffffffff82cd579c r dsc_shift +ffffffff82cd5854 r dsc_mask +ffffffff82cd5b30 r dwbc30_regs +ffffffff82cd5d0c r dwbc30_shift +ffffffff82cd5e40 r dwbc30_mask +ffffffff82cd6310 r mcif_wb30_regs +ffffffff82cd640c r mcif_wb30_shift +ffffffff82cd64b8 r mcif_wb30_mask +ffffffff82cd6770 r aux_engine_regs +ffffffff82cd6838 r aux_mask +ffffffff82cd6898 r aux_shift +ffffffff82cd68b0 r i2c_hw_regs +ffffffff82cd69c8 r i2c_shifts +ffffffff82cd69f4 r i2c_masks +ffffffff82cd6aa0 r audio_regs +ffffffff82cd6bd4 r audio_shift +ffffffff82cd6bec r audio_mask +ffffffff82cd6c30 r stream_enc_regs +ffffffff82cd72d4 r se_shift +ffffffff82cd73b0 r se_mask +ffffffff82cd7720 r vpg_regs +ffffffff82cd7810 r vpg_shift +ffffffff82cd7838 r vpg_mask +ffffffff82cd78e0 r afmt_regs +ffffffff82cd79b8 r afmt_shift +ffffffff82cd79cc r afmt_mask +ffffffff82cd7a20 r hpo_dp_stream_enc_regs +ffffffff82cd7c50 r hpo_dp_se_shift +ffffffff82cd7c78 r hpo_dp_se_mask +ffffffff82cd7d20 r apg_regs +ffffffff82cd7d60 r apg_shift +ffffffff82cd7d68 r apg_mask +ffffffff82cd7d80 r hpo_dp_link_enc_regs +ffffffff82cd7e90 r hpo_dp_le_shift +ffffffff82cd7eac r hpo_dp_le_mask +ffffffff82cd7f10 r hwseq_reg +ffffffff82cd812c r hwseq_shift +ffffffff82cd81ac r hwseq_mask +ffffffff82cd9000 r bios_regs +ffffffff82cd9008 r res_cap_dcn31 +ffffffff82cd9050 r clk_src_regs +ffffffff82cd91f4 r dccg_regs +ffffffff82cd92e4 r dccg_shift +ffffffff82cd9384 r dccg_mask +ffffffff82cd9600 r abm_regs +ffffffff82cd97a0 r abm_shift +ffffffff82cd97c4 r abm_mask +ffffffff82cd9850 r res_create_funcs +ffffffff82cd9880 r plane_cap +ffffffff82cd98b0 r link_enc_regs +ffffffff82cd9f10 r link_enc_aux_regs +ffffffff82cd9f60 r link_enc_hpd_regs +ffffffff82cd9f74 r le_shift +ffffffff82cda064 r le_mask +ffffffff82cda41c r link_enc_feature +ffffffff82cda42c r panel_config_defaults +ffffffff82cda480 r debug_defaults_drv +ffffffff82cda628 r cs_shift +ffffffff82cda634 r cs_mask +ffffffff82cda65c r hubbub_reg +ffffffff82cda7e4 r hubbub_shift +ffffffff82cda874 r hubbub_mask +ffffffff82cdaab0 r vmid_regs +ffffffff82cdac70 r vmid_shifts +ffffffff82cdac78 r vmid_masks +ffffffff82cdaca0 r hubp_regs +ffffffff82cdb4d0 r hubp_shift +ffffffff82cdb5cc r hubp_mask +ffffffff82cdb9c0 r dpp_regs +ffffffff82cdced0 r tf_shift +ffffffff82cdd1a4 r tf_mask +ffffffff82cddcf0 r opp_regs +ffffffff82cdde50 r opp_shift +ffffffff82cdde88 r opp_mask +ffffffff82cddf60 r optc_regs +ffffffff82cde500 r optc_shift +ffffffff82cde5d4 r optc_mask +ffffffff82cde91c r mpc_regs +ffffffff82ce0108 r mpc_shift +ffffffff82ce01e4 r mpc_mask +ffffffff82ce0550 r dsc_regs +ffffffff82ce079c r dsc_shift +ffffffff82ce0854 r dsc_mask +ffffffff82ce0b30 r dwbc30_regs +ffffffff82ce0d0c r dwbc30_shift +ffffffff82ce0e40 r dwbc30_mask +ffffffff82ce1310 r mcif_wb30_regs +ffffffff82ce140c r mcif_wb30_shift +ffffffff82ce14b8 r mcif_wb30_mask +ffffffff82ce1770 r aux_engine_regs +ffffffff82ce1838 r aux_mask +ffffffff82ce1898 r aux_shift +ffffffff82ce18b0 r i2c_hw_regs +ffffffff82ce19c8 r i2c_shifts +ffffffff82ce19f4 r i2c_masks +ffffffff82ce1aa0 r audio_regs +ffffffff82ce1bd4 r audio_shift +ffffffff82ce1bec r audio_mask +ffffffff82ce1c30 r stream_enc_regs +ffffffff82ce22d4 r se_shift +ffffffff82ce23b0 r se_mask +ffffffff82ce2720 r vpg_regs +ffffffff82ce2810 r vpg_shift +ffffffff82ce2838 r vpg_mask +ffffffff82ce28e0 r afmt_regs +ffffffff82ce29b8 r afmt_shift +ffffffff82ce29cc r afmt_mask +ffffffff82ce2a20 r hpo_dp_stream_enc_regs +ffffffff82ce2c50 r hpo_dp_se_shift +ffffffff82ce2c78 r hpo_dp_se_mask +ffffffff82ce2d20 r apg_regs +ffffffff82ce2d60 r apg_shift +ffffffff82ce2d68 r apg_mask +ffffffff82ce2d80 r hpo_dp_link_enc_regs +ffffffff82ce2e90 r hpo_dp_le_shift +ffffffff82ce2eac r hpo_dp_le_mask +ffffffff82ce2f10 r hwseq_reg +ffffffff82ce312c r hwseq_shift +ffffffff82ce31ac r hwseq_mask +ffffffff82ce4000 r dccg32_funcs +ffffffff82ce5000 r dcn32_link_enc_funcs +ffffffff82ce6000 r dcn32_str_enc_funcs +ffffffff82ce7000 r hubbub32_funcs +ffffffff82ce8000 r dcn32_funcs +ffffffff82ce82e8 r dcn32_private_funcs +ffffffff82ce9000 r dcn32_mmhubbub_funcs +ffffffff82cea000 r dcn32_mpc_funcs +ffffffff82ceb000 r res_cap_dcn32 +ffffffff82ceb03c r dccg_shift +ffffffff82ceb0dc r dccg_mask +ffffffff82ceb350 r abm_shift +ffffffff82ceb374 r abm_mask +ffffffff82ceb400 r res_create_funcs +ffffffff82ceb430 r plane_cap +ffffffff82ceb45c r le_shift +ffffffff82ceb54c r le_mask +ffffffff82ceb904 r link_enc_feature +ffffffff82ceb918 r debug_defaults_drv +ffffffff82cebac0 r cs_shift +ffffffff82cebacc r cs_mask +ffffffff82cebaf4 r hubbub_shift +ffffffff82cebb84 r hubbub_mask +ffffffff82cebdbc r vmid_shifts +ffffffff82cebdc4 r vmid_masks +ffffffff82cebde4 r hubp_shift +ffffffff82cebee0 r hubp_mask +ffffffff82cec2d0 r tf_shift +ffffffff82cec5a4 r tf_mask +ffffffff82ced0e8 r opp_shift +ffffffff82ced120 r opp_mask +ffffffff82ced1f4 r optc_shift +ffffffff82ced2c8 r optc_mask +ffffffff82ced610 r mpc_shift +ffffffff82ced6ec r mpc_mask +ffffffff82ceda58 r dsc_shift +ffffffff82cedb10 r dsc_mask +ffffffff82cedde8 r dwbc30_shift +ffffffff82cedf1c r dwbc30_mask +ffffffff82cee3e4 r mcif_wb30_shift +ffffffff82cee490 r mcif_wb30_mask +ffffffff82cee73c r aux_mask +ffffffff82cee79c r aux_shift +ffffffff82cee7b4 r i2c_shifts +ffffffff82cee7e0 r i2c_masks +ffffffff82cee884 r audio_shift +ffffffff82cee89c r audio_mask +ffffffff82cee8d8 r se_shift +ffffffff82cee9b4 r se_mask +ffffffff82ceed20 r vpg_shift +ffffffff82ceed48 r vpg_mask +ffffffff82ceeddc r afmt_shift +ffffffff82ceedf0 r afmt_mask +ffffffff82ceee34 r hpo_dp_se_shift +ffffffff82ceee5c r hpo_dp_se_mask +ffffffff82ceeefc r apg_shift +ffffffff82ceef04 r apg_mask +ffffffff82ceef1c r hpo_dp_le_shift +ffffffff82ceef38 r hpo_dp_le_mask +ffffffff82ceef9c r hwseq_shift +ffffffff82cef01c r hwseq_mask +ffffffff82cf0000 r dcn321_link_enc_funcs +ffffffff82cf1000 r res_cap_dcn321 +ffffffff82cf103c r dccg_shift +ffffffff82cf10dc r dccg_mask +ffffffff82cf1350 r abm_shift +ffffffff82cf1374 r abm_mask +ffffffff82cf1400 r res_create_funcs +ffffffff82cf1430 r plane_cap +ffffffff82cf145c r le_shift +ffffffff82cf154c r le_mask +ffffffff82cf1904 r link_enc_feature +ffffffff82cf1918 r debug_defaults_drv +ffffffff82cf1ac0 r cs_shift +ffffffff82cf1acc r cs_mask +ffffffff82cf1af4 r hubbub_shift +ffffffff82cf1b84 r hubbub_mask +ffffffff82cf1dbc r vmid_shifts +ffffffff82cf1dc4 r vmid_masks +ffffffff82cf1de4 r hubp_shift +ffffffff82cf1ee0 r hubp_mask +ffffffff82cf22d0 r tf_shift +ffffffff82cf25a4 r tf_mask +ffffffff82cf30e8 r opp_shift +ffffffff82cf3120 r opp_mask +ffffffff82cf31f4 r optc_shift +ffffffff82cf32c8 r optc_mask +ffffffff82cf3610 r mpc_shift +ffffffff82cf36ec r mpc_mask +ffffffff82cf3a58 r dsc_shift +ffffffff82cf3b10 r dsc_mask +ffffffff82cf3de8 r dwbc30_shift +ffffffff82cf3f1c r dwbc30_mask +ffffffff82cf43e4 r mcif_wb30_shift +ffffffff82cf4490 r mcif_wb30_mask +ffffffff82cf473c r aux_mask +ffffffff82cf479c r aux_shift +ffffffff82cf47b4 r i2c_shifts +ffffffff82cf47e0 r i2c_masks +ffffffff82cf4884 r audio_shift +ffffffff82cf489c r audio_mask +ffffffff82cf48d8 r se_shift +ffffffff82cf49b4 r se_mask +ffffffff82cf4d20 r vpg_shift +ffffffff82cf4d48 r vpg_mask +ffffffff82cf4ddc r afmt_shift +ffffffff82cf4df0 r afmt_mask +ffffffff82cf4e34 r hpo_dp_se_shift +ffffffff82cf4e5c r hpo_dp_se_mask +ffffffff82cf4efc r apg_shift +ffffffff82cf4f04 r apg_mask +ffffffff82cf4f1c r hpo_dp_le_shift +ffffffff82cf4f38 r hpo_dp_le_mask +ffffffff82cf4f9c r hwseq_shift +ffffffff82cf501c r hwseq_mask +ffffffff82cf7000 R dcn10_soc_defaults +ffffffff82cf708c R dcn10_ip_defaults +ffffffff82d03000 r dml20_funcs +ffffffff82d03030 r dml20v2_funcs +ffffffff82d03060 r dml21_funcs +ffffffff82d03090 r dml30_funcs +ffffffff82d030c0 r dml31_funcs +ffffffff82d030f0 r dml314_funcs +ffffffff82d03120 r dml32_funcs +ffffffff82d06000 r qp_table_444_8bpc_max +ffffffff82d06940 r qp_table_444_8bpc_min +ffffffff82d07280 r qp_table_444_10bpc_max +ffffffff82d07ec0 r qp_table_444_10bpc_min +ffffffff82d08b00 r qp_table_444_12bpc_max +ffffffff82d09a40 r qp_table_444_12bpc_min +ffffffff82d0a980 r qp_table_422_8bpc_max +ffffffff82d0aec0 r qp_table_422_8bpc_min +ffffffff82d0b400 r qp_table_422_10bpc_max +ffffffff82d0bb40 r qp_table_422_10bpc_min +ffffffff82d0c280 r qp_table_422_12bpc_max +ffffffff82d0cbc0 r qp_table_422_12bpc_min +ffffffff82d0d500 r qp_table_420_8bpc_max +ffffffff82d0d940 r qp_table_420_8bpc_min +ffffffff82d0dd80 r qp_table_420_10bpc_max +ffffffff82d0e340 r qp_table_420_10bpc_min +ffffffff82d0e900 r qp_table_420_12bpc_max +ffffffff82d0f040 r qp_table_420_12bpc_min ffffffff82d11000 r funcs ffffffff82d11050 r hpd_regs ffffffff82d111a0 r hpd_shift @@ -47697,111 +47690,111 @@ ffffffff82d151c0 r ddc_data_regs ffffffff82d153a0 r ddc_clk_regs ffffffff82d15580 r ddc_shift ffffffff82d155a8 r ddc_mask -ffffffff82d155d0 r generic_regs -ffffffff82d15640 r generic_shift -ffffffff82d15650 r generic_mask ffffffff82d16000 r funcs ffffffff82d17000 r funcs ffffffff82d17050 r hpd_regs ffffffff82d171a0 r hpd_shift ffffffff82d171b0 r hpd_mask -ffffffff82d171c0 r ddc_data_regs_dcn -ffffffff82d17370 r ddc_clk_regs_dcn -ffffffff82d17520 r ddc_shift -ffffffff82d17640 r ddc_mask -ffffffff82d17760 r generic_regs -ffffffff82d177d0 r generic_shift -ffffffff82d177e0 r generic_mask +ffffffff82d171c0 r ddc_data_regs +ffffffff82d173a0 r ddc_clk_regs +ffffffff82d17580 r ddc_shift +ffffffff82d175a8 r ddc_mask +ffffffff82d175d0 r generic_regs +ffffffff82d17640 r generic_shift +ffffffff82d17650 r generic_mask ffffffff82d18000 r funcs ffffffff82d19000 r funcs ffffffff82d19050 r hpd_regs -ffffffff82d19168 r hpd_shift -ffffffff82d19178 r hpd_mask -ffffffff82d19190 r ddc_data_regs_dcn -ffffffff82d192c0 r ddc_clk_regs_dcn -ffffffff82d193f0 r ddc_shift -ffffffff82d194e0 r ddc_mask -ffffffff82d195d0 r generic_regs -ffffffff82d19604 r generic_shift -ffffffff82d1960c r generic_mask +ffffffff82d191a0 r hpd_shift +ffffffff82d191b0 r hpd_mask +ffffffff82d191c0 r ddc_data_regs_dcn +ffffffff82d19370 r ddc_clk_regs_dcn +ffffffff82d19520 r ddc_shift +ffffffff82d19640 r ddc_mask +ffffffff82d19760 r generic_regs +ffffffff82d197d0 r generic_shift +ffffffff82d197e0 r generic_mask ffffffff82d1a000 r funcs ffffffff82d1b000 r funcs ffffffff82d1b050 r hpd_regs -ffffffff82d1b1a0 r hpd_shift -ffffffff82d1b1b0 r hpd_mask -ffffffff82d1b1c0 r ddc_data_regs_dcn -ffffffff82d1b370 r ddc_clk_regs_dcn -ffffffff82d1b520 r ddc_shift -ffffffff82d1b640 r ddc_mask -ffffffff82d1b760 r generic_regs -ffffffff82d1b7d0 r generic_shift -ffffffff82d1b7e0 r generic_mask +ffffffff82d1b168 r hpd_shift +ffffffff82d1b178 r hpd_mask +ffffffff82d1b190 r ddc_data_regs_dcn +ffffffff82d1b2c0 r ddc_clk_regs_dcn +ffffffff82d1b3f0 r ddc_shift +ffffffff82d1b4e0 r ddc_mask +ffffffff82d1b5d0 r generic_regs +ffffffff82d1b604 r generic_shift +ffffffff82d1b60c r generic_mask ffffffff82d1c000 r funcs ffffffff82d1d000 r funcs ffffffff82d1d050 r hpd_regs -ffffffff82d1d168 r hpd_shift -ffffffff82d1d178 r hpd_mask -ffffffff82d1d190 r ddc_data_regs_dcn -ffffffff82d1d300 r ddc_clk_regs_dcn -ffffffff82d1d470 r ddc_shift -ffffffff82d1d560 r ddc_mask -ffffffff82d1d650 r generic_regs -ffffffff82d1d6c0 r generic_shift -ffffffff82d1d6d0 r generic_mask +ffffffff82d1d1a0 r hpd_shift +ffffffff82d1d1b0 r hpd_mask +ffffffff82d1d1c0 r ddc_data_regs_dcn +ffffffff82d1d370 r ddc_clk_regs_dcn +ffffffff82d1d520 r ddc_shift +ffffffff82d1d640 r ddc_mask +ffffffff82d1d760 r generic_regs +ffffffff82d1d7d0 r generic_shift +ffffffff82d1d7e0 r generic_mask ffffffff82d1e000 r funcs ffffffff82d1f000 r funcs ffffffff82d1f050 r hpd_regs ffffffff82d1f168 r hpd_shift ffffffff82d1f178 r hpd_mask ffffffff82d1f190 r ddc_data_regs_dcn -ffffffff82d1f340 r ddc_clk_regs_dcn -ffffffff82d1f4f0 r ddc_shift -ffffffff82d1f610 r ddc_mask -ffffffff82d1f730 r generic_regs -ffffffff82d1f7a0 r generic_shift -ffffffff82d1f7b0 r generic_mask +ffffffff82d1f300 r ddc_clk_regs_dcn +ffffffff82d1f470 r ddc_shift +ffffffff82d1f560 r ddc_mask +ffffffff82d1f650 r generic_regs +ffffffff82d1f6c0 r generic_shift +ffffffff82d1f6d0 r generic_mask ffffffff82d20000 r funcs ffffffff82d21000 r funcs +ffffffff82d21050 r hpd_regs +ffffffff82d21168 r hpd_shift +ffffffff82d21178 r hpd_mask +ffffffff82d21190 r ddc_data_regs_dcn +ffffffff82d21340 r ddc_clk_regs_dcn +ffffffff82d214f0 r ddc_shift +ffffffff82d21610 r ddc_mask +ffffffff82d21730 r generic_regs +ffffffff82d217a0 r generic_shift +ffffffff82d217b0 r generic_mask ffffffff82d22000 r funcs ffffffff82d23000 r funcs -ffffffff82d24000 r hdmi_14_protection -ffffffff82d24010 r dp_11_protection -ffffffff82d24020 r hdcp_i2c_offsets -ffffffff82d24050 r hdcp_dpcd_addrs -ffffffff82d25000 r irq_service_funcs_dce110 -ffffffff82d25008 r dummy_irq_info_funcs -ffffffff82d25018 r hpd_irq_info_funcs -ffffffff82d25028 r hpd_rx_irq_info_funcs -ffffffff82d25038 r pflip_irq_info_funcs -ffffffff82d25048 r vupdate_irq_info_funcs -ffffffff82d25058 r vblank_irq_info_funcs -ffffffff82d25070 r irq_source_info_dce110 -ffffffff82d27000 r irq_service_funcs_dce120 +ffffffff82d24000 r funcs +ffffffff82d25000 r funcs +ffffffff82d26000 r hdmi_14_protection +ffffffff82d26010 r dp_11_protection +ffffffff82d26020 r hdcp_i2c_offsets +ffffffff82d26050 r hdcp_dpcd_addrs +ffffffff82d27000 r irq_service_funcs_dce110 ffffffff82d27008 r dummy_irq_info_funcs ffffffff82d27018 r hpd_irq_info_funcs ffffffff82d27028 r hpd_rx_irq_info_funcs ffffffff82d27038 r pflip_irq_info_funcs ffffffff82d27048 r vupdate_irq_info_funcs ffffffff82d27058 r vblank_irq_info_funcs -ffffffff82d27070 r irq_source_info_dce120 -ffffffff82d29000 r irq_service_funcs_dce80 +ffffffff82d27070 r irq_source_info_dce110 +ffffffff82d29000 r irq_service_funcs_dce120 ffffffff82d29008 r dummy_irq_info_funcs ffffffff82d29018 r hpd_irq_info_funcs ffffffff82d29028 r hpd_rx_irq_info_funcs ffffffff82d29038 r pflip_irq_info_funcs ffffffff82d29048 r vupdate_irq_info_funcs ffffffff82d29058 r vblank_irq_info_funcs -ffffffff82d29070 r irq_source_info_dce80 -ffffffff82d2b000 r irq_service_funcs_dcn10 +ffffffff82d29070 r irq_source_info_dce120 +ffffffff82d2b000 r irq_service_funcs_dce80 ffffffff82d2b008 r dummy_irq_info_funcs ffffffff82d2b018 r hpd_irq_info_funcs ffffffff82d2b028 r hpd_rx_irq_info_funcs ffffffff82d2b038 r pflip_irq_info_funcs -ffffffff82d2b048 r vupdate_no_lock_irq_info_funcs +ffffffff82d2b048 r vupdate_irq_info_funcs ffffffff82d2b058 r vblank_irq_info_funcs -ffffffff82d2b068 r vline0_irq_info_funcs -ffffffff82d2b080 r irq_source_info_dcn10 -ffffffff82d2d000 r irq_service_funcs_dcn20 +ffffffff82d2b070 r irq_source_info_dce80 +ffffffff82d2d000 r irq_service_funcs_dcn10 ffffffff82d2d008 r dummy_irq_info_funcs ffffffff82d2d018 r hpd_irq_info_funcs ffffffff82d2d028 r hpd_rx_irq_info_funcs @@ -47809,8 +47802,8 @@ ffffffff82d2d038 r pflip_irq_info_funcs ffffffff82d2d048 r vupdate_no_lock_irq_info_funcs ffffffff82d2d058 r vblank_irq_info_funcs ffffffff82d2d068 r vline0_irq_info_funcs -ffffffff82d2d080 r irq_source_info_dcn20 -ffffffff82d2f000 r irq_service_funcs_dcn201 +ffffffff82d2d080 r irq_source_info_dcn10 +ffffffff82d2f000 r irq_service_funcs_dcn20 ffffffff82d2f008 r dummy_irq_info_funcs ffffffff82d2f018 r hpd_irq_info_funcs ffffffff82d2f028 r hpd_rx_irq_info_funcs @@ -47818,19 +47811,18 @@ ffffffff82d2f038 r pflip_irq_info_funcs ffffffff82d2f048 r vupdate_no_lock_irq_info_funcs ffffffff82d2f058 r vblank_irq_info_funcs ffffffff82d2f068 r vline0_irq_info_funcs -ffffffff82d2f080 r irq_source_info_dcn201 -ffffffff82d31000 r irq_source_info_dcn21 -ffffffff82d32290 r irq_service_funcs_dcn21 -ffffffff82d32298 r dummy_irq_info_funcs -ffffffff82d322a8 r hpd_irq_info_funcs -ffffffff82d322b8 r hpd_rx_irq_info_funcs -ffffffff82d322c8 r pflip_irq_info_funcs -ffffffff82d322d8 r vupdate_no_lock_irq_info_funcs -ffffffff82d322e8 r vblank_irq_info_funcs -ffffffff82d322f8 r vline0_irq_info_funcs -ffffffff82d32308 r dmub_outbox_irq_info_funcs -ffffffff82d33000 r irq_source_info_dcn30 -ffffffff82d34290 r irq_service_funcs_dcn30 +ffffffff82d2f080 r irq_source_info_dcn20 +ffffffff82d31000 r irq_service_funcs_dcn201 +ffffffff82d31008 r dummy_irq_info_funcs +ffffffff82d31018 r hpd_irq_info_funcs +ffffffff82d31028 r hpd_rx_irq_info_funcs +ffffffff82d31038 r pflip_irq_info_funcs +ffffffff82d31048 r vupdate_no_lock_irq_info_funcs +ffffffff82d31058 r vblank_irq_info_funcs +ffffffff82d31068 r vline0_irq_info_funcs +ffffffff82d31080 r irq_source_info_dcn201 +ffffffff82d33000 r irq_source_info_dcn21 +ffffffff82d34290 r irq_service_funcs_dcn21 ffffffff82d34298 r dummy_irq_info_funcs ffffffff82d342a8 r hpd_irq_info_funcs ffffffff82d342b8 r hpd_rx_irq_info_funcs @@ -47838,9 +47830,9 @@ ffffffff82d342c8 r pflip_irq_info_funcs ffffffff82d342d8 r vupdate_no_lock_irq_info_funcs ffffffff82d342e8 r vblank_irq_info_funcs ffffffff82d342f8 r vline0_irq_info_funcs -ffffffff82d34308 r dmub_trace_irq_info_funcs -ffffffff82d35000 r irq_source_info_dcn302 -ffffffff82d36290 r irq_service_funcs_dcn302 +ffffffff82d34308 r dmub_outbox_irq_info_funcs +ffffffff82d35000 r irq_source_info_dcn30 +ffffffff82d36290 r irq_service_funcs_dcn30 ffffffff82d36298 r dummy_irq_info_funcs ffffffff82d362a8 r hpd_irq_info_funcs ffffffff82d362b8 r hpd_rx_irq_info_funcs @@ -47849,27 +47841,27 @@ ffffffff82d362d8 r vupdate_no_lock_irq_info_funcs ffffffff82d362e8 r vblank_irq_info_funcs ffffffff82d362f8 r vline0_irq_info_funcs ffffffff82d36308 r dmub_trace_irq_info_funcs -ffffffff82d37000 r irq_service_funcs_dcn303 -ffffffff82d37008 r dummy_irq_info_funcs -ffffffff82d37018 r hpd_irq_info_funcs -ffffffff82d37028 r hpd_rx_irq_info_funcs -ffffffff82d37038 r pflip_irq_info_funcs -ffffffff82d37048 r vupdate_no_lock_irq_info_funcs -ffffffff82d37058 r vblank_irq_info_funcs -ffffffff82d37068 r vline0_irq_info_funcs -ffffffff82d37080 r irq_source_info_dcn303 -ffffffff82d39000 r irq_source_info_dcn31 -ffffffff82d3a290 r irq_service_funcs_dcn31 -ffffffff82d3a298 r dummy_irq_info_funcs -ffffffff82d3a2a8 r hpd_irq_info_funcs -ffffffff82d3a2b8 r hpd_rx_irq_info_funcs -ffffffff82d3a2c8 r pflip_irq_info_funcs -ffffffff82d3a2d8 r vupdate_no_lock_irq_info_funcs -ffffffff82d3a2e8 r vblank_irq_info_funcs -ffffffff82d3a2f8 r vline0_irq_info_funcs -ffffffff82d3a308 r outbox_irq_info_funcs -ffffffff82d3b000 r irq_source_info_dcn314 -ffffffff82d3c290 r irq_service_funcs_dcn314 +ffffffff82d37000 r irq_source_info_dcn302 +ffffffff82d38290 r irq_service_funcs_dcn302 +ffffffff82d38298 r dummy_irq_info_funcs +ffffffff82d382a8 r hpd_irq_info_funcs +ffffffff82d382b8 r hpd_rx_irq_info_funcs +ffffffff82d382c8 r pflip_irq_info_funcs +ffffffff82d382d8 r vupdate_no_lock_irq_info_funcs +ffffffff82d382e8 r vblank_irq_info_funcs +ffffffff82d382f8 r vline0_irq_info_funcs +ffffffff82d38308 r dmub_trace_irq_info_funcs +ffffffff82d39000 r irq_service_funcs_dcn303 +ffffffff82d39008 r dummy_irq_info_funcs +ffffffff82d39018 r hpd_irq_info_funcs +ffffffff82d39028 r hpd_rx_irq_info_funcs +ffffffff82d39038 r pflip_irq_info_funcs +ffffffff82d39048 r vupdate_no_lock_irq_info_funcs +ffffffff82d39058 r vblank_irq_info_funcs +ffffffff82d39068 r vline0_irq_info_funcs +ffffffff82d39080 r irq_source_info_dcn303 +ffffffff82d3b000 r irq_source_info_dcn31 +ffffffff82d3c290 r irq_service_funcs_dcn31 ffffffff82d3c298 r dummy_irq_info_funcs ffffffff82d3c2a8 r hpd_irq_info_funcs ffffffff82d3c2b8 r hpd_rx_irq_info_funcs @@ -47878,8 +47870,8 @@ ffffffff82d3c2d8 r vupdate_no_lock_irq_info_funcs ffffffff82d3c2e8 r vblank_irq_info_funcs ffffffff82d3c2f8 r vline0_irq_info_funcs ffffffff82d3c308 r outbox_irq_info_funcs -ffffffff82d3d000 r irq_source_info_dcn315 -ffffffff82d3e290 r irq_service_funcs_dcn315 +ffffffff82d3d000 r irq_source_info_dcn314 +ffffffff82d3e290 r irq_service_funcs_dcn314 ffffffff82d3e298 r dummy_irq_info_funcs ffffffff82d3e2a8 r hpd_irq_info_funcs ffffffff82d3e2b8 r hpd_rx_irq_info_funcs @@ -47888,8 +47880,8 @@ ffffffff82d3e2d8 r vupdate_no_lock_irq_info_funcs ffffffff82d3e2e8 r vblank_irq_info_funcs ffffffff82d3e2f8 r vline0_irq_info_funcs ffffffff82d3e308 r outbox_irq_info_funcs -ffffffff82d3f000 r irq_source_info_dcn32 -ffffffff82d40290 r irq_service_funcs_dcn32 +ffffffff82d3f000 r irq_source_info_dcn315 +ffffffff82d40290 r irq_service_funcs_dcn315 ffffffff82d40298 r dummy_irq_info_funcs ffffffff82d402a8 r hpd_irq_info_funcs ffffffff82d402b8 r hpd_rx_irq_info_funcs @@ -47898,9571 +47890,9582 @@ ffffffff82d402d8 r vupdate_no_lock_irq_info_funcs ffffffff82d402e8 r vblank_irq_info_funcs ffffffff82d402f8 r vline0_irq_info_funcs ffffffff82d40308 r outbox_irq_info_funcs -ffffffff82d42000 r dio_link_hwss -ffffffff82d43000 r dio_fixed_vs_pe_retimer_link_hwss -ffffffff82d44000 r dpia_link_hwss -ffffffff82d45000 r hpo_dp_link_hwss -ffffffff82d46000 r hpo_fixed_vs_pe_retimer_dp_link_hwss -ffffffff82d47000 r DP_SINK_BRANCH_DEV_NAME_7580 -ffffffff82d48000 r DP_VGA_DONGLE_BRANCH_DEV_NAME -ffffffff82d48006 r DP_DVI_CONVERTER_ID_4 -ffffffff82d4800d r DP_DVI_CONVERTER_ID_5 -ffffffff82d49000 r dp_lt_fallbacks -ffffffff82d4d000 r mandatory_dpcd_partitions -ffffffff82d4e000 r DP_VGA_LVDS_CONVERTER_ID_2 -ffffffff82d4e007 r DP_VGA_LVDS_CONVERTER_ID_3 -ffffffff82d4f000 r virtual_lnk_enc_funcs -ffffffff82d50000 r virtual_link_hwss -ffffffff82d51000 r virtual_str_enc_funcs -ffffffff82d52000 R dmub_srv_dcn20_regs -ffffffff82d53000 R dmub_srv_dcn21_regs -ffffffff82d54000 R dmub_srv_dcn30_regs -ffffffff82d55000 R dmub_srv_dcn301_regs -ffffffff82d56000 R dmub_srv_dcn302_regs -ffffffff82d57000 R dmub_srv_dcn303_regs -ffffffff82d58000 R dmub_srv_dcn31_regs -ffffffff82d59000 R dmub_srv_dcn314_regs -ffffffff82d5a000 R dmub_srv_dcn315_regs -ffffffff82d5b000 R dmub_srv_dcn316_regs -ffffffff82d5c000 R dmub_srv_dcn32_regs -ffffffff82d5d000 r numerator01 -ffffffff82d5d020 r numerator02 -ffffffff82d5d040 r numerator04 -ffffffff82d5d060 r numerator05 -ffffffff82d61000 r abm_settings -ffffffff82d61020 r abm_settings_config0 -ffffffff82d61060 r abm_settings_config1 -ffffffff82d610a0 r abm_settings_config2 -ffffffff82d610d8 r min_reduction_table_v_2_2 -ffffffff82d610e5 r max_reduction_table_v_2_2 -ffffffff82d610f2 r min_reduction_table -ffffffff82d610ff r max_reduction_table -ffffffff82d61110 r custom_backlight_curve0 -ffffffff82d62000 R amdgpu_pp_profile_name -ffffffff82d63000 r pp_lib_thermal_controller_names -ffffffff82d64000 r pp_ip_funcs -ffffffff82d640a0 R pp_smu_ip_block -ffffffff82d640b8 r pp_dpm_funcs -ffffffff82d65000 r gpio_tbl -ffffffff82d650f0 r enable_fb_req_rej_tbl -ffffffff82d65140 r use_bclk_tbl -ffffffff82d65310 r turn_off_plls_tbl -ffffffff82d65640 r enter_baco_tbl -ffffffff82d65730 r exit_baco_tbl -ffffffff82d65850 r clean_baco_tbl -ffffffff82d66000 r gpio_tbl -ffffffff82d660f0 r enable_fb_req_rej_tbl -ffffffff82d66140 r use_bclk_tbl -ffffffff82d662e0 r turn_off_plls_tbl -ffffffff82d66370 r clk_req_b_tbl -ffffffff82d66490 r enter_baco_tbl -ffffffff82d665b0 r exit_baco_tbl -ffffffff82d666d0 r clean_baco_tbl +ffffffff82d41000 r irq_source_info_dcn32 +ffffffff82d42290 r irq_service_funcs_dcn32 +ffffffff82d42298 r dummy_irq_info_funcs +ffffffff82d422a8 r hpd_irq_info_funcs +ffffffff82d422b8 r hpd_rx_irq_info_funcs +ffffffff82d422c8 r pflip_irq_info_funcs +ffffffff82d422d8 r vupdate_no_lock_irq_info_funcs +ffffffff82d422e8 r vblank_irq_info_funcs +ffffffff82d422f8 r vline0_irq_info_funcs +ffffffff82d42308 r outbox_irq_info_funcs +ffffffff82d44000 r dio_link_hwss +ffffffff82d45000 r dio_fixed_vs_pe_retimer_link_hwss +ffffffff82d46000 r dpia_link_hwss +ffffffff82d47000 r hpo_dp_link_hwss +ffffffff82d48000 r hpo_fixed_vs_pe_retimer_dp_link_hwss +ffffffff82d49000 r DP_SINK_BRANCH_DEV_NAME_7580 +ffffffff82d4a000 r DP_VGA_DONGLE_BRANCH_DEV_NAME +ffffffff82d4a006 r DP_DVI_CONVERTER_ID_4 +ffffffff82d4a00d r DP_DVI_CONVERTER_ID_5 +ffffffff82d4b000 r dp_lt_fallbacks +ffffffff82d4f000 r mandatory_dpcd_partitions +ffffffff82d50000 r DP_VGA_LVDS_CONVERTER_ID_2 +ffffffff82d50007 r DP_VGA_LVDS_CONVERTER_ID_3 +ffffffff82d51000 r virtual_lnk_enc_funcs +ffffffff82d52000 r virtual_link_hwss +ffffffff82d53000 r virtual_str_enc_funcs +ffffffff82d54000 R dmub_srv_dcn20_regs +ffffffff82d55000 R dmub_srv_dcn21_regs +ffffffff82d56000 R dmub_srv_dcn30_regs +ffffffff82d57000 R dmub_srv_dcn301_regs +ffffffff82d58000 R dmub_srv_dcn302_regs +ffffffff82d59000 R dmub_srv_dcn303_regs +ffffffff82d5a000 R dmub_srv_dcn31_regs +ffffffff82d5b000 R dmub_srv_dcn314_regs +ffffffff82d5c000 R dmub_srv_dcn315_regs +ffffffff82d5d000 R dmub_srv_dcn316_regs +ffffffff82d5e000 R dmub_srv_dcn32_regs +ffffffff82d5f000 r numerator01 +ffffffff82d5f020 r numerator02 +ffffffff82d5f040 r numerator04 +ffffffff82d5f060 r numerator05 +ffffffff82d63000 r abm_settings +ffffffff82d63020 r abm_settings_config0 +ffffffff82d63060 r abm_settings_config1 +ffffffff82d630a0 r abm_settings_config2 +ffffffff82d630d8 r min_reduction_table_v_2_2 +ffffffff82d630e5 r max_reduction_table_v_2_2 +ffffffff82d630f2 r min_reduction_table +ffffffff82d630ff r max_reduction_table +ffffffff82d63110 r custom_backlight_curve0 +ffffffff82d64000 R amdgpu_pp_profile_name +ffffffff82d65000 r pp_lib_thermal_controller_names +ffffffff82d66000 r pp_ip_funcs +ffffffff82d660a0 R pp_smu_ip_block +ffffffff82d660b8 r pp_dpm_funcs ffffffff82d67000 r gpio_tbl ffffffff82d670f0 r enable_fb_req_rej_tbl -ffffffff82d67140 r use_bclk_tbl_vg -ffffffff82d67200 r turn_off_plls_tbl_vg -ffffffff82d67350 r use_bclk_tbl -ffffffff82d67440 r turn_off_plls_tbl -ffffffff82d675f0 r clk_req_b_tbl -ffffffff82d67710 r enter_baco_tbl -ffffffff82d67830 r exit_baco_tbl -ffffffff82d67950 r clean_baco_tbl -ffffffff82d68000 r vega10_fuses_default -ffffffff82d77000 r pp_r600_encode_lanes -ffffffff82d78000 R pptable_v1_0_funcs -ffffffff82d79000 R pptable_funcs -ffffffff82d79020 r soft_dummy_pp_table -ffffffff82d7a000 r smu10_hwmgr_funcs -ffffffff82d7b000 r smu7_hwmgr_funcs -ffffffff82d7b2f8 r smu7_irq_funcs -ffffffff82d7b310 r SMU7ThermalPolicy -ffffffff82d7c000 r GCCACConfig_Polaris10 -ffffffff82d7c1b0 r DIDTConfig_Polaris10 -ffffffff82d7ca50 r GCCACConfig_Polaris11 -ffffffff82d7cc00 r DIDTConfig_Polaris11_Kicker -ffffffff82d7d4a0 r DIDTConfig_Polaris11 -ffffffff82d7dd40 r DIDTConfig_Polaris12 -ffffffff82d7e5e0 r GCCACConfig_VegaM -ffffffff82d7e790 r DIDTConfig_VegaM -ffffffff82d80000 r smu8_hwmgr_funcs -ffffffff82d802f0 r SMU7ThermalPolicy -ffffffff82d81000 r smu9_irq_funcs -ffffffff82d82000 r gpio_tbl_iceland -ffffffff82d82060 r gpio_tbl -ffffffff82d82150 r enable_fb_req_rej_tbl -ffffffff82d821a0 r use_bclk_tbl -ffffffff82d82370 r turn_off_plls_tbl -ffffffff82d82610 r enter_baco_tbl -ffffffff82d82730 r exit_baco_tbl_iceland -ffffffff82d82870 r clean_baco_tbl_iceland -ffffffff82d82890 r exit_baco_tbl -ffffffff82d829b0 r clean_baco_tbl -ffffffff82d83000 r pre_baco_tbl -ffffffff82d83090 r enter_baco_tbl -ffffffff82d832b0 r exit_baco_tbl -ffffffff82d83520 r clean_baco_tbl -ffffffff82d84000 r vega10_hwmgr_funcs -ffffffff82d842f0 r channel_number -ffffffff82d84320 r SMU7ThermalWithDelayPolicy -ffffffff82d85000 r SEDiDtStallCtrlConfig_vega10 -ffffffff82d85110 r SEDiDtStallPatternConfig_vega10 -ffffffff82d852e0 r SEDiDtWeightConfig_Vega10 -ffffffff82d853b0 r SEDiDtCtrl1Config_Vega10 -ffffffff82d85440 r SEDiDtCtrl2Config_Vega10 -ffffffff82d85510 r SEDiDtCtrl3Config_vega10 -ffffffff82d85820 r SEDiDtTuningCtrlConfig_Vega10 -ffffffff82d858b0 r SELCacConfig_Vega10 -ffffffff82d85a40 r SEDiDtCtrl0Config_Vega10 -ffffffff82d85d10 r AvfsPSMInitConfig_vega10 -ffffffff82d85d90 r SEEDCStallPatternConfig_Vega10 -ffffffff82d85ea0 r SEEDCStallDelayConfig_Vega10 -ffffffff82d85f80 r SEEDCCtrlConfig_Vega10 -ffffffff82d86040 r PSMSEEDCStallPatternConfig_Vega10 -ffffffff82d860c0 r PSMSEEDCStallDelayConfig_Vega10 -ffffffff82d861d0 r PSMSEEDCCtrlResetConfig_Vega10 -ffffffff82d86290 r PSMSEEDCCtrlConfig_Vega10 -ffffffff82d86350 r SEEDCForceStallPatternConfig_Vega10 -ffffffff82d863e0 r SEEDCCtrlForceStallConfig_Vega10 -ffffffff82d87000 R vega10_pptable_funcs -ffffffff82d88000 r pre_baco_tbl -ffffffff82d88090 r enter_baco_tbl -ffffffff82d882b0 r exit_baco_tbl -ffffffff82d88520 r clean_baco_tbl -ffffffff82d89000 r vega12_hwmgr_funcs -ffffffff82d892f0 r SMU7ThermalWithDelayPolicy -ffffffff82d89340 r link_width -ffffffff82d8a000 R vega12_pptable_funcs -ffffffff82d8b000 r clean_baco_tbl -ffffffff82d8c000 r vega20_hwmgr_funcs -ffffffff82d8c2f0 r SMU7ThermalWithDelayPolicy -ffffffff82d8c340 r link_width -ffffffff82d8d000 R vega20_pptable_funcs -ffffffff82d8e000 R ci_smu_funcs -ffffffff82d8e0e0 r defaults_hawaii_pro -ffffffff82d8e12c r defaults_hawaii_xt -ffffffff82d8e178 r defaults_saturn_xt -ffffffff82d8e1c4 r defaults_bonaire_xt -ffffffff82d8e210 r ci_program_jump_on_start.data -ffffffff82d8f000 R fiji_smu_funcs -ffffffff82d8f0e0 r avfs_graphics_level -ffffffff82d8f240 r fiji_power_tune_data_set_array -ffffffff82d8f246 r fiji_clock_stretch_amount_conversion -ffffffff82d8f260 r fiji_clock_stretcher_ddt_table -ffffffff82d90000 R iceland_smu_funcs -ffffffff82d900e0 r defaults_icelandxt -ffffffff82d9012c r defaults_icelandpro -ffffffff82d90178 r defaults_iceland -ffffffff82d91000 R polaris10_smu_funcs -ffffffff82d910e0 r avfs_graphics_level_polaris10 -ffffffff82d912a0 r avfs_memory_level_polaris10 -ffffffff82d912c0 r polaris10_power_tune_data_set_array -ffffffff82d91310 r Range_Table -ffffffff82d92000 R smu10_smu_funcs -ffffffff82d93000 r smu7_program_jump_on_start.data -ffffffff82d93010 r pwr_virus_table_pre -ffffffff82d93680 r pwr_virus_table_post -ffffffff82d93f80 r pwr_virus_section1 -ffffffff82d94610 r pwr_virus_section2 -ffffffff82d94660 r pwr_virus_section3 -ffffffff82d9bab0 r pwr_virus_section4 -ffffffff82d9be80 r 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pppoe_cloner -ffffffff831fb030 D pppoediscinq -ffffffff831fb060 D pppoeinq -ffffffff831fc000 D dt_lock -ffffffff831fd000 D dt_prov_profile -ffffffff831fd030 D dt_prov_interval -ffffffff831fe000 D dtps_nsysent -ffffffff831fe008 D dt_prov_syscall -ffffffff831ff000 D dt_prov_static -ffffffff831ff030 D dt_static_sched_dequeue -ffffffff831ff0a0 D dt_static_sched_enqueue -ffffffff831ff110 D dt_static_sched_fork -ffffffff831ff180 D dt_static_sched_off__cpu -ffffffff831ff1f0 D dt_static_sched_on__cpu -ffffffff831ff260 D dt_static_sched_remain__cpu -ffffffff831ff2d0 D dt_static_sched_sleep -ffffffff831ff340 D dt_static_sched_steal -ffffffff831ff3b0 D dt_static_sched_unsleep -ffffffff831ff420 D dt_static_sched_wakeup -ffffffff831ff490 D dt_static_raw_syscalls_sys_enter -ffffffff831ff500 D dt_static_raw_syscalls_sys_exit -ffffffff831ff570 D dt_static_uvm_fault -ffffffff831ff5e0 D dt_static_uvm_map_insert -ffffffff831ff650 D dt_static_uvm_map_remove -ffffffff831ff6c0 D dt_static_uvm_malloc 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dt_static_refcnt_tdb -ffffffff83201000 D db_next_free_breakpoint -ffffffff83201008 D db_breakpoints_inserted -ffffffff83202000 D db_ed_style -ffffffff83203000 D db_examine_format -ffffffff83203078 D db_print_format -ffffffff83204000 D db_history_size -ffffffff83204008 D db_history_curr -ffffffff83204010 D db_history_last -ffffffff83205000 D db_tab_stop_width -ffffffff83205004 D db_max_line -ffffffff83205008 D db_max_width -ffffffff8320500c D db_radix -ffffffff83206000 D db_lastsym -ffffffff83206008 D db_maxoff -ffffffff83207000 D db_vars -ffffffff83207090 D db_evars -ffffffff83208000 D db_watchpoints_inserted -ffffffff83208008 D db_next_free_watchpoint -ffffffff83209000 D db_log -ffffffff8320a000 D audio_cd -ffffffff8320a020 D audio_lock -ffffffff8320b000 D midi_cd -ffffffff8320c000 D rnd_cold -ffffffff8320c004 D rnd_slowextract -ffffffff8320c008 D rnd_timeout -ffffffff8320c050 D rndlock -ffffffff8320c060 D rndreinit_timeout -ffffffff8320c0a8 D rnd_task -ffffffff8320d000 D video_cd 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sched_cost_priority -ffffffff8321b008 D sched_cost_runnable -ffffffff8321b00c D sched_cost_resident -ffffffff8321c000 D intrmap_lock -ffffffff8321d000 D nosuidcoredump -ffffffff8321d008 D sigio_lock -ffffffff8321e000 D smr_lock -ffffffff8321e010 D smr_logintvl -ffffffff8321f000 D startuphook_list -ffffffff83220000 D sysctl_lock -ffffffff83220010 D sysctl_disklock -ffffffff83220020 d openbsd -ffffffff83220024 d arg_max -ffffffff83220028 d posix_version -ffffffff8322002c d ngroups_max -ffffffff83220030 d int_one -ffffffff83220034 d maxpartitions -ffffffff83220038 d raw_part -ffffffff8322003c D allowpowerdown -ffffffff83220040 D hw_power -ffffffff83220044 d byte_order -ffffffff83220048 d page_size -ffffffff83221000 d thrsleep_queue -ffffffff83221010 d thrsleep_lock -ffffffff83222000 D tc_lock -ffffffff83222010 D windup_mtx -ffffffff83222020 d dummy_timecounter -ffffffff83222070 D timecounter -ffffffff83222078 D time_second -ffffffff83222080 d timehands -ffffffff83222088 d th0 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syncer_maxdelay -ffffffff8323b004 D syncdelay -ffffffff8323c000 D dosdirtemplate -ffffffff8323d000 D ntfs_hashlock -ffffffff8323e000 D ntfs_toupper_lock -ffffffff8323f000 D art_table_gc_mtx -ffffffff8323f010 D art_table_gc_task -ffffffff8323f040 D art_node_gc_mtx -ffffffff8323f050 D art_node_gc_task -ffffffff83240000 D bpf_bufsize -ffffffff83240004 D bpf_maxbufsize -ffffffff83240008 D bpf_sysctl_lk -ffffffff83241000 D ifg_head -ffffffff83241010 D if_cloners_lock -ffffffff83241020 D if_input_task_locked -ffffffff83241050 D netlock -ffffffff83241060 D ifnetlist -ffffffff83242000 D ifiq_maxlen_drop -ffffffff83242004 D ifiq_maxlen_return -ffffffff83243000 D etherbroadcastaddr -ffffffff83243006 D ether_ipmulticast_min -ffffffff8324300c D ether_ipmulticast_max -ffffffff83243012 D ether_ip6multicast_min -ffffffff83243018 D ether_ip6multicast_max -ffffffff83244000 D etherip_cloner -ffffffff83244030 D etherip_list -ffffffff83245000 D loop_cloner -ffffffff83246000 D ifmedia_mtx -ffffffff83247000 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icmperrppslim -ffffffff83264008 D icmp_redirtimeout -ffffffff83265000 D ipsendredirects -ffffffff83265004 D ip_defttl -ffffffff83265008 D ip_mtudisc -ffffffff8326500c D ip_mtudisc_timeout -ffffffff83265010 D ipq_mutex -ffffffff83265020 D ip_maxqueue -ffffffff83265028 D ipintrq -ffffffff83265060 d ipsend_task -ffffffff83265090 d ipsendraw_task -ffffffff83266000 D ip_mrtproto -ffffffff83266004 d sin -ffffffff83267000 D rip_sendspace -ffffffff83267008 D rip_recvspace -ffffffff83268000 D tcprexmtthresh -ffffffff83268004 D tcptv_keep_init -ffffffff83268008 D tcp_rst_ppslim -ffffffff8326800c D tcp_ackdrop_ppslim -ffffffff83268010 D tcp_syn_hash_size -ffffffff83268014 D tcp_syn_cache_limit -ffffffff83268018 D tcp_syn_bucket_limit -ffffffff8326801c D tcp_syn_use_limit -ffffffff83268020 D syn_cache_mtx -ffffffff83269000 D tcp_outflags -ffffffff8326a000 D tcp_timer_mtx -ffffffff8326a010 D tcp_mssdflt -ffffffff8326a014 D tcp_rttdflt -ffffffff8326a018 D tcp_do_rfc1323 -ffffffff8326a01c D tcp_do_sack -ffffffff8326a020 D tcp_do_rfc3390 -ffffffff8326a024 D tcp_do_tso -ffffffff8326a028 D tcp_reass_limit -ffffffff8326a02c D tcp_sackhole_limit -ffffffff8326b000 D tcp_backoff -ffffffff8326b034 D tcp_totbackoff -ffffffff8326c000 D tcp_sendspace -ffffffff8326c004 D tcp_recvspace -ffffffff8326c008 D tcp_autorcvbuf_inc -ffffffff8326d000 D udpcksum -ffffffff8326d004 D udp_sendspace -ffffffff8326d008 D udp_recvspace -ffffffff8326e000 D ipsec_flows_mtx -ffffffff8326e010 D ipsec_ids_idle -ffffffff8326e014 D ipsec_ids_next_flow -ffffffff8326e018 D ipsec_policy_head -ffffffff8326e028 D ipsp_ids_gc_timeout -ffffffff8326e070 D tdb_sadb_mtx -ffffffff8326e080 d tdb_hashmask -ffffffff8326f000 D ipo_tdb_mtx -ffffffff8326f010 D ipsec_acquire_mtx -ffffffff8326f020 D ipsec_acquire_head -ffffffff83270000 D ipsec_keep_invalid -ffffffff83270004 D ipsec_require_pfs -ffffffff83270008 D ipsec_soft_timeout -ffffffff8327000c D ipsec_exp_timeout -ffffffff83270010 D ipsec_soft_first_use -ffffffff83270014 D ipsec_exp_first_use -ffffffff83270018 D ipsec_expire_acquire -ffffffff8327001c D esp_enable -ffffffff83270020 D ah_enable -ffffffff83271000 D udpencap_enable -ffffffff83271004 D udpencap_port -ffffffff83272000 D carp_vh_rc -ffffffff83272020 D carp_sc_rc -ffffffff83272040 D carp_opts -ffffffff83272058 D carp_cloner -ffffffff83272088 d carp_send_na.mcast -ffffffff83273000 d PADDING -ffffffff83274000 d PADDING -ffffffff83275000 d weak_keys -ffffffff83276000 D swcr_id -ffffffff83277000 D window_inflate -ffffffff83277004 D window_deflate -ffffffff83278000 D ghash_update -ffffffff83279000 D mpls_defttl -ffffffff83279004 D mpls_mapttl_ip -ffffffff8327a000 D nfskevq_lock -ffffffff8327b000 D nfs_backoff -ffffffff8327b020 D nfs_ptimers -ffffffff8327c000 D desirednfsrvcache -ffffffff8327c010 D nonidempotent -ffffffff8327c070 D nfsv2_repstat -ffffffff8327d000 D nfsv2_type -ffffffff8327d030 D nfsv3_type -ffffffff8327d060 D nv2tov_type -ffffffff8327d080 D nv3tov_type -ffffffff8327d0a0 D nfsv3_procid -ffffffff8327d100 D nfsv2_procid -ffffffff8327d15c d nfsv3err_getattr -ffffffff8327d170 d nfsv3err_setattr -ffffffff8327d190 d nfsv3err_lookup -ffffffff8327d1a4 d nfsv3err_access -ffffffff8327d1b0 d nfsv3err_readlink -ffffffff8327d1d0 d nfsv3err_read -ffffffff8327d1f0 d nfsv3err_write -ffffffff8327d210 d nfsv3err_create -ffffffff8327d230 d nfsv3err_mkdir -ffffffff8327d250 d nfsv3err_symlink -ffffffff8327d270 d nfsv3err_mknod -ffffffff8327d290 d nfsv3err_remove -ffffffff8327d2b0 d nfsv3err_rmdir -ffffffff8327d2d0 d nfsv3err_rename -ffffffff8327d300 d nfsv3err_link -ffffffff8327d330 d nfsv3err_readdir -ffffffff8327d350 d nfsv3err_readdirplus -ffffffff8327d366 d nfsv3err_fsstat -ffffffff8327d372 d nfsv3err_fsinfo -ffffffff8327d37c d nfsv3err_pathconf -ffffffff8327d386 d nfsv3err_commit -ffffffff8327e000 D nfsrv3_procs -ffffffff8327e0b8 D nfs_niothreads -ffffffff8327f000 D fragtbl -ffffffff83280000 D ffs_vtbl -ffffffff83281000 D softdep_typenames -ffffffff83281070 D tickdelay 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dcn314_bw_params -ffffffff833c7000 d dcn315_funcs -ffffffff833c7090 d dcn315_bw_params -ffffffff833c8000 d dcn316_funcs -ffffffff833c8090 d dcn316_bw_params -ffffffff833c9000 d dcn32_funcs -ffffffff833ca000 d dcn10_dpp_cap -ffffffff833cb000 d dcn20_dpp_funcs -ffffffff833cb110 d dcn20_dpp_cap -ffffffff833cc000 d dcn20_hubp_funcs -ffffffff833cd000 d dcn20_opp_funcs -ffffffff833ce000 d dcn20_tg_funcs -ffffffff833cf000 d dcn201_dpp_funcs -ffffffff833cf110 d dcn201_dpp_cap -ffffffff833d0000 d dcn201_hubp_funcs -ffffffff833d1000 d dcn201_opp_funcs -ffffffff833d2000 d dcn201_tg_funcs -ffffffff833d3000 d dcn201_res_pool_funcs -ffffffff833d30f8 d dcn201_ip -ffffffff833d32b0 d dcn201_soc -ffffffff833d5000 d dcn21_hubp_funcs -ffffffff833d6000 d dcn30_afmt_funcs -ffffffff833d7000 d dcn30_dpp_funcs -ffffffff833d7110 d dcn30_dpp_cap -ffffffff833d8000 d dcn30_hubp_funcs -ffffffff833d9000 d dcn30_tg_funcs -ffffffff833da000 d dcn30_vpg_funcs +ffffffff82d67140 r use_bclk_tbl +ffffffff82d67310 r turn_off_plls_tbl +ffffffff82d67640 r enter_baco_tbl +ffffffff82d67730 r exit_baco_tbl +ffffffff82d67850 r clean_baco_tbl +ffffffff82d68000 r gpio_tbl +ffffffff82d680f0 r enable_fb_req_rej_tbl +ffffffff82d68140 r use_bclk_tbl +ffffffff82d682e0 r turn_off_plls_tbl +ffffffff82d68370 r clk_req_b_tbl +ffffffff82d68490 r enter_baco_tbl +ffffffff82d685b0 r exit_baco_tbl +ffffffff82d686d0 r clean_baco_tbl +ffffffff82d69000 r gpio_tbl +ffffffff82d690f0 r enable_fb_req_rej_tbl +ffffffff82d69140 r use_bclk_tbl_vg +ffffffff82d69200 r turn_off_plls_tbl_vg +ffffffff82d69350 r use_bclk_tbl +ffffffff82d69440 r turn_off_plls_tbl +ffffffff82d695f0 r clk_req_b_tbl +ffffffff82d69710 r enter_baco_tbl +ffffffff82d69830 r exit_baco_tbl +ffffffff82d69950 r clean_baco_tbl +ffffffff82d6a000 r vega10_fuses_default +ffffffff82d79000 r pp_r600_encode_lanes +ffffffff82d7a000 R pptable_v1_0_funcs +ffffffff82d7b000 R pptable_funcs +ffffffff82d7b020 r soft_dummy_pp_table +ffffffff82d7c000 r smu10_hwmgr_funcs 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+ffffffff82d88350 r SEEDCForceStallPatternConfig_Vega10 +ffffffff82d883e0 r SEEDCCtrlForceStallConfig_Vega10 +ffffffff82d89000 R vega10_pptable_funcs +ffffffff82d8a000 r pre_baco_tbl +ffffffff82d8a090 r enter_baco_tbl +ffffffff82d8a2b0 r exit_baco_tbl +ffffffff82d8a520 r clean_baco_tbl +ffffffff82d8b000 r vega12_hwmgr_funcs +ffffffff82d8b2f0 r SMU7ThermalWithDelayPolicy +ffffffff82d8b340 r link_width +ffffffff82d8c000 R vega12_pptable_funcs +ffffffff82d8d000 r clean_baco_tbl +ffffffff82d8e000 r vega20_hwmgr_funcs +ffffffff82d8e2f0 r SMU7ThermalWithDelayPolicy +ffffffff82d8e340 r link_width +ffffffff82d8f000 R vega20_pptable_funcs +ffffffff82d90000 R ci_smu_funcs +ffffffff82d900e0 r defaults_hawaii_pro +ffffffff82d9012c r defaults_hawaii_xt +ffffffff82d90178 r defaults_saturn_xt +ffffffff82d901c4 r defaults_bonaire_xt +ffffffff82d90210 r ci_program_jump_on_start.data +ffffffff82d91000 R fiji_smu_funcs +ffffffff82d910e0 r avfs_graphics_level +ffffffff82d91240 r fiji_power_tune_data_set_array +ffffffff82d91246 r fiji_clock_stretch_amount_conversion +ffffffff82d91260 r fiji_clock_stretcher_ddt_table +ffffffff82d92000 R iceland_smu_funcs +ffffffff82d920e0 r defaults_icelandxt +ffffffff82d9212c r defaults_icelandpro +ffffffff82d92178 r defaults_iceland +ffffffff82d93000 R polaris10_smu_funcs +ffffffff82d930e0 r avfs_graphics_level_polaris10 +ffffffff82d932a0 r avfs_memory_level_polaris10 +ffffffff82d932c0 r polaris10_power_tune_data_set_array +ffffffff82d93310 r Range_Table +ffffffff82d94000 R smu10_smu_funcs +ffffffff82d95000 r smu7_program_jump_on_start.data +ffffffff82d95010 r pwr_virus_table_pre +ffffffff82d95680 r pwr_virus_table_post +ffffffff82d95f80 r pwr_virus_section1 +ffffffff82d96610 r pwr_virus_section2 +ffffffff82d96660 r pwr_virus_section3 +ffffffff82d9dab0 r pwr_virus_section4 +ffffffff82d9de80 r pwr_virus_section5 +ffffffff82d9e490 r pwr_virus_section6 +ffffffff82da0000 R smu8_smu_funcs +ffffffff82da1000 R tonga_smu_funcs +ffffffff82da10e0 r tonga_power_tune_data_set_array +ffffffff82da112c r tonga_clock_stretch_amount_conversion +ffffffff82da1140 r tonga_clock_stretcher_ddt_table +ffffffff82da2000 R vega10_smu_funcs +ffffffff82da3000 R vega12_smu_funcs +ffffffff82da4000 R vega20_smu_funcs +ffffffff82da5000 R vegam_smu_funcs +ffffffff82da50e0 r vegam_power_tune_data_set_array +ffffffff82da5130 r Range_Table +ffffffff82da6000 R smu_ip_funcs +ffffffff82da60a0 R smu_v11_0_ip_block +ffffffff82da60b8 R smu_v12_0_ip_block +ffffffff82da60d0 R smu_v13_0_ip_block +ffffffff82da60e8 r swsmu_pm_funcs +ffffffff82da7000 r arcturus_ppt_funcs +ffffffff82da73f0 r arcturus_table_map +ffffffff82da7470 r arcturus_pwr_src_map +ffffffff82da7480 r arcturus_workload_map +ffffffff82da74d0 r smu11_thermal_policy +ffffffff82da7528 r arcturus_i2c_algo +ffffffff82da7538 r arcturus_i2c_control_quirks +ffffffff82da7550 r arcturus_throttler_map +ffffffff82da7570 r arcturus_message_map +ffffffff82da7ff0 r arcturus_clk_map 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aldebaran_i2c_algo +ffffffff82db1598 r aldebaran_i2c_control_quirks +ffffffff82db15b0 r aldebaran_throttler_map +ffffffff82db15d0 r aldebaran_message_map +ffffffff82db2050 r aldebaran_feature_mask_map +ffffffff82db3000 R pmfw_decoded_link_speed +ffffffff82db3020 R pmfw_decoded_link_width +ffffffff82db3040 r smu_v13_0_irq_funcs +ffffffff82db4000 r smu_v13_0_0_ppt_funcs +ffffffff82db43f0 r smu13_thermal_policy +ffffffff82db4448 r smu_v13_0_0_i2c_algo +ffffffff82db4458 r smu_v13_0_0_i2c_control_quirks +ffffffff82db4470 r smu_v13_0_0_throttler_map +ffffffff82db5000 r smu_v13_0_4_ppt_funcs +ffffffff82db6000 r smu_v13_0_5_ppt_funcs +ffffffff82db7000 r smu_v13_0_6_ppt_funcs +ffffffff82db73f0 r smu_v13_0_6_message_map +ffffffff82db7e70 r smu_v13_0_6_clk_map +ffffffff82db7f30 r smu_v13_0_6_table_map +ffffffff82db7fb0 r smu_v13_0_6_i2c_algo +ffffffff82db7fc0 r smu_v13_0_6_i2c_control_quirks +ffffffff82db7fd0 r smu_v13_0_6_irq_funcs +ffffffff82db7fe0 r smu_v13_0_6_throttler_map +ffffffff82db7ff0 r smu_v13_0_6_feature_mask_map +ffffffff82db9000 r smu_v13_0_7_ppt_funcs +ffffffff82db93f0 r smu13_thermal_policy +ffffffff82db9450 r smu_v13_0_7_throttler_map +ffffffff82dba000 r yellow_carp_ppt_funcs +ffffffff82dbb000 R link_speed +ffffffff82dbb020 r __smu_message_names +ffffffff82dbc000 R pchb_ca +ffffffff82dbd000 R amas_ca +ffffffff82dbd028 R amas_devices +ffffffff82dbd040 r amas_feature +ffffffff82dbe000 R cardslot_ca +ffffffff82dbf000 R cardbus_ca +ffffffff82dc0000 R com_cardbus_ca +ffffffff82dc1000 R xl_cardbus_ca +ffffffff82dc1030 R xl_cardbus_products +ffffffff82dc2000 R dc_cardbus_ca +ffffffff82dc2030 R dc_cardbus_devices +ffffffff82dc3000 R fxp_cardbus_ca +ffffffff82dc3028 R fxp_cardbus_devices +ffffffff82dc4000 R rl_cardbus_devices +ffffffff82dc4028 R rl_cardbus_ca +ffffffff82dc5000 R re_cardbus_ca +ffffffff82dc5028 R re_cardbus_devices +ffffffff82dc6000 R ath_cardbus_ca +ffffffff82dc7000 R athn_cardbus_ca +ffffffff82dc7030 r athn_cardbus_devices +ffffffff82dc8000 R atw_cardbus_ca +ffffffff82dc8028 R atw_cardbus_devices +ffffffff82dc9000 R rtw_cardbus_ca +ffffffff82dc9028 R rtw_cardbus_devices +ffffffff82dca000 R ral_cardbus_ca +ffffffff82dca030 r ral_cardbus_devices +ffffffff82dcb000 R acx_cardbus_ca +ffffffff82dcb028 r acx_cardbus_devices +ffffffff82dcc000 R pgt_cardbus_ca +ffffffff82dcc028 R pgt_cardbus_devices +ffffffff82dcd000 R ehci_cardbus_ca +ffffffff82dce000 R ohci_cardbus_ca +ffffffff82dcf000 R uhci_cardbus_ca +ffffffff82dd0000 R malo_cardbus_ca +ffffffff82dd0028 r malo_cardbus_devices +ffffffff82dd1000 R bwi_cardbus_ca +ffffffff82dd1030 r bwi_cardbus_devices +ffffffff82dd2000 R pcmcia_ca +ffffffff82dd3000 r pcmcia_parse_cis_tuple.init_cfe +ffffffff82dd4000 r pcmcia_cis_quirks +ffffffff82dd5000 R ep_pcmcia_ca +ffffffff82dd6000 R ne_pcmcia_ca +ffffffff82dd6030 R ne2000devs +ffffffff82dd8000 R aic_pcmcia_ca +ffffffff82dd9000 R com_pcmcia_ca +ffffffff82dda000 R wdc_pcmcia_ca +ffffffff82ddb000 R sm_pcmcia_ca +ffffffff82ddc000 R xe_pcmcia_ca +ffffffff82ddd000 R wi_pcmcia_ca +ffffffff82ddd030 r wi_pcmcia_products +ffffffff82dde000 R malo_pcmcia_ca +ffffffff82ddf000 R an_pcmcia_ca +ffffffff82de0000 R pcib_ca +ffffffff82de1000 R amdpcib_ca +ffffffff82de1028 R amdpcib_devices +ffffffff82de2000 R tcpcib_ca +ffffffff82de2028 R tcpcib_devices +ffffffff82de3000 R aapic_ca +ffffffff82de4000 R hme_pci_ca +ffffffff82de4028 r hme_promhdr +ffffffff82de402a r hme_promdat +ffffffff82de5000 R isa_ca +ffffffff82de6000 R isadma_ca +ffffffff82de7000 R fdc_ca +ffffffff82de8000 R fd_ca +ffffffff82de9000 R com_isa_ca +ffffffff82dea000 R pckbc_isa_ca +ffffffff82deb000 R vga_isa_ca +ffffffff82dec000 R wdc_isa_ca +ffffffff82ded000 R mpu_midi_hw_if +ffffffff82dee000 R mpu_isa_ca +ffffffff82def000 R pcppi_ca +ffffffff82df0000 R spkr_ca +ffffffff82df0030 r pitchtab +ffffffff82df1000 R lpt_isa_ca +ffffffff82df2000 R wbsio_ca +ffffffff82df3000 R schsio_ca +ffffffff82df4000 R lm_isa_ca +ffffffff82df4028 R lm_wbsio_ca +ffffffff82df5000 R it_sensors +ffffffff82df5110 R it_vrfact +ffffffff82df5140 R it_fan_regs +ffffffff82df5160 R it_fan_ext_regs +ffffffff82df5178 R it_ca +ffffffff82df6000 R abitkv_sensors +ffffffff82df6200 R abitaa_sensors +ffffffff82df6480 R abitav_sensors +ffffffff82df6700 R abitas_sensors +ffffffff82df6980 R abitax_sensors +ffffffff82df6bc0 R abitm4_sensors +ffffffff82df6e80 R abitan_sensors +ffffffff82df7120 R abital_sensors +ffffffff82df73a0 R abitaw_sensors +ffffffff82df7700 R abitni_sensors +ffffffff82df79a0 R abitat_sensors +ffffffff82df7cc0 R abitan2_sensors +ffffffff82df7f60 R abitab_sensors +ffffffff82df8220 R abitan3_sensors +ffffffff82df8500 R abitaw2_sensors +ffffffff82df8860 R abitat2_sensors +ffffffff82df8b60 R abitab2_sensors +ffffffff82df8ea0 R abitin_sensors +ffffffff82df91e0 R uguru_ca +ffffffff82dfa000 R aps_ca +ffffffff82dfb000 R wsdisplay_emul_ca +ffffffff82dfb030 r charClass +ffffffff82dfc000 r usl_syncops +ffffffff82dfd000 R wsevent_filtops +ffffffff82dfe000 R wskbd_ca +ffffffff82dff000 r latin1_to_upper +ffffffff82e00000 R wsmouse_ca +ffffffff82e01000 R cyrillic_to_koi8 +ffffffff82e01060 R unicode_to_latin2 +ffffffff82e010e0 R unicode_to_latin7 +ffffffff82e02000 R wsemul_vt100_ops +ffffffff82e03000 r decspcgr2uni +ffffffff82e03100 r dectech2uni +ffffffff82e03200 r nrctable +ffffffff82e04000 r vt100_fkeys +ffffffff82e040c0 r vt100_pfkeys +ffffffff82e040e0 r vt100_numpad +ffffffff82e05000 R pckbd_ca +ffffffff82e05028 R pckbd_accessops +ffffffff82e05040 R pckbd_consops +ffffffff82e05060 R pckbd_keymapdata +ffffffff82e05070 R pckbd_xtbl2 +ffffffff82e05100 R pckbd_xtbl2_ext +ffffffff82e06000 r pckbd_keydesc_us +ffffffff82e06250 r pckbd_keydesc_de +ffffffff82e062f0 r pckbd_keydesc_de_nodead +ffffffff82e06310 r pckbd_keydesc_fr +ffffffff82e063d0 r pckbd_keydesc_fr_dvorak_bepo +ffffffff82e06510 r pckbd_keydesc_dk +ffffffff82e065a0 r pckbd_keydesc_dk_nodead +ffffffff82e065b0 r pckbd_keydesc_it +ffffffff82e06640 r pckbd_keydesc_uk +ffffffff82e066e0 r pckbd_keydesc_jp +ffffffff82e06750 r pckbd_keydesc_sv +ffffffff82e06780 r pckbd_keydesc_sv_nodead +ffffffff82e06790 r pckbd_keydesc_no +ffffffff82e067c0 r pckbd_keydesc_no_nodead +ffffffff82e067d0 r pckbd_keydesc_us_declk +ffffffff82e06860 r pckbd_keydesc_us_dvorak +ffffffff82e06900 r pckbd_keydesc_us_colemak +ffffffff82e06948 r pckbd_keydesc_swapctrlcaps +ffffffff82e06960 r pckbd_keydesc_iopener +ffffffff82e069b0 r pckbd_keydesc_es +ffffffff82e06a50 r pckbd_keydesc_be +ffffffff82e06b10 r pckbd_keydesc_ru +ffffffff82e06c80 r pckbd_keydesc_ua +ffffffff82e06e10 r pckbd_keydesc_sg +ffffffff82e06ec0 r pckbd_keydesc_sg_nodead +ffffffff82e06ee0 r pckbd_keydesc_sf +ffffffff82e06f00 r pckbd_keydesc_pt +ffffffff82e06f90 r pckbd_keydesc_lt +ffffffff82e07070 r pckbd_keydesc_la +ffffffff82e07100 r pckbd_keydesc_br +ffffffff82e07180 r pckbd_keydesc_tr +ffffffff82e07230 r pckbd_keydesc_tr_nodead +ffffffff82e07250 r pckbd_keydesc_pl +ffffffff82e072b0 r pckbd_keydesc_hu +ffffffff82e073c0 r pckbd_keydesc_si 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ukbd_keydesc_sv_nodead +ffffffff82e2a960 r ukbd_keydesc_no +ffffffff82e2a990 r ukbd_keydesc_no_nodead +ffffffff82e2a9a0 r ukbd_keydesc_us_dvorak +ffffffff82e2aa40 r ukbd_keydesc_us_colemak +ffffffff82e2aa88 r ukbd_keydesc_swapctrlcaps +ffffffff82e2aaa0 r ukbd_keydesc_iopener +ffffffff82e2aaf0 r ukbd_keydesc_es +ffffffff82e2ab90 r ukbd_keydesc_be +ffffffff82e2ac50 r ukbd_keydesc_ru +ffffffff82e2adc0 r ukbd_keydesc_ua +ffffffff82e2af60 r ukbd_keydesc_sg +ffffffff82e2b020 r ukbd_keydesc_sg_nodead +ffffffff82e2b040 r ukbd_keydesc_sf +ffffffff82e2b060 r ukbd_keydesc_pt +ffffffff82e2b0f0 r ukbd_keydesc_pt_apple +ffffffff82e2b110 r ukbd_keydesc_lt +ffffffff82e2b1f0 r ukbd_keydesc_la +ffffffff82e2b290 r ukbd_keydesc_br +ffffffff82e2b320 r ukbd_keydesc_tr +ffffffff82e2b3e0 r ukbd_keydesc_tr_nodead +ffffffff82e2b400 r ukbd_keydesc_pl +ffffffff82e2b460 r ukbd_keydesc_hu +ffffffff82e2b570 r ukbd_keydesc_si +ffffffff82e2b690 r ukbd_keydesc_cf +ffffffff82e2b770 r ukbd_keydesc_cf_nodead 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uscom_methods +ffffffff82e5f040 R uscom_ca +ffffffff82e5f068 r uscom_devs +ffffffff82e60000 R ucrcom_methods +ffffffff82e60040 R ucrcom_ca +ffffffff82e61000 R uxrcom_methods +ffffffff82e61040 R uxrcom_ca +ffffffff82e61068 r uxrcom_devs +ffffffff82e62000 R uipaq_methods +ffffffff82e62040 R uipaq_ca +ffffffff82e62070 r uipaq_devs +ffffffff82e63000 R umsm_methods +ffffffff82e63040 R umsm_ca +ffffffff82e63070 r umsm_devs +ffffffff82e64000 R uchcom_methods +ffffffff82e64040 R uchcom_ca +ffffffff82e64068 r uchcom_devs +ffffffff82e64080 r dividers +ffffffff82e65000 R uticom_methods +ffffffff82e65040 R uticom_ca +ffffffff82e65070 r uticom_devs +ffffffff82e66000 R wi_usb_devs +ffffffff82e660f0 R wi_usb_ca +ffffffff82e67000 R atu_ca +ffffffff82e68000 R ural_ca +ffffffff82e68030 r ural_devs +ffffffff82e680a0 r ural_rf2522_r2 +ffffffff82e680e0 r ural_rf2524_r2 +ffffffff82e68120 r ural_rf2525_hi_r2 +ffffffff82e68160 r ural_rf2525_r2 +ffffffff82e681a0 r ural_rf2525e_r2 +ffffffff82e681e0 r ural_rf2526_hi_r2 +ffffffff82e68220 r ural_rf2526_r2 +ffffffff82e68260 r ural_def_bbp +ffffffff82e682a0 r ural_def_mac +ffffffff82e69000 R rum_ca +ffffffff82e69030 r rum_devs +ffffffff82e69110 r rum_rf5225 +ffffffff82e69460 r rum_rf5226 +ffffffff82e697b0 r rum_def_bbp +ffffffff82e697f0 r rum_def_mac +ffffffff82e6a000 R run_ca +ffffffff82e6a030 r run_devs +ffffffff82e6a430 r rt2860_rf2850 +ffffffff82e6a860 r rt2860_rates +ffffffff82e6a920 r rt5592_freqs_40mhz +ffffffff82e6aa60 r rt5592_freqs_20mhz +ffffffff82e6aba0 r rt5592_2ghz_def_rf +ffffffff82e6abe0 r rt5592_chan_5ghz +ffffffff82e6ae30 r rt5592_def_bbp +ffffffff82e6ae70 r rt5592_bbp_r196 +ffffffff82e6aed0 r rt5390_def_bbp +ffffffff82e6af00 r rt3572_def_rf +ffffffff82e6af40 r rt3070_def_rf +ffffffff82e6af70 r rt3593_def_rf +ffffffff82e6afb0 r rt5592_def_rf +ffffffff82e6afe0 r rt5392_def_rf +ffffffff82e6b060 r rt5390_def_rf +ffffffff82e6b0e0 r rt2870_def_mac +ffffffff82e6c000 R mtw_ca +ffffffff82e6c030 r mtw_devs +ffffffff82e6c070 r rt2860_rates +ffffffff82e6c130 r mt7601_rf_chan +ffffffff82e6c1a0 r mt7601_def_bbp +ffffffff82e6c2d0 r mt7601_rf_bank0 +ffffffff82e6c330 r mt7601_rf_bank4 +ffffffff82e6c3b0 r mt7601_rf_bank5 +ffffffff82e6c430 r mt7601_def_mac +ffffffff82e6d000 R zyd_ca +ffffffff82e6d030 r zyd_devs +ffffffff82e6d1b0 r zyd_rfmd_init.phyini +ffffffff82e6d2e0 r zyd_rfmd_init.rfini +ffffffff82e6d330 r zyd_rfmd_set_channel.rfprog +ffffffff82e6d3a0 r zyd_al2230_init.phyini +ffffffff82e6d480 r zyd_al2230_init.rfini +ffffffff82e6d4e0 r zyd_al2230_init_b.phyini +ffffffff82e6d5d0 r zyd_al2230_init_b.rfini +ffffffff82e6d620 r zyd_al2230_set_channel.rfprog +ffffffff82e6d6d0 r zyd_al7230B_init.phyini_1 +ffffffff82e6d7b0 r zyd_al7230B_init.rfini_1 +ffffffff82e6d7f0 r zyd_al7230B_set_channel.rfprog +ffffffff82e6d860 r zyd_al7230B_set_channel.rfsc +ffffffff82e6d890 r zyd_al2210_init.phyini +ffffffff82e6d8f0 r zyd_al2210_init.rfini +ffffffff82e6d920 r zyd_al2210_set_channel.rfprog +ffffffff82e6d960 r zyd_gct_init.phyini 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rtl8192ce_bb_prog +ffffffff82e71a60 r rtl8192cu_bb_prog +ffffffff82e71a90 r rtl8188eu_bb_regs +ffffffff82e71c10 r rtl8188eu_bb_vals +ffffffff82e71f10 r rtl8188eu_agc_vals +ffffffff82e72110 r rtl8188ftv_bb_regs +ffffffff82e722b0 r rtl8188ftv_bb_vals +ffffffff82e725f0 r rtl8188ftv_agc_vals +ffffffff82e726f0 r rtl8192e_bb_regs +ffffffff82e72890 r rtl8192e_bb_vals +ffffffff82e72bd0 r rtl8192eu_agc_vals +ffffffff82e72dd0 r rtl8192ce_bb_regs +ffffffff82e72f50 r rtl8188ce_bb_vals +ffffffff82e73240 r rtl8188ce_agc_vals +ffffffff82e734c0 r rtl8188ru_bb_regs +ffffffff82e73640 r rtl8188ru_bb_vals +ffffffff82e73940 r rtl8188ru_agc_vals +ffffffff82e73bc0 r rtl8188cu_bb_vals +ffffffff82e73eb0 r rtl8192ce_bb_vals +ffffffff82e741a0 r rtl8192ce_agc_vals +ffffffff82e74420 r rtl8192cu_bb_vals +ffffffff82e75000 R rsu_ca +ffffffff82e75030 r rsu_devs +ffffffff82e750c8 r rsu_devs_noht +ffffffff82e750d0 r rsu_qid2idx_4ep +ffffffff82e750da r rsu_qid2idx_6ep +ffffffff82e750e4 r rsu_qid2idx_11ep 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R andl_ca +ffffffff82e96030 r andl_temp +ffffffff82e97000 R spdmem_iic_ca +ffffffff82e98000 R sdtemp_ca +ffffffff82e99000 R lisa_ca +ffffffff82e9a000 R ihidev_ca +ffffffff82e9b000 R ikbd_consops +ffffffff82e9b020 R ikbd_accessops +ffffffff82e9b038 R ikbd_ca +ffffffff82e9c000 R ims_accessops +ffffffff82e9c018 R ims_ca +ffffffff82e9d000 R imt_accessops +ffffffff82e9d018 R imt_ca +ffffffff82e9e000 R iatp_accessops +ffffffff82e9e018 R iatp_ca +ffffffff82e9e040 r mxt_t19_button_map_devs +ffffffff82e9f000 R ietp_ca +ffffffff82e9f028 R ietp_mouse_access +ffffffff82ea0000 R bgw_ca +ffffffff82ea1000 R icc_ca +ffffffff82ea2000 R gpio_ca +ffffffff82ea3000 r sbtn_pnp +ffffffff82ea4000 R hext +ffffffff82ea6000 R acpitimer_ca +ffffffff82ea7000 R acpiac_ca +ffffffff82ea8000 R acpibat_ca +ffffffff82ea9000 R acpibtn_ca +ffffffff82eaa000 R acpicmos_ca +ffffffff82eab000 R acpicpu_ca +ffffffff82eac000 R acpihpet_ca +ffffffff82ead000 R acpiec_ca +ffffffff82eae000 R acpitz_ca +ffffffff82eaf000 R acpimadt_ca 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unp_rights_mtx +ffffffff83238030 D unp_ino_mtx +ffffffff83238040 D unp_gc_task +ffffffff83238070 D unpst_sendspace +ffffffff83238074 D unpst_recvspace +ffffffff83238078 D unpsq_sendspace +ffffffff8323807c D unpsq_recvspace +ffffffff83238080 D unpdg_sendspace +ffffffff83238084 D unpdg_recvspace +ffffffff83239000 D doingcache +ffffffff8323a000 D maxvfsconf +ffffffff8323a010 d vfsconflist +ffffffff8323b000 D lockf_lock +ffffffff8323b010 D maxlocksperuid +ffffffff8323c000 D iftovt_tab +ffffffff8323c040 D vttoif_tab +ffffffff8323c064 D suid_clear +ffffffff8323c068 D vnode_mtx +ffffffff8323c078 D vfs_stall_lock +ffffffff8323c090 D vtypes +ffffffff8323c0e0 D vtags +ffffffff8323d000 D syncer_maxdelay +ffffffff8323d004 D syncdelay +ffffffff8323e000 D dosdirtemplate +ffffffff8323f000 D ntfs_hashlock +ffffffff83240000 D ntfs_toupper_lock +ffffffff83241000 D art_table_gc_mtx +ffffffff83241010 D art_table_gc_task +ffffffff83241040 D art_node_gc_mtx +ffffffff83241050 D art_node_gc_task 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D bridge_cloner +ffffffff8324f000 d veb_cloner +ffffffff8324f030 d vport_cloner +ffffffff83250000 D vlan_tagh_lk +ffffffff83250010 D vlan_cloner +ffffffff83250040 D svlan_cloner +ffffffff83251000 D pipex_list_mtx +ffffffff83251010 D pipex_prune +ffffffff83251018 D pipexoutq +ffffffff83251050 d SHAPad2 +ffffffff83252000 D rtmap_gc +ffffffff83252018 D rt_rc +ffffffff83253000 D rt_labels +ffffffff83253010 D rtlabel_mtx +ffffffff83254000 D enc_cloner +ffffffff83255000 D gre_cloner +ffffffff83255030 D gre_list +ffffffff83255040 D mgre_cloner +ffffffff83255070 D egre_cloner +ffffffff832550a0 D nvgre_cloner +ffffffff832550d0 D eoip_cloner +ffffffff83256000 D trunk_cloner +ffffffff83257000 d aggr_cloner +ffffffff83258000 d tpmr_cloner +ffffffff83259000 D mpe_cloner +ffffffff8325a000 D mpw_cloner +ffffffff8325b000 D mpip_cloner +ffffffff8325c000 d bpe_cloner +ffffffff8325c030 d bpe_lock +ffffffff8325d000 D vether_cloner +ffffffff8325e000 D pair_cloner +ffffffff8325f000 d vxlan_cloner +ffffffff8325f030 d vxlan_lock +ffffffff8325f040 d vxlan_teps +ffffffff83260000 D underload_interval +ffffffff83260010 D wg_cloner +ffffffff83261000 d stoeplitz_keyseed +ffffffff83262000 D ieee80211_cache_size +ffffffff83263000 D arpt_prune +ffffffff83263004 D arpt_keep +ffffffff83263008 D arpt_down +ffffffff83263010 D arpinq +ffffffff83263048 D arp_mtx +ffffffff83263058 D arp_maxtries +ffffffff83264000 D ipport_firstauto +ffffffff83264004 D ipport_lastauto +ffffffff83264008 D ipport_hifirstauto +ffffffff8326400c D ipport_hilastauto +ffffffff83265000 D divert_sendspace +ffffffff83265004 D divert_recvspace +ffffffff83265008 D divbhashsize +ffffffff83266000 D icmptstamprepl +ffffffff83266004 D icmperrppslim +ffffffff83266008 D icmp_redirtimeout +ffffffff83267000 D ipsendredirects +ffffffff83267004 D ip_defttl +ffffffff83267008 D ip_mtudisc +ffffffff8326700c D ip_mtudisc_timeout +ffffffff83267010 D ipq_mutex +ffffffff83267020 D ip_maxqueue +ffffffff83267028 D ipintrq +ffffffff83267060 d ipsend_task +ffffffff83267090 d ipsendraw_task +ffffffff83268000 D ip_mrtproto +ffffffff83268004 d sin +ffffffff83269000 D rip_sendspace +ffffffff83269008 D rip_recvspace +ffffffff8326a000 D tcprexmtthresh +ffffffff8326a004 D tcptv_keep_init +ffffffff8326a008 D tcp_rst_ppslim +ffffffff8326a00c D tcp_ackdrop_ppslim +ffffffff8326a010 D tcp_syn_hash_size +ffffffff8326a014 D tcp_syn_cache_limit +ffffffff8326a018 D tcp_syn_bucket_limit +ffffffff8326a01c D tcp_syn_use_limit +ffffffff8326a020 D syn_cache_mtx +ffffffff8326b000 D tcp_outflags +ffffffff8326c000 D tcp_timer_mtx +ffffffff8326c010 D tcp_mssdflt +ffffffff8326c014 D tcp_rttdflt +ffffffff8326c018 D tcp_do_rfc1323 +ffffffff8326c01c D tcp_do_sack +ffffffff8326c020 D tcp_do_rfc3390 +ffffffff8326c024 D tcp_do_tso +ffffffff8326c028 D tcp_reass_limit +ffffffff8326c02c D tcp_sackhole_limit +ffffffff8326d000 D tcp_backoff +ffffffff8326d034 D tcp_totbackoff +ffffffff8326e000 D tcp_sendspace +ffffffff8326e004 D tcp_recvspace +ffffffff8326e008 D tcp_autorcvbuf_inc +ffffffff8326f000 D udpcksum +ffffffff8326f004 D udp_sendspace +ffffffff8326f008 D udp_recvspace +ffffffff83270000 D ipsec_flows_mtx +ffffffff83270010 D ipsec_ids_idle +ffffffff83270014 D ipsec_ids_next_flow +ffffffff83270018 D ipsec_policy_head +ffffffff83270028 D ipsp_ids_gc_timeout +ffffffff83270070 D tdb_sadb_mtx +ffffffff83270080 d tdb_hashmask +ffffffff83271000 D ipo_tdb_mtx +ffffffff83271010 D ipsec_acquire_mtx +ffffffff83271020 D ipsec_acquire_head +ffffffff83272000 D ipsec_keep_invalid +ffffffff83272004 D ipsec_require_pfs +ffffffff83272008 D ipsec_soft_timeout +ffffffff8327200c D ipsec_exp_timeout +ffffffff83272010 D ipsec_soft_first_use +ffffffff83272014 D ipsec_exp_first_use +ffffffff83272018 D ipsec_expire_acquire +ffffffff8327201c D esp_enable +ffffffff83272020 D ah_enable +ffffffff83273000 D udpencap_enable +ffffffff83273004 D udpencap_port +ffffffff83274000 D carp_vh_rc +ffffffff83274020 D carp_sc_rc +ffffffff83274040 D carp_opts +ffffffff83274058 D carp_cloner +ffffffff83274088 d carp_send_na.mcast +ffffffff83275000 d PADDING +ffffffff83276000 d PADDING +ffffffff83277000 d weak_keys +ffffffff83278000 D swcr_id +ffffffff83279000 D window_inflate +ffffffff83279004 D window_deflate +ffffffff8327a000 D ghash_update +ffffffff8327b000 D mpls_defttl +ffffffff8327b004 D mpls_mapttl_ip +ffffffff8327c000 D nfskevq_lock +ffffffff8327d000 D nfs_backoff +ffffffff8327d020 D nfs_ptimers +ffffffff8327e000 D desirednfsrvcache +ffffffff8327e010 D nonidempotent +ffffffff8327e070 D nfsv2_repstat +ffffffff8327f000 D nfsv2_type +ffffffff8327f030 D nfsv3_type +ffffffff8327f060 D nv2tov_type +ffffffff8327f080 D nv3tov_type +ffffffff8327f0a0 D nfsv3_procid +ffffffff8327f100 D nfsv2_procid +ffffffff8327f15c d nfsv3err_getattr +ffffffff8327f170 d nfsv3err_setattr +ffffffff8327f190 d nfsv3err_lookup +ffffffff8327f1a4 d nfsv3err_access +ffffffff8327f1b0 d nfsv3err_readlink +ffffffff8327f1d0 d nfsv3err_read +ffffffff8327f1f0 d nfsv3err_write +ffffffff8327f210 d nfsv3err_create +ffffffff8327f230 d nfsv3err_mkdir +ffffffff8327f250 d nfsv3err_symlink +ffffffff8327f270 d nfsv3err_mknod +ffffffff8327f290 d nfsv3err_remove +ffffffff8327f2b0 d nfsv3err_rmdir +ffffffff8327f2d0 d nfsv3err_rename +ffffffff8327f300 d nfsv3err_link +ffffffff8327f330 d nfsv3err_readdir +ffffffff8327f350 d nfsv3err_readdirplus +ffffffff8327f366 d nfsv3err_fsstat +ffffffff8327f372 d nfsv3err_fsinfo +ffffffff8327f37c d nfsv3err_pathconf +ffffffff8327f386 d nfsv3err_commit +ffffffff83280000 D nfsrv3_procs +ffffffff832800b8 D nfs_niothreads +ffffffff83281000 D fragtbl +ffffffff83282000 D ffs_vtbl +ffffffff83283000 D softdep_typenames +ffffffff83283070 D tickdelay +ffffffff83284000 D dirchk +ffffffff83285000 D desireddquot +ffffffff83286000 D amap_list_lock +ffffffff83287000 d uao_list_lock +ffffffff83288000 d uvmexp_countersboot_boot_cpumem +ffffffff832880c0 D uvmexp_counters +ffffffff832880c8 D vm_min_kernel_address +ffffffff83289000 D no_constraint +ffffffff8328a000 d uvm_kmapent_warn_rate +ffffffff8328b000 D maxslp +ffffffff8328c000 D uvmpagerops +ffffffff8328d000 D uvm_swap_data_lock +ffffffff8328d010 D swap_syscall_lock +ffffffff8328d020 D oommtx +ffffffff8328e000 D uvm_doswapencrypt +ffffffff8328f000 D gif_list +ffffffff8328f010 D gif_cloner +ffffffff83290000 d sec_cloner +ffffffff83290030 d sec_tdb_gc_mtx +ffffffff83290040 d sec_tdb_gc_task +ffffffff83291000 D divert6_sendspace +ffffffff83291004 D divert6_recvspace +ffffffff83291008 D divb6hashsize +ffffffff83292000 d in6_get_hw_ifid.allone +ffffffff83293000 D ip6_sendredirects +ffffffff83293004 D ip6_defhlim +ffffffff83293008 D ip6_defmcasthlim +ffffffff8329300c D ip6_maxfragpackets +ffffffff83293010 D ip6_maxfrags +ffffffff83293014 D ip6_log_interval +ffffffff83293018 D ip6_hdrnestlimit +ffffffff8329301c D ip6_dad_count +ffffffff83293020 D ip6_auto_flowlabel +ffffffff83293024 D ip6_use_deprecated +ffffffff83293028 D ip6_neighborgcthresh +ffffffff8329302c D ip6_maxdynroutes +ffffffff83293030 D rip6_sendspace +ffffffff83293038 D rip6_recvspace +ffffffff83293040 D icmp6_redirtimeout +ffffffff83293044 D icmp6errppslim +ffffffff83293048 D ip6_mtudisc_timeout +ffffffff83294000 D frag6_mutex +ffffffff83295000 d icmp6_mtudisc_hiwat +ffffffff83295004 d icmp6_mtudisc_lowat +ffffffff83296000 d randomtab_20 +ffffffff83297000 D ip6intrq +ffffffff83297038 d ip6send_task +ffffffff83298000 D nd6_timer_next +ffffffff83298008 D nd6_expire_next +ffffffff83298010 D nd6_delay +ffffffff83298014 D nd6_umaxtries +ffffffff83298018 D nd6_mmaxtries +ffffffff8329801c D nd6_gctimer +ffffffff83298020 D nd6_maxndopt +ffffffff83298028 D nd6_mtx +ffffffff83298038 D nd6_list +ffffffff83299000 d dadq +ffffffff8329a000 D pfkeyv2_mtx +ffffffff8329a010 d pfkeyv2_seq +ffffffff8329b000 D sadb_exts_allowed_in +ffffffff8329b090 D sadb_exts_required_in +ffffffff8329c000 D cold +ffffffff8329d000 D bdevsw +ffffffff8329d460 D nblkdev +ffffffff8329d470 D cdevsw +ffffffff8329f400 D nchrdev +ffffffff8329f404 D mem_no +ffffffff8329f408 D swapdev +ffffffff8329f410 D constab +ffffffff832a0000 D machine +ffffffff832a0008 D cpu_idle_cycle_fcn +ffffffff832a0010 D lid_action +ffffffff832a0014 D pwr_action +ffffffff832a0018 D isa_constraint +ffffffff832a0028 D dma_constraint +ffffffff832a0040 D uvm_md_constraints +ffffffff832a0058 D delay_func +ffffffff832a0060 D initclock_func +ffffffff832a0068 D startclock_func +ffffffff832a0070 D bootinfo_size +ffffffff832a0074 D waittime +ffffffff832a0078 D dumpmag +ffffffff832a1000 D tsc_rdtsc +ffffffff832a1008 D tsc_timecounter +ffffffff832a1058 D tsc_is_synchronized +ffffffff832a2000 D local_apic +ffffffff832a2020 D lapic_id +ffffffff832a2080 D lapic_tpr +ffffffff832a20a0 d lapic_ppr +ffffffff832a2100 d lapic_isr +ffffffff832a3000 D warn_once +ffffffff832a4000 d errata +ffffffff832a5000 D cpu_ucode_mtx +ffffffff832a6000 D mem_owner_bios +ffffffff832a6008 D mrops +ffffffff832a6028 D mtrrmask +ffffffff832a6030 D mtrrtomrt +ffffffff832a7000 D pmap_pg_wc +ffffffff832a7008 D pmaps_lock +ffffffff832a7018 d pmap_maxkvaddr +ffffffff832a8000 D kv_physwait +ffffffff832a9000 D fpu_save_len +ffffffff832aa000 D i8259_pic +ffffffff832ab000 D softintr_pic +ffffffff832ac000 D ipifunc +ffffffff832ad000 D setperf_mp_mutex +ffffffff832ae000 D db_Grp6 +ffffffff832ae040 D db_Grp7 +ffffffff832ae100 D db_Grp8 +ffffffff832ae140 D db_Grp9 +ffffffff832ae200 D db_GrpA +ffffffff832ae240 D db_GrpB +ffffffff832ae280 D db_GrpC +ffffffff832ae2c0 D db_inst_0f0x +ffffffff832ae440 D db_inst_0f2x +ffffffff832ae5c0 D db_inst_0f3x +ffffffff832ae740 D db_inst_0f8x +ffffffff832ae8c0 D db_inst_0f9x +ffffffff832aea40 D db_inst_0fax +ffffffff832aebc0 D db_inst_0fbx +ffffffff832aed40 D db_inst_0fcx +ffffffff832aeec0 D db_inst_0f +ffffffff832aef40 D db_Esc92 +ffffffff832aef80 D db_Esc94 +ffffffff832aefc0 D db_Esc95 +ffffffff832af000 D db_Esc96 +ffffffff832af040 D db_Esc97 +ffffffff832af080 D db_Esca5 +ffffffff832af0c0 D db_Escb4 +ffffffff832af100 D db_Esce3 +ffffffff832af140 D db_Escf4 +ffffffff832af180 D db_Esc8 +ffffffff832af240 D db_Esc9 +ffffffff832af300 D db_Esca +ffffffff832af3c0 D db_Escb +ffffffff832af480 D db_Escc +ffffffff832af540 D db_Escd +ffffffff832af600 D db_Esce +ffffffff832af6c0 D db_Escf +ffffffff832af780 D db_Esc_inst +ffffffff832af7c0 D db_Grp1 +ffffffff832af800 D db_Grp2 +ffffffff832af840 D db_Grp3 +ffffffff832af900 D db_Grp4 +ffffffff832af9c0 D db_Grp5 +ffffffff832afa80 D db_inst_table +ffffffff832b1280 D db_bad_inst +ffffffff832b12a0 D db_index_reg_16 +ffffffff832b12e0 D db_reg +ffffffff832b14e0 D db_seg_reg +ffffffff832b1520 D db_lengths +ffffffff832b2000 D db_regs +ffffffff832b21e0 D db_eregs +ffffffff832b21f0 D db_reg_args +ffffffff832b3000 D timer_mutex +ffffffff832b3010 d i8254_timecounter +ffffffff832b4000 D spleen8x16 +ffffffff832b4058 D spleen12x24 +ffffffff832b40b0 D spleen16x32 +ffffffff832b4108 D spleen32x64 +ffffffff832b4160 d builtin_fonts +ffffffff832b41e0 d wsfont_add.cookiegen +ffffffff832b41f0 d spleen8x16_data +ffffffff832b4ff0 d spleen12x24_data +ffffffff832b79f0 d spleen16x32_data +ffffffff832bb1f0 d spleen32x64_data +ffffffff832ca000 D nsphy_cd +ffffffff832cb000 D nsphyter_cd +ffffffff832cc000 D gentbi_cd +ffffffff832cd000 D qsphy_cd +ffffffff832ce000 D inphy_cd +ffffffff832cf000 D iophy_cd +ffffffff832d0000 D eephy_cd +ffffffff832d1000 D exphy_cd +ffffffff832d2000 D rlphy_cd +ffffffff832d3000 D lxtphy_cd +ffffffff832d4000 D luphy_cd +ffffffff832d5000 D mtdphy_cd +ffffffff832d6000 D icsphy_cd +ffffffff832d7000 D sqphy_cd +ffffffff832d8000 D tqphy_cd +ffffffff832d9000 D ukphy_cd +ffffffff832da000 D dcphy_cd +ffffffff832db000 D bmtphy_cd +ffffffff832dc000 D brgphy_cd +ffffffff832dd000 D xmphy_cd +ffffffff832de000 D amphy_cd +ffffffff832df000 D acphy_cd +ffffffff832e0000 D nsgphy_cd +ffffffff832e1000 D urlphy_cd +ffffffff832e2000 D rgephy_cd +ffffffff832e3000 D ciphy_cd +ffffffff832e4000 D ipgphy_cd +ffffffff832e5000 D etphy_cd +ffffffff832e6000 D jmphy_cd +ffffffff832e7000 D atphy_cd +ffffffff832e8000 D scsi_autoconf +ffffffff832e8008 D scsibus_cd +ffffffff832e9000 D cd_cd +ffffffff832ea000 D ch_cd +ffffffff832ea020 D chquirks +ffffffff832eb000 D sd_cd +ffffffff832ec000 D st_cd +ffffffff832ed000 D uk_cd +ffffffff832ee000 D safte_cd +ffffffff832ef000 D ses_cd +ffffffff832f0000 D sym_cd +ffffffff832f0020 D sym_devices +ffffffff832f0070 D asym_devices +ffffffff832f1000 D rdac_cd +ffffffff832f1020 D rdac_devices +ffffffff832f2000 D emc_cd +ffffffff832f2020 D emc_devices +ffffffff832f3000 D hds_cd +ffffffff832f3020 D hds_devices +ffffffff832f4000 D atapiscsi_cd +ffffffff832f5000 D wd_cd +ffffffff832f5020 d wddumpmulti +ffffffff832f6000 D mainbus_cd +ffffffff832f6020 D mba_iba +ffffffff832f7000 D bios_cd +ffffffff832f7020 D smbios_uninfo +ffffffff832f8000 D mpbios_cd +ffffffff832f8020 d mp_conf +ffffffff832f8070 d extint_bus +ffffffff832f80a0 d smi_bus +ffffffff832f80d0 d nmi_bus +ffffffff832f9000 D cpu_info_full_primary +ffffffff832fc000 D cpu_info_list +ffffffff832fc008 D mp_cpu_funcs +ffffffff832fc020 D cpu_cd +ffffffff832fc040 D cpu_info +ffffffff832fd000 D local_pic +ffffffff832fd098 D lapic_readreg +ffffffff832fd0a0 D lapic_writereg +ffffffff832fd0a8 D x86_ipi +ffffffff832fe000 D ioapic_cold +ffffffff832fe008 D ioapic_cd +ffffffff832ff000 D efifb_std_descr +ffffffff832ff030 D efifb_descrs +ffffffff832ff038 D efifb_accessops +ffffffff832ff098 D efifb_cd +ffffffff83300000 D pvbus_cd +ffffffff83300020 D pvbus_types +ffffffff833000e0 D pvbus_dma_tag +ffffffff83301000 D pvclock_cd +ffffffff83301020 D pvclock_timecounter +ffffffff83302000 D vmt_tclo_rpc +ffffffff833020d0 D vmt_cd +ffffffff83303000 D xen_cd +ffffffff83303020 D xen_bus_dma_tag +ffffffff83304000 D xnf_cd +ffffffff83305000 D xbf_cd +ffffffff83306000 D hv_msg_dispatch +ffffffff83306110 D hv_timecounter +ffffffff83306160 D hyperv_cd +ffffffff83307000 d hv_ic_devs +ffffffff83308000 D hvn_cd +ffffffff83309000 D hvs_cd +ffffffff8330a000 D virtio_cd +ffffffff8330b000 D vio_cd +ffffffff8330c000 D vioblk_cd +ffffffff8330d000 D viomb_cd +ffffffff8330e000 D viornd_cd +ffffffff8330f000 D vioscsi_cd +ffffffff83310000 D vmmci_cd +ffffffff83311000 D pci_cd +ffffffff83312000 D arc_fw_hdr +ffffffff83312008 D arc_cd +ffffffff83313000 D jmb_cd +ffffffff83314000 D mfii_cd +ffffffff83315000 D ips_cd +ffffffff83316000 D eap_cd +ffffffff83317000 D auacer_cd +ffffffff83318000 D auich_cd +ffffffff83319000 D azalia_cd +ffffffff8331a000 D envy_cd +ffffffff8331a020 D envy_matchids +ffffffff8331a030 D envy_rates +ffffffff8331a0b0 D ak4524_dac +ffffffff8331a0d8 D ak4524_adc +ffffffff8331a100 D ak4358_dac +ffffffff8331a128 D ak5365_adc +ffffffff8331a150 D unkenvy_codec +ffffffff8331a180 D envy_cards +ffffffff8331a3f0 D envy_cards_ht +ffffffff8331a600 d julia_eeprom +ffffffff8331b000 D emu_cd +ffffffff8331c000 D auixp_cd +ffffffff8331d000 D clcs_cd +ffffffff8331e000 D yds_cd +ffffffff8331f000 D auvia_cd +ffffffff83320000 D qle_cd +ffffffff83321000 D mpii_cd +ffffffff83322000 D aq_cd +ffffffff83323000 D de_cd +ffffffff83324000 D pcn_cd +ffffffff83325000 D wdc_sii3114_vtbl +ffffffff83325038 D wdc_pdc203xx_vtbl +ffffffff83325070 D wdc_svwsata_vtbl +ffffffff833250a8 D pciide_cd +ffffffff833250d0 d sis_hostbr_type +ffffffff83326000 D ppb_cd +ffffffff83327000 D vr_cd +ffffffff83327020 D vr_devices +ffffffff83328000 D txp_cd +ffffffff83329000 D bt848_card_signature +ffffffff8332a000 D bktr_cd +ffffffff8332b000 D em_cd +ffffffff8332c000 D ixgb_cd +ffffffff8332d000 D ix_cd +ffffffff8332d020 D ixgbe_smart_speed +ffffffff8332d024 D ixgbe_enable_msix +ffffffff8332e000 D ixl_cd +ffffffff8332e020 d ixl_sff_lock +ffffffff8332f000 D xge_cd +ffffffff83330000 D thtc_cd +ffffffff83330020 D tht_cd +ffffffff83330040 D tht_txt_desc +ffffffff83330068 D tht_rxf_desc +ffffffff83330090 D tht_rxd_desc +ffffffff833300b8 D tht_txf_desc +ffffffff83331000 D myx_cd +ffffffff83332000 D oce_cd +ffffffff83333000 D dc_devs +ffffffff83334000 D cas_cd +ffffffff83335000 D sis_cd +ffffffff83336000 D se_cd +ffffffff83337000 D mbg_cd +ffffffff83338000 D cbb_cd +ffffffff83338020 D yc_chipsets +ffffffff833381b0 d pccbb_funcs +ffffffff833381e0 d pccbb_pcmcia_funcs +ffffffff83339000 D skc_cd +ffffffff83339020 D sk_cd +ffffffff8333a000 D mskc_cd +ffffffff8333a020 D msk_cd +ffffffff8333b000 D puc_cd +ffffffff8333c000 D puc_ndevs +ffffffff8333d000 D iwi_cd +ffffffff8333e000 D wpi_cd +ffffffff8333f000 D iwn_cd +ffffffff83340000 D iwm_cd +ffffffff83341000 D iwx_cd +ffffffff83342000 D cmpci_cd +ffffffff83343000 D iha_cd +ffffffff83344000 D pcscp_cd +ffffffff83344020 D pcscp_glue +ffffffff83345000 D bge_cd +ffffffff83346000 D bnx_firmwares +ffffffff83346160 D bnx_rv2ps +ffffffff833461c0 D bnx_cd +ffffffff833461e0 d flash_5709 +ffffffff83346210 d flash_table +ffffffff83347000 D vge_cd +ffffffff83348000 D stge_cd +ffffffff83349000 D nfe_cd +ffffffff8334a000 D et_cd +ffffffff8334b000 D jme_cd +ffffffff8334c000 D age_cd +ffffffff8334d000 D alc_dma_burst +ffffffff8334d020 D alc_cd +ffffffff8334e000 D ale_cd +ffffffff8334f000 D amdpm_cd +ffffffff8334f020 d amdpm_timecounter +ffffffff83350000 D bce_cd +ffffffff83351000 D rtwn_cd +ffffffff83352000 d ral_rt2560_opns +ffffffff83352028 d ral_rt2661_opns +ffffffff83352050 d ral_rt2860_opns +ffffffff83353000 D piixpm_cd +ffffffff83354000 D vic_cd +ffffffff83355000 D vmx_cd +ffffffff83356000 D vmwpvs_cd +ffffffff83357000 D lii_cd +ffffffff83358000 D ichiic_cd +ffffffff83359000 D viapm_cd +ffffffff83359020 d viapm_timecounter +ffffffff8335a000 D amdiic_cd +ffffffff8335b000 D nviic_cd +ffffffff8335c000 D kate_cd +ffffffff8335d000 D km_cd +ffffffff8335e000 D cpu_model_offsets +ffffffff8335e070 D ksmn_cd +ffffffff8335f000 D itherm_cd +ffffffff83360000 D pchtemp_cd +ffffffff83361000 D xspd_cd +ffffffff83362000 D virtio_pci_ops +ffffffff83363000 D bwfm_pci_buscore_ops +ffffffff83363030 D bwfm_pci_bus_ops +ffffffff83363058 D bwfm_pci_msgbuf_ops +ffffffff83364000 D bnxt_cd +ffffffff83365000 D mcx_cd +ffffffff83366000 D iavf_cd +ffffffff83367000 D rge_cd +ffffffff83368000 D igc_cd +ffffffff83369000 D ngbe_cd +ffffffff8336a000 D agp_cd +ffffffff8336b000 D intagp_cd +ffffffff8336b020 D agp_i810_methods +ffffffff8336c000 D reservation_ww_class +ffffffff8336d000 d bridge_lock +ffffffff8336d010 d bridge_list +ffffffff8336e000 d drm_connector_enum_list +ffffffff8336e1f8 d connector_list_lock +ffffffff8336e208 d connector_list +ffffffff8336f000 d kernel_fb_helper_list +ffffffff8336f010 d kernel_fb_helper_lock +ffffffff83370000 D drm_global_mutex +ffffffff83371000 D i2c_bit_algo +ffffffff83371010 d drm_fence_context_count +ffffffff83371018 d dma_fence_stub_mtx +ffffffff83371028 D wait_bit_mtx +ffffffff83371038 D shrinkers +ffffffff83372000 d crtc_ww_class +ffffffff83373000 d panel_lock +ffffffff83373010 d panel_list +ffffffff83374000 d ttm_global_mutex +ffffffff83375000 D drm_sched_policy +ffffffff83376000 D intel_bbops +ffffffff83377000 d i915_sys_placement +ffffffff83377020 d i915_ttm_bo_driver +ffffffff83378000 d mchdev_lock +ffffffff83379000 D inteldrm_stdscreen +ffffffff83379030 D inteldrm_scrlist +ffffffff83379038 D inteldrm_screenlist +ffffffff83379048 D inteldrm_accessops +ffffffff833790a8 D inteldrm_cd +ffffffff8337a000 d capture_mutex +ffffffff8337b000 d mitigations +ffffffff8337c000 D i915_modparams +ffffffff8337d000 d schedule_lock +ffffffff8337e000 d unbind_fence_ops +ffffffff8337f000 D intel_graphics_stolen_res +ffffffff83380000 D btc_valid_sclk +ffffffff83381000 d evergreen_cs_packet_parse_vline.vline_start_end +ffffffff83381020 d evergreen_cs_packet_parse_vline.vline_status +ffffffff83382000 d r600_cs_packet_parse_vline.vline_start_end +ffffffff83382008 d r600_cs_packet_parse_vline.vline_status +ffffffff83383000 d r100_asic +ffffffff833832e0 d r200_asic +ffffffff833835c0 d r300_asic_pcie +ffffffff833838a0 d r300_asic +ffffffff83383b80 d r420_asic +ffffffff83383e60 d rs400_asic +ffffffff83384140 d rs600_asic +ffffffff83384420 d rs690_asic +ffffffff83384700 d rv515_asic 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radeon_pcie_gen2 +ffffffff8338801c D radeon_msi +ffffffff83388020 D radeon_lockup_timeout +ffffffff83388024 D radeon_dpm +ffffffff83388028 D radeon_aspm +ffffffff8338802c D radeon_runtime_pm +ffffffff83388030 D radeon_vm_size +ffffffff83388034 D radeon_vm_block_size +ffffffff83388038 D radeon_use_pflipirq +ffffffff8338803c D radeon_bapm +ffffffff83388040 D radeon_backlight +ffffffff83388044 D radeon_auxch +ffffffff83388048 D radeon_uvd +ffffffff8338804c D radeon_vce +ffffffff83388050 D radeon_si_support +ffffffff83388054 D radeon_cik_support +ffffffff83388058 D radeondrm_cd +ffffffff83388078 D radeondrm_stdscreen +ffffffff833880a8 D radeondrm_scrlist +ffffffff833880b0 D radeondrm_screenlist +ffffffff833880c0 D radeondrm_accessops +ffffffff83389000 D radeon_bbops +ffffffff8338a000 d radeon_bo_driver +ffffffff8338b000 d verde_pg_init +ffffffff8338c000 d cac_weights_pitcairn +ffffffff8338c4d0 d cac_weights_oland +ffffffff8338d000 d aldebaran_mode2_handler +ffffffff8338e000 d amdgpu_vbios_version_attrs +ffffffff8338f000 D amdgpu_asic_name +ffffffff83390000 D amdgpu_vram_limit +ffffffff83390004 D amdgpu_gart_size +ffffffff83390008 D amdgpu_gtt_size +ffffffff8339000c D amdgpu_moverate +ffffffff83390010 D amdgpu_audio +ffffffff83390014 D amdgpu_pcie_gen2 +ffffffff83390018 D amdgpu_msi +ffffffff8339001c D amdgpu_dpm +ffffffff83390020 D amdgpu_fw_load_type +ffffffff83390024 D amdgpu_aspm +ffffffff83390028 D amdgpu_runtime_pm +ffffffff8339002c D amdgpu_ip_block_mask +ffffffff83390030 D amdgpu_bapm +ffffffff83390034 D amdgpu_vm_size +ffffffff83390038 D amdgpu_vm_fragment_size +ffffffff8339003c D amdgpu_vm_block_size +ffffffff83390040 D amdgpu_vm_update_mode +ffffffff83390044 D amdgpu_dc +ffffffff83390048 D amdgpu_sched_jobs +ffffffff8339004c D amdgpu_sched_hw_submission +ffffffff83390050 D amdgpu_cg_mask +ffffffff83390058 D amdgpu_pg_mask +ffffffff8339005c D amdgpu_sdma_phase_quantum +ffffffff83390060 D amdgpu_pp_feature_mask +ffffffff83390064 D amdgpu_lbpw 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dcn3_0_ip -ffffffff833f81b8 D dcn3_0_soc -ffffffff833fa000 D dcn3_01_ip -ffffffff833fa1b8 D dcn3_01_soc -ffffffff833fb4f0 D ddr4_wm_table -ffffffff833fb5b0 D lpddr5_wm_table -ffffffff833fc000 D dcn3_02_ip -ffffffff833fc1b8 D dcn3_02_soc -ffffffff833fe000 D dcn3_03_ip -ffffffff833fe1b8 D dcn3_03_soc -ffffffff83400000 D dcn3_1_ip -ffffffff834001b8 D dcn3_15_ip -ffffffff83400370 D dcn3_16_ip -ffffffff83400528 d dcn3_15_soc -ffffffff83401860 d dcn3_1_soc -ffffffff83402b98 d dcn3_16_soc -ffffffff83404000 D dcn3_14_ip -ffffffff834041b8 d dcn3_14_soc -ffffffff83406000 D dcn3_2_ip -ffffffff834061b8 D dcn3_2_soc -ffffffff83408000 D dcn3_21_ip -ffffffff834081b8 D dcn3_21_soc -ffffffff8340a000 d dsc_policy_max_target_bpp_limit -ffffffff8340b000 D DIDTEDCConfig_P12 -ffffffff8340b070 d smu7_profiling -ffffffff8340c000 d cyan_skillfish_table_map -ffffffff8340c080 d cyan_skillfish_message_map -ffffffff8340d000 d navi10_table_map -ffffffff8340d080 d navi10_pwr_src_map -ffffffff8340d090 d navi10_workload_map -ffffffff8340d0e0 d navi10_message_map -ffffffff8340db60 d navi10_clk_map -ffffffff8340dc20 d navi10_feature_mask_map -ffffffff8340e000 d sienna_cichlid_table_map -ffffffff8340e080 d sienna_cichlid_pwr_src_map -ffffffff8340e090 d sienna_cichlid_workload_map -ffffffff8340e0e0 d sienna_cichlid_message_map -ffffffff8340eb60 d sienna_cichlid_clk_map -ffffffff8340ec20 d sienna_cichlid_feature_mask_map -ffffffff8340f000 d vangogh_message_map -ffffffff8340fa80 d vangogh_table_map -ffffffff8340fb00 d vangogh_workload_map -ffffffff8340fb50 d vangogh_feature_mask_map -ffffffff83410000 d renoir_table_map -ffffffff83410080 d renoir_workload_map -ffffffff834100d0 d renoir_message_map -ffffffff83410b50 d renoir_clk_map -ffffffff83411000 d smu_v13_0_0_message_map -ffffffff83411a80 d smu_v13_0_0_feature_mask_map -ffffffff83411e50 d smu_v13_0_0_table_map -ffffffff83411ed0 d smu_v13_0_0_pwr_src_map -ffffffff83411ee0 d smu_v13_0_0_workload_map -ffffffff83411f30 d smu_v13_0_0_clk_map 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ral_rt2661_opns -ffffffff8341c050 d ral_rt2860_opns -ffffffff8341d000 D pcmcia_cd -ffffffff8341e000 D pcmcia_3cxem556_func0 -ffffffff8341e0b8 D pcmcia_3cxem556_func0_cfe0 -ffffffff8341e158 D pcmcia_megahertz_xjem1144_func0 -ffffffff8341e210 D pcmcia_megahertz_xjem1144_func0_cfe0 -ffffffff8341e2b0 d pcmcia_3cxem556_func1 -ffffffff8341e368 d pcmcia_3cxem556_func1_cfe0 -ffffffff8341e408 d pcmcia_megahertz_xjem1144_func1 -ffffffff8341e4c0 d pcmcia_megahertz_xjem1144_func1_cfe0 -ffffffff8341e560 d pcmcia_sierra_a555_func1 -ffffffff8341e618 d pcmcia_sierra_a555_func1_cfe0 -ffffffff8341e6b8 d pcmcia_sveclancard_func0 -ffffffff8341e770 d pcmcia_sveclancard_func0_cfe0 -ffffffff8341f000 D ep_pcmcia_prod -ffffffff83420000 D aic_pcmcia_prod -ffffffff83421000 D com_pcmcia_prod -ffffffff83422000 D wdc_pcmcia_pr -ffffffff83423000 D sm_pcmcia_prod -ffffffff83424000 D xe_cd -ffffffff83425000 D pcib_cd -ffffffff83426000 D amdpcib_cd -ffffffff83427000 D tcpcib_cd -ffffffff83428000 D aapic_cd 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d ral_rt2560_opns +ffffffff8341e028 d ral_rt2661_opns +ffffffff8341e050 d ral_rt2860_opns +ffffffff8341f000 D pcmcia_cd +ffffffff83420000 D pcmcia_3cxem556_func0 +ffffffff834200b8 D pcmcia_3cxem556_func0_cfe0 +ffffffff83420158 D pcmcia_megahertz_xjem1144_func0 +ffffffff83420210 D pcmcia_megahertz_xjem1144_func0_cfe0 +ffffffff834202b0 d pcmcia_3cxem556_func1 +ffffffff83420368 d pcmcia_3cxem556_func1_cfe0 +ffffffff83420408 d pcmcia_megahertz_xjem1144_func1 +ffffffff834204c0 d pcmcia_megahertz_xjem1144_func1_cfe0 +ffffffff83420560 d pcmcia_sierra_a555_func1 +ffffffff83420618 d pcmcia_sierra_a555_func1_cfe0 +ffffffff834206b8 d pcmcia_sveclancard_func0 +ffffffff83420770 d pcmcia_sveclancard_func0_cfe0 +ffffffff83421000 D ep_pcmcia_prod +ffffffff83422000 D aic_pcmcia_prod +ffffffff83423000 D com_pcmcia_prod +ffffffff83424000 D wdc_pcmcia_pr +ffffffff83425000 D sm_pcmcia_prod +ffffffff83426000 D xe_cd +ffffffff83427000 D pcib_cd +ffffffff83428000 D amdpcib_cd +ffffffff83429000 D tcpcib_cd +ffffffff8342a000 D aapic_cd +ffffffff8342b000 D hme_cd +ffffffff8342c000 D isa_cd +ffffffff8342d000 D isadma_cd +ffffffff8342e000 D fdc_cd +ffffffff8342f000 D fd_types +ffffffff8342f1f8 D fd_cd +ffffffff83430000 D mpu_cd +ffffffff83431000 D pcppi_cd +ffffffff83432000 D spkr_cd +ffffffff83433000 D wbsio_cd +ffffffff83434000 D schsio_cd +ffffffff83435000 D it_cd +ffffffff83436000 D uguru_cd +ffffffff83437000 D aps_cd +ffffffff83438000 D isa_bus_dma_tag +ffffffff83439000 D wsdisplay_cd +ffffffff83439020 D wsdisplay_cons +ffffffff83439058 D wsdisplay_defaultscreens +ffffffff8343a000 D wskbd_cd +ffffffff8343a020 D wskbd_default_bell_data +ffffffff8343a030 D wskbd_default_keyrepeat_data +ffffffff8343a040 D wskbd_srcops +ffffffff8343b000 d compose_tab +ffffffff8343c000 D wsmouse_cd +ffffffff8343c020 D wsmouse_srcops +ffffffff8343d000 D wsmux_srcops +ffffffff8343d030 D wsmux_tree_lock +ffffffff8343e000 D vt100_output +ffffffff8343f000 D pckbd_cd +ffffffff83440000 D pms_cd +ffffffff83440020 d synaptics_params +ffffffff83440030 d alps_params +ffffffff83441000 D skgpio_cd +ffffffff83442000 D pctr_conf_lock +ffffffff83443000 D ukbd_keymapdata +ffffffff83444000 D usbrev_str +ffffffff83444030 D usb_cd +ffffffff83445000 d usbd_ratecheck.errinterval +ffffffff83446000 D uhub_cd +ffffffff83447000 D uaudio_cd +ffffffff83448000 D uvideo_ctrls +ffffffff834482d8 D uvideo_cd +ffffffff83449000 D utvfu_norm_params +ffffffff83449030 D utvfu_cd +ffffffff8344a000 D udl_reg_vals_640x480_60 +ffffffff8344a020 D udl_reg_vals_640x480_67 +ffffffff8344a040 D udl_reg_vals_640x480_72 +ffffffff8344a060 D udl_reg_vals_640x480_75 +ffffffff8344a080 D udl_reg_vals_800x480_61 +ffffffff8344a0a0 D udl_reg_vals_800x600_56 +ffffffff8344a0c0 D udl_reg_vals_800x600_60 +ffffffff8344a0e0 D udl_reg_vals_800x600_72 +ffffffff8344a100 D udl_reg_vals_800x600_74 +ffffffff8344a120 D udl_reg_vals_800x600_75 +ffffffff8344a140 D udl_reg_vals_1024x768_60 +ffffffff8344a160 D udl_reg_vals_1024x768_70 +ffffffff8344a180 D udl_reg_vals_1024x768_75 +ffffffff8344a1a0 D udl_reg_vals_1280x800_60 +ffffffff8344a1c0 D udl_reg_vals_1280x960_60 +ffffffff8344a1e0 D udl_reg_vals_1280x1024_60 +ffffffff8344a200 D udl_reg_vals_1280x1024_75 +ffffffff8344a220 D udl_reg_vals_1366x768_60 +ffffffff8344a240 D udl_reg_vals_1440x900_60 +ffffffff8344a260 D udl_reg_vals_1440x900_59 +ffffffff8344a280 D udl_reg_vals_1440x900_75 +ffffffff8344a2a0 D udl_reg_vals_1680x1050_60 +ffffffff8344a2c0 D udl_reg_vals_1600x1200_60 +ffffffff8344a2e0 D udl_reg_vals_1920x1080_60 +ffffffff8344a300 D udl_null_key_1 +ffffffff8344a310 D udl_decomp_table +ffffffff8344b510 D udl_cd +ffffffff8344b530 D udl_stdscreen +ffffffff8344b560 D udl_scrlist +ffffffff8344b568 D udl_screenlist +ffffffff8344b578 D udl_accessops +ffffffff8344c000 D umidi_cd +ffffffff8344d000 d umq_YAMAHA_YAMAHA_UX256_ANYIFACE +ffffffff8344d020 d umq_ROLAND_ROLAND_UM1_2 +ffffffff8344d040 d umq_ROLAND_ROLAND_SC8850_2 +ffffffff8344d060 d umq_ROLAND_ROLAND_SD90_2 +ffffffff8344d080 d umq_ROLAND_ROLAND_UM880N_0 +ffffffff8344d0a0 d umq_ROLAND_ROLAND_UA100_2 +ffffffff8344d0c0 d umq_ROLAND_ROLAND_UM4_2 +ffffffff8344d0e0 d umq_ROLAND_ROLAND_U8_2 +ffffffff8344d100 d umq_ROLAND_ROLAND_UM2_2 +ffffffff8344d120 d umq_ROLAND_ROLAND_SC8820_2 +ffffffff8344d140 d umq_ROLAND_ROLAND_PC300_2 +ffffffff8344d160 d umq_ROLAND_ROLAND_SK500_2 +ffffffff8344d180 d umq_ROLAND_ROLAND_SCD70_2 +ffffffff8344d1a0 d umq_ROLAND_ROLAND_UM550_0 +ffffffff8344d1c0 d umq_ROLAND_ROLAND_SD20_0 +ffffffff8344d1e0 d umq_ROLAND_ROLAND_SD80_0 +ffffffff8344d200 d umq_ROLAND_ROLAND_UA700_3 +ffffffff8344d220 d umq_ROLAND_ROLAND_UMONE_ANYIFACE +ffffffff8344d240 D umidi_quirklist +ffffffff8344d4a0 d umq_YAMAHA_YAMAHA_UX256_ANYIFACE_fixed_ep_desc +ffffffff8344d4c0 d umq_YAMAHA_YAMAHA_UX256_ANYIFACE_fixed_ep_endpoints +ffffffff8344d4d0 d umq_ROLAND_ROLAND_UM1_2_fixed_ep_desc +ffffffff8344d4f0 d umq_ROLAND_ROLAND_UM1_2_fixed_ep_endpoints +ffffffff8344d500 d umq_ROLAND_ROLAND_SC8850_2_fixed_ep_desc +ffffffff8344d520 d umq_ROLAND_ROLAND_SC8850_2_fixed_ep_endpoints +ffffffff8344d530 d umq_ROLAND_ROLAND_SD90_2_fixed_ep_desc +ffffffff8344d550 d umq_ROLAND_ROLAND_SD90_2_fixed_ep_endpoints +ffffffff8344d560 d umq_ROLAND_ROLAND_UM880N_0_fixed_ep_desc +ffffffff8344d580 d umq_ROLAND_ROLAND_UM880N_0_fixed_ep_endpoints +ffffffff8344d590 d umq_ROLAND_ROLAND_UA100_2_fixed_ep_desc +ffffffff8344d5b0 d umq_ROLAND_ROLAND_UA100_2_fixed_ep_endpoints +ffffffff8344d5c0 d umq_ROLAND_ROLAND_UM4_2_fixed_ep_desc +ffffffff8344d5e0 d umq_ROLAND_ROLAND_UM4_2_fixed_ep_endpoints +ffffffff8344d5f0 d umq_ROLAND_ROLAND_U8_2_fixed_ep_desc +ffffffff8344d610 d umq_ROLAND_ROLAND_U8_2_fixed_ep_endpoints +ffffffff8344d620 d umq_ROLAND_ROLAND_UM2_2_fixed_ep_desc +ffffffff8344d640 d umq_ROLAND_ROLAND_UM2_2_fixed_ep_endpoints +ffffffff8344d650 d umq_ROLAND_ROLAND_SC8820_2_fixed_ep_desc +ffffffff8344d670 d umq_ROLAND_ROLAND_SC8820_2_fixed_ep_endpoints +ffffffff8344d680 d umq_ROLAND_ROLAND_PC300_2_fixed_ep_desc +ffffffff8344d6a0 d umq_ROLAND_ROLAND_PC300_2_fixed_ep_endpoints +ffffffff8344d6b0 d umq_ROLAND_ROLAND_SK500_2_fixed_ep_desc +ffffffff8344d6d0 d umq_ROLAND_ROLAND_SK500_2_fixed_ep_endpoints +ffffffff8344d6e0 d umq_ROLAND_ROLAND_SCD70_2_fixed_ep_desc +ffffffff8344d700 d umq_ROLAND_ROLAND_SCD70_2_fixed_ep_endpoints +ffffffff8344d710 d umq_ROLAND_ROLAND_UM550_0_fixed_ep_desc +ffffffff8344d730 d umq_ROLAND_ROLAND_UM550_0_fixed_ep_endpoints +ffffffff8344d740 d umq_ROLAND_ROLAND_SD20_0_fixed_ep_desc +ffffffff8344d760 d umq_ROLAND_ROLAND_SD20_0_fixed_ep_endpoints +ffffffff8344d770 d umq_ROLAND_ROLAND_SD80_0_fixed_ep_desc +ffffffff8344d790 d umq_ROLAND_ROLAND_SD80_0_fixed_ep_endpoints +ffffffff8344d7a0 d umq_ROLAND_ROLAND_UA700_3_fixed_ep_desc +ffffffff8344d7c0 d umq_ROLAND_ROLAND_UA700_3_fixed_ep_endpoints +ffffffff8344d7d0 d umq_ROLAND_ROLAND_UMONE_ANYIFACE_fixed_ep_desc +ffffffff8344d7f0 d umq_ROLAND_ROLAND_UMONE_ANYIFACE_fixed_ep_endpoints +ffffffff8344e000 D ucom_cd +ffffffff8344e020 D sysctl_ucomlock +ffffffff8344f000 D ugen_cd +ffffffff83450000 D uhidev_cd +ffffffff83450020 d uhidev_use_rdesc.reportbuf +ffffffff83451000 D uhid_cd +ffffffff83452000 D fido_cd +ffffffff83453000 D ujoy_cd +ffffffff83454000 D ukbd_cd +ffffffff83455000 D ums_cd +ffffffff83455020 d ums_fix_elecom_descriptor.match +ffffffff83456000 D umt_cd +ffffffff83457000 D def_scale +ffffffff83457020 D uts_cd +ffffffff83458000 D ubcmtp_cd +ffffffff83458020 d ubcmtp_wsmousecfg +ffffffff83459000 D ucycom_cd +ffffffff8345a000 D uslhcom_cd +ffffffff8345b000 D ulpt_fwdevs +ffffffff8345b060 D ulpt_cd +ffffffff8345b080 D ulptusein +ffffffff8345c000 D umass_cd +ffffffff8345c020 d umass_bbb_transfer.dCBWtag +ffffffff8345d000 D uthum_cd +ffffffff8345e000 D ugold_cd +ffffffff8345e020 d cmd_init +ffffffff8345e028 d cmd_type +ffffffff8345e030 d cmd_data +ffffffff8345f000 D utrh_cd +ffffffff83460000 D uoakrh_cd +ffffffff83461000 D uoaklux_cd +ffffffff83462000 D uoakv_cd +ffffffff83463000 D uonerng_cd +ffffffff83464000 D urng_cd +ffffffff83465000 D udcf_cd +ffffffff83466000 D umbg_cd +ffffffff83467000 D uvisor_cd +ffffffff83468000 D udsbr_cd +ffffffff83469000 D utwitch_cd +ffffffff8346a000 D aue_cd +ffffffff8346b000 D axe_cd +ffffffff8346c000 D axen_cd +ffffffff8346d000 D smsc_cd +ffffffff8346e000 D cue_devs +ffffffff8346e010 D cue_cd +ffffffff8346f000 D kue_cd +ffffffff83470000 D cdce_cd +ffffffff83471000 D urndis_cd +ffffffff83472000 D mos_cd +ffffffff83473000 D mue_cd +ffffffff83474000 D udav_cd +ffffffff83475000 D upl_devs +ffffffff83475008 D upl_cd +ffffffff83476000 D ugl_devs +ffffffff83476008 D ugl_cd +ffffffff83477000 D url_cd +ffffffff83478000 D ure_cd +ffffffff83479000 D uaq_cd +ffffffff8347a000 D umodem_cd +ffffffff8347b000 D uftdi_cd +ffffffff8347c000 D uplcom_cd +ffffffff8347d000 D umct_cd +ffffffff8347e000 D uvscom_cd +ffffffff8347f000 D ubsa_cd +ffffffff83480000 D ukspan_cd +ffffffff83481000 D uslcom_cd +ffffffff83482000 D uark_cd +ffffffff83483000 D moscom_cd +ffffffff83484000 D umcs_cd +ffffffff83485000 D uscom_cd +ffffffff83486000 D ucrcom_cd +ffffffff83487000 D uxrcom_cd +ffffffff83488000 D uipaq_cd +ffffffff83489000 D umsm_cd +ffffffff8348a000 D uchcom_cd +ffffffff8348b000 D uticom_cd +ffffffff8348c000 D wi_func_usb +ffffffff8348c060 D wi_usb_cd +ffffffff8348d000 D atu_cd +ffffffff8348d020 D atu_devs +ffffffff8348d270 D atu_radfirm +ffffffff8348e000 D ural_cd +ffffffff8348f000 D rum_cd +ffffffff83490000 D run_cd +ffffffff83490020 D rt3070_freqs +ffffffff83491000 D mtw_cd +ffffffff83492000 D zyd_cd +ffffffff83493000 D upgt_cd +ffffffff83494000 D urtw_cd +ffffffff83495000 D urtwn_cd +ffffffff83496000 D rsu_cd +ffffffff83497000 D otus_cd +ffffffff83497020 d AR_PLCP_HDR_INTR +ffffffff83498000 D umb_xfer_tout +ffffffff83498010 D umb_uuid_basic_connect +ffffffff83498020 D umb_uuid_context_internet +ffffffff83498030 D umb_uuid_qmi_mbim +ffffffff83498040 D umb_cd +ffffffff83498060 D umb_delay +ffffffff83498070 D umb_qmi_alloc_cid +ffffffff83498080 D umb_qmi_fcc_auth +ffffffff83499000 D uath_cd +ffffffff8349a000 D uow_cd +ffffffff8349b000 D uberry_cd +ffffffff8349c000 D upd_cd +ffffffff8349c020 d upd_usage_roots +ffffffff8349c0a0 d upd_usage_batdep +ffffffff8349d000 D uwacom_cd +ffffffff8349d020 d uwacom_attach.wacom_report_buf +ffffffff8349e000 D bwfm_usb_bus_ops +ffffffff8349f000 D umstc_cd +ffffffff834a0000 D uhidpp_cd +ffffffff834a1000 D ucc_cd +ffffffff834a2000 D iic_cd +ffffffff834a3000 D probe_addrs_sensor +ffffffff834a3008 D probe_addrs_eeprom +ffffffff834a4000 D lmtemp_cd +ffffffff834a5000 D lmn_worklist +ffffffff834a5240 D lmn_cd +ffffffff834a6000 D lmenv_cd +ffffffff834a7000 D maxtmp_cd +ffffffff834a8000 D adc_cd +ffffffff834a9000 D admtemp_cd +ffffffff834aa000 D admlc_cd +ffffffff834ab000 D admtm_cd +ffffffff834ac000 D admtmp_cd +ffffffff834ad000 D admtt_cd +ffffffff834ae000 D maxds_cd +ffffffff834af000 D adt_chips +ffffffff834af160 D worklist +ffffffff834af1a0 D adt_cd +ffffffff834b0000 D admcts_cd +ffffffff834b1000 D wbng_cd +ffffffff834b2000 D nvt_cd +ffffffff834b3000 D adl_worklist +ffffffff834b3138 D adl_cd +ffffffff834b4000 D andl_cd +ffffffff834b5000 D sdtemp_cd +ffffffff834b6000 D lisa_cd +ffffffff834b7000 D ihidev_cd +ffffffff834b8000 D ikbd_cd +ffffffff834b9000 D ims_cd +ffffffff834ba000 D imt_cd +ffffffff834bb000 D iatp_cd +ffffffff834bc000 D ietp_cd +ffffffff834bd000 D bgw_cd +ffffffff834be000 D icc_cd +ffffffff834bf000 D gpio_cd +ffffffff834c0000 D acpi_cd +ffffffff834c0020 D acpi_pcidevs +ffffffff834c0030 D acpi_pcirootdevs +ffffffff834c0040 D acpi_taskq +ffffffff834c0050 d acpi_indicator.save_led_state +ffffffff834c0060 d acpi_getprop.prop_guid +ffffffff834c0070 d acpi_getpropint.prop_guid +ffffffff834c0080 D acpi_skip_hids +ffffffff834c00f0 D acpi_isa_hids +ffffffff834c1000 D aml_intlen +ffffffff834c1010 D aml_table +ffffffff834c1af0 d osstring +ffffffff834c1b10 D aml_defobj +ffffffff834c1ca0 D aml_valid_osi +ffffffff834c1d78 D acpi_max_osi +ffffffff834c1d80 D aml_regionspace +ffffffff834c3000 D acpitimer_cd +ffffffff834c3020 d acpi_timecounter +ffffffff834c4000 D acpiac_cd +ffffffff834c4020 D acpiac_hids +ffffffff834c5000 D acpibat_cd +ffffffff834c5020 D acpibat_hids +ffffffff834c6000 D acpibtn_cd +ffffffff834c6020 D acpibtn_hids +ffffffff834c7000 D acpicmos_cd +ffffffff834c7020 D acpicmos_hids +ffffffff834c8000 D acpicpu_cd +ffffffff834c8020 D acpicpu_hids +ffffffff834c8030 d acpicpu_set_pdc.cpu_oscuuid +ffffffff834c9000 D acpihpet_cd +ffffffff834c9020 d hpet_timecounter +ffffffff834ca000 D acpiec_cd +ffffffff834ca020 D acpiec_hids +ffffffff834cb000 D acpitz_cd +ffffffff834cb020 D acpitz_perflevel +ffffffff834cc000 D acpimadt_cd +ffffffff834cd000 D acpimcfg_cd +ffffffff834ce000 D acpiprt_map_list +ffffffff834ce010 D acpiprt_cd +ffffffff834ce030 D acpiprt_pri +ffffffff834cf000 D acpidmar_force_cm +ffffffff834cf008 D acpidmar_cd +ffffffff834cf030 D vtd_faults +ffffffff834d0000 D acpidock_cd +ffffffff834d1000 D abl_cd +ffffffff834d1020 D abl_hids +ffffffff834d2000 D asmc_cd +ffffffff834d2020 D asmc_hids +ffffffff834d3000 D acpiasus_cd +ffffffff834d3020 D acpiasus_hids +ffffffff834d4000 D acpithinkpad_cd +ffffffff834d4020 D acpithinkpad_hids +ffffffff834d5000 D acpitoshiba_cd +ffffffff834d5020 D acpitoshiba_hids +ffffffff834d6000 D acpisony_cd +ffffffff834d7000 D acpivideo_cd +ffffffff834d8000 D acpivout_cd +ffffffff834d9000 D acpipwrres_cd +ffffffff834da000 D aibs_cd +ffffffff834da020 d aibs_hids +ffffffff834db000 D aplgpio_cd +ffffffff834db020 D aplgpio_hids +ffffffff834dc000 D bytgpio_cd +ffffffff834dc020 D bytgpio_hids +ffffffff834dd000 D chvgpio_cd +ffffffff834dd020 D chvgpio_hids +ffffffff834de000 D glkgpio_cd +ffffffff834de020 D glkgpio_hids +ffffffff834df000 D pchgpio_cd +ffffffff834df020 D pchgpio_hids +ffffffff834df080 D pchgpio_devices +ffffffff834e0000 D tipmic_cd +ffffffff834e0020 D tipmic_thermal_regmap +ffffffff834e0030 D tipmic_power_regmap +ffffffff834e1000 D ccpmic_cd +ffffffff834e1020 D ccpmic_thermal_regmap +ffffffff834e1023 D ccpmic_power_regmap +ffffffff834e2000 D com_hids +ffffffff834e3000 D sdhc_hids +ffffffff834e4000 D dwiic_hids +ffffffff834e4050 D ihidev_hids +ffffffff834e4070 D ietp_hids +ffffffff834e4220 D iatp_hids +ffffffff834e4240 d dwiic_acpi_found_ihidev.i2c_hid_guid +ffffffff834e5000 D acpicbkbd_cd +ffffffff834e5020 D acpicbkbd_hids +ffffffff834e6000 D acpials_cd +ffffffff834e6020 D acpials_hids +ffffffff834e7000 D tpm_cd +ffffffff834e7020 D tpm_hids +ffffffff834e8000 D acpihve_cd +ffffffff834e9000 D acpisbs_cd +ffffffff834e9020 D acpisbs_hids +ffffffff834ea000 D acpisurface_cd +ffffffff834ea020 D acpisurface_hids +ffffffff834eb000 D ipmi_acpi_hids +ffffffff834ec000 D amdgpio_cd +ffffffff834ec020 D amdgpio_hids +ffffffff834ed000 D acpihid_cd +ffffffff834ed020 D acpihid_hids +ffffffff834ed030 d acpihid_guid +ffffffff834ee000 d iosf_hids +ffffffff834ef000 D acpipci_cd +ffffffff834ef020 D acpipci_hids +ffffffff834ef040 d acpipci_osc.uuid +ffffffff834f0000 D efi_cd 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pdevnames_size +ffffffff835027c0 D pdevinit +ffffffff83503000 D rootdev +ffffffff83503004 D dumpdev +ffffffff83503010 D swdevt +ffffffff83504000 A __kudata_start +ffffffff83504000 D tlb_shoot_first_pcid +ffffffff83504008 D tlb_shoot_addr1 +ffffffff83504010 D tlb_shoot_addr2 +ffffffff83504018 D tlb_shoot_wait +ffffffff83505000 A __kudata_end +ffffffff83505000 C _edata +ffffffff83505000 b drm_minors_idr +ffffffff83505008 B drm_refcnt +ffffffff83506000 B vga_console_screen +ffffffff83506070 B vga_console_attached +ffffffff83506078 B vga_console_vc +ffffffff83506488 B vgaconsole +ffffffff8350648c B vga_console_type +ffffffff83507000 b wdc_alloc_queue.inited +ffffffff83507008 B wdc_xfer_pool +ffffffff835071b0 B wdc_xfer_iopool +ffffffff83508000 B aic_debug +ffffffff83509000 B gdt_cnt +ffffffff83509004 B gdt_polling +ffffffff83509005 B gdt_from_wait +ffffffff83509008 b gdt_exec_ccb.__level +ffffffff8350900c B gdt_wait_index +ffffffff83509010 B gdt_wait_gdt +ffffffff8350a000 B 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