--- 7.4/2024-01-26T23:47:18Z/2023-12-11T00:00:00Z/nm-bsd-ot14.txt	Sun Jan 28 10:38:47 2024
+++ 7.4/2024-01-26T23:47:18Z/2023-12-12T00:00:00Z/nm-bsd-ot14.txt	Sun Jan 28 13:24:51 2024
@@ -4871,35 +4871,35 @@ ffffffff81245860 t pfsync_in_tdb
 ffffffff81245a40 t pfsync_deferred
 ffffffff81245b30 t pfsync_in_updates
 ffffffff81246000 T pflow_clone_create
-ffffffff812462f0 T pflow_clone_destroy
-ffffffff812464d0 T pflowattach
-ffffffff81246500 T pflow_output
-ffffffff81246540 T pflow_output_process
-ffffffff81246650 T pflow_sendout_mbuf
-ffffffff81246710 T pflowioctl
-ffffffff81246b50 T pflow_setmtu
-ffffffff81246c50 T pflow_timeout
-ffffffff81246ca0 T pflow_timeout6
-ffffffff81246ce0 T pflow_timeout_tmpl
-ffffffff81246d10 T pflow_flush
-ffffffff81246d70 T pflowvalidsockaddr
-ffffffff81246de0 T pflow_set
-ffffffff81247320 T pflow_sendout_ipfix_tmpl
-ffffffff812474b0 T pflow_calc_mtu
-ffffffff81247560 T pflow_get_mbuf
-ffffffff81247700 T copy_flow_data
-ffffffff81247870 T copy_flow_ipfix_4_data
-ffffffff81247a50 T copy_flow_ipfix_6_data
-ffffffff81247c80 T export_pflow
-ffffffff81247d50 T export_pflow_if
-ffffffff81247f20 T pflow_pack_flow_ipfix
-ffffffff812481f0 T pflow_pack_flow
-ffffffff81248470 T copy_flow_to_m
-ffffffff812485a0 T pflow_sendout_v5
-ffffffff812486f0 T copy_flow_ipfix_4_to_m
-ffffffff81248840 T pflow_sendout_ipfix
-ffffffff81248a40 T copy_flow_ipfix_6_to_m
-ffffffff81248b90 T pflow_sysctl
+ffffffff81246300 T pflow_clone_destroy
+ffffffff81246500 T pflowattach
+ffffffff81246530 T pflow_output
+ffffffff81246570 T pflow_output_process
+ffffffff81246680 T pflow_sendout_mbuf
+ffffffff81246740 T pflowioctl
+ffffffff81246b80 T pflow_setmtu
+ffffffff81246c80 T pflow_timeout
+ffffffff81246cd0 T pflow_timeout6
+ffffffff81246d10 T pflow_timeout_tmpl
+ffffffff81246d40 T pflow_flush
+ffffffff81246da0 T pflowvalidsockaddr
+ffffffff81246e10 T pflow_set
+ffffffff81247350 T pflow_sendout_ipfix_tmpl
+ffffffff812474e0 T pflow_calc_mtu
+ffffffff81247590 T pflow_get_mbuf
+ffffffff81247730 T copy_flow_data
+ffffffff812478a0 T copy_flow_ipfix_4_data
+ffffffff81247a80 T copy_flow_ipfix_6_data
+ffffffff81247cb0 T export_pflow
+ffffffff81247d70 T export_pflow_if
+ffffffff81247f40 T pflow_pack_flow_ipfix
+ffffffff81248210 T pflow_pack_flow
+ffffffff81248490 T copy_flow_to_m
+ffffffff812485c0 T pflow_sendout_v5
+ffffffff81248710 T copy_flow_ipfix_4_to_m
+ffffffff81248860 T pflow_sendout_ipfix
+ffffffff81248a60 T copy_flow_ipfix_6_to_m
+ffffffff81248bb0 T pflow_sysctl
 ffffffff81249000 T bioattach
 ffffffff81249030 T bioopen
 ffffffff81249060 T bioclose
@@ -13634,30 +13634,30 @@ ffffffff81696cd0 T vio_rx_intr
 ffffffff81696d50 T vio_tx_intr
 ffffffff81696db0 T vio_ctrleof
 ffffffff81696e60 T vio_start
-ffffffff81697300 T vio_ioctl
-ffffffff816974b0 T vio_media_change
-ffffffff816974e0 T vio_media_status
-ffffffff816975a0 T vio_config_change
-ffffffff81697630 T vio_txtick
-ffffffff81697690 T vio_rxtick
-ffffffff816976d0 T vio_link_state
-ffffffff81697760 T vio_init
-ffffffff81697840 T vio_stop
-ffffffff81697a90 T vio_populate_rx_mbufs
-ffffffff81697d40 T vio_iff
-ffffffff81697f20 T vio_rxeof
-ffffffff816981e0 T vio_tx_drain
-ffffffff816982a0 T vio_rx_drain
-ffffffff81698350 T vio_txeof
-ffffffff81698510 T vio_encap
-ffffffff816985e0 T vio_add_rx_mbuf
-ffffffff816986b0 T vio_free_rx_mbuf
-ffffffff81698730 T vio_rx_offload
-ffffffff816987e0 T vio_ctrl_rx
-ffffffff81698c00 T vio_wait_ctrl
-ffffffff81698cd0 T vio_wait_ctrl_done
-ffffffff81698da0 T vio_ctrl_wakeup
-ffffffff81698dc0 T vio_set_rx_filter
+ffffffff816972e0 T vio_ioctl
+ffffffff81697490 T vio_media_change
+ffffffff816974c0 T vio_media_status
+ffffffff81697580 T vio_config_change
+ffffffff81697610 T vio_txtick
+ffffffff81697670 T vio_rxtick
+ffffffff816976b0 T vio_link_state
+ffffffff81697740 T vio_init
+ffffffff81697820 T vio_stop
+ffffffff81697a70 T vio_populate_rx_mbufs
+ffffffff81697d20 T vio_iff
+ffffffff81697f00 T vio_rxeof
+ffffffff816981c0 T vio_tx_drain
+ffffffff81698280 T vio_rx_drain
+ffffffff81698330 T vio_txeof
+ffffffff816984f0 T vio_encap
+ffffffff816985c0 T vio_add_rx_mbuf
+ffffffff81698690 T vio_free_rx_mbuf
+ffffffff81698710 T vio_rx_offload
+ffffffff816987c0 T vio_ctrl_rx
+ffffffff81698be0 T vio_wait_ctrl
+ffffffff81698cb0 T vio_wait_ctrl_done
+ffffffff81698d80 T vio_ctrl_wakeup
+ffffffff81698da0 T vio_set_rx_filter
 ffffffff8169a000 T vioblk_match
 ffffffff8169a040 T vioblk_attach
 ffffffff8169a300 T vioblk_scsi_cmd
@@ -18588,18 +18588,18 @@ ffffffff8190d000 T dma_resv_init
 ffffffff8190d060 T dma_resv_fini
 ffffffff8190d160 T dma_resv_reserve_fences
 ffffffff8190d320 T dma_resv_add_fence
-ffffffff8190d490 T dma_resv_replace_fences
-ffffffff8190d540 T dma_resv_iter_first_unlocked
-ffffffff8190d5d0 t dma_resv_iter_walk_unlocked
-ffffffff8190d6c0 T dma_resv_iter_next_unlocked
-ffffffff8190d750 T dma_resv_iter_first
-ffffffff8190d7e0 T dma_resv_iter_next
-ffffffff8190d860 T dma_resv_copy_fences
-ffffffff8190dbf0 T dma_resv_get_fences
-ffffffff8190dfe0 T dma_resv_get_singleton
-ffffffff8190e0e0 T dma_resv_wait_timeout
-ffffffff8190e350 T dma_resv_test_signaled
-ffffffff8190e4a0 T dma_resv_describe
+ffffffff8190d4a0 T dma_resv_replace_fences
+ffffffff8190d550 T dma_resv_iter_first_unlocked
+ffffffff8190d5e0 t dma_resv_iter_walk_unlocked
+ffffffff8190d6d0 T dma_resv_iter_next_unlocked
+ffffffff8190d760 T dma_resv_iter_first
+ffffffff8190d7f0 T dma_resv_iter_next
+ffffffff8190d870 T dma_resv_copy_fences
+ffffffff8190dc00 T dma_resv_get_fences
+ffffffff8190dff0 T dma_resv_get_singleton
+ffffffff8190e0f0 T dma_resv_wait_timeout
+ffffffff8190e360 T dma_resv_test_signaled
+ffffffff8190e4b0 T dma_resv_describe
 ffffffff8190f000 T drm_legacy_agp_info
 ffffffff8190f0b0 T drm_legacy_agp_acquire
 ffffffff8190f120 T drm_legacy_agp_release
@@ -27727,103 +27727,103 @@ ffffffff81dde270 t gfx_v11_0_late_init
 ffffffff81dde2e0 t gfx_v11_0_sw_init
 ffffffff81ddec90 t gfx_v11_0_sw_fini
 ffffffff81ddef60 t gfx_v11_0_hw_init
-ffffffff81de3430 t gfx_v11_0_hw_fini
-ffffffff81de36a0 t gfx_v11_0_suspend
-ffffffff81de36e0 t gfx_v11_0_resume
-ffffffff81de36f0 t gfx_v11_0_is_idle
-ffffffff81de3780 t gfx_v11_0_wait_for_idle
-ffffffff81de3860 t gfx_v11_0_check_soft_reset
-ffffffff81de3990 t gfx_v11_0_soft_reset
-ffffffff81de4650 t gfx_v11_0_post_soft_reset
-ffffffff81de4660 t gfx_v11_0_set_clockgating_state
-ffffffff81de5240 t gfx_v11_0_set_powergating_state
-ffffffff81de52e0 t gfx_v11_0_get_clockgating_state
-ffffffff81de54b0 t gfx11_kiq_set_resources
-ffffffff81de57d0 t gfx11_kiq_map_queues
-ffffffff81de5b60 t gfx11_kiq_unmap_queues
-ffffffff81de5f60 t gfx11_kiq_query_status
-ffffffff81de6250 t gfx11_kiq_invalidate_tlbs
-ffffffff81de6370 t gfx_v11_0_ring_get_rptr_compute
-ffffffff81de63a0 t gfx_v11_0_ring_get_wptr_compute
-ffffffff81de6410 t gfx_v11_0_ring_set_wptr_compute
-ffffffff81de6550 t gfx_v11_0_ring_emit_ib_compute
-ffffffff81de6890 t gfx_v11_0_ring_emit_fence_kiq
-ffffffff81de6cc0 t gfx_v11_0_ring_test_ring
-ffffffff81de6f40 t gfx_v11_0_ring_test_ib
-ffffffff81de71e0 t gfx_v11_0_ring_emit_rreg
-ffffffff81de7470 t gfx_v11_0_ring_emit_wreg
-ffffffff81de76a0 t gfx_v11_0_ring_emit_reg_wait
-ffffffff81de76f0 t gfx_v11_0_ring_emit_reg_write_reg_wait
-ffffffff81de7760 t gfx_v11_0_wait_reg_mem
-ffffffff81de7a90 t gfx_v11_0_ring_get_rptr_gfx
-ffffffff81de7ac0 t gfx_v11_0_ring_get_wptr_gfx
-ffffffff81de7bd0 t gfx_v11_0_ring_set_wptr_gfx
-ffffffff81de7de0 t gfx_v11_0_ring_emit_ib_gfx
-ffffffff81de8470 t gfx_v11_0_ring_emit_fence
-ffffffff81de8840 t gfx_v11_0_ring_emit_pipeline_sync
-ffffffff81de88a0 t gfx_v11_0_ring_emit_vm_flush
-ffffffff81de8a70 t gfx_v11_0_ring_emit_hdp_flush
-ffffffff81de8b40 t gfx_v11_0_ring_emit_gds_switch
-ffffffff81de8c20 t gfx_v11_0_ring_emit_init_cond_exec
-ffffffff81de8e50 t gfx_v11_0_ring_emit_patch_cond_exec
-ffffffff81de8f10 t gfx_v11_0_ring_emit_cntxcntl
-ffffffff81de9070 t gfx_v11_0_ring_emit_frame_cntl
-ffffffff81de9180 t gfx_v11_0_ring_soft_recovery
-ffffffff81de91f0 t gfx_v11_0_ring_preempt_ib
-ffffffff81de9360 t gfx_v11_0_emit_mem_sync
-ffffffff81de9690 t gfx_v11_0_write_data_to_reg
-ffffffff81de98a0 t gfx_v11_0_set_eop_interrupt_state
-ffffffff81de9930 t gfx_v11_0_eop_irq
-ffffffff81de9af0 t gfx_v11_0_set_gfx_eop_interrupt_state
-ffffffff81de9c80 t gfx_v11_0_set_compute_eop_interrupt_state
-ffffffff81de9e10 t gfx_v11_0_set_priv_reg_fault_state
-ffffffff81de9f30 t gfx_v11_0_priv_reg_irq
-ffffffff81de9f90 t gfx_v11_0_handle_priv_fault
-ffffffff81dea100 t gfx_v11_0_set_priv_inst_fault_state
-ffffffff81dea220 t gfx_v11_0_priv_inst_irq
-ffffffff81dea280 t gfx_v11_0_is_rlc_enabled
-ffffffff81dea300 t gfx_v11_0_set_safe_mode
-ffffffff81dea450 t gfx_v11_0_unset_safe_mode
-ffffffff81dea4c0 t gfx_v11_0_rlc_init
-ffffffff81dea540 t gfx_v11_0_get_csb_size
-ffffffff81dea570 t gfx_v11_0_get_csb_buffer
-ffffffff81dea6e0 t gfx_v11_0_rlc_resume
-ffffffff81deb400 t gfx_v11_0_rlc_stop
-ffffffff81deb4e0 t gfx_v11_0_rlc_reset
-ffffffff81deb680 t gfx_v11_0_rlc_start
-ffffffff81deb820 t gfx_v11_0_update_spm_vmid
-ffffffff81deb920 t gfx_v11_0_init_csb
-ffffffff81debaa0 t gfx_v11_0_gfx_mqd_init
-ffffffff81debe70 t gfx_v11_0_compute_mqd_init
-ffffffff81dec390 t gfx_v11_0_mec_init
-ffffffff81dec4d0 t gfx_v11_0_compute_ring_init
-ffffffff81dec610 t gfx_v11_0_init_toc_microcode
-ffffffff81dec7b0 t gfx_v11_0_rlc_autoload_buffer_init
-ffffffff81dec9a0 t gfx_v11_0_gpu_early_init
-ffffffff81deca40 t amdgpu_bo_unreserve
-ffffffff81decb20 t gfx_v11_0_get_gpu_clock_counter
-ffffffff81dece80 t gfx_v11_0_select_se_sh
-ffffffff81decf20 t gfx_v11_0_read_wave_data
-ffffffff81ded160 t gfx_v11_0_read_wave_vgprs
-ffffffff81ded190 t gfx_v11_0_read_wave_sgprs
-ffffffff81ded210 t gfx_v11_0_select_me_pipe_q
-ffffffff81ded230 t gfx_v11_0_update_perf_clk
-ffffffff81ded360 t wave_read_ind
-ffffffff81ded440 t wave_read_regs
-ffffffff81ded5a0 t gfx_v11_0_disable_gpa_mode
-ffffffff81ded730 t gfx_v11_0_cp_resume
-ffffffff81df1660 t gfx_v11_0_config_me_cache
-ffffffff81df1a00 t gfx_v11_0_config_pfp_cache
-ffffffff81df1da0 t gfx_v11_0_config_mec_cache
-ffffffff81df2140 t gfx_v11_0_enable_gui_idle_interrupt
-ffffffff81df2250 t gfx_v11_0_cp_compute_enable
-ffffffff81df2420 t gfx_v11_0_cp_gfx_enable
-ffffffff81df2610 t amdgpu_bo_reserve
-ffffffff81df2780 t gfx_v11_0_kiq_init_register
-ffffffff81df35d0 t gfx_v11_0_cp_gfx_switch_pipe
-ffffffff81df36b0 t gfx_v11_0_cp_gfx_set_doorbell
-ffffffff81df3890 t gfx_v11_0_cp_gfx_start
-ffffffff81df4110 t gfx_v11_cntl_pg
+ffffffff81de3450 t gfx_v11_0_hw_fini
+ffffffff81de36c0 t gfx_v11_0_suspend
+ffffffff81de3700 t gfx_v11_0_resume
+ffffffff81de3710 t gfx_v11_0_is_idle
+ffffffff81de37a0 t gfx_v11_0_wait_for_idle
+ffffffff81de3880 t gfx_v11_0_check_soft_reset
+ffffffff81de39b0 t gfx_v11_0_soft_reset
+ffffffff81de4670 t gfx_v11_0_post_soft_reset
+ffffffff81de4680 t gfx_v11_0_set_clockgating_state
+ffffffff81de5260 t gfx_v11_0_set_powergating_state
+ffffffff81de5300 t gfx_v11_0_get_clockgating_state
+ffffffff81de54d0 t gfx11_kiq_set_resources
+ffffffff81de57f0 t gfx11_kiq_map_queues
+ffffffff81de5b80 t gfx11_kiq_unmap_queues
+ffffffff81de5f80 t gfx11_kiq_query_status
+ffffffff81de6270 t gfx11_kiq_invalidate_tlbs
+ffffffff81de6390 t gfx_v11_0_ring_get_rptr_compute
+ffffffff81de63c0 t gfx_v11_0_ring_get_wptr_compute
+ffffffff81de6430 t gfx_v11_0_ring_set_wptr_compute
+ffffffff81de6580 t gfx_v11_0_ring_emit_ib_compute
+ffffffff81de68c0 t gfx_v11_0_ring_emit_fence_kiq
+ffffffff81de6cf0 t gfx_v11_0_ring_test_ring
+ffffffff81de6f70 t gfx_v11_0_ring_test_ib
+ffffffff81de7210 t gfx_v11_0_ring_emit_rreg
+ffffffff81de74a0 t gfx_v11_0_ring_emit_wreg
+ffffffff81de76d0 t gfx_v11_0_ring_emit_reg_wait
+ffffffff81de7720 t gfx_v11_0_ring_emit_reg_write_reg_wait
+ffffffff81de7790 t gfx_v11_0_wait_reg_mem
+ffffffff81de7ac0 t gfx_v11_0_ring_get_rptr_gfx
+ffffffff81de7af0 t gfx_v11_0_ring_get_wptr_gfx
+ffffffff81de7c00 t gfx_v11_0_ring_set_wptr_gfx
+ffffffff81de7e10 t gfx_v11_0_ring_emit_ib_gfx
+ffffffff81de84a0 t gfx_v11_0_ring_emit_fence
+ffffffff81de8870 t gfx_v11_0_ring_emit_pipeline_sync
+ffffffff81de88d0 t gfx_v11_0_ring_emit_vm_flush
+ffffffff81de8aa0 t gfx_v11_0_ring_emit_hdp_flush
+ffffffff81de8b70 t gfx_v11_0_ring_emit_gds_switch
+ffffffff81de8c50 t gfx_v11_0_ring_emit_init_cond_exec
+ffffffff81de8e80 t gfx_v11_0_ring_emit_patch_cond_exec
+ffffffff81de8f40 t gfx_v11_0_ring_emit_cntxcntl
+ffffffff81de90a0 t gfx_v11_0_ring_emit_frame_cntl
+ffffffff81de91b0 t gfx_v11_0_ring_soft_recovery
+ffffffff81de9220 t gfx_v11_0_ring_preempt_ib
+ffffffff81de9390 t gfx_v11_0_emit_mem_sync
+ffffffff81de96c0 t gfx_v11_0_write_data_to_reg
+ffffffff81de98d0 t gfx_v11_0_set_eop_interrupt_state
+ffffffff81de9960 t gfx_v11_0_eop_irq
+ffffffff81de9b20 t gfx_v11_0_set_gfx_eop_interrupt_state
+ffffffff81de9cb0 t gfx_v11_0_set_compute_eop_interrupt_state
+ffffffff81de9e40 t gfx_v11_0_set_priv_reg_fault_state
+ffffffff81de9f60 t gfx_v11_0_priv_reg_irq
+ffffffff81de9fc0 t gfx_v11_0_handle_priv_fault
+ffffffff81dea130 t gfx_v11_0_set_priv_inst_fault_state
+ffffffff81dea250 t gfx_v11_0_priv_inst_irq
+ffffffff81dea2b0 t gfx_v11_0_is_rlc_enabled
+ffffffff81dea330 t gfx_v11_0_set_safe_mode
+ffffffff81dea480 t gfx_v11_0_unset_safe_mode
+ffffffff81dea4f0 t gfx_v11_0_rlc_init
+ffffffff81dea570 t gfx_v11_0_get_csb_size
+ffffffff81dea5a0 t gfx_v11_0_get_csb_buffer
+ffffffff81dea710 t gfx_v11_0_rlc_resume
+ffffffff81deb430 t gfx_v11_0_rlc_stop
+ffffffff81deb510 t gfx_v11_0_rlc_reset
+ffffffff81deb6b0 t gfx_v11_0_rlc_start
+ffffffff81deb850 t gfx_v11_0_update_spm_vmid
+ffffffff81deb950 t gfx_v11_0_init_csb
+ffffffff81debad0 t gfx_v11_0_gfx_mqd_init
+ffffffff81debea0 t gfx_v11_0_compute_mqd_init
+ffffffff81dec3c0 t gfx_v11_0_mec_init
+ffffffff81dec500 t gfx_v11_0_compute_ring_init
+ffffffff81dec640 t gfx_v11_0_init_toc_microcode
+ffffffff81dec7e0 t gfx_v11_0_rlc_autoload_buffer_init
+ffffffff81dec9d0 t gfx_v11_0_gpu_early_init
+ffffffff81deca70 t amdgpu_bo_unreserve
+ffffffff81decb50 t gfx_v11_0_get_gpu_clock_counter
+ffffffff81deceb0 t gfx_v11_0_select_se_sh
+ffffffff81decf50 t gfx_v11_0_read_wave_data
+ffffffff81ded190 t gfx_v11_0_read_wave_vgprs
+ffffffff81ded1c0 t gfx_v11_0_read_wave_sgprs
+ffffffff81ded240 t gfx_v11_0_select_me_pipe_q
+ffffffff81ded260 t gfx_v11_0_update_perf_clk
+ffffffff81ded390 t wave_read_ind
+ffffffff81ded470 t wave_read_regs
+ffffffff81ded5d0 t gfx_v11_0_disable_gpa_mode
+ffffffff81ded760 t gfx_v11_0_cp_resume
+ffffffff81df1690 t gfx_v11_0_config_me_cache
+ffffffff81df1a30 t gfx_v11_0_config_pfp_cache
+ffffffff81df1dd0 t gfx_v11_0_config_mec_cache
+ffffffff81df2170 t gfx_v11_0_enable_gui_idle_interrupt
+ffffffff81df2280 t gfx_v11_0_cp_compute_enable
+ffffffff81df2450 t gfx_v11_0_cp_gfx_enable
+ffffffff81df2640 t amdgpu_bo_reserve
+ffffffff81df27b0 t gfx_v11_0_kiq_init_register
+ffffffff81df3600 t gfx_v11_0_cp_gfx_switch_pipe
+ffffffff81df36e0 t gfx_v11_0_cp_gfx_set_doorbell
+ffffffff81df38c0 t gfx_v11_0_cp_gfx_start
+ffffffff81df4140 t gfx_v11_cntl_pg
 ffffffff81df5000 t gfx_v8_0_early_init
 ffffffff81df51f0 t gfx_v8_0_late_init
 ffffffff81df5920 t gfx_v8_0_sw_init
@@ -29689,92 +29689,92 @@ ffffffff81f13070 T amdgpu_dm_update_connector_after_de
 ffffffff81f135b0 T amdgpu_dm_update_freesync_caps
 ffffffff81f13ab0 T dm_atomic_get_state
 ffffffff81f13b20 T amdgpu_dm_connector_atomic_set_property
-ffffffff81f13bd0 T amdgpu_dm_connector_atomic_get_property
-ffffffff81f13c70 T amdgpu_dm_connector_funcs_reset
-ffffffff81f13d50 T amdgpu_dm_connector_atomic_duplicate_state
-ffffffff81f13e50 T create_validate_stream_for_sink
-ffffffff81f14b60 T amdgpu_dm_connector_mode_valid
-ffffffff81f14d10 T convert_dc_color_depth_into_bpc
-ffffffff81f14d50 t dm_encoder_helper_disable
-ffffffff81f14d80 t dm_encoder_helper_atomic_check
-ffffffff81f14f60 T amdgpu_dm_connector_init_helper
-ffffffff81f15220 T amdgpu_dm_get_encoder_crtc_mask
-ffffffff81f15270 T dm_restore_drm_connector_state
-ffffffff81f153e0 T amdgpu_dm_trigger_timing_sync
-ffffffff81f155b0 T dm_write_reg_func
-ffffffff81f155d0 T dm_read_reg_func
-ffffffff81f15670 T amdgpu_dm_process_dmub_aux_transfer_sync
-ffffffff81f15880 T amdgpu_dm_process_dmub_set_config_sync
-ffffffff81f159f0 T check_seamless_boot_capability
-ffffffff81f15a30 t dm_early_init
-ffffffff81f15c30 t dm_late_init
-ffffffff81f15f10 t dm_sw_init
-ffffffff81f166b0 t dm_sw_fini
-ffffffff81f167a0 t amdgpu_dm_early_fini
-ffffffff81f16800 t dm_hw_init
-ffffffff81f18560 t dm_hw_fini
-ffffffff81f185b0 t dm_suspend
-ffffffff81f18920 t dm_resume
-ffffffff81f19170 t dm_is_idle
-ffffffff81f191a0 t dm_wait_for_idle
-ffffffff81f191d0 t dm_check_soft_reset
-ffffffff81f19200 t dm_soft_reset
-ffffffff81f19230 t dm_set_clockgating_state
-ffffffff81f19260 t dm_set_powergating_state
-ffffffff81f19290 t dm_bandwidth_update
-ffffffff81f192c0 t dm_vblank_get_counter
-ffffffff81f19330 t dm_crtc_get_scanoutpos
-ffffffff81f193f0 t amdgpu_dm_dmub_reg_read
-ffffffff81f194a0 t amdgpu_dm_dmub_reg_write
-ffffffff81f194d0 t dm_dmub_hw_init
-ffffffff81f198a0 t dmub_aux_setconfig_callback
-ffffffff81f19950 t dmub_hpd_callback
-ffffffff81f19aa0 t amdgpu_dm_fini
-ffffffff81f19c70 t handle_hpd_irq_helper
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-ffffffff81f1b220 t dm_update_plane_state
-ffffffff81f1b7f0 t dm_update_crtc_state
-ffffffff81f1c0f0 t dm_check_crtc_cursor
-ffffffff81f1c460 t is_scaling_state_different
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-ffffffff81f1c770 t dm_update_mst_vcpi_slots_for_dsc
-ffffffff81f1c960 t dm_atomic_destroy_state
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-ffffffff81f1cb30 t fill_dc_plane_attributes
-ffffffff81f1cdc0 t fill_dc_plane_info_and_addr
-ffffffff81f1d0f0 t fill_hdr_info_packet
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-ffffffff81f1d5a0 t update_stream_scaling_settings
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-ffffffff81f20060 t amdgpu_dm_backlight_set_level
-ffffffff81f20240 t dm_atomic_duplicate_state
-ffffffff81f202e0 t dm_dmub_outbox1_low_irq
-ffffffff81f20550 t dm_handle_hpd_work
-ffffffff81f205c0 t amdgpu_dm_encoder_destroy
-ffffffff81f205f0 t amdgpu_dm_i2c_xfer
-ffffffff81f20740 t amdgpu_dm_i2c_func
-ffffffff81f20770 t amdgpu_dm_connector_detect
-ffffffff81f20830 t amdgpu_dm_connector_late_register
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-ffffffff81f208b0 t amdgpu_dm_connector_destroy
-ffffffff81f209d0 t get_modes
-ffffffff81f209e0 t amdgpu_dm_connector_atomic_check
-ffffffff81f20ae0 t amdgpu_dm_connector_get_modes
-ffffffff81f21040 t amdgpu_dm_backlight_update_status
-ffffffff81f210c0 t amdgpu_dm_backlight_get_brightness
-ffffffff81f212b0 t dm_crtc_high_irq
-ffffffff81f21450 t dm_vupdate_high_irq
-ffffffff81f215c0 t dm_pflip_high_irq
-ffffffff81f217c0 t handle_hpd_irq
-ffffffff81f217d0 t dm_gpureset_toggle_interrupts
-ffffffff81f219d0 t s3_handle_mst
-ffffffff81f21c30 t fill_stream_properties_from_drm_display_mode
+ffffffff81f13be0 T amdgpu_dm_connector_atomic_get_property
+ffffffff81f13c80 T amdgpu_dm_connector_funcs_reset
+ffffffff81f13d70 T amdgpu_dm_connector_atomic_duplicate_state
+ffffffff81f13e70 T create_validate_stream_for_sink
+ffffffff81f14b80 T amdgpu_dm_connector_mode_valid
+ffffffff81f14d30 T convert_dc_color_depth_into_bpc
+ffffffff81f14d70 t dm_encoder_helper_disable
+ffffffff81f14da0 t dm_encoder_helper_atomic_check
+ffffffff81f14f80 T amdgpu_dm_connector_init_helper
+ffffffff81f15240 T amdgpu_dm_get_encoder_crtc_mask
+ffffffff81f15290 T dm_restore_drm_connector_state
+ffffffff81f15400 T amdgpu_dm_trigger_timing_sync
+ffffffff81f155d0 T dm_write_reg_func
+ffffffff81f155f0 T dm_read_reg_func
+ffffffff81f15690 T amdgpu_dm_process_dmub_aux_transfer_sync
+ffffffff81f158a0 T amdgpu_dm_process_dmub_set_config_sync
+ffffffff81f15a10 T check_seamless_boot_capability
+ffffffff81f15a50 t dm_early_init
+ffffffff81f15c50 t dm_late_init
+ffffffff81f15f30 t dm_sw_init
+ffffffff81f166d0 t dm_sw_fini
+ffffffff81f167c0 t amdgpu_dm_early_fini
+ffffffff81f16820 t dm_hw_init
+ffffffff81f18580 t dm_hw_fini
+ffffffff81f185d0 t dm_suspend
+ffffffff81f18940 t dm_resume
+ffffffff81f19190 t dm_is_idle
+ffffffff81f191c0 t dm_wait_for_idle
+ffffffff81f191f0 t dm_check_soft_reset
+ffffffff81f19220 t dm_soft_reset
+ffffffff81f19250 t dm_set_clockgating_state
+ffffffff81f19280 t dm_set_powergating_state
+ffffffff81f192b0 t dm_bandwidth_update
+ffffffff81f192e0 t dm_vblank_get_counter
+ffffffff81f19350 t dm_crtc_get_scanoutpos
+ffffffff81f19410 t amdgpu_dm_dmub_reg_read
+ffffffff81f194c0 t amdgpu_dm_dmub_reg_write
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+ffffffff81f198c0 t dmub_aux_setconfig_callback
+ffffffff81f19970 t dmub_hpd_callback
+ffffffff81f19ac0 t amdgpu_dm_fini
+ffffffff81f19c90 t handle_hpd_irq_helper
+ffffffff81f19dc0 t handle_hpd_rx_irq
+ffffffff81f1a090 t emulated_link_detect
+ffffffff81f1a190 t schedule_hpd_rx_offload_work
+ffffffff81f1a240 t dm_handle_hpd_rx_offload_work
+ffffffff81f1a510 t amdgpu_dm_atomic_check
+ffffffff81f1b240 t dm_update_plane_state
+ffffffff81f1b810 t dm_update_crtc_state
+ffffffff81f1c110 t dm_check_crtc_cursor
+ffffffff81f1c480 t is_scaling_state_different
+ffffffff81f1c520 t do_aquire_global_lock
+ffffffff81f1c790 t dm_update_mst_vcpi_slots_for_dsc
+ffffffff81f1c980 t dm_atomic_destroy_state
+ffffffff81f1c9c0 t dm_check_cursor_fb
+ffffffff81f1cb50 t fill_dc_plane_attributes
+ffffffff81f1cde0 t fill_dc_plane_info_and_addr
+ffffffff81f1d110 t fill_hdr_info_packet
+ffffffff81f1d270 t is_timing_unchanged_for_freesync
+ffffffff81f1d3a0 t is_freesync_video_mode
+ffffffff81f1d490 t get_highest_refresh_rate_mode
+ffffffff81f1d5c0 t update_stream_scaling_settings
+ffffffff81f1d700 t amdgpu_dm_atomic_commit_tail
+ffffffff81f20080 t amdgpu_dm_backlight_set_level
+ffffffff81f20260 t dm_atomic_duplicate_state
+ffffffff81f20300 t dm_dmub_outbox1_low_irq
+ffffffff81f20570 t dm_handle_hpd_work
+ffffffff81f205e0 t amdgpu_dm_encoder_destroy
+ffffffff81f20610 t amdgpu_dm_i2c_xfer
+ffffffff81f20760 t amdgpu_dm_i2c_func
+ffffffff81f20790 t amdgpu_dm_connector_detect
+ffffffff81f20850 t amdgpu_dm_connector_late_register
+ffffffff81f208b0 t amdgpu_dm_connector_unregister
+ffffffff81f208d0 t amdgpu_dm_connector_destroy
+ffffffff81f209f0 t get_modes
+ffffffff81f20a00 t amdgpu_dm_connector_atomic_check
+ffffffff81f20b00 t amdgpu_dm_connector_get_modes
+ffffffff81f21060 t amdgpu_dm_backlight_update_status
+ffffffff81f210e0 t amdgpu_dm_backlight_get_brightness
+ffffffff81f212d0 t dm_crtc_high_irq
+ffffffff81f21470 t dm_vupdate_high_irq
+ffffffff81f215e0 t dm_pflip_high_irq
+ffffffff81f217e0 t handle_hpd_irq
+ffffffff81f217f0 t dm_gpureset_toggle_interrupts
+ffffffff81f219f0 t s3_handle_mst
+ffffffff81f21c50 t fill_stream_properties_from_drm_display_mode
 ffffffff81f23000 T amdgpu_dm_init_color_mod
 ffffffff81f23010 T amdgpu_dm_verify_lut_sizes
 ffffffff81f230e0 T amdgpu_dm_update_crtc_color_mgmt
@@ -31336,7 +31336,7 @@ ffffffff81ffd000 T cm_helper_program_color_matrices
 ffffffff81ffd0c0 T cm_helper_program_xfer_func
 ffffffff81ffd480 T cm_helper_convert_to_custom_float
 ffffffff81ffd8d0 T cm_helper_translate_curve_to_hw_format
-ffffffff81ffe430 T cm_helper_translate_curve_to_degamma_hw_format
+ffffffff81ffe490 T cm_helper_translate_curve_to_degamma_hw_format
 ffffffff81fff000 T dpp_read_state
 ffffffff81fff260 T dpp1_get_optimal_number_of_taps
 ffffffff81fff400 T dpp_reset
@@ -31445,42 +31445,42 @@ ffffffff82010180 T dcn10_reset_hw_ctx_wrap
 ffffffff820104d0 T dcn10_update_plane_addr
 ffffffff820105f0 T dcn10_set_input_transfer_func
 ffffffff82010760 T dcn10_set_output_transfer_func
-ffffffff82010820 T dcn10_pipe_control_lock
-ffffffff820108f0 T dcn10_cursor_lock
-ffffffff82010ab0 T dcn10_enable_vblanks_synchronization
-ffffffff82011220 T dcn10_enable_timing_synchronization
-ffffffff82011620 T dcn10_enable_per_frame_crtc_position_reset
-ffffffff820117f0 T dcn10_program_gamut_remap
-ffffffff820119f0 T dcn10_program_output_csc
-ffffffff82011b20 T dcn10_update_visual_confirm_color
-ffffffff82011c20 T dcn10_update_mpcc
-ffffffff82011ee0 T dcn10_blank_pixel_data
-ffffffff82012020 T dcn10_set_hdr_multiplier
-ffffffff820120b0 T dcn10_program_pipe
-ffffffff82012c50 T dcn10_wait_for_pending_cleared
-ffffffff82012d50 T dcn10_post_unlock_program_front_end
-ffffffff82012ff0 T dcn10_prepare_bandwidth
-ffffffff820131a0 T dcn10_optimize_bandwidth
-ffffffff82013350 T dcn10_set_drr
-ffffffff82013450 T dcn10_get_position
-ffffffff820134e0 T dcn10_set_static_screen_control
-ffffffff82013580 T dcn10_setup_stereo
-ffffffff820136c0 T dcn10_wait_for_mpcc_disconnect
-ffffffff82013870 T dcn10_dummy_display_power_gating
-ffffffff820138a0 T dcn10_update_pending_status
-ffffffff820139e0 T dcn10_update_dchub
-ffffffff82013a10 T dcn10_set_cursor_position
-ffffffff82013f50 T dcn10_set_cursor_attribute
-ffffffff82013fa0 T dcn10_set_cursor_sdr_white_level
-ffffffff82014060 T dcn10_get_vupdate_offset_from_vsync
-ffffffff820140f0 T dcn10_calc_vupdate_position
-ffffffff82014180 T dcn10_setup_periodic_interrupt
-ffffffff82014290 T dcn10_setup_vupdate_interrupt
-ffffffff82014350 T dcn10_unblank_stream
-ffffffff82014460 T dcn10_send_immediate_sdp_message
-ffffffff820144c0 T dcn10_set_clock
-ffffffff820145d0 T dcn10_get_clock
-ffffffff82014630 T dcn10_get_dcc_en_bits
+ffffffff82010830 T dcn10_pipe_control_lock
+ffffffff82010900 T dcn10_cursor_lock
+ffffffff82010ac0 T dcn10_enable_vblanks_synchronization
+ffffffff82011230 T dcn10_enable_timing_synchronization
+ffffffff82011630 T dcn10_enable_per_frame_crtc_position_reset
+ffffffff82011800 T dcn10_program_gamut_remap
+ffffffff82011a00 T dcn10_program_output_csc
+ffffffff82011b30 T dcn10_update_visual_confirm_color
+ffffffff82011c30 T dcn10_update_mpcc
+ffffffff82011ef0 T dcn10_blank_pixel_data
+ffffffff82012030 T dcn10_set_hdr_multiplier
+ffffffff820120c0 T dcn10_program_pipe
+ffffffff82012c60 T dcn10_wait_for_pending_cleared
+ffffffff82012d60 T dcn10_post_unlock_program_front_end
+ffffffff82013000 T dcn10_prepare_bandwidth
+ffffffff820131b0 T dcn10_optimize_bandwidth
+ffffffff82013360 T dcn10_set_drr
+ffffffff82013460 T dcn10_get_position
+ffffffff820134f0 T dcn10_set_static_screen_control
+ffffffff82013590 T dcn10_setup_stereo
+ffffffff820136d0 T dcn10_wait_for_mpcc_disconnect
+ffffffff82013880 T dcn10_dummy_display_power_gating
+ffffffff820138b0 T dcn10_update_pending_status
+ffffffff820139f0 T dcn10_update_dchub
+ffffffff82013a20 T dcn10_set_cursor_position
+ffffffff82013f60 T dcn10_set_cursor_attribute
+ffffffff82013fb0 T dcn10_set_cursor_sdr_white_level
+ffffffff82014070 T dcn10_get_vupdate_offset_from_vsync
+ffffffff82014100 T dcn10_calc_vupdate_position
+ffffffff82014190 T dcn10_setup_periodic_interrupt
+ffffffff820142a0 T dcn10_setup_vupdate_interrupt
+ffffffff82014360 T dcn10_unblank_stream
+ffffffff82014470 T dcn10_send_immediate_sdp_message
+ffffffff820144d0 T dcn10_set_clock
+ffffffff820145e0 T dcn10_get_clock
+ffffffff82014640 T dcn10_get_dcc_en_bits
 ffffffff82015000 T snprintf_count
 ffffffff82015090 T dcn10_clear_status_bits
 ffffffff82015240 T dcn10_get_hw_state
@@ -31748,37 +31748,37 @@ ffffffff82040630 T dcn20_blank_pixel_data
 ffffffff82040830 T dcn20_enable_stream_timing
 ffffffff82040dd0 T dcn20_program_output_csc
 ffffffff82040ec0 T dcn20_set_output_transfer_func
-ffffffff82041030 T dcn20_set_blend_lut
-ffffffff820410a0 T dcn20_set_shaper_3dlut
-ffffffff82041160 T dcn20_set_input_transfer_func
-ffffffff82041320 T dcn20_update_odm
-ffffffff82041410 T dcn20_pipe_control_lock
-ffffffff82041730 T dcn20_program_front_end_for_ctx
-ffffffff82042230 t dcn20_program_pipe
-ffffffff82042ce0 T dcn20_post_unlock_program_front_end
-ffffffff82043030 T dcn20_prepare_bandwidth
-ffffffff82043180 T dcn20_optimize_bandwidth
-ffffffff82043350 T dcn20_update_bandwidth
-ffffffff82043610 T dcn20_enable_writeback
-ffffffff82043760 T dcn20_disable_writeback
-ffffffff820437f0 T dcn20_wait_for_blank_complete
-ffffffff82043880 T dcn20_dmdata_status_done
-ffffffff820438d0 T dcn20_disable_stream_gating
-ffffffff82043980 T dcn20_enable_stream_gating
-ffffffff82043a20 T dcn20_set_dmdata_attributes
-ffffffff82043ae0 T dcn20_init_vm_ctx
-ffffffff82043ba0 T dcn20_init_sys_ctx
-ffffffff82043c50 T dcn20_update_plane_addr
-ffffffff82043d90 T dcn20_unblank_stream
-ffffffff82043f20 T dcn20_setup_vupdate_interrupt
-ffffffff82043f90 T dcn20_reset_hw_ctx_wrap
-ffffffff82044350 T dcn20_update_visual_confirm_color
-ffffffff82044460 T dcn20_update_mpcc
-ffffffff820446d0 T dcn20_enable_stream
-ffffffff820448a0 T dcn20_program_dmdata_engine
-ffffffff82044940 T dcn20_fpga_init_hw
-ffffffff82044f20 T dcn20_optimize_timing_for_fsft
-ffffffff82044f60 T dcn20_set_disp_pattern_generator
+ffffffff82041040 T dcn20_set_blend_lut
+ffffffff820410b0 T dcn20_set_shaper_3dlut
+ffffffff82041170 T dcn20_set_input_transfer_func
+ffffffff82041330 T dcn20_update_odm
+ffffffff82041420 T dcn20_pipe_control_lock
+ffffffff82041740 T dcn20_program_front_end_for_ctx
+ffffffff82042240 t dcn20_program_pipe
+ffffffff82042cf0 T dcn20_post_unlock_program_front_end
+ffffffff82043040 T dcn20_prepare_bandwidth
+ffffffff82043190 T dcn20_optimize_bandwidth
+ffffffff82043360 T dcn20_update_bandwidth
+ffffffff82043620 T dcn20_enable_writeback
+ffffffff82043770 T dcn20_disable_writeback
+ffffffff82043800 T dcn20_wait_for_blank_complete
+ffffffff82043890 T dcn20_dmdata_status_done
+ffffffff820438e0 T dcn20_disable_stream_gating
+ffffffff82043990 T dcn20_enable_stream_gating
+ffffffff82043a30 T dcn20_set_dmdata_attributes
+ffffffff82043af0 T dcn20_init_vm_ctx
+ffffffff82043bb0 T dcn20_init_sys_ctx
+ffffffff82043c60 T dcn20_update_plane_addr
+ffffffff82043da0 T dcn20_unblank_stream
+ffffffff82043f30 T dcn20_setup_vupdate_interrupt
+ffffffff82043fa0 T dcn20_reset_hw_ctx_wrap
+ffffffff82044360 T dcn20_update_visual_confirm_color
+ffffffff82044470 T dcn20_update_mpcc
+ffffffff820446e0 T dcn20_enable_stream
+ffffffff820448b0 T dcn20_program_dmdata_engine
+ffffffff82044950 T dcn20_fpga_init_hw
+ffffffff82044f30 T dcn20_optimize_timing_for_fsft
+ffffffff82044f70 T dcn20_set_disp_pattern_generator
 ffffffff82045000 T dcn20_hw_sequencer_construct
 ffffffff82046000 T enc2_fec_set_enable
 ffffffff82046090 T enc2_fec_set_ready
@@ -32067,21 +32067,21 @@ ffffffff82082520 T hubp3_construct
 ffffffff82083000 T dcn30_set_blend_lut
 ffffffff82083070 T dcn30_set_input_transfer_func
 ffffffff820831d0 T dcn30_set_output_transfer_func
-ffffffff820834f0 T dcn30_update_writeback
-ffffffff82083580 t dcn30_set_writeback
-ffffffff82083730 T dcn30_mmhubbub_warmup
-ffffffff82083980 T dcn30_enable_writeback
-ffffffff82083a50 T dcn30_disable_writeback
-ffffffff82083b30 T dcn30_program_all_writeback_pipes_in_tree
-ffffffff82083e30 T dcn30_init_hw
-ffffffff820846b0 T dcn30_set_avmute
-ffffffff82084710 T dcn30_update_info_frame
-ffffffff820847e0 T dcn30_program_dmdata_engine
-ffffffff82084880 T dcn30_apply_idle_power_optimizations
-ffffffff82084e00 T dcn30_does_plane_fit_in_mall
-ffffffff82084eb0 T dcn30_hardware_release
-ffffffff82084fa0 T dcn30_set_disp_pattern_generator
-ffffffff82085010 T dcn30_prepare_bandwidth
+ffffffff82083500 T dcn30_update_writeback
+ffffffff82083590 t dcn30_set_writeback
+ffffffff82083740 T dcn30_mmhubbub_warmup
+ffffffff82083990 T dcn30_enable_writeback
+ffffffff82083a60 T dcn30_disable_writeback
+ffffffff82083b40 T dcn30_program_all_writeback_pipes_in_tree
+ffffffff82083e40 T dcn30_init_hw
+ffffffff820846c0 T dcn30_set_avmute
+ffffffff82084720 T dcn30_update_info_frame
+ffffffff820847f0 T dcn30_program_dmdata_engine
+ffffffff82084890 T dcn30_apply_idle_power_optimizations
+ffffffff82084e10 T dcn30_does_plane_fit_in_mall
+ffffffff82084ec0 T dcn30_hardware_release
+ffffffff82084fb0 T dcn30_set_disp_pattern_generator
+ffffffff82085020 T dcn30_prepare_bandwidth
 ffffffff82086000 T dcn30_hw_sequencer_construct
 ffffffff82087000 t mmhubbub3_warmup_mcif
 ffffffff82087210 t mmhubbub3_config_mcif_buf
@@ -32583,21 +32583,21 @@ ffffffff8212b450 T dcn_bw_notify_pplib_of_wm_ranges
 ffffffff8212c000 T dcn20_populate_dml_writeback_from_context
 ffffffff8212c180 T dcn20_fpu_set_wb_arb_params
 ffffffff8212c330 T dcn20_calculate_dlg_params
-ffffffff8212cb40 T dcn20_populate_dml_pipes_from_context
-ffffffff8212d9e0 T dcn20_calculate_wm
-ffffffff8212e1d0 T dcn20_update_bounding_box
-ffffffff8212e450 T dcn20_cap_soc_clocks
-ffffffff8212e7b0 T dcn20_patch_bounding_box
-ffffffff8212e920 T dcn20_validate_bandwidth_fp
-ffffffff8212eac0 t dcn20_validate_bandwidth_internal
-ffffffff8212eec0 T dcn20_fpu_set_wm_ranges
-ffffffff8212ef60 T dcn20_fpu_adjust_dppclk
-ffffffff8212f000 T dcn21_populate_dml_pipes_from_context
-ffffffff8212f110 T dcn21_validate_bandwidth_fp
-ffffffff8212fb90 T dcn21_update_bw_bounding_box
-ffffffff8212ffa0 T dcn21_clk_mgr_set_bw_params_wm_table
-ffffffff82130000 T dcn201_populate_dml_writeback_from_context_fpu
-ffffffff82130300 t calculate_wm_set_for_vlevel
+ffffffff8212cb00 T dcn20_populate_dml_pipes_from_context
+ffffffff8212d9a0 T dcn20_calculate_wm
+ffffffff8212e190 T dcn20_update_bounding_box
+ffffffff8212e410 T dcn20_cap_soc_clocks
+ffffffff8212e770 T dcn20_patch_bounding_box
+ffffffff8212e8e0 T dcn20_validate_bandwidth_fp
+ffffffff8212ea80 t dcn20_validate_bandwidth_internal
+ffffffff8212ee80 T dcn20_fpu_set_wm_ranges
+ffffffff8212ef20 T dcn20_fpu_adjust_dppclk
+ffffffff8212efc0 T dcn21_populate_dml_pipes_from_context
+ffffffff8212f0d0 T dcn21_validate_bandwidth_fp
+ffffffff8212fb50 T dcn21_update_bw_bounding_box
+ffffffff8212ff60 T dcn21_clk_mgr_set_bw_params_wm_table
+ffffffff8212ffc0 T dcn201_populate_dml_writeback_from_context_fpu
+ffffffff821302c0 t calculate_wm_set_for_vlevel
 ffffffff82131000 T dml20_recalculate
 ffffffff82131740 t dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
 ffffffff82136bf0 T dml20_ModeSupportAndSystemConfigurationFull
@@ -32754,11 +32754,11 @@ ffffffff821c45e0 T insert_entry_into_table_sorted
 ffffffff821c4a30 T dcn32_set_phantom_stream_timing
 ffffffff821c4cd0 t dcn32_split_stream_for_mpc_or_odm
 ffffffff821c5080 T dcn32_calculate_wm_and_dlg_fpu
-ffffffff821c6600 T dcn32_patch_dpm_table
-ffffffff821c6810 T dcn32_update_bw_bounding_box_fpu
-ffffffff821c7fa0 T dcn32_zero_pipe_dcc_fraction
-ffffffff821c8000 T dcn32_allow_subvp_with_active_margin
-ffffffff821c80d0 t subvp_drr_schedulable
+ffffffff821c6610 T dcn32_patch_dpm_table
+ffffffff821c6820 T dcn32_update_bw_bounding_box_fpu
+ffffffff821c7fb0 T dcn32_zero_pipe_dcc_fraction
+ffffffff821c8010 T dcn32_allow_subvp_with_active_margin
+ffffffff821c80e0 t subvp_drr_schedulable
 ffffffff821c9000 T dml32_recalculate
 ffffffff821cd300 T dml32_ModeSupportAndSystemConfigurationFull
 ffffffff821d5000 T dml32_dscceComputeDelay
@@ -33240,24 +33240,25 @@ ffffffff82232210 T dmub_dcn20_reset_release
 ffffffff822322e0 T dmub_dcn20_backdoor_load
 ffffffff82232590 T dmub_dcn20_setup_windows
 ffffffff82232af0 T dmub_dcn20_setup_mailbox
-ffffffff82232b50 T dmub_dcn20_get_inbox1_rptr
-ffffffff82232b80 T dmub_dcn20_set_inbox1_wptr
-ffffffff82232bb0 T dmub_dcn20_setup_out_mailbox
-ffffffff82232c10 T dmub_dcn20_get_outbox1_wptr
-ffffffff82232c40 T dmub_dcn20_set_outbox1_rptr
-ffffffff82232c70 T dmub_dcn20_setup_outbox0
-ffffffff82232cc0 T dmub_dcn20_get_outbox0_wptr
-ffffffff82232cf0 T dmub_dcn20_set_outbox0_rptr
-ffffffff82232d20 T dmub_dcn20_is_hw_init
-ffffffff82232d80 T dmub_dcn20_is_supported
-ffffffff82232de0 T dmub_dcn20_set_gpint
-ffffffff82232e10 T dmub_dcn20_is_gpint_acked
-ffffffff82232e70 T dmub_dcn20_get_gpint_response
-ffffffff82232ea0 T dmub_dcn20_get_fw_boot_status
-ffffffff82232ed0 T dmub_dcn20_enable_dmub_boot_options
-ffffffff82232f00 T dmub_dcn20_skip_dmub_panel_power_sequence
-ffffffff82232f60 T dmub_dcn20_get_current_time
-ffffffff82232f90 T dmub_dcn20_get_diagnostic_data
+ffffffff82232b50 T dmub_dcn20_get_inbox1_wptr
+ffffffff82232b80 T dmub_dcn20_get_inbox1_rptr
+ffffffff82232bb0 T dmub_dcn20_set_inbox1_wptr
+ffffffff82232be0 T dmub_dcn20_setup_out_mailbox
+ffffffff82232c40 T dmub_dcn20_get_outbox1_wptr
+ffffffff82232c70 T dmub_dcn20_set_outbox1_rptr
+ffffffff82232ca0 T dmub_dcn20_setup_outbox0
+ffffffff82232cf0 T dmub_dcn20_get_outbox0_wptr
+ffffffff82232d20 T dmub_dcn20_set_outbox0_rptr
+ffffffff82232d50 T dmub_dcn20_is_hw_init
+ffffffff82232db0 T dmub_dcn20_is_supported
+ffffffff82232e10 T dmub_dcn20_set_gpint
+ffffffff82232e40 T dmub_dcn20_is_gpint_acked
+ffffffff82232ea0 T dmub_dcn20_get_gpint_response
+ffffffff82232ed0 T dmub_dcn20_get_fw_boot_status
+ffffffff82232f00 T dmub_dcn20_enable_dmub_boot_options
+ffffffff82232f30 T dmub_dcn20_skip_dmub_panel_power_sequence
+ffffffff82232f90 T dmub_dcn20_get_current_time
+ffffffff82232fc0 T dmub_dcn20_get_diagnostic_data
 ffffffff82234000 T dmub_dcn21_is_phy_init
 ffffffff82235000 T dmub_dcn30_backdoor_load
 ffffffff82235270 T dmub_dcn30_setup_windows
@@ -33266,27 +33267,28 @@ ffffffff82236280 T dmub_dcn31_reset_release
 ffffffff82236350 T dmub_dcn31_backdoor_load
 ffffffff822365c0 T dmub_dcn31_setup_windows
 ffffffff82236910 T dmub_dcn31_setup_mailbox
-ffffffff82236960 T dmub_dcn31_get_inbox1_rptr
-ffffffff82236990 T dmub_dcn31_set_inbox1_wptr
-ffffffff822369c0 T dmub_dcn31_setup_out_mailbox
-ffffffff82236a10 T dmub_dcn31_get_outbox1_wptr
-ffffffff82236a40 T dmub_dcn31_set_outbox1_rptr
-ffffffff82236a70 T dmub_dcn31_is_hw_init
-ffffffff82236af0 T dmub_dcn31_is_supported
-ffffffff82236b50 T dmub_dcn31_is_psrsu_supported
-ffffffff82236b80 T dmub_dcn31_set_gpint
-ffffffff82236bb0 T dmub_dcn31_is_gpint_acked
-ffffffff82236c10 T dmub_dcn31_get_gpint_response
-ffffffff82236c40 T dmub_dcn31_get_gpint_dataout
-ffffffff82236d60 T dmub_dcn31_get_fw_boot_status
-ffffffff82236d90 T dmub_dcn31_enable_dmub_boot_options
-ffffffff82236e10 T dmub_dcn31_skip_dmub_panel_power_sequence
-ffffffff82236e70 T dmub_dcn31_setup_outbox0
-ffffffff82236ec0 T dmub_dcn31_get_outbox0_wptr
-ffffffff82236ef0 T dmub_dcn31_set_outbox0_rptr
-ffffffff82236f20 T dmub_dcn31_get_current_time
-ffffffff82236f50 T dmub_dcn31_get_diagnostic_data
-ffffffff82237400 T dmub_dcn31_should_detect
+ffffffff82236960 T dmub_dcn31_get_inbox1_wptr
+ffffffff82236990 T dmub_dcn31_get_inbox1_rptr
+ffffffff822369c0 T dmub_dcn31_set_inbox1_wptr
+ffffffff822369f0 T dmub_dcn31_setup_out_mailbox
+ffffffff82236a40 T dmub_dcn31_get_outbox1_wptr
+ffffffff82236a70 T dmub_dcn31_set_outbox1_rptr
+ffffffff82236aa0 T dmub_dcn31_is_hw_init
+ffffffff82236b20 T dmub_dcn31_is_supported
+ffffffff82236b80 T dmub_dcn31_is_psrsu_supported
+ffffffff82236bb0 T dmub_dcn31_set_gpint
+ffffffff82236be0 T dmub_dcn31_is_gpint_acked
+ffffffff82236c40 T dmub_dcn31_get_gpint_response
+ffffffff82236c70 T dmub_dcn31_get_gpint_dataout
+ffffffff82236d90 T dmub_dcn31_get_fw_boot_status
+ffffffff82236dc0 T dmub_dcn31_enable_dmub_boot_options
+ffffffff82236e40 T dmub_dcn31_skip_dmub_panel_power_sequence
+ffffffff82236ea0 T dmub_dcn31_setup_outbox0
+ffffffff82236ef0 T dmub_dcn31_get_outbox0_wptr
+ffffffff82236f20 T dmub_dcn31_set_outbox0_rptr
+ffffffff82236f50 T dmub_dcn31_get_current_time
+ffffffff82236f80 T dmub_dcn31_get_diagnostic_data
+ffffffff82237430 T dmub_dcn31_should_detect
 ffffffff82238000 T dmub_dcn314_is_psrsu_supported
 ffffffff82239000 T dmub_dcn32_reset
 ffffffff82239200 T dmub_dcn32_reset_release
@@ -33294,57 +33296,59 @@ ffffffff822392d0 T dmub_dcn32_backdoor_load
 ffffffff82239540 T dmub_dcn32_backdoor_load_zfb_mode
 ffffffff82239730 T dmub_dcn32_setup_windows
 ffffffff82239a80 T dmub_dcn32_setup_mailbox
-ffffffff82239ad0 T dmub_dcn32_get_inbox1_rptr
-ffffffff82239b00 T dmub_dcn32_set_inbox1_wptr
-ffffffff82239b30 T dmub_dcn32_setup_out_mailbox
-ffffffff82239b80 T dmub_dcn32_get_outbox1_wptr
-ffffffff82239bb0 T dmub_dcn32_set_outbox1_rptr
-ffffffff82239be0 T dmub_dcn32_is_hw_init
-ffffffff82239c60 T dmub_dcn32_is_supported
-ffffffff82239cc0 T dmub_dcn32_set_gpint
-ffffffff82239cf0 T dmub_dcn32_is_gpint_acked
-ffffffff82239d50 T dmub_dcn32_get_gpint_response
-ffffffff82239d80 T dmub_dcn32_get_gpint_dataout
-ffffffff82239ea0 T dmub_dcn32_get_fw_boot_status
-ffffffff82239ed0 T dmub_dcn32_enable_dmub_boot_options
-ffffffff82239f00 T dmub_dcn32_skip_dmub_panel_power_sequence
-ffffffff82239f60 T dmub_dcn32_setup_outbox0
-ffffffff82239fb0 T dmub_dcn32_get_outbox0_wptr
-ffffffff82239fe0 T dmub_dcn32_set_outbox0_rptr
-ffffffff8223a010 T dmub_dcn32_get_current_time
-ffffffff8223a040 T dmub_dcn32_get_diagnostic_data
-ffffffff8223a4f0 T dmub_dcn32_configure_dmub_in_system_memory
-ffffffff8223a520 T dmub_dcn32_send_inbox0_cmd
-ffffffff8223a550 T dmub_dcn32_clear_inbox0_ack_register
-ffffffff8223a580 T dmub_dcn32_read_inbox0_ack_register
+ffffffff82239ad0 T dmub_dcn32_get_inbox1_wptr
+ffffffff82239b00 T dmub_dcn32_get_inbox1_rptr
+ffffffff82239b30 T dmub_dcn32_set_inbox1_wptr
+ffffffff82239b60 T dmub_dcn32_setup_out_mailbox
+ffffffff82239bb0 T dmub_dcn32_get_outbox1_wptr
+ffffffff82239be0 T dmub_dcn32_set_outbox1_rptr
+ffffffff82239c10 T dmub_dcn32_is_hw_init
+ffffffff82239c90 T dmub_dcn32_is_supported
+ffffffff82239cf0 T dmub_dcn32_set_gpint
+ffffffff82239d20 T dmub_dcn32_is_gpint_acked
+ffffffff82239d80 T dmub_dcn32_get_gpint_response
+ffffffff82239db0 T dmub_dcn32_get_gpint_dataout
+ffffffff82239ed0 T dmub_dcn32_get_fw_boot_status
+ffffffff82239f00 T dmub_dcn32_enable_dmub_boot_options
+ffffffff82239f30 T dmub_dcn32_skip_dmub_panel_power_sequence
+ffffffff82239f90 T dmub_dcn32_setup_outbox0
+ffffffff82239fe0 T dmub_dcn32_get_outbox0_wptr
+ffffffff8223a010 T dmub_dcn32_set_outbox0_rptr
+ffffffff8223a040 T dmub_dcn32_get_current_time
+ffffffff8223a070 T dmub_dcn32_get_diagnostic_data
+ffffffff8223a520 T dmub_dcn32_configure_dmub_in_system_memory
+ffffffff8223a550 T dmub_dcn32_send_inbox0_cmd
+ffffffff8223a580 T dmub_dcn32_clear_inbox0_ack_register
+ffffffff8223a5b0 T dmub_dcn32_read_inbox0_ack_register
 ffffffff8223b000 T dmub_reg_update
 ffffffff8223b150 T dmub_reg_set
 ffffffff8223b2b0 T dmub_reg_get
 ffffffff8223c000 T dmub_flush_buffer_mem
 ffffffff8223c030 T dmub_srv_create
-ffffffff8223c580 T dmub_srv_destroy
-ffffffff8223c5a0 T dmub_srv_calc_region_info
-ffffffff8223c990 T dmub_srv_calc_mem_info
-ffffffff8223cb50 T dmub_srv_has_hw_support
-ffffffff8223cbc0 T dmub_srv_is_hw_init
-ffffffff8223cc40 T dmub_srv_hw_init
-ffffffff8223d090 T dmub_srv_hw_reset
-ffffffff8223d120 T dmub_srv_cmd_queue
-ffffffff8223d220 T dmub_srv_cmd_execute
-ffffffff8223d2e0 T dmub_srv_wait_for_auto_load
-ffffffff8223d380 T dmub_srv_wait_for_phy_init
-ffffffff8223d430 T dmub_srv_wait_for_idle
-ffffffff8223d4e0 T dmub_srv_send_gpint_command
-ffffffff8223d5d0 T dmub_srv_get_gpint_response
-ffffffff8223d630 T dmub_srv_get_gpint_dataout
-ffffffff8223d690 T dmub_srv_get_fw_boot_status
-ffffffff8223d700 T dmub_srv_cmd_with_reply_data
-ffffffff8223d970 T dmub_srv_get_outbox0_msg
-ffffffff8223da10 T dmub_srv_get_diagnostic_data
-ffffffff8223da60 T dmub_srv_should_detect
-ffffffff8223dab0 T dmub_srv_clear_inbox0_ack
-ffffffff8223db00 T dmub_srv_wait_for_inbox0_ack
-ffffffff8223dba0 T dmub_srv_send_inbox0_cmd
+ffffffff8223c5b0 T dmub_srv_destroy
+ffffffff8223c5d0 T dmub_srv_calc_region_info
+ffffffff8223c9c0 T dmub_srv_calc_mem_info
+ffffffff8223cb80 T dmub_srv_has_hw_support
+ffffffff8223cbf0 T dmub_srv_is_hw_init
+ffffffff8223cc70 T dmub_srv_hw_init
+ffffffff8223d0c0 T dmub_srv_sync_inbox1
+ffffffff8223d170 T dmub_srv_hw_reset
+ffffffff8223d200 T dmub_srv_cmd_queue
+ffffffff8223d300 T dmub_srv_cmd_execute
+ffffffff8223d3c0 T dmub_srv_wait_for_auto_load
+ffffffff8223d460 T dmub_srv_wait_for_phy_init
+ffffffff8223d510 T dmub_srv_wait_for_idle
+ffffffff8223d5c0 T dmub_srv_send_gpint_command
+ffffffff8223d6b0 T dmub_srv_get_gpint_response
+ffffffff8223d710 T dmub_srv_get_gpint_dataout
+ffffffff8223d770 T dmub_srv_get_fw_boot_status
+ffffffff8223d7e0 T dmub_srv_cmd_with_reply_data
+ffffffff8223da40 T dmub_srv_get_outbox0_msg
+ffffffff8223dae0 T dmub_srv_get_diagnostic_data
+ffffffff8223db30 T dmub_srv_should_detect
+ffffffff8223db80 T dmub_srv_clear_inbox0_ack
+ffffffff8223dbd0 T dmub_srv_wait_for_inbox0_ack
+ffffffff8223dc80 T dmub_srv_send_inbox0_cmd
 ffffffff8223e000 T dmub_srv_stat_get_notification
 ffffffff8223f000 T setup_x_points_distribution
 ffffffff8223f170 T log_x_points_distribution
@@ -34753,26 +34757,26 @@ ffffffff822ef000 t aldebaran_i2c_control_init
 ffffffff822ef0c0 t aldebaran_i2c_control_fini
 ffffffff822ef100 t aldebaran_get_unique_id
 ffffffff822ef1e0 t aldebaran_init_smc_tables
-ffffffff822ef370 t aldebaran_set_mp1_state
-ffffffff822ef3b0 t aldebaran_setup_pptable
-ffffffff822ef480 t aldebaran_system_features_control
-ffffffff822ef5e0 t aldebaran_set_power_limit
-ffffffff822ef670 t aldebaran_is_baco_supported
-ffffffff822ef6a0 t aldebaran_is_mode1_reset_supported
-ffffffff822ef6d0 t aldebaran_is_mode2_reset_supported
-ffffffff822ef700 t aldebaran_mode1_reset
-ffffffff822ef7e0 t aldebaran_mode2_reset
-ffffffff822efb00 t aldebaran_set_soft_freq_limited_range
-ffffffff822efd00 t aldebaran_log_thermal_throttling_event
-ffffffff822f0010 t aldebaran_get_gpu_metrics
-ffffffff822f0290 t aldebaran_smu_handle_passthrough_sbr
-ffffffff822f02b0 t aldebaran_smu_send_hbm_bad_page_num
-ffffffff822f0330 t aldebaran_get_ecc_info
-ffffffff822f0490 t aldebaran_send_hbm_bad_channel_flag
-ffffffff822f0560 t aldebaran_get_current_clk_freq_by_table
-ffffffff822f0730 t aldebaran_upload_dpm_level
-ffffffff822f0820 t aldebaran_i2c_xfer
-ffffffff822f0ac0 t aldebaran_i2c_func
+ffffffff822ef3a0 t aldebaran_set_mp1_state
+ffffffff822ef3e0 t aldebaran_setup_pptable
+ffffffff822ef4b0 t aldebaran_system_features_control
+ffffffff822ef610 t aldebaran_set_power_limit
+ffffffff822ef6a0 t aldebaran_is_baco_supported
+ffffffff822ef6d0 t aldebaran_is_mode1_reset_supported
+ffffffff822ef700 t aldebaran_is_mode2_reset_supported
+ffffffff822ef730 t aldebaran_mode1_reset
+ffffffff822ef810 t aldebaran_mode2_reset
+ffffffff822efb30 t aldebaran_set_soft_freq_limited_range
+ffffffff822efd30 t aldebaran_log_thermal_throttling_event
+ffffffff822f0040 t aldebaran_get_gpu_metrics
+ffffffff822f02c0 t aldebaran_smu_handle_passthrough_sbr
+ffffffff822f02e0 t aldebaran_smu_send_hbm_bad_page_num
+ffffffff822f0360 t aldebaran_get_ecc_info
+ffffffff822f04c0 t aldebaran_send_hbm_bad_channel_flag
+ffffffff822f0590 t aldebaran_get_current_clk_freq_by_table
+ffffffff822f0760 t aldebaran_upload_dpm_level
+ffffffff822f0850 t aldebaran_i2c_xfer
+ffffffff822f0af0 t aldebaran_i2c_func
 ffffffff822f1000 T smu_v13_0_init_microcode
 ffffffff822f11d0 T smu_v13_0_fini_microcode
 ffffffff822f1250 T smu_v13_0_load_microcode
@@ -40097,18 +40101,18 @@ ffffffff8254b000 r isomappings
 ffffffff8254b080 r unimappings
 ffffffff8254b230 r replacements
 ffffffff8254e93f r apollo_pio_rec
-ffffffff8259768b r apollo_udma33_tim
-ffffffff825aae18 r pp_r600_decoded_lanes
-ffffffff825ddb81 r cmd680_setup_channel.udma_tbl
-ffffffff825e57ed r apollo_udma100_tim
-ffffffff825e57f3 r cmd0646_9_tim_udma
-ffffffff825f314a r substchar
-ffffffff82643e70 r apollo_udma133_tim
-ffffffff82643e77 r apollo_udma66_tim
-ffffffff82643ea1 r cy_pio_rec
-ffffffff82648e40 R drm_ca
-ffffffff82648e68 R drm_filtops
-ffffffff82648e98 R drmread_filtops
+ffffffff8259765a r apollo_udma33_tim
+ffffffff825aade7 r pp_r600_decoded_lanes
+ffffffff825ddb50 r cmd680_setup_channel.udma_tbl
+ffffffff825e57bc r apollo_udma100_tim
+ffffffff825e57c2 r cmd0646_9_tim_udma
+ffffffff825f3156 r substchar
+ffffffff82643e98 r apollo_udma133_tim
+ffffffff82643e9f r apollo_udma66_tim
+ffffffff82643ec9 r cy_pio_rec
+ffffffff82648e68 R drm_ca
+ffffffff82648e90 R drm_filtops
+ffffffff82648ec0 R drmread_filtops
 ffffffff82649000 r vga_emulops
 ffffffff82649048 R vga_stdscreen
 ffffffff82649078 R vga_stdscreen_mono
@@ -43938,6 +43942,7 @@ ffffffff82a97d50 r gfx11_SECT_CONTEXT_def_4
 ffffffff82a97fd0 r gfx11_SECT_CONTEXT_def_7
 ffffffff82a98438 r gfx_v11_0_gfx_funcs
 ffffffff82a98480 r golden_settings_gc_11_0_1
+ffffffff82a98560 r golden_settings_gc_11_0
 ffffffff82a99000 r gfx_v8_0_ip_funcs
 ffffffff82a990a0 R gfx_v8_0_ip_block
 ffffffff82a990b8 R gfx_v8_1_ip_block