--- 7.3/2023-09-01T06:17:13Z/2023-08-24T00:00:00Z/nm-bsd-ot14.txt	Mon Sep  4 02:31:43 2023
+++ 7.3/2023-09-01T06:17:13Z/2023-08-25T00:00:00Z/nm-bsd-ot14.txt	Mon Sep  4 05:22:06 2023
@@ -21639,41 +21639,41 @@ ffffffff81aae220 t intel_dmi_reverse_brightness
 ffffffff81aae270 t intel_dmi_no_pps_backlight
 ffffffff81aaf000 T intel_sdvo_port_enabled
 ffffffff81aaf0a0 T intel_sdvo_init
-ffffffff81aafc70 t intel_sdvo_compute_config
-ffffffff81ab01d0 t pch_disable_sdvo
-ffffffff81ab0200 t pch_post_disable_sdvo
-ffffffff81ab0210 t intel_disable_sdvo
-ffffffff81ab0380 t intel_sdvo_pre_enable
-ffffffff81ab0d00 t intel_enable_sdvo
-ffffffff81ab0f00 t intel_sdvo_get_hw_state
-ffffffff81ab0ff0 t intel_sdvo_get_config
-ffffffff81ab1560 t intel_sdvo_ddc_proxy_xfer
-ffffffff81ab1610 t intel_sdvo_ddc_proxy_func
-ffffffff81ab1640 t __intel_sdvo_write_cmd
-ffffffff81ab1b00 t proxy_lock_bus
-ffffffff81ab1b30 t proxy_trylock_bus
-ffffffff81ab1b60 t proxy_unlock_bus
-ffffffff81ab1b90 t intel_sdvo_enc_destroy
-ffffffff81ab1ba0 t intel_sdvo_get_preferred_input_mode
-ffffffff81ab1f30 t intel_sdvo_get_dtd_from_mode
-ffffffff81ab20a0 t intel_sdvo_read_response
-ffffffff81ab2540 t intel_sdvo_write_sdvox
-ffffffff81ab2730 t intel_sdvo_write_infoframe
-ffffffff81ab2900 t intel_sdvo_dvi_init
-ffffffff81ab2b90 t intel_sdvo_tv_init
-ffffffff81ab2eb0 t intel_sdvo_lvds_init
-ffffffff81ab30a0 t intel_sdvo_hotplug
-ffffffff81ab30e0 t intel_sdvo_connector_get_hw_state
-ffffffff81ab3170 t intel_sdvo_detect
-ffffffff81ab34f0 t intel_sdvo_connector_register
-ffffffff81ab3500 t intel_sdvo_connector_unregister
-ffffffff81ab3510 t intel_sdvo_connector_duplicate_state
-ffffffff81ab3590 t intel_sdvo_connector_atomic_set_property
-ffffffff81ab3760 t intel_sdvo_connector_atomic_get_property
-ffffffff81ab3980 t intel_sdvo_get_modes
-ffffffff81ab3c40 t intel_sdvo_mode_valid
-ffffffff81ab3d10 t intel_sdvo_atomic_check
-ffffffff81ab3dc0 t intel_sdvo_create_enhance_property
+ffffffff81aafc50 t intel_sdvo_compute_config
+ffffffff81ab01b0 t pch_disable_sdvo
+ffffffff81ab01e0 t pch_post_disable_sdvo
+ffffffff81ab01f0 t intel_disable_sdvo
+ffffffff81ab0360 t intel_sdvo_pre_enable
+ffffffff81ab0ce0 t intel_enable_sdvo
+ffffffff81ab0ee0 t intel_sdvo_get_hw_state
+ffffffff81ab0fd0 t intel_sdvo_get_config
+ffffffff81ab1540 t intel_sdvo_ddc_proxy_xfer
+ffffffff81ab15f0 t intel_sdvo_ddc_proxy_func
+ffffffff81ab1620 t __intel_sdvo_write_cmd
+ffffffff81ab1ae0 t proxy_lock_bus
+ffffffff81ab1b10 t proxy_trylock_bus
+ffffffff81ab1b40 t proxy_unlock_bus
+ffffffff81ab1b70 t intel_sdvo_enc_destroy
+ffffffff81ab1b80 t intel_sdvo_get_preferred_input_mode
+ffffffff81ab1f10 t intel_sdvo_get_dtd_from_mode
+ffffffff81ab2080 t intel_sdvo_read_response
+ffffffff81ab2520 t intel_sdvo_write_sdvox
+ffffffff81ab2710 t intel_sdvo_write_infoframe
+ffffffff81ab28e0 t intel_sdvo_dvi_init
+ffffffff81ab2b60 t intel_sdvo_tv_init
+ffffffff81ab2e70 t intel_sdvo_lvds_init
+ffffffff81ab3050 t intel_sdvo_hotplug
+ffffffff81ab3090 t intel_sdvo_connector_get_hw_state
+ffffffff81ab3120 t intel_sdvo_detect
+ffffffff81ab34a0 t intel_sdvo_connector_register
+ffffffff81ab34b0 t intel_sdvo_connector_unregister
+ffffffff81ab34c0 t intel_sdvo_connector_duplicate_state
+ffffffff81ab3540 t intel_sdvo_connector_atomic_set_property
+ffffffff81ab3710 t intel_sdvo_connector_atomic_get_property
+ffffffff81ab3930 t intel_sdvo_get_modes
+ffffffff81ab3bf0 t intel_sdvo_mode_valid
+ffffffff81ab3cc0 t intel_sdvo_atomic_check
+ffffffff81ab3d70 t intel_sdvo_create_enhance_property
 ffffffff81ab5000 T intel_snps_phy_wait_for_calibration
 ffffffff81ab50d0 T intel_snps_phy_update_psr_power_state
 ffffffff81ab51a0 T intel_snps_phy_set_signal_levels
@@ -25870,14 +25870,14 @@ ffffffff81d4c070 t amdgpu_connector_lvds_get_modes
 ffffffff81d4c1e0 t amdgpu_connector_lvds_mode_valid
 ffffffff81d4d000 T amdgpu_cs_report_moved_bytes
 ffffffff81d4d070 T amdgpu_cs_ioctl
-ffffffff81d4ee60 t amdgpu_cs_parser_fini
-ffffffff81d4eff0 T amdgpu_cs_wait_ioctl
-ffffffff81d4f130 T amdgpu_cs_fence_to_handle_ioctl
-ffffffff81d4f2d0 t amdgpu_cs_get_fence
-ffffffff81d4f380 T amdgpu_cs_wait_fences_ioctl
-ffffffff81d4f670 T amdgpu_cs_find_mapping
-ffffffff81d4f770 t amdgpu_cs_bo_validate
-ffffffff81d4fa80 t amdgpu_cs_list_validate
+ffffffff81d4ee80 t amdgpu_cs_parser_fini
+ffffffff81d4f010 T amdgpu_cs_wait_ioctl
+ffffffff81d4f150 T amdgpu_cs_fence_to_handle_ioctl
+ffffffff81d4f2f0 t amdgpu_cs_get_fence
+ffffffff81d4f3a0 T amdgpu_cs_wait_fences_ioctl
+ffffffff81d4f690 T amdgpu_cs_find_mapping
+ffffffff81d4f790 t amdgpu_cs_bo_validate
+ffffffff81d4faa0 t amdgpu_cs_list_validate
 ffffffff81d50000 T amdgpu_csa_vaddr
 ffffffff81d50060 T amdgpu_allocate_static_csa
 ffffffff81d50100 T amdgpu_free_static_csa
@@ -25965,33 +25965,33 @@ ffffffff81d58cf0 T amdgpu_device_fini_hw
 ffffffff81d591e0 t amdgpu_device_unmap_mmio
 ffffffff81d592e0 T amdgpu_device_fini_sw
 ffffffff81d596c0 T amdgpu_device_suspend
-ffffffff81d59860 T amdgpu_device_resume
-ffffffff81d59b80 T amdgpu_device_has_job_running
-ffffffff81d59c50 T amdgpu_device_should_recover_gpu
-ffffffff81d59d80 T amdgpu_device_mode1_reset
-ffffffff81d59e80 T amdgpu_device_load_pci_state
-ffffffff81d59ed0 T amdgpu_device_pre_asic_reset
-ffffffff81d5a2d0 T amdgpu_do_asic_reset
-ffffffff81d5a8b0 t amdgpu_device_ip_resume_phase1
-ffffffff81d5a9b0 t amdgpu_device_fw_loading
-ffffffff81d5ab10 t amdgpu_device_ip_resume_phase2
-ffffffff81d5ac30 t amdgpu_device_recover_vram
-ffffffff81d5ae10 T amdgpu_device_gpu_recover
-ffffffff81d5b960 t amdgpu_device_reset_sriov
-ffffffff81d5be40 T amdgpu_device_is_peer_accessible
-ffffffff81d5be70 T amdgpu_device_baco_enter
-ffffffff81d5bf20 T amdgpu_device_baco_exit
-ffffffff81d5c000 T amdgpu_pci_error_detected
-ffffffff81d5c050 T amdgpu_pci_mmio_enabled
-ffffffff81d5c0a0 T amdgpu_pci_slot_reset
-ffffffff81d5c0f0 T amdgpu_pci_resume
-ffffffff81d5c110 T amdgpu_in_reset
-ffffffff81d5c140 T amdgpu_device_halt
-ffffffff81d5c180 T amdgpu_device_pcie_port_rreg
-ffffffff81d5c3c0 T amdgpu_device_pcie_port_wreg
-ffffffff81d5c680 T amdgpu_device_switch_gang
-ffffffff81d5c710 T amdgpu_device_has_display_hardware
-ffffffff81d5c770 t __delayed_work_tick
+ffffffff81d59870 T amdgpu_device_resume
+ffffffff81d59b90 T amdgpu_device_has_job_running
+ffffffff81d59c60 T amdgpu_device_should_recover_gpu
+ffffffff81d59d90 T amdgpu_device_mode1_reset
+ffffffff81d59e90 T amdgpu_device_load_pci_state
+ffffffff81d59ee0 T amdgpu_device_pre_asic_reset
+ffffffff81d5a2e0 T amdgpu_do_asic_reset
+ffffffff81d5a8c0 t amdgpu_device_ip_resume_phase1
+ffffffff81d5a9c0 t amdgpu_device_fw_loading
+ffffffff81d5ab20 t amdgpu_device_ip_resume_phase2
+ffffffff81d5ac40 t amdgpu_device_recover_vram
+ffffffff81d5ae20 T amdgpu_device_gpu_recover
+ffffffff81d5b970 t amdgpu_device_reset_sriov
+ffffffff81d5be50 T amdgpu_device_is_peer_accessible
+ffffffff81d5be80 T amdgpu_device_baco_enter
+ffffffff81d5bf30 T amdgpu_device_baco_exit
+ffffffff81d5c010 T amdgpu_pci_error_detected
+ffffffff81d5c060 T amdgpu_pci_mmio_enabled
+ffffffff81d5c0b0 T amdgpu_pci_slot_reset
+ffffffff81d5c100 T amdgpu_pci_resume
+ffffffff81d5c120 T amdgpu_in_reset
+ffffffff81d5c150 T amdgpu_device_halt
+ffffffff81d5c190 T amdgpu_device_pcie_port_rreg
+ffffffff81d5c3d0 T amdgpu_device_pcie_port_wreg
+ffffffff81d5c690 T amdgpu_device_switch_gang
+ffffffff81d5c720 T amdgpu_device_has_display_hardware
+ffffffff81d5c780 t __delayed_work_tick
 ffffffff81d5d000 T amdgpu_discovery_fini
 ffffffff81d5d050 T amdgpu_discovery_get_ip_version
 ffffffff81d5d170 T amdgpu_discovery_set_ip_blocks
@@ -26068,19 +26068,19 @@ ffffffff81d69670 T amdgpu_fence_driver_init_ring
 ffffffff81d69760 t amdgpu_fence_fallback
 ffffffff81d697c0 T amdgpu_fence_driver_sw_init
 ffffffff81d697f0 T amdgpu_fence_driver_hw_fini
-ffffffff81d69940 T amdgpu_fence_driver_force_completion
-ffffffff81d69960 T amdgpu_fence_driver_isr_toggle
-ffffffff81d69980 T amdgpu_fence_driver_sw_fini
-ffffffff81d69a60 T amdgpu_fence_driver_hw_init
-ffffffff81d69ae0 T amdgpu_fence_driver_clear_job_fences
-ffffffff81d69b90 T amdgpu_debugfs_fence_init
-ffffffff81d69bc0 t amdgpu_fence_get_driver_name
-ffffffff81d69bf0 t amdgpu_fence_get_timeline_name
-ffffffff81d69c50 t amdgpu_fence_enable_signaling
-ffffffff81d69cf0 t amdgpu_fence_release
-ffffffff81d69d30 t amdgpu_job_fence_get_timeline_name
-ffffffff81d69d70 t amdgpu_job_fence_enable_signaling
-ffffffff81d69df0 t amdgpu_job_fence_release
+ffffffff81d69990 T amdgpu_fence_driver_force_completion
+ffffffff81d699b0 T amdgpu_fence_driver_isr_toggle
+ffffffff81d699d0 T amdgpu_fence_driver_sw_fini
+ffffffff81d69ab0 T amdgpu_fence_driver_hw_init
+ffffffff81d69b70 T amdgpu_fence_driver_clear_job_fences
+ffffffff81d69c20 T amdgpu_debugfs_fence_init
+ffffffff81d69c50 t amdgpu_fence_get_driver_name
+ffffffff81d69c80 t amdgpu_fence_get_timeline_name
+ffffffff81d69ce0 t amdgpu_fence_enable_signaling
+ffffffff81d69d80 t amdgpu_fence_release
+ffffffff81d69dc0 t amdgpu_job_fence_get_timeline_name
+ffffffff81d69e00 t amdgpu_job_fence_enable_signaling
+ffffffff81d69e80 t amdgpu_job_fence_release
 ffffffff81d6a000 T amdgpu_fru_get_product_info
 ffffffff81d6b000 T amdgpu_fw_attestation_debugfs_init
 ffffffff81d6c000 T amdgpu_gart_dummy_page_fini
@@ -26135,17 +26135,17 @@ ffffffff81d70050 T amdgpu_gfx_disable_kcq
 ffffffff81d701a0 T amdgpu_queue_mask_bit_to_set_resource_bit
 ffffffff81d701f0 T amdgpu_gfx_enable_kcq
 ffffffff81d70440 T amdgpu_gfx_off_ctrl
-ffffffff81d70620 T amdgpu_set_gfx_off_residency
-ffffffff81d70690 T amdgpu_get_gfx_off_residency
-ffffffff81d70700 T amdgpu_get_gfx_off_entrycount
-ffffffff81d70770 T amdgpu_get_gfx_off_status
-ffffffff81d707e0 T amdgpu_gfx_ras_late_init
-ffffffff81d708c0 T amdgpu_gfx_process_ras_data_cb
-ffffffff81d70940 T amdgpu_gfx_cp_ecc_error_irq
-ffffffff81d70a10 T amdgpu_kiq_rreg
-ffffffff81d70c90 T amdgpu_kiq_wreg
-ffffffff81d70ec0 T amdgpu_gfx_get_num_kcq
-ffffffff81d70f40 T amdgpu_gfx_cp_init_microcode
+ffffffff81d705e0 T amdgpu_set_gfx_off_residency
+ffffffff81d70650 T amdgpu_get_gfx_off_residency
+ffffffff81d706c0 T amdgpu_get_gfx_off_entrycount
+ffffffff81d70730 T amdgpu_get_gfx_off_status
+ffffffff81d707a0 T amdgpu_gfx_ras_late_init
+ffffffff81d70880 T amdgpu_gfx_process_ras_data_cb
+ffffffff81d70900 T amdgpu_gfx_cp_ecc_error_irq
+ffffffff81d709d0 T amdgpu_kiq_rreg
+ffffffff81d70c50 T amdgpu_kiq_wreg
+ffffffff81d70e80 T amdgpu_gfx_get_num_kcq
+ffffffff81d70f00 T amdgpu_gfx_cp_init_microcode
 ffffffff81d72000 T amdgpu_gmc_pdb0_alloc
 ffffffff81d72290 t amdgpu_bo_unreserve
 ffffffff81d72370 T amdgpu_gmc_get_pde_for_bo
@@ -26225,26 +26225,26 @@ ffffffff81d786e0 T amdgpu_ih_process
 ffffffff81d788a0 T amdgpu_ih_decode_iv_helper
 ffffffff81d78970 T amdgpu_ih_decode_iv_ts_helper
 ffffffff81d79000 T amdgpu_irq_disable_all
-ffffffff81d79110 T amdgpu_irq_handler
-ffffffff81d79180 T amdgpu_msi_ok
-ffffffff81d791b0 T amdgpu_irq_init
-ffffffff81d79300 t amdgpu_hotplug_work_func
-ffffffff81d793b0 t amdgpu_irq_handle_ih1
-ffffffff81d793e0 t amdgpu_irq_handle_ih2
-ffffffff81d79410 t amdgpu_irq_handle_ih_soft
-ffffffff81d79440 T amdgpu_irq_fini_hw
-ffffffff81d794c0 T amdgpu_irq_fini_sw
-ffffffff81d79590 T amdgpu_irq_add_id
-ffffffff81d79690 T amdgpu_irq_dispatch
-ffffffff81d79820 T amdgpu_irq_delegate
-ffffffff81d79870 T amdgpu_irq_update
-ffffffff81d79920 T amdgpu_irq_enabled
-ffffffff81d79980 T amdgpu_irq_gpu_reset_resume_helper
-ffffffff81d79b00 T amdgpu_irq_get
-ffffffff81d79c00 T amdgpu_irq_put
-ffffffff81d79d30 T amdgpu_irq_add_domain
-ffffffff81d79d60 T amdgpu_irq_remove_domain
-ffffffff81d79d80 T amdgpu_irq_create_mapping
+ffffffff81d79100 T amdgpu_irq_handler
+ffffffff81d79170 T amdgpu_msi_ok
+ffffffff81d791a0 T amdgpu_irq_init
+ffffffff81d792f0 t amdgpu_hotplug_work_func
+ffffffff81d793a0 t amdgpu_irq_handle_ih1
+ffffffff81d793d0 t amdgpu_irq_handle_ih2
+ffffffff81d79400 t amdgpu_irq_handle_ih_soft
+ffffffff81d79430 T amdgpu_irq_fini_hw
+ffffffff81d794b0 T amdgpu_irq_fini_sw
+ffffffff81d79580 T amdgpu_irq_add_id
+ffffffff81d79680 T amdgpu_irq_dispatch
+ffffffff81d79810 T amdgpu_irq_delegate
+ffffffff81d79860 T amdgpu_irq_update
+ffffffff81d79910 T amdgpu_irq_enabled
+ffffffff81d79970 T amdgpu_irq_gpu_reset_resume_helper
+ffffffff81d79af0 T amdgpu_irq_get
+ffffffff81d79bf0 T amdgpu_irq_put
+ffffffff81d79d20 T amdgpu_irq_add_domain
+ffffffff81d79d50 T amdgpu_irq_remove_domain
+ffffffff81d79d70 T amdgpu_irq_create_mapping
 ffffffff81d7a000 T amdgpu_job_alloc
 ffffffff81d7a0e0 T amdgpu_job_alloc_with_ib
 ffffffff81d7a1f0 T amdgpu_job_set_resources
@@ -26411,8 +26411,8 @@ ffffffff81d8e2f0 T amdgpu_psp_sysfs_init
 ffffffff81d8e370 t psp_early_init
 ffffffff81d8e570 t psp_sw_init
 ffffffff81d8e9e0 t psp_sw_fini
-ffffffff81d8ec00 t psp_hw_init
-ffffffff81d8f240 t psp_hw_fini
+ffffffff81d8ed20 t psp_hw_init
+ffffffff81d8f360 t psp_hw_fini
 ffffffff81d8f790 t psp_suspend
 ffffffff81d8fc70 t psp_resume
 ffffffff81d90190 t psp_set_clockgating_state
@@ -26495,11 +26495,11 @@ ffffffff81d9b1f0 T amdgpu_ring_commit
 ffffffff81d9b280 T amdgpu_ring_undo
 ffffffff81d9b2d0 T amdgpu_ring_init
 ffffffff81d9b9a0 T amdgpu_ring_fini
-ffffffff81d9bab0 T amdgpu_ring_emit_reg_write_reg_wait_helper
-ffffffff81d9bb10 T amdgpu_ring_soft_recovery
-ffffffff81d9bc70 T amdgpu_debugfs_ring_init
-ffffffff81d9bca0 T amdgpu_ring_test_helper
-ffffffff81d9bd50 T amdgpu_ring_init_mqd
+ffffffff81d9bac0 T amdgpu_ring_emit_reg_write_reg_wait_helper
+ffffffff81d9bb20 T amdgpu_ring_soft_recovery
+ffffffff81d9bc80 T amdgpu_debugfs_ring_init
+ffffffff81d9bcb0 T amdgpu_ring_test_helper
+ffffffff81d9bd60 T amdgpu_ring_init_mqd
 ffffffff81d9c000 T amdgpu_gfx_rlc_enter_safe_mode
 ffffffff81d9c080 T amdgpu_gfx_rlc_exit_safe_mode
 ffffffff81d9c100 T amdgpu_gfx_rlc_init_sr
@@ -31650,20 +31650,20 @@ ffffffff820d0480 t optc314_set_odm_combine
 ffffffff820d0780 t optc314_set_h_timing_div_manual_mode
 ffffffff820d1000 T dcn314_validate_bandwidth
 ffffffff820d14a0 T dcn314_create_resource_pool
-ffffffff820d2770 t dcn314_resource_destruct
-ffffffff820d2dd0 t dcn314_destroy_resource_pool
-ffffffff820d2e30 t dcn31_panel_cntl_create
-ffffffff820d2ea0 t dcn31_link_encoder_create
-ffffffff820d2f60 t dcn31_link_enc_create_minimal
-ffffffff820d3000 t dcn314_populate_dml_pipes_from_context
-ffffffff820d3090 t dcn314_update_bw_bounding_box
-ffffffff820d30e0 t dcn314_get_panel_config_defaults
-ffffffff820d3160 t read_dce_straps
-ffffffff820d3190 t dcn31_create_audio
-ffffffff820d31c0 t dcn314_stream_encoder_create
-ffffffff820d3340 t dcn31_hpo_dp_stream_encoder_create
-ffffffff820d3500 t dcn31_hpo_dp_link_encoder_create
-ffffffff820d3590 t dcn314_hwseq_create
+ffffffff820d2780 t dcn314_resource_destruct
+ffffffff820d2de0 t dcn314_destroy_resource_pool
+ffffffff820d2e40 t dcn31_panel_cntl_create
+ffffffff820d2eb0 t dcn31_link_encoder_create
+ffffffff820d2f70 t dcn31_link_enc_create_minimal
+ffffffff820d3010 t dcn314_populate_dml_pipes_from_context
+ffffffff820d30a0 t dcn314_update_bw_bounding_box
+ffffffff820d30f0 t dcn314_get_panel_config_defaults
+ffffffff820d3170 t read_dce_straps
+ffffffff820d31a0 t dcn31_create_audio
+ffffffff820d31d0 t dcn314_stream_encoder_create
+ffffffff820d3350 t dcn31_hpo_dp_stream_encoder_create
+ffffffff820d3510 t dcn31_hpo_dp_link_encoder_create
+ffffffff820d35a0 t dcn314_hwseq_create
 ffffffff820d4000 T dcn315_create_resource_pool
 ffffffff820d5270 t dcn315_resource_destruct
 ffffffff820d58d0 t dcn315_destroy_resource_pool
@@ -31699,7 +31699,7 @@ ffffffff820da120 t dccg32_otg_drop_pixel
 ffffffff820da160 t dccg32_set_dpstreamclk
 ffffffff820da530 t dccg32_set_dtbclk_dto
 ffffffff820da730 t dccg32_set_pixel_rate_div
-ffffffff820daaa0 t dccg32_set_valid_pixel_rate
+ffffffff820dab00 t dccg32_set_valid_pixel_rate
 ffffffff820db000 T enc32_hw_init
 ffffffff820db090 T dcn32_link_encoder_enable_dp_output
 ffffffff820db0e0 T dcn32_link_encoder_construct
@@ -31791,20 +31791,20 @@ ffffffff820eed50 T dcn32_populate_dml_pipes_from_conte
 ffffffff820ef130 T dcn32_calculate_wm_and_dlg
 ffffffff820ef1a0 T dcn32_create_resource_pool
 ffffffff820ef250 t dcn32_resource_construct
-ffffffff820fb670 T dcn32_acquire_idle_pipe_for_head_pipe_in_layer
-ffffffff820fb8b0 T dcn32_calc_num_avail_chans_for_mall
-ffffffff820fb920 t dcn32_mpc_create
-ffffffff821002e0 t dcn32_resource_destruct
-ffffffff82100950 t dcn32_destroy_resource_pool
-ffffffff821009b0 t dcn32_link_encoder_create
-ffffffff82101910 t dcn32_update_bw_bounding_box
-ffffffff82101960 t read_dce_straps
-ffffffff82101990 t dcn32_create_audio
-ffffffff82101cd0 t dcn32_stream_encoder_create
-ffffffff82103b50 t dcn32_hpo_dp_stream_encoder_create
-ffffffff82104830 t dcn32_hpo_dp_link_encoder_create
-ffffffff82104cb0 t dcn32_hwseq_create
-ffffffff82105150 t dcn32_vpg_create
+ffffffff820fb680 T dcn32_acquire_idle_pipe_for_head_pipe_in_layer
+ffffffff820fb8c0 T dcn32_calc_num_avail_chans_for_mall
+ffffffff820fb930 t dcn32_mpc_create
+ffffffff821002f0 t dcn32_resource_destruct
+ffffffff82100960 t dcn32_destroy_resource_pool
+ffffffff821009c0 t dcn32_link_encoder_create
+ffffffff82101920 t dcn32_update_bw_bounding_box
+ffffffff82101970 t read_dce_straps
+ffffffff821019a0 t dcn32_create_audio
+ffffffff82101ce0 t dcn32_stream_encoder_create
+ffffffff82103b60 t dcn32_hpo_dp_stream_encoder_create
+ffffffff82104840 t dcn32_hpo_dp_link_encoder_create
+ffffffff82104cc0 t dcn32_hwseq_create
+ffffffff82105160 t dcn32_vpg_create
 ffffffff82106000 T dcn32_helper_calculate_num_ways_for_subvp
 ffffffff821061e0 T dcn32_merge_pipes_for_subvp
 ffffffff821063b0 T dcn32_all_pipes_have_stream_and_plane
@@ -31818,18 +31818,18 @@ ffffffff82106b40 T dcn32_restore_mall_state
 ffffffff82107000 T dcn321_link_encoder_construct
 ffffffff82108000 T dcn321_create_resource_pool
 ffffffff821080b0 t dcn321_resource_construct
-ffffffff82114470 t dcn321_mpc_create
-ffffffff82118e30 t dcn321_resource_destruct
-ffffffff821194a0 t dcn321_destroy_resource_pool
-ffffffff82119500 t dcn321_link_encoder_create
-ffffffff8211a460 t dcn321_update_bw_bounding_box
-ffffffff8211a4b0 t read_dce_straps
-ffffffff8211a4e0 t dcn321_create_audio
-ffffffff8211a820 t dcn321_stream_encoder_create
-ffffffff8211c6a0 t dcn321_hpo_dp_stream_encoder_create
-ffffffff8211d380 t dcn321_hpo_dp_link_encoder_create
-ffffffff8211d800 t dcn321_hwseq_create
-ffffffff8211dca0 t dcn321_vpg_create
+ffffffff82114480 t dcn321_mpc_create
+ffffffff82118e40 t dcn321_resource_destruct
+ffffffff821194b0 t dcn321_destroy_resource_pool
+ffffffff82119510 t dcn321_link_encoder_create
+ffffffff8211a470 t dcn321_update_bw_bounding_box
+ffffffff8211a4c0 t read_dce_straps
+ffffffff8211a4f0 t dcn321_create_audio
+ffffffff8211a830 t dcn321_stream_encoder_create
+ffffffff8211c6b0 t dcn321_hpo_dp_stream_encoder_create
+ffffffff8211d390 t dcn321_hpo_dp_link_encoder_create
+ffffffff8211d810 t dcn321_hwseq_create
+ffffffff8211dcb0 t dcn321_vpg_create
 ffffffff8211f000 T bw_int_to_fixed_nonconst
 ffffffff8211f090 T bw_frc_to_fixed
 ffffffff8211f260 T bw_floor2
@@ -33815,9 +33815,9 @@ ffffffff822ecde0 t sienna_cichlid_get_default_config_t
 ffffffff822ece50 t sienna_cichlid_set_config_table
 ffffffff822ecf20 t sienna_cichlid_get_smu_metrics_data
 ffffffff822ed360 t sienna_cichlid_get_throttler_status_locked
-ffffffff822ed4e0 t sienna_cichlid_get_smartshift_power_percentage
-ffffffff822ed610 t sienna_cichlid_i2c_xfer
-ffffffff822ed8c0 t sienna_cichlid_i2c_func
+ffffffff822ed4c0 t sienna_cichlid_get_smartshift_power_percentage
+ffffffff822ed5f0 t sienna_cichlid_i2c_xfer
+ffffffff822ed8a0 t sienna_cichlid_i2c_func
 ffffffff822ee000 T smu_v11_0_init_microcode
 ffffffff822ee2a0 T smu_v11_0_fini_microcode
 ffffffff822ee320 T smu_v11_0_load_microcode
@@ -39312,10 +39312,10 @@ ffffffff825e401d r apollo_udma100_tim
 ffffffff8260ba2a r apollo_udma66_tim
 ffffffff82612f7f r apollo_pio_rec
 ffffffff826224a0 r cy_pio_rec
-ffffffff82651c63 r apollo_udma133_tim
-ffffffff8265e968 R drm_ca
-ffffffff8265e990 R drm_filtops
-ffffffff8265e9c0 R drmread_filtops
+ffffffff82651c87 r apollo_udma133_tim
+ffffffff8265e988 R drm_ca
+ffffffff8265e9b0 R drm_filtops
+ffffffff8265e9e0 R drmread_filtops
 ffffffff8265f000 r vga_emulops
 ffffffff8265f048 R vga_stdscreen
 ffffffff8265f078 R vga_stdscreen_mono
@@ -39330,23 +39330,23 @@ ffffffff8265f1f8 R vga_screenlist
 ffffffff8265f208 R vga_screenlist_mono
 ffffffff8265f218 R vga_accessops
 ffffffff8265f278 r i945_wm_info
-ffffffff8265f2b0 r bgansitopc
-ffffffff8265f2b8 r pctoansi
-ffffffff8265f2f8 r sdma_offsets
-ffffffff8265f2f8 r sdma_offsets
-ffffffff8265f330 r iha_rate_tbl
-ffffffff8265f368 r i830_a_wm_info
-ffffffff8265f3a0 r gen9_edram_size_mb.ways
-ffffffff8265f400 r aggr_periodic_times
-ffffffff8265f488 r jsl_ehl_revids
-ffffffff8265f500 r michael_final.pad
-ffffffff8265f528 r rt_copysa.maskarray
-ffffffff8265f530 r i915_wm_info
-ffffffff8265f538 r amdgpu_ih_clientid_jpeg
-ffffffff8265f538 r amdgpu_ih_clientid_uvds
-ffffffff8265f538 r amdgpu_ih_clientid_vcns
-ffffffff8265f538 r amdgpu_ih_clientid_vcns
-ffffffff8265f538 r amdgpu_ih_clientid_vcns
+ffffffff8265f2b8 r bgansitopc
+ffffffff8265f2c0 r pctoansi
+ffffffff8265f300 r sdma_offsets
+ffffffff8265f300 r sdma_offsets
+ffffffff8265f338 r iha_rate_tbl
+ffffffff8265f370 r i830_a_wm_info
+ffffffff8265f3a8 r gen9_edram_size_mb.ways
+ffffffff8265f408 r aggr_periodic_times
+ffffffff8265f490 r jsl_ehl_revids
+ffffffff8265f508 r michael_final.pad
+ffffffff8265f530 r rt_copysa.maskarray
+ffffffff8265f538 r i915_wm_info
+ffffffff8265f540 r amdgpu_ih_clientid_jpeg
+ffffffff8265f540 r amdgpu_ih_clientid_uvds
+ffffffff8265f540 r amdgpu_ih_clientid_vcns
+ffffffff8265f540 r amdgpu_ih_clientid_vcns
+ffffffff8265f540 r amdgpu_ih_clientid_vcns
 ffffffff8265f578 r vga_setfontset.cmaptabb
 ffffffff8265f590 r tgl_revids
 ffffffff8265f5e8 r i830_bc_wm_info
@@ -44313,23 +44313,23 @@ ffffffff82b988e0 r clk_src_regs
 ffffffff82b98ad8 r dccg_regs
 ffffffff82b98bc4 r dccg_shift
 ffffffff82b98c5c r dccg_mask
-ffffffff82b98eb8 r dmcu_regs
-ffffffff82b98f14 r dmcu_shift
-ffffffff82b98f28 r dmcu_mask
-ffffffff82b98f74 r abm_regs
-ffffffff82b98fb4 r abm_shift
-ffffffff82b98fc8 r abm_mask
-ffffffff82b99010 r res_create_funcs
-ffffffff82b99040 r res_create_maximus_funcs
-ffffffff82b99070 r plane_cap
-ffffffff82b990a0 r panel_cntl_regs
-ffffffff82b990c0 r panel_cntl_shift
-ffffffff82b990d0 r panel_cntl_mask
-ffffffff82b9910c r cs_shift
-ffffffff82b99118 r cs_mask
-ffffffff82b99140 r audio_regs
-ffffffff82b99274 r audio_shift
-ffffffff82b9928c r audio_mask
+ffffffff82b98ebc r dmcu_regs
+ffffffff82b98f18 r dmcu_shift
+ffffffff82b98f2c r dmcu_mask
+ffffffff82b98f78 r abm_regs
+ffffffff82b98fb8 r abm_shift
+ffffffff82b98fcc r abm_mask
+ffffffff82b99018 r res_create_funcs
+ffffffff82b99048 r res_create_maximus_funcs
+ffffffff82b99078 r plane_cap
+ffffffff82b990b0 r panel_cntl_regs
+ffffffff82b990d0 r panel_cntl_shift
+ffffffff82b990e0 r panel_cntl_mask
+ffffffff82b9911c r cs_shift
+ffffffff82b99128 r cs_mask
+ffffffff82b99150 r audio_regs
+ffffffff82b99284 r audio_shift
+ffffffff82b9929c r audio_mask
 ffffffff82b9a000 r dcn20_str_enc_funcs
 ffffffff82b9b000 r dccg201_funcs
 ffffffff82b9c000 r hubbub201_funcs
@@ -44344,9 +44344,9 @@ ffffffff82ba01c0 r clk_src_regs
 ffffffff82ba0268 r dccg_regs
 ffffffff82ba0354 r dccg_shift
 ffffffff82ba03ec r dccg_mask
-ffffffff82ba0648 r res_create_funcs
-ffffffff82ba0678 r res_create_maximus_funcs
-ffffffff82ba06a8 r plane_cap
+ffffffff82ba0650 r res_create_funcs
+ffffffff82ba0680 r res_create_maximus_funcs
+ffffffff82ba06b0 r plane_cap
 ffffffff82ba06e0 r link_enc_regs
 ffffffff82ba0970 r link_enc_aux_regs
 ffffffff82ba0990 r link_enc_hpd_regs
@@ -44406,12 +44406,12 @@ ffffffff82baa420 r clk_src_regs
 ffffffff82baa5c4 r dccg_regs
 ffffffff82baa6b0 r dccg_shift
 ffffffff82baa748 r dccg_mask
-ffffffff82baa9a4 r dmcu_regs
-ffffffff82baaa00 r dmcu_shift
-ffffffff82baaa14 r dmcu_mask
-ffffffff82baaa60 r abm_regs
-ffffffff82baaaa0 r abm_shift
-ffffffff82baaab4 r abm_mask
+ffffffff82baa9a8 r dmcu_regs
+ffffffff82baaa04 r dmcu_shift
+ffffffff82baaa18 r dmcu_mask
+ffffffff82baaa64 r abm_regs
+ffffffff82baaaa4 r abm_shift
+ffffffff82baaab8 r abm_mask
 ffffffff82baab00 r res_create_funcs
 ffffffff82baab30 r res_create_maximus_funcs
 ffffffff82baab60 r plane_cap
@@ -44570,74 +44570,74 @@ ffffffff82bcd300 r clk_src_regs
 ffffffff82bcd450 r dccg_regs
 ffffffff82bcd53c r dccg_shift
 ffffffff82bcd5d4 r dccg_mask
-ffffffff82bcd830 r abm_regs
-ffffffff82bcd930 r abm_shift
-ffffffff82bcd944 r abm_mask
-ffffffff82bcd990 r res_create_funcs
-ffffffff82bcd9c0 r res_create_maximus_funcs
-ffffffff82bcd9f0 r plane_cap
-ffffffff82bcda20 r panel_cntl_regs
-ffffffff82bcda60 r panel_cntl_shift
-ffffffff82bcda70 r panel_cntl_mask
-ffffffff82bcdab0 r link_enc_regs
-ffffffff82bcdfc0 r link_enc_aux_regs
-ffffffff82bce000 r link_enc_hpd_regs
-ffffffff82bce010 r le_shift
-ffffffff82bce100 r le_mask
-ffffffff82bce4b8 r link_enc_feature
-ffffffff82bce4c8 r cs_shift
-ffffffff82bce4d4 r cs_mask
-ffffffff82bce4fc r hubbub_reg
-ffffffff82bce670 r hubbub_shift
-ffffffff82bce6f8 r hubbub_mask
-ffffffff82bce920 r vmid_regs
-ffffffff82bceae0 r vmid_shifts
-ffffffff82bceae8 r vmid_masks
-ffffffff82bceb10 r hubp_regs
-ffffffff82bcf340 r hubp_shift
-ffffffff82bcf43c r hubp_mask
-ffffffff82bcf830 r dpp_regs
-ffffffff82bd0d30 r tf_shift
-ffffffff82bd1000 r tf_mask
-ffffffff82bd1b40 r opp_regs
-ffffffff82bd1ca0 r opp_shift
-ffffffff82bd1cd8 r opp_mask
-ffffffff82bd1db0 r optc_regs
-ffffffff82bd22b0 r optc_shift
-ffffffff82bd2370 r optc_mask
-ffffffff82bd2670 r mpc_regs
-ffffffff82bd3e5c r mpc_shift
-ffffffff82bd3f38 r mpc_mask
-ffffffff82bd42b0 r dsc_regs
-ffffffff82bd44fc r dsc_shift
-ffffffff82bd45b4 r dsc_mask
-ffffffff82bd4890 r dwbc30_regs
-ffffffff82bd4a6c r dwbc30_shift
-ffffffff82bd4ba0 r dwbc30_mask
-ffffffff82bd5070 r mcif_wb30_regs
-ffffffff82bd516c r mcif_wb30_shift
-ffffffff82bd5218 r mcif_wb30_mask
-ffffffff82bd54d0 r aux_engine_regs
-ffffffff82bd5570 r aux_mask
-ffffffff82bd55d0 r aux_shift
-ffffffff82bd55f0 r i2c_hw_regs
-ffffffff82bd56d0 r i2c_shifts
-ffffffff82bd56fc r i2c_masks
-ffffffff82bd57a0 r audio_regs
-ffffffff82bd58d4 r audio_shift
-ffffffff82bd58ec r audio_mask
-ffffffff82bd5930 r stream_enc_regs
-ffffffff82bd5e80 r se_shift
-ffffffff82bd5f5c r se_mask
-ffffffff82bd62d0 r vpg_regs
-ffffffff82bd6320 r vpg_shift
-ffffffff82bd6348 r vpg_mask
-ffffffff82bd63e0 r afmt_regs
-ffffffff82bd6470 r afmt_shift
-ffffffff82bd6484 r afmt_mask
-ffffffff82bd64c8 r hwseq_reg
-ffffffff82bd66e4 r hwseq_shift
-ffffffff82bd6764 r hwseq_mask
+ffffffff82bcd840 r abm_regs
+ffffffff82bcd940 r abm_shift
+ffffffff82bcd954 r abm_mask
+ffffffff82bcd9a0 r res_create_funcs
+ffffffff82bcd9d0 r res_create_maximus_funcs
+ffffffff82bcda00 r plane_cap
+ffffffff82bcda30 r panel_cntl_regs
+ffffffff82bcda70 r panel_cntl_shift
+ffffffff82bcda80 r panel_cntl_mask
+ffffffff82bcdac0 r link_enc_regs
+ffffffff82bcdfd0 r link_enc_aux_regs
+ffffffff82bce010 r link_enc_hpd_regs
+ffffffff82bce020 r le_shift
+ffffffff82bce110 r le_mask
+ffffffff82bce4c8 r link_enc_feature
+ffffffff82bce4d8 r cs_shift
+ffffffff82bce4e4 r cs_mask
+ffffffff82bce50c r hubbub_reg
+ffffffff82bce680 r hubbub_shift
+ffffffff82bce708 r hubbub_mask
+ffffffff82bce930 r vmid_regs
+ffffffff82bceaf0 r vmid_shifts
+ffffffff82bceaf8 r vmid_masks
+ffffffff82bceb20 r hubp_regs
+ffffffff82bcf350 r hubp_shift
+ffffffff82bcf44c r hubp_mask
+ffffffff82bcf840 r dpp_regs
+ffffffff82bd0d40 r tf_shift
+ffffffff82bd1010 r tf_mask
+ffffffff82bd1b50 r opp_regs
+ffffffff82bd1cb0 r opp_shift
+ffffffff82bd1ce8 r opp_mask
+ffffffff82bd1dc0 r optc_regs
+ffffffff82bd22c0 r optc_shift
+ffffffff82bd2380 r optc_mask
+ffffffff82bd2680 r mpc_regs
+ffffffff82bd3e6c r mpc_shift
+ffffffff82bd3f48 r mpc_mask
+ffffffff82bd42c0 r dsc_regs
+ffffffff82bd450c r dsc_shift
+ffffffff82bd45c4 r dsc_mask
+ffffffff82bd48a0 r dwbc30_regs
+ffffffff82bd4a7c r dwbc30_shift
+ffffffff82bd4bb0 r dwbc30_mask
+ffffffff82bd5080 r mcif_wb30_regs
+ffffffff82bd517c r mcif_wb30_shift
+ffffffff82bd5228 r mcif_wb30_mask
+ffffffff82bd54e0 r aux_engine_regs
+ffffffff82bd5580 r aux_mask
+ffffffff82bd55e0 r aux_shift
+ffffffff82bd5600 r i2c_hw_regs
+ffffffff82bd56e0 r i2c_shifts
+ffffffff82bd570c r i2c_masks
+ffffffff82bd57b0 r audio_regs
+ffffffff82bd58e4 r audio_shift
+ffffffff82bd58fc r audio_mask
+ffffffff82bd5940 r stream_enc_regs
+ffffffff82bd5e90 r se_shift
+ffffffff82bd5f6c r se_mask
+ffffffff82bd62e0 r vpg_regs
+ffffffff82bd6330 r vpg_shift
+ffffffff82bd6358 r vpg_mask
+ffffffff82bd63f0 r afmt_regs
+ffffffff82bd6480 r afmt_shift
+ffffffff82bd6494 r afmt_mask
+ffffffff82bd64d8 r hwseq_reg
+ffffffff82bd66f4 r hwseq_shift
+ffffffff82bd6774 r hwseq_mask
 ffffffff82bd7000 r bios_regs
 ffffffff82bd7008 r res_cap_dcn302
 ffffffff82bd7048 r debug_defaults_drv
@@ -45148,113 +45148,113 @@ ffffffff82c27000 r res_cap_dcn32
 ffffffff82c27040 r debug_defaults_diags
 ffffffff82c271b8 r dccg_shift
 ffffffff82c27250 r dccg_mask
-ffffffff82c274ac r abm_shift
-ffffffff82c274c0 r abm_mask
-ffffffff82c27508 r res_create_funcs
-ffffffff82c27538 r res_create_maximus_funcs
-ffffffff82c27568 r plane_cap
-ffffffff82c27594 r le_shift
-ffffffff82c27684 r le_mask
-ffffffff82c27a3c r link_enc_feature
-ffffffff82c27a50 r debug_defaults_drv
-ffffffff82c27bc8 r cs_shift
-ffffffff82c27bd4 r cs_mask
-ffffffff82c27bfc r hubbub_shift
-ffffffff82c27c84 r hubbub_mask
-ffffffff82c27ea0 r vmid_shifts
-ffffffff82c27ea8 r vmid_masks
-ffffffff82c27ec8 r hubp_shift
-ffffffff82c27fc4 r hubp_mask
-ffffffff82c283b4 r tf_shift
-ffffffff82c28684 r tf_mask
-ffffffff82c291c4 r opp_shift
-ffffffff82c291fc r opp_mask
-ffffffff82c292d0 r optc_shift
-ffffffff82c29390 r optc_mask
-ffffffff82c29690 r mpc_shift
-ffffffff82c2976c r mpc_mask
-ffffffff82c29ad8 r dsc_shift
-ffffffff82c29b90 r dsc_mask
-ffffffff82c29e68 r dwbc30_shift
-ffffffff82c29f9c r dwbc30_mask
-ffffffff82c2a464 r mcif_wb30_shift
-ffffffff82c2a510 r mcif_wb30_mask
-ffffffff82c2a7bc r aux_mask
-ffffffff82c2a81c r aux_shift
-ffffffff82c2a834 r i2c_shifts
-ffffffff82c2a860 r i2c_masks
-ffffffff82c2a904 r audio_shift
-ffffffff82c2a91c r audio_mask
-ffffffff82c2a958 r se_shift
-ffffffff82c2aa34 r se_mask
-ffffffff82c2ada0 r vpg_shift
-ffffffff82c2adc8 r vpg_mask
-ffffffff82c2ae5c r afmt_shift
-ffffffff82c2ae70 r afmt_mask
-ffffffff82c2aeb4 r hpo_dp_se_shift
-ffffffff82c2aedc r hpo_dp_se_mask
-ffffffff82c2af7c r apg_shift
-ffffffff82c2af84 r apg_mask
-ffffffff82c2af9c r hpo_dp_le_shift
-ffffffff82c2afb8 r hpo_dp_le_mask
-ffffffff82c2b01c r hwseq_shift
-ffffffff82c2b09c r hwseq_mask
+ffffffff82c274b0 r abm_shift
+ffffffff82c274c4 r abm_mask
+ffffffff82c27510 r res_create_funcs
+ffffffff82c27540 r res_create_maximus_funcs
+ffffffff82c27570 r plane_cap
+ffffffff82c2759c r le_shift
+ffffffff82c2768c r le_mask
+ffffffff82c27a44 r link_enc_feature
+ffffffff82c27a58 r debug_defaults_drv
+ffffffff82c27bd0 r cs_shift
+ffffffff82c27bdc r cs_mask
+ffffffff82c27c04 r hubbub_shift
+ffffffff82c27c8c r hubbub_mask
+ffffffff82c27ea8 r vmid_shifts
+ffffffff82c27eb0 r vmid_masks
+ffffffff82c27ed0 r hubp_shift
+ffffffff82c27fcc r hubp_mask
+ffffffff82c283bc r tf_shift
+ffffffff82c2868c r tf_mask
+ffffffff82c291cc r opp_shift
+ffffffff82c29204 r opp_mask
+ffffffff82c292d8 r optc_shift
+ffffffff82c29398 r optc_mask
+ffffffff82c29698 r mpc_shift
+ffffffff82c29774 r mpc_mask
+ffffffff82c29ae0 r dsc_shift
+ffffffff82c29b98 r dsc_mask
+ffffffff82c29e70 r dwbc30_shift
+ffffffff82c29fa4 r dwbc30_mask
+ffffffff82c2a46c r mcif_wb30_shift
+ffffffff82c2a518 r mcif_wb30_mask
+ffffffff82c2a7c4 r aux_mask
+ffffffff82c2a824 r aux_shift
+ffffffff82c2a83c r i2c_shifts
+ffffffff82c2a868 r i2c_masks
+ffffffff82c2a90c r audio_shift
+ffffffff82c2a924 r audio_mask
+ffffffff82c2a960 r se_shift
+ffffffff82c2aa3c r se_mask
+ffffffff82c2ada8 r vpg_shift
+ffffffff82c2add0 r vpg_mask
+ffffffff82c2ae64 r afmt_shift
+ffffffff82c2ae78 r afmt_mask
+ffffffff82c2aebc r hpo_dp_se_shift
+ffffffff82c2aee4 r hpo_dp_se_mask
+ffffffff82c2af84 r apg_shift
+ffffffff82c2af8c r apg_mask
+ffffffff82c2afa4 r hpo_dp_le_shift
+ffffffff82c2afc0 r hpo_dp_le_mask
+ffffffff82c2b024 r hwseq_shift
+ffffffff82c2b0a4 r hwseq_mask
 ffffffff82c2c000 r dcn321_link_enc_funcs
 ffffffff82c2d000 r res_cap_dcn321
 ffffffff82c2d040 r debug_defaults_diags
 ffffffff82c2d1b8 r dccg_shift
 ffffffff82c2d250 r dccg_mask
-ffffffff82c2d4ac r abm_shift
-ffffffff82c2d4c0 r abm_mask
-ffffffff82c2d508 r res_create_funcs
-ffffffff82c2d538 r res_create_maximus_funcs
-ffffffff82c2d568 r plane_cap
-ffffffff82c2d594 r le_shift
-ffffffff82c2d684 r le_mask
-ffffffff82c2da3c r link_enc_feature
-ffffffff82c2da50 r debug_defaults_drv
-ffffffff82c2dbc8 r cs_shift
-ffffffff82c2dbd4 r cs_mask
-ffffffff82c2dbfc r hubbub_shift
-ffffffff82c2dc84 r hubbub_mask
-ffffffff82c2dea0 r vmid_shifts
-ffffffff82c2dea8 r vmid_masks
-ffffffff82c2dec8 r hubp_shift
-ffffffff82c2dfc4 r hubp_mask
-ffffffff82c2e3b4 r tf_shift
-ffffffff82c2e684 r tf_mask
-ffffffff82c2f1c4 r opp_shift
-ffffffff82c2f1fc r opp_mask
-ffffffff82c2f2d0 r optc_shift
-ffffffff82c2f390 r optc_mask
-ffffffff82c2f690 r mpc_shift
-ffffffff82c2f76c r mpc_mask
-ffffffff82c2fad8 r dsc_shift
-ffffffff82c2fb90 r dsc_mask
-ffffffff82c2fe68 r dwbc30_shift
-ffffffff82c2ff9c r dwbc30_mask
-ffffffff82c30464 r mcif_wb30_shift
-ffffffff82c30510 r mcif_wb30_mask
-ffffffff82c307bc r aux_mask
-ffffffff82c3081c r aux_shift
-ffffffff82c30834 r i2c_shifts
-ffffffff82c30860 r i2c_masks
-ffffffff82c30904 r audio_shift
-ffffffff82c3091c r audio_mask
-ffffffff82c30958 r se_shift
-ffffffff82c30a34 r se_mask
-ffffffff82c30da0 r vpg_shift
-ffffffff82c30dc8 r vpg_mask
-ffffffff82c30e5c r afmt_shift
-ffffffff82c30e70 r afmt_mask
-ffffffff82c30eb4 r hpo_dp_se_shift
-ffffffff82c30edc r hpo_dp_se_mask
-ffffffff82c30f7c r apg_shift
-ffffffff82c30f84 r apg_mask
-ffffffff82c30f9c r hpo_dp_le_shift
-ffffffff82c30fb8 r hpo_dp_le_mask
-ffffffff82c3101c r hwseq_shift
-ffffffff82c3109c r hwseq_mask
+ffffffff82c2d4b0 r abm_shift
+ffffffff82c2d4c4 r abm_mask
+ffffffff82c2d510 r res_create_funcs
+ffffffff82c2d540 r res_create_maximus_funcs
+ffffffff82c2d570 r plane_cap
+ffffffff82c2d59c r le_shift
+ffffffff82c2d68c r le_mask
+ffffffff82c2da44 r link_enc_feature
+ffffffff82c2da58 r debug_defaults_drv
+ffffffff82c2dbd0 r cs_shift
+ffffffff82c2dbdc r cs_mask
+ffffffff82c2dc04 r hubbub_shift
+ffffffff82c2dc8c r hubbub_mask
+ffffffff82c2dea8 r vmid_shifts
+ffffffff82c2deb0 r vmid_masks
+ffffffff82c2ded0 r hubp_shift
+ffffffff82c2dfcc r hubp_mask
+ffffffff82c2e3bc r tf_shift
+ffffffff82c2e68c r tf_mask
+ffffffff82c2f1cc r opp_shift
+ffffffff82c2f204 r opp_mask
+ffffffff82c2f2d8 r optc_shift
+ffffffff82c2f398 r optc_mask
+ffffffff82c2f698 r mpc_shift
+ffffffff82c2f774 r mpc_mask
+ffffffff82c2fae0 r dsc_shift
+ffffffff82c2fb98 r dsc_mask
+ffffffff82c2fe70 r dwbc30_shift
+ffffffff82c2ffa4 r dwbc30_mask
+ffffffff82c3046c r mcif_wb30_shift
+ffffffff82c30518 r mcif_wb30_mask
+ffffffff82c307c4 r aux_mask
+ffffffff82c30824 r aux_shift
+ffffffff82c3083c r i2c_shifts
+ffffffff82c30868 r i2c_masks
+ffffffff82c3090c r audio_shift
+ffffffff82c30924 r audio_mask
+ffffffff82c30960 r se_shift
+ffffffff82c30a3c r se_mask
+ffffffff82c30da8 r vpg_shift
+ffffffff82c30dd0 r vpg_mask
+ffffffff82c30e64 r afmt_shift
+ffffffff82c30e78 r afmt_mask
+ffffffff82c30ebc r hpo_dp_se_shift
+ffffffff82c30ee4 r hpo_dp_se_mask
+ffffffff82c30f84 r apg_shift
+ffffffff82c30f8c r apg_mask
+ffffffff82c30fa4 r hpo_dp_le_shift
+ffffffff82c30fc0 r hpo_dp_le_mask
+ffffffff82c31024 r hwseq_shift
+ffffffff82c310a4 r hwseq_mask
 ffffffff82c33000 R dcn10_soc_defaults
 ffffffff82c3308c R dcn10_ip_defaults
 ffffffff82c3e000 R dml20_funcs