--- 7.3/2023-07-01T06:17:07Z/2023-06-15T00:00:00Z/nm-bsd-ot14.txt	Mon Jul  3 12:35:23 2023
+++ 7.3/2023-07-01T06:17:07Z/2023-06-16T00:00:00Z/nm-bsd-ot14.txt	Mon Jul  3 15:24:44 2023
@@ -5443,8 +5443,8 @@ ffffffff81294740 T vmcmd_mutable
 ffffffff812947b0 T vmcmd_randomize
 ffffffff81294910 T exec_setup_stack
 ffffffff81295000 T main
-ffffffff81295800 T start_init
-ffffffff81295af0 T check_console
+ffffffff81295820 T start_init
+ffffffff81295b10 T check_console
 ffffffff81296000 T sys_acct
 ffffffff812961c0 T acct_start
 ffffffff81296220 T acct_process
@@ -5489,27 +5489,27 @@ ffffffff81299000 T clockintr_init
 ffffffff81299300 T clockintr_statvar_init
 ffffffff812993d0 T clockintr_setstatclockrate
 ffffffff812994d0 T clockintr_cpu_init
-ffffffff81299950 T clockqueue_init
-ffffffff812999d0 T clockintr_establish
-ffffffff81299a70 T clockintr_hardclock
-ffffffff81299ae0 T clockintr_statclock
-ffffffff81299c30 T clockintr_schedclock
-ffffffff81299cb0 T clockintr_schedule
-ffffffff81299e30 T clockintr_advance
-ffffffff8129a070 T clockintr_trigger
-ffffffff8129a100 T clockintr_dispatch
-ffffffff8129a5c0 T clockqueue_next
-ffffffff8129a640 T clockintr_cancel_locked
-ffffffff8129a720 T clockintr_schedule_locked
-ffffffff8129a840 T nsec_advance
-ffffffff8129a8c0 T clockqueue_reset_intrclock
-ffffffff8129a9d0 T clockintr_cancel
-ffffffff8129ab50 T clockintr_expiration
-ffffffff8129abc0 T clockintr_nsecuptime
-ffffffff8129ac20 T sysctl_clockintr
-ffffffff8129add0 T db_show_all_clockintr
-ffffffff8129aeb0 T db_show_clockintr_cpu
-ffffffff8129b130 T db_show_clockintr
+ffffffff812998d0 T clockintr_establish
+ffffffff81299970 T clockintr_hardclock
+ffffffff812999e0 T clockintr_statclock
+ffffffff81299b30 T clockintr_schedclock
+ffffffff81299bb0 T clockintr_schedule
+ffffffff81299d30 T clockintr_advance
+ffffffff81299f70 T clockintr_trigger
+ffffffff8129a010 T clockintr_dispatch
+ffffffff8129a4d0 T clockqueue_next
+ffffffff8129a550 T clockintr_cancel_locked
+ffffffff8129a630 T clockintr_schedule_locked
+ffffffff8129a740 T nsec_advance
+ffffffff8129a7c0 T clockqueue_reset_intrclock
+ffffffff8129a8d0 T clockintr_cancel
+ffffffff8129aa50 T clockintr_expiration
+ffffffff8129aac0 T clockintr_nsecuptime
+ffffffff8129ab20 T clockqueue_init
+ffffffff8129aba0 T sysctl_clockintr
+ffffffff8129ad50 T db_show_all_clockintr
+ffffffff8129ae30 T db_show_clockintr_cpu
+ffffffff8129b0b0 T db_show_clockintr
 ffffffff8129c000 T filedesc_init
 ffffffff8129c090 T find_last_set
 ffffffff8129c130 T fd_iterfile
@@ -13032,23 +13032,23 @@ ffffffff81679660 T mp_cpu_start
 ffffffff81679760 T mp_cpu_start_cleanup
 ffffffff81679790 T cpu_match
 ffffffff816797f0 T cpu_attach
-ffffffff81679d70 T cpu_activate
-ffffffff81679e70 T cpu_idle_mwait_cycle
-ffffffff81679f50 T cpu_init_mwait
-ffffffff8167a0f0 T cpu_enter_pages
-ffffffff8167a1d0 T cpu_tsx_disable
-ffffffff8167a260 T cpu_fix_msrs
-ffffffff8167a430 T cpu_init
-ffffffff8167a700 T cpu_start_secondary
-ffffffff8167a8a0 T cpu_init_vmm
-ffffffff8167a950 T cpu_boot_secondary_processors
-ffffffff8167aa80 T cpu_boot_secondary
-ffffffff8167ab50 T cpu_hatch
-ffffffff8167adf0 T cpu_init_msrs
-ffffffff8167aed0 T cpu_debug_dump
-ffffffff8167af80 T patinit
-ffffffff8167afd0 T rdrand
-ffffffff8167b0c0 T wbinvd_on_all_cpus
+ffffffff81679d80 T cpu_activate
+ffffffff81679e80 T cpu_idle_mwait_cycle
+ffffffff81679f60 T cpu_init_mwait
+ffffffff8167a100 T cpu_enter_pages
+ffffffff8167a1e0 T cpu_tsx_disable
+ffffffff8167a270 T cpu_fix_msrs
+ffffffff8167a440 T cpu_init
+ffffffff8167a710 T cpu_start_secondary
+ffffffff8167a8b0 T cpu_init_vmm
+ffffffff8167a960 T cpu_boot_secondary_processors
+ffffffff8167aa90 T cpu_boot_secondary
+ffffffff8167ab60 T cpu_hatch
+ffffffff8167ae00 T cpu_init_msrs
+ffffffff8167aee0 T cpu_debug_dump
+ffffffff8167af90 T patinit
+ffffffff8167afe0 T rdrand
+ffffffff8167b0d0 T wbinvd_on_all_cpus
 ffffffff8167c000 T lapic_hwmask
 ffffffff8167c050 T lapic_hwunmask
 ffffffff8167c0a0 T lapic_setup
@@ -18672,7 +18672,7 @@ ffffffff8194b4a0 T drm_atomic_helper_damage_iter_next
 ffffffff8194b540 T drm_atomic_helper_damage_merged
 ffffffff8194c000 T displayid_iter_edid_begin
 ffffffff8194c050 T __displayid_iter_next
-ffffffff8194c2e0 T displayid_iter_end
+ffffffff8194c310 T displayid_iter_end
 ffffffff8194d000 T drm_mode_create_dumb
 ffffffff8194d0c0 T drm_mode_create_dumb_ioctl
 ffffffff8194d180 T drm_mode_mmap_dumb_ioctl
@@ -20842,19 +20842,19 @@ ffffffff81a41a10 t intel_dp_set_common_rates
 ffffffff81a41bb0 T intel_dp_mst_suspend
 ffffffff81a41c50 T intel_dp_mst_resume
 ffffffff81a41d00 t intel_dp_compute_link_config
-ffffffff81a42a30 t intel_dp_dsc_get_slice_count
-ffffffff81a42ba0 t intel_dp_set_sink_rates
-ffffffff81a42dd0 t intel_dp_check_device_service_irq
-ffffffff81a433a0 t intel_dp_force
-ffffffff81a434e0 t intel_dp_connector_register
-ffffffff81a435c0 t intel_dp_connector_unregister
-ffffffff81a43620 t intel_dp_oob_hotplug_event
-ffffffff81a436a0 t intel_dp_set_edid
-ffffffff81a43ad0 t intel_dp_get_modes
-ffffffff81a43bd0 t intel_dp_detect
-ffffffff81a444c0 t intel_dp_mode_valid
-ffffffff81a44c60 t intel_dp_connector_atomic_check
-ffffffff81a44fa0 t intel_dp_get_dsc_sink_cap
+ffffffff81a42aa0 t intel_dp_dsc_get_slice_count
+ffffffff81a42c10 t intel_dp_set_sink_rates
+ffffffff81a42e40 t intel_dp_check_device_service_irq
+ffffffff81a43410 t intel_dp_force
+ffffffff81a43550 t intel_dp_connector_register
+ffffffff81a43630 t intel_dp_connector_unregister
+ffffffff81a43690 t intel_dp_oob_hotplug_event
+ffffffff81a43710 t intel_dp_set_edid
+ffffffff81a43b40 t intel_dp_get_modes
+ffffffff81a43c40 t intel_dp_detect
+ffffffff81a44530 t intel_dp_mode_valid
+ffffffff81a44cd0 t intel_dp_connector_atomic_check
+ffffffff81a45010 t intel_dp_get_dsc_sink_cap
 ffffffff81a46000 T intel_dp_aux_fini
 ffffffff81a46020 T intel_dp_aux_init
 ffffffff81a46200 t xelpdp_aux_ctl_reg
@@ -26107,12 +26107,12 @@ ffffffff81d726d0 T amdgpu_get_gfx_off_residency
 ffffffff81d72740 T amdgpu_get_gfx_off_entrycount
 ffffffff81d727b0 T amdgpu_get_gfx_off_status
 ffffffff81d72820 T amdgpu_gfx_ras_late_init
-ffffffff81d728e0 T amdgpu_gfx_process_ras_data_cb
-ffffffff81d72960 T amdgpu_gfx_cp_ecc_error_irq
-ffffffff81d72a30 T amdgpu_kiq_rreg
-ffffffff81d72cb0 T amdgpu_kiq_wreg
-ffffffff81d72ef0 T amdgpu_gfx_get_num_kcq
-ffffffff81d72f70 T amdgpu_gfx_cp_init_microcode
+ffffffff81d72900 T amdgpu_gfx_process_ras_data_cb
+ffffffff81d72980 T amdgpu_gfx_cp_ecc_error_irq
+ffffffff81d72a50 T amdgpu_kiq_rreg
+ffffffff81d72cd0 T amdgpu_kiq_wreg
+ffffffff81d72f10 T amdgpu_gfx_get_num_kcq
+ffffffff81d72f90 T amdgpu_gfx_cp_init_microcode
 ffffffff81d74000 T amdgpu_gmc_pdb0_alloc
 ffffffff81d74290 t amdgpu_bo_unreserve
 ffffffff81d74370 T amdgpu_gmc_get_pde_for_bo
@@ -26933,96 +26933,97 @@ ffffffff81de1b00 t gfx_v10_0_wait_for_idle
 ffffffff81de1be0 t gfx_v10_0_soft_reset
 ffffffff81de1f30 t gfx_v10_0_set_clockgating_state
 ffffffff81de21d0 t gfx_v10_0_set_powergating_state
-ffffffff81de23f0 t gfx_v10_0_get_clockgating_state
-ffffffff81de2500 t gfx10_kiq_set_resources
-ffffffff81de2830 t gfx10_kiq_map_queues
-ffffffff81de2bc0 t gfx10_kiq_unmap_queues
-ffffffff81de2fc0 t gfx10_kiq_query_status
-ffffffff81de32c0 t gfx10_kiq_invalidate_tlbs
-ffffffff81de33e0 t gfx_v10_0_ring_get_rptr_compute
-ffffffff81de3410 t gfx_v10_0_ring_get_wptr_compute
-ffffffff81de3480 t gfx_v10_0_ring_set_wptr_compute
-ffffffff81de35c0 t gfx_v10_0_ring_emit_ib_compute
-ffffffff81de3910 t gfx_v10_0_ring_emit_fence_kiq
-ffffffff81de3d50 t gfx_v10_0_ring_test_ring
-ffffffff81de3fc0 t gfx_v10_0_ring_test_ib
-ffffffff81de4270 t gfx_v10_0_ring_emit_rreg
-ffffffff81de4510 t gfx_v10_0_ring_emit_wreg
-ffffffff81de4750 t gfx_v10_0_ring_emit_reg_wait
-ffffffff81de47a0 t gfx_v10_0_ring_emit_reg_write_reg_wait
-ffffffff81de4830 t gfx_v10_0_wait_reg_mem
-ffffffff81de4b60 t gfx_v10_0_ring_get_rptr_gfx
-ffffffff81de4b90 t gfx_v10_0_ring_get_wptr_gfx
-ffffffff81de4ca0 t gfx_v10_0_ring_set_wptr_gfx
-ffffffff81de4eb0 t gfx_v10_0_ring_emit_ib_gfx
-ffffffff81de5560 t gfx_v10_0_ring_emit_fence
-ffffffff81de5930 t gfx_v10_0_ring_emit_pipeline_sync
-ffffffff81de5990 t gfx_v10_0_ring_emit_vm_flush
-ffffffff81de5b60 t gfx_v10_0_ring_emit_hdp_flush
-ffffffff81de5c30 t gfx_v10_0_ring_emit_gds_switch
-ffffffff81de5d10 t gfx_v10_0_ring_emit_init_cond_exec
-ffffffff81de5f40 t gfx_v10_0_ring_emit_patch_cond_exec
-ffffffff81de6000 t gfx_v10_0_ring_emit_sb
-ffffffff81de60f0 t gfx_v10_0_ring_emit_cntxcntl
-ffffffff81de65e0 t gfx_v10_0_ring_emit_frame_cntl
-ffffffff81de66f0 t gfx_v10_0_ring_soft_recovery
-ffffffff81de6760 t gfx_v10_0_ring_preempt_ib
-ffffffff81de68d0 t gfx_v10_0_emit_mem_sync
-ffffffff81de6c10 t gfx_v10_0_write_data_to_reg
-ffffffff81de6e20 t gfx_v10_0_set_eop_interrupt_state
-ffffffff81de6f00 t gfx_v10_0_eop_irq
-ffffffff81de70d0 t gfx_v10_0_set_gfx_eop_interrupt_state
-ffffffff81de7260 t gfx_v10_0_set_compute_eop_interrupt_state
-ffffffff81de7410 t gfx_v10_0_kiq_set_interrupt_state
-ffffffff81de76f0 t gfx_v10_0_kiq_irq
-ffffffff81de7770 t gfx_v10_0_set_priv_reg_fault_state
-ffffffff81de7890 t gfx_v10_0_priv_reg_irq
-ffffffff81de78f0 t gfx_v10_0_handle_priv_fault
-ffffffff81de7a80 t gfx_v10_0_set_priv_inst_fault_state
-ffffffff81de7ba0 t gfx_v10_0_priv_inst_irq
-ffffffff81de7c00 t gfx_v10_0_is_rlc_enabled
-ffffffff81de7c80 t gfx_v10_0_set_safe_mode
-ffffffff81de7f20 t gfx_v10_0_unset_safe_mode
-ffffffff81de7fd0 t gfx_v10_0_rlc_init
-ffffffff81de8050 t gfx_v10_0_get_csb_size
-ffffffff81de80b0 t gfx_v10_0_get_csb_buffer
-ffffffff81de8230 t gfx_v10_0_rlc_resume
-ffffffff81de8d30 t gfx_v10_0_rlc_stop
-ffffffff81de8e10 t gfx_v10_0_rlc_reset
-ffffffff81de8fb0 t gfx_v10_0_rlc_start
-ffffffff81de9150 t gfx_v10_0_update_spm_vmid
-ffffffff81de9280 t gfx_v10_0_wait_for_rlc_autoload_complete
-ffffffff81de9e10 t gfx_v10_0_init_csb
-ffffffff81dea0e0 t gfx_v10_0_is_rlcg_access_range
-ffffffff81dea110 t gfx_v10_0_gfx_mqd_init
-ffffffff81dea4f0 t gfx_v10_0_compute_mqd_init
-ffffffff81dea990 t amdgpu_bo_unreserve
-ffffffff81deaa70 t gfx_v10_0_get_gpu_clock_counter
-ffffffff81deaf70 t gfx_v10_0_select_se_sh
-ffffffff81deb010 t gfx_v10_0_read_wave_data
-ffffffff81deb270 t gfx_v10_0_read_wave_vgprs
-ffffffff81deb2a0 t gfx_v10_0_read_wave_sgprs
-ffffffff81deb320 t gfx_v10_0_select_me_pipe_q
-ffffffff81deb340 t gfx_v10_0_init_spm_golden_registers
-ffffffff81deb3b0 t gfx_v10_0_update_perfmon_mgcg
-ffffffff81deb4d0 t wave_read_ind
-ffffffff81deb5b0 t wave_read_regs
-ffffffff81deb710 t gfx_v10_0_cp_resume
-ffffffff81dee350 t gfx_v10_3_get_disabled_sa
-ffffffff81dee460 t gfx_v10_0_get_rb_active_bitmap
-ffffffff81dee580 t gfx_v10_0_get_wgp_active_bitmap_per_sh
-ffffffff81dee690 t gfx_v10_0_enable_gui_idle_interrupt
-ffffffff81dee7a0 t gfx_v10_0_cp_gfx_enable
-ffffffff81dee9e0 t gfx_v10_0_cp_compute_enable
-ffffffff81deeb70 t amdgpu_bo_reserve
-ffffffff81deecf0 t gfx_v10_0_kiq_init_register
-ffffffff81defb60 t gfx_v10_0_cp_gfx_switch_pipe
-ffffffff81defc60 t gfx_v10_0_cp_gfx_set_doorbell
-ffffffff81deff30 t gfx_v10_0_cp_gfx_start
-ffffffff81df0910 t gfx_v10_0_update_fine_grain_clock_gating
-ffffffff81df0c30 t gfx_v10_0_update_medium_grain_clock_gating
-ffffffff81df1350 t gfx_v10_0_update_3d_clock_gating
-ffffffff81df1710 t gfx_v10_0_update_coarse_grain_clock_gating
+ffffffff81de2290 t gfx_v10_0_get_clockgating_state
+ffffffff81de23a0 t gfx10_kiq_set_resources
+ffffffff81de26d0 t gfx10_kiq_map_queues
+ffffffff81de2a60 t gfx10_kiq_unmap_queues
+ffffffff81de2e60 t gfx10_kiq_query_status
+ffffffff81de3160 t gfx10_kiq_invalidate_tlbs
+ffffffff81de3280 t gfx_v10_0_ring_get_rptr_compute
+ffffffff81de32b0 t gfx_v10_0_ring_get_wptr_compute
+ffffffff81de3320 t gfx_v10_0_ring_set_wptr_compute
+ffffffff81de3460 t gfx_v10_0_ring_emit_ib_compute
+ffffffff81de37b0 t gfx_v10_0_ring_emit_fence_kiq
+ffffffff81de3bf0 t gfx_v10_0_ring_test_ring
+ffffffff81de3e60 t gfx_v10_0_ring_test_ib
+ffffffff81de4110 t gfx_v10_0_ring_emit_rreg
+ffffffff81de43b0 t gfx_v10_0_ring_emit_wreg
+ffffffff81de45f0 t gfx_v10_0_ring_emit_reg_wait
+ffffffff81de4640 t gfx_v10_0_ring_emit_reg_write_reg_wait
+ffffffff81de46d0 t gfx_v10_0_wait_reg_mem
+ffffffff81de4a00 t gfx_v10_0_ring_get_rptr_gfx
+ffffffff81de4a30 t gfx_v10_0_ring_get_wptr_gfx
+ffffffff81de4b40 t gfx_v10_0_ring_set_wptr_gfx
+ffffffff81de4d50 t gfx_v10_0_ring_emit_ib_gfx
+ffffffff81de5400 t gfx_v10_0_ring_emit_fence
+ffffffff81de57d0 t gfx_v10_0_ring_emit_pipeline_sync
+ffffffff81de5830 t gfx_v10_0_ring_emit_vm_flush
+ffffffff81de5a00 t gfx_v10_0_ring_emit_hdp_flush
+ffffffff81de5ad0 t gfx_v10_0_ring_emit_gds_switch
+ffffffff81de5bb0 t gfx_v10_0_ring_emit_init_cond_exec
+ffffffff81de5de0 t gfx_v10_0_ring_emit_patch_cond_exec
+ffffffff81de5ea0 t gfx_v10_0_ring_emit_sb
+ffffffff81de5f90 t gfx_v10_0_ring_emit_cntxcntl
+ffffffff81de6480 t gfx_v10_0_ring_emit_frame_cntl
+ffffffff81de6590 t gfx_v10_0_ring_soft_recovery
+ffffffff81de6600 t gfx_v10_0_ring_preempt_ib
+ffffffff81de6770 t gfx_v10_0_emit_mem_sync
+ffffffff81de6ab0 t gfx_v10_0_write_data_to_reg
+ffffffff81de6cc0 t gfx_v10_0_set_eop_interrupt_state
+ffffffff81de6da0 t gfx_v10_0_eop_irq
+ffffffff81de6f70 t gfx_v10_0_set_gfx_eop_interrupt_state
+ffffffff81de7100 t gfx_v10_0_set_compute_eop_interrupt_state
+ffffffff81de72b0 t gfx_v10_0_kiq_set_interrupt_state
+ffffffff81de7590 t gfx_v10_0_kiq_irq
+ffffffff81de7610 t gfx_v10_0_set_priv_reg_fault_state
+ffffffff81de7730 t gfx_v10_0_priv_reg_irq
+ffffffff81de7790 t gfx_v10_0_handle_priv_fault
+ffffffff81de7920 t gfx_v10_0_set_priv_inst_fault_state
+ffffffff81de7a40 t gfx_v10_0_priv_inst_irq
+ffffffff81de7aa0 t gfx_v10_0_is_rlc_enabled
+ffffffff81de7b20 t gfx_v10_0_set_safe_mode
+ffffffff81de7dc0 t gfx_v10_0_unset_safe_mode
+ffffffff81de7e70 t gfx_v10_0_rlc_init
+ffffffff81de7ef0 t gfx_v10_0_get_csb_size
+ffffffff81de7f50 t gfx_v10_0_get_csb_buffer
+ffffffff81de80d0 t gfx_v10_0_rlc_resume
+ffffffff81de8bd0 t gfx_v10_0_rlc_stop
+ffffffff81de8cb0 t gfx_v10_0_rlc_reset
+ffffffff81de8e50 t gfx_v10_0_rlc_start
+ffffffff81de8ff0 t gfx_v10_0_update_spm_vmid
+ffffffff81de9120 t gfx_v10_0_wait_for_rlc_autoload_complete
+ffffffff81de9cb0 t gfx_v10_0_init_csb
+ffffffff81de9f80 t gfx_v10_0_is_rlcg_access_range
+ffffffff81de9fb0 t gfx_v10_0_gfx_mqd_init
+ffffffff81dea390 t gfx_v10_0_compute_mqd_init
+ffffffff81dea830 t amdgpu_bo_unreserve
+ffffffff81dea910 t gfx_v10_0_get_gpu_clock_counter
+ffffffff81deae10 t gfx_v10_0_select_se_sh
+ffffffff81deaeb0 t gfx_v10_0_read_wave_data
+ffffffff81deb110 t gfx_v10_0_read_wave_vgprs
+ffffffff81deb140 t gfx_v10_0_read_wave_sgprs
+ffffffff81deb1c0 t gfx_v10_0_select_me_pipe_q
+ffffffff81deb1e0 t gfx_v10_0_init_spm_golden_registers
+ffffffff81deb250 t gfx_v10_0_update_perfmon_mgcg
+ffffffff81deb370 t wave_read_ind
+ffffffff81deb450 t wave_read_regs
+ffffffff81deb5b0 t gfx_v10_0_cp_resume
+ffffffff81dee1f0 t gfx_v10_3_get_disabled_sa
+ffffffff81dee300 t gfx_v10_0_get_rb_active_bitmap
+ffffffff81dee420 t gfx_v10_0_get_wgp_active_bitmap_per_sh
+ffffffff81dee530 t gfx_v10_0_enable_gui_idle_interrupt
+ffffffff81dee640 t gfx_v10_0_cp_gfx_enable
+ffffffff81dee880 t gfx_v10_0_cp_compute_enable
+ffffffff81deea10 t amdgpu_bo_reserve
+ffffffff81deeb90 t gfx_v10_0_kiq_init_register
+ffffffff81defa00 t gfx_v10_0_cp_gfx_switch_pipe
+ffffffff81defb00 t gfx_v10_0_cp_gfx_set_doorbell
+ffffffff81defdd0 t gfx_v10_0_cp_gfx_start
+ffffffff81df07b0 t gfx_v10_0_update_fine_grain_clock_gating
+ffffffff81df0ad0 t gfx_v10_0_update_medium_grain_clock_gating
+ffffffff81df11f0 t gfx_v10_0_update_3d_clock_gating
+ffffffff81df15b0 t gfx_v10_0_update_coarse_grain_clock_gating
+ffffffff81df1970 t gfx_v10_cntl_pg
 ffffffff81df2000 t gfx_v11_0_early_init
 ffffffff81df23a0 t gfx_v11_0_late_init
 ffffffff81df2410 t gfx_v11_0_sw_init
@@ -27038,87 +27039,88 @@ ffffffff81df8030 t gfx_v11_0_soft_reset
 ffffffff81df8d10 t gfx_v11_0_post_soft_reset
 ffffffff81df8d20 t gfx_v11_0_set_clockgating_state
 ffffffff81df9900 t gfx_v11_0_set_powergating_state
-ffffffff81df9af0 t gfx_v11_0_get_clockgating_state
-ffffffff81df9cc0 t gfx11_kiq_set_resources
-ffffffff81df9ff0 t gfx11_kiq_map_queues
-ffffffff81dfa380 t gfx11_kiq_unmap_queues
-ffffffff81dfa780 t gfx11_kiq_query_status
-ffffffff81dfaa80 t gfx11_kiq_invalidate_tlbs
-ffffffff81dfaba0 t gfx_v11_0_ring_get_rptr_compute
-ffffffff81dfabd0 t gfx_v11_0_ring_get_wptr_compute
-ffffffff81dfac40 t gfx_v11_0_ring_set_wptr_compute
-ffffffff81dfad80 t gfx_v11_0_ring_emit_ib_compute
-ffffffff81dfb0d0 t gfx_v11_0_ring_emit_fence_kiq
-ffffffff81dfb510 t gfx_v11_0_ring_test_ring
-ffffffff81dfb7a0 t gfx_v11_0_ring_test_ib
-ffffffff81dfba60 t gfx_v11_0_ring_emit_rreg
-ffffffff81dfbd00 t gfx_v11_0_ring_emit_wreg
-ffffffff81dfbf40 t gfx_v11_0_ring_emit_reg_wait
-ffffffff81dfbf90 t gfx_v11_0_ring_emit_reg_write_reg_wait
-ffffffff81dfc000 t gfx_v11_0_wait_reg_mem
-ffffffff81dfc330 t gfx_v11_0_ring_get_rptr_gfx
-ffffffff81dfc360 t gfx_v11_0_ring_get_wptr_gfx
-ffffffff81dfc470 t gfx_v11_0_ring_set_wptr_gfx
-ffffffff81dfc680 t gfx_v11_0_ring_emit_ib_gfx
-ffffffff81dfcd20 t gfx_v11_0_ring_emit_fence
-ffffffff81dfd0f0 t gfx_v11_0_ring_emit_pipeline_sync
-ffffffff81dfd150 t gfx_v11_0_ring_emit_vm_flush
-ffffffff81dfd320 t gfx_v11_0_ring_emit_hdp_flush
-ffffffff81dfd3f0 t gfx_v11_0_ring_emit_gds_switch
-ffffffff81dfd4d0 t gfx_v11_0_ring_emit_init_cond_exec
-ffffffff81dfd700 t gfx_v11_0_ring_emit_patch_cond_exec
-ffffffff81dfd7c0 t gfx_v11_0_ring_emit_cntxcntl
-ffffffff81dfd920 t gfx_v11_0_ring_emit_frame_cntl
-ffffffff81dfda30 t gfx_v11_0_ring_soft_recovery
-ffffffff81dfdaa0 t gfx_v11_0_ring_preempt_ib
-ffffffff81dfdc10 t gfx_v11_0_emit_mem_sync
-ffffffff81dfdf50 t gfx_v11_0_write_data_to_reg
-ffffffff81dfe160 t gfx_v11_0_set_eop_interrupt_state
-ffffffff81dfe1f0 t gfx_v11_0_eop_irq
-ffffffff81dfe3c0 t gfx_v11_0_set_gfx_eop_interrupt_state
-ffffffff81dfe550 t gfx_v11_0_set_compute_eop_interrupt_state
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-ffffffff81dfe800 t gfx_v11_0_priv_reg_irq
-ffffffff81dfe860 t gfx_v11_0_handle_priv_fault
-ffffffff81dfe9f0 t gfx_v11_0_set_priv_inst_fault_state
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-ffffffff81dfeb70 t gfx_v11_0_is_rlc_enabled
-ffffffff81dfebf0 t gfx_v11_0_set_safe_mode
-ffffffff81dfed40 t gfx_v11_0_unset_safe_mode
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-ffffffff81dfee90 t gfx_v11_0_get_csb_buffer
-ffffffff81dff010 t gfx_v11_0_rlc_resume
-ffffffff81dffd30 t gfx_v11_0_rlc_stop
-ffffffff81dffe10 t gfx_v11_0_rlc_reset
-ffffffff81dfffb0 t gfx_v11_0_rlc_start
-ffffffff81e00150 t gfx_v11_0_update_spm_vmid
-ffffffff81e00250 t gfx_v11_0_init_csb
-ffffffff81e003d0 t gfx_v11_0_gfx_mqd_init
-ffffffff81e007a0 t gfx_v11_0_compute_mqd_init
-ffffffff81e00cc0 t amdgpu_bo_unreserve
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-ffffffff81e00ed0 t gfx_v11_0_select_se_sh
-ffffffff81e00f70 t gfx_v11_0_read_wave_data
-ffffffff81e011b0 t gfx_v11_0_read_wave_vgprs
-ffffffff81e011e0 t gfx_v11_0_read_wave_sgprs
-ffffffff81e01260 t gfx_v11_0_select_me_pipe_q
-ffffffff81e01280 t gfx_v11_0_update_perf_clk
-ffffffff81e013b0 t wave_read_ind
-ffffffff81e01490 t wave_read_regs
-ffffffff81e015f0 t gfx_v11_0_disable_gpa_mode
-ffffffff81e01780 t gfx_v11_0_cp_resume
-ffffffff81e05820 t gfx_v11_0_config_me_cache
-ffffffff81e05bc0 t gfx_v11_0_config_pfp_cache
-ffffffff81e05f60 t gfx_v11_0_config_mec_cache
-ffffffff81e06300 t gfx_v11_0_enable_gui_idle_interrupt
-ffffffff81e06410 t gfx_v11_0_cp_compute_enable
-ffffffff81e065e0 t gfx_v11_0_cp_gfx_enable
-ffffffff81e067d0 t amdgpu_bo_reserve
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-ffffffff81e077c0 t gfx_v11_0_cp_gfx_switch_pipe
-ffffffff81e078a0 t gfx_v11_0_cp_gfx_set_doorbell
-ffffffff81e07a80 t gfx_v11_0_cp_gfx_start
+ffffffff81df99a0 t gfx_v11_0_get_clockgating_state
+ffffffff81df9b70 t gfx11_kiq_set_resources
+ffffffff81df9ea0 t gfx11_kiq_map_queues
+ffffffff81dfa230 t gfx11_kiq_unmap_queues
+ffffffff81dfa630 t gfx11_kiq_query_status
+ffffffff81dfa930 t gfx11_kiq_invalidate_tlbs
+ffffffff81dfaa50 t gfx_v11_0_ring_get_rptr_compute
+ffffffff81dfaa80 t gfx_v11_0_ring_get_wptr_compute
+ffffffff81dfaaf0 t gfx_v11_0_ring_set_wptr_compute
+ffffffff81dfac30 t gfx_v11_0_ring_emit_ib_compute
+ffffffff81dfaf80 t gfx_v11_0_ring_emit_fence_kiq
+ffffffff81dfb3c0 t gfx_v11_0_ring_test_ring
+ffffffff81dfb650 t gfx_v11_0_ring_test_ib
+ffffffff81dfb910 t gfx_v11_0_ring_emit_rreg
+ffffffff81dfbbb0 t gfx_v11_0_ring_emit_wreg
+ffffffff81dfbdf0 t gfx_v11_0_ring_emit_reg_wait
+ffffffff81dfbe40 t gfx_v11_0_ring_emit_reg_write_reg_wait
+ffffffff81dfbeb0 t gfx_v11_0_wait_reg_mem
+ffffffff81dfc1e0 t gfx_v11_0_ring_get_rptr_gfx
+ffffffff81dfc210 t gfx_v11_0_ring_get_wptr_gfx
+ffffffff81dfc320 t gfx_v11_0_ring_set_wptr_gfx
+ffffffff81dfc530 t gfx_v11_0_ring_emit_ib_gfx
+ffffffff81dfcbd0 t gfx_v11_0_ring_emit_fence
+ffffffff81dfcfa0 t gfx_v11_0_ring_emit_pipeline_sync
+ffffffff81dfd000 t gfx_v11_0_ring_emit_vm_flush
+ffffffff81dfd1d0 t gfx_v11_0_ring_emit_hdp_flush
+ffffffff81dfd2a0 t gfx_v11_0_ring_emit_gds_switch
+ffffffff81dfd380 t gfx_v11_0_ring_emit_init_cond_exec
+ffffffff81dfd5b0 t gfx_v11_0_ring_emit_patch_cond_exec
+ffffffff81dfd670 t gfx_v11_0_ring_emit_cntxcntl
+ffffffff81dfd7d0 t gfx_v11_0_ring_emit_frame_cntl
+ffffffff81dfd8e0 t gfx_v11_0_ring_soft_recovery
+ffffffff81dfd950 t gfx_v11_0_ring_preempt_ib
+ffffffff81dfdac0 t gfx_v11_0_emit_mem_sync
+ffffffff81dfde00 t gfx_v11_0_write_data_to_reg
+ffffffff81dfe010 t gfx_v11_0_set_eop_interrupt_state
+ffffffff81dfe0a0 t gfx_v11_0_eop_irq
+ffffffff81dfe270 t gfx_v11_0_set_gfx_eop_interrupt_state
+ffffffff81dfe400 t gfx_v11_0_set_compute_eop_interrupt_state
+ffffffff81dfe590 t gfx_v11_0_set_priv_reg_fault_state
+ffffffff81dfe6b0 t gfx_v11_0_priv_reg_irq
+ffffffff81dfe710 t gfx_v11_0_handle_priv_fault
+ffffffff81dfe8a0 t gfx_v11_0_set_priv_inst_fault_state
+ffffffff81dfe9c0 t gfx_v11_0_priv_inst_irq
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+ffffffff81dfece0 t gfx_v11_0_get_csb_size
+ffffffff81dfed40 t gfx_v11_0_get_csb_buffer
+ffffffff81dfeec0 t gfx_v11_0_rlc_resume
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+ffffffff81dffcc0 t gfx_v11_0_rlc_reset
+ffffffff81dffe60 t gfx_v11_0_rlc_start
+ffffffff81e00000 t gfx_v11_0_update_spm_vmid
+ffffffff81e00100 t gfx_v11_0_init_csb
+ffffffff81e00280 t gfx_v11_0_gfx_mqd_init
+ffffffff81e00650 t gfx_v11_0_compute_mqd_init
+ffffffff81e00b70 t amdgpu_bo_unreserve
+ffffffff81e00c50 t gfx_v11_0_get_gpu_clock_counter
+ffffffff81e00fb0 t gfx_v11_0_select_se_sh
+ffffffff81e01050 t gfx_v11_0_read_wave_data
+ffffffff81e01290 t gfx_v11_0_read_wave_vgprs
+ffffffff81e012c0 t gfx_v11_0_read_wave_sgprs
+ffffffff81e01340 t gfx_v11_0_select_me_pipe_q
+ffffffff81e01360 t gfx_v11_0_update_perf_clk
+ffffffff81e01490 t wave_read_ind
+ffffffff81e01570 t wave_read_regs
+ffffffff81e016d0 t gfx_v11_0_disable_gpa_mode
+ffffffff81e01860 t gfx_v11_0_cp_resume
+ffffffff81e05900 t gfx_v11_0_config_me_cache
+ffffffff81e05ca0 t gfx_v11_0_config_pfp_cache
+ffffffff81e06040 t gfx_v11_0_config_mec_cache
+ffffffff81e063e0 t gfx_v11_0_enable_gui_idle_interrupt
+ffffffff81e064f0 t gfx_v11_0_cp_compute_enable
+ffffffff81e066c0 t gfx_v11_0_cp_gfx_enable
+ffffffff81e068b0 t amdgpu_bo_reserve
+ffffffff81e06a30 t gfx_v11_0_kiq_init_register
+ffffffff81e078a0 t gfx_v11_0_cp_gfx_switch_pipe
+ffffffff81e07980 t gfx_v11_0_cp_gfx_set_doorbell
+ffffffff81e07b60 t gfx_v11_0_cp_gfx_start
+ffffffff81e08420 t gfx_v11_cntl_pg
 ffffffff81e09000 t gfx_v8_0_early_init
 ffffffff81e09320 t gfx_v8_0_late_init
 ffffffff81e09a20 t gfx_v8_0_sw_init
@@ -27412,9 +27414,9 @@ ffffffff81e41310 t gmc_v11_0_map_mtype
 ffffffff81e41360 t gmc_v11_0_get_vm_pde
 ffffffff81e41460 t gmc_v11_0_get_vm_pte
 ffffffff81e41510 t gmc_v11_0_get_vbios_fb_size
-ffffffff81e41540 t gmc_v11_0_vm_fault_interrupt_state
-ffffffff81e415b0 t gmc_v11_0_process_interrupt
-ffffffff81e417d0 t gmc_v11_0_ecc_interrupt_state
+ffffffff81e41680 t gmc_v11_0_vm_fault_interrupt_state
+ffffffff81e416f0 t gmc_v11_0_process_interrupt
+ffffffff81e41910 t gmc_v11_0_ecc_interrupt_state
 ffffffff81e42000 t gmc_v7_0_early_init
 ffffffff81e42090 t gmc_v7_0_late_init
 ffffffff81e420e0 t gmc_v7_0_sw_init
@@ -29265,35 +29267,35 @@ ffffffff81f50de0 t bios_parser_get_connectors_number
 ffffffff81f50f70 t bios_parser_get_connector_id
 ffffffff81f51000 t bios_parser_get_src_obj
 ffffffff81f512a0 t bios_parser_get_i2c_info
-ffffffff81f51510 t bios_parser_get_hpd_info
-ffffffff81f51680 t bios_parser_get_device_tag
-ffffffff81f51950 t bios_parser_get_spread_spectrum_info
-ffffffff81f51d10 t bios_parser_get_ss_entry_number
-ffffffff81f51d40 t bios_parser_get_embedded_panel_info
-ffffffff81f51f40 t bios_parser_get_gpio_pin_info
-ffffffff81f52060 t bios_parser_get_encoder_cap_info
-ffffffff81f521d0 t bios_parser_is_accelerated_mode
-ffffffff81f521e0 t bios_parser_set_scratch_critical_state
-ffffffff81f521f0 t bios_parser_is_device_id_supported
-ffffffff81f52270 t bios_parser_encoder_control
-ffffffff81f522b0 t bios_parser_transmitter_control
-ffffffff81f522f0 t bios_parser_enable_crtc
-ffffffff81f52340 t bios_parser_set_pixel_clock
-ffffffff81f52380 t bios_parser_set_dce_clock
-ffffffff81f523c0 t bios_parser_program_crtc_timing
-ffffffff81f52400 t bios_parser_enable_disp_power_gating
-ffffffff81f52440 t firmware_parser_destroy
-ffffffff81f52500 t bios_get_board_layout_info
-ffffffff81f529b0 t bios_parser_pack_data_tables
-ffffffff81f529e0 t bios_get_atom_dc_golden_table
-ffffffff81f52b20 t bios_parser_enable_lvtma_control
-ffffffff81f52b70 t bios_parser_get_soc_bb_info
-ffffffff81f52c80 t bios_parser_get_disp_connector_caps_info
-ffffffff81f52de0 t bios_parser_get_lttpr_caps
-ffffffff81f52f30 t bios_parser_get_lttpr_interop
-ffffffff81f53070 t bios_parser_get_connector_speed_cap_info
-ffffffff81f531c0 t get_bios_object
-ffffffff81f53320 t get_bios_object_from_path_v3
+ffffffff81f51530 t bios_parser_get_hpd_info
+ffffffff81f516a0 t bios_parser_get_device_tag
+ffffffff81f51970 t bios_parser_get_spread_spectrum_info
+ffffffff81f51d30 t bios_parser_get_ss_entry_number
+ffffffff81f51d60 t bios_parser_get_embedded_panel_info
+ffffffff81f51f60 t bios_parser_get_gpio_pin_info
+ffffffff81f52080 t bios_parser_get_encoder_cap_info
+ffffffff81f521f0 t bios_parser_is_accelerated_mode
+ffffffff81f52200 t bios_parser_set_scratch_critical_state
+ffffffff81f52210 t bios_parser_is_device_id_supported
+ffffffff81f52290 t bios_parser_encoder_control
+ffffffff81f522d0 t bios_parser_transmitter_control
+ffffffff81f52310 t bios_parser_enable_crtc
+ffffffff81f52360 t bios_parser_set_pixel_clock
+ffffffff81f523a0 t bios_parser_set_dce_clock
+ffffffff81f523e0 t bios_parser_program_crtc_timing
+ffffffff81f52420 t bios_parser_enable_disp_power_gating
+ffffffff81f52460 t firmware_parser_destroy
+ffffffff81f52520 t bios_get_board_layout_info
+ffffffff81f529d0 t bios_parser_pack_data_tables
+ffffffff81f52a00 t bios_get_atom_dc_golden_table
+ffffffff81f52b40 t bios_parser_enable_lvtma_control
+ffffffff81f52b90 t bios_parser_get_soc_bb_info
+ffffffff81f52ca0 t bios_parser_get_disp_connector_caps_info
+ffffffff81f52e00 t bios_parser_get_lttpr_caps
+ffffffff81f52f50 t bios_parser_get_lttpr_interop
+ffffffff81f53090 t bios_parser_get_connector_speed_cap_info
+ffffffff81f531e0 t get_bios_object
+ffffffff81f53340 t get_bios_object_from_path_v3
 ffffffff81f54000 T object_id_from_bios_object_id
 ffffffff81f55000 T bios_get_image
 ffffffff81f55050 T bios_is_accelerated_mode
@@ -30058,8 +30060,8 @@ ffffffff81fbfb80 T dc_dmub_srv_p_state_delegate
 ffffffff81fbfed0 T dc_dmub_srv_query_caps_cmd
 ffffffff81fbffc0 T dc_dmub_srv_get_visual_confirm_color_cmd
 ffffffff81fc0190 T dc_dmub_setup_subvp_dmub_command
-ffffffff81fc0af0 T dc_dmub_srv_get_diagnostic_data
-ffffffff81fc0b30 T dc_send_update_cursor_info_to_dmu
+ffffffff81fc0b30 T dc_dmub_srv_get_diagnostic_data
+ffffffff81fc0b70 T dc_send_update_cursor_info_to_dmu
 ffffffff81fc1000 T dc_edid_parser_send_cea
 ffffffff81fc10b0 T dc_edid_parser_recv_cea_ack
 ffffffff81fc1140 T dc_edid_parser_recv_amd_vsdb
@@ -31706,15 +31708,15 @@ ffffffff820e54a0 T dcn32_subvp_update_force_pstate
 ffffffff820e5610 T dcn32_update_mall_sel
 ffffffff820e5790 T dcn32_program_mall_pipe_config
 ffffffff820e5870 T dcn32_init_hw
-ffffffff820e6070 T dcn32_update_odm
-ffffffff820e6680 T dcn32_calculate_dccg_k1_k2_values
-ffffffff820e6880 T dcn32_is_dp_dig_pixel_rate_div_policy
-ffffffff820e6910 T dcn32_set_pixels_per_cycle
-ffffffff820e6a50 T dcn32_unblank_stream
-ffffffff820e6c20 T dcn32_disable_link_output
-ffffffff820e6eb0 T dcn32_update_phantom_vp_position
-ffffffff820e6fd0 T dcn32_dsc_pg_status
-ffffffff820e70b0 T dcn32_update_dsc_pg
+ffffffff820e6080 T dcn32_update_odm
+ffffffff820e6690 T dcn32_calculate_dccg_k1_k2_values
+ffffffff820e6890 T dcn32_is_dp_dig_pixel_rate_div_policy
+ffffffff820e6920 T dcn32_set_pixels_per_cycle
+ffffffff820e6a60 T dcn32_unblank_stream
+ffffffff820e6c30 T dcn32_disable_link_output
+ffffffff820e6ec0 T dcn32_update_phantom_vp_position
+ffffffff820e6fe0 T dcn32_dsc_pg_status
+ffffffff820e70c0 T dcn32_update_dsc_pg
 ffffffff820e8000 T dcn32_hw_sequencer_init_functions
 ffffffff820e9000 t mmhubbub32_warmup_mcif
 ffffffff820e9210 t mmhubbub32_config_mcif_buf
@@ -31940,19 +31942,19 @@ ffffffff8219d000 T dml31_recalculate
 ffffffff8219d2a0 t DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
 ffffffff821a4060 T dml31_CalculateWriteBackDISPCLK
 ffffffff821a41e0 T dml31_ModeSupportAndSystemConfigurationFull
-ffffffff821ac4a0 t CalculateSwathAndDETConfiguration
-ffffffff821acaa0 t TruncToValidBPP
-ffffffff821acd20 t dscceComputeDelay
-ffffffff821ace60 t CalculateDCFCLKDeepSleep
-ffffffff821ad1a0 t CalculateVMAndRowBytes
-ffffffff821ad7f0 t CalculatePrefetchSourceLines
-ffffffff821ad9b0 t CalculateUrgentBurstFactor
-ffffffff821adc40 t CalculatePrefetchSchedulePerPlane
-ffffffff821ae370 t CalculateFlipSchedule
-ffffffff821ae8f0 t CalculateWatermarksAndDRAMSpeedChangeSupport
-ffffffff821af550 t CalculateSwathWidth
-ffffffff821afa60 t CalculatePrefetchSchedule
-ffffffff821b0ef0 t CalculateVupdateAndDynamicMetadataParameters
+ffffffff821acc40 t CalculateSwathAndDETConfiguration
+ffffffff821ad240 t TruncToValidBPP
+ffffffff821ad4c0 t dscceComputeDelay
+ffffffff821ad600 t CalculateDCFCLKDeepSleep
+ffffffff821ad940 t CalculateVMAndRowBytes
+ffffffff821adf90 t CalculatePrefetchSourceLines
+ffffffff821ae150 t CalculateUrgentBurstFactor
+ffffffff821ae3e0 t CalculatePrefetchSchedulePerPlane
+ffffffff821aeb10 t CalculateFlipSchedule
+ffffffff821af090 t CalculateWatermarksAndDRAMSpeedChangeSupport
+ffffffff821afcf0 t CalculateSwathWidth
+ffffffff821b0200 t CalculatePrefetchSchedule
+ffffffff821b1690 t CalculateVupdateAndDynamicMetadataParameters
 ffffffff821b2000 T dml31_rq_dlg_get_rq_reg
 ffffffff821b24b0 t dml_rq_dlg_get_rq_params
 ffffffff821b2720 T dml31_rq_dlg_get_dlg_reg
@@ -31963,21 +31965,21 @@ ffffffff821b7000 T dml314_recalculate
 ffffffff821b7280 t DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
 ffffffff821bdf60 T dml314_CalculateWriteBackDISPCLK
 ffffffff821be0e0 T dml314_ModeSupportAndSystemConfigurationFull
-ffffffff821c6280 t CalculateBytePerPixelAnd256BBlockSizes
-ffffffff821c64f0 t CalculateSwathAndDETConfiguration
-ffffffff821c6af0 t TruncToValidBPP
-ffffffff821c6d70 t dscceComputeDelay
-ffffffff821c6eb0 t CalculateDCFCLKDeepSleep
-ffffffff821c71f0 t CalculateVMAndRowBytes
-ffffffff821c7840 t CalculatePrefetchSourceLines
-ffffffff821c7a00 t CalculateUrgentBurstFactor
-ffffffff821c7c90 t CalculateMaxVStartup
-ffffffff821c7dd0 t CalculatePrefetchSchedulePerPlane
-ffffffff821c8500 t CalculateFlipSchedule
-ffffffff821c8a80 t CalculateWatermarksAndDRAMSpeedChangeSupport
-ffffffff821c96e0 t CalculateSwathWidth
-ffffffff821c9bf0 t CalculatePrefetchSchedule
-ffffffff821cb080 t CalculateVupdateAndDynamicMetadataParameters
+ffffffff821c6a20 t CalculateBytePerPixelAnd256BBlockSizes
+ffffffff821c6c90 t CalculateSwathAndDETConfiguration
+ffffffff821c7290 t TruncToValidBPP
+ffffffff821c7510 t dscceComputeDelay
+ffffffff821c7650 t CalculateDCFCLKDeepSleep
+ffffffff821c7990 t CalculateVMAndRowBytes
+ffffffff821c7fe0 t CalculatePrefetchSourceLines
+ffffffff821c81a0 t CalculateUrgentBurstFactor
+ffffffff821c8430 t CalculateMaxVStartup
+ffffffff821c8570 t CalculatePrefetchSchedulePerPlane
+ffffffff821c8ca0 t CalculateFlipSchedule
+ffffffff821c9220 t CalculateWatermarksAndDRAMSpeedChangeSupport
+ffffffff821c9e80 t CalculateSwathWidth
+ffffffff821ca390 t CalculatePrefetchSchedule
+ffffffff821cb820 t CalculateVupdateAndDynamicMetadataParameters
 ffffffff821cc000 T dml314_rq_dlg_get_rq_reg
 ffffffff821cc4b0 t dml_rq_dlg_get_rq_params
 ffffffff821cc720 T dml314_rq_dlg_get_dlg_reg
@@ -33547,79 +33549,79 @@ ffffffff822da3e0 T smu_write_watermarks_table
 ffffffff822da450 T smu_set_ac_dc
 ffffffff822da550 t smu_early_init
 ffffffff822da7b0 t smu_late_init
-ffffffff822daf60 t smu_sw_init
-ffffffff822db7a0 t smu_sw_fini
-ffffffff822db9f0 t smu_hw_init
-ffffffff822dbe30 t smu_hw_fini
-ffffffff822dbf30 t smu_late_fini
-ffffffff822dbf50 t smu_suspend
-ffffffff822dc020 t smu_resume
-ffffffff822dc290 t smu_set_clockgating_state
-ffffffff822dc2c0 t smu_set_powergating_state
-ffffffff822dc2f0 T smu_get_power_limit
-ffffffff822dc440 T smu_mode1_reset_is_support
-ffffffff822dc490 T smu_mode2_reset_is_support
-ffffffff822dc4e0 T smu_mode1_reset
-ffffffff822dc530 T smu_handle_passthrough_sbr
-ffffffff822dc580 T smu_get_ecc_info
-ffffffff822dc5d0 T smu_wait_for_event
-ffffffff822dc620 T smu_stb_collect_info
-ffffffff822dc680 T amdgpu_smu_stb_debug_fs_init
-ffffffff822dc6b0 T smu_send_hbm_bad_pages_num
-ffffffff822dc700 T smu_send_hbm_bad_channel_flag
-ffffffff822dc750 t smu_set_fan_control_mode
-ffffffff822dc810 t smu_get_fan_control_mode
-ffffffff822dc890 t smu_set_fan_speed_pwm
-ffffffff822dc940 t smu_get_fan_speed_pwm
-ffffffff822dc9a0 t smu_force_ppclk_levels
-ffffffff822dcac0 t smu_print_ppclk_levels
-ffffffff822dcb30 t smu_emit_ppclk_levels
-ffffffff822dcba0 t smu_force_performance_level
-ffffffff822dce40 t smu_read_sensor
-ffffffff822dd040 t smu_get_performance_level
-ffffffff822dd0b0 t smu_get_current_power_state
-ffffffff822dd110 t smu_get_fan_speed_rpm
-ffffffff822dd170 t smu_set_fan_speed_rpm
-ffffffff822dd220 t smu_get_power_num_states
-ffffffff822dd2a0 t smu_sys_get_pp_table
-ffffffff822dd310 t smu_sys_set_pp_table
-ffffffff822dd500 t smu_switch_power_profile
-ffffffff822dd610 t smu_handle_dpm_task
-ffffffff822dd6c0 t smu_load_microcode
-ffffffff822dd7b0 t smu_dpm_set_power_gate
-ffffffff822ddb30 t smu_set_power_limit
-ffffffff822ddc60 t smu_get_power_profile_mode
-ffffffff822ddcc0 t smu_set_power_profile_mode
-ffffffff822ddd20 t smu_od_edit_dpm_table
-ffffffff822ddd80 t smu_set_mp1_state
-ffffffff822ddde0 t smu_gfx_state_change_set
-ffffffff822dde20 t smu_get_sclk
-ffffffff822ddea0 t smu_get_mclk
-ffffffff822ddf20 t smu_display_configuration_change
-ffffffff822ddfb0 t smu_get_clock_by_type_with_latency
-ffffffff822de070 t smu_display_clock_voltage_request
-ffffffff822de0d0 t smu_enable_mgpu_fan_boost
-ffffffff822de130 t smu_set_display_count
-ffffffff822de1a0 t smu_set_deep_sleep_dcefclk
-ffffffff822de210 t smu_get_baco_capability
-ffffffff822de270 t smu_baco_set_state
-ffffffff822de350 t smu_sys_get_pp_feature_mask
-ffffffff822de3c0 t smu_sys_set_pp_feature_mask
-ffffffff822de430 t smu_mode2_reset
-ffffffff822de4e0 t smu_set_df_cstate
-ffffffff822de5a0 t smu_set_xgmi_pstate
-ffffffff822de650 t smu_sys_get_gpu_metrics
-ffffffff822de6b0 t smu_set_watermarks_for_clock_ranges
-ffffffff822de730 t smu_display_disable_memory_clock_switch
-ffffffff822de790 t smu_get_max_sustainable_clocks_by_dc
-ffffffff822de7f0 t smu_get_uclk_dpm_states
-ffffffff822de850 t smu_get_dpm_clock_table
-ffffffff822de8b0 t smu_get_prv_buffer_details
-ffffffff822de920 t smu_adjust_power_state_dynamic
-ffffffff822deb80 t smu_throttling_logging_work_fn
-ffffffff822debd0 t smu_interrupt_work_fn
-ffffffff822dec20 t smu_smc_hw_setup
-ffffffff822df580 t smu_smc_hw_cleanup
+ffffffff822db000 t smu_sw_init
+ffffffff822db840 t smu_sw_fini
+ffffffff822dba90 t smu_hw_init
+ffffffff822dbed0 t smu_hw_fini
+ffffffff822dbfd0 t smu_late_fini
+ffffffff822dbff0 t smu_suspend
+ffffffff822dc0c0 t smu_resume
+ffffffff822dc330 t smu_set_clockgating_state
+ffffffff822dc360 t smu_set_powergating_state
+ffffffff822dc390 T smu_get_power_limit
+ffffffff822dc4e0 T smu_mode1_reset_is_support
+ffffffff822dc530 T smu_mode2_reset_is_support
+ffffffff822dc580 T smu_mode1_reset
+ffffffff822dc5d0 T smu_handle_passthrough_sbr
+ffffffff822dc620 T smu_get_ecc_info
+ffffffff822dc670 T smu_wait_for_event
+ffffffff822dc6c0 T smu_stb_collect_info
+ffffffff822dc720 T amdgpu_smu_stb_debug_fs_init
+ffffffff822dc750 T smu_send_hbm_bad_pages_num
+ffffffff822dc7a0 T smu_send_hbm_bad_channel_flag
+ffffffff822dc7f0 t smu_set_fan_control_mode
+ffffffff822dc8b0 t smu_get_fan_control_mode
+ffffffff822dc930 t smu_set_fan_speed_pwm
+ffffffff822dc9e0 t smu_get_fan_speed_pwm
+ffffffff822dca40 t smu_force_ppclk_levels
+ffffffff822dcb60 t smu_print_ppclk_levels
+ffffffff822dcbd0 t smu_emit_ppclk_levels
+ffffffff822dcc40 t smu_force_performance_level
+ffffffff822dcee0 t smu_read_sensor
+ffffffff822dd0e0 t smu_get_performance_level
+ffffffff822dd150 t smu_get_current_power_state
+ffffffff822dd1b0 t smu_get_fan_speed_rpm
+ffffffff822dd210 t smu_set_fan_speed_rpm
+ffffffff822dd2c0 t smu_get_power_num_states
+ffffffff822dd340 t smu_sys_get_pp_table
+ffffffff822dd3b0 t smu_sys_set_pp_table
+ffffffff822dd5a0 t smu_switch_power_profile
+ffffffff822dd6b0 t smu_handle_dpm_task
+ffffffff822dd760 t smu_load_microcode
+ffffffff822dd850 t smu_dpm_set_power_gate
+ffffffff822ddbd0 t smu_set_power_limit
+ffffffff822ddd00 t smu_get_power_profile_mode
+ffffffff822ddd60 t smu_set_power_profile_mode
+ffffffff822dddc0 t smu_od_edit_dpm_table
+ffffffff822dde20 t smu_set_mp1_state
+ffffffff822dde80 t smu_gfx_state_change_set
+ffffffff822ddec0 t smu_get_sclk
+ffffffff822ddf40 t smu_get_mclk
+ffffffff822ddfc0 t smu_display_configuration_change
+ffffffff822de050 t smu_get_clock_by_type_with_latency
+ffffffff822de110 t smu_display_clock_voltage_request
+ffffffff822de170 t smu_enable_mgpu_fan_boost
+ffffffff822de1d0 t smu_set_display_count
+ffffffff822de240 t smu_set_deep_sleep_dcefclk
+ffffffff822de2b0 t smu_get_baco_capability
+ffffffff822de310 t smu_baco_set_state
+ffffffff822de3f0 t smu_sys_get_pp_feature_mask
+ffffffff822de460 t smu_sys_set_pp_feature_mask
+ffffffff822de4d0 t smu_mode2_reset
+ffffffff822de580 t smu_set_df_cstate
+ffffffff822de640 t smu_set_xgmi_pstate
+ffffffff822de6f0 t smu_sys_get_gpu_metrics
+ffffffff822de750 t smu_set_watermarks_for_clock_ranges
+ffffffff822de7d0 t smu_display_disable_memory_clock_switch
+ffffffff822de830 t smu_get_max_sustainable_clocks_by_dc
+ffffffff822de890 t smu_get_uclk_dpm_states
+ffffffff822de8f0 t smu_get_dpm_clock_table
+ffffffff822de950 t smu_get_prv_buffer_details
+ffffffff822de9c0 t smu_adjust_power_state_dynamic
+ffffffff822dec20 t smu_throttling_logging_work_fn
+ffffffff822dec70 t smu_interrupt_work_fn
+ffffffff822decc0 t smu_smc_hw_setup
+ffffffff822df620 t smu_smc_hw_cleanup
 ffffffff822e0000 T arcturus_set_ppt_funcs
 ffffffff822e0050 t arcturus_run_btc
 ffffffff822e0100 t arcturus_get_allowed_feature_mask
@@ -33703,13 +33705,13 @@ ffffffff822e8180 t navi1x_get_gpu_metrics
 ffffffff822e8b20 t navi10_enable_mgpu_fan_boost
 ffffffff822e8ba0 t navi10_get_fan_parameters
 ffffffff822e8be0 t navi10_post_smu_init
-ffffffff822e8ed0 t navi10_get_default_config_table_settings
-ffffffff822e8f20 t navi10_set_config_table
-ffffffff822e8fd0 t navi1x_get_smu_metrics_data
-ffffffff822e9430 t navi10_get_smu_metrics_data
-ffffffff822e9660 t navi10_i2c_xfer
-ffffffff822e9920 t navi10_i2c_func
-ffffffff822e9950 t navi10_umc_hybrid_cdr_workaround
+ffffffff822e8e70 t navi10_get_default_config_table_settings
+ffffffff822e8ec0 t navi10_set_config_table
+ffffffff822e8f70 t navi1x_get_smu_metrics_data
+ffffffff822e93d0 t navi10_get_smu_metrics_data
+ffffffff822e9600 t navi10_i2c_xfer
+ffffffff822e98c0 t navi10_i2c_func
+ffffffff822e98f0 t navi10_umc_hybrid_cdr_workaround
 ffffffff822ea000 T sienna_cichlid_set_ppt_funcs
 ffffffff822ea050 t sienna_cichlid_run_btc
 ffffffff822ea0d0 t sienna_cichlid_get_allowed_feature_mask
@@ -39219,18 +39221,18 @@ ffffffff8255c000 r isomappings
 ffffffff8255c080 r unimappings
 ffffffff8255c230 r replacements
 ffffffff8255fb5f r cmd0646_9_tim_udma
-ffffffff825b37eb r pp_r600_decoded_lanes
-ffffffff825cebc0 r cmd680_setup_channel.udma_tbl
-ffffffff825d6885 r apollo_udma33_tim
-ffffffff825dc96d r substchar
-ffffffff825dea86 r apollo_udma100_tim
-ffffffff8260634a r apollo_udma66_tim
-ffffffff8260d836 r apollo_pio_rec
-ffffffff8261cbd6 r cy_pio_rec
-ffffffff8264c1a7 r apollo_udma133_tim
-ffffffff82658de0 R drm_ca
-ffffffff82658e08 R drm_filtops
-ffffffff82658e38 R drmread_filtops
+ffffffff825b3808 r pp_r600_decoded_lanes
+ffffffff825cebdd r cmd680_setup_channel.udma_tbl
+ffffffff825d68a5 r apollo_udma33_tim
+ffffffff825dc98d r substchar
+ffffffff825deaa6 r apollo_udma100_tim
+ffffffff8260636a r apollo_udma66_tim
+ffffffff8260d8b7 r apollo_pio_rec
+ffffffff8261cc57 r cy_pio_rec
+ffffffff8264c23a r apollo_udma133_tim
+ffffffff82658e70 R drm_ca
+ffffffff82658e98 R drm_filtops
+ffffffff82658ec8 R drmread_filtops
 ffffffff82659000 r vga_emulops
 ffffffff82659048 R vga_stdscreen
 ffffffff82659078 R vga_stdscreen_mono
@@ -39249,23 +39251,23 @@ ffffffff826592b0 r bgansitopc
 ffffffff826592b8 r pctoansi
 ffffffff826592f8 r sdma_offsets
 ffffffff826592f8 r sdma_offsets
-ffffffff82659328 r iha_rate_tbl
-ffffffff82659360 r i830_a_wm_info
-ffffffff82659398 r gen9_edram_size_mb.ways
+ffffffff82659330 r iha_rate_tbl
+ffffffff82659368 r i830_a_wm_info
+ffffffff826593a0 r gen9_edram_size_mb.ways
 ffffffff82659400 r aggr_periodic_times
-ffffffff82659480 r jsl_ehl_revids
-ffffffff826594f8 r michael_final.pad
-ffffffff82659520 r rt_copysa.maskarray
-ffffffff82659528 r i915_wm_info
-ffffffff82659530 r amdgpu_ih_clientid_jpeg
-ffffffff82659530 r amdgpu_ih_clientid_uvds
-ffffffff82659530 r amdgpu_ih_clientid_vcns
-ffffffff82659530 r amdgpu_ih_clientid_vcns
-ffffffff82659530 r amdgpu_ih_clientid_vcns
-ffffffff82659570 r vga_setfontset.cmaptabb
-ffffffff82659588 r tgl_revids
-ffffffff826595e0 r i830_bc_wm_info
-ffffffff82659650 r hsw_activate_psr2.map
+ffffffff82659488 r jsl_ehl_revids
+ffffffff82659500 r michael_final.pad
+ffffffff82659528 r rt_copysa.maskarray
+ffffffff82659530 r i915_wm_info
+ffffffff82659538 r amdgpu_ih_clientid_jpeg
+ffffffff82659538 r amdgpu_ih_clientid_uvds
+ffffffff82659538 r amdgpu_ih_clientid_vcns
+ffffffff82659538 r amdgpu_ih_clientid_vcns
+ffffffff82659538 r amdgpu_ih_clientid_vcns
+ffffffff82659578 r vga_setfontset.cmaptabb
+ffffffff82659590 r tgl_revids
+ffffffff826595e8 r i830_bc_wm_info
+ffffffff82659658 r hsw_activate_psr2.map
 ffffffff82659690 r __drm_universal_plane_init.default_modifiers
 ffffffff826596a0 r iwn_tid2fifo
 ffffffff826596b8 r vga_setfontset.cmaptaba
@@ -42240,15 +42242,15 @@ ffffffff829e2028 r guc_class_engine_class_map
 ffffffff829e2030 r xe_lpd_lists
 ffffffff829e2170 r default_lists
 ffffffff829e22b0 r xe_lpd_global_regs
-ffffffff829e23c0 r xe_lpd_rc_class_regs
-ffffffff829e2420 r xe_lpd_rc_inst_regs
-ffffffff829e2720 r empty_regs_list
-ffffffff829e2720 r xe_lpd_vd_inst_regs
-ffffffff829e2a20 r xe_lpd_vec_class_regs
-ffffffff829e2a80 r xe_lpd_vec_inst_regs
-ffffffff829e2d80 r xe_lpd_blt_inst_regs
-ffffffff829e3080 r default_global_regs
-ffffffff829e3110 r default_rc_class_regs
+ffffffff829e2390 r xe_lpd_rc_class_regs
+ffffffff829e23f0 r xe_lpd_rc_inst_regs
+ffffffff829e26f0 r empty_regs_list
+ffffffff829e26f0 r xe_lpd_vd_inst_regs
+ffffffff829e29f0 r xe_lpd_vec_class_regs
+ffffffff829e2a50 r xe_lpd_vec_inst_regs
+ffffffff829e2d50 r xe_lpd_blt_inst_regs
+ffffffff829e3050 r default_global_regs
+ffffffff829e30e0 r default_rc_class_regs
 ffffffff829e4000 r _guc_log_init_sizes.sections
 ffffffff829e6000 r guc_context_ops
 ffffffff829e6080 r virtual_guc_context_ops