--- 7.3/2023-07-01T06:17:07Z/2023-06-13T00:00:00Z/nm-bsd-ot14.txt Sun Jul 2 18:45:50 2023 +++ 7.3/2023-07-01T06:17:07Z/2023-06-14T00:00:00Z/nm-bsd-ot14.txt Mon Jul 3 09:50:12 2023 @@ -2,11 +2,11 @@ 00011006 A mp_pdirpa 0001419d A acpi_pdirpa 01000000 A __kernel_phys_base -02554000 T __kernel_kutext_phys -02558000 C __kernel_cptext_phys -02559000 C __kernel_rodata_phys -02e10000 R __kernel_kutext_page_phys -02e12000 C __kernel_randomdata_phys +02555000 T __kernel_kutext_phys +02559000 C __kernel_cptext_phys +0255a000 C __kernel_rodata_phys +02e11000 R __kernel_kutext_page_phys +02e13000 C __kernel_randomdata_phys 030d4000 R __kernel_data_phys 03408000 D __kernel_kudata_phys 03409000 C __kernel_bss_phys @@ -20063,25 +20063,25 @@ ffffffff819dc000 T icl_dsi_frame_update ffffffff819dc0b0 T icl_dsi_init ffffffff819dc790 t gen11_dsi_pre_pll_enable ffffffff819dcb60 t gen11_dsi_pre_enable -ffffffff819df210 t gen11_dsi_enable -ffffffff819df510 t gen11_dsi_disable -ffffffff819e01b0 t gen11_dsi_post_disable -ffffffff819e01f0 t gen11_dsi_get_config -ffffffff819e0420 t gen11_dsi_sync_state -ffffffff819e04d0 t gen11_dsi_compute_config -ffffffff819e0850 t gen11_dsi_get_hw_state -ffffffff819e09f0 t gen11_dsi_initial_fastset_check -ffffffff819e0a60 t gen11_dsi_get_power_domains -ffffffff819e0b30 t gen11_dsi_gate_clocks -ffffffff819e0bf0 t gen11_dsi_is_clock_enabled -ffffffff819e0cc0 t gen11_dsi_encoder_destroy -ffffffff819e0cd0 t wait_for_cmds_dispatched_to_panel -ffffffff819e1140 t wait_for_header_credits -ffffffff819e12d0 t wait_for_payload_credits -ffffffff819e1460 t gen11_dsi_mode_valid -ffffffff819e1470 t gen11_dsi_host_attach -ffffffff819e14a0 t gen11_dsi_host_detach -ffffffff819e14d0 t gen11_dsi_host_transfer +ffffffff819df230 t gen11_dsi_enable +ffffffff819df530 t gen11_dsi_disable +ffffffff819e01d0 t gen11_dsi_post_disable +ffffffff819e0210 t gen11_dsi_get_config +ffffffff819e0440 t gen11_dsi_sync_state +ffffffff819e04f0 t gen11_dsi_compute_config +ffffffff819e0870 t gen11_dsi_get_hw_state +ffffffff819e0a10 t gen11_dsi_initial_fastset_check +ffffffff819e0a80 t gen11_dsi_get_power_domains +ffffffff819e0b50 t gen11_dsi_gate_clocks +ffffffff819e0c10 t gen11_dsi_is_clock_enabled +ffffffff819e0ce0 t gen11_dsi_encoder_destroy +ffffffff819e0cf0 t wait_for_cmds_dispatched_to_panel +ffffffff819e1160 t wait_for_header_credits +ffffffff819e12f0 t wait_for_payload_credits +ffffffff819e1480 t gen11_dsi_mode_valid +ffffffff819e1490 t gen11_dsi_host_attach +ffffffff819e14c0 t gen11_dsi_host_detach +ffffffff819e14f0 t gen11_dsi_host_transfer ffffffff819e2000 T intel_digital_connector_atomic_get_property ffffffff819e2090 T intel_digital_connector_atomic_set_property ffffffff819e2110 T intel_digital_connector_atomic_check @@ -20842,19 +20842,19 @@ ffffffff81a41a10 t intel_dp_set_common_rates ffffffff81a41bb0 T intel_dp_mst_suspend ffffffff81a41c50 T intel_dp_mst_resume ffffffff81a41d00 t intel_dp_compute_link_config -ffffffff81a42a20 t intel_dp_dsc_get_slice_count -ffffffff81a42b90 t intel_dp_set_sink_rates -ffffffff81a42dc0 t intel_dp_check_device_service_irq -ffffffff81a43390 t intel_dp_force -ffffffff81a434d0 t intel_dp_connector_register -ffffffff81a435b0 t intel_dp_connector_unregister -ffffffff81a43610 t intel_dp_oob_hotplug_event -ffffffff81a43690 t intel_dp_set_edid -ffffffff81a43ac0 t intel_dp_get_modes -ffffffff81a43bc0 t intel_dp_detect -ffffffff81a444b0 t intel_dp_mode_valid -ffffffff81a44c40 t intel_dp_connector_atomic_check -ffffffff81a44f80 t intel_dp_get_dsc_sink_cap +ffffffff81a42a30 t intel_dp_dsc_get_slice_count +ffffffff81a42ba0 t intel_dp_set_sink_rates +ffffffff81a42dd0 t intel_dp_check_device_service_irq +ffffffff81a433a0 t intel_dp_force +ffffffff81a434e0 t intel_dp_connector_register +ffffffff81a435c0 t intel_dp_connector_unregister +ffffffff81a43620 t intel_dp_oob_hotplug_event +ffffffff81a436a0 t intel_dp_set_edid +ffffffff81a43ad0 t intel_dp_get_modes +ffffffff81a43bd0 t intel_dp_detect +ffffffff81a444c0 t intel_dp_mode_valid +ffffffff81a44c60 t intel_dp_connector_atomic_check +ffffffff81a44fa0 t intel_dp_get_dsc_sink_cap ffffffff81a46000 T intel_dp_aux_fini ffffffff81a46020 T intel_dp_aux_init ffffffff81a46200 t xelpdp_aux_ctl_reg @@ -21135,11 +21135,10 @@ ffffffff81a66200 t dcs_set_backlight ffffffff81a662f0 t dcs_disable_backlight ffffffff81a66670 t dcs_enable_backlight ffffffff81a67000 T intel_dsi_vbt_exec_sequence -ffffffff81a67020 T intel_dsi_msleep -ffffffff81a67090 T intel_dsi_log_params -ffffffff81a67410 T intel_dsi_vbt_init -ffffffff81a678a0 T intel_dsi_vbt_gpio_init -ffffffff81a678c0 T intel_dsi_vbt_gpio_cleanup +ffffffff81a67020 T intel_dsi_log_params +ffffffff81a673a0 T intel_dsi_vbt_init +ffffffff81a67830 T intel_dsi_vbt_gpio_init +ffffffff81a67850 T intel_dsi_vbt_gpio_cleanup ffffffff81a68000 T intel_dvo_init ffffffff81a684f0 t intel_disable_dvo ffffffff81a685a0 t intel_enable_dvo @@ -21747,11 +21746,11 @@ ffffffff81ac5670 T intel_vrr_disable ffffffff81ac5740 T intel_vrr_get_config ffffffff81ac6000 T skl_update_scaler_crtc ffffffff81ac60c0 t skl_update_scaler -ffffffff81ac6370 T skl_update_scaler_plane -ffffffff81ac6760 T skl_pfit_enable -ffffffff81ac6c40 T skl_program_plane_scaler -ffffffff81ac7300 T skl_detach_scalers -ffffffff81ac7440 T skl_scaler_disable +ffffffff81ac63e0 T skl_update_scaler_plane +ffffffff81ac67d0 T skl_pfit_enable +ffffffff81ac6cb0 T skl_program_plane_scaler +ffffffff81ac7370 T skl_detach_scalers +ffffffff81ac74b0 T skl_scaler_disable ffffffff81ac8000 T skl_format_to_fourcc ffffffff81ac8180 T icl_is_nv12_y_plane ffffffff81ac81f0 T icl_is_hdr_plane @@ -21769,21 +21768,21 @@ ffffffff81ac8f40 t skl_plane_max_width ffffffff81ac9010 t skl_plane_min_cdclk ffffffff81ac9080 t skl_plane_max_stride ffffffff81ac9120 t icl_plane_update_noarm -ffffffff81ac9af0 t icl_plane_update_arm -ffffffff81ac9c60 t icl_plane_disable_arm -ffffffff81ac9d70 t skl_plane_update_noarm -ffffffff81ac9f10 t skl_plane_update_arm -ffffffff81aca310 t skl_plane_disable_arm -ffffffff81aca3c0 t skl_plane_get_hw_state -ffffffff81aca480 t skl_plane_check -ffffffff81acb8b0 t skl_plane_async_flip -ffffffff81acb9e0 t skl_plane_enable_flip_done -ffffffff81acba40 t skl_plane_disable_flip_done -ffffffff81acbaa0 T skl_get_initial_plane_config -ffffffff81acc140 t skl_surf_address -ffffffff81acc260 t skl_check_main_ccs_coordinates -ffffffff81acc400 t gen12_plane_format_mod_supported -ffffffff81acc650 t skl_plane_format_mod_supported +ffffffff81ac9ae0 t icl_plane_update_arm +ffffffff81ac9c50 t icl_plane_disable_arm +ffffffff81ac9d60 t skl_plane_update_noarm +ffffffff81ac9f00 t skl_plane_update_arm +ffffffff81aca300 t skl_plane_disable_arm +ffffffff81aca3b0 t skl_plane_get_hw_state +ffffffff81aca470 t skl_plane_check +ffffffff81acb8a0 t skl_plane_async_flip +ffffffff81acb9d0 t skl_plane_enable_flip_done +ffffffff81acba30 t skl_plane_disable_flip_done +ffffffff81acba90 T skl_get_initial_plane_config +ffffffff81acc130 t skl_surf_address +ffffffff81acc250 t skl_check_main_ccs_coordinates +ffffffff81acc3f0 t gen12_plane_format_mod_supported +ffffffff81acc640 t skl_plane_format_mod_supported ffffffff81acd000 T intel_enabled_dbuf_slices_mask ffffffff81acd130 T intel_sagv_pre_plane_update ffffffff81acd2a0 T intel_sagv_post_plane_update @@ -21820,18 +21819,18 @@ ffffffff81ad5060 T vlv_dsi_wait_for_fifo_empty ffffffff81ad5120 T vlv_dsi_init ffffffff81ad5980 t intel_dsi_compute_config ffffffff81ad5ad0 t intel_dsi_pre_enable -ffffffff81ad7750 t bxt_dsi_enable -ffffffff81ad77b0 t intel_dsi_disable -ffffffff81ad7a60 t intel_dsi_post_disable -ffffffff81ad8740 t intel_dsi_get_hw_state -ffffffff81ad89f0 t intel_dsi_get_config -ffffffff81ad91b0 t intel_dsi_shutdown -ffffffff81ad92a0 t intel_dsi_encoder_destroy -ffffffff81ad92d0 t intel_dsi_prepare -ffffffff81ad9f20 t dpi_send_cmd -ffffffff81ada0b0 t intel_dsi_host_attach -ffffffff81ada0e0 t intel_dsi_host_detach -ffffffff81ada110 t intel_dsi_host_transfer +ffffffff81ad7760 t bxt_dsi_enable +ffffffff81ad77c0 t intel_dsi_disable +ffffffff81ad7a70 t intel_dsi_post_disable +ffffffff81ad8770 t intel_dsi_get_hw_state +ffffffff81ad8a20 t intel_dsi_get_config +ffffffff81ad91e0 t intel_dsi_shutdown +ffffffff81ad92d0 t intel_dsi_encoder_destroy +ffffffff81ad9300 t intel_dsi_prepare +ffffffff81ad9f50 t dpi_send_cmd +ffffffff81ada0e0 t intel_dsi_host_attach +ffffffff81ada110 t intel_dsi_host_detach +ffffffff81ada140 t intel_dsi_host_transfer ffffffff81adb000 T vlv_dsi_pll_compute ffffffff81adb390 t vlv_dsi_pclk ffffffff81adb540 T vlv_dsi_pll_enable @@ -26285,3105 +26284,3098 @@ ffffffff81d85490 T amdgpu_mes_ctx_free_meta_data ffffffff81d854d0 T amdgpu_mes_ctx_map_meta_data ffffffff81d856d0 T amdgpu_mes_ctx_unmap_meta_data ffffffff81d858e0 T amdgpu_mes_self_test -ffffffff81d86000 T amdgpu_nbio_ras_late_init -ffffffff81d87000 T amdgpu_bo_is_amdgpu_bo -ffffffff81d87070 t amdgpu_bo_destroy -ffffffff81d87100 t amdgpu_bo_user_destroy -ffffffff81d871a0 t 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T psp_wait_for -ffffffff81d8c120 T psp_get_fw_attestation_records_addr -ffffffff81d8c1e0 t psp_cmd_submit_buf -ffffffff81d8c4b0 T psp_ta_unload -ffffffff81d8c550 T psp_reg_program -ffffffff81d8c620 T psp_ta_init_shared_buf -ffffffff81d8c680 T psp_ta_invoke_indirect -ffffffff81d8c760 T psp_ta_invoke -ffffffff81d8c810 T psp_ta_load -ffffffff81d8c940 T psp_copy_fw -ffffffff81d8c9d0 T psp_xgmi_invoke -ffffffff81d8ca90 T psp_xgmi_terminate -ffffffff81d8cb60 T psp_xgmi_initialize -ffffffff81d8ccf0 T psp_xgmi_get_hive_id -ffffffff81d8cde0 T psp_xgmi_get_node_id -ffffffff81d8ced0 T psp_xgmi_get_topology_info -ffffffff81d8d260 T psp_xgmi_set_topology_info -ffffffff81d8d3a0 T psp_ras_invoke -ffffffff81d8d640 T psp_ras_enable_features -ffffffff81d8d6f0 T psp_ras_terminate -ffffffff81d8d7b0 T psp_ras_trigger_error -ffffffff81d8d890 T psp_hdcp_invoke -ffffffff81d8d960 T psp_dtm_invoke -ffffffff81d8da30 T psp_rap_invoke -ffffffff81d8dbc0 T psp_securedisplay_invoke -ffffffff81d8dcb0 T psp_load_fw_list -ffffffff81d8dd40 t psp_print_fw_hdr -ffffffff81d8de10 t psp_execute_non_psp_fw_load -ffffffff81d8df00 T psp_gpu_reset -ffffffff81d8df90 T psp_rlc_autoload_start -ffffffff81d8e020 T psp_update_vcn_sram -ffffffff81d8e0b0 T psp_ring_cmd_submit -ffffffff81d8e240 T psp_init_asd_microcode -ffffffff81d8e410 T psp_init_toc_microcode -ffffffff81d8e5e0 T psp_init_sos_microcode -ffffffff81d8ecc0 T psp_init_ta_microcode -ffffffff81d8f0c0 T psp_init_cap_microcode -ffffffff81d8f2f0 T is_psp_fw_valid -ffffffff81d8f320 T amdgpu_psp_sysfs_init -ffffffff81d8f3a0 t psp_early_init -ffffffff81d8f5a0 t psp_sw_init -ffffffff81d8fa10 t psp_sw_fini -ffffffff81d8fc30 t psp_hw_init -ffffffff81d90280 t psp_hw_fini -ffffffff81d907d0 t psp_suspend -ffffffff81d90cb0 t psp_resume -ffffffff81d911e0 t psp_set_clockgating_state -ffffffff81d91210 t psp_set_powergating_state -ffffffff81d91240 T amdgpu_psp_sysfs_fini -ffffffff81d91270 t psp_get_runtime_db_entry -ffffffff81d91460 t psp_hw_start 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amdgpu_ras_interrupt_fatal_error_handler -ffffffff81d963f0 T amdgpu_ras_interrupt_dispatch -ffffffff81d964c0 T amdgpu_ras_interrupt_remove_handler -ffffffff81d96640 T amdgpu_ras_interrupt_add_handler -ffffffff81d96970 t amdgpu_ras_interrupt_process_handler -ffffffff81d96c70 T amdgpu_ras_add_bad_pages -ffffffff81d96ef0 T amdgpu_ras_save_bad_pages -ffffffff81d96ff0 T amdgpu_ras_recovery_init -ffffffff81d97320 t amdgpu_ras_do_recovery -ffffffff81d97730 T amdgpu_ras_init -ffffffff81d97a90 t amdgpu_ras_counte_dw -ffffffff81d97b00 T amdgpu_ras_set_context -ffffffff81d97b40 t amdgpu_ras_check_supported -ffffffff81d97c80 T amdgpu_ras_register_ras_block -ffffffff81d97d90 T amdgpu_persistent_edc_harvesting_supported -ffffffff81d97dc0 T amdgpu_ras_block_late_init -ffffffff81d98060 T amdgpu_ras_block_late_fini -ffffffff81d98150 T amdgpu_ras_resume -ffffffff81d98420 T amdgpu_release_ras_context -ffffffff81d98490 T amdgpu_ras_suspend -ffffffff81d98560 T amdgpu_ras_late_init -ffffffff81d98690 T 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amd_sriov_msg_checksum +ffffffff81db66c0 T amdgpu_virt_release_ras_err_handler_data +ffffffff81db67a0 T amdgpu_virt_fini_data_exchange +ffffffff81db6820 T amdgpu_virt_init_data_exchange +ffffffff81db6940 T amdgpu_virt_exchange_data +ffffffff81db6c50 t amdgpu_virt_update_vf2pf_work_item +ffffffff81db6cb0 t amdgpu_virt_read_pf2vf_data +ffffffff81db70d0 t amdgpu_virt_write_vf2pf_data +ffffffff81db7490 T amdgpu_detect_virtualization +ffffffff81db7640 T amdgpu_virt_enable_access_debugfs +ffffffff81db76d0 T amdgpu_virt_disable_access_debugfs +ffffffff81db7710 T amdgpu_virt_get_sriov_vf_mode +ffffffff81db7760 T amdgpu_virt_fw_load_skip_check +ffffffff81db77e0 T amdgpu_virt_update_sriov_video_codec +ffffffff81db78e0 T amdgpu_sriov_wreg +ffffffff81db7960 t amdgpu_virt_rlcg_reg_rw +ffffffff81db7c10 T amdgpu_sriov_rreg +ffffffff81db7c70 t __delayed_work_tick +ffffffff81db8000 T amdgpu_vm_set_pasid +ffffffff81db8130 T amdgpu_vm_bo_base_init +ffffffff81db8390 T amdgpu_vm_get_pd_bo +ffffffff81db8400 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dce_v10_0_encoder_prepare +ffffffff81dce4b0 t dce_v10_0_encoder_commit +ffffffff81dce4e0 t dce_v10_0_encoder_mode_set +ffffffff81dcf380 t dce_v10_0_encoder_disable +ffffffff81dcf490 t dce_v10_0_ext_dpms +ffffffff81dcf4c0 t dce_v10_0_ext_prepare +ffffffff81dcf4f0 t dce_v10_0_ext_commit +ffffffff81dcf520 t dce_v10_0_ext_mode_set +ffffffff81dcf550 t dce_v10_0_ext_disable +ffffffff81dcf580 t dce_v10_0_set_crtc_irq_state +ffffffff81dcf660 t dce_v10_0_crtc_irq +ffffffff81dcf890 t dce_v10_0_set_crtc_vblank_interrupt_state +ffffffff81dcf960 t dce_v10_0_set_crtc_vline_interrupt_state +ffffffff81dcfa30 t dce_v10_0_set_pageflip_irq_state +ffffffff81dcfae0 t dce_v10_0_pageflip_irq +ffffffff81dcfc40 t dce_v10_0_set_hpd_irq_state +ffffffff81dcfd10 t dce_v10_0_hpd_irq +ffffffff81dcfe30 t dce_v10_0_crtc_cursor_set2 +ffffffff81dd01a0 t dce_v10_0_crtc_cursor_move +ffffffff81dd0280 t dce_v10_0_crtc_gamma_set +ffffffff81dd02c0 t dce_v10_0_crtc_destroy +ffffffff81dd02f0 t amdgpu_bo_reserve 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dce_v11_0_soft_reset +ffffffff81dd3110 t dce_v11_0_set_clockgating_state +ffffffff81dd3140 t dce_v11_0_set_powergating_state +ffffffff81dd3170 t dce_v11_0_audio_endpt_rreg +ffffffff81dd3200 t dce_v11_0_audio_endpt_wreg +ffffffff81dd3280 t dce_v11_0_bandwidth_update +ffffffff81dd3cf0 t dce_v11_0_vblank_get_counter +ffffffff81dd3d40 t dce_v11_0_hpd_sense +ffffffff81dd3da0 t dce_v11_0_hpd_set_polarity +ffffffff81dd3e70 t dce_v11_0_hpd_get_gpio_reg +ffffffff81dd3ea0 t dce_v11_0_page_flip +ffffffff81dd3fa0 t dce_v11_0_crtc_get_scanoutpos +ffffffff81dd4040 t dce_v11_0_encoder_add +ffffffff81dd4270 t dce_v11_0_latency_watermark +ffffffff81dd4490 t dce_v11_0_encoder_destroy +ffffffff81dd44f0 t dce_v11_0_encoder_prepare +ffffffff81dd46f0 t dce_v11_0_encoder_commit +ffffffff81dd4720 t dce_v11_0_encoder_mode_set +ffffffff81dd55c0 t dce_v11_0_encoder_disable +ffffffff81dd56d0 t dce_v11_0_ext_dpms +ffffffff81dd5700 t dce_v11_0_ext_prepare +ffffffff81dd5730 t dce_v11_0_ext_commit +ffffffff81dd5760 t dce_v11_0_ext_mode_set +ffffffff81dd5790 t dce_v11_0_ext_disable +ffffffff81dd57c0 t dce_v11_0_set_crtc_irq_state +ffffffff81dd58a0 t dce_v11_0_crtc_irq +ffffffff81dd5ac0 t dce_v11_0_set_crtc_vblank_interrupt_state +ffffffff81dd5b90 t dce_v11_0_set_crtc_vline_interrupt_state +ffffffff81dd5c60 t dce_v11_0_set_pageflip_irq_state +ffffffff81dd5d10 t dce_v11_0_pageflip_irq +ffffffff81dd5e70 t dce_v11_0_set_hpd_irq_state +ffffffff81dd5f40 t dce_v11_0_hpd_irq +ffffffff81dd6060 t dce_v11_0_crtc_cursor_set2 +ffffffff81dd63d0 t dce_v11_0_crtc_cursor_move +ffffffff81dd64b0 t dce_v11_0_crtc_gamma_set +ffffffff81dd64f0 t dce_v11_0_crtc_destroy +ffffffff81dd6520 t amdgpu_bo_reserve +ffffffff81dd6730 t amdgpu_bo_unreserve +ffffffff81dd6810 t dce_v11_0_cursor_move_locked +ffffffff81dd6960 t dce_v11_0_crtc_load_lut +ffffffff81dd6cd0 t dce_v11_0_crtc_dpms +ffffffff81dd6ea0 t dce_v11_0_crtc_prepare +ffffffff81dd6ee0 t dce_v11_0_crtc_commit +ffffffff81dd6f10 t dce_v11_0_crtc_mode_fixup +ffffffff81dd7180 t dce_v11_0_crtc_mode_set +ffffffff81dd73e0 t dce_v11_0_crtc_set_base +ffffffff81dd7400 t dce_v11_0_crtc_set_base_atomic +ffffffff81dd7420 t dce_v11_0_crtc_disable +ffffffff81dd75c0 t dce_v11_0_crtc_do_set_base +ffffffff81dd8000 t df_v1_7_sw_init +ffffffff81dd8040 t df_v1_7_sw_fini +ffffffff81dd8070 t df_v1_7_enable_broadcast_mode +ffffffff81dd8190 t df_v1_7_get_fb_channel_number +ffffffff81dd8210 t df_v1_7_get_hbm_channel_number +ffffffff81dd8260 t df_v1_7_update_medium_grain_clock_gating +ffffffff81dd83d0 t df_v1_7_get_clockgating_state +ffffffff81dd8460 t df_v1_7_enable_ecc_force_par_wr_rmw +ffffffff81dd9000 t df_v3_6_sw_init +ffffffff81dd9150 t df_v3_6_sw_fini +ffffffff81dd9180 t df_v3_6_enable_broadcast_mode +ffffffff81dd92a0 t df_v3_6_get_fb_channel_number +ffffffff81dd9380 t df_v3_6_get_hbm_channel_number +ffffffff81dd93d0 t df_v3_6_update_medium_grain_clock_gating +ffffffff81dd9570 t df_v3_6_get_clockgating_state +ffffffff81dd9600 t df_v3_6_pmc_start +ffffffff81dd9980 t df_v3_6_pmc_stop +ffffffff81dd9c20 t df_v3_6_pmc_get_count +ffffffff81dd9db0 t df_v3_6_get_fica +ffffffff81dd9ec0 t df_v3_6_set_fica +ffffffff81dd9fa0 t df_v3_6_query_ras_poison_mode +ffffffff81dda110 t df_v3_6_perfmon_arm_with_status +ffffffff81ddb000 T dimgrey_cavefish_reg_base_init +ffffffff81ddc000 T emu_soc_asic_init +ffffffff81ddd000 t gfx_v10_0_early_init +ffffffff81ddd420 t gfx_v10_0_late_init +ffffffff81ddd490 t gfx_v10_0_sw_init +ffffffff81dde840 t gfx_v10_0_sw_fini +ffffffff81ddeb80 t gfx_v10_0_hw_init +ffffffff81de1730 t gfx_v10_0_hw_fini +ffffffff81de1a20 t gfx_v10_0_suspend +ffffffff81de1a60 t gfx_v10_0_resume +ffffffff81de1a70 t gfx_v10_0_is_idle +ffffffff81de1b00 t gfx_v10_0_wait_for_idle +ffffffff81de1be0 t gfx_v10_0_soft_reset +ffffffff81de1f30 t gfx_v10_0_set_clockgating_state +ffffffff81de21d0 t gfx_v10_0_set_powergating_state +ffffffff81de23f0 t gfx_v10_0_get_clockgating_state +ffffffff81de2500 t gfx10_kiq_set_resources +ffffffff81de2830 t gfx10_kiq_map_queues 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gfx_v10_0_ring_emit_pipeline_sync +ffffffff81de5990 t gfx_v10_0_ring_emit_vm_flush +ffffffff81de5b60 t gfx_v10_0_ring_emit_hdp_flush +ffffffff81de5c30 t gfx_v10_0_ring_emit_gds_switch +ffffffff81de5d10 t gfx_v10_0_ring_emit_init_cond_exec +ffffffff81de5f40 t gfx_v10_0_ring_emit_patch_cond_exec +ffffffff81de6000 t gfx_v10_0_ring_emit_sb +ffffffff81de60f0 t gfx_v10_0_ring_emit_cntxcntl +ffffffff81de65e0 t gfx_v10_0_ring_emit_frame_cntl +ffffffff81de66f0 t gfx_v10_0_ring_soft_recovery +ffffffff81de6760 t gfx_v10_0_ring_preempt_ib +ffffffff81de68d0 t gfx_v10_0_emit_mem_sync +ffffffff81de6c10 t gfx_v10_0_write_data_to_reg +ffffffff81de6e20 t gfx_v10_0_set_eop_interrupt_state +ffffffff81de6f00 t gfx_v10_0_eop_irq +ffffffff81de70d0 t gfx_v10_0_set_gfx_eop_interrupt_state +ffffffff81de7260 t gfx_v10_0_set_compute_eop_interrupt_state +ffffffff81de7410 t gfx_v10_0_kiq_set_interrupt_state +ffffffff81de76f0 t gfx_v10_0_kiq_irq +ffffffff81de7770 t gfx_v10_0_set_priv_reg_fault_state +ffffffff81de7890 t gfx_v10_0_priv_reg_irq +ffffffff81de78f0 t gfx_v10_0_handle_priv_fault +ffffffff81de7a80 t gfx_v10_0_set_priv_inst_fault_state +ffffffff81de7ba0 t gfx_v10_0_priv_inst_irq +ffffffff81de7c00 t gfx_v10_0_is_rlc_enabled +ffffffff81de7c80 t gfx_v10_0_set_safe_mode +ffffffff81de7f20 t gfx_v10_0_unset_safe_mode +ffffffff81de7fd0 t gfx_v10_0_rlc_init +ffffffff81de8050 t gfx_v10_0_get_csb_size +ffffffff81de80b0 t gfx_v10_0_get_csb_buffer +ffffffff81de8230 t gfx_v10_0_rlc_resume +ffffffff81de8d30 t gfx_v10_0_rlc_stop +ffffffff81de8e10 t gfx_v10_0_rlc_reset +ffffffff81de8fb0 t gfx_v10_0_rlc_start +ffffffff81de9150 t gfx_v10_0_update_spm_vmid +ffffffff81de9280 t gfx_v10_0_wait_for_rlc_autoload_complete +ffffffff81de9e10 t gfx_v10_0_init_csb +ffffffff81dea0e0 t gfx_v10_0_is_rlcg_access_range +ffffffff81dea110 t gfx_v10_0_gfx_mqd_init +ffffffff81dea4f0 t gfx_v10_0_compute_mqd_init +ffffffff81dea990 t amdgpu_bo_unreserve +ffffffff81deaa70 t gfx_v10_0_get_gpu_clock_counter +ffffffff81deaf70 t gfx_v10_0_select_se_sh +ffffffff81deb010 t gfx_v10_0_read_wave_data +ffffffff81deb270 t gfx_v10_0_read_wave_vgprs +ffffffff81deb2a0 t gfx_v10_0_read_wave_sgprs +ffffffff81deb320 t gfx_v10_0_select_me_pipe_q +ffffffff81deb340 t gfx_v10_0_init_spm_golden_registers +ffffffff81deb3b0 t gfx_v10_0_update_perfmon_mgcg +ffffffff81deb4d0 t wave_read_ind +ffffffff81deb5b0 t wave_read_regs +ffffffff81deb710 t gfx_v10_0_cp_resume +ffffffff81dee350 t gfx_v10_3_get_disabled_sa +ffffffff81dee460 t gfx_v10_0_get_rb_active_bitmap +ffffffff81dee580 t gfx_v10_0_get_wgp_active_bitmap_per_sh +ffffffff81dee690 t gfx_v10_0_enable_gui_idle_interrupt +ffffffff81dee7a0 t gfx_v10_0_cp_gfx_enable +ffffffff81dee9e0 t gfx_v10_0_cp_compute_enable +ffffffff81deeb70 t amdgpu_bo_reserve +ffffffff81deecf0 t gfx_v10_0_kiq_init_register +ffffffff81defb60 t gfx_v10_0_cp_gfx_switch_pipe +ffffffff81defc60 t gfx_v10_0_cp_gfx_set_doorbell +ffffffff81deff30 t gfx_v10_0_cp_gfx_start +ffffffff81df0910 t gfx_v10_0_update_fine_grain_clock_gating +ffffffff81df0c30 t gfx_v10_0_update_medium_grain_clock_gating +ffffffff81df1350 t gfx_v10_0_update_3d_clock_gating +ffffffff81df1710 t gfx_v10_0_update_coarse_grain_clock_gating +ffffffff81df2000 t gfx_v11_0_early_init +ffffffff81df23a0 t gfx_v11_0_late_init +ffffffff81df2410 t gfx_v11_0_sw_init +ffffffff81df3360 t gfx_v11_0_sw_fini +ffffffff81df3640 t gfx_v11_0_hw_init +ffffffff81df7ac0 t gfx_v11_0_hw_fini +ffffffff81df7d40 t gfx_v11_0_suspend +ffffffff81df7d80 t gfx_v11_0_resume +ffffffff81df7d90 t gfx_v11_0_is_idle +ffffffff81df7e20 t gfx_v11_0_wait_for_idle +ffffffff81df7f00 t gfx_v11_0_check_soft_reset +ffffffff81df8030 t gfx_v11_0_soft_reset +ffffffff81df8d10 t gfx_v11_0_post_soft_reset +ffffffff81df8d20 t gfx_v11_0_set_clockgating_state +ffffffff81df9900 t gfx_v11_0_set_powergating_state +ffffffff81df9af0 t gfx_v11_0_get_clockgating_state +ffffffff81df9cc0 t gfx11_kiq_set_resources +ffffffff81df9ff0 t gfx11_kiq_map_queues +ffffffff81dfa380 t gfx11_kiq_unmap_queues +ffffffff81dfa780 t gfx11_kiq_query_status +ffffffff81dfaa80 t gfx11_kiq_invalidate_tlbs +ffffffff81dfaba0 t gfx_v11_0_ring_get_rptr_compute +ffffffff81dfabd0 t gfx_v11_0_ring_get_wptr_compute +ffffffff81dfac40 t gfx_v11_0_ring_set_wptr_compute +ffffffff81dfad80 t gfx_v11_0_ring_emit_ib_compute +ffffffff81dfb0d0 t gfx_v11_0_ring_emit_fence_kiq +ffffffff81dfb510 t gfx_v11_0_ring_test_ring +ffffffff81dfb7a0 t gfx_v11_0_ring_test_ib +ffffffff81dfba60 t gfx_v11_0_ring_emit_rreg +ffffffff81dfbd00 t gfx_v11_0_ring_emit_wreg +ffffffff81dfbf40 t gfx_v11_0_ring_emit_reg_wait +ffffffff81dfbf90 t gfx_v11_0_ring_emit_reg_write_reg_wait +ffffffff81dfc000 t gfx_v11_0_wait_reg_mem +ffffffff81dfc330 t gfx_v11_0_ring_get_rptr_gfx +ffffffff81dfc360 t gfx_v11_0_ring_get_wptr_gfx +ffffffff81dfc470 t gfx_v11_0_ring_set_wptr_gfx +ffffffff81dfc680 t gfx_v11_0_ring_emit_ib_gfx +ffffffff81dfcd20 t gfx_v11_0_ring_emit_fence +ffffffff81dfd0f0 t gfx_v11_0_ring_emit_pipeline_sync +ffffffff81dfd150 t gfx_v11_0_ring_emit_vm_flush +ffffffff81dfd320 t gfx_v11_0_ring_emit_hdp_flush +ffffffff81dfd3f0 t gfx_v11_0_ring_emit_gds_switch +ffffffff81dfd4d0 t gfx_v11_0_ring_emit_init_cond_exec +ffffffff81dfd700 t gfx_v11_0_ring_emit_patch_cond_exec +ffffffff81dfd7c0 t gfx_v11_0_ring_emit_cntxcntl +ffffffff81dfd920 t gfx_v11_0_ring_emit_frame_cntl +ffffffff81dfda30 t gfx_v11_0_ring_soft_recovery +ffffffff81dfdaa0 t gfx_v11_0_ring_preempt_ib +ffffffff81dfdc10 t gfx_v11_0_emit_mem_sync +ffffffff81dfdf50 t gfx_v11_0_write_data_to_reg +ffffffff81dfe160 t gfx_v11_0_set_eop_interrupt_state +ffffffff81dfe1f0 t gfx_v11_0_eop_irq +ffffffff81dfe3c0 t gfx_v11_0_set_gfx_eop_interrupt_state +ffffffff81dfe550 t gfx_v11_0_set_compute_eop_interrupt_state +ffffffff81dfe6e0 t gfx_v11_0_set_priv_reg_fault_state +ffffffff81dfe800 t gfx_v11_0_priv_reg_irq +ffffffff81dfe860 t gfx_v11_0_handle_priv_fault +ffffffff81dfe9f0 t gfx_v11_0_set_priv_inst_fault_state +ffffffff81dfeb10 t gfx_v11_0_priv_inst_irq +ffffffff81dfeb70 t gfx_v11_0_is_rlc_enabled +ffffffff81dfebf0 t gfx_v11_0_set_safe_mode +ffffffff81dfed40 t gfx_v11_0_unset_safe_mode +ffffffff81dfedb0 t gfx_v11_0_rlc_init +ffffffff81dfee30 t gfx_v11_0_get_csb_size +ffffffff81dfee90 t gfx_v11_0_get_csb_buffer +ffffffff81dff010 t gfx_v11_0_rlc_resume +ffffffff81dffd30 t gfx_v11_0_rlc_stop +ffffffff81dffe10 t gfx_v11_0_rlc_reset +ffffffff81dfffb0 t gfx_v11_0_rlc_start +ffffffff81e00150 t gfx_v11_0_update_spm_vmid +ffffffff81e00250 t gfx_v11_0_init_csb +ffffffff81e003d0 t gfx_v11_0_gfx_mqd_init +ffffffff81e007a0 t gfx_v11_0_compute_mqd_init +ffffffff81e00cc0 t amdgpu_bo_unreserve +ffffffff81e00da0 t gfx_v11_0_get_gpu_clock_counter +ffffffff81e00ed0 t gfx_v11_0_select_se_sh +ffffffff81e00f70 t gfx_v11_0_read_wave_data +ffffffff81e011b0 t gfx_v11_0_read_wave_vgprs +ffffffff81e011e0 t gfx_v11_0_read_wave_sgprs +ffffffff81e01260 t gfx_v11_0_select_me_pipe_q +ffffffff81e01280 t gfx_v11_0_update_perf_clk +ffffffff81e013b0 t wave_read_ind +ffffffff81e01490 t wave_read_regs +ffffffff81e015f0 t gfx_v11_0_disable_gpa_mode +ffffffff81e01780 t gfx_v11_0_cp_resume +ffffffff81e05820 t gfx_v11_0_config_me_cache +ffffffff81e05bc0 t gfx_v11_0_config_pfp_cache +ffffffff81e05f60 t gfx_v11_0_config_mec_cache +ffffffff81e06300 t gfx_v11_0_enable_gui_idle_interrupt +ffffffff81e06410 t gfx_v11_0_cp_compute_enable +ffffffff81e065e0 t gfx_v11_0_cp_gfx_enable +ffffffff81e067d0 t amdgpu_bo_reserve +ffffffff81e06950 t gfx_v11_0_kiq_init_register +ffffffff81e077c0 t gfx_v11_0_cp_gfx_switch_pipe +ffffffff81e078a0 t gfx_v11_0_cp_gfx_set_doorbell +ffffffff81e07a80 t gfx_v11_0_cp_gfx_start +ffffffff81e09000 t gfx_v8_0_early_init +ffffffff81e09320 t gfx_v8_0_late_init +ffffffff81e09a20 t gfx_v8_0_sw_init +ffffffff81e0b0f0 t gfx_v8_0_sw_fini +ffffffff81e0b3b0 t gfx_v8_0_hw_init +ffffffff81e0d5e0 t gfx_v8_0_hw_fini +ffffffff81e0dad0 t gfx_v8_0_suspend +ffffffff81e0db10 t gfx_v8_0_resume +ffffffff81e0db20 t gfx_v8_0_is_idle +ffffffff81e0db90 t gfx_v8_0_wait_for_idle +ffffffff81e0dc40 t gfx_v8_0_check_soft_reset +ffffffff81e0dd20 t gfx_v8_0_pre_soft_reset +ffffffff81e0dea0 t gfx_v8_0_soft_reset +ffffffff81e0e060 t gfx_v8_0_post_soft_reset +ffffffff81e0e220 t gfx_v8_0_set_clockgating_state +ffffffff81e0e4e0 t gfx_v8_0_set_powergating_state +ffffffff81e0e8a0 t gfx_v8_0_get_clockgating_state +ffffffff81e0e980 t gfx_v8_0_get_gpu_clock_counter +ffffffff81e0ea20 t gfx_v8_0_select_se_sh +ffffffff81e0ea80 t gfx_v8_0_read_wave_data +ffffffff81e0ef20 t gfx_v8_0_read_wave_sgprs +ffffffff81e0efd0 t gfx_v8_0_select_me_pipe_q +ffffffff81e0eff0 t gfx_v8_0_ring_get_rptr +ffffffff81e0f020 t gfx_v8_0_ring_get_wptr_compute +ffffffff81e0f050 t gfx_v8_0_ring_set_wptr_compute +ffffffff81e0f090 t gfx_v8_0_ring_emit_fence_kiq +ffffffff81e0f4c0 t gfx_v8_0_ring_test_ring +ffffffff81e0f6c0 t gfx_v8_0_ring_emit_rreg +ffffffff81e0f960 t gfx_v8_0_ring_emit_wreg +ffffffff81e0fba0 t gfx_v8_0_ring_get_wptr_gfx +ffffffff81e0fc00 t gfx_v8_0_ring_set_wptr_gfx +ffffffff81e0fc70 t gfx_v8_0_ring_emit_ib_gfx +ffffffff81e101d0 t gfx_v8_0_ring_emit_fence_gfx +ffffffff81e106d0 t gfx_v8_0_ring_emit_pipeline_sync +ffffffff81e109c0 t gfx_v8_0_ring_emit_vm_flush +ffffffff81e10d70 t gfx_v8_0_ring_emit_hdp_flush +ffffffff81e11090 t gfx_v8_0_ring_emit_gds_switch +ffffffff81e11860 t gfx_v8_0_ring_test_ib +ffffffff81e11a10 t gfx_v8_0_ring_emit_init_cond_exec +ffffffff81e11c40 t gfx_v8_0_ring_emit_patch_cond_exec +ffffffff81e11cf0 t gfx_v8_ring_emit_sb +ffffffff81e11de0 t gfx_v8_ring_emit_cntxcntl +ffffffff81e12380 t gfx_v8_0_ring_soft_recovery +ffffffff81e123b0 t gfx_v8_0_emit_mem_sync +ffffffff81e125c0 t gfx_v8_0_ring_emit_ib_compute +ffffffff81e128d0 t gfx_v8_0_ring_emit_fence_compute +ffffffff81e12bd0 t gfx_v8_0_emit_mem_sync_compute +ffffffff81e12e90 t gfx_v8_0_emit_wave_limit +ffffffff81e13040 t gfx_v8_0_set_eop_interrupt_state +ffffffff81e13250 t gfx_v8_0_eop_irq +ffffffff81e13380 t gfx_v8_0_set_priv_reg_fault_state +ffffffff81e13400 t gfx_v8_0_priv_reg_irq +ffffffff81e13520 t gfx_v8_0_set_priv_inst_fault_state +ffffffff81e135a0 t gfx_v8_0_priv_inst_irq +ffffffff81e136c0 t gfx_v8_0_set_cp_ecc_int_state +ffffffff81e13930 t gfx_v8_0_cp_ecc_error_irq +ffffffff81e13980 t gfx_v8_0_set_sq_int_state +ffffffff81e13a10 t gfx_v8_0_sq_irq +ffffffff81e13ab0 t gfx_v8_0_parse_sq_irq +ffffffff81e13d00 t gfx_v8_0_is_rlc_enabled +ffffffff81e13d40 t gfx_v8_0_set_safe_mode +ffffffff81e13e40 t gfx_v8_0_unset_safe_mode +ffffffff81e13ee0 t gfx_v8_0_rlc_init +ffffffff81e13f90 t gfx_v8_0_get_csb_size +ffffffff81e13ff0 t gfx_v8_0_get_csb_buffer +ffffffff81e14170 t gfx_v8_0_cp_jump_table_num +ffffffff81e141b0 t gfx_v8_0_rlc_resume +ffffffff81e14540 t gfx_v8_0_rlc_stop +ffffffff81e145b0 t gfx_v8_0_rlc_reset +ffffffff81e14630 t gfx_v8_0_rlc_start +ffffffff81e146b0 t gfx_v8_0_update_spm_vmid +ffffffff81e14720 t gfx_v8_0_init_save_restore_list +ffffffff81e14b40 t gfx_v8_0_wait_for_rlc_serdes +ffffffff81e14d60 t gfx_v8_0_sq_irq_work_func +ffffffff81e14d80 t amdgpu_bo_unreserve +ffffffff81e14e60 t gfx_v8_0_kiq_resume +ffffffff81e150c0 t gfx_v8_0_cp_gfx_resume +ffffffff81e15be0 t gfx_v8_0_kcq_resume +ffffffff81e16610 t amdgpu_bo_reserve +ffffffff81e16790 t gfx_v8_0_mqd_commit +ffffffff81e16970 t gfx_v8_0_mqd_init +ffffffff81e16d90 t gfx_v8_0_deactivate_hqd +ffffffff81e16e50 t gfx_v8_0_update_medium_grain_clock_gating +ffffffff81e17180 t gfx_v8_0_update_coarse_grain_clock_gating +ffffffff81e18000 t gfx_v9_0_ras_error_inject +ffffffff81e181a0 t gfx_v9_0_query_ras_error_count +ffffffff81e18d40 t gfx_v9_0_reset_ras_error_count +ffffffff81e19780 T gfx_v9_0_select_se_sh +ffffffff81e19820 t gfx_v9_0_early_init +ffffffff81e19c80 t gfx_v9_0_late_init +ffffffff81e1a990 t gfx_v9_0_sw_init +ffffffff81e1c000 t gfx_v9_0_sw_fini +ffffffff81e1c2b0 t gfx_v9_0_hw_init +ffffffff81e1f350 t gfx_v9_0_hw_fini +ffffffff81e1fac0 t gfx_v9_0_suspend +ffffffff81e1fb00 t gfx_v9_0_resume +ffffffff81e1fb10 t gfx_v9_0_is_idle +ffffffff81e1fb90 t gfx_v9_0_wait_for_idle +ffffffff81e1fc70 t gfx_v9_0_soft_reset +ffffffff81e20000 t gfx_v9_0_set_clockgating_state +ffffffff81e200d0 t gfx_v9_0_set_powergating_state +ffffffff81e204d0 t gfx_v9_0_get_clockgating_state +ffffffff81e205e0 t gfx_v9_0_kiq_set_resources +ffffffff81e20910 t gfx_v9_0_kiq_map_queues +ffffffff81e20c50 t gfx_v9_0_kiq_unmap_queues +ffffffff81e20fd0 t gfx_v9_0_kiq_query_status +ffffffff81e212d0 t gfx_v9_0_kiq_invalidate_tlbs +ffffffff81e213f0 t gfx_v9_0_ring_get_rptr_compute +ffffffff81e21420 t gfx_v9_0_ring_get_wptr_compute +ffffffff81e21490 t gfx_v9_0_ring_set_wptr_compute +ffffffff81e214f0 t gfx_v9_0_ring_emit_fence_kiq +ffffffff81e21930 t gfx_v9_0_ring_test_ring +ffffffff81e21b60 t gfx_v9_0_ring_emit_rreg +ffffffff81e21e00 t gfx_v9_0_ring_emit_wreg +ffffffff81e22040 t gfx_v9_0_ring_emit_reg_wait +ffffffff81e22090 t gfx_v9_0_ring_emit_reg_write_reg_wait +ffffffff81e22130 t gfx_v9_0_wait_reg_mem +ffffffff81e22460 t gfx_v9_0_ring_get_rptr_gfx +ffffffff81e22490 t gfx_v9_0_ring_get_wptr_gfx +ffffffff81e225a0 t gfx_v9_0_ring_set_wptr_gfx +ffffffff81e226d0 t gfx_v9_0_ring_emit_ib_gfx +ffffffff81e22bf0 t gfx_v9_0_ring_emit_fence +ffffffff81e22fb0 t gfx_v9_0_ring_emit_pipeline_sync +ffffffff81e23010 t gfx_v9_0_ring_emit_vm_flush +ffffffff81e23120 t gfx_v9_0_ring_emit_hdp_flush +ffffffff81e231f0 t gfx_v9_0_ring_emit_gds_switch +ffffffff81e232d0 t gfx_v9_0_ring_test_ib +ffffffff81e23480 t gfx_v9_0_ring_emit_init_cond_exec +ffffffff81e236b0 t gfx_v9_0_ring_emit_patch_cond_exec +ffffffff81e23780 t gfx_v9_ring_emit_sb +ffffffff81e23870 t gfx_v9_ring_emit_cntxcntl +ffffffff81e23c70 t gfx_v9_0_ring_emit_frame_cntl +ffffffff81e23d80 t gfx_v9_0_ring_soft_recovery +ffffffff81e23df0 t gfx_v9_0_emit_mem_sync +ffffffff81e240b0 t gfx_v9_0_write_data_to_reg +ffffffff81e242c0 t gfx_v9_0_ring_emit_ib_compute +ffffffff81e245f0 t gfx_v9_0_emit_wave_limit +ffffffff81e247c0 t gfx_v9_0_set_eop_interrupt_state +ffffffff81e24990 t gfx_v9_0_eop_irq +ffffffff81e24ac0 t gfx_v9_0_set_compute_eop_interrupt_state +ffffffff81e24c70 t gfx_v9_0_set_priv_reg_fault_state +ffffffff81e24d90 t gfx_v9_0_priv_reg_irq +ffffffff81e24eb0 t gfx_v9_0_set_priv_inst_fault_state +ffffffff81e24fd0 t gfx_v9_0_priv_inst_irq +ffffffff81e250f0 t gfx_v9_0_set_cp_ecc_error_state +ffffffff81e25920 t gfx_v9_0_is_rlc_enabled +ffffffff81e259a0 t gfx_v9_0_set_safe_mode +ffffffff81e25af0 t gfx_v9_0_unset_safe_mode +ffffffff81e25b60 t gfx_v9_0_rlc_init +ffffffff81e26370 t gfx_v9_0_get_csb_size +ffffffff81e263d0 t gfx_v9_0_get_csb_buffer +ffffffff81e26520 t gfx_v9_0_cp_jump_table_num +ffffffff81e26570 t gfx_v9_0_rlc_resume +ffffffff81e27310 t gfx_v9_0_rlc_stop +ffffffff81e277b0 t gfx_v9_0_rlc_reset +ffffffff81e27940 t gfx_v9_0_rlc_start +ffffffff81e27a80 t gfx_v9_0_update_spm_vmid +ffffffff81e27bb0 t gfx_v9_0_is_rlcg_access_range +ffffffff81e27c00 t gfx_v9_0_init_always_on_cu_mask +ffffffff81e27f60 t gfx_v9_0_init_csb +ffffffff81e280f0 t gfx_v9_0_enable_lbpw +ffffffff81e281e0 t gfx_v9_0_enable_gui_idle_interrupt +ffffffff81e282e0 t amdgpu_bo_unreserve +ffffffff81e283c0 t gfx_v9_0_get_gpu_clock_counter +ffffffff81e28b40 t gfx_v9_0_read_wave_data +ffffffff81e28d80 t gfx_v9_0_read_wave_vgprs +ffffffff81e28da0 t gfx_v9_0_read_wave_sgprs +ffffffff81e28df0 t gfx_v9_0_select_me_pipe_q +ffffffff81e28e10 t wave_read_ind +ffffffff81e28f20 t wave_read_regs +ffffffff81e29090 t gfx_v9_0_cp_gfx_enable +ffffffff81e29170 t amdgpu_bo_reserve +ffffffff81e292f0 t gfx_v9_0_kiq_init_register +ffffffff81e29f70 t gfx_v9_0_mqd_init +ffffffff81e2a4b0 t gfx_v9_0_update_medium_grain_clock_gating +ffffffff81e2a9c0 t gfx_v9_0_update_3d_clock_gating +ffffffff81e2ada0 t gfx_v9_0_update_coarse_grain_clock_gating +ffffffff81e2c000 t gfx_v9_4_ras_error_inject +ffffffff81e2c130 t gfx_v9_4_query_ras_error_count +ffffffff81e2cef0 t gfx_v9_4_query_ras_error_status +ffffffff81e2d0c0 t gfx_v9_4_reset_ras_error_count +ffffffff81e2e000 T gfx_v9_4_2_do_edc_gpr_workarounds +ffffffff81e2e790 T gfx_v9_4_2_init_golden_registers +ffffffff81e2e830 T gfx_v9_4_2_debug_trap_config_init +ffffffff81e2e8d0 T gfx_v9_4_2_set_power_brake_sequence +ffffffff81e2eaa0 t gfx_v9_4_2_ras_error_inject +ffffffff81e2ebd0 t gfx_v9_4_2_query_ras_error_count +ffffffff81e2ec80 t gfx_v9_4_2_query_ras_error_status +ffffffff81e2f4d0 t gfx_v9_4_2_reset_ras_error_count +ffffffff81e2f530 t gfx_v9_4_2_reset_ras_error_status +ffffffff81e2f9f0 t gfx_v9_4_2_enable_watchdog_timer +ffffffff81e2fc10 t gfx_v9_4_2_query_uctl2_poison_status +ffffffff81e2fc90 t gfx_v9_4_2_run_shader +ffffffff81e30010 t gfx_v9_4_2_wait_for_waves_assigned +ffffffff81e30650 t gfx_v9_4_2_query_sram_edc_count +ffffffff81e309a0 t gfx_v9_4_2_query_utc_edc_count +ffffffff81e30b80 t wave_read_ind +ffffffff81e31000 t gfxhub_v1_0_get_mc_fb_offset +ffffffff81e31090 t gfxhub_v1_0_setup_vm_pt_regs +ffffffff81e311d0 t gfxhub_v1_0_gart_enable +ffffffff81e326c0 t gfxhub_v1_0_gart_disable +ffffffff81e32950 t gfxhub_v1_0_set_fault_enable_default +ffffffff81e32a40 t gfxhub_v1_0_init +ffffffff81e33000 T gfxhub_v1_1_get_xgmi_info +ffffffff81e34000 t gfxhub_v2_0_get_fb_location +ffffffff81e34090 t gfxhub_v2_0_get_mc_fb_offset +ffffffff81e34120 t gfxhub_v2_0_setup_vm_pt_regs +ffffffff81e34260 t gfxhub_v2_0_gart_enable +ffffffff81e35460 t gfxhub_v2_0_gart_disable +ffffffff81e356a0 t gfxhub_v2_0_set_fault_enable_default +ffffffff81e35790 t gfxhub_v2_0_init +ffffffff81e35860 t gfxhub_v2_0_print_l2_protection_fault_status +ffffffff81e35a40 t gfxhub_v2_0_get_invalidate_req +ffffffff81e36000 t gfxhub_v2_1_get_fb_location +ffffffff81e36090 t gfxhub_v2_1_get_mc_fb_offset +ffffffff81e36120 t gfxhub_v2_1_setup_vm_pt_regs +ffffffff81e36260 t gfxhub_v2_1_gart_enable +ffffffff81e37540 t gfxhub_v2_1_gart_disable +ffffffff81e377c0 t gfxhub_v2_1_set_fault_enable_default +ffffffff81e378d0 t gfxhub_v2_1_init +ffffffff81e379a0 t gfxhub_v2_1_get_xgmi_info +ffffffff81e37ad0 t gfxhub_v2_1_utcl2_harvest +ffffffff81e37cb0 t gfxhub_v2_1_save_regs +ffffffff81e386e0 t gfxhub_v2_1_restore_regs +ffffffff81e392c0 t gfxhub_v2_1_halt +ffffffff81e39680 t gfxhub_v2_1_print_l2_protection_fault_status +ffffffff81e39860 t gfxhub_v2_1_get_invalidate_req +ffffffff81e3a000 t gfxhub_v3_0_get_fb_location +ffffffff81e3a090 t gfxhub_v3_0_get_mc_fb_offset +ffffffff81e3a120 t gfxhub_v3_0_setup_vm_pt_regs +ffffffff81e3a260 t gfxhub_v3_0_gart_enable +ffffffff81e3b4e0 t gfxhub_v3_0_gart_disable +ffffffff81e3b760 t gfxhub_v3_0_set_fault_enable_default +ffffffff81e3bb00 t gfxhub_v3_0_init +ffffffff81e3bbd0 t gfxhub_v3_0_print_l2_protection_fault_status +ffffffff81e3bdb0 t gfxhub_v3_0_get_invalidate_req +ffffffff81e3c000 t gfxhub_v3_0_3_get_fb_location +ffffffff81e3c090 t gfxhub_v3_0_3_get_mc_fb_offset +ffffffff81e3c120 t gfxhub_v3_0_3_setup_vm_pt_regs +ffffffff81e3c260 t gfxhub_v3_0_3_gart_enable +ffffffff81e3d4f0 t gfxhub_v3_0_3_gart_disable +ffffffff81e3d790 t gfxhub_v3_0_3_set_fault_enable_default +ffffffff81e3d8a0 t gfxhub_v3_0_3_init +ffffffff81e3d970 t gfxhub_v3_0_3_print_l2_protection_fault_status +ffffffff81e3db50 t gfxhub_v3_0_3_get_invalidate_req +ffffffff81e3e000 t gmc_v10_0_early_init +ffffffff81e3e1f0 t gmc_v10_0_late_init +ffffffff81e3e260 t gmc_v10_0_sw_init +ffffffff81e3e680 t gmc_v10_0_sw_fini +ffffffff81e3e6d0 t gmc_v10_0_hw_init +ffffffff81e3e8a0 t gmc_v10_0_hw_fini +ffffffff81e3e930 t gmc_v10_0_suspend +ffffffff81e3e9c0 t gmc_v10_0_resume +ffffffff81e3ea20 t gmc_v10_0_is_idle +ffffffff81e3ea50 t gmc_v10_0_wait_for_idle +ffffffff81e3ea80 t gmc_v10_0_soft_reset +ffffffff81e3eab0 t gmc_v10_0_set_clockgating_state +ffffffff81e3eb60 t gmc_v10_0_set_powergating_state +ffffffff81e3eb90 t gmc_v10_0_get_clockgating_state +ffffffff81e3ec30 t gmc_v10_0_flush_gpu_tlb +ffffffff81e3eee0 t gmc_v10_0_flush_gpu_tlb_pasid +ffffffff81e3f100 t gmc_v10_0_emit_flush_gpu_tlb +ffffffff81e3f2b0 t gmc_v10_0_emit_pasid_mapping +ffffffff81e3f320 t gmc_v10_0_map_mtype +ffffffff81e3f370 t gmc_v10_0_get_vm_pde +ffffffff81e3f460 t gmc_v10_0_get_vm_pte +ffffffff81e3f510 t gmc_v10_0_get_vbios_fb_size +ffffffff81e3f680 t gmc_v10_0_flush_vm_hub +ffffffff81e3fae0 t gmc_v10_0_vm_fault_interrupt_state +ffffffff81e3fb50 t gmc_v10_0_process_interrupt +ffffffff81e3fe10 t gmc_v10_0_ecc_interrupt_state +ffffffff81e40000 t gmc_v11_0_early_init +ffffffff81e40230 t gmc_v11_0_late_init +ffffffff81e402a0 t gmc_v11_0_sw_init +ffffffff81e405c0 t gmc_v11_0_sw_fini +ffffffff81e40610 t gmc_v11_0_hw_init +ffffffff81e40750 t gmc_v11_0_hw_fini +ffffffff81e407d0 t gmc_v11_0_suspend +ffffffff81e40850 t gmc_v11_0_resume +ffffffff81e408b0 t gmc_v11_0_is_idle +ffffffff81e408e0 t gmc_v11_0_wait_for_idle +ffffffff81e40910 t gmc_v11_0_soft_reset +ffffffff81e40940 t gmc_v11_0_set_clockgating_state +ffffffff81e409c0 t gmc_v11_0_set_powergating_state +ffffffff81e409f0 t gmc_v11_0_get_clockgating_state +ffffffff81e40a30 t gmc_v11_0_flush_gpu_tlb +ffffffff81e40f00 t gmc_v11_0_flush_gpu_tlb_pasid +ffffffff81e410f0 t gmc_v11_0_emit_flush_gpu_tlb +ffffffff81e412a0 t gmc_v11_0_emit_pasid_mapping +ffffffff81e41310 t gmc_v11_0_map_mtype +ffffffff81e41360 t gmc_v11_0_get_vm_pde +ffffffff81e41460 t gmc_v11_0_get_vm_pte +ffffffff81e41510 t gmc_v11_0_get_vbios_fb_size +ffffffff81e41540 t gmc_v11_0_vm_fault_interrupt_state +ffffffff81e415b0 t gmc_v11_0_process_interrupt +ffffffff81e417d0 t gmc_v11_0_ecc_interrupt_state +ffffffff81e42000 t gmc_v7_0_early_init +ffffffff81e42090 t gmc_v7_0_late_init +ffffffff81e420e0 t gmc_v7_0_sw_init +ffffffff81e425e0 t gmc_v7_0_sw_fini +ffffffff81e42690 t gmc_v7_0_hw_init +ffffffff81e43040 t gmc_v7_0_hw_fini +ffffffff81e43100 t gmc_v7_0_suspend +ffffffff81e43140 t gmc_v7_0_resume +ffffffff81e431a0 t gmc_v7_0_is_idle +ffffffff81e431f0 t gmc_v7_0_wait_for_idle +ffffffff81e43290 t gmc_v7_0_soft_reset +ffffffff81e434f0 t gmc_v7_0_set_clockgating_state +ffffffff81e43750 t gmc_v7_0_set_powergating_state +ffffffff81e43780 t gmc_v7_0_flush_gpu_tlb +ffffffff81e437b0 t gmc_v7_0_flush_gpu_tlb_pasid +ffffffff81e43870 t gmc_v7_0_emit_flush_gpu_tlb +ffffffff81e43900 t gmc_v7_0_emit_pasid_mapping +ffffffff81e43930 t gmc_v7_0_set_prt +ffffffff81e43af0 t gmc_v7_0_get_vm_pde +ffffffff81e43b50 t gmc_v7_0_get_vm_pte +ffffffff81e43b90 t gmc_v7_0_get_vbios_fb_size +ffffffff81e43c00 t gmc_v7_0_vm_fault_interrupt_state +ffffffff81e43cd0 t gmc_v7_0_process_interrupt +ffffffff81e44000 t gmc_v8_0_early_init +ffffffff81e44090 t gmc_v8_0_late_init +ffffffff81e440e0 t gmc_v8_0_sw_init +ffffffff81e44760 t gmc_v8_0_sw_fini +ffffffff81e44810 t gmc_v8_0_hw_init +ffffffff81e454c0 t gmc_v8_0_hw_fini +ffffffff81e45580 t gmc_v8_0_suspend +ffffffff81e455c0 t gmc_v8_0_resume +ffffffff81e45620 t gmc_v8_0_is_idle +ffffffff81e45670 t gmc_v8_0_wait_for_idle +ffffffff81e45710 t gmc_v8_0_check_soft_reset +ffffffff81e45780 t gmc_v8_0_pre_soft_reset +ffffffff81e458f0 t gmc_v8_0_soft_reset +ffffffff81e459c0 t gmc_v8_0_post_soft_reset +ffffffff81e45a30 t gmc_v8_0_set_clockgating_state +ffffffff81e45ff0 t gmc_v8_0_set_powergating_state +ffffffff81e46020 t gmc_v8_0_get_clockgating_state +ffffffff81e46090 t gmc_v8_0_flush_gpu_tlb +ffffffff81e460c0 t gmc_v8_0_flush_gpu_tlb_pasid +ffffffff81e46180 t gmc_v8_0_emit_flush_gpu_tlb +ffffffff81e46210 t gmc_v8_0_emit_pasid_mapping +ffffffff81e46240 t gmc_v8_0_set_prt +ffffffff81e46400 t gmc_v8_0_get_vm_pde +ffffffff81e46460 t gmc_v8_0_get_vm_pte +ffffffff81e464b0 t gmc_v8_0_get_vbios_fb_size +ffffffff81e46520 t gmc_v8_0_vm_fault_interrupt_state +ffffffff81e465f0 t gmc_v8_0_process_interrupt +ffffffff81e47000 T gmc_v9_0_restore_registers +ffffffff81e47150 t gmc_v9_0_early_init +ffffffff81e47500 t gmc_v9_0_late_init +ffffffff81e47610 t gmc_v9_0_sw_init +ffffffff81e47cc0 t gmc_v9_0_sw_fini +ffffffff81e47d30 t gmc_v9_0_hw_init +ffffffff81e48130 t gmc_v9_0_hw_fini +ffffffff81e481e0 t gmc_v9_0_suspend +ffffffff81e48290 t gmc_v9_0_resume +ffffffff81e482f0 t gmc_v9_0_is_idle +ffffffff81e48320 t gmc_v9_0_wait_for_idle +ffffffff81e48350 t gmc_v9_0_soft_reset +ffffffff81e48380 t gmc_v9_0_set_clockgating_state +ffffffff81e483e0 t gmc_v9_0_set_powergating_state +ffffffff81e48410 t gmc_v9_0_get_clockgating_state +ffffffff81e48450 t gmc_v9_0_flush_gpu_tlb +ffffffff81e48a90 t gmc_v9_0_flush_gpu_tlb_pasid +ffffffff81e48d60 t gmc_v9_0_emit_flush_gpu_tlb +ffffffff81e48f30 t gmc_v9_0_emit_pasid_mapping +ffffffff81e48fa0 t gmc_v9_0_map_mtype +ffffffff81e48fe0 t gmc_v9_0_get_vm_pde +ffffffff81e490e0 t gmc_v9_0_get_vm_pte +ffffffff81e491b0 t gmc_v9_0_get_vbios_fb_size +ffffffff81e49340 t gmc_v9_0_vm_fault_interrupt_state +ffffffff81e496c0 t gmc_v9_0_process_interrupt +ffffffff81e49d00 t gmc_v9_0_ecc_interrupt_state +ffffffff81e4a000 t hdp_v4_0_query_ras_error_count +ffffffff81e4a0c0 t hdp_v4_0_reset_ras_error_count +ffffffff81e4a1e0 t hdp_v4_0_flush_hdp +ffffffff81e4a230 t hdp_v4_0_invalidate_hdp +ffffffff81e4a300 t hdp_v4_0_update_clock_gating +ffffffff81e4a400 t hdp_v4_0_get_clockgating_state +ffffffff81e4a450 t hdp_v4_0_init_registers +ffffffff81e4b000 t hdp_v5_0_flush_hdp +ffffffff81e4b050 t hdp_v5_0_invalidate_hdp +ffffffff81e4b0f0 t hdp_v5_0_update_clock_gating +ffffffff81e4b4e0 t hdp_v5_0_get_clockgating_state +ffffffff81e4b600 t hdp_v5_0_init_registers +ffffffff81e4c000 t hdp_v5_2_flush_hdp +ffffffff81e4c050 t hdp_v5_2_update_clock_gating +ffffffff81e4c440 t hdp_v5_2_get_clockgating_state +ffffffff81e4d000 t hdp_v6_0_flush_hdp +ffffffff81e4d050 t hdp_v6_0_update_clock_gating +ffffffff81e4d360 t hdp_v6_0_get_clockgating_state +ffffffff81e4e000 t iceland_ih_early_init +ffffffff81e4e050 t iceland_ih_sw_init +ffffffff81e4e0b0 t iceland_ih_sw_fini +ffffffff81e4e0f0 t iceland_ih_hw_init +ffffffff81e4e320 t iceland_ih_hw_fini +ffffffff81e4e3f0 t iceland_ih_suspend +ffffffff81e4e4c0 t iceland_ih_resume +ffffffff81e4e500 t iceland_ih_is_idle +ffffffff81e4e550 t iceland_ih_wait_for_idle +ffffffff81e4e5f0 t iceland_ih_soft_reset +ffffffff81e4e6d0 t iceland_ih_set_clockgating_state +ffffffff81e4e700 t iceland_ih_set_powergating_state +ffffffff81e4e730 t iceland_ih_get_wptr +ffffffff81e4e820 t iceland_ih_decode_iv +ffffffff81e4e8a0 t iceland_ih_set_rptr +ffffffff81e4f000 t ih_v6_0_early_init +ffffffff81e4f050 t ih_v6_0_sw_init +ffffffff81e4f1b0 t ih_v6_0_sw_fini +ffffffff81e4f1f0 t ih_v6_0_hw_init +ffffffff81e4f7a0 t ih_v6_0_hw_fini +ffffffff81e4f800 t ih_v6_0_suspend +ffffffff81e4f860 t ih_v6_0_resume +ffffffff81e4f870 t ih_v6_0_is_idle +ffffffff81e4f8a0 t ih_v6_0_wait_for_idle +ffffffff81e4f8d0 t ih_v6_0_soft_reset +ffffffff81e4f900 t ih_v6_0_set_clockgating_state +ffffffff81e4fa20 t ih_v6_0_set_powergating_state +ffffffff81e4fb90 t ih_v6_0_get_clockgating_state +ffffffff81e4fc20 t ih_v6_0_get_wptr +ffffffff81e4fd10 t ih_v6_0_set_rptr +ffffffff81e4fde0 t ih_v6_0_self_irq +ffffffff81e4fe50 t ih_v6_0_toggle_interrupts +ffffffff81e50030 t force_update_wptr_for_self_int +ffffffff81e51000 t imu_v11_0_init_microcode +ffffffff81e511f0 t imu_v11_0_load_microcode +ffffffff81e51550 t imu_v11_0_setup +ffffffff81e517d0 t imu_v11_0_start +ffffffff81e518c0 t imu_v11_0_program_rlc_ram +ffffffff81e51a70 t imu_v11_0_wait_for_reset_status +ffffffff81e51bc0 t program_imu_rlc_ram +ffffffff81e52000 T imu_v11_0_3_program_rlc_ram +ffffffff81e53000 T jpeg_v1_0_early_init +ffffffff81e53060 T jpeg_v1_0_sw_init +ffffffff81e53130 T jpeg_v1_0_sw_fini +ffffffff81e53150 T jpeg_v1_0_start +ffffffff81e53bc0 t jpeg_v1_0_decode_ring_get_rptr +ffffffff81e53c50 t jpeg_v1_0_decode_ring_get_wptr +ffffffff81e53ce0 t jpeg_v1_0_decode_ring_set_wptr +ffffffff81e53d50 t jpeg_v1_0_decode_ring_emit_ib +ffffffff81e54660 t jpeg_v1_0_decode_ring_emit_fence +ffffffff81e54fc0 t jpeg_v1_0_decode_ring_emit_vm_flush +ffffffff81e55030 t jpeg_v1_0_decode_ring_nop +ffffffff81e55190 t jpeg_v1_0_decode_ring_insert_start +ffffffff81e55360 t jpeg_v1_0_decode_ring_insert_end +ffffffff81e55530 t jpeg_v1_0_ring_begin_use +ffffffff81e55630 t jpeg_v1_0_decode_ring_emit_wreg +ffffffff81e55890 t jpeg_v1_0_decode_ring_emit_reg_wait +ffffffff81e55cb0 t jpeg_v1_0_set_interrupt_state +ffffffff81e55ce0 t jpeg_v1_0_process_interrupt +ffffffff81e56000 T jpeg_v2_0_dec_ring_insert_start +ffffffff81e561b0 T jpeg_v2_0_dec_ring_insert_end +ffffffff81e56360 T jpeg_v2_0_dec_ring_emit_fence +ffffffff81e56a50 T jpeg_v2_0_dec_ring_emit_ib +ffffffff81e57240 T jpeg_v2_0_dec_ring_emit_reg_wait +ffffffff81e57600 T jpeg_v2_0_dec_ring_emit_vm_flush +ffffffff81e57670 T jpeg_v2_0_dec_ring_emit_wreg +ffffffff81e578b0 T jpeg_v2_0_dec_ring_nop +ffffffff81e57a10 t jpeg_v2_0_early_init +ffffffff81e57a80 t jpeg_v2_0_sw_init +ffffffff81e57b90 t jpeg_v2_0_sw_fini +ffffffff81e57be0 t jpeg_v2_0_hw_init +ffffffff81e57c60 t jpeg_v2_0_hw_fini +ffffffff81e57d40 t jpeg_v2_0_suspend +ffffffff81e57d70 t jpeg_v2_0_resume +ffffffff81e57e00 t jpeg_v2_0_is_idle +ffffffff81e57e80 t jpeg_v2_0_wait_for_idle +ffffffff81e57f70 t jpeg_v2_0_set_clockgating_state +ffffffff81e58020 t jpeg_v2_0_set_powergating_state +ffffffff81e58820 t jpeg_v2_0_dec_ring_get_rptr +ffffffff81e588b0 t jpeg_v2_0_dec_ring_get_wptr +ffffffff81e58950 t jpeg_v2_0_dec_ring_set_wptr +ffffffff81e589f0 t jpeg_v2_0_set_interrupt_state +ffffffff81e58a20 t jpeg_v2_0_process_interrupt +ffffffff81e58ab0 t jpeg_v2_0_enable_clock_gating +ffffffff81e58c50 t jpeg_v2_0_disable_clock_gating +ffffffff81e59000 t jpeg_v2_6_query_ras_poison_status +ffffffff81e59140 t jpeg_v2_5_early_init +ffffffff81e59410 t jpeg_v2_5_sw_init +ffffffff81e59630 t jpeg_v2_5_sw_fini +ffffffff81e59680 t jpeg_v2_5_hw_init +ffffffff81e59770 t jpeg_v2_5_hw_fini +ffffffff81e598b0 t jpeg_v2_5_suspend +ffffffff81e598e0 t jpeg_v2_5_resume +ffffffff81e599e0 t jpeg_v2_5_is_idle +ffffffff81e59ae0 t jpeg_v2_5_wait_for_idle +ffffffff81e59c10 t jpeg_v2_5_set_clockgating_state +ffffffff81e59d80 t jpeg_v2_5_set_powergating_state +ffffffff81e5a470 t jpeg_v2_5_dec_ring_get_rptr +ffffffff81e5a510 t jpeg_v2_5_dec_ring_get_wptr +ffffffff81e5a5c0 t jpeg_v2_5_dec_ring_set_wptr +ffffffff81e5a670 t jpeg_v2_6_dec_ring_insert_start +ffffffff81e5a830 t jpeg_v2_6_dec_ring_insert_end +ffffffff81e5a9f0 t jpeg_v2_5_set_interrupt_state +ffffffff81e5aa20 t jpeg_v2_5_process_interrupt +ffffffff81e5ab00 t jpeg_v2_5_enable_clock_gating +ffffffff81e5abd0 t jpeg_v2_5_disable_clock_gating +ffffffff81e5b000 t jpeg_v3_0_early_init +ffffffff81e5b0f0 t jpeg_v3_0_sw_init +ffffffff81e5b200 t jpeg_v3_0_sw_fini +ffffffff81e5b250 t jpeg_v3_0_hw_init +ffffffff81e5b2d0 t jpeg_v3_0_hw_fini +ffffffff81e5b3b0 t jpeg_v3_0_suspend +ffffffff81e5b3e0 t jpeg_v3_0_resume +ffffffff81e5b470 t jpeg_v3_0_is_idle +ffffffff81e5b4f0 t jpeg_v3_0_wait_for_idle +ffffffff81e5b5e0 t jpeg_v3_0_set_clockgating_state +ffffffff81e5b690 t jpeg_v3_0_set_powergating_state +ffffffff81e5bf40 t jpeg_v3_0_dec_ring_get_rptr +ffffffff81e5bfd0 t jpeg_v3_0_dec_ring_get_wptr +ffffffff81e5c070 t jpeg_v3_0_dec_ring_set_wptr +ffffffff81e5c110 t jpeg_v3_0_set_interrupt_state +ffffffff81e5c140 t jpeg_v3_0_process_interrupt +ffffffff81e5c1d0 t jpeg_v3_0_enable_clock_gating +ffffffff81e5c2a0 t jpeg_v3_0_disable_clock_gating +ffffffff81e5d000 t jpeg_v4_0_early_init +ffffffff81e5d080 t jpeg_v4_0_sw_init +ffffffff81e5d190 t jpeg_v4_0_sw_fini +ffffffff81e5d1e0 t jpeg_v4_0_hw_init +ffffffff81e5d300 t jpeg_v4_0_hw_fini +ffffffff81e5d3e0 t jpeg_v4_0_suspend +ffffffff81e5d410 t jpeg_v4_0_resume +ffffffff81e5d460 t jpeg_v4_0_is_idle +ffffffff81e5d4e0 t jpeg_v4_0_wait_for_idle +ffffffff81e5d5d0 t jpeg_v4_0_set_clockgating_state +ffffffff81e5d680 t jpeg_v4_0_set_powergating_state +ffffffff81e5de90 t jpeg_v4_0_dec_ring_get_rptr +ffffffff81e5df20 t jpeg_v4_0_dec_ring_get_wptr +ffffffff81e5dfc0 t jpeg_v4_0_dec_ring_set_wptr +ffffffff81e5e060 t jpeg_v4_0_set_interrupt_state +ffffffff81e5e090 t jpeg_v4_0_process_interrupt +ffffffff81e5e130 t jpeg_v4_0_enable_clock_gating +ffffffff81e5e2e0 t jpeg_v4_0_disable_clock_gating +ffffffff81e5f000 t lsdma_v6_0_copy_mem +ffffffff81e5f360 t lsdma_v6_0_fill_mem +ffffffff81e5f640 t lsdma_v6_0_update_memory_power_gating +ffffffff81e60000 t mca_v3_0_mp0_query_ras_error_count +ffffffff81e60020 t mca_v3_0_ras_block_match +ffffffff81e60070 t mca_v3_0_mp1_query_ras_error_count +ffffffff81e60090 t mca_v3_0_mpio_query_ras_error_count +ffffffff81e600b0 t mca_v3_0_init +ffffffff81e61000 t mes_v10_0_early_init +ffffffff81e61060 t mes_v10_0_late_init +ffffffff81e610b0 t mes_v10_1_sw_init +ffffffff81e61580 t mes_v10_1_sw_fini +ffffffff81e616b0 t mes_v10_1_hw_init +ffffffff81e61f50 t mes_v10_1_hw_fini +ffffffff81e62010 t mes_v10_1_suspend +ffffffff81e620f0 t mes_v10_1_resume +ffffffff81e62140 t mes_v10_1_kiq_hw_init +ffffffff81e62550 t mes_v10_1_add_hw_queue +ffffffff81e626d0 t mes_v10_1_remove_hw_queue +ffffffff81e62760 t mes_v10_1_unmap_legacy_queue +ffffffff81e62850 t mes_v10_1_suspend_gang +ffffffff81e62880 t mes_v10_1_resume_gang +ffffffff81e628b0 t mes_v10_1_submit_pkt_and_poll_completion +ffffffff81e62ab0 t mes_v10_1_load_microcode +ffffffff81e632a0 t mes_v10_1_enable +ffffffff81e63710 t mes_v10_1_queue_init +ffffffff81e639b0 t amdgpu_bo_unreserve +ffffffff81e63a90 t mes_v10_1_ring_get_rptr +ffffffff81e63ac0 t mes_v10_1_ring_get_wptr +ffffffff81e63b30 t mes_v10_1_ring_set_wptr +ffffffff81e64000 t mes_v11_0_early_init +ffffffff81e64060 t mes_v11_0_late_init +ffffffff81e640d0 t mes_v11_0_sw_init +ffffffff81e645b0 t mes_v11_0_sw_fini +ffffffff81e64750 t mes_v11_0_hw_init +ffffffff81e64f60 t mes_v11_0_hw_fini +ffffffff81e64f90 t mes_v11_0_suspend +ffffffff81e64fa0 t mes_v11_0_resume +ffffffff81e64ff0 t mes_v11_0_kiq_hw_init +ffffffff81e651f0 t mes_v11_0_kiq_hw_fini +ffffffff81e65630 t mes_v11_0_add_hw_queue +ffffffff81e65830 t mes_v11_0_remove_hw_queue +ffffffff81e658c0 t mes_v11_0_unmap_legacy_queue +ffffffff81e659c0 t mes_v11_0_suspend_gang +ffffffff81e659f0 t mes_v11_0_resume_gang +ffffffff81e65a20 t mes_v11_0_misc_op +ffffffff81e65b90 t mes_v11_0_submit_pkt_and_poll_completion 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mmhub_v1_7_reset_ras_error_count +ffffffff81e6b2d0 t mmhub_v1_7_reset_ras_error_status +ffffffff81e6b3c0 t mmhub_v1_7_get_fb_location +ffffffff81e6b4d0 t mmhub_v1_7_init +ffffffff81e6b570 t mmhub_v1_7_gart_enable +ffffffff81e6ca50 t mmhub_v1_7_set_fault_enable_default +ffffffff81e6cb60 t mmhub_v1_7_gart_disable +ffffffff81e6cdf0 t mmhub_v1_7_set_clockgating +ffffffff81e6d170 t mmhub_v1_7_get_clockgating +ffffffff81e6d290 t mmhub_v1_7_setup_vm_pt_regs +ffffffff81e6e000 t mmhub_v2_0_init +ffffffff81e6e0d0 t mmhub_v2_0_gart_enable +ffffffff81e6f250 t mmhub_v2_0_set_fault_enable_default +ffffffff81e6f360 t mmhub_v2_0_gart_disable +ffffffff81e6f5e0 t mmhub_v2_0_set_clockgating +ffffffff81e6f920 t mmhub_v2_0_get_clockgating +ffffffff81e6fab0 t mmhub_v2_0_setup_vm_pt_regs +ffffffff81e6fbf0 t mmhub_v2_0_print_l2_protection_fault_status +ffffffff81e6fe50 t mmhub_v2_0_get_invalidate_req +ffffffff81e70000 t mmhub_v2_3_init +ffffffff81e700e0 t mmhub_v2_3_gart_enable +ffffffff81e71470 t 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mmhub_v3_0_1_init +ffffffff81e751f0 t mmhub_v3_0_1_gart_enable +ffffffff81e76470 t mmhub_v3_0_1_set_fault_enable_default +ffffffff81e76570 t mmhub_v3_0_1_gart_disable +ffffffff81e76800 t mmhub_v3_0_1_set_clockgating +ffffffff81e769c0 t mmhub_v3_0_1_get_clockgating +ffffffff81e76a70 t mmhub_v3_0_1_setup_vm_pt_regs +ffffffff81e76bb0 t mmhub_v3_0_1_print_l2_protection_fault_status +ffffffff81e76dc0 t mmhub_v3_0_1_get_invalidate_req +ffffffff81e77000 t mmhub_v3_0_2_get_fb_location +ffffffff81e77090 t mmhub_v3_0_2_get_mc_fb_offset +ffffffff81e77120 t mmhub_v3_0_2_init +ffffffff81e771f0 t mmhub_v3_0_2_gart_enable +ffffffff81e78370 t mmhub_v3_0_2_set_fault_enable_default +ffffffff81e78480 t mmhub_v3_0_2_gart_disable +ffffffff81e78700 t mmhub_v3_0_2_set_clockgating +ffffffff81e78730 t mmhub_v3_0_2_get_clockgating +ffffffff81e78760 t mmhub_v3_0_2_setup_vm_pt_regs +ffffffff81e788a0 t mmhub_v3_0_2_print_l2_protection_fault_status +ffffffff81e78aa0 t mmhub_v3_0_2_get_invalidate_req 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xgpu_ai_request_reset +ffffffff81e7c530 t xgpu_ai_mailbox_trans_msg +ffffffff81e7c760 t xgpu_ai_set_mailbox_ack_irq +ffffffff81e7c7f0 t xgpu_ai_mailbox_ack_irq +ffffffff81e7c840 t xgpu_ai_set_mailbox_rcv_irq +ffffffff81e7c8d0 t xgpu_ai_mailbox_rcv_irq +ffffffff81e7c9b0 t xgpu_ai_send_access_requests +ffffffff81e7caa0 t xgpu_ai_poll_msg +ffffffff81e7d000 T xgpu_nv_mailbox_set_irq_funcs +ffffffff81e7d050 T xgpu_nv_mailbox_add_irq_id +ffffffff81e7d0e0 T xgpu_nv_mailbox_get_irq +ffffffff81e7d190 t xgpu_nv_mailbox_flr_work +ffffffff81e7d3b0 T xgpu_nv_mailbox_put_irq +ffffffff81e7d3f0 t xgpu_nv_request_full_gpu_access +ffffffff81e7d410 t xgpu_nv_release_full_gpu_access +ffffffff81e7d430 t xgpu_nv_request_init_data +ffffffff81e7d450 t xgpu_nv_request_reset +ffffffff81e7d550 t xgpu_nv_mailbox_trans_msg +ffffffff81e7d6f0 t xgpu_nv_set_mailbox_ack_irq +ffffffff81e7d770 t xgpu_nv_mailbox_ack_irq +ffffffff81e7d7c0 t xgpu_nv_set_mailbox_rcv_irq +ffffffff81e7d840 t xgpu_nv_mailbox_rcv_irq +ffffffff81e7d8f0 t xgpu_nv_send_access_requests +ffffffff81e7e000 T xgpu_vi_init_golden_registers +ffffffff81e7e0c0 T xgpu_vi_mailbox_set_irq_funcs +ffffffff81e7e110 T xgpu_vi_mailbox_add_irq_id +ffffffff81e7e1a0 T xgpu_vi_mailbox_get_irq +ffffffff81e7e250 t xgpu_vi_mailbox_flr_work +ffffffff81e7e3a0 T xgpu_vi_mailbox_put_irq +ffffffff81e7e3e0 t xgpu_vi_request_full_gpu_access +ffffffff81e7e400 t xgpu_vi_release_full_gpu_access +ffffffff81e7e420 t xgpu_vi_request_reset +ffffffff81e7e440 t xgpu_vi_wait_reset_cmpl +ffffffff81e7e520 t xgpu_vi_set_mailbox_ack_irq +ffffffff81e7e5a0 t xgpu_vi_mailbox_ack_irq +ffffffff81e7e5f0 t xgpu_vi_set_mailbox_rcv_irq +ffffffff81e7e670 t xgpu_vi_mailbox_rcv_irq +ffffffff81e7e720 t xgpu_vi_mailbox_rcv_msg +ffffffff81e7e840 t xgpu_vi_send_access_requests +ffffffff81e7f000 t navi10_ih_early_init +ffffffff81e7f060 t navi10_ih_sw_init +ffffffff81e7f1d0 t navi10_ih_sw_fini +ffffffff81e7f210 t navi10_ih_hw_init +ffffffff81e7f640 t navi10_ih_hw_fini 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nbio_v2_3_vcn_doorbell_range +ffffffff81e813a0 t nbio_v2_3_enable_doorbell_aperture +ffffffff81e81490 t nbio_v2_3_enable_doorbell_selfring_aperture +ffffffff81e815f0 t nbio_v2_3_ih_doorbell_range +ffffffff81e81700 t nbio_v2_3_update_medium_grain_clock_gating +ffffffff81e817a0 t nbio_v2_3_update_medium_grain_light_sleep +ffffffff81e81840 t nbio_v2_3_get_clockgating_state +ffffffff81e818c0 t nbio_v2_3_ih_control +ffffffff81e81a10 t nbio_v2_3_init_registers +ffffffff81e81aa0 t nbio_v2_3_remap_hdp_registers +ffffffff81e81bb0 t nbio_v2_3_enable_aspm +ffffffff81e81c50 t nbio_v2_3_program_aspm +ffffffff81e822e0 t nbio_v2_3_apply_lc_spc_mode_wa +ffffffff81e82370 t nbio_v2_3_apply_l1_link_width_reconfig_wa +ffffffff81e823e0 t nbio_v2_3_clear_doorbell_interrupt +ffffffff81e83000 t nbio_v4_3_get_hdp_flush_req_offset +ffffffff81e83040 t nbio_v4_3_get_hdp_flush_done_offset +ffffffff81e83080 t nbio_v4_3_get_pcie_index_offset +ffffffff81e830b0 t nbio_v4_3_get_pcie_data_offset +ffffffff81e830f0 t nbio_v4_3_get_rev_id +ffffffff81e83170 t nbio_v4_3_mc_access_enable +ffffffff81e83220 t nbio_v4_3_get_memsize +ffffffff81e83290 t nbio_v4_3_sdma_doorbell_range +ffffffff81e83400 t nbio_v4_3_vcn_doorbell_range +ffffffff81e835b0 t nbio_v4_3_gc_doorbell_init +ffffffff81e836a0 t nbio_v4_3_enable_doorbell_aperture +ffffffff81e83790 t nbio_v4_3_enable_doorbell_selfring_aperture +ffffffff81e838f0 t nbio_v4_3_ih_doorbell_range +ffffffff81e83a10 t nbio_v4_3_update_medium_grain_clock_gating +ffffffff81e83b50 t nbio_v4_3_update_medium_grain_light_sleep +ffffffff81e83c80 t nbio_v4_3_get_clockgating_state +ffffffff81e83d90 t nbio_v4_3_ih_control +ffffffff81e83ee0 t nbio_v4_3_init_registers +ffffffff81e83ff0 t nbio_v4_3_remap_hdp_registers +ffffffff81e84100 t nbio_v4_3_program_aspm +ffffffff81e84da0 t nbio_v4_3_get_rom_offset +ffffffff81e84e30 t nbio_v4_3_sriov_sdma_doorbell_range +ffffffff81e84e60 t nbio_v4_3_sriov_vcn_doorbell_range +ffffffff81e84e90 t nbio_v4_3_sriov_gc_doorbell_init +ffffffff81e84ec0 t nbio_v4_3_sriov_ih_doorbell_range +ffffffff81e85000 t nbio_v6_1_get_hdp_flush_req_offset +ffffffff81e85040 t nbio_v6_1_get_hdp_flush_done_offset +ffffffff81e85080 t nbio_v6_1_get_pcie_index_offset +ffffffff81e850c0 t nbio_v6_1_get_pcie_data_offset +ffffffff81e85100 t nbio_v6_1_get_rev_id +ffffffff81e85180 t nbio_v6_1_mc_access_enable +ffffffff81e85230 t nbio_v6_1_get_memsize +ffffffff81e852a0 t nbio_v6_1_sdma_doorbell_range +ffffffff81e85330 t nbio_v6_1_enable_doorbell_aperture +ffffffff81e85420 t nbio_v6_1_enable_doorbell_selfring_aperture +ffffffff81e85580 t nbio_v6_1_ih_doorbell_range +ffffffff81e85690 t nbio_v6_1_update_medium_grain_clock_gating +ffffffff81e85730 t nbio_v6_1_update_medium_grain_light_sleep +ffffffff81e857d0 t nbio_v6_1_get_clockgating_state +ffffffff81e85850 t nbio_v6_1_ih_control +ffffffff81e859a0 t nbio_v6_1_init_registers +ffffffff81e85a70 t nbio_v6_1_remap_hdp_registers +ffffffff81e85b80 t nbio_v6_1_program_aspm +ffffffff81e86000 t nbio_v7_0_get_hdp_flush_req_offset +ffffffff81e86040 t nbio_v7_0_get_hdp_flush_done_offset +ffffffff81e86080 t nbio_v7_0_get_pcie_index_offset +ffffffff81e860c0 t nbio_v7_0_get_pcie_data_offset +ffffffff81e86100 t nbio_v7_0_get_rev_id +ffffffff81e86180 t nbio_v7_0_mc_access_enable +ffffffff81e86230 t nbio_v7_0_get_memsize +ffffffff81e862a0 t nbio_v7_0_sdma_doorbell_range +ffffffff81e86330 t nbio_v7_0_vcn_doorbell_range +ffffffff81e863b0 t nbio_v7_0_enable_doorbell_aperture +ffffffff81e864a0 t nbio_v7_0_enable_doorbell_selfring_aperture +ffffffff81e864d0 t nbio_v7_0_ih_doorbell_range +ffffffff81e865e0 t nbio_v7_0_update_medium_grain_clock_gating +ffffffff81e86710 t nbio_v7_0_update_medium_grain_light_sleep +ffffffff81e867b0 t nbio_v7_0_get_clockgating_state +ffffffff81e86830 t nbio_v7_0_ih_control +ffffffff81e86980 t nbio_v7_0_init_registers +ffffffff81e869d0 t nbio_v7_0_remap_hdp_registers +ffffffff81e86ae0 t nbio_7_0_read_syshub_ind_mmr +ffffffff81e86bb0 t nbio_7_0_write_syshub_ind_mmr +ffffffff81e87000 t nbio_v7_2_get_hdp_flush_req_offset +ffffffff81e87040 t nbio_v7_2_get_hdp_flush_done_offset +ffffffff81e87080 t nbio_v7_2_get_pcie_index_offset +ffffffff81e870c0 t nbio_v7_2_get_pcie_data_offset +ffffffff81e87100 t nbio_v7_2_get_pcie_port_index_offset +ffffffff81e87130 t nbio_v7_2_get_pcie_port_data_offset +ffffffff81e87170 t nbio_v7_2_get_rev_id +ffffffff81e87250 t nbio_v7_2_mc_access_enable +ffffffff81e87390 t nbio_v7_2_get_memsize +ffffffff81e87400 t nbio_v7_2_sdma_doorbell_range +ffffffff81e874a0 t nbio_v7_2_vcn_doorbell_range +ffffffff81e87520 t nbio_v7_2_enable_doorbell_aperture +ffffffff81e87600 t nbio_v7_2_enable_doorbell_selfring_aperture +ffffffff81e87760 t nbio_v7_2_ih_doorbell_range +ffffffff81e877f0 t nbio_v7_2_update_medium_grain_clock_gating +ffffffff81e878b0 t nbio_v7_2_update_medium_grain_light_sleep +ffffffff81e87a40 t nbio_v7_2_get_clockgating_state +ffffffff81e87ad0 t nbio_v7_2_ih_control +ffffffff81e87c20 t nbio_v7_2_init_registers +ffffffff81e87de0 t nbio_v7_2_remap_hdp_registers +ffffffff81e88000 t nbio_v7_4_query_ras_error_count +ffffffff81e881a0 t nbio_v7_4_handle_ras_controller_intr_no_bifring +ffffffff81e883e0 t nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring +ffffffff81e88590 t nbio_v7_4_init_ras_controller_interrupt +ffffffff81e885d0 t nbio_v7_4_init_ras_err_event_athub_interrupt +ffffffff81e88610 t nbio_v7_4_get_hdp_flush_req_offset +ffffffff81e88650 t nbio_v7_4_get_hdp_flush_done_offset +ffffffff81e88690 t nbio_v7_4_get_pcie_index_offset +ffffffff81e886d0 t nbio_v7_4_get_pcie_data_offset +ffffffff81e88710 t nbio_v7_4_get_rev_id +ffffffff81e887d0 t nbio_v7_4_mc_access_enable +ffffffff81e88880 t nbio_v7_4_get_memsize +ffffffff81e888f0 t nbio_v7_4_sdma_doorbell_range +ffffffff81e889c0 t nbio_v7_4_vcn_doorbell_range +ffffffff81e88a60 t nbio_v7_4_enable_doorbell_aperture +ffffffff81e88b50 t nbio_v7_4_enable_doorbell_selfring_aperture +ffffffff81e88cb0 t nbio_v7_4_ih_doorbell_range +ffffffff81e88dc0 t nbio_v7_4_enable_doorbell_interrupt +ffffffff81e88f00 t nbio_v7_4_update_medium_grain_clock_gating +ffffffff81e88f30 t nbio_v7_4_update_medium_grain_light_sleep +ffffffff81e88fd0 t nbio_v7_4_get_clockgating_state +ffffffff81e89050 t nbio_v7_4_ih_control +ffffffff81e891a0 t nbio_v7_4_init_registers +ffffffff81e89290 t nbio_v7_4_remap_hdp_registers +ffffffff81e893a0 t nbio_v7_4_program_aspm +ffffffff81e897b0 t nbio_v7_4_set_ras_controller_irq_state +ffffffff81e89940 t nbio_v7_4_process_ras_controller_irq +ffffffff81e89970 t nbio_v7_4_set_ras_err_event_athub_irq_state +ffffffff81e89b00 t nbio_v7_4_process_err_event_athub_irq +ffffffff81e8a000 t nbio_v7_7_get_hdp_flush_req_offset +ffffffff81e8a040 t nbio_v7_7_get_hdp_flush_done_offset +ffffffff81e8a080 t nbio_v7_7_get_pcie_index_offset +ffffffff81e8a0c0 t nbio_v7_7_get_pcie_data_offset +ffffffff81e8a100 t nbio_v7_7_get_pcie_port_index_offset +ffffffff81e8a130 t nbio_v7_7_get_pcie_port_data_offset +ffffffff81e8a170 t nbio_v7_7_get_rev_id +ffffffff81e8a1f0 t nbio_v7_7_mc_access_enable +ffffffff81e8a2a0 t nbio_v7_7_get_memsize +ffffffff81e8a310 t nbio_v7_7_sdma_doorbell_range +ffffffff81e8a3a0 t nbio_v7_7_vcn_doorbell_range +ffffffff81e8a420 t nbio_v7_7_enable_doorbell_aperture +ffffffff81e8a500 t nbio_v7_7_enable_doorbell_selfring_aperture +ffffffff81e8a660 t nbio_v7_7_ih_doorbell_range +ffffffff81e8a770 t nbio_v7_7_update_medium_grain_clock_gating +ffffffff81e8a8b0 t nbio_v7_7_update_medium_grain_light_sleep +ffffffff81e8aac0 t nbio_v7_7_get_clockgating_state +ffffffff81e8abd0 t nbio_v7_7_ih_control +ffffffff81e8ad20 t nbio_v7_7_init_registers +ffffffff81e8ae20 t nbio_v7_7_remap_hdp_registers +ffffffff81e8b000 T nv_grbm_select +ffffffff81e8b0a0 T nv_set_virt_ops +ffffffff81e8b0e0 t nv_common_early_init +ffffffff81e8b4d0 t nv_common_late_init +ffffffff81e8b540 t nv_common_sw_init +ffffffff81e8b580 t nv_common_sw_fini +ffffffff81e8b5b0 t nv_common_hw_init +ffffffff81e8b6c0 t nv_common_hw_fini +ffffffff81e8b720 t nv_common_suspend +ffffffff81e8b780 t nv_common_resume +ffffffff81e8b7c0 t nv_common_is_idle +ffffffff81e8b7f0 t nv_common_wait_for_idle +ffffffff81e8b820 t nv_common_soft_reset +ffffffff81e8b850 t nv_common_set_clockgating_state +ffffffff81e8b920 t nv_common_set_powergating_state +ffffffff81e8b950 t nv_common_get_clockgating_state +ffffffff81e8b9c0 t nv_pcie_rreg +ffffffff81e8ba20 t nv_pcie_wreg +ffffffff81e8ba80 t nv_pcie_rreg64 +ffffffff81e8bae0 t nv_pcie_wreg64 +ffffffff81e8bb40 t nv_didt_rreg +ffffffff81e8bbe0 t nv_didt_wreg +ffffffff81e8bc60 t nv_read_disabled_bios +ffffffff81e8bc90 t nv_read_register +ffffffff81e8bd70 t nv_vga_set_state +ffffffff81e8bda0 t nv_asic_reset +ffffffff81e8bee0 t nv_asic_reset_method +ffffffff81e8bfd0 t nv_get_xclk +ffffffff81e8c000 t nv_set_uvd_clocks +ffffffff81e8c030 t nv_set_vce_clocks +ffffffff81e8c060 t nv_get_config_memsize +ffffffff81e8c080 t nv_need_full_reset +ffffffff81e8c0b0 t nv_init_doorbell_index +ffffffff81e8c1e0 t nv_need_reset_on_init +ffffffff81e8c270 t nv_get_pcie_replay_count +ffffffff81e8c2a0 t nv_pre_asic_init +ffffffff81e8c2d0 t nv_update_umd_stable_pstate +ffffffff81e8c390 t nv_query_video_codecs +ffffffff81e8d000 T psp_v10_0_set_psp_funcs +ffffffff81e8d030 t psp_v10_0_init_microcode +ffffffff81e8d2a0 t psp_v10_0_ring_init +ffffffff81e8d320 t psp_v10_0_ring_create +ffffffff81e8d630 t psp_v10_0_ring_stop +ffffffff81e8d820 t psp_v10_0_ring_destroy +ffffffff81e8d8a0 t psp_v10_0_mode1_reset +ffffffff81e8d8f0 t psp_v10_0_ring_get_wptr +ffffffff81e8d950 t psp_v10_0_ring_set_wptr +ffffffff81e8e000 T psp_v11_0_set_psp_funcs +ffffffff81e8e030 t psp_v11_0_init_microcode +ffffffff81e8e450 t psp_v11_0_bootloader_load_kdb +ffffffff81e8e470 t psp_v11_0_bootloader_load_spl +ffffffff81e8e490 t psp_v11_0_bootloader_load_sysdrv +ffffffff81e8e4b0 t psp_v11_0_bootloader_load_sos +ffffffff81e8e800 t psp_v11_0_ring_init +ffffffff81e8e880 t psp_v11_0_ring_create +ffffffff81e8ef10 t psp_v11_0_ring_stop +ffffffff81e8f130 t psp_v11_0_ring_destroy +ffffffff81e8f1b0 t psp_v11_0_mode1_reset +ffffffff81e8f2b0 t psp_v11_0_memory_training +ffffffff81e8f730 t psp_v11_0_ring_get_wptr +ffffffff81e8f780 t psp_v11_0_ring_set_wptr +ffffffff81e8f8c0 t psp_v11_0_load_usbc_pd_fw +ffffffff81e8fab0 t psp_v11_0_read_usbc_pd_fw +ffffffff81e8fbd0 t psp_v11_0_bootloader_load_component +ffffffff81e8fd90 t psp_v11_0_wait_for_bootloader +ffffffff81e8ff60 t psp_v11_0_memory_training_send_msg +ffffffff81e91000 T psp_v11_0_8_set_psp_funcs +ffffffff81e91030 t psp_v11_0_8_ring_init +ffffffff81e910b0 t psp_v11_0_8_ring_create +ffffffff81e91740 t psp_v11_0_8_ring_stop +ffffffff81e91ad0 t psp_v11_0_8_ring_destroy +ffffffff81e91b50 t psp_v11_0_8_ring_get_wptr +ffffffff81e91bc0 t psp_v11_0_8_ring_set_wptr +ffffffff81e92000 T psp_v12_0_set_psp_funcs +ffffffff81e92030 t psp_v12_0_init_microcode +ffffffff81e922a0 t psp_v12_0_bootloader_load_sysdrv +ffffffff81e925c0 t psp_v12_0_bootloader_load_sos +ffffffff81e92920 t psp_v12_0_ring_init +ffffffff81e92f00 t psp_v12_0_ring_create +ffffffff81e93460 t psp_v12_0_ring_stop +ffffffff81e93680 t psp_v12_0_ring_destroy +ffffffff81e93700 t psp_v12_0_mode1_reset +ffffffff81e93800 t psp_v12_0_ring_get_wptr +ffffffff81e93870 t psp_v12_0_ring_set_wptr +ffffffff81e94000 T psp_v13_0_set_psp_funcs +ffffffff81e94030 t psp_v13_0_init_microcode +ffffffff81e94160 t psp_v13_0_bootloader_load_kdb +ffffffff81e94180 t psp_v13_0_bootloader_load_spl +ffffffff81e941a0 t psp_v13_0_bootloader_load_sysdrv +ffffffff81e941c0 t psp_v13_0_bootloader_load_soc_drv +ffffffff81e941e0 t psp_v13_0_bootloader_load_intf_drv +ffffffff81e94200 t psp_v13_0_bootloader_load_dbg_drv +ffffffff81e94220 t psp_v13_0_bootloader_load_ras_drv +ffffffff81e94240 t psp_v13_0_bootloader_load_sos +ffffffff81e945a0 t psp_v13_0_ring_init +ffffffff81e94620 t psp_v13_0_ring_create +ffffffff81e94cb0 t psp_v13_0_ring_stop +ffffffff81e95040 t psp_v13_0_ring_destroy +ffffffff81e950c0 t psp_v13_0_memory_training +ffffffff81e95500 t psp_v13_0_ring_get_wptr +ffffffff81e95570 t psp_v13_0_ring_set_wptr +ffffffff81e95670 t psp_v13_0_load_usbc_pd_fw +ffffffff81e95860 t psp_v13_0_read_usbc_pd_fw +ffffffff81e95980 t psp_v13_0_update_spirom +ffffffff81e95b60 t psp_v13_0_vbflash_status +ffffffff81e95bc0 t psp_v13_0_bootloader_load_component +ffffffff81e95d90 t psp_v13_0_wait_for_bootloader +ffffffff81e95f60 t psp_v13_0_memory_training_send_msg +ffffffff81e960c0 t psp_v13_0_exec_spi_cmd +ffffffff81e97000 T psp_v13_0_4_set_psp_funcs +ffffffff81e97030 t psp_v13_0_4_init_microcode +ffffffff81e97100 t psp_v13_0_4_bootloader_load_kdb +ffffffff81e97120 t psp_v13_0_4_bootloader_load_spl +ffffffff81e97140 t psp_v13_0_4_bootloader_load_sysdrv +ffffffff81e97160 t psp_v13_0_4_bootloader_load_soc_drv +ffffffff81e97180 t psp_v13_0_4_bootloader_load_intf_drv +ffffffff81e971a0 t psp_v13_0_4_bootloader_load_dbg_drv +ffffffff81e971c0 t psp_v13_0_4_bootloader_load_sos +ffffffff81e97530 t psp_v13_0_4_ring_init +ffffffff81e975b0 t psp_v13_0_4_ring_create +ffffffff81e97c50 t psp_v13_0_4_ring_stop +ffffffff81e97fe0 t psp_v13_0_4_ring_destroy +ffffffff81e98060 t psp_v13_0_4_ring_get_wptr +ffffffff81e980d0 t psp_v13_0_4_ring_set_wptr +ffffffff81e981d0 t psp_v13_0_4_bootloader_load_component +ffffffff81e983a0 t psp_v13_0_4_wait_for_bootloader +ffffffff81e99000 T psp_v3_1_set_psp_funcs +ffffffff81e99030 t psp_v3_1_init_microcode +ffffffff81e990f0 t psp_v3_1_bootloader_load_sysdrv +ffffffff81e99410 t psp_v3_1_bootloader_load_sos +ffffffff81e99770 t psp_v3_1_ring_init +ffffffff81e997f0 t psp_v3_1_ring_create +ffffffff81e9a2f0 t psp_v3_1_ring_stop +ffffffff81e9a510 t psp_v3_1_ring_destroy +ffffffff81e9a590 t psp_v3_1_smu_reload_quirk +ffffffff81e9a5e0 t psp_v3_1_mode1_reset +ffffffff81e9a6e0 t psp_v3_1_ring_get_wptr +ffffffff81e9a730 t psp_v3_1_ring_set_wptr +ffffffff81e9b000 t sdma_v2_4_early_init +ffffffff81e9b0e0 t sdma_v2_4_sw_init +ffffffff81e9b470 t sdma_v2_4_sw_fini +ffffffff81e9b550 t sdma_v2_4_hw_init +ffffffff81e9b910 t sdma_v2_4_hw_fini +ffffffff81e9b950 t sdma_v2_4_suspend +ffffffff81e9b990 t sdma_v2_4_resume +ffffffff81e9b9a0 t sdma_v2_4_is_idle +ffffffff81e9b9e0 t sdma_v2_4_wait_for_idle +ffffffff81e9ba80 t sdma_v2_4_soft_reset +ffffffff81e9bbc0 t sdma_v2_4_set_clockgating_state +ffffffff81e9bbf0 t sdma_v2_4_set_powergating_state +ffffffff81e9bc20 t sdma_v2_4_ring_get_rptr +ffffffff81e9bc60 t sdma_v2_4_ring_get_wptr +ffffffff81e9bcc0 t sdma_v2_4_ring_set_wptr +ffffffff81e9bd00 t sdma_v2_4_ring_emit_ib +ffffffff81e9bfb0 t sdma_v2_4_ring_emit_fence +ffffffff81e9c3b0 t sdma_v2_4_ring_emit_pipeline_sync +ffffffff81e9c630 t sdma_v2_4_ring_emit_vm_flush +ffffffff81e9c8b0 t sdma_v2_4_ring_emit_hdp_flush +ffffffff81e9cb30 t sdma_v2_4_ring_test_ring +ffffffff81e9ce10 t sdma_v2_4_ring_test_ib +ffffffff81e9cff0 t sdma_v2_4_ring_insert_nop +ffffffff81e9d120 t sdma_v2_4_ring_pad_ib +ffffffff81e9d250 t sdma_v2_4_ring_emit_wreg +ffffffff81e9d3a0 t sdma_v2_4_emit_copy_buffer +ffffffff81e9d460 t sdma_v2_4_emit_fill_buffer +ffffffff81e9d4f0 t sdma_v2_4_vm_copy_pte +ffffffff81e9d5b0 t sdma_v2_4_vm_write_pte +ffffffff81e9d680 t sdma_v2_4_vm_set_pte_pde +ffffffff81e9d780 t sdma_v2_4_set_trap_irq_state +ffffffff81e9d840 t sdma_v2_4_process_trap_irq +ffffffff81e9d8e0 t sdma_v2_4_process_illegal_inst_irq +ffffffff81e9d960 t sdma_v2_4_enable +ffffffff81e9e000 t sdma_v3_0_early_init +ffffffff81e9e150 t sdma_v3_0_sw_init +ffffffff81e9e500 t sdma_v3_0_sw_fini +ffffffff81e9e5e0 t sdma_v3_0_hw_init +ffffffff81e9e710 t sdma_v3_0_hw_fini +ffffffff81e9e760 t sdma_v3_0_suspend +ffffffff81e9e7b0 t sdma_v3_0_resume +ffffffff81e9e7c0 t sdma_v3_0_is_idle +ffffffff81e9e800 t sdma_v3_0_wait_for_idle +ffffffff81e9e8a0 t sdma_v3_0_check_soft_reset +ffffffff81e9e900 t sdma_v3_0_pre_soft_reset +ffffffff81e9e950 t sdma_v3_0_soft_reset +ffffffff81e9ea20 t sdma_v3_0_post_soft_reset +ffffffff81e9ea70 t sdma_v3_0_set_clockgating_state +ffffffff81e9ecd0 t sdma_v3_0_set_powergating_state +ffffffff81e9ed00 t sdma_v3_0_get_clockgating_state +ffffffff81e9ed80 t sdma_v3_0_ring_get_rptr +ffffffff81e9edc0 t sdma_v3_0_ring_get_wptr +ffffffff81e9ee40 t sdma_v3_0_ring_set_wptr +ffffffff81e9eef0 t sdma_v3_0_ring_emit_ib +ffffffff81e9f1a0 t sdma_v3_0_ring_emit_fence +ffffffff81e9f5a0 t sdma_v3_0_ring_emit_pipeline_sync +ffffffff81e9f820 t sdma_v3_0_ring_emit_vm_flush +ffffffff81e9faa0 t sdma_v3_0_ring_emit_hdp_flush +ffffffff81e9fd20 t sdma_v3_0_ring_test_ring +ffffffff81ea0000 t sdma_v3_0_ring_test_ib +ffffffff81ea01e0 t sdma_v3_0_ring_insert_nop +ffffffff81ea0310 t sdma_v3_0_ring_pad_ib +ffffffff81ea0440 t sdma_v3_0_ring_emit_wreg +ffffffff81ea0590 t sdma_v3_0_emit_copy_buffer +ffffffff81ea0650 t sdma_v3_0_emit_fill_buffer +ffffffff81ea06e0 t sdma_v3_0_vm_copy_pte +ffffffff81ea07a0 t sdma_v3_0_vm_write_pte +ffffffff81ea0870 t sdma_v3_0_vm_set_pte_pde +ffffffff81ea0970 t sdma_v3_0_set_trap_irq_state +ffffffff81ea0a30 t sdma_v3_0_process_trap_irq +ffffffff81ea0ad0 t sdma_v3_0_process_illegal_inst_irq +ffffffff81ea0b50 t sdma_v3_0_ctx_switch_enable +ffffffff81ea0ce0 t sdma_v3_0_enable +ffffffff81ea0e50 t sdma_v3_0_gfx_resume +ffffffff81ea2000 t sdma_v4_0_early_init +ffffffff81ea2580 t sdma_v4_0_late_init +ffffffff81ea2820 t sdma_v4_0_sw_init +ffffffff81ea2ba0 t sdma_v4_0_sw_fini +ffffffff81ea2c60 t sdma_v4_0_hw_init +ffffffff81ea5c00 t sdma_v4_0_hw_fini +ffffffff81ea5cc0 t sdma_v4_0_suspend +ffffffff81ea5d10 t sdma_v4_0_resume +ffffffff81ea5d90 t sdma_v4_0_is_idle +ffffffff81ea5ec0 t sdma_v4_0_wait_for_idle +ffffffff81ea6060 t sdma_v4_0_soft_reset +ffffffff81ea6090 t sdma_v4_0_set_clockgating_state +ffffffff81ea6590 t sdma_v4_0_set_powergating_state +ffffffff81ea6650 t sdma_v4_0_get_clockgating_state +ffffffff81ea66f0 t sdma_v4_0_query_ras_error_count +ffffffff81ea68c0 t sdma_v4_0_reset_ras_error_count +ffffffff81ea6a10 t sdma_v4_0_ring_get_rptr +ffffffff81ea6a70 t sdma_v4_0_ring_get_wptr +ffffffff81ea6c60 t sdma_v4_0_ring_set_wptr +ffffffff81ea6ee0 t sdma_v4_0_ring_emit_ib +ffffffff81ea7190 t sdma_v4_0_ring_emit_fence +ffffffff81ea75c0 t sdma_v4_0_ring_emit_pipeline_sync +ffffffff81ea7620 t sdma_v4_0_ring_emit_vm_flush +ffffffff81ea7640 t sdma_v4_0_ring_emit_hdp_flush +ffffffff81ea76e0 t sdma_v4_0_ring_test_ring +ffffffff81ea79c0 t sdma_v4_0_ring_test_ib +ffffffff81ea7ba0 t sdma_v4_0_ring_insert_nop +ffffffff81ea7cd0 t sdma_v4_0_ring_pad_ib +ffffffff81ea7e00 t sdma_v4_0_ring_emit_wreg +ffffffff81ea7f50 t sdma_v4_0_ring_emit_reg_wait +ffffffff81ea7fa0 t sdma_v4_0_wait_reg_mem +ffffffff81ea82d0 t sdma_v4_0_page_ring_get_wptr +ffffffff81ea8480 t sdma_v4_0_page_ring_set_wptr +ffffffff81ea8640 t sdma_v4_0_emit_copy_buffer +ffffffff81ea8700 t sdma_v4_0_emit_fill_buffer +ffffffff81ea8790 t sdma_v4_0_vm_copy_pte +ffffffff81ea8850 t sdma_v4_0_vm_write_pte +ffffffff81ea8920 t sdma_v4_0_vm_set_pte_pde +ffffffff81ea8a20 t sdma_v4_0_set_trap_irq_state +ffffffff81ea8bc0 t sdma_v4_0_process_trap_irq +ffffffff81ea8d00 t sdma_v4_0_process_illegal_inst_irq +ffffffff81ea8e20 t sdma_v4_0_set_ecc_irq_state +ffffffff81ea8fc0 t sdma_v4_0_process_vm_hole_irq +ffffffff81ea9100 t sdma_v4_0_process_doorbell_invalid_irq +ffffffff81ea9240 t sdma_v4_0_process_pool_timeout_irq +ffffffff81ea9380 t sdma_v4_0_process_srbm_write_irq +ffffffff81ea94c0 t sdma_v4_0_process_ras_data_cb +ffffffff81ea9540 t sdma_v4_0_ctx_switch_enable +ffffffff81ea9bf0 t sdma_v4_0_enable +ffffffff81eaa190 t sdma_v4_0_gfx_enable +ffffffff81eab000 t sdma_v4_4_query_ras_error_count +ffffffff81eab270 t sdma_v4_4_reset_ras_error_count +ffffffff81eac000 t sdma_v5_0_early_init +ffffffff81eac170 t sdma_v5_0_sw_init +ffffffff81eac410 t sdma_v5_0_sw_fini +ffffffff81eac4a0 t sdma_v5_0_hw_init +ffffffff81ead750 t sdma_v5_0_hw_fini +ffffffff81ead7b0 t sdma_v5_0_suspend +ffffffff81ead810 t sdma_v5_0_resume +ffffffff81ead820 t sdma_v5_0_is_idle +ffffffff81ead8b0 t sdma_v5_0_wait_for_idle +ffffffff81ead970 t sdma_v5_0_soft_reset +ffffffff81ead9a0 t sdma_v5_0_set_clockgating_state +ffffffff81eadba0 t sdma_v5_0_set_powergating_state +ffffffff81eadbd0 t sdma_v5_0_get_clockgating_state +ffffffff81eadc70 t sdma_v5_0_ring_get_rptr +ffffffff81eadcd0 t sdma_v5_0_ring_get_wptr +ffffffff81eade70 t sdma_v5_0_ring_set_wptr +ffffffff81eae1d0 t sdma_v5_0_ring_emit_ib +ffffffff81eae490 t sdma_v5_0_ring_emit_fence +ffffffff81eae900 t sdma_v5_0_ring_emit_pipeline_sync +ffffffff81eaeb80 t sdma_v5_0_ring_emit_vm_flush +ffffffff81eaeba0 t sdma_v5_0_ring_emit_hdp_flush +ffffffff81eaee40 t sdma_v5_0_ring_test_ring +ffffffff81eaf210 t sdma_v5_0_ring_test_ib +ffffffff81eaf540 t sdma_v5_0_ring_insert_nop +ffffffff81eaf670 t sdma_v5_0_ring_pad_ib +ffffffff81eaf7a0 t sdma_v5_0_ring_init_cond_exec +ffffffff81eaf9d0 t sdma_v5_0_ring_patch_cond_exec +ffffffff81eafa90 t sdma_v5_0_ring_emit_wreg +ffffffff81eafbe0 t sdma_v5_0_ring_emit_reg_wait +ffffffff81eafe60 t sdma_v5_0_ring_emit_reg_write_reg_wait +ffffffff81eafee0 t sdma_v5_0_ring_preempt_ib +ffffffff81eb0020 t sdma_v5_0_ring_emit_mem_sync +ffffffff81eb0230 t sdma_v5_0_emit_copy_buffer +ffffffff81eb02f0 t sdma_v5_0_emit_fill_buffer +ffffffff81eb0380 t sdma_v5_0_vm_copy_pte +ffffffff81eb0440 t sdma_v5_0_vm_write_pte +ffffffff81eb0510 t sdma_v5_0_vm_set_pte_pde +ffffffff81eb0610 t sdma_v5_0_set_trap_irq_state +ffffffff81eb06a0 t sdma_v5_0_process_trap_irq +ffffffff81eb07b0 t sdma_v5_0_process_illegal_inst_irq +ffffffff81eb07e0 t sdma_v5_0_mqd_init +ffffffff81eb08c0 t sdma_v5_0_ctx_switch_enable +ffffffff81eb0bc0 t sdma_v5_0_enable +ffffffff81eb1000 t sdma_v5_2_early_init +ffffffff81eb1170 t sdma_v5_2_sw_init +ffffffff81eb13a0 t sdma_v5_2_sw_fini +ffffffff81eb1430 t sdma_v5_2_hw_init +ffffffff81eb1770 t sdma_v5_2_hw_fini +ffffffff81eb17d0 t sdma_v5_2_suspend +ffffffff81eb1830 t sdma_v5_2_resume +ffffffff81eb1840 t sdma_v5_2_is_idle +ffffffff81eb1900 t sdma_v5_2_wait_for_idle +ffffffff81eb1a00 t sdma_v5_2_soft_reset +ffffffff81eb1ca0 t sdma_v5_2_set_clockgating_state +ffffffff81eb1fc0 t sdma_v5_2_set_powergating_state +ffffffff81eb1ff0 t sdma_v5_2_get_clockgating_state +ffffffff81eb2080 t sdma_v5_2_ring_get_rptr +ffffffff81eb20e0 t sdma_v5_2_ring_get_wptr +ffffffff81eb2220 t sdma_v5_2_ring_set_wptr +ffffffff81eb23e0 t sdma_v5_2_ring_emit_ib +ffffffff81eb26a0 t sdma_v5_2_ring_emit_fence +ffffffff81eb2b10 t sdma_v5_2_ring_emit_pipeline_sync +ffffffff81eb2d90 t sdma_v5_2_ring_emit_vm_flush +ffffffff81eb2db0 t sdma_v5_2_ring_emit_hdp_flush +ffffffff81eb3050 t sdma_v5_2_ring_test_ring +ffffffff81eb3420 t sdma_v5_2_ring_test_ib +ffffffff81eb3750 t sdma_v5_2_ring_insert_nop +ffffffff81eb3880 t sdma_v5_2_ring_pad_ib +ffffffff81eb39b0 t sdma_v5_2_ring_init_cond_exec +ffffffff81eb3be0 t sdma_v5_2_ring_patch_cond_exec +ffffffff81eb3ca0 t sdma_v5_2_ring_emit_wreg +ffffffff81eb3df0 t sdma_v5_2_ring_emit_reg_wait +ffffffff81eb4070 t sdma_v5_2_ring_emit_reg_write_reg_wait +ffffffff81eb40f0 t sdma_v5_2_ring_preempt_ib +ffffffff81eb4260 t sdma_v5_2_ring_emit_mem_sync +ffffffff81eb4470 t sdma_v5_2_emit_copy_buffer +ffffffff81eb4530 t sdma_v5_2_emit_fill_buffer +ffffffff81eb45c0 t sdma_v5_2_vm_copy_pte +ffffffff81eb4680 t sdma_v5_2_vm_write_pte +ffffffff81eb4750 t sdma_v5_2_vm_set_pte_pde +ffffffff81eb4850 t sdma_v5_2_set_trap_irq_state +ffffffff81eb4910 t sdma_v5_2_process_trap_irq +ffffffff81eb4a50 t sdma_v5_2_process_illegal_inst_irq +ffffffff81eb4a80 t sdma_v5_2_mqd_init +ffffffff81eb4b60 t sdma_v5_2_ctx_switch_enable +ffffffff81eb4f60 t sdma_v5_2_enable +ffffffff81eb5370 t sdma_v5_2_gfx_resume +ffffffff81eb7000 t sdma_v6_0_early_init +ffffffff81eb7140 t sdma_v6_0_sw_init +ffffffff81eb7320 t sdma_v6_0_sw_fini +ffffffff81eb73b0 t sdma_v6_0_hw_init +ffffffff81eb73c0 t sdma_v6_0_hw_fini +ffffffff81eb7410 t sdma_v6_0_suspend +ffffffff81eb7460 t sdma_v6_0_resume +ffffffff81eb7470 t sdma_v6_0_is_idle +ffffffff81eb7500 t sdma_v6_0_wait_for_idle +ffffffff81eb75c0 t sdma_v6_0_check_soft_reset +ffffffff81eb7680 t sdma_v6_0_soft_reset +ffffffff81eb7b20 t sdma_v6_0_set_clockgating_state +ffffffff81eb7b50 t sdma_v6_0_set_powergating_state +ffffffff81eb7b80 t sdma_v6_0_get_clockgating_state +ffffffff81eb7bb0 t sdma_v6_0_ring_get_rptr +ffffffff81eb7c10 t sdma_v6_0_ring_get_wptr +ffffffff81eb7c80 t sdma_v6_0_ring_set_wptr +ffffffff81eb7fe0 t sdma_v6_0_ring_emit_ib +ffffffff81eb82a0 t sdma_v6_0_ring_emit_fence +ffffffff81eb8710 t sdma_v6_0_ring_emit_pipeline_sync +ffffffff81eb8990 t sdma_v6_0_ring_emit_vm_flush +ffffffff81eb89b0 t sdma_v6_0_ring_emit_hdp_flush +ffffffff81eb8c50 t sdma_v6_0_ring_test_ring +ffffffff81eb9020 t sdma_v6_0_ring_test_ib +ffffffff81eb9350 t sdma_v6_0_ring_insert_nop +ffffffff81eb9480 t sdma_v6_0_ring_pad_ib +ffffffff81eb95b0 t sdma_v6_0_ring_init_cond_exec +ffffffff81eb97e0 t sdma_v6_0_ring_patch_cond_exec +ffffffff81eb98a0 t sdma_v6_0_ring_emit_wreg +ffffffff81eb99f0 t sdma_v6_0_ring_emit_reg_wait +ffffffff81eb9c70 t sdma_v6_0_ring_emit_reg_write_reg_wait +ffffffff81eb9cf0 t sdma_v6_0_ring_preempt_ib +ffffffff81eb9e40 t sdma_v6_0_ring_emit_mem_sync +ffffffff81eba050 t sdma_v6_0_emit_copy_buffer +ffffffff81eba110 t sdma_v6_0_emit_fill_buffer +ffffffff81eba1a0 t sdma_v6_0_vm_copy_pte +ffffffff81eba260 t sdma_v6_0_vm_write_pte +ffffffff81eba330 t sdma_v6_0_vm_set_pte_pde +ffffffff81eba430 t sdma_v6_0_set_trap_irq_state +ffffffff81eba4c0 t sdma_v6_0_process_trap_irq +ffffffff81eba5f0 t sdma_v6_0_process_illegal_inst_irq +ffffffff81eba620 t sdma_v6_0_mqd_init +ffffffff81eba740 t sdma_v6_0_start +ffffffff81eba9c0 t sdma_v6_0_enable +ffffffff81ebab40 t sdma_v6_0_gfx_resume +ffffffff81ebbbc0 t sdma_v6_0_gfx_stop +ffffffff81ebc000 T sienna_cichlid_reset_init +ffffffff81ebc0c0 t sienna_cichlid_async_reset +ffffffff81ebc120 t sienna_cichlid_get_reset_handler +ffffffff81ebc180 T sienna_cichlid_reset_fini +ffffffff81ebc1e0 t sienna_cichlid_mode2_prepare_hwcontext +ffffffff81ebc330 t sienna_cichlid_mode2_perform_reset +ffffffff81ebc3b0 t sienna_cichlid_mode2_restore_hwcontext +ffffffff81ebc6b0 t sienna_cichlid_mode2_reset +ffffffff81ebd000 T smu_v11_0_i2c_control_init +ffffffff81ebd0d0 T smu_v11_0_i2c_control_fini +ffffffff81ebd110 t smu_v11_0_i2c_xfer +ffffffff81ebe1f0 t smu_v11_0_i2c_func +ffffffff81ebe220 t smu_v11_0_i2c_enable +ffffffff81ebe360 t smu_v11_0_i2c_abort +ffffffff81ebe460 t lock_bus +ffffffff81ebe500 t trylock_bus +ffffffff81ebe550 t unlock_bus +ffffffff81ebf000 t smuio_v11_0_get_rom_index_offset +ffffffff81ebf040 t smuio_v11_0_get_rom_data_offset +ffffffff81ebf080 t smuio_v11_0_update_rom_clock_gating +ffffffff81ebf1c0 t smuio_v11_0_get_clock_gating_state +ffffffff81ec0000 t smuio_v11_0_6_get_rom_index_offset +ffffffff81ec0040 t smuio_v11_0_6_get_rom_data_offset +ffffffff81ec0080 t smuio_v11_0_6_update_rom_clock_gating +ffffffff81ec01c0 t smuio_v11_0_6_get_clock_gating_state +ffffffff81ec1000 t smuio_v13_0_get_rom_index_offset +ffffffff81ec1040 t smuio_v13_0_get_rom_data_offset +ffffffff81ec1080 t smuio_v13_0_update_rom_clock_gating +ffffffff81ec11c0 t smuio_v13_0_get_clock_gating_state +ffffffff81ec1260 t smuio_v13_0_get_die_id +ffffffff81ec12e0 t smuio_v13_0_get_socket_id +ffffffff81ec1360 t smuio_v13_0_is_host_gpu_xgmi_supported +ffffffff81ec2000 t smuio_v13_0_6_get_rom_index_offset +ffffffff81ec2040 t smuio_v13_0_6_get_rom_data_offset +ffffffff81ec3000 t smuio_v9_0_get_rom_index_offset +ffffffff81ec3040 t smuio_v9_0_get_rom_data_offset +ffffffff81ec3080 t smuio_v9_0_update_rom_clock_gating +ffffffff81ec31c0 t smuio_v9_0_get_clock_gating_state +ffffffff81ec4000 T soc15_grbm_select +ffffffff81ec4080 T soc15_program_register_sequence +ffffffff81ec4280 T soc15_set_virt_ops +ffffffff81ec42f0 t soc15_common_early_init +ffffffff81ec4680 t soc15_common_late_init +ffffffff81ec46c0 t soc15_common_sw_init +ffffffff81ec4720 t soc15_common_sw_fini +ffffffff81ec4770 t soc15_common_hw_init +ffffffff81ec48a0 t soc15_common_hw_fini +ffffffff81ec4970 t soc15_common_suspend +ffffffff81ec49b0 t soc15_common_resume +ffffffff81ec49f0 t soc15_common_is_idle +ffffffff81ec4a20 t soc15_common_wait_for_idle +ffffffff81ec4a50 t soc15_common_soft_reset +ffffffff81ec4a80 t soc15_common_set_clockgating_state +ffffffff81ec4dc0 t soc15_common_set_powergating_state +ffffffff81ec4df0 t soc15_common_get_clockgating_state +ffffffff81ec4ed0 t soc15_pcie_rreg +ffffffff81ec4f30 t soc15_pcie_wreg +ffffffff81ec4f90 t soc15_pcie_rreg64 +ffffffff81ec4ff0 t soc15_pcie_wreg64 +ffffffff81ec5050 t soc15_uvd_ctx_rreg +ffffffff81ec50f0 t soc15_uvd_ctx_wreg +ffffffff81ec5180 t soc15_didt_rreg +ffffffff81ec5220 t soc15_didt_wreg +ffffffff81ec52a0 t soc15_gc_cac_rreg +ffffffff81ec53c0 t soc15_gc_cac_wreg +ffffffff81ec54d0 t soc15_se_cac_rreg +ffffffff81ec55f0 t soc15_se_cac_wreg +ffffffff81ec5700 t soc15_read_disabled_bios +ffffffff81ec5730 t soc15_read_register +ffffffff81ec5830 t soc15_vga_set_state +ffffffff81ec5860 t soc15_asic_reset +ffffffff81ec5960 t soc15_asic_reset_method +ffffffff81ec5ae0 t soc15_get_xclk +ffffffff81ec5b30 t soc15_set_uvd_clocks +ffffffff81ec5b60 t soc15_set_vce_clocks +ffffffff81ec5b90 t soc15_get_config_memsize +ffffffff81ec5bb0 t soc15_need_full_reset +ffffffff81ec5be0 t soc15_get_pcie_usage +ffffffff81ec5d10 t soc15_need_reset_on_init +ffffffff81ec5db0 t soc15_get_pcie_replay_count +ffffffff81ec5e20 t soc15_supports_baco +ffffffff81ec5e80 t soc15_pre_asic_init +ffffffff81ec5e90 t soc15_query_video_codecs +ffffffff81ec5f40 t vega20_get_pcie_usage +ffffffff81ec7000 T soc21_grbm_select +ffffffff81ec7080 t soc21_common_early_init +ffffffff81ec72d0 t soc21_common_late_init +ffffffff81ec7300 t soc21_common_sw_init +ffffffff81ec7330 t soc21_common_sw_fini +ffffffff81ec7360 t soc21_common_hw_init +ffffffff81ec7430 t soc21_common_hw_fini +ffffffff81ec7490 t soc21_common_suspend +ffffffff81ec74f0 t soc21_common_resume +ffffffff81ec75c0 t soc21_common_is_idle +ffffffff81ec75f0 t soc21_common_wait_for_idle +ffffffff81ec7620 t soc21_common_soft_reset +ffffffff81ec7650 t soc21_common_set_clockgating_state +ffffffff81ec7700 t soc21_common_set_powergating_state +ffffffff81ec7760 t soc21_common_get_clockgating_state +ffffffff81ec77b0 t soc21_pcie_rreg +ffffffff81ec7810 t soc21_pcie_wreg +ffffffff81ec7870 t soc21_pcie_rreg64 +ffffffff81ec78d0 t soc21_pcie_wreg64 +ffffffff81ec7930 t soc21_didt_rreg +ffffffff81ec79d0 t soc21_didt_wreg +ffffffff81ec7a50 t soc21_read_disabled_bios +ffffffff81ec7a80 t soc21_read_register +ffffffff81ec7b70 t soc21_vga_set_state +ffffffff81ec7ba0 t soc21_asic_reset +ffffffff81ec7c80 t soc21_asic_reset_method +ffffffff81ec7d40 t soc21_get_xclk +ffffffff81ec7d70 t soc21_set_uvd_clocks +ffffffff81ec7da0 t soc21_set_vce_clocks +ffffffff81ec7dd0 t soc21_get_config_memsize +ffffffff81ec7df0 t soc21_need_full_reset +ffffffff81ec7e50 t soc21_init_doorbell_index +ffffffff81ec7f70 t soc21_need_reset_on_init +ffffffff81ec8000 t soc21_get_pcie_replay_count +ffffffff81ec8030 t soc21_pre_asic_init +ffffffff81ec8060 t soc21_update_umd_stable_pstate +ffffffff81ec80d0 t soc21_query_video_codecs +ffffffff81ec9000 t tonga_ih_early_init +ffffffff81ec9050 t tonga_ih_sw_init +ffffffff81ec90d0 t tonga_ih_sw_fini +ffffffff81ec9110 t tonga_ih_hw_init +ffffffff81ec9300 t tonga_ih_hw_fini +ffffffff81ec93a0 t tonga_ih_suspend +ffffffff81ec9440 t tonga_ih_resume +ffffffff81ec9480 t tonga_ih_is_idle +ffffffff81ec94d0 t tonga_ih_wait_for_idle +ffffffff81ec9570 t tonga_ih_check_soft_reset +ffffffff81ec95d0 t tonga_ih_pre_soft_reset +ffffffff81ec9680 t tonga_ih_soft_reset +ffffffff81ec9750 t tonga_ih_post_soft_reset +ffffffff81ec9790 t tonga_ih_set_clockgating_state +ffffffff81ec97c0 t tonga_ih_set_powergating_state +ffffffff81ec97f0 t tonga_ih_get_wptr +ffffffff81ec98e0 t tonga_ih_decode_iv +ffffffff81ec9960 t tonga_ih_set_rptr +ffffffff81eca000 t umc_v6_0_init_registers +ffffffff81ecb000 t umc_v6_1_query_ras_error_count +ffffffff81ecb4e0 t umc_v6_1_query_ras_error_address +ffffffff81ecb7c0 t umc_v6_1_err_cnt_init +ffffffff81ecc000 t umc_v6_7_query_ras_error_count +ffffffff81ecc410 t umc_v6_7_query_ras_error_address +ffffffff81ecc590 t umc_v6_7_query_ras_poison_mode +ffffffff81ecc5f0 t umc_v6_7_convert_error_address +ffffffff81ecc8f0 t umc_v6_7_ecc_info_query_ras_error_count +ffffffff81eccb30 t umc_v6_7_ecc_info_query_ras_error_address +ffffffff81ecd000 t umc_v8_10_query_ras_error_count +ffffffff81ecd280 t umc_v8_10_query_ras_error_address +ffffffff81ecd5b0 t umc_v8_10_err_cnt_init +ffffffff81ecd730 t umc_v8_10_query_ras_poison_mode +ffffffff81ece000 t umc_v8_7_query_ras_error_count +ffffffff81ece310 t umc_v8_7_query_ras_error_address +ffffffff81ece4c0 t umc_v8_7_err_cnt_init +ffffffff81ece610 t umc_v8_7_ecc_info_query_ras_error_count +ffffffff81ece740 t umc_v8_7_ecc_info_query_ras_error_address +ffffffff81ecf000 t uvd_v5_0_early_init +ffffffff81ecf050 t uvd_v5_0_sw_init +ffffffff81ecf140 t uvd_v5_0_sw_fini +ffffffff81ecf190 t uvd_v5_0_hw_init +ffffffff81ecf6a0 t uvd_v5_0_hw_fini +ffffffff81ecf720 t uvd_v5_0_suspend +ffffffff81ecf820 t uvd_v5_0_resume +ffffffff81ecf870 t uvd_v5_0_is_idle +ffffffff81ecf8c0 t uvd_v5_0_wait_for_idle +ffffffff81ecf950 t uvd_v5_0_soft_reset +ffffffff81ecf9f0 t uvd_v5_0_set_clockgating_state +ffffffff81ecfb90 t uvd_v5_0_set_powergating_state +ffffffff81ecfbd0 t uvd_v5_0_get_clockgating_state +ffffffff81ecfc50 t uvd_v5_0_ring_get_rptr +ffffffff81ecfc90 t uvd_v5_0_ring_get_wptr +ffffffff81ecfcd0 t uvd_v5_0_ring_set_wptr +ffffffff81ecfd00 t uvd_v5_0_ring_emit_ib +ffffffff81ecff70 t uvd_v5_0_ring_emit_fence +ffffffff81ed0520 t uvd_v5_0_ring_test_ring +ffffffff81ed06c0 t uvd_v5_0_ring_insert_nop +ffffffff81ed0820 t uvd_v5_0_set_interrupt_state +ffffffff81ed0850 t uvd_v5_0_process_interrupt +ffffffff81ed08b0 t uvd_v5_0_stop +ffffffff81ed09c0 t uvd_v5_0_start +ffffffff81ed2000 t uvd_v6_0_early_init +ffffffff81ed2140 t uvd_v6_0_sw_init +ffffffff81ed2460 t uvd_v6_0_sw_fini +ffffffff81ed2520 t uvd_v6_0_hw_init +ffffffff81ed2ae0 t uvd_v6_0_hw_fini +ffffffff81ed2b60 t uvd_v6_0_suspend +ffffffff81ed2c60 t uvd_v6_0_resume +ffffffff81ed2cb0 t uvd_v6_0_is_idle +ffffffff81ed2d00 t uvd_v6_0_wait_for_idle +ffffffff81ed2d90 t uvd_v6_0_check_soft_reset +ffffffff81ed2e10 t uvd_v6_0_pre_soft_reset +ffffffff81ed2e50 t uvd_v6_0_soft_reset +ffffffff81ed2f20 t uvd_v6_0_post_soft_reset +ffffffff81ed2fc0 t uvd_v6_0_set_clockgating_state +ffffffff81ed3150 t uvd_v6_0_set_powergating_state +ffffffff81ed31c0 t uvd_v6_0_get_clockgating_state +ffffffff81ed3250 t uvd_v6_0_ring_get_rptr +ffffffff81ed3290 t uvd_v6_0_ring_get_wptr +ffffffff81ed32d0 t uvd_v6_0_ring_set_wptr +ffffffff81ed3300 t uvd_v6_0_ring_emit_ib +ffffffff81ed3660 t uvd_v6_0_ring_emit_fence +ffffffff81ed3c10 t uvd_v6_0_ring_emit_pipeline_sync +ffffffff81ed4010 t uvd_v6_0_ring_emit_vm_flush +ffffffff81ed4370 t uvd_v6_0_ring_emit_hdp_flush +ffffffff81ed43a0 t uvd_v6_0_ring_test_ring +ffffffff81ed4540 t uvd_v6_0_ring_insert_nop +ffffffff81ed46a0 t uvd_v6_0_ring_emit_wreg +ffffffff81ed4920 t uvd_v6_0_enc_ring_get_rptr +ffffffff81ed4980 t uvd_v6_0_enc_ring_get_wptr +ffffffff81ed49e0 t uvd_v6_0_enc_ring_set_wptr +ffffffff81ed4a20 t uvd_v6_0_enc_ring_emit_ib +ffffffff81ed4c60 t uvd_v6_0_enc_ring_emit_fence +ffffffff81ed4ea0 t uvd_v6_0_enc_ring_emit_pipeline_sync +ffffffff81ed5050 t uvd_v6_0_enc_ring_emit_vm_flush +ffffffff81ed5260 t uvd_v6_0_enc_ring_test_ring +ffffffff81ed53b0 t uvd_v6_0_enc_ring_test_ib +ffffffff81ed5970 t uvd_v6_0_enc_ring_insert_end +ffffffff81ed5a00 t uvd_v6_0_set_interrupt_state +ffffffff81ed5a30 t uvd_v6_0_process_interrupt +ffffffff81ed5b20 t uvd_v6_0_stop +ffffffff81ed5c30 t uvd_v6_0_start +ffffffff81ed7000 t uvd_v7_0_early_init +ffffffff81ed7270 t uvd_v7_0_sw_init +ffffffff81ed75f0 t uvd_v7_0_sw_fini +ffffffff81ed7700 t uvd_v7_0_hw_init +ffffffff81eda620 t uvd_v7_0_hw_fini +ffffffff81eda930 t uvd_v7_0_suspend +ffffffff81eda9e0 t uvd_v7_0_resume +ffffffff81edaa30 t uvd_v7_0_set_clockgating_state +ffffffff81edaa60 t uvd_v7_0_ring_get_rptr +ffffffff81edab00 t uvd_v7_0_ring_get_wptr +ffffffff81edaba0 t uvd_v7_0_ring_set_wptr +ffffffff81edac20 t uvd_v7_0_ring_patch_cs_in_place +ffffffff81edaca0 t uvd_v7_0_ring_emit_ib +ffffffff81edb050 t uvd_v7_0_ring_emit_fence +ffffffff81edb6b0 t uvd_v7_0_ring_emit_vm_flush +ffffffff81edb720 t uvd_v7_0_ring_emit_hdp_flush +ffffffff81edb750 t uvd_v7_0_ring_test_ring +ffffffff81edb9e0 t uvd_v7_0_ring_insert_nop +ffffffff81edbb80 t uvd_v7_0_ring_emit_wreg +ffffffff81edbe50 t uvd_v7_0_ring_emit_reg_wait +ffffffff81edc1f0 t uvd_v7_0_enc_ring_get_rptr +ffffffff81edc2e0 t uvd_v7_0_enc_ring_get_wptr +ffffffff81edc3e0 t uvd_v7_0_enc_ring_set_wptr +ffffffff81edc4e0 t uvd_v7_0_enc_ring_emit_ib +ffffffff81edc720 t uvd_v7_0_enc_ring_emit_fence +ffffffff81edc960 t uvd_v7_0_enc_ring_emit_vm_flush +ffffffff81edc9d0 t uvd_v7_0_enc_ring_test_ring +ffffffff81edcb30 t uvd_v7_0_enc_ring_test_ib +ffffffff81edd0f0 t uvd_v7_0_enc_ring_insert_end +ffffffff81edd180 t uvd_v7_0_enc_ring_emit_wreg +ffffffff81edd2e0 t uvd_v7_0_enc_ring_emit_reg_wait +ffffffff81edd4a0 t uvd_v7_0_set_interrupt_state +ffffffff81edd4d0 t uvd_v7_0_process_interrupt +ffffffff81ede000 t vce_v3_0_early_init +ffffffff81ede180 t vce_v3_0_sw_init +ffffffff81ede2d0 t vce_v3_0_sw_fini +ffffffff81ede320 t vce_v3_0_hw_init +ffffffff81ede400 t vce_v3_0_hw_fini +ffffffff81ede4f0 t vce_v3_0_suspend +ffffffff81ede5c0 t vce_v3_0_resume +ffffffff81ede610 t vce_v3_0_is_idle +ffffffff81ede680 t vce_v3_0_wait_for_idle +ffffffff81ede730 t vce_v3_0_check_soft_reset +ffffffff81ede830 t vce_v3_0_pre_soft_reset +ffffffff81ede8d0 t vce_v3_0_soft_reset +ffffffff81ede9a0 t vce_v3_0_post_soft_reset +ffffffff81edeb00 t vce_v3_0_set_clockgating_state +ffffffff81ededf0 t vce_v3_0_set_powergating_state +ffffffff81edf640 t vce_v3_0_get_clockgating_state +ffffffff81edf700 t vce_v3_0_ring_get_rptr +ffffffff81edf7d0 t vce_v3_0_ring_get_wptr +ffffffff81edf8a0 t vce_v3_0_ring_set_wptr +ffffffff81edf960 t vce_v3_0_ring_emit_ib +ffffffff81edfba0 t vce_v3_0_emit_pipeline_sync +ffffffff81edfd50 t vce_v3_0_emit_vm_flush +ffffffff81edffc0 t vce_v3_0_set_interrupt_state +ffffffff81ee0030 t vce_v3_0_process_interrupt +ffffffff81ee00f0 t vce_v3_0_stop +ffffffff81ee1000 t vce_v4_0_early_init +ffffffff81ee10b0 t vce_v4_0_sw_init +ffffffff81ee12e0 t vce_v4_0_sw_fini +ffffffff81ee1360 t vce_v4_0_hw_init +ffffffff81ee1b40 t vce_v4_0_hw_fini +ffffffff81ee1be0 t vce_v4_0_suspend +ffffffff81ee1e00 t vce_v4_0_resume +ffffffff81ee1eb0 t vce_v4_0_set_clockgating_state +ffffffff81ee1ee0 t vce_v4_0_set_powergating_state +ffffffff81ee1fc0 t vce_v4_0_ring_get_rptr +ffffffff81ee2030 t vce_v4_0_ring_get_wptr +ffffffff81ee20c0 t vce_v4_0_ring_set_wptr +ffffffff81ee2150 t vce_v4_0_ring_emit_ib +ffffffff81ee2390 t vce_v4_0_ring_emit_fence +ffffffff81ee25d0 t vce_v4_0_emit_vm_flush +ffffffff81ee2640 t vce_v4_0_ring_insert_end +ffffffff81ee26d0 t vce_v4_0_emit_wreg +ffffffff81ee2830 t vce_v4_0_emit_reg_wait +ffffffff81ee29f0 t vce_v4_0_set_interrupt_state +ffffffff81ee2a80 t vce_v4_0_process_interrupt +ffffffff81ee2b20 t vce_v4_0_start +ffffffff81ee3500 t vce_v4_0_stop +ffffffff81ee4000 T vcn_dec_sw_ring_emit_fence +ffffffff81ee4240 T vcn_dec_sw_ring_insert_end +ffffffff81ee42d0 T vcn_dec_sw_ring_emit_ib +ffffffff81ee4510 T vcn_dec_sw_ring_emit_reg_wait +ffffffff81ee46d0 T vcn_dec_sw_ring_emit_vm_flush +ffffffff81ee4740 T vcn_dec_sw_ring_emit_wreg +ffffffff81ee5000 T vcn_v1_0_set_pg_for_begin_use +ffffffff81ee5150 T vcn_v1_0_ring_end_use +ffffffff81ee51c0 t vcn_v1_0_early_init +ffffffff81ee5340 t vcn_v1_0_sw_init +ffffffff81ee55e0 t vcn_v1_0_sw_fini +ffffffff81ee5640 t vcn_v1_0_hw_init +ffffffff81ee5720 t vcn_v1_0_hw_fini +ffffffff81ee5820 t vcn_v1_0_suspend +ffffffff81ee5890 t vcn_v1_0_resume +ffffffff81ee5980 t vcn_v1_0_is_idle +ffffffff81ee5a10 t vcn_v1_0_wait_for_idle +ffffffff81ee5b00 t vcn_v1_0_set_clockgating_state +ffffffff81ee5bb0 t vcn_v1_0_set_powergating_state +ffffffff81ee6540 t vcn_v1_0_dec_ring_get_rptr +ffffffff81ee65d0 t vcn_v1_0_dec_ring_get_wptr +ffffffff81ee6660 t vcn_v1_0_dec_ring_set_wptr +ffffffff81ee6770 t vcn_v1_0_ring_patch_cs_in_place +ffffffff81ee6940 t vcn_v1_0_dec_ring_emit_ib +ffffffff81ee6cd0 t vcn_v1_0_dec_ring_emit_fence +ffffffff81ee7300 t vcn_v1_0_dec_ring_emit_vm_flush +ffffffff81ee7370 t vcn_v1_0_dec_ring_insert_nop +ffffffff81ee7500 t vcn_v1_0_dec_ring_insert_start +ffffffff81ee76e0 t vcn_v1_0_dec_ring_insert_end +ffffffff81ee77f0 t vcn_v1_0_ring_begin_use +ffffffff81ee7890 t vcn_v1_0_dec_ring_emit_wreg +ffffffff81ee7b40 t vcn_v1_0_dec_ring_emit_reg_wait +ffffffff81ee7ec0 t vcn_v1_0_enc_ring_get_rptr +ffffffff81ee7f90 t vcn_v1_0_enc_ring_get_wptr +ffffffff81ee8060 t vcn_v1_0_enc_ring_set_wptr +ffffffff81ee8120 t vcn_v1_0_enc_ring_emit_ib +ffffffff81ee8360 t vcn_v1_0_enc_ring_emit_fence +ffffffff81ee85a0 t vcn_v1_0_enc_ring_emit_vm_flush +ffffffff81ee8610 t vcn_v1_0_enc_ring_insert_end +ffffffff81ee86a0 t vcn_v1_0_enc_ring_emit_wreg +ffffffff81ee8800 t vcn_v1_0_enc_ring_emit_reg_wait +ffffffff81ee89c0 t vcn_v1_0_set_interrupt_state +ffffffff81ee89f0 t vcn_v1_0_process_interrupt +ffffffff81ee8aa0 t vcn_v1_0_idle_work_handler +ffffffff81ee8c30 t vcn_v1_0_pause_dpg_mode +ffffffff81ee9d50 t vcn_v1_0_enable_clock_gating +ffffffff81eea160 t vcn_v1_0_disable_clock_gating +ffffffff81eea6f0 t vcn_1_0_enable_static_power_gating +ffffffff81eea910 t vcn_v1_0_start_dpg_mode +ffffffff81eee540 t vcn_v1_0_start_spg_mode +ffffffff81ef0760 t vcn_v1_0_clock_gating_dpg_mode +ffffffff81ef1000 T vcn_v2_0_dec_ring_insert_start +ffffffff81ef11c0 T vcn_v2_0_dec_ring_insert_end +ffffffff81ef12c0 T vcn_v2_0_dec_ring_insert_nop +ffffffff81ef1430 T vcn_v2_0_dec_ring_emit_fence +ffffffff81ef19f0 T vcn_v2_0_dec_ring_emit_ib +ffffffff81ef1d50 T vcn_v2_0_dec_ring_emit_reg_wait +ffffffff81ef20a0 T vcn_v2_0_dec_ring_emit_vm_flush +ffffffff81ef2110 T vcn_v2_0_dec_ring_emit_wreg +ffffffff81ef23a0 T vcn_v2_0_enc_ring_emit_fence +ffffffff81ef25e0 T vcn_v2_0_enc_ring_insert_end +ffffffff81ef2670 T vcn_v2_0_enc_ring_emit_ib +ffffffff81ef28b0 T vcn_v2_0_enc_ring_emit_reg_wait +ffffffff81ef2a70 T vcn_v2_0_enc_ring_emit_vm_flush +ffffffff81ef2ae0 T vcn_v2_0_enc_ring_emit_wreg +ffffffff81ef2c40 T vcn_v2_0_dec_ring_test_ring +ffffffff81ef2ee0 t vcn_v2_0_early_init +ffffffff81ef3060 t vcn_v2_0_sw_init +ffffffff81ef3370 t vcn_v2_0_sw_fini +ffffffff81ef33f0 t vcn_v2_0_hw_init +ffffffff81ef3da0 t vcn_v2_0_hw_fini +ffffffff81ef3ea0 t vcn_v2_0_suspend +ffffffff81ef3ed0 t vcn_v2_0_resume +ffffffff81ef3f20 t vcn_v2_0_is_idle +ffffffff81ef3fb0 t vcn_v2_0_wait_for_idle +ffffffff81ef40a0 t vcn_v2_0_set_clockgating_state +ffffffff81ef4130 t vcn_v2_0_set_powergating_state +ffffffff81ef63f0 t vcn_v2_0_dec_ring_get_rptr +ffffffff81ef6480 t vcn_v2_0_dec_ring_get_wptr +ffffffff81ef6520 t vcn_v2_0_dec_ring_set_wptr +ffffffff81ef6650 t vcn_v2_0_enc_ring_get_rptr +ffffffff81ef6720 t vcn_v2_0_enc_ring_get_wptr +ffffffff81ef6810 t vcn_v2_0_enc_ring_set_wptr +ffffffff81ef6900 t vcn_v2_0_set_interrupt_state +ffffffff81ef6930 t vcn_v2_0_process_interrupt +ffffffff81ef69e0 t vcn_v2_0_pause_dpg_mode +ffffffff81ef7340 t vcn_v2_0_enable_clock_gating +ffffffff81ef75c0 t vcn_v2_0_disable_clock_gating +ffffffff81ef79c0 t vcn_v2_0_enable_static_power_gating +ffffffff81ef7ba0 t vcn_v2_0_start_dpg_mode +ffffffff81efc660 t vcn_v2_0_clock_gating_dpg_mode +ffffffff81efd000 t vcn_v2_6_query_poison_status +ffffffff81efd0d0 t vcn_v2_5_early_init +ffffffff81efd410 t vcn_v2_5_sw_init +ffffffff81efd890 t vcn_v2_5_sw_fini +ffffffff81efd960 t vcn_v2_5_hw_init +ffffffff81efe420 t vcn_v2_5_hw_fini +ffffffff81efe560 t vcn_v2_5_suspend +ffffffff81efe590 t vcn_v2_5_resume +ffffffff81efe5e0 t vcn_v2_5_is_idle +ffffffff81efe6d0 t vcn_v2_5_wait_for_idle +ffffffff81efe800 t vcn_v2_5_set_clockgating_state +ffffffff81efe880 t vcn_v2_5_set_powergating_state +ffffffff81eff160 t vcn_v2_5_dec_ring_get_rptr +ffffffff81eff200 t vcn_v2_5_dec_ring_get_wptr +ffffffff81eff2b0 t vcn_v2_5_dec_ring_set_wptr +ffffffff81eff360 t vcn_v2_5_enc_ring_get_rptr +ffffffff81eff450 t vcn_v2_5_enc_ring_get_wptr +ffffffff81eff550 t vcn_v2_5_enc_ring_set_wptr +ffffffff81eff650 t vcn_v2_5_set_interrupt_state +ffffffff81eff680 t vcn_v2_5_process_interrupt +ffffffff81eff7a0 t vcn_v2_5_pause_dpg_mode +ffffffff81f00110 t vcn_v2_5_enable_clock_gating +ffffffff81f00410 t vcn_v2_5_disable_clock_gating +ffffffff81f00930 t vcn_v2_5_start +ffffffff81f04530 t vcn_v2_5_clock_gating_dpg_mode +ffffffff81f04ed0 t vcn_v2_5_mc_resume_dpg_mode +ffffffff81f08000 t vcn_v3_0_early_init +ffffffff81f08220 t vcn_v3_0_sw_init +ffffffff81f086d0 t vcn_v3_0_sw_fini +ffffffff81f087b0 t vcn_v3_0_hw_init +ffffffff81f09350 t vcn_v3_0_hw_fini +ffffffff81f09450 t vcn_v3_0_suspend +ffffffff81f09480 t vcn_v3_0_resume +ffffffff81f094d0 t vcn_v3_0_is_idle +ffffffff81f095c0 t vcn_v3_0_wait_for_idle +ffffffff81f096f0 t vcn_v3_0_set_clockgating_state +ffffffff81f09800 t vcn_v3_0_set_powergating_state +ffffffff81f0c080 t vcn_v3_0_dec_ring_get_rptr +ffffffff81f0c120 t vcn_v3_0_dec_ring_get_wptr +ffffffff81f0c1d0 t vcn_v3_0_dec_ring_set_wptr +ffffffff81f0c340 t vcn_v3_0_ring_patch_cs_in_place +ffffffff81f0c640 t vcn_v3_0_enc_ring_get_rptr +ffffffff81f0c730 t vcn_v3_0_enc_ring_get_wptr +ffffffff81f0c830 t vcn_v3_0_enc_ring_set_wptr +ffffffff81f0c930 t vcn_v3_0_set_interrupt_state +ffffffff81f0c960 t vcn_v3_0_process_interrupt +ffffffff81f0ca50 t vcn_v3_0_pause_dpg_mode +ffffffff81f0d3c0 t vcn_v3_0_enable_clock_gating +ffffffff81f0d640 t vcn_v3_0_disable_clock_gating +ffffffff81f0dbe0 t vcn_v3_0_start_dpg_mode +ffffffff81f12980 t vcn_v3_0_clock_gating_dpg_mode +ffffffff81f14000 t vcn_v4_0_early_init +ffffffff81f14120 t vcn_v4_0_sw_init +ffffffff81f14360 t vcn_v4_0_sw_fini +ffffffff81f14440 t vcn_v4_0_hw_init +ffffffff81f14e80 t vcn_v4_0_hw_fini +ffffffff81f14f90 t vcn_v4_0_suspend +ffffffff81f14fc0 t vcn_v4_0_resume +ffffffff81f15010 t vcn_v4_0_is_idle +ffffffff81f15110 t vcn_v4_0_wait_for_idle +ffffffff81f15240 t vcn_v4_0_set_clockgating_state +ffffffff81f15350 t vcn_v4_0_set_powergating_state +ffffffff81f17900 t vcn_v4_0_unified_ring_get_rptr +ffffffff81f179e0 t vcn_v4_0_unified_ring_get_wptr +ffffffff81f17ad0 t vcn_v4_0_unified_ring_set_wptr +ffffffff81f17bd0 t vcn_v4_0_ring_patch_cs_in_place +ffffffff81f17e50 t vcn_v4_0_set_interrupt_state +ffffffff81f17e80 t vcn_v4_0_process_interrupt +ffffffff81f17f40 t vcn_v4_0_pause_dpg_mode +ffffffff81f18300 t vcn_v4_0_enable_clock_gating +ffffffff81f185f0 t vcn_v4_0_disable_clock_gating +ffffffff81f18b40 t vcn_v4_0_start_dpg_mode +ffffffff81f1d1d0 t vcn_v4_0_disable_clock_gating_dpg_mode +ffffffff81f1e000 t vega10_ih_early_init +ffffffff81f1e050 t vega10_ih_sw_init +ffffffff81f1e300 t vega10_ih_sw_fini +ffffffff81f1e340 t vega10_ih_hw_init +ffffffff81f1e6d0 t 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vega20_ih_set_clockgating_state +ffffffff81f20cc0 t vega20_ih_set_powergating_state +ffffffff81f20cf0 t vega20_ih_get_wptr +ffffffff81f20e00 t vega20_ih_set_rptr +ffffffff81f20ed0 t vega20_ih_self_irq +ffffffff81f20f50 t vega20_ih_toggle_interrupts +ffffffff81f22000 T vega20_reg_base_init +ffffffff81f22160 T vega20_doorbell_index_init +ffffffff81f23000 T vi_srbm_select +ffffffff81f23050 T vi_set_virt_ops +ffffffff81f23090 T vi_set_ip_blocks +ffffffff81f234d0 T legacy_doorbell_index_init +ffffffff81f23580 t vi_common_early_init +ffffffff81f23870 t vi_common_late_init +ffffffff81f238b0 t vi_common_sw_init +ffffffff81f238f0 t vi_common_sw_fini +ffffffff81f23920 t vi_common_hw_init +ffffffff81f23ff0 t vi_common_hw_fini +ffffffff81f24070 t vi_common_suspend +ffffffff81f240f0 t vi_common_resume +ffffffff81f24130 t vi_common_is_idle +ffffffff81f24160 t vi_common_wait_for_idle +ffffffff81f24190 t vi_common_soft_reset +ffffffff81f241c0 t vi_common_set_clockgating_state +ffffffff81f24720 t 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dm_helpers_dp_mst_poll_pending_down_reply +ffffffff81f37570 T dm_helpers_dp_mst_clear_payload_allocation_table +ffffffff81f375a0 T dm_helpers_dp_mst_poll_for_allocation_change_trigger +ffffffff81f37610 T dm_helpers_dp_mst_send_payload_allocation +ffffffff81f376e0 T dm_dtn_log_begin +ffffffff81f37730 T dm_dtn_log_append_v +ffffffff81f37880 T dm_dtn_log_end +ffffffff81f378d0 T dm_helpers_dp_mst_start_top_mgr +ffffffff81f37970 T dm_helpers_dp_mst_stop_top_mgr +ffffffff81f37a10 T dm_helpers_dp_read_dpcd +ffffffff81f37a90 T dm_helpers_dp_write_dpcd +ffffffff81f37b10 T dm_helpers_submit_i2c +ffffffff81f37c30 T dm_helpers_dp_write_dsc_enable +ffffffff81f381b0 T dm_helpers_is_dp_sink_present +ffffffff81f38240 T dm_helpers_read_local_edid +ffffffff81f383e0 T dm_helper_dmub_aux_transfer_sync +ffffffff81f38400 T dm_helpers_dmub_set_config_sync +ffffffff81f38420 T dm_set_dcn_clocks +ffffffff81f38450 T dm_helpers_smu_timeout +ffffffff81f38480 T dm_helpers_init_panel_settings +ffffffff81f384f0 T dm_helpers_override_panel_settings +ffffffff81f38530 T dm_helpers_allocate_gpu_mem +ffffffff81f38620 T dm_helpers_free_gpu_mem +ffffffff81f386d0 T dm_helpers_dmub_outbox_interrupt_control +ffffffff81f38760 T dm_helpers_mst_enable_stream_features +ffffffff81f38870 T dm_set_phyd32clk +ffffffff81f388a0 T dm_helpers_enable_periodic_detection +ffffffff81f388d0 t execute_synaptics_rc_command +ffffffff81f39000 T amdgpu_dm_irq_register_interrupt +ffffffff81f391a0 t dm_irq_work_func +ffffffff81f391c0 T amdgpu_dm_irq_unregister_interrupt +ffffffff81f393e0 T amdgpu_dm_irq_init +ffffffff81f394d0 T amdgpu_dm_irq_fini +ffffffff81f39670 T amdgpu_dm_irq_suspend +ffffffff81f39780 T amdgpu_dm_irq_resume_early +ffffffff81f39940 T amdgpu_dm_irq_resume_late +ffffffff81f39b00 T amdgpu_dm_set_irq_funcs +ffffffff81f39bc0 T amdgpu_dm_outbox_init +ffffffff81f39bf0 T amdgpu_dm_hpd_init +ffffffff81f39cb0 T amdgpu_dm_hpd_fini +ffffffff81f39d70 t amdgpu_dm_set_crtc_irq_state +ffffffff81f39df0 t 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dal_bios_parser_create +ffffffff81f56070 T dal_bios_parser_destroy +ffffffff81f57000 T dal_bios_parser_init_cmd_tbl +ffffffff81f57800 t encoder_control_digx_v3 +ffffffff81f57900 t encoder_control_digx_v4 +ffffffff81f57a00 t encoder_control_digx_v5 +ffffffff81f57b50 t encoder_control_dig1_v1 +ffffffff81f57bd0 t encoder_control_dig2_v1 +ffffffff81f57c50 t encoder_control_dig_v1 +ffffffff81f57cb0 t transmitter_control_v2 +ffffffff81f57e50 t transmitter_control_v3 +ffffffff81f58010 t transmitter_control_v4 +ffffffff81f581c0 t transmitter_control_v1_5 +ffffffff81f58340 t transmitter_control_v1_6 +ffffffff81f584b0 t set_pixel_clock_v3 +ffffffff81f58620 t set_pixel_clock_v5 +ffffffff81f587c0 t set_pixel_clock_v6 +ffffffff81f58970 t set_pixel_clock_v7 +ffffffff81f58b40 t enable_spread_spectrum_on_ppll_v1 +ffffffff81f58c60 t enable_spread_spectrum_on_ppll_v2 +ffffffff81f58d90 t enable_spread_spectrum_on_ppll_v3 +ffffffff81f58ea0 t adjust_display_pll_v2 +ffffffff81f58ff0 t adjust_display_pll_v3 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dal_hw_gpio_config_mode -ffffffff822251a0 T dal_hw_gpio_get_value -ffffffff82225200 T dal_hw_gpio_set_value -ffffffff82225290 T dal_hw_gpio_change_mode -ffffffff822252a0 T dal_hw_gpio_close -ffffffff82225350 T dal_hw_gpio_construct -ffffffff822253b0 T dal_hw_gpio_destruct -ffffffff82226000 T dal_hw_hpd_init -ffffffff82226100 T dal_hw_hpd_get_pin -ffffffff82226110 t dal_hw_hpd_destroy -ffffffff82226170 t get_value -ffffffff82226210 t set_config -ffffffff82227000 T dal_hw_translate_init -ffffffff82228000 T dc_process_hdcp_msg -ffffffff82228180 t hdmi_14_process_transaction -ffffffff822282e0 t dp_11_process_transaction -ffffffff82229000 T dal_irq_service_dummy_set -ffffffff82229050 T dal_irq_service_dummy_ack -ffffffff822290a0 T dce110_vblank_set -ffffffff82229170 T to_dal_irq_source_dce110 -ffffffff822292f0 T dal_irq_service_dce110_create -ffffffff82229370 t hpd_ack -ffffffff8222a000 T dal_irq_service_dce120_create -ffffffff8222a080 t hpd_ack -ffffffff8222b000 T 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dentist_get_divider_from_did +ffffffff81f63070 T dce_adjust_dp_ref_freq_for_ss +ffffffff81f63180 T dce_get_dp_ref_freq_khz +ffffffff81f632b0 T dce12_get_dp_ref_freq_khz +ffffffff81f632d0 T dce_get_max_pixel_clock_for_all_paths +ffffffff81f634e0 T dce_get_required_clocks_state +ffffffff81f63590 T dce_set_clock +ffffffff81f636f0 T dce_clock_read_ss_info +ffffffff81f63830 T dce_clk_mgr_construct +ffffffff81f63a20 t dce_update_clocks +ffffffff81f64000 T dce110_get_min_vblank_time_us +ffffffff81f64080 T dce110_fill_display_configs +ffffffff81f642e0 T dce11_pplib_apply_display_requirements +ffffffff81f645d0 T dce110_clk_mgr_construct +ffffffff81f64680 t dce11_update_clocks +ffffffff81f65000 T dce112_set_clock +ffffffff81f651a0 T dce112_set_dispclk +ffffffff81f652d0 T dce112_set_dprefclk +ffffffff81f65340 T dce112_clk_mgr_construct +ffffffff81f653f0 t dce112_update_clocks +ffffffff81f66000 T dce120_clk_mgr_construct +ffffffff81f66090 T dce121_clk_mgr_construct +ffffffff81f661c0 t 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dcn301_smu_set_display_idle_optimization +ffffffff81f73570 T dcn301_smu_enable_phy_refclk_pwrdwn +ffffffff81f735c0 T dcn301_smu_enable_pme_wa +ffffffff81f735e0 T dcn301_smu_set_dram_addr_high +ffffffff81f73630 T dcn301_smu_set_dram_addr_low +ffffffff81f73680 T dcn301_smu_transfer_dpm_table_smu_2_dram +ffffffff81f736a0 T dcn301_smu_transfer_wm_table_dram_2_smu +ffffffff81f74000 T vg_clk_mgr_construct +ffffffff81f747f0 T vg_clk_mgr_destroy +ffffffff81f74840 t vg_update_clocks +ffffffff81f74bd0 t vg_init_clocks +ffffffff81f74c70 t vg_enable_pme_wa +ffffffff81f74c80 t vg_are_clock_states_equal +ffffffff81f74cd0 t vg_notify_wm_ranges +ffffffff81f76000 T dcn31_update_clocks +ffffffff81f76620 T dcn31_init_clocks +ffffffff81f766d0 T dcn31_are_clock_states_equal +ffffffff81f76730 T dcn31_get_dtb_ref_freq_khz +ffffffff81f76760 T dcn31_clk_mgr_construct +ffffffff81f76dd0 T dcn31_clk_mgr_destroy +ffffffff81f76e20 t dcn31_set_low_power_state +ffffffff81f77000 t dcn31_enable_pme_wa +ffffffff81f77010 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T dcn315_clk_mgr_destroy +ffffffff81f7ca10 t dcn315_update_clocks +ffffffff81f7d000 t dcn315_enable_pme_wa +ffffffff81f7d010 t dcn315_notify_wm_ranges +ffffffff81f7e000 T dcn315_smu_get_smu_version +ffffffff81f7e020 t dcn315_smu_send_msg_with_param +ffffffff81f7e1b0 T dcn315_smu_set_dispclk +ffffffff81f7e220 T dcn315_smu_set_hard_min_dcfclk +ffffffff81f7e2a0 T dcn315_smu_set_min_deep_sleep_dcfclk +ffffffff81f7e320 T dcn315_smu_set_dppclk +ffffffff81f7e390 T dcn315_smu_set_display_idle_optimization +ffffffff81f7e3e0 T dcn315_smu_enable_phy_refclk_pwrdwn +ffffffff81f7e430 T dcn315_smu_enable_pme_wa +ffffffff81f7e470 T dcn315_smu_set_dram_addr_high +ffffffff81f7e4b0 T dcn315_smu_set_dram_addr_low +ffffffff81f7e4f0 T dcn315_smu_transfer_dpm_table_smu_2_dram +ffffffff81f7e530 T dcn315_smu_transfer_wm_table_dram_2_smu +ffffffff81f7e570 T dcn315_smu_get_dpref_clk +ffffffff81f7e5d0 T dcn315_smu_get_dtbclk +ffffffff81f7e630 T dcn315_smu_set_dtbclk +ffffffff81f7f000 T dcn316_clk_mgr_construct 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dcn316_smu_get_smu_fclk +ffffffff81f82000 T dcn32_init_clocks +ffffffff81f824e0 T dcn32_clk_mgr_construct +ffffffff81f827b0 t dcn32_dump_clk_registers +ffffffff81f829d0 T dcn32_clk_mgr_destroy +ffffffff81f82a40 t dcn32_update_clocks +ffffffff81f83190 t dcn32_enable_pme_wa +ffffffff81f831d0 t dcn32_are_clock_states_equal +ffffffff81f83240 t dcn32_notify_wm_ranges +ffffffff81f833c0 t dcn32_set_hard_min_memclk +ffffffff81f83460 t dcn32_set_hard_max_memclk +ffffffff81f834c0 t dcn32_get_memclk_states_from_smu +ffffffff81f836b0 t dcn32_is_smu_present +ffffffff81f84000 T dcn32_smu_send_fclk_pstate_message +ffffffff81f84020 t dcn32_smu_send_msg_with_param +ffffffff81f84160 T dcn32_smu_send_cab_for_uclk_message +ffffffff81f84190 T dcn32_smu_transfer_wm_table_dram_2_smu +ffffffff81f841b0 T dcn32_smu_set_pme_workaround +ffffffff81f841d0 T dcn32_smu_set_hard_min_by_freq +ffffffff81f85000 T dc_stream_adjust_vmin_vmax +ffffffff81f85180 T dc_stream_get_last_used_drr_vtotal +ffffffff81f852e0 T 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dc_process_dmub_set_config_async +ffffffff81f8ed10 T dc_process_dmub_set_mst_slots +ffffffff81f8ee00 T dc_process_dmub_dpia_hpd_int_enable +ffffffff81f8eed0 T dc_disable_accelerated_mode +ffffffff81f8eef0 T dc_notify_vsync_int_state +ffffffff81f8f120 T dc_extended_blank_supported +ffffffff81f90000 T pre_surface_trace +ffffffff81f90030 T update_surface_trace +ffffffff81f90060 T post_surface_trace +ffffffff81f90090 T context_timing_trace +ffffffff81f90240 T context_clock_trace +ffffffff81f90270 T dc_status_to_str +ffffffff81f91000 T find_color_matrix +ffffffff81f910b0 T color_space_to_black_color +ffffffff81f91140 T hwss_wait_for_blank_complete +ffffffff81f911f0 T get_mpctree_visual_confirm_color +ffffffff81f91250 T get_surface_visual_confirm_color +ffffffff81f91300 T get_hdr_visual_confirm_color +ffffffff81f913b0 T get_subvp_visual_confirm_color +ffffffff81f914a0 T get_surface_tile_visual_confirm_color +ffffffff81f92000 T get_hpd_gpio +ffffffff81f920e0 T dc_link_wait_for_t12 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dc_link_set_test_pattern +ffffffff81f9a430 T dc_link_bandwidth_kbps +ffffffff81f9a4d0 T dc_link_should_enable_fec +ffffffff81f9a5f0 T dc_link_get_link_cap +ffffffff81f9a640 T dc_link_overwrite_extended_receiver_cap +ffffffff81f9a650 T dc_link_is_fec_supported +ffffffff81f9a710 T dc_bandwidth_in_kbps_from_timing +ffffffff81f9a870 T dc_get_cur_link_res_map +ffffffff81f9a950 T dc_restore_link_res_map +ffffffff81f9aa80 t read_current_link_settings_on_detect +ffffffff81f9ac90 t enable_link_dp +ffffffff81f9b000 T dal_ddc_i2c_payloads_add +ffffffff81f9b0c0 T dal_ddc_service_create +ffffffff81f9b230 T dal_ddc_service_destroy +ffffffff81f9b2c0 T dal_ddc_service_get_type +ffffffff81f9b2f0 T dal_ddc_service_set_transaction_type +ffffffff81f9b320 T dal_ddc_service_is_in_aux_transaction_mode +ffffffff81f9b360 T ddc_service_set_dongle_type +ffffffff81f9b390 T get_defer_delay +ffffffff81f9b4c0 T dal_ddc_service_i2c_query_dp_dual_mode_adaptor +ffffffff81f9b8d0 T dal_ddc_service_query_ddc_data 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dp_get_panel_mode +ffffffff81fa2350 T dp_enable_link_phy +ffffffff81fa23e0 T dp_set_panel_mode +ffffffff81fa24f0 T dp_disable_link_phy +ffffffff81fa25c0 t decide_fallback_link_setting +ffffffff81fa2920 T dc_link_dp_sync_lt_begin +ffffffff81fa2a00 T dc_link_dp_sync_lt_attempt +ffffffff81fa2f30 t perform_clock_recovery_sequence +ffffffff81fa34f0 t perform_channel_equalization_sequence +ffffffff81fa3b70 T dc_link_dp_sync_lt_end +ffffffff81fa3c60 T dc_link_dp_get_max_link_enc_cap +ffffffff81fa3d50 T dp_get_max_link_cap +ffffffff81fa3f40 T dp_is_lttpr_present +ffffffff81fa3fb0 T hpd_rx_irq_check_link_loss_status +ffffffff81fa40b0 T dp_verify_link_cap_with_retries +ffffffff81fa47c0 T dp_validate_mode_timing +ffffffff81fa4880 T decide_edp_link_settings +ffffffff81fa49c0 T decide_link_settings +ffffffff81fa4e00 t decide_edp_link_settings_with_dsc +ffffffff81fa51a0 T dc_link_dp_allow_hpd_rx_irq +ffffffff81fa51e0 T is_dp_branch_device +ffffffff81fa5210 T dc_link_dp_handle_automated_test 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link_enc_cfg_get_link_using_link_enc +ffffffff81fb10f0 T link_enc_cfg_get_link_enc_used_by_link +ffffffff81fb1280 T link_enc_cfg_get_next_avail_link_enc +ffffffff81fb1400 T link_enc_cfg_get_link_enc_used_by_stream +ffffffff81fb1420 T link_enc_cfg_get_link_enc +ffffffff81fb14b0 T link_enc_cfg_get_link_enc_used_by_stream_current +ffffffff81fb15e0 T link_enc_cfg_is_link_enc_avail +ffffffff81fb17d0 T link_enc_cfg_set_transient_mode +ffffffff81fb2000 T resource_parse_asic_id +ffffffff81fb2290 T dc_create_resource_pool +ffffffff81fb2590 T dc_destroy_resource_pool +ffffffff81fb2600 T resource_construct +ffffffff81fb2b30 T resource_unreference_clock_source +ffffffff81fb2bb0 T resource_reference_clock_source +ffffffff81fb2c30 T resource_get_clock_source_reference +ffffffff81fb2cc0 T resource_are_vblanks_synchronizable +ffffffff81fb2ee0 T resource_are_streams_timing_synchronizable +ffffffff81fb2fc0 T resource_find_used_clk_src_for_sharing +ffffffff81fb30f0 T get_num_mpc_splits +ffffffff81fb3180 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dc_resource_is_dsc_encoding_supported +ffffffff81fb68a0 T dc_validate_global_state +ffffffff81fb6c20 T dc_resource_state_destruct +ffffffff81fb6d00 T dc_resource_find_first_free_pll +ffffffff81fb6d70 T resource_build_info_frame +ffffffff81fb7380 T resource_map_clock_resources +ffffffff81fb7510 T pipe_need_reprogram +ffffffff81fb7680 T resource_build_bit_depth_reduction_params +ffffffff81fb7870 T dc_validate_stream +ffffffff81fb7940 T dc_validate_plane +ffffffff81fb79d0 T resource_pixel_format_to_bpp +ffffffff81fb7a50 T get_audio_check +ffffffff81fb7b70 T get_temp_dp_link_res +ffffffff81fb7c70 T reset_syncd_pipes_from_disabled_pipes +ffffffff81fb7db0 T check_syncd_pipes_for_disabled_master_pipe +ffffffff81fb7ec0 T reset_sync_context_for_pipe +ffffffff81fb7f60 T resource_transmitter_to_phy_idx +ffffffff81fb7fc0 T get_link_hwss +ffffffff81fb8030 T is_h_timing_divisible_by_2 +ffffffff81fb8090 T dc_resource_acquire_secondary_pipe_for_mpc_odm +ffffffff81fb8290 t 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dc_dmub_srv_p_state_delegate +ffffffff81fbfed0 T dc_dmub_srv_query_caps_cmd +ffffffff81fbffc0 T dc_dmub_srv_get_visual_confirm_color_cmd +ffffffff81fc0190 T dc_dmub_setup_subvp_dmub_command +ffffffff81fc0af0 T dc_dmub_srv_get_diagnostic_data +ffffffff81fc0b30 T dc_send_update_cursor_info_to_dmu +ffffffff81fc1000 T dc_edid_parser_send_cea +ffffffff81fc10b0 T dc_edid_parser_recv_cea_ack +ffffffff81fc1140 T dc_edid_parser_recv_amd_vsdb +ffffffff81fc2000 T generic_reg_update_ex +ffffffff81fc2370 t set_reg_field_values +ffffffff81fc2530 T generic_reg_set_ex +ffffffff81fc2780 T generic_reg_get +ffffffff81fc27f0 T generic_reg_get2 +ffffffff81fc2880 T generic_reg_get3 +ffffffff81fc2920 T generic_reg_get4 +ffffffff81fc29d0 T generic_reg_get5 +ffffffff81fc2aa0 T generic_reg_get6 +ffffffff81fc2b80 T generic_reg_get7 +ffffffff81fc2c80 T generic_reg_get8 +ffffffff81fc2d90 T generic_reg_wait +ffffffff81fc3000 T generic_write_indirect_reg +ffffffff81fc3050 T generic_read_indirect_reg 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dce112_i2c_hw_construct +ffffffff81fd2010 T dcn1_i2c_hw_construct +ffffffff81fd2080 T dcn2_i2c_hw_construct +ffffffff81fd2110 t is_hw_busy +ffffffff81fd3000 T dce_i2c_sw_construct +ffffffff81fd3030 T dce_i2c_engine_acquire_sw +ffffffff81fd30d0 T dce_i2c_submit_command_sw +ffffffff81fd38d0 t write_byte_sw +ffffffff81fd4000 T dce_ipp_construct +ffffffff81fd4050 T dce_ipp_destroy +ffffffff81fd40a0 t dce_ipp_cursor_set_position +ffffffff81fd41d0 t dce_ipp_cursor_set_attributes +ffffffff81fd4460 t dce_ipp_program_prescale +ffffffff81fd4620 t dce_ipp_program_input_lut +ffffffff81fd4ab0 t dce_ipp_set_degamma +ffffffff81fd5000 T dce110_get_dig_frontend +ffffffff81fd50c0 T dce110_link_encoder_set_dp_phy_pattern_training_pattern +ffffffff81fd5160 T dce110_psr_program_dp_dphy_fast_training +ffffffff81fd51d0 T dce110_psr_program_secondary_packet +ffffffff81fd5240 T dce110_is_dig_enabled +ffffffff81fd52a0 T dce110_link_encoder_validate_dvi_output +ffffffff81fd5350 T dce110_link_encoder_validate_dp_output +ffffffff81fd5380 T dce110_link_encoder_construct +ffffffff81fd5550 T dce110_link_encoder_validate_output_with_stream +ffffffff81fd5700 T dce110_link_encoder_hw_init +ffffffff81fd5920 T dce110_link_encoder_destroy +ffffffff81fd5970 T dce110_link_encoder_setup +ffffffff81fd5aa0 T dce110_link_encoder_enable_tmds_output +ffffffff81fd5b90 T dce110_link_encoder_enable_lvds_output +ffffffff81fd5c80 T dce110_link_encoder_enable_dp_output +ffffffff81fd5e00 T dce110_link_encoder_enable_dp_mst_output +ffffffff81fd5f80 T dce110_link_encoder_disable_output +ffffffff81fd61a0 T dce110_link_encoder_dp_set_lane_settings +ffffffff81fd6340 T dce110_link_encoder_dp_set_phy_pattern +ffffffff81fd6b40 t set_dp_phy_pattern_hbr2_compliance_cp2520_2 +ffffffff81fd6d50 T dce110_link_encoder_update_mst_stream_allocation_table +ffffffff81fd6fd0 T dce110_link_encoder_connect_dig_be_to_fe +ffffffff81fd7100 T dce110_link_encoder_enable_hpd +ffffffff81fd7130 T dce110_link_encoder_disable_hpd +ffffffff81fd7160 T dce110_link_encoder_get_max_link_cap +ffffffff81fd8000 T dce_mem_input_construct +ffffffff81fd8060 T dce112_mem_input_construct +ffffffff81fd80c0 T dce120_mem_input_construct +ffffffff81fd8120 t dce_mi_program_display_marks +ffffffff81fd83f0 t dce_mi_allocate_dmif +ffffffff81fd8630 t dce_mi_free_dmif +ffffffff81fd8790 t dce_mi_program_surface_flip_and_addr +ffffffff81fd8ab0 t dce_mi_program_pte_vm +ffffffff81fd8c70 t dce_mi_program_surface_config +ffffffff81fd94f0 t dce_mi_is_flip_pending +ffffffff81fd9580 t program_nbp_watermark +ffffffff81fd9780 t dce112_mi_program_display_marks +ffffffff81fd9c90 t dce120_mi_program_display_marks +ffffffff81fda150 t dce120_program_stutter_watermark +ffffffff81fdb000 T dce110_opp_set_clamping +ffffffff81fdb2b0 T dce110_opp_program_bit_depth_reduction +ffffffff81fdba80 T dce110_opp_program_clamping_and_pixel_encoding +ffffffff81fdbc20 T dce110_opp_set_dyn_expansion +ffffffff81fdbd70 T dce110_opp_program_fmt +ffffffff81fdbef0 T dce110_opp_construct +ffffffff81fdbf50 T dce110_opp_destroy +ffffffff81fdc000 T dce_panel_cntl_construct +ffffffff81fdc060 t dce_panel_cntl_destroy +ffffffff81fdc0b0 t dce_panel_cntl_hw_init +ffffffff81fdc2f0 t dce_is_panel_backlight_on +ffffffff81fdc3a0 t dce_is_panel_powered_on +ffffffff81fdc450 t dce_store_backlight_level +ffffffff81fdc4f0 t dce_driver_set_backlight +ffffffff81fdc680 t dce_get_16_bit_backlight_from_pwm +ffffffff81fdd000 T get_filter_3tap_16p +ffffffff81fdd090 T get_filter_3tap_64p +ffffffff81fdd120 T get_filter_4tap_16p +ffffffff81fdd1b0 T get_filter_4tap_64p +ffffffff81fdd240 T get_filter_5tap_64p +ffffffff81fdd2d0 T get_filter_6tap_64p +ffffffff81fdd360 T get_filter_7tap_64p +ffffffff81fdd3f0 T get_filter_8tap_64p +ffffffff81fdd480 T get_filter_2tap_16p +ffffffff81fdd4b0 T get_filter_2tap_64p +ffffffff81fde000 T dce110_se_audio_mute_control +ffffffff81fde050 T dce110_se_dp_audio_setup +ffffffff81fde060 t dce110_se_audio_setup +ffffffff81fde1f0 T dce110_se_dp_audio_enable +ffffffff81fde430 T dce110_se_dp_audio_disable +ffffffff81fde590 T dce110_se_hdmi_audio_setup +ffffffff81fdeaa0 T dce110_se_hdmi_audio_disable +ffffffff81fdeb00 T dce110_stream_encoder_construct +ffffffff81fdeb50 t dce110_stream_encoder_dp_set_stream_attribute +ffffffff81fdf1a0 t dce110_stream_encoder_hdmi_set_stream_attribute +ffffffff81fdf6c0 t dce110_stream_encoder_dvi_set_stream_attribute +ffffffff81fdf7f0 t dce110_stream_encoder_lvds_set_stream_attribute +ffffffff81fdf8d0 t dce110_stream_encoder_set_throttled_vcp_size +ffffffff81fdfad0 t dce110_stream_encoder_update_hdmi_info_packets +ffffffff81fe01c0 t dce110_stream_encoder_stop_hdmi_info_packets +ffffffff81fe0460 t dce110_stream_encoder_update_dp_info_packets +ffffffff81fe05f0 t dce110_stream_encoder_stop_dp_info_packets +ffffffff81fe0760 t dce110_stream_encoder_dp_blank +ffffffff81fe08a0 t dce110_stream_encoder_dp_unblank +ffffffff81fe0a60 t setup_stereo_sync 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dmub_abm_destroy +ffffffff81fe5110 t dmub_abm_init +ffffffff81fe54f0 t dmub_abm_set_level +ffffffff81fe56b0 t dmub_abm_get_current_backlight +ffffffff81fe56e0 t dmub_abm_get_target_backlight +ffffffff81fe5710 t dmub_abm_init_config +ffffffff81fe5840 t dmub_abm_set_pause +ffffffff81fe6000 T dmub_hw_lock_mgr_cmd +ffffffff81fe60b0 T dmub_hw_lock_mgr_inbox0_cmd +ffffffff81fe60f0 T should_use_dmub_lock +ffffffff81fe7000 T dmub_enable_outbox_notification +ffffffff81fe8000 T dmub_psr_create +ffffffff81fe80a0 T dmub_psr_destroy +ffffffff81fe80f0 t dmub_psr_copy_settings +ffffffff81fe85a0 t dmub_psr_enable +ffffffff81fe8730 t dmub_psr_get_state +ffffffff81fe8a20 t dmub_psr_set_level +ffffffff81fe8b10 t dmub_psr_force_static +ffffffff81fe8bc0 t dmub_psr_get_residency +ffffffff81fe8c10 t dmub_psr_set_sink_vtotal_in_psr_active +ffffffff81fe8cd0 t dmub_psr_set_power_opt +ffffffff81fe9000 T dce100_enable_display_power_gating +ffffffff81fe90a0 T dce100_prepare_bandwidth +ffffffff81fe90f0 T dce100_optimize_bandwidth +ffffffff81fe9140 T dce100_hw_sequencer_construct +ffffffff81fea000 T dce100_add_stream_to_ctx +ffffffff81fea0a0 T dce100_validate_plane +ffffffff81fea0e0 T dce100_find_first_free_match_stream_enc_for_link +ffffffff81fea190 T dce100_create_resource_pool +ffffffff81feaf40 t dce100_resource_destruct +ffffffff81feb210 t dce100_destroy_resource_pool +ffffffff81feb270 t dce100_panel_cntl_create +ffffffff81feb300 t dce100_link_encoder_create +ffffffff81feb410 t dce100_validate_bandwidth +ffffffff81feb570 t dce100_validate_global +ffffffff81feb600 t read_dce_straps +ffffffff81feb660 t create_audio +ffffffff81feb690 t dce100_stream_encoder_create +ffffffff81feb730 t dce100_hwseq_create +ffffffff81fec000 T dce110_compressor_power_up_fbc +ffffffff81fec130 T dce110_compressor_enable_fbc +ffffffff81fec340 T dce110_compressor_is_fbc_enabled_in_hw +ffffffff81fec3f0 T dce110_compressor_disable_fbc +ffffffff81fec6d0 T dce110_compressor_program_compressed_surface_address_and_pitch +ffffffff81fec7f0 T dce110_compressor_set_fbc_invalidation_triggers +ffffffff81fec870 T dce110_compressor_create +ffffffff81fec920 T dce110_compressor_construct +ffffffff81fec9a0 T dce110_compressor_destroy +ffffffff81fec9f0 T get_max_support_fbc_buffersize +ffffffff81fed000 T dce110_update_info_frame +ffffffff81fed0d0 T dce110_enable_stream +ffffffff81fed1d0 T dce110_edp_wait_for_hpd_ready +ffffffff81fed410 T dce110_edp_power_control +ffffffff81fed8d0 T dce110_edp_wait_for_T12 +ffffffff81feda60 T dce110_edp_backlight_control +ffffffff81fedd90 T dce110_enable_audio_stream +ffffffff81fedea0 T dce110_disable_audio_stream +ffffffff81fee010 T dce110_disable_stream +ffffffff81fee150 T dce110_unblank_stream +ffffffff81fee250 T dce110_blank_stream +ffffffff81fee3a0 T dce110_set_avmute +ffffffff81fee3f0 T dce110_enable_accelerated_mode +ffffffff81fee7b0 t power_down_all_hw_blocks +ffffffff81fee970 T dce110_set_safe_displaymarks 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dce_mem_input_v_program_surface_flip_and_addr +ffffffff81ff33d0 t dce_mem_input_v_program_pte_vm +ffffffff81ff36b0 t dce_mem_input_v_program_surface_config +ffffffff81ff3a70 t dce_mem_input_v_is_surface_pending +ffffffff81ff3ae0 t program_urgency_watermark +ffffffff81ff3bf0 t program_nbp_watermark +ffffffff81ff3d60 t program_stutter_watermark +ffffffff81ff4000 T dce110_opp_v_set_csc_default +ffffffff81ff4310 t program_color_matrix_v +ffffffff81ff4480 t configure_graphics_mode_v +ffffffff81ff4570 T dce110_opp_v_set_csc_adjustment +ffffffff81ff5000 T dce110_opp_program_regamma_pwl_v +ffffffff81ff54b0 t power_on_lut +ffffffff81ff55d0 T dce110_opp_power_on_regamma_lut_v +ffffffff81ff5630 T dce110_opp_set_regamma_mode_v +ffffffff81ff6000 T dce110_opp_v_construct +ffffffff81ff7000 T dce110_resource_build_pipe_hw_param +ffffffff81ff7150 T dce110_find_first_free_match_stream_enc_for_link +ffffffff81ff71f0 T dce110_create_resource_pool +ffffffff81ff81b0 t dce110_resource_destruct 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dce110_timing_generator_get_vblank_counter +ffffffff81ff9600 T dce110_timing_generator_get_position +ffffffff81ff96a0 T dce110_timing_generator_get_crtc_scanoutpos +ffffffff81ff9790 T dce110_timing_generator_program_blanking +ffffffff81ff9a10 T dce110_timing_generator_set_test_pattern +ffffffff81ff9d00 T dce110_timing_generator_validate_timing +ffffffff81ff9de0 T dce110_timing_generator_wait_for_vblank +ffffffff81ff9f50 T dce110_timing_generator_is_counter_moving +ffffffff81ff9fd0 T dce110_timing_generator_wait_for_vactive +ffffffff81ffa0b0 T dce110_timing_generator_setup_global_swap_lock +ffffffff81ffa210 T dce110_timing_generator_tear_down_global_swap_lock +ffffffff81ffa290 T dce110_timing_generator_enable_advanced_request +ffffffff81ffa330 T dce110_timing_generator_set_lock_master +ffffffff81ffa390 T dce110_timing_generator_enable_reset_trigger +ffffffff81ffa470 T dce110_timing_generator_enable_crtc_reset +ffffffff81ffa660 T dce110_timing_generator_disable_reset_trigger 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dce112_compressor_create +ffffffff81ffefe0 T dce112_compressor_destroy +ffffffff82000000 T dce112_hw_sequencer_construct +ffffffff82000050 t dce112_enable_display_power_gating +ffffffff82001000 T dce112_validate_bandwidth +ffffffff820010c0 T resource_map_phy_clock_resources +ffffffff82001210 T dce112_add_stream_to_ctx +ffffffff820012b0 T dce112_create_resource_pool +ffffffff82002650 t dce112_resource_destruct +ffffffff82002920 t dce112_destroy_resource_pool +ffffffff82002980 t dce112_panel_cntl_create +ffffffff82002a10 t dce112_link_encoder_create +ffffffff82002b20 t dce112_validate_global +ffffffff82002bb0 t read_dce_straps +ffffffff82002c10 t create_audio +ffffffff82002c40 t dce112_stream_encoder_create +ffffffff82002ce0 t dce112_hwseq_create +ffffffff82003000 T dce121_xgmi_enabled +ffffffff82003060 T dce120_hw_sequencer_construct +ffffffff820030c0 t dce120_enable_display_power_gating +ffffffff820030f0 t dce120_update_dchub +ffffffff82004000 T dce120_create_resource_pool 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dce80_hw_sequencer_construct +ffffffff82009000 T dce80_create_resource_pool +ffffffff82009e40 T dce81_create_resource_pool +ffffffff8200ac70 T dce83_create_resource_pool +ffffffff8200b940 t dce80_resource_destruct +ffffffff8200bc10 t dce80_destroy_resource_pool +ffffffff8200bc70 t dce80_panel_cntl_create +ffffffff8200bd00 t dce80_link_encoder_create +ffffffff8200be10 t dce80_validate_bandwidth +ffffffff8200bf70 t dce80_validate_global +ffffffff8200c000 t read_dce_straps +ffffffff8200c060 t create_audio +ffffffff8200c090 t dce80_stream_encoder_create +ffffffff8200c130 t dce80_hwseq_create +ffffffff8200d000 T dce80_timing_generator_construct +ffffffff8200d090 t program_timing +ffffffff8200d170 t dce80_timing_generator_enable_advanced_request +ffffffff8200e000 T cm_helper_program_color_matrices +ffffffff8200e0c0 T cm_helper_program_xfer_func +ffffffff8200e460 T cm_helper_convert_to_custom_float +ffffffff8200e8b0 T cm_helper_translate_curve_to_hw_format +ffffffff8200f430 T cm_helper_translate_curve_to_degamma_hw_format +ffffffff82010000 T dpp_read_state +ffffffff82010260 T dpp1_get_optimal_number_of_taps +ffffffff82010400 T dpp_reset +ffffffff82010470 T dpp1_cnv_setup +ffffffff82010970 T dpp1_set_cursor_attributes +ffffffff82010aa0 T dpp1_set_cursor_position +ffffffff82010bd0 T dpp1_cnv_set_optional_cursor_attributes +ffffffff82010c90 T dpp1_dppclk_control +ffffffff82010d90 T dpp1_construct +ffffffff82010e10 t dpp1_cm_set_regamma_pwl +ffffffff82011000 T dpp1_cm_set_gamut_remap +ffffffff820111a0 T dpp1_cm_set_output_csc_default +ffffffff82011220 t dpp1_cm_program_color_matrix +ffffffff820113e0 T dpp1_cm_set_output_csc_adjustment +ffffffff820113f0 T dpp1_cm_power_on_regamma_lut +ffffffff82011470 T dpp1_cm_program_regamma_lut +ffffffff82011680 T dpp1_cm_configure_regamma_lut +ffffffff82011780 T dpp1_cm_program_regamma_luta_settings +ffffffff82011910 T dpp1_cm_program_regamma_lutb_settings +ffffffff82011aa0 T dpp1_program_input_csc +ffffffff82011cf0 T dpp1_program_bias_and_scale +ffffffff82011e60 T dpp1_program_degamma_lutb_settings +ffffffff82012010 T dpp1_program_degamma_luta_settings +ffffffff820121c0 T dpp1_power_on_degamma_lut +ffffffff82012240 T dpp1_set_degamma +ffffffff82012430 T dpp1_degamma_ram_select +ffffffff82012490 T dpp1_program_degamma_lut +ffffffff820127b0 T dpp1_set_degamma_pwl +ffffffff82012980 T dpp1_full_bypass +ffffffff82012b20 T dpp1_program_input_lut +ffffffff820131f0 T dpp1_set_hdr_multiplier +ffffffff82014000 T dpp1_dscl_calc_lb_num_partitions +ffffffff820141e0 T dpp1_dscl_is_lb_conf_valid +ffffffff82014220 T dpp1_dscl_set_scaler_manual_scale +ffffffff820155e0 t dpp1_dscl_get_filter_coeffs_64p +ffffffff820156b0 t dpp1_dscl_set_scaler_filter +ffffffff82016000 T hubbub1_wm_read_state +ffffffff82016380 T hubbub1_allow_self_refresh_control +ffffffff82016400 T hubbub1_is_allow_self_refresh_enabled +ffffffff82016470 T hubbub1_verify_allow_pstate_change_high +ffffffff82016630 T hubbub1_wm_change_req_wa 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hubp1_program_requestor +ffffffff82019a60 T hubp1_program_deadline +ffffffff8201a160 T hubp1_is_flip_pending +ffffffff8201a270 T min_set_viewport +ffffffff8201a560 T hubp1_read_state_common +ffffffff8201b200 T hubp1_read_state +ffffffff8201b4d0 T hubp1_get_cursor_pitch +ffffffff8201b570 T hubp1_cursor_set_attributes +ffffffff8201b820 T hubp1_cursor_set_position +ffffffff8201bb80 T hubp1_clk_cntl +ffffffff8201bbd0 T hubp1_vtg_sel +ffffffff8201bc10 T hubp1_in_blank +ffffffff8201bc80 T hubp1_soft_reset +ffffffff8201bcc0 T hubp1_set_flip_int +ffffffff8201bd10 T hubp1_init +ffffffff8201bd40 T dcn10_hubp_construct +ffffffff8201bdb0 t hubp1_setup +ffffffff8201be70 t hubp1_setup_interdependent +ffffffff8201c1e0 t hubp1_set_vm_system_aperture_settings +ffffffff8201c400 t hubp1_set_vm_context0_settings +ffffffff8201c6e0 t hubp1_set_hubp_blank_en +ffffffff8201c720 t hubp1_disconnect +ffffffff8201c7b0 t hubp1_disable_control +ffffffff8201c7f0 t hubp1_get_underflow_status +ffffffff8201c860 t hubp1_wait_pipe_read_start +ffffffff8201d000 T dcn10_lock_all_pipes +ffffffff8201d100 T dcn10_log_hw_state +ffffffff8201ed10 T dcn10_did_underflow_occur +ffffffff8201edb0 T dcn10_enable_power_gating_plane +ffffffff8201ef50 T dcn10_disable_vga +ffffffff8201f140 T dcn10_dpp_pg_control +ffffffff8201f390 T dcn10_hubp_pg_control +ffffffff8201f5e0 T dcn10_bios_golden_init +ffffffff8201f740 T dcn10_enable_stream_timing +ffffffff8201fb30 T dcn10_verify_allow_pstate_change_high +ffffffff8201fe90 T dcn10_plane_atomic_disconnect +ffffffff8201ffc0 T dcn10_plane_atomic_power_down +ffffffff82020120 T dcn10_plane_atomic_disable +ffffffff82020280 T dcn10_disable_plane +ffffffff82020440 T dcn10_init_pipes +ffffffff82020b40 T dcn10_init_hw +ffffffff82021130 T dcn10_power_down_on_boot +ffffffff820212d0 T dcn10_reset_hw_ctx_wrap +ffffffff820215f0 T dcn10_update_plane_addr +ffffffff82021710 T dcn10_set_input_transfer_func +ffffffff82021880 T dcn10_set_output_transfer_func +ffffffff82021940 T dcn10_pipe_control_lock +ffffffff82021a10 T dcn10_cursor_lock +ffffffff82021bd0 T dcn10_enable_vblanks_synchronization +ffffffff82022350 T dcn10_enable_timing_synchronization +ffffffff82022710 T dcn10_enable_per_frame_crtc_position_reset +ffffffff820228f0 T dcn10_program_gamut_remap +ffffffff82022af0 T dcn10_program_output_csc +ffffffff82022c20 T dcn10_update_visual_confirm_color +ffffffff82022d20 T dcn10_update_mpcc +ffffffff82022fa0 T dcn10_blank_pixel_data +ffffffff820230e0 T dcn10_set_hdr_multiplier +ffffffff82023170 T dcn10_program_pipe +ffffffff82023d40 T dcn10_wait_for_pending_cleared +ffffffff82023e40 T dcn10_post_unlock_program_front_end +ffffffff820240f0 T dcn10_prepare_bandwidth +ffffffff820242a0 T dcn10_optimize_bandwidth +ffffffff82024450 T dcn10_set_drr +ffffffff82024550 T dcn10_get_position +ffffffff820245e0 T dcn10_set_static_screen_control +ffffffff82024680 T dcn10_setup_stereo +ffffffff820247e0 T dcn10_wait_for_mpcc_disconnect +ffffffff82024990 T dcn10_dummy_display_power_gating +ffffffff820249c0 T dcn10_update_pending_status +ffffffff82024b00 T dcn10_update_dchub +ffffffff82024b30 T dcn10_set_cursor_position +ffffffff82025070 T dcn10_set_cursor_attribute +ffffffff820250c0 T dcn10_set_cursor_sdr_white_level +ffffffff82025190 T dcn10_get_vupdate_offset_from_vsync +ffffffff82025220 T dcn10_calc_vupdate_position +ffffffff820252b0 T dcn10_setup_periodic_interrupt +ffffffff820253c0 T dcn10_setup_vupdate_interrupt +ffffffff82025480 T dcn10_unblank_stream +ffffffff82025590 T dcn10_send_immediate_sdp_message +ffffffff820255f0 T dcn10_set_clock +ffffffff82025700 T dcn10_get_clock +ffffffff82025760 T dcn10_get_dcc_en_bits +ffffffff82026000 T snprintf_count +ffffffff82026090 T dcn10_clear_status_bits +ffffffff82026240 T dcn10_get_hw_state +ffffffff82028000 T dcn10_hw_sequencer_construct +ffffffff82029000 T dcn10_ipp_construct +ffffffff82029050 T dcn20_ipp_construct +ffffffff820290a0 t dcn10_ipp_destroy +ffffffff8202a000 T dcn10_link_encoder_set_dp_phy_pattern_training_pattern +ffffffff8202a0b0 T dcn10_get_dig_frontend +ffffffff8202a170 T enc1_configure_encoder +ffffffff8202a1f0 T dcn10_psr_program_dp_dphy_fast_training +ffffffff8202a270 T dcn10_psr_program_secondary_packet +ffffffff8202a2f0 T dcn10_is_dig_enabled +ffffffff8202a350 T dcn10_link_encoder_validate_dvi_output +ffffffff8202a400 T dcn10_link_encoder_validate_dp_output +ffffffff8202a440 T dcn10_link_encoder_construct +ffffffff8202a630 T dcn10_link_encoder_validate_output_with_stream +ffffffff8202a820 T dcn10_link_encoder_hw_init +ffffffff8202aa20 T dcn10_aux_initialize +ffffffff8202aab0 T dcn10_link_encoder_destroy +ffffffff8202ab00 T dcn10_link_encoder_setup +ffffffff8202ac50 T dcn10_link_encoder_enable_tmds_output +ffffffff8202ad40 T dcn10_link_encoder_enable_tmds_output_with_clk_pattern_wa +ffffffff8202ae60 T dcn10_link_encoder_enable_dp_output +ffffffff8202afe0 T dcn10_link_encoder_enable_dp_mst_output +ffffffff8202b160 T dcn10_link_encoder_disable_output +ffffffff8202b340 T dcn10_link_encoder_dp_set_lane_settings +ffffffff8202b4e0 T dcn10_link_encoder_dp_set_phy_pattern +ffffffff8202bc00 t set_dp_phy_pattern_hbr2_compliance_cp2520_2 +ffffffff8202be00 T dcn10_link_encoder_update_mst_stream_allocation_table +ffffffff8202c0e0 T dcn10_link_encoder_connect_dig_be_to_fe +ffffffff8202c220 T dcn10_link_encoder_enable_hpd +ffffffff8202c260 T dcn10_link_encoder_disable_hpd +ffffffff8202c2a0 T dcn10_get_dig_mode +ffffffff8202c310 T dcn10_link_encoder_get_max_link_cap +ffffffff8202c390 t program_pattern_symbols +ffffffff8202d000 T mpc1_set_bg_color +ffffffff8202d1e0 T mpc1_get_mpcc +ffffffff8202d270 T mpc1_update_stereo_mix +ffffffff8202d3a0 T mpc1_assert_idle_mpcc +ffffffff8202d470 T mpc1_get_mpcc_for_dpp +ffffffff8202d520 T mpc1_is_mpcc_idle +ffffffff8202d610 T mpc1_assert_mpcc_idle_before_connect +ffffffff8202d750 T mpc1_insert_plane +ffffffff8202dca0 T mpc1_remove_mpcc +ffffffff8202e060 T mpc1_mpc_init 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optc1_set_timing_double_buffer +ffffffff82030b80 T optc1_set_blank +ffffffff82030c60 T optc1_is_blanked +ffffffff82030ce0 T optc1_enable_optc_clock +ffffffff82030f00 T optc1_disable_crtc +ffffffff82030ff0 T optc1_program_blank_color +ffffffff820310a0 T optc1_validate_timing +ffffffff820311a0 T optc1_get_vblank_counter +ffffffff82031200 T optc1_lock +ffffffff820312f0 T optc1_unlock +ffffffff82031360 T optc1_get_position +ffffffff820313e0 T optc1_is_counter_moving +ffffffff82031460 T optc1_did_triggered_reset_occur +ffffffff82031500 T optc1_disable_reset_trigger +ffffffff820315c0 T optc1_enable_reset_trigger +ffffffff820316d0 T optc1_enable_crtc_reset +ffffffff82031830 T optc1_wait_for_state +ffffffff82031900 T optc1_set_early_control +ffffffff82031930 T optc1_set_static_screen_control +ffffffff820319d0 T optc1_set_drr +ffffffff82031c00 T optc1_set_vtotal_min_max +ffffffff82031ca0 T optc1_get_crtc_scanoutpos +ffffffff82031db0 T optc1_program_stereo +ffffffff82031fb0 T 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dpp20_program_shaper +ffffffff820410a0 T dpp20_program_3dlut +ffffffff820417a0 t dpp20_set3dlut_ram12 +ffffffff82041970 T dpp2_set_hdr_multiplier +ffffffff82042000 t dsc2_get_enc_caps +ffffffff82042080 t dsc2_read_state +ffffffff82042230 t dsc2_validate_stream +ffffffff82042290 t dsc2_set_config +ffffffff82043620 t dsc2_get_packed_pps +ffffffff820437c0 t dsc2_enable +ffffffff82043970 t dsc2_disable +ffffffff82043af0 t dsc2_disconnect +ffffffff82043b60 T dsc2_construct +ffffffff82043bb0 t dsc_prepare_config +ffffffff82044270 t dsc_log_pps +ffffffff82045000 T dwb2_config_dwb_cnv +ffffffff820451f0 T dwb2_disable +ffffffff82045300 T dwb2_is_enabled +ffffffff820453a0 T dwb2_set_stereo +ffffffff82045490 T dwb2_set_new_content +ffffffff82045500 T dwb2_set_scaler +ffffffff82045890 t dwb2_get_caps +ffffffff82045970 t dwb2_enable +ffffffff82045ad0 t dwb2_update +ffffffff82045c30 t dwb2_set_warmup +ffffffff82045da0 T dcn20_dwbc_construct +ffffffff82046000 T dwb_program_horz_scalar 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is_rgb_equal +ffffffff82083000 T dccg3_create +ffffffff820830b0 T dccg30_create +ffffffff82084000 T dcn30_link_encoder_validate_output_with_stream +ffffffff82084010 T dcn30_link_encoder_construct +ffffffff82084230 T enc3_hw_init +ffffffff82085000 T enc3_stream_encoder_update_hdmi_info_packets +ffffffff82085100 t enc3_update_hdmi_info_packet +ffffffff820854f0 T enc3_stream_encoder_stop_hdmi_info_packets +ffffffff82085ab0 T enc3_dp_set_dsc_pps_info_packet +ffffffff82085dd0 T enc3_stream_encoder_update_dp_info_packets +ffffffff82086010 T enc3_audio_mute_control +ffffffff82086080 T enc3_se_dp_audio_setup +ffffffff82086100 T enc3_se_dp_audio_enable +ffffffff820861f0 T enc3_se_hdmi_audio_setup +ffffffff82086500 T dcn30_dio_stream_encoder_construct +ffffffff82086570 t enc3_stream_encoder_hdmi_set_stream_attribute +ffffffff82086b60 t enc3_stream_encoder_dvi_set_stream_attribute +ffffffff82086d60 t enc3_read_state +ffffffff82086ef0 t enc3_dp_set_dsc_config +ffffffff82086fc0 t enc3_dp_set_odm_combine +ffffffff82087000 T dpp30_read_state +ffffffff82087050 T dpp3_program_post_csc +ffffffff82087230 T dpp3_set_pre_degam +ffffffff820872e0 T dpp3_cnv_setup +ffffffff82087ba0 T dpp3_set_cursor_attributes +ffffffff82087d20 T dpp3_get_optimal_number_of_taps +ffffffff82088790 T dpp3_construct +ffffffff820887f0 t dpp3_deferred_update +ffffffff82088bc0 t dpp3_program_blnd_lut +ffffffff82089630 t dpp3_program_shaper +ffffffff8208b680 t dpp3_program_3dlut +ffffffff8208be50 t dpp3_set3dlut_ram12 +ffffffff8208d000 T dpp3_program_cm_dealpha +ffffffff8208d0a0 T dpp3_program_cm_bias +ffffffff8208d190 T dpp3_program_gamcor_lut +ffffffff8208dbd0 t dpp3_power_on_gamcor_lut +ffffffff8208dd00 T dpp3_set_hdr_multiplier +ffffffff8208dd50 T dpp3_cm_set_gamut_remap +ffffffff8208e000 T dwb3_config_fc +ffffffff8208e1b0 T dwb3_set_stereo +ffffffff8208e270 T dwb3_enable +ffffffff8208e3a0 T dwb3_set_denorm +ffffffff8208e4c0 T dwb3_disable +ffffffff8208e570 T dwb3_update +ffffffff8208e6a0 T dwb3_is_enabled +ffffffff8208e740 T dwb3_set_new_content +ffffffff8208e780 t dwb3_get_caps +ffffffff8208e820 T dcn30_dwbc_construct +ffffffff8208e870 T dwb3_set_host_read_rate_control +ffffffff8208f000 T dwb3_ogam_set_input_transfer_func +ffffffff8208f9d0 T dwb3_set_gamut_remap +ffffffff8208fb30 t dwb3_program_gamut_remap +ffffffff8208fcc0 T dwb3_program_hdr_mult +ffffffff82090000 T hubbub3_init_dchub_sys_ctx +ffffffff820901e0 T hubbub3_program_watermarks +ffffffff820902f0 T hubbub3_dcc_support_swizzle +ffffffff820903c0 T hubbub3_get_dcc_compression_cap +ffffffff820905b0 T hubbub3_force_wm_propagate_to_pipes +ffffffff82090660 T hubbub3_force_pstate_change_control +ffffffff820906e0 T hubbub3_init_watermarks +ffffffff82090a20 T hubbub3_construct +ffffffff82091000 T hubp3_set_vm_system_aperture_settings +ffffffff82091130 T hubp3_program_surface_flip_and_addr +ffffffff82091b60 T hubp3_dcc_control +ffffffff82091c20 T hubp3_dcc_control_sienna_cichlid +ffffffff82091d30 T hubp3_dmdata_set_attributes +ffffffff82091f30 T hubp3_program_surface_config +ffffffff82092230 T hubp3_read_state +ffffffff820924a0 T hubp3_setup +ffffffff82092530 T hubp3_init +ffffffff82092560 T hubp3_construct +ffffffff82093000 T dcn30_set_blend_lut +ffffffff82093070 T dcn30_set_input_transfer_func +ffffffff820931d0 T dcn30_set_output_transfer_func +ffffffff820934f0 T dcn30_update_writeback +ffffffff82093580 t dcn30_set_writeback +ffffffff82093730 T dcn30_mmhubbub_warmup +ffffffff820939e0 T dcn30_enable_writeback +ffffffff82093ab0 T dcn30_disable_writeback +ffffffff82093b90 T dcn30_program_all_writeback_pipes_in_tree +ffffffff82093e80 T dcn30_init_hw +ffffffff82094770 T dcn30_set_avmute +ffffffff820947d0 T dcn30_update_info_frame +ffffffff820948a0 T dcn30_program_dmdata_engine +ffffffff82094940 T dcn30_apply_idle_power_optimizations +ffffffff82094ec0 T dcn30_does_plane_fit_in_mall +ffffffff82094f70 T dcn30_hardware_release +ffffffff82095080 T dcn30_set_disp_pattern_generator +ffffffff820950f0 T dcn30_prepare_bandwidth +ffffffff82096000 T dcn30_hw_sequencer_construct +ffffffff82097000 t mmhubbub3_warmup_mcif +ffffffff82097210 t mmhubbub3_config_mcif_buf +ffffffff820976c0 t mmhubbub3_config_mcif_arb +ffffffff82097b10 T dcn30_mmhubbub_construct +ffffffff82098000 T mpc3_is_dwb_idle +ffffffff82098070 T mpc3_set_dwb_mux +ffffffff820980f0 T mpc3_disable_dwb_mux +ffffffff82098170 T mpc3_set_out_rate_control +ffffffff82098280 T mpc3_get_ogam_current +ffffffff82098320 T mpc3_power_on_ogam_lut +ffffffff820983f0 T mpc3_set_output_gamma +ffffffff82098f90 T mpc3_set_denorm +ffffffff82099000 T mpc3_set_denorm_clamp +ffffffff82099150 T mpc3_program_shaper +ffffffff8209b3c0 t mpc3_power_on_shaper_3dlut +ffffffff8209b740 T mpc3_init_mpcc +ffffffff8209b7c0 T mpc3_set_gamut_remap +ffffffff8209ba10 T mpc3_program_3dlut +ffffffff8209c1a0 t mpc3_set3dlut_ram12 +ffffffff8209c380 T mpc3_set_output_csc +ffffffff8209c4f0 T mpc3_set_ocsc_default +ffffffff8209c660 T mpc3_set_rmu_mux +ffffffff8209c700 T mpc3_get_rmu_mux_status +ffffffff8209c7b0 T mpcc3_acquire_rmu +ffffffff8209c910 t mpcc3_release_rmu +ffffffff8209ca80 t mpc3_set_mpc_mem_lp_mode +ffffffff8209cc10 T dcn30_mpc_construct +ffffffff8209d000 T optc3_triplebuffer_lock +ffffffff8209d120 T optc3_lock_doublebuffer_enable +ffffffff8209d3b0 T optc3_lock_doublebuffer_disable +ffffffff8209d4c0 T optc3_lock +ffffffff8209d590 T optc3_set_out_mux +ffffffff8209d5d0 T optc3_program_blank_color +ffffffff8209d710 T optc3_set_drr_trigger_window +ffffffff8209d7a0 T optc3_set_vtotal_change_limit +ffffffff8209d810 T optc3_set_dsc_config +ffffffff8209d860 T optc3_set_odm_bypass +ffffffff8209d9e0 T optc3_wait_drr_doublebuffer_pending_clear +ffffffff8209da60 T optc3_set_vtotal_min_max +ffffffff8209da80 T optc3_tg_init +ffffffff8209dae0 T dcn30_timing_generator_init +ffffffff8209db50 t optc3_set_odm_combine +ffffffff8209e000 T dcn30_add_stream_to_ctx +ffffffff8209e020 T dcn30_populate_dml_pipes_from_context +ffffffff8209e110 T dcn30_populate_dml_writeback_from_context +ffffffff8209e170 T dcn30_calc_max_scaled_time +ffffffff8209e1d0 T dcn30_set_mcif_arb_params +ffffffff8209e340 T dcn30_acquire_post_bldn_3dlut +ffffffff8209e4c0 T dcn30_release_post_bldn_3dlut +ffffffff8209e570 T dcn30_internal_validate_bw +ffffffff8209f340 t dcn30_split_stream_for_mpc_or_odm +ffffffff8209f660 T dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch +ffffffff8209f780 T dcn30_setup_mclk_switch_using_fw_based_vblank_stretch +ffffffff8209f820 T dcn30_update_soc_for_wm_a +ffffffff8209f870 T dcn30_calculate_wm_and_dlg +ffffffff8209f8e0 T dcn30_validate_bandwidth +ffffffff8209fd20 T dcn30_update_bw_bounding_box +ffffffff820a0500 T dcn30_create_resource_pool +ffffffff820a1ad0 t dcn30_resource_destruct +ffffffff820a2040 t dcn30_destroy_resource_pool +ffffffff820a20a0 t dcn30_panel_cntl_create +ffffffff820a2130 t dcn30_link_encoder_create +ffffffff820a21f0 t dcn30_get_panel_config_defaults +ffffffff820a2260 t read_dce_straps +ffffffff820a2290 t dcn30_create_audio +ffffffff820a22c0 t dcn30_stream_encoder_create +ffffffff820a2440 t dcn30_hwseq_create +ffffffff820a3000 T vpg3_update_generic_info_packet +ffffffff820a39a0 T vpg3_construct +ffffffff820a4000 T dccg301_create +ffffffff820a5000 T dcn301_link_encoder_construct +ffffffff820a6000 T hubbub301_construct +ffffffff820a7000 T dcn301_hw_sequencer_construct +ffffffff820a8000 T dcn301_panel_cntl_construct +ffffffff820a8050 t dcn301_panel_cntl_destroy +ffffffff820a80a0 t dcn301_panel_cntl_hw_init +ffffffff820a82b0 t dcn301_is_panel_backlight_on +ffffffff820a8310 t dcn301_is_panel_powered_on +ffffffff820a83c0 t dcn301_store_backlight_level +ffffffff820a8460 t dcn301_get_16_bit_backlight_from_pwm +ffffffff820a9000 T dcn301_create_resource_pool +ffffffff820aa5a0 t dcn301_destruct +ffffffff820aaae0 t dcn301_destroy_resource_pool +ffffffff820aab40 t dcn301_panel_cntl_create +ffffffff820aabd0 t dcn301_link_encoder_create +ffffffff820aac90 t dcn301_calculate_wm_and_dlg +ffffffff820aad00 t read_dce_straps +ffffffff820aad30 t dcn301_create_audio +ffffffff820aad60 t dcn301_stream_encoder_create +ffffffff820aaee0 t dcn301_hwseq_create +ffffffff820ab000 T dcn302_dpp_pg_control +ffffffff820ab2a0 T dcn302_hubp_pg_control +ffffffff820ab550 T dcn302_dsc_pg_control +ffffffff820ac000 T dcn302_hw_sequencer_construct +ffffffff820ad000 T dcn302_update_bw_bounding_box +ffffffff820ad050 T dcn302_create_resource_pool +ffffffff820ae3e0 t dcn302_resource_destruct +ffffffff820ae8f0 t dcn302_destroy_resource_pool +ffffffff820ae940 t dcn302_panel_cntl_create +ffffffff820ae9d0 t dcn302_link_encoder_create +ffffffff820aea90 t dcn302_get_panel_config_defaults +ffffffff820aeb00 t read_dce_straps +ffffffff820aeb30 t dcn302_create_audio +ffffffff820aeb60 t dcn302_stream_encoder_create +ffffffff820aece0 t dcn302_hwseq_create +ffffffff820af000 T dcn303_dpp_pg_control +ffffffff820af030 T dcn303_hubp_pg_control +ffffffff820af060 T dcn303_dsc_pg_control +ffffffff820af090 T dcn303_enable_power_gating_plane +ffffffff820b0000 T dcn303_hw_sequencer_construct +ffffffff820b1000 T dcn303_update_bw_bounding_box +ffffffff820b1050 T dcn303_create_resource_pool +ffffffff820b2290 t dcn303_resource_destruct +ffffffff820b27b0 t dcn303_destroy_resource_pool +ffffffff820b2800 t dcn303_panel_cntl_create +ffffffff820b2890 t dcn303_link_encoder_create +ffffffff820b2950 t dcn303_get_panel_config_defaults +ffffffff820b29c0 t read_dce_straps +ffffffff820b29f0 t dcn303_create_audio +ffffffff820b2a20 t dcn303_stream_encoder_create +ffffffff820b2ba0 t dcn303_hwseq_create +ffffffff820b3000 T afmt31_powerdown +ffffffff820b3090 T afmt31_poweron +ffffffff820b3120 T afmt31_construct +ffffffff820b4000 T apg31_construct +ffffffff820b4050 t apg31_se_audio_setup +ffffffff820b4160 t apg31_audio_mute_control +ffffffff820b41a0 t apg31_enable +ffffffff820b42b0 t apg31_disable +ffffffff820b5000 T dccg31_update_dpp_dto +ffffffff820b5160 T dccg31_set_dpstreamclk +ffffffff820b52f0 t dccg31_disable_dpstreamclk +ffffffff820b5440 T dccg31_enable_symclk32_se +ffffffff820b5730 T dccg31_disable_symclk32_se +ffffffff820b5a00 T dccg31_enable_symclk32_le +ffffffff820b5bd0 T dccg31_disable_symclk32_le +ffffffff820b5d70 T dccg31_disable_dscclk +ffffffff820b5f30 T dccg31_enable_dscclk +ffffffff820b6100 T dccg31_set_physymclk +ffffffff820b6620 T dccg31_set_dtbclk_dto +ffffffff820b68d0 T dccg31_set_audio_dtbclk_dto +ffffffff820b69e0 T dccg31_get_dccg_ref_freq +ffffffff820b6a10 T dccg31_set_dispclk_change_mode +ffffffff820b6a60 T dccg31_init +ffffffff820b6fc0 T dccg31_otg_add_pixel +ffffffff820b7000 T dccg31_otg_drop_pixel +ffffffff820b7040 T dccg31_create +ffffffff820b8000 T dcn31_link_encoder_set_dio_phy_mux +ffffffff820b8390 T dcn31_link_encoder_construct +ffffffff820b8590 T dcn31_link_encoder_construct_minimal +ffffffff820b8610 T dcn31_link_encoder_enable_dp_output +ffffffff820b8850 T dcn31_link_encoder_enable_dp_mst_output +ffffffff820b8a90 T dcn31_link_encoder_disable_output +ffffffff820b8d20 T dcn31_link_encoder_is_in_alt_mode +ffffffff820b8e60 T dcn31_link_encoder_get_max_link_cap +ffffffff820b8fd0 t enc31_hw_init +ffffffff820ba000 T dcn31_hpo_dp_link_enc_enable +ffffffff820ba160 T dcn31_hpo_dp_link_enc_disable +ffffffff820ba1d0 T dcn31_hpo_dp_link_enc_set_link_test_pattern +ffffffff820bab00 T dcn31_hpo_dp_link_enc_update_stream_allocation_table +ffffffff820bad90 T dcn31_hpo_dp_link_enc_set_throttled_vcp_size +ffffffff820bb030 T dcn31_hpo_dp_link_enc_read_state +ffffffff820bb2e0 T dcn31_hpo_dp_link_enc_enable_dp_output +ffffffff820bb3e0 T dcn31_hpo_dp_link_enc_disable_output +ffffffff820bb520 T dcn31_hpo_dp_link_enc_set_ffe +ffffffff820bb610 T hpo_dp_link_encoder31_construct +ffffffff820bb670 t dcn31_hpo_dp_link_enc_is_in_alt_mode +ffffffff820bc000 T dcn31_hpo_dp_stream_encoder_construct +ffffffff820bc070 t dcn31_hpo_dp_stream_enc_enable_stream +ffffffff820bc1b0 t dcn31_hpo_dp_stream_enc_dp_unblank +ffffffff820bc460 t dcn31_hpo_dp_stream_enc_dp_blank +ffffffff820bc560 t dcn31_hpo_dp_stream_enc_disable +ffffffff820bc5d0 t dcn31_hpo_dp_stream_enc_set_stream_attribute +ffffffff820bce80 t dcn31_hpo_dp_stream_enc_update_dp_info_packets +ffffffff820bd040 t dcn31_hpo_dp_stream_enc_stop_dp_info_packets +ffffffff820bd1d0 t dcn31_hpo_dp_stream_enc_set_dsc_pps_info_packet +ffffffff820bd470 t dcn31_hpo_dp_stream_enc_map_stream_to_link +ffffffff820bd570 t dcn31_hpo_dp_stream_enc_mute_control +ffffffff820bd5e0 t dcn31_hpo_dp_stream_enc_audio_setup +ffffffff820bd690 t dcn31_hpo_dp_stream_enc_audio_enable +ffffffff820bd760 t dcn31_hpo_dp_stream_enc_audio_disable +ffffffff820bd910 t dcn31_hpo_dp_stream_enc_read_state +ffffffff820bdaa0 t dcn31_set_hblank_min_symbol_width +ffffffff820be000 T hubbub31_init_dchub_sys_ctx +ffffffff820be1f0 T hubbub31_construct +ffffffff820be290 t hubbub31_get_dcc_compression_cap +ffffffff820be480 t hubbub31_get_dchub_ref_freq +ffffffff820be560 t hubbub31_program_watermarks +ffffffff820bfe20 t hubbub31_verify_allow_pstate_change_high +ffffffff820bffe0 t dcn31_program_det_size +ffffffff820c01a0 t dcn31_program_compbuf_size +ffffffff820c0420 t dcn31_init_crb +ffffffff820c1000 T hubp31_set_unbounded_requesting +ffffffff820c1090 T hubp31_soft_reset +ffffffff820c10e0 T hubp31_construct +ffffffff820c1150 t hubp31_program_extended_blank +ffffffff820c2000 T dcn31_init_hw +ffffffff820c2960 T dcn31_dsc_pg_control +ffffffff820c2cb0 T dcn31_enable_power_gating_plane +ffffffff820c2f10 T dcn31_update_info_frame +ffffffff820c2fe0 T dcn31_z10_save_init +ffffffff820c30a0 T dcn31_z10_restore +ffffffff820c3180 T dcn31_hubp_pg_control +ffffffff820c34a0 T dcn31_init_sys_ctx +ffffffff820c3550 T dcn31_reset_hw_ctx_wrap +ffffffff820c38c0 T dcn31_setup_hpo_hw_control +ffffffff820c4000 T dcn31_hw_sequencer_construct +ffffffff820c5000 T optc31_immediate_disable_crtc +ffffffff820c5100 T optc31_set_drr +ffffffff820c5320 T optc3_init_odm +ffffffff820c5490 T dcn31_timing_generator_init +ffffffff820c5500 t optc31_enable_crtc +ffffffff820c5600 t optc31_disable_crtc +ffffffff820c56e0 t optc31_set_odm_combine +ffffffff820c6000 T dcn31_panel_cntl_construct +ffffffff820c6040 t dcn31_panel_cntl_destroy +ffffffff820c6090 t dcn31_panel_cntl_hw_init +ffffffff820c6180 t dcn31_is_panel_backlight_on +ffffffff820c6220 t dcn31_is_panel_powered_on +ffffffff820c62d0 t dcn31_store_backlight_level +ffffffff820c6390 t dcn31_get_16_bit_backlight_from_pwm +ffffffff820c7000 T dcn31_populate_dml_pipes_from_context +ffffffff820c7350 T dcn31_calculate_wm_and_dlg +ffffffff820c73c0 T dcn31_populate_dml_writeback_from_context +ffffffff820c7420 T dcn31_set_mcif_arb_params +ffffffff820c7480 T dcn31_validate_bandwidth +ffffffff820c7870 T dcn31_create_resource_pool +ffffffff820c8c10 t dcn31_resource_destruct +ffffffff820c9270 t dcn31_destroy_resource_pool +ffffffff820c92d0 t dcn31_panel_cntl_create +ffffffff820c9340 t dcn31_link_encoder_create +ffffffff820c9400 t dcn31_link_enc_create_minimal +ffffffff820c94a0 t dcn31_get_panel_config_defaults +ffffffff820c9520 t read_dce_straps +ffffffff820c9550 t dcn31_create_audio +ffffffff820c9580 t dcn31_stream_encoder_create +ffffffff820c9700 t dcn31_hpo_dp_stream_encoder_create +ffffffff820c98c0 t dcn31_hpo_dp_link_encoder_create +ffffffff820c9950 t dcn31_hwseq_create +ffffffff820ca000 T vpg31_powerdown +ffffffff820ca090 T vpg31_poweron +ffffffff820ca120 T vpg31_construct +ffffffff820cb000 T dccg314_create +ffffffff820cb0b0 t dccg314_set_dpstreamclk +ffffffff820cb480 t dccg314_set_dtbclk_dto +ffffffff820cb670 t dccg314_set_pixel_rate_div +ffffffff820cb9e0 t dccg314_set_valid_pixel_rate +ffffffff820cba50 t dccg314_dpp_root_clock_control +ffffffff820cc000 T dcn314_dio_stream_encoder_construct +ffffffff820cc070 t enc314_stream_encoder_hdmi_set_stream_attribute +ffffffff820cc660 t enc314_stream_encoder_dvi_set_stream_attribute +ffffffff820cc870 t enc314_stream_encoder_dp_blank +ffffffff820cc8c0 t enc314_stream_encoder_dp_unblank +ffffffff820ccc00 t enc314_read_state +ffffffff820ccd60 t enc314_dp_set_dsc_config +ffffffff820ccdb0 t enc314_dp_set_odm_combine +ffffffff820ccdf0 t enc314_set_dig_input_mode +ffffffff820cce40 t enc314_enable_fifo +ffffffff820ccee0 t enc314_disable_fifo +ffffffff820ccf30 t enc314_reset_fifo +ffffffff820ce000 T dcn314_update_odm +ffffffff820ce610 T dcn314_dsc_pg_control +ffffffff820ce9e0 T dcn314_enable_power_gating_plane +ffffffff820cec70 T dcn314_calculate_dccg_k1_k2_values +ffffffff820cee00 T dcn314_set_pixels_per_cycle +ffffffff820ceef0 T dcn314_dpp_root_clock_control +ffffffff820cef50 T dcn314_hubp_pg_control +ffffffff820d0000 T dcn314_hw_sequencer_construct +ffffffff820d1000 T dcn314_timing_generator_init +ffffffff820d1070 t optc314_enable_crtc +ffffffff820d1170 t optc314_disable_crtc +ffffffff820d1250 t optc314_phantom_crtc_post_enable +ffffffff820d1310 t optc314_set_odm_bypass +ffffffff820d1480 t optc314_set_odm_combine +ffffffff820d1780 t optc314_set_h_timing_div_manual_mode +ffffffff820d2000 T dcn314_validate_bandwidth +ffffffff820d24a0 T dcn314_create_resource_pool +ffffffff820d3770 t dcn314_resource_destruct +ffffffff820d3dd0 t dcn314_destroy_resource_pool +ffffffff820d3e30 t dcn31_panel_cntl_create +ffffffff820d3ea0 t dcn31_link_encoder_create +ffffffff820d3f60 t dcn31_link_enc_create_minimal +ffffffff820d4000 t dcn314_populate_dml_pipes_from_context +ffffffff820d4090 t dcn314_update_bw_bounding_box +ffffffff820d40e0 t dcn314_get_panel_config_defaults +ffffffff820d4160 t read_dce_straps +ffffffff820d4190 t dcn31_create_audio +ffffffff820d41c0 t dcn314_stream_encoder_create +ffffffff820d4340 t dcn31_hpo_dp_stream_encoder_create +ffffffff820d4500 t dcn31_hpo_dp_link_encoder_create +ffffffff820d4590 t dcn314_hwseq_create +ffffffff820d5000 T dcn315_create_resource_pool +ffffffff820d6270 t dcn315_resource_destruct +ffffffff820d68d0 t dcn315_destroy_resource_pool +ffffffff820d6930 t dcn31_panel_cntl_create +ffffffff820d69a0 t dcn31_link_encoder_create +ffffffff820d6a60 t dcn31_link_enc_create_minimal +ffffffff820d6b00 t dcn315_populate_dml_pipes_from_context +ffffffff820d6e50 t dcn315_get_panel_config_defaults +ffffffff820d6ed0 t read_dce_straps +ffffffff820d6f00 t dcn31_create_audio +ffffffff820d6f30 t dcn315_stream_encoder_create +ffffffff820d70b0 t dcn31_hpo_dp_stream_encoder_create +ffffffff820d7270 t dcn31_hpo_dp_link_encoder_create +ffffffff820d7300 t dcn31_hwseq_create +ffffffff820d8000 T dcn316_create_resource_pool +ffffffff820d92b0 t dcn316_resource_destruct +ffffffff820d9910 t dcn316_destroy_resource_pool +ffffffff820d9970 t dcn31_panel_cntl_create +ffffffff820d99e0 t dcn31_link_encoder_create +ffffffff820d9aa0 t dcn31_link_enc_create_minimal +ffffffff820d9b40 t dcn316_populate_dml_pipes_from_context +ffffffff820d9e70 t dcn316_get_panel_config_defaults +ffffffff820d9ef0 t read_dce_straps +ffffffff820d9f20 t dcn31_create_audio +ffffffff820d9f50 t dcn316_stream_encoder_create +ffffffff820da0d0 t dcn31_hpo_dp_stream_encoder_create +ffffffff820da290 t dcn31_hpo_dp_link_encoder_create +ffffffff820da320 t dcn31_hwseq_create +ffffffff820db000 T dccg32_create +ffffffff820db0b0 t dccg32_get_dccg_ref_freq +ffffffff820db0e0 t dccg32_otg_add_pixel +ffffffff820db120 t dccg32_otg_drop_pixel +ffffffff820db160 t dccg32_set_dpstreamclk +ffffffff820db530 t dccg32_set_dtbclk_dto +ffffffff820db730 t dccg32_set_pixel_rate_div +ffffffff820dbaa0 t dccg32_set_valid_pixel_rate +ffffffff820dc000 T enc32_hw_init +ffffffff820dc090 T dcn32_link_encoder_enable_dp_output +ffffffff820dc0e0 T dcn32_link_encoder_construct +ffffffff820dc2c0 t dcn32_link_encoder_is_in_alt_mode +ffffffff820dc340 t dcn32_link_encoder_get_max_link_cap +ffffffff820dd000 T dcn32_dio_stream_encoder_construct +ffffffff820dd070 t enc32_stream_encoder_hdmi_set_stream_attribute +ffffffff820dd5a0 t enc32_stream_encoder_dvi_set_stream_attribute +ffffffff820dd720 t enc32_stream_encoder_dp_unblank +ffffffff820ddbe0 t enc32_read_state +ffffffff820ddd40 t enc32_dp_set_dsc_config +ffffffff820ddd90 t enc32_dp_set_odm_combine +ffffffff820dddd0 t enc32_set_dig_input_mode +ffffffff820de000 T dpp32_construct +ffffffff820de060 t dscl32_calc_lb_num_partitions +ffffffff820df000 T hpo_dp_link_encoder32_construct +ffffffff820df060 t dcn32_hpo_dp_link_enc_is_in_alt_mode +ffffffff820e0000 T dcn32_program_det_size +ffffffff820e01a0 T hubbub32_program_urgent_watermarks +ffffffff820e0910 T hubbub32_program_stutter_watermarks +ffffffff820e0d60 T hubbub32_program_pstate_watermarks +ffffffff820e11f0 T hubbub32_program_usr_watermarks +ffffffff820e1440 T hubbub32_force_usr_retraining_allow +ffffffff820e14c0 T hubbub32_force_wm_propagate_to_pipes +ffffffff820e1560 T hubbub32_construct +ffffffff820e15e0 t hubbub32_wm_read_state +ffffffff820e1a60 t hubbub32_program_watermarks +ffffffff820e1b70 t hubbub32_init_watermarks +ffffffff820e1fb0 t dcn32_program_compbuf_size +ffffffff820e2230 t dcn32_init_crb +ffffffff820e3000 T hubp32_update_force_pstate_disallow +ffffffff820e3090 T hubp32_update_mall_sel +ffffffff820e3120 T hubp32_prepare_subvp_buffering +ffffffff820e31c0 T hubp32_phantom_hubp_post_enable +ffffffff820e32d0 T hubp32_cursor_set_attributes +ffffffff820e3590 T hubp32_construct +ffffffff820e4000 T dcn32_dsc_pg_control +ffffffff820e4310 T dcn32_enable_power_gating_plane +ffffffff820e44b0 T dcn32_hubp_pg_control +ffffffff820e4720 T dcn32_apply_idle_power_optimizations +ffffffff820e4990 t dcn32_calculate_cab_allocation +ffffffff820e4d40 T dcn32_commit_subvp_config +ffffffff820e4df0 T dcn32_subvp_pipe_control_lock +ffffffff820e4fc0 T dcn32_set_mcm_luts +ffffffff820e5150 T dcn32_set_input_transfer_func +ffffffff820e5290 T dcn32_set_output_transfer_func +ffffffff820e54a0 T dcn32_subvp_update_force_pstate +ffffffff820e5610 T dcn32_update_mall_sel +ffffffff820e5790 T dcn32_program_mall_pipe_config +ffffffff820e5870 T dcn32_init_hw +ffffffff820e6070 T dcn32_update_odm +ffffffff820e6680 T dcn32_calculate_dccg_k1_k2_values +ffffffff820e6880 T dcn32_is_dp_dig_pixel_rate_div_policy +ffffffff820e6910 T dcn32_set_pixels_per_cycle +ffffffff820e6a50 T dcn32_unblank_stream +ffffffff820e6c20 T dcn32_disable_link_output +ffffffff820e6eb0 T dcn32_update_phantom_vp_position +ffffffff820e6fd0 T dcn32_dsc_pg_status +ffffffff820e70b0 T dcn32_update_dsc_pg +ffffffff820e8000 T dcn32_hw_sequencer_init_functions +ffffffff820e9000 t mmhubbub32_warmup_mcif +ffffffff820e9210 t mmhubbub32_config_mcif_buf +ffffffff820e96c0 t mmhubbub32_config_mcif_arb +ffffffff820e9ad0 T dcn32_mmhubbub_construct +ffffffff820ea000 t mpc32_mpc_init +ffffffff820ea220 t mpc32_program_post1dlut +ffffffff820ead00 t mpc32_program_shaper +ffffffff820ecfb0 t mpc32_program_3dlut +ffffffff820ed8a0 T dcn32_mpc_construct +ffffffff820ed960 t mpc32_power_on_shaper_3dlut +ffffffff820edb90 t mpc32_set3dlut_ram12 +ffffffff820ee000 T dcn32_timing_generator_init +ffffffff820ee070 t optc32_enable_crtc +ffffffff820ee170 t optc32_disable_crtc +ffffffff820ee250 t optc32_phantom_crtc_post_enable +ffffffff820ee310 t optc32_set_drr +ffffffff820ee560 t optc32_set_odm_bypass +ffffffff820ee6d0 t optc32_set_odm_combine +ffffffff820ee9d0 t optc32_set_h_timing_div_manual_mode +ffffffff820ef000 T dcn32_panel_cntl_create +ffffffff820ef070 T dcn32_acquire_post_bldn_3dlut +ffffffff820ef160 T dcn32_release_post_bldn_3dlut +ffffffff820ef210 T dcn32_remove_phantom_pipes +ffffffff820ef380 T dcn32_add_phantom_pipes +ffffffff820ef7c0 T dcn32_validate_bandwidth +ffffffff820efc80 T dcn32_populate_dml_pipes_from_context +ffffffff820f0050 T dcn32_calculate_wm_and_dlg +ffffffff820f00c0 T dcn32_create_resource_pool +ffffffff820f0170 t dcn32_resource_construct +ffffffff820fc590 T dcn32_acquire_idle_pipe_for_head_pipe_in_layer +ffffffff820fc7d0 T dcn32_calc_num_avail_chans_for_mall +ffffffff820fc840 t dcn32_mpc_create +ffffffff82101200 t dcn32_resource_destruct +ffffffff82101870 t dcn32_destroy_resource_pool +ffffffff821018d0 t dcn32_link_encoder_create +ffffffff82102830 t dcn32_update_bw_bounding_box +ffffffff82102880 t read_dce_straps +ffffffff821028b0 t dcn32_create_audio +ffffffff82102bf0 t dcn32_stream_encoder_create +ffffffff82104a70 t dcn32_hpo_dp_stream_encoder_create +ffffffff82105750 t dcn32_hpo_dp_link_encoder_create +ffffffff82105bd0 t dcn32_hwseq_create +ffffffff82106070 t dcn32_vpg_create +ffffffff82107000 T dcn32_helper_calculate_num_ways_for_subvp +ffffffff821071e0 T dcn32_merge_pipes_for_subvp +ffffffff821073b0 T dcn32_all_pipes_have_stream_and_plane +ffffffff82107440 T dcn32_subvp_in_use +ffffffff821074d0 T dcn32_mpo_in_use +ffffffff82107540 T dcn32_any_surfaces_rotated +ffffffff821075d0 T dcn32_determine_det_override +ffffffff82107910 T dcn32_set_det_allocations +ffffffff82107a90 T dcn32_save_mall_state +ffffffff82107b40 T dcn32_restore_mall_state +ffffffff82108000 T dcn321_link_encoder_construct +ffffffff82109000 T dcn321_create_resource_pool +ffffffff821090b0 t dcn321_resource_construct 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display_pipe_configuration +ffffffff821329a0 T dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation +ffffffff82138000 T dcn_bw_mod +ffffffff82138060 T dcn_bw_min2 +ffffffff821380a0 T dcn_bw_max +ffffffff821380d0 T dcn_bw_max2 +ffffffff82138110 T dcn_bw_floor2 +ffffffff821381b0 T dcn_bw_floor +ffffffff821381e0 T dcn_bw_ceil +ffffffff82138220 T dcn_bw_ceil2 +ffffffff821382d0 T dcn_bw_max3 +ffffffff82138370 T dcn_bw_max5 +ffffffff821384e0 T dcn_bw_pow +ffffffff82138570 T dcn_bw_fabs +ffffffff821385d0 T dcn_bw_log +ffffffff82139000 T swizzle_mode_to_macro_tile_size +ffffffff82139090 T dcn_validate_bandwidth +ffffffff8213b330 T dcn_bw_sync_calcs_and_dml +ffffffff8213b580 t dcn_bw_calc_rq_dlg_ttu +ffffffff8213bf00 T dcn_find_dcfclk_suits_all +ffffffff8213c360 T dcn_bw_update_from_pplib_fclks +ffffffff8213c4f0 T dcn_bw_update_from_pplib_dcfclks +ffffffff8213c5c0 T dcn_get_soc_clks +ffffffff8213c640 T dcn_bw_notify_pplib_of_wm_ranges +ffffffff8213d000 T dcn20_populate_dml_writeback_from_context +ffffffff8213d180 T dcn20_fpu_set_wb_arb_params +ffffffff8213d330 T dcn20_calculate_dlg_params +ffffffff8213db40 T dcn20_populate_dml_pipes_from_context +ffffffff8213ea40 T dcn20_calculate_wm +ffffffff8213f1e0 T dcn20_update_bounding_box +ffffffff8213f460 T dcn20_cap_soc_clocks +ffffffff8213f7e0 T dcn20_patch_bounding_box +ffffffff8213f950 T dcn20_validate_bandwidth_fp +ffffffff8213fae0 t dcn20_validate_bandwidth_internal +ffffffff8213fec0 T dcn20_fpu_set_wm_ranges +ffffffff8213ff60 T dcn20_fpu_adjust_dppclk +ffffffff82140000 T dcn21_populate_dml_pipes_from_context +ffffffff82140100 T dcn21_validate_bandwidth_fp +ffffffff82140b80 T dcn21_update_bw_bounding_box +ffffffff82141060 T dcn21_clk_mgr_set_bw_params_wm_table +ffffffff821410c0 T dcn201_populate_dml_writeback_from_context_fpu +ffffffff821413d0 t calculate_wm_set_for_vlevel +ffffffff82142000 T dml20_recalculate +ffffffff82142740 t dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation +ffffffff82147da0 T dml20_ModeSupportAndSystemConfigurationFull +ffffffff8214ed30 t TruncToValidBPP +ffffffff8214ef10 t CalculateVMAndRowBytes +ffffffff8214f5a0 t CalculatePrefetchSourceLines +ffffffff8214f760 t CalculateWriteBackDelay +ffffffff8214fa30 t CalculatePrefetchSchedule +ffffffff821508f0 t CalculateFlipSchedule +ffffffff82150ca0 t adjust_ReturnBW +ffffffff82151000 T dml20v2_recalculate +ffffffff82151740 t dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation +ffffffff82156e50 T dml20v2_ModeSupportAndSystemConfigurationFull +ffffffff8215dcd0 t TruncToValidBPP +ffffffff8215e260 t CalculateVMAndRowBytes +ffffffff8215e8f0 t CalculatePrefetchSourceLines +ffffffff8215eab0 t CalculateWriteBackDelay +ffffffff8215ed80 t CalculateDelayAfterScaler +ffffffff8215f0d0 t CalculatePrefetchSchedule +ffffffff8215fe40 t CalculateFlipSchedule +ffffffff821601f0 t adjust_ReturnBW +ffffffff82161000 T dml20_rq_dlg_get_rq_reg +ffffffff82161490 t dml20_rq_dlg_get_rq_params +ffffffff82161660 T dml20_rq_dlg_get_dlg_reg +ffffffff821635b0 t get_surf_rq_param +ffffffff82163e30 t calculate_ttu_cursor +ffffffff82165000 T dml20v2_rq_dlg_get_rq_reg +ffffffff82165490 t dml20v2_rq_dlg_get_rq_params +ffffffff82165660 T dml20v2_rq_dlg_get_dlg_reg +ffffffff821675b0 t get_surf_rq_param +ffffffff82167e30 t calculate_ttu_cursor +ffffffff82169000 T dml21_recalculate +ffffffff82169700 t DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation +ffffffff8216f0b0 T dml21_ModeSupportAndSystemConfigurationFull +ffffffff82175190 t TruncToValidBPP +ffffffff82175720 t CalculateDCFCLKDeepSleep +ffffffff82175a60 t CalculateVMAndRowBytes +ffffffff821762d0 t CalculatePrefetchSourceLines +ffffffff82176490 t CalculateWriteBackDelay +ffffffff82176760 t CalculatePrefetchSchedulePerPlane +ffffffff82176f70 t CalculateUrgentBurstFactor +ffffffff82177380 t CalculateFlipSchedule +ffffffff82177870 t CalculateWatermarksAndDRAMSpeedChangeSupport +ffffffff821788d0 t CalculatePrefetchSchedule +ffffffff8217a000 T dml21_rq_dlg_get_rq_reg +ffffffff8217a490 t dml_rq_dlg_get_rq_params +ffffffff8217a660 T dml21_rq_dlg_get_dlg_reg +ffffffff8217c9c0 t get_surf_rq_param +ffffffff8217d300 t calculate_ttu_cursor +ffffffff8217e000 T optc3_fpu_set_vrr_m_const +ffffffff8217e4a0 T dcn30_fpu_populate_dml_writeback_from_context +ffffffff8217e7f0 T dcn30_fpu_set_mcif_arb_params +ffffffff8217e960 T dcn30_fpu_update_soc_for_wm_a +ffffffff8217ea30 T dcn30_fpu_calculate_wm_and_dlg +ffffffff8217f330 T dcn30_fpu_update_dram_channel_width_bytes +ffffffff8217f390 T dcn30_fpu_update_max_clk +ffffffff8217f440 T dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk +ffffffff8217f540 T dcn30_fpu_update_bw_bounding_box +ffffffff8217f720 T dcn30_find_dummy_latency_index_for_fw_based_mclk_switch +ffffffff8217f900 T dcn3_fpu_build_wm_range_table +ffffffff8217fbe0 T patch_dcn30_soc_bounding_box +ffffffff82180000 T dml30_recalculate +ffffffff82180600 t DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation +ffffffff82186c50 T dml30_CalculateBytePerPixelAnd256BBlockSizes +ffffffff82186ec0 T dml30_CalculateWriteBackDISPCLK +ffffffff82187040 T dml30_ModeSupportAndSystemConfigurationFull +ffffffff8218e440 t CalculateSwathAndDETConfiguration +ffffffff8218eab0 t TruncToValidBPP +ffffffff8218ed30 t dscceComputeDelay +ffffffff8218ee70 t CalculateVMAndRowBytes +ffffffff8218f520 t CalculatePrefetchSourceLines +ffffffff8218f6e0 t CalculateUrgentBurstFactor +ffffffff8218f970 t CalculateDCFCLKDeepSleep +ffffffff8218fc90 t UseMinimumDCFCLK +ffffffff82190e90 t CalculatePrefetchSchedule +ffffffff821923f0 t CalculateFlipSchedule +ffffffff821928e0 t CalculateWatermarksAndDRAMSpeedChangeSupport +ffffffff82193700 t CalculateSwathWidth +ffffffff82194000 T dml30_rq_dlg_get_rq_reg +ffffffff821944b0 t dml_rq_dlg_get_rq_params +ffffffff82194720 T dml30_rq_dlg_get_dlg_reg +ffffffff82196ed0 t get_surf_rq_param +ffffffff82197870 t calculate_ttu_cursor +ffffffff82198000 T dcn301_update_bw_bounding_box +ffffffff82198320 T dcn301_fpu_set_wm_ranges +ffffffff821983c0 T dcn301_fpu_init_soc_bounding_box +ffffffff82198460 T dcn301_calculate_wm_and_dlg_fp +ffffffff82198790 t calculate_wm_set_for_vlevel +ffffffff82199000 T dcn302_fpu_update_bw_bounding_box +ffffffff82199ac0 T dcn302_fpu_init_soc_bounding_box +ffffffff8219a000 T dcn303_fpu_update_bw_bounding_box +ffffffff8219ab00 T dcn303_fpu_init_soc_bounding_box +ffffffff8219b000 T dcn31_zero_pipe_dcc_fraction +ffffffff8219b060 T dcn31_update_soc_for_wm_a +ffffffff8219b110 T dcn315_update_soc_for_wm_a +ffffffff8219b1e0 T dcn31_calculate_wm_and_dlg_fp +ffffffff8219b6e0 T dcn31_update_bw_bounding_box +ffffffff8219bad0 T dcn315_update_bw_bounding_box +ffffffff8219bdc0 T dcn316_update_bw_bounding_box +ffffffff8219d000 T dml31_recalculate +ffffffff8219d2a0 t DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation +ffffffff821a4060 T dml31_CalculateWriteBackDISPCLK +ffffffff821a41e0 T dml31_ModeSupportAndSystemConfigurationFull +ffffffff821ac4a0 t CalculateSwathAndDETConfiguration +ffffffff821acaa0 t TruncToValidBPP +ffffffff821acd20 t dscceComputeDelay +ffffffff821ace60 t CalculateDCFCLKDeepSleep +ffffffff821ad1a0 t CalculateVMAndRowBytes +ffffffff821ad7f0 t CalculatePrefetchSourceLines +ffffffff821ad9b0 t CalculateUrgentBurstFactor +ffffffff821adc40 t CalculatePrefetchSchedulePerPlane +ffffffff821ae370 t CalculateFlipSchedule +ffffffff821ae8f0 t CalculateWatermarksAndDRAMSpeedChangeSupport +ffffffff821af550 t CalculateSwathWidth +ffffffff821afa60 t CalculatePrefetchSchedule +ffffffff821b0ef0 t CalculateVupdateAndDynamicMetadataParameters +ffffffff821b2000 T dml31_rq_dlg_get_rq_reg +ffffffff821b24b0 t dml_rq_dlg_get_rq_params +ffffffff821b2720 T dml31_rq_dlg_get_dlg_reg +ffffffff821b51f0 t get_surf_rq_param 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subvp_drr_schedulable +ffffffff821d7000 T dml32_recalculate +ffffffff821db330 T dml32_ModeSupportAndSystemConfigurationFull +ffffffff821e3000 T dml32_dscceComputeDelay +ffffffff821e3140 T dml32_dscComputeDelay +ffffffff821e3180 T IsVertical +ffffffff821e31b0 T dml32_CalculateSinglePipeDPPCLKAndSCLThroughput +ffffffff821e34d0 T dml32_CalculateBytePerPixelAndBlockSizes +ffffffff821e3800 T dml32_CalculateSwathAndDETConfiguration +ffffffff821e4020 T dml32_CalculateSwathWidth +ffffffff821e48c0 T dml32_UnboundedRequest +ffffffff821e4930 T dml32_CalculateDETBufferSize +ffffffff821e4f70 T dml32_CalculateODMMode +ffffffff821e56d0 T dml32_CalculateRequiredDispclk +ffffffff821e5890 T dml32_RoundToDFSGranularity +ffffffff821e5920 T dml32_CalculateOutputLink +ffffffff821e6450 T dml32_TruncToValidBPP +ffffffff821e67a0 T dml32_CalculateDPPCLK +ffffffff821e6950 T dml32_RequiredDTBCLK +ffffffff821e6ba0 T dml32_DSCDelayRequirement +ffffffff821e7070 T dml32_CalculateSurfaceSizeInMall +ffffffff821e7b80 T dml32_CalculateVMRowAndSwath +ffffffff821e89b0 T dml32_CalculateVMAndRowBytes +ffffffff821e95f0 T dml32_CalculatePrefetchSourceLines +ffffffff821e9840 T dml32_CalculateMALLUseForStaticScreen +ffffffff821e9990 T dml32_CalculateRowBandwidth +ffffffff821e9af0 T dml32_CalculateUrgentLatency +ffffffff821e9b90 T dml32_CalculateUrgentBurstFactor +ffffffff821e9e40 T dml32_CalculateDCFCLKDeepSleep +ffffffff821ea190 T dml32_CalculateWriteBackDelay +ffffffff821ea2f0 T dml32_UseMinimumDCFCLK +ffffffff821eb1b0 T dml32_CalculateExtraLatencyBytes +ffffffff821eb380 T dml32_CalculateTWait +ffffffff821eb460 T dml32_CalculateVUpdateAndDynamicMetadataParameters +ffffffff821eb6c0 T dml32_get_return_bw_mbps +ffffffff821eb880 T dml32_get_return_bw_mbps_vm_only +ffffffff821eb960 T dml32_CalculateExtraLatency +ffffffff821ebb90 T dml32_CalculatePrefetchSchedule +ffffffff821ed140 T dml32_CalculateFlipSchedule +ffffffff821ed6c0 T dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport +ffffffff821ee820 T dml32_CalculateWriteBackDISPCLK +ffffffff821ee9e0 T dml32_CalculateMinAndMaxPrefetchMode +ffffffff821eea20 T dml32_CalculatePixelDeliveryTimes +ffffffff821eee90 T dml32_CalculateMetaAndPTETimes +ffffffff821ef5d0 T dml32_CalculateVMGroupAndRequestTimes +ffffffff821efac0 T dml32_CalculateDCCConfiguration +ffffffff821f00e0 T dml32_CalculateStutterEfficiency +ffffffff821f1030 T dml32_CalculateMaxDETAndMinCompressedBufferSize +ffffffff821f1120 T dml32_CalculateVActiveBandwithSupport +ffffffff821f12b0 T dml32_CalculatePrefetchBandwithSupport +ffffffff821f1550 T dml32_CalculateBandwidthAvailableForImmediateFlip +ffffffff821f16a0 T dml32_CalculateImmediateFlipBandwithSupport +ffffffff821f18f0 T dml32_CalculateDETSwathFillLatencyHiding +ffffffff821f2000 T dml32_rq_dlg_get_rq_reg +ffffffff821f26a0 T dml32_rq_dlg_get_dlg_reg +ffffffff821f5000 T dcn321_insert_entry_into_table_sorted +ffffffff821f5430 T dcn321_update_bw_bounding_box_fpu +ffffffff821f7000 T dml_init_instance +ffffffff821f7310 T dml_get_status_message +ffffffff821f7350 T dml_log_pipe_params +ffffffff821f7380 T dml_log_mode_support_params +ffffffff821f8000 T dml_get_voltage_level +ffffffff821f81f0 t fetch_socbb_params +ffffffff821f8700 t fetch_ip_params +ffffffff821f8ba0 t fetch_pipe_params +ffffffff821f9ca0 T PixelClockAdjustmentForProgressiveToInterlaceUnit +ffffffff821f9d20 T get_clk_dcf_deepsleep +ffffffff821f9e30 T get_wm_urgent +ffffffff821f9f40 T get_wm_memory_trip +ffffffff821fa050 T get_wm_writeback_urgent +ffffffff821fa160 T get_wm_stutter_exit +ffffffff821fa270 T get_wm_stutter_enter_exit +ffffffff821fa380 T get_wm_z8_stutter_exit +ffffffff821fa490 T get_wm_z8_stutter_enter_exit +ffffffff821fa5a0 T get_stutter_efficiency_z8 +ffffffff821fa6b0 T get_stutter_num_bursts_z8 +ffffffff821fa7c0 T get_wm_dram_clock_change +ffffffff821fa8d0 T get_wm_writeback_dram_clock_change +ffffffff821fa9e0 T get_stutter_efficiency +ffffffff821faaf0 T get_stutter_efficiency_no_vblank +ffffffff821fac00 T get_stutter_period +ffffffff821fad10 T get_urgent_latency +ffffffff821fae20 T get_urgent_extra_latency +ffffffff821faf30 T get_nonurgent_latency +ffffffff821fb040 T get_dram_clock_change_latency +ffffffff821fb150 T get_dispclk_calculated +ffffffff821fb260 T get_total_data_read_bw +ffffffff821fb370 T get_return_bw +ffffffff821fb480 T get_tcalc +ffffffff821fb590 T get_fraction_of_urgent_bandwidth +ffffffff821fb6a0 T get_fraction_of_urgent_bandwidth_imm_flip +ffffffff821fb7b0 T get_cstate_max_cap_mode +ffffffff821fb8d0 T get_comp_buffer_size_kbytes +ffffffff821fb9e0 T get_pixel_chunk_size_in_kbyte +ffffffff821fbb00 T get_alpha_pixel_chunk_size_in_kbyte +ffffffff821fbc20 T get_meta_chunk_size_in_kbyte +ffffffff821fbd40 T get_min_pixel_chunk_size_in_byte +ffffffff821fbe50 T get_min_meta_chunk_size_in_byte +ffffffff821fbf70 T get_fclk_watermark +ffffffff821fc080 T get_usr_retraining_watermark +ffffffff821fc190 T get_comp_buffer_reserved_space_kbytes +ffffffff821fc2b0 T get_comp_buffer_reserved_space_64bytes +ffffffff821fc3d0 T get_comp_buffer_reserved_space_zs +ffffffff821fc4f0 T get_unbounded_request_enabled +ffffffff821fc610 T get_dsc_delay +ffffffff821fc740 T get_dppclk_calculated +ffffffff821fc860 T get_dscclk_calculated +ffffffff821fc980 T get_min_ttu_vblank +ffffffff821fcaa0 T get_min_ttu_vblank_in_us +ffffffff821fcbc0 T get_vratio_prefetch_l +ffffffff821fcce0 T get_vratio_prefetch_c +ffffffff821fce00 T get_dst_x_after_scaler +ffffffff821fcf20 T get_dst_y_after_scaler +ffffffff821fd040 T get_dst_y_per_vm_vblank +ffffffff821fd160 T get_dst_y_per_row_vblank +ffffffff821fd280 T get_dst_y_prefetch +ffffffff821fd3a0 T get_dst_y_per_vm_flip +ffffffff821fd4c0 T get_dst_y_per_row_flip +ffffffff821fd5e0 T get_refcyc_per_vm_group_vblank +ffffffff821fd700 T get_refcyc_per_vm_group_flip +ffffffff821fd820 T get_refcyc_per_vm_req_vblank +ffffffff821fd940 T get_refcyc_per_vm_req_flip +ffffffff821fda60 T get_refcyc_per_vm_group_vblank_in_us +ffffffff821fdb80 T get_refcyc_per_vm_group_flip_in_us +ffffffff821fdca0 T get_refcyc_per_vm_req_vblank_in_us +ffffffff821fddc0 T get_refcyc_per_vm_req_flip_in_us +ffffffff821fdee0 T get_refcyc_per_vm_dmdata_in_us +ffffffff821fe000 T get_dmdata_dl_delta_in_us +ffffffff821fe120 T get_refcyc_per_line_delivery_l_in_us +ffffffff821fe240 T get_refcyc_per_line_delivery_c_in_us +ffffffff821fe360 T get_refcyc_per_line_delivery_pre_l_in_us +ffffffff821fe480 T get_refcyc_per_line_delivery_pre_c_in_us +ffffffff821fe5a0 T get_refcyc_per_req_delivery_l_in_us +ffffffff821fe6c0 T get_refcyc_per_req_delivery_c_in_us +ffffffff821fe7e0 T get_refcyc_per_req_delivery_pre_l_in_us +ffffffff821fe900 T get_refcyc_per_req_delivery_pre_c_in_us +ffffffff821fea20 T get_refcyc_per_cursor_req_delivery_in_us +ffffffff821feb40 T get_refcyc_per_cursor_req_delivery_pre_in_us +ffffffff821fec60 T get_refcyc_per_meta_chunk_nom_l_in_us +ffffffff821fed80 T get_refcyc_per_meta_chunk_nom_c_in_us +ffffffff821feea0 T get_refcyc_per_meta_chunk_vblank_l_in_us +ffffffff821fefc0 T get_refcyc_per_meta_chunk_vblank_c_in_us +ffffffff821ff0e0 T get_refcyc_per_meta_chunk_flip_l_in_us +ffffffff821ff200 T get_refcyc_per_meta_chunk_flip_c_in_us +ffffffff821ff320 T get_vstartup +ffffffff821ff450 T get_vupdate_offset +ffffffff821ff580 T get_vupdate_width +ffffffff821ff6a0 T get_vready_offset +ffffffff821ff7c0 T get_vready_at_or_after_vsync +ffffffff821ff8f0 T get_min_dst_y_next_start +ffffffff821ffa20 T get_dst_y_per_pte_row_nom_l +ffffffff821ffb40 T get_dst_y_per_pte_row_nom_c +ffffffff821ffc60 T get_dst_y_per_meta_row_nom_l +ffffffff821ffd80 T get_dst_y_per_meta_row_nom_c +ffffffff821ffea0 T get_refcyc_per_pte_group_nom_l_in_us +ffffffff821fffc0 T get_refcyc_per_pte_group_nom_c_in_us +ffffffff822000e0 T get_refcyc_per_pte_group_vblank_l_in_us +ffffffff82200200 T get_refcyc_per_pte_group_vblank_c_in_us +ffffffff82200320 T get_refcyc_per_pte_group_flip_l_in_us +ffffffff82200440 T get_refcyc_per_pte_group_flip_c_in_us +ffffffff82200560 T get_vstartup_calculated +ffffffff82200690 T get_dpte_row_height_linear_c +ffffffff822007c0 T get_swath_height_l +ffffffff822008f0 T get_swath_height_c +ffffffff82200a20 T get_det_stored_buffer_size_l_bytes +ffffffff82200b50 T get_det_stored_buffer_size_c_bytes +ffffffff82200c80 T get_dpte_group_size_in_bytes +ffffffff82200db0 T get_vm_group_size_in_bytes +ffffffff82200ee0 T get_dpte_row_height_linear_l +ffffffff82201010 T get_pte_buffer_mode +ffffffff82201140 T get_subviewport_lines_needed_in_mall +ffffffff82201270 T get_total_immediate_flip_bytes +ffffffff82201390 T get_total_immediate_flip_bw +ffffffff82201570 T get_total_prefetch_bw +ffffffff82201750 T get_total_surface_size_in_mall_bytes +ffffffff82201900 T get_det_buffer_size_kbytes +ffffffff82201a30 T get_is_phantom_pipe +ffffffff82201b60 T Calculate256BBlockSizes +ffffffff82201c50 T CalculateMinAndMaxPrefetchMode +ffffffff82201cd0 T ModeSupportAndSystemConfiguration +ffffffff82201ff0 T CalculateWriteBackDISPCLK +ffffffff82203000 T print__rq_params_st +ffffffff82203030 T print__data_rq_sizing_params_st +ffffffff82203060 T print__data_rq_dlg_params_st +ffffffff82203090 T print__data_rq_misc_params_st +ffffffff822030c0 T print__rq_dlg_params_st +ffffffff822030f0 T print__dlg_sys_params_st +ffffffff82203120 T print__data_rq_regs_st +ffffffff82203150 T print__rq_regs_st +ffffffff82203180 T print__dlg_regs_st +ffffffff822031b0 T print__ttu_regs_st +ffffffff82204000 T dml1_extract_rq_regs +ffffffff82204330 T dml1_rq_dlg_get_rq_params +ffffffff82204500 t get_surf_rq_param +ffffffff82205200 T dml1_rq_dlg_get_dlg_params +ffffffff82208000 T _do_calc_rc_params +ffffffff82209040 t get_qp_set +ffffffff8220a000 T dc_dsc_parse_dsc_dpcd +ffffffff8220a2a0 t dsc_throughput_from_dpcd +ffffffff8220a460 T dc_dsc_compute_bandwidth_range +ffffffff8220a640 t intersect_dsc_caps +ffffffff8220a800 t setup_dsc_config +ffffffff8220b1d0 T dc_dsc_compute_config +ffffffff8220b2d0 T dc_dsc_stream_bandwidth_in_kbps +ffffffff8220b430 T dc_dsc_stream_bandwidth_overhead_in_kbps +ffffffff8220b580 T dc_dsc_get_policy_for_timing +ffffffff8220b620 T dc_dsc_policy_set_max_target_bpp_limit +ffffffff8220b650 T dc_dsc_policy_set_enable_dsc_when_not_needed +ffffffff8220b680 T dc_dsc_policy_set_disable_dsc_stream_overhead +ffffffff8220c000 T calc_rc_params +ffffffff8220d000 T dscc_compute_dsc_parameters +ffffffff8220e000 T dal_hw_factory_dce110_init +ffffffff8220e060 t define_hpd_registers +ffffffff8220e0b0 t define_ddc_registers +ffffffff8220f000 T dal_hw_translate_dce110_init +ffffffff8220f030 t offset_to_id +ffffffff8220f390 t id_to_offset +ffffffff82210000 T dal_hw_factory_dce120_init +ffffffff82210060 t define_hpd_registers +ffffffff822100b0 t define_ddc_registers +ffffffff82211000 T dal_hw_translate_dce120_init +ffffffff82211030 t offset_to_id +ffffffff822113a0 t id_to_offset +ffffffff82212000 T dal_hw_factory_dce80_init +ffffffff82212060 t define_hpd_registers +ffffffff822120b0 t define_ddc_registers +ffffffff82213000 T dal_hw_translate_dce80_init +ffffffff82213030 t offset_to_id +ffffffff822137b0 t id_to_offset +ffffffff82214000 T dal_hw_factory_dcn10_init +ffffffff82214060 t define_hpd_registers +ffffffff822140b0 t define_ddc_registers +ffffffff82214150 t define_generic_registers +ffffffff82215000 T dal_hw_translate_dcn10_init +ffffffff82215030 t offset_to_id +ffffffff82215390 t id_to_offset +ffffffff82216000 T dal_hw_factory_dcn20_init +ffffffff82216060 t define_hpd_registers +ffffffff822160b0 t define_ddc_registers +ffffffff82216160 t define_generic_registers +ffffffff82217000 T dal_hw_translate_dcn20_init +ffffffff82217030 t offset_to_id +ffffffff822172b0 t id_to_offset +ffffffff82218000 T dal_hw_factory_dcn21_init +ffffffff82218060 t define_hpd_registers +ffffffff822180b0 t define_ddc_registers +ffffffff82218160 t define_generic_registers +ffffffff82219000 T dal_hw_translate_dcn21_init +ffffffff82219030 t offset_to_id +ffffffff822192b0 t id_to_offset +ffffffff8221a000 T dal_hw_factory_dcn30_init +ffffffff8221a060 t define_hpd_registers +ffffffff8221a0b0 t define_ddc_registers +ffffffff8221a160 t define_generic_registers +ffffffff8221b000 T dal_hw_translate_dcn30_init +ffffffff8221b030 t offset_to_id +ffffffff8221b2c0 t id_to_offset +ffffffff8221c000 T dal_hw_factory_dcn315_init +ffffffff8221c060 t define_hpd_registers +ffffffff8221c0b0 t define_ddc_registers +ffffffff8221c160 t define_generic_registers +ffffffff8221d000 T dal_hw_translate_dcn315_init +ffffffff8221d030 t offset_to_id +ffffffff8221d2b0 t id_to_offset +ffffffff8221e000 T dal_hw_factory_dcn32_init +ffffffff8221e060 t define_hpd_registers +ffffffff8221e0b0 t define_ddc_registers +ffffffff8221e160 t define_generic_registers +ffffffff8221f000 T dal_hw_translate_dcn32_init +ffffffff8221f030 t offset_to_id +ffffffff8221f290 t id_to_offset +ffffffff82220000 T dal_gpio_open +ffffffff822200c0 T dal_gpio_open_ex +ffffffff82220180 T dal_gpio_get_value +ffffffff82220200 T dal_gpio_set_value +ffffffff82220280 T dal_gpio_get_mode +ffffffff822202b0 T dal_gpio_lock_pin +ffffffff822202d0 T dal_gpio_unlock_pin +ffffffff822202f0 T dal_gpio_change_mode +ffffffff82220370 T dal_gpio_get_id +ffffffff822203a0 T dal_gpio_get_enum +ffffffff822203d0 T dal_gpio_set_config +ffffffff82220450 T dal_gpio_get_pin_info +ffffffff822204b0 T dal_gpio_get_sync_source +ffffffff82220540 T dal_gpio_get_output_state +ffffffff82220570 T dal_gpio_get_ddc +ffffffff822205a0 T dal_gpio_get_hpd +ffffffff822205d0 T dal_gpio_get_generic +ffffffff82220600 T dal_gpio_close +ffffffff82220650 T dal_gpio_create +ffffffff822207e0 T dal_gpio_destroy +ffffffff82221000 T dal_gpio_service_create +ffffffff82221260 T dal_gpio_service_create_irq +ffffffff82221320 T dal_gpio_create_irq +ffffffff822213a0 T dal_gpio_service_create_generic_mux +ffffffff82221440 T dal_gpio_destroy_generic_mux +ffffffff822214d0 T dal_gpio_get_generic_pin_info +ffffffff82221530 T dal_gpio_service_destroy +ffffffff82221660 T dal_mux_setup_config +ffffffff822216c0 T dal_gpio_service_lock +ffffffff82221740 T dal_gpio_service_unlock +ffffffff822217c0 T dal_gpio_service_open +ffffffff82221a00 T dal_gpio_service_close +ffffffff82221aa0 T dal_irq_get_source +ffffffff82221b10 T dal_irq_get_rx_source +ffffffff82221b60 T dal_irq_setup_hpd_filter +ffffffff82221bc0 T dal_gpio_destroy_irq +ffffffff82221c50 T dal_gpio_create_ddc +ffffffff82221dc0 T dal_gpio_destroy_ddc +ffffffff82221e90 T dal_ddc_close +ffffffff82221ee0 T dal_ddc_open +ffffffff82222040 T dal_ddc_change_mode +ffffffff822220e0 T dal_ddc_get_line +ffffffff82222100 T dal_ddc_set_config +ffffffff82223000 T dal_hw_ddc_init +ffffffff82223100 T dal_hw_ddc_get_pin +ffffffff82223110 t dal_hw_ddc_destroy +ffffffff82223170 t set_config +ffffffff82224000 T dal_hw_factory_init +ffffffff82225000 T dal_hw_generic_init +ffffffff82225100 T dal_hw_generic_get_pin +ffffffff82225110 t dal_hw_generic_destroy +ffffffff82225170 t set_config +ffffffff82226000 T dal_hw_gpio_open +ffffffff822260b0 T dal_hw_gpio_config_mode +ffffffff822261a0 T dal_hw_gpio_get_value +ffffffff82226200 T dal_hw_gpio_set_value +ffffffff82226290 T dal_hw_gpio_change_mode +ffffffff822262a0 T dal_hw_gpio_close +ffffffff82226350 T dal_hw_gpio_construct +ffffffff822263b0 T dal_hw_gpio_destruct +ffffffff82227000 T dal_hw_hpd_init +ffffffff82227100 T dal_hw_hpd_get_pin +ffffffff82227110 t dal_hw_hpd_destroy +ffffffff82227170 t get_value +ffffffff82227210 t set_config +ffffffff82228000 T dal_hw_translate_init +ffffffff82229000 T dc_process_hdcp_msg +ffffffff82229180 t hdmi_14_process_transaction +ffffffff822292e0 t dp_11_process_transaction +ffffffff8222a000 T dal_irq_service_dummy_set +ffffffff8222a050 T dal_irq_service_dummy_ack +ffffffff8222a0a0 T dce110_vblank_set +ffffffff8222a170 T to_dal_irq_source_dce110 +ffffffff8222a2f0 T dal_irq_service_dce110_create +ffffffff8222a370 t hpd_ack +ffffffff8222b000 T dal_irq_service_dce120_create ffffffff8222b080 t hpd_ack -ffffffff8222c000 T dal_irq_service_dcn10_create +ffffffff8222c000 T dal_irq_service_dce80_create ffffffff8222c080 t hpd_ack -ffffffff8222c130 t to_dal_irq_source_dcn10 -ffffffff8222d000 T dal_irq_service_dcn20_create +ffffffff8222d000 T dal_irq_service_dcn10_create ffffffff8222d080 t hpd_ack -ffffffff8222d130 t to_dal_irq_source_dcn20 -ffffffff8222e000 T dal_irq_service_dcn201_create +ffffffff8222d130 t to_dal_irq_source_dcn10 +ffffffff8222e000 T dal_irq_service_dcn20_create ffffffff8222e080 t hpd_ack -ffffffff8222e130 t to_dal_irq_source_dcn201 -ffffffff8222f000 T dal_irq_service_dcn21_create +ffffffff8222e130 t to_dal_irq_source_dcn20 +ffffffff8222f000 T dal_irq_service_dcn201_create ffffffff8222f080 t hpd_ack -ffffffff8222f130 t to_dal_irq_source_dcn21 -ffffffff82230000 T dal_irq_service_dcn30_create +ffffffff8222f130 t to_dal_irq_source_dcn201 +ffffffff82230000 T dal_irq_service_dcn21_create ffffffff82230080 t hpd_ack -ffffffff82230130 t to_dal_irq_source_dcn30 -ffffffff82231000 T dal_irq_service_dcn302_create +ffffffff82230130 t to_dal_irq_source_dcn21 +ffffffff82231000 T dal_irq_service_dcn30_create ffffffff82231080 t hpd_ack -ffffffff82231130 t to_dal_irq_source_dcn302 -ffffffff82232000 T dal_irq_service_dcn303_create +ffffffff82231130 t to_dal_irq_source_dcn30 +ffffffff82232000 T dal_irq_service_dcn302_create ffffffff82232080 t hpd_ack -ffffffff82232130 t to_dal_irq_source_dcn303 -ffffffff82233000 T dal_irq_service_dcn31_create +ffffffff82232130 t to_dal_irq_source_dcn302 +ffffffff82233000 T dal_irq_service_dcn303_create ffffffff82233080 t hpd_ack -ffffffff82233130 t to_dal_irq_source_dcn31 -ffffffff82234000 T dal_irq_service_dcn314_create +ffffffff82233130 t to_dal_irq_source_dcn303 +ffffffff82234000 T dal_irq_service_dcn31_create ffffffff82234080 t hpd_ack -ffffffff82234130 t to_dal_irq_source_dcn314 -ffffffff82235000 T dal_irq_service_dcn315_create +ffffffff82234130 t to_dal_irq_source_dcn31 +ffffffff82235000 T dal_irq_service_dcn314_create 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dc_dp_trace_set_is_logged_flag -ffffffff822382f0 T dc_dp_trace_is_logged -ffffffff82238330 T dp_trace_lt_result_update -ffffffff82238370 T dp_trace_set_lt_start_timestamp -ffffffff82238450 T dp_trace_set_lt_end_timestamp -ffffffff82238530 T dc_dp_trace_get_lt_end_timestamp -ffffffff82238570 T dc_dp_trace_get_lt_counts -ffffffff822385b0 T dc_dp_trace_get_link_loss_count -ffffffff822385e0 T dp_trace_set_edp_power_timestamp -ffffffff822386c0 T dp_trace_get_edp_poweron_timestamp -ffffffff822386f0 T dp_trace_get_edp_poweroff_timestamp -ffffffff82239000 T set_dio_throttled_vcp_size -ffffffff82239020 T setup_dio_stream_encoder -ffffffff822390e0 T reset_dio_stream_encoder -ffffffff822391a0 T setup_dio_stream_attribute -ffffffff82239320 T enable_dio_dp_link_output -ffffffff82239390 T disable_dio_link_output -ffffffff822393d0 T set_dio_dp_link_test_pattern -ffffffff82239410 T set_dio_dp_lane_settings -ffffffff82239450 T can_use_dio_link_hwss -ffffffff82239490 T get_dio_link_hwss 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bwfm_sdio_buscore_read -ffffffff82549700 T bwfm_sdio_buscore_write -ffffffff82549720 T bwfm_sdio_buscore_prepare -ffffffff82549860 T bwfm_sdio_buscore_activate -ffffffff825498e0 T bwfm_sdio_match -ffffffff825499b0 T bwfm_sdio_attach -ffffffff82549c70 T bwfm_sdio_detach -ffffffff82549cd0 T bwfm_sdio_task -ffffffff82549e30 T bwfm_sdio_write_1 -ffffffff82549e60 T bwfm_sdio_read_1 -ffffffff82549e90 T bwfm_sdio_write_4 -ffffffff82549f40 T bwfm_sdio_read_4 -ffffffff82549ff0 T bwfm_sdio_load_microcode -ffffffff8254a250 T bwfm_sdio_clkctl -ffffffff8254a380 T bwfm_sdio_dev_write -ffffffff8254a3d0 T bwfm_sdio_intr -ffffffff8254a410 T bwfm_sdio_ram_read_write -ffffffff8254a640 T bwfm_sdio_htclk -ffffffff8254a8a0 T bwfm_sdio_readshared -ffffffff8254a970 T bwfm_sdio_dev_read -ffffffff8254a9b0 T bwfm_sdio_rx_frames -ffffffff8254ad40 T bwfm_sdio_tx_frames -ffffffff8254ae20 T bwfm_sdio_backplane -ffffffff8254aed0 T bwfm_sdio_buf_read -ffffffff8254afb0 T bwfm_sdio_buf_write -ffffffff8254b060 T bwfm_sdio_frame_read_write -ffffffff8254b1e0 T bwfm_sdio_newbuf -ffffffff8254b260 T bwfm_sdio_tx_ok -ffffffff8254b2b0 T bwfm_sdio_tx_ctrlframe -ffffffff8254b3b0 T bwfm_sdio_tx_dataframe -ffffffff8254b500 T bwfm_sdio_rx_glom -ffffffff8254c000 T onewire_match -ffffffff8254c050 T onewire_attach -ffffffff8254c0f0 T onewire_detach -ffffffff8254c160 T onewire_activate -ffffffff8254c180 T onewire_scan -ffffffff8254c390 T onewire_createthread -ffffffff8254c400 T onewire_print -ffffffff8254c4d0 T onewirebus_print -ffffffff8254c520 T onewire_lock -ffffffff8254c540 T onewire_unlock -ffffffff8254c560 T onewire_reset -ffffffff8254c580 T onewire_bit -ffffffff8254c5a0 T onewire_read_byte -ffffffff8254c6e0 T onewire_write_byte -ffffffff8254c7c0 T onewire_read_block -ffffffff8254c860 T onewire_write_block -ffffffff8254c900 T onewire_triplet -ffffffff8254c9e0 T onewire_matchrom -ffffffff8254cb30 T onewire_search -ffffffff8254cec0 T onewire_thread -ffffffff8254d000 T onewire_crc -ffffffff8254d0e0 T onewire_crc16 -ffffffff8254d1c0 T onewire_famname -ffffffff8254d200 T onewire_matchbyfam -ffffffff8254e000 T owid_match -ffffffff8254e030 T owid_attach -ffffffff8254e100 T owid_detach -ffffffff8254e140 T owid_activate -ffffffff8254f000 T owsbm_match -ffffffff8254f030 T owsbm_attach -ffffffff8254f1d0 T owsbm_detach -ffffffff8254f240 T owsbm_activate -ffffffff8254f270 T owsbm_update -ffffffff82550000 T owtemp_match -ffffffff82550030 T owtemp_attach -ffffffff82550130 T owtemp_detach -ffffffff825501a0 T owtemp_activate -ffffffff825501d0 T owtemp_update -ffffffff82551000 T owctr_match -ffffffff82551030 T owctr_attach -ffffffff82551180 T owctr_detach -ffffffff825511f0 T owctr_activate -ffffffff82551220 T owctr_update -ffffffff82551250 T owctr_update_counter -ffffffff82552000 A __text_page_start -ffffffff82552000 T Xsyscall_meltdown -ffffffff8255200c T Xsyscall -ffffffff8255226e t Xsyscall_trampback -ffffffff82552280 T intr_user_exit -ffffffff825522c2 t intr_user_exit_post_ast -ffffffff825523ee t Xiretq_trampback -ffffffff825523fa T doreti_iret -ffffffff82553000 T alltraps -ffffffff82553138 T recall_trap -ffffffff82553150 T alltraps_kern -ffffffff82553153 T alltraps_kern_meltdown -ffffffff82554000 ? Xsyscall32 -ffffffff82554000 A __kutext_start -ffffffff82554000 A __text_page_end -ffffffff82555000 ? Xtrap00 -ffffffff82555010 ? Xtrap01 -ffffffff82555020 ? Xtrap02 -ffffffff82555028 c calltrap_specstk -ffffffff825550f0 ? calltrap_specstk_tramp -ffffffff82555110 ? Xtrap03 -ffffffff82555120 ? Xtrap04 -ffffffff82555130 ? Xtrap05 -ffffffff82555140 ? Xtrap06 -ffffffff82555150 ? Xtrap07 -ffffffff82555160 ? Xtrap08 -ffffffff82555170 ? Xtrap09 -ffffffff82555180 ? Xtrap0a -ffffffff82555190 ? Xtrap0b -ffffffff825551a0 ? Xtrap0c -ffffffff825551b0 ? Xtrap0d -ffffffff82555240 ? Xtrap0e -ffffffff82555250 ? Xintrspurious -ffffffff82555250 ? Xtrap0f -ffffffff82555260 ? Xtrap10 -ffffffff82555270 ? Xtrap11 -ffffffff82555280 ? Xtrap12 -ffffffff82555290 ? Xtrap13 -ffffffff825552a0 ? Xtrap14 -ffffffff825552b0 ? Xtrap15 -ffffffff825552c0 ? Xtrap16 -ffffffff825552c0 ? Xtrap17 -ffffffff825552c0 ? Xtrap18 -ffffffff825552c0 ? Xtrap19 -ffffffff825552c0 ? Xtrap1a -ffffffff825552c0 ? Xtrap1b -ffffffff825552c0 ? Xtrap1c -ffffffff825552c0 ? Xtrap1d -ffffffff825552c0 ? Xtrap1e -ffffffff825552c0 ? Xtrap1f -ffffffff825552d0 ? x2apic_eoi -ffffffff825552f0 ? Xintr_lapic_ipi -ffffffff82555330 ? Xipi_invltlb -ffffffff82555360 ? Xipi_invlpg -ffffffff82555390 ? Xipi_invlrange -ffffffff825553d0 ? Xipi_invltlb_pcid -ffffffff82555410 ? Xipi_invlpg_pcid -ffffffff82555460 ? Xipi_invlrange_pcid -ffffffff825554d0 ? Xintr_lapic_ltimer -ffffffff82555510 ? Xintr_xen_upcall -ffffffff82555550 ? Xintr_hyperv_upcall -ffffffff82555590 ? Xintr_legacy0 -ffffffff825555d0 ? Xintr_legacy1 -ffffffff82555610 ? Xintr_legacy2 -ffffffff82555650 ? Xintr_legacy3 -ffffffff82555690 ? Xintr_legacy4 -ffffffff825556d0 ? Xintr_legacy5 -ffffffff82555710 ? Xintr_legacy6 -ffffffff82555750 ? Xintr_legacy7 -ffffffff82555790 ? Xintr_legacy8 -ffffffff825557d0 ? Xintr_legacy9 -ffffffff82555810 ? Xintr_legacy10 -ffffffff82555850 ? Xintr_legacy11 -ffffffff82555890 ? Xintr_legacy12 -ffffffff825558d0 ? Xintr_legacy13 -ffffffff82555910 ? Xintr_legacy14 -ffffffff82555950 ? Xintr_legacy15 -ffffffff82555990 ? Xintr_ioapic_edge0 -ffffffff825559d0 ? Xintr_ioapic_edge1 -ffffffff82555a10 ? Xintr_ioapic_edge2 -ffffffff82555a50 ? Xintr_ioapic_edge3 -ffffffff82555a90 ? Xintr_ioapic_edge4 -ffffffff82555ad0 ? Xintr_ioapic_edge5 -ffffffff82555b10 ? Xintr_ioapic_edge6 -ffffffff82555b50 ? Xintr_ioapic_edge7 -ffffffff82555b90 ? Xintr_ioapic_edge8 -ffffffff82555bd0 ? Xintr_ioapic_edge9 -ffffffff82555c10 ? Xintr_ioapic_edge10 -ffffffff82555c50 ? Xintr_ioapic_edge11 -ffffffff82555c90 ? Xintr_ioapic_edge12 -ffffffff82555cd0 ? Xintr_ioapic_edge13 -ffffffff82555d10 ? Xintr_ioapic_edge14 -ffffffff82555d50 ? Xintr_ioapic_edge15 -ffffffff82555d90 ? Xintr_ioapic_edge16 -ffffffff82555dd0 ? Xintr_ioapic_edge17 -ffffffff82555e10 ? Xintr_ioapic_edge18 -ffffffff82555e50 ? Xintr_ioapic_edge19 -ffffffff82555e90 ? Xintr_ioapic_edge20 -ffffffff82555ed0 ? Xintr_ioapic_edge21 -ffffffff82555f10 ? Xintr_ioapic_edge22 -ffffffff82555f50 ? Xintr_ioapic_edge23 -ffffffff82555f90 ? Xintr_ioapic_edge24 -ffffffff82555fd0 ? Xintr_ioapic_edge25 -ffffffff82556010 ? Xintr_ioapic_edge26 -ffffffff82556050 ? Xintr_ioapic_edge27 -ffffffff82556090 ? Xintr_ioapic_edge28 -ffffffff825560d0 ? Xintr_ioapic_edge29 -ffffffff82556110 ? Xintr_ioapic_edge30 -ffffffff82556150 ? Xintr_ioapic_edge31 -ffffffff82556190 ? Xintr_ioapic_edge32 -ffffffff825561d0 ? Xintr_ioapic_edge33 -ffffffff82556210 ? Xintr_ioapic_edge34 -ffffffff82556250 ? Xintr_ioapic_edge35 -ffffffff82556290 ? Xintr_ioapic_edge36 -ffffffff825562d0 ? Xintr_ioapic_edge37 -ffffffff82556310 ? Xintr_ioapic_edge38 -ffffffff82556350 ? Xintr_ioapic_edge39 -ffffffff82556390 ? Xintr_ioapic_edge40 -ffffffff825563d0 ? Xintr_ioapic_edge41 -ffffffff82556410 ? Xintr_ioapic_edge42 -ffffffff82556450 ? Xintr_ioapic_edge43 -ffffffff82556490 ? Xintr_ioapic_edge44 -ffffffff825564d0 ? Xintr_ioapic_edge45 -ffffffff82556510 ? Xintr_ioapic_edge46 -ffffffff82556550 ? Xintr_ioapic_edge47 -ffffffff82556590 ? Xintr_ioapic_edge48 -ffffffff825565d0 ? Xintr_ioapic_edge49 -ffffffff82556610 ? Xintr_ioapic_edge50 -ffffffff82556650 ? Xintr_ioapic_edge51 -ffffffff82556690 ? Xintr_ioapic_edge52 -ffffffff825566d0 ? Xintr_ioapic_edge53 -ffffffff82556710 ? Xintr_ioapic_edge54 -ffffffff82556750 ? Xintr_ioapic_edge55 -ffffffff82556790 ? Xintr_ioapic_edge56 -ffffffff825567d0 ? Xintr_ioapic_edge57 -ffffffff82556810 ? Xintr_ioapic_edge58 -ffffffff82556850 ? Xintr_ioapic_edge59 -ffffffff82556890 ? Xintr_ioapic_edge60 -ffffffff825568d0 ? Xintr_ioapic_edge61 -ffffffff82556910 ? Xintr_ioapic_edge62 -ffffffff82556950 ? Xintr_ioapic_edge63 -ffffffff82556990 ? Xintr_ioapic_level0 -ffffffff825569d0 ? Xintr_ioapic_level1 -ffffffff82556a10 ? Xintr_ioapic_level2 -ffffffff82556a50 ? Xintr_ioapic_level3 -ffffffff82556a90 ? Xintr_ioapic_level4 -ffffffff82556ad0 ? Xintr_ioapic_level5 -ffffffff82556b10 ? Xintr_ioapic_level6 -ffffffff82556b50 ? Xintr_ioapic_level7 -ffffffff82556b90 ? Xintr_ioapic_level8 -ffffffff82556bd0 ? Xintr_ioapic_level9 -ffffffff82556c10 ? Xintr_ioapic_level10 -ffffffff82556c50 ? Xintr_ioapic_level11 -ffffffff82556c90 ? Xintr_ioapic_level12 -ffffffff82556cd0 ? Xintr_ioapic_level13 -ffffffff82556d10 ? Xintr_ioapic_level14 -ffffffff82556d50 ? Xintr_ioapic_level15 -ffffffff82556d90 ? Xintr_ioapic_level16 -ffffffff82556dd0 ? Xintr_ioapic_level17 -ffffffff82556e10 ? Xintr_ioapic_level18 -ffffffff82556e50 ? Xintr_ioapic_level19 -ffffffff82556e90 ? Xintr_ioapic_level20 -ffffffff82556ed0 ? Xintr_ioapic_level21 -ffffffff82556f10 ? Xintr_ioapic_level22 -ffffffff82556f50 ? Xintr_ioapic_level23 -ffffffff82556f90 ? Xintr_ioapic_level24 -ffffffff82556fd0 ? Xintr_ioapic_level25 -ffffffff82557010 ? Xintr_ioapic_level26 -ffffffff82557050 ? Xintr_ioapic_level27 -ffffffff82557090 ? Xintr_ioapic_level28 -ffffffff825570d0 ? Xintr_ioapic_level29 -ffffffff82557110 ? Xintr_ioapic_level30 -ffffffff82557150 ? Xintr_ioapic_level31 -ffffffff82557190 ? Xintr_ioapic_level32 -ffffffff825571d0 ? Xintr_ioapic_level33 -ffffffff82557210 ? Xintr_ioapic_level34 -ffffffff82557250 ? Xintr_ioapic_level35 -ffffffff82557290 ? Xintr_ioapic_level36 -ffffffff825572d0 ? Xintr_ioapic_level37 -ffffffff82557310 ? Xintr_ioapic_level38 -ffffffff82557350 ? Xintr_ioapic_level39 -ffffffff82557390 ? Xintr_ioapic_level40 -ffffffff825573d0 ? Xintr_ioapic_level41 -ffffffff82557410 ? Xintr_ioapic_level42 -ffffffff82557450 ? Xintr_ioapic_level43 -ffffffff82557490 ? Xintr_ioapic_level44 -ffffffff825574d0 ? Xintr_ioapic_level45 -ffffffff82557510 ? Xintr_ioapic_level46 -ffffffff82557550 ? Xintr_ioapic_level47 -ffffffff82557590 ? Xintr_ioapic_level48 -ffffffff825575d0 ? Xintr_ioapic_level49 -ffffffff82557610 ? Xintr_ioapic_level50 -ffffffff82557650 ? Xintr_ioapic_level51 -ffffffff82557690 ? Xintr_ioapic_level52 -ffffffff825576d0 ? Xintr_ioapic_level53 -ffffffff82557710 ? Xintr_ioapic_level54 -ffffffff82557750 ? Xintr_ioapic_level55 -ffffffff82557790 ? Xintr_ioapic_level56 -ffffffff825577d0 ? Xintr_ioapic_level57 -ffffffff82557810 ? Xintr_ioapic_level58 -ffffffff82557850 ? Xintr_ioapic_level59 -ffffffff82557890 ? Xintr_ioapic_level60 -ffffffff825578d0 ? Xintr_ioapic_level61 -ffffffff82557910 ? Xintr_ioapic_level62 -ffffffff82557950 ? Xintr_ioapic_level63 -ffffffff82558000 ? codepatch_fill_nop -ffffffff82558000 A __cptext_start -ffffffff82558000 A __kutext_end -ffffffff825580b0 ? codepatch_maprw -ffffffff82558190 ? codepatch_unmaprw -ffffffff82558200 ? codepatch_nop -ffffffff82558360 ? codepatch_replace -ffffffff82558510 ? codepatch_call -ffffffff82558530 ? codepatch_jmp -ffffffff82559000 A __cptext_end -ffffffff82559000 A __rodata_start -ffffffff82559000 C _etext -ffffffff82559000 C etext -ffffffff8255a000 r seeprom_read -ffffffff8255a004 r icl_mg_pll_find_divisors.div1_vals -ffffffff8255a028 r gen9bc_tgp_ddc_pin_map -ffffffff8255a038 r athn_ac2qid -ffffffff8255a038 r athn_ac2qid -ffffffff8255a038 r athn_ac2qid -ffffffff8255a044 r rtwn_get_rssi.cckoff -ffffffff8255a06c r rsu_ac2qid -ffffffff8255a07c r pckbc_portcmd -ffffffff8255a080 r tht_fifo_write_pad.pad -ffffffff8255a088 r rsu_get_rssi.cckoff -ffffffff8255a09c r adlp_n_revids -ffffffff8255a0ec r apple_iso_trans -ffffffff8255a0f0 r dg2_g12_revid_step_tbl -ffffffff8255a0f8 r wihap_check_tx.txratetable -ffffffff8255a0fc r dmamode -ffffffff8255a124 r gen9_edram_size_mb.sets -ffffffff8255b000 r isomappings -ffffffff8255b080 r unimappings -ffffffff8255b230 r replacements -ffffffff8255eb5f r cmd0646_9_tim_udma -ffffffff825b27d7 r pp_r600_decoded_lanes -ffffffff825cdbbf r cmd680_setup_channel.udma_tbl -ffffffff825d5884 r apollo_udma33_tim -ffffffff825db96c r substchar -ffffffff825dda85 r apollo_udma100_tim -ffffffff826053bd r apollo_udma66_tim -ffffffff8260c8a9 r apollo_pio_rec -ffffffff8261bc64 r cy_pio_rec -ffffffff8264b23e r apollo_udma133_tim -ffffffff82657e30 R drm_ca -ffffffff82657e58 R drm_filtops -ffffffff82657e88 R drmread_filtops -ffffffff82658000 r vga_emulops -ffffffff82658048 R vga_stdscreen -ffffffff82658078 R vga_stdscreen_mono -ffffffff826580a8 R vga_stdscreen_bf -ffffffff826580d8 R vga_40lscreen -ffffffff82658108 R vga_40lscreen_mono -ffffffff82658138 R vga_40lscreen_bf -ffffffff82658168 R vga_50lscreen -ffffffff82658198 R vga_50lscreen_mono -ffffffff826581c8 R vga_50lscreen_bf -ffffffff826581f8 R vga_screenlist -ffffffff82658208 R vga_screenlist_mono -ffffffff82658218 R vga_accessops -ffffffff82658278 r i945_wm_info -ffffffff826582b0 r bgansitopc -ffffffff826582b8 r pctoansi -ffffffff826582f8 r sdma_offsets -ffffffff826582f8 r sdma_offsets -ffffffff82658328 r iha_rate_tbl -ffffffff82658360 r i830_a_wm_info -ffffffff82658398 r gen9_edram_size_mb.ways -ffffffff82658400 r aggr_periodic_times -ffffffff82658480 r jsl_ehl_revids -ffffffff826584f8 r michael_final.pad -ffffffff82658520 r rt_copysa.maskarray -ffffffff82658528 r i915_wm_info -ffffffff82658530 r amdgpu_ih_clientid_jpeg -ffffffff82658530 r amdgpu_ih_clientid_uvds -ffffffff82658530 r amdgpu_ih_clientid_vcns -ffffffff82658530 r amdgpu_ih_clientid_vcns -ffffffff82658530 r amdgpu_ih_clientid_vcns -ffffffff82658568 r vga_setfontset.cmaptabb -ffffffff82658580 r tgl_revids -ffffffff826585d8 r i830_bc_wm_info -ffffffff82658648 r hsw_activate_psr2.map -ffffffff82658688 r __drm_universal_plane_init.default_modifiers -ffffffff82658698 r iwn_tid2fifo -ffffffff826586b0 r vga_setfontset.cmaptaba -ffffffff826586b8 r crtc_offsets -ffffffff826586b8 r crtc_offsets -ffffffff826586b8 r crtc_offsets -ffffffff826586d8 r link_speed -ffffffff826586d8 r link_speed -ffffffff826586d8 r link_speed -ffffffff82658750 r rtwn_r88e_get_rssi.cckoff -ffffffff82659000 R edid_vendors -ffffffff826592c0 R edid_nvendors -ffffffff826592d0 R edid_products -ffffffff82659330 R edid_nproducts -ffffffff82659340 r _edid_modes -ffffffff8265a000 R videomode_list -ffffffff8265b080 R videomode_count -ffffffff8265c000 r ahc_hard_errors -ffffffff8265c080 r critical_sections -ffffffff8265c0b0 r patches -ffffffff8265cd50 r seqprog -ffffffff8265e000 r ahc_switch -ffffffff8265f000 r termstat_strings -ffffffff8265f020 r critical_sections -ffffffff8265f060 r seqprog -ffffffff8265fd50 r patches -ffffffff82661000 r ahd_switch -ffffffff82662000 R aic_switch -ffffffff82663000 R adw_switch -ffffffff82664000 R gdt_switch -ffffffff82665000 R twe_switch -ffffffff82666000 R ciss_switch -ffffffff82666030 R ciss_level -ffffffff82666050 R ciss_stat -ffffffff82667000 R ami_switch -ffffffff82667028 R ami_raw_switch -ffffffff82668000 R mfi_switch -ffffffff82668028 R mfi_pd_switch -ffffffff82668050 r mfi_iop_xscale -ffffffff82668080 r mfi_iop_ppc -ffffffff826680b0 r mfi_iop_gen2 -ffffffff826680e0 r mfi_iop_skinny -ffffffff82668110 r mfi_bbu_indicators -ffffffff826681c0 r bwi_rf_calc_nrssi_slope_11b.save_phy_regs -ffffffff826681f0 r chv_oa_mux_regs -ffffffff82668210 r fiji_clock_stretcher_lookup_table -ffffffff82668210 r tonga_clock_stretcher_lookup_table -ffffffff82668230 r iosf_pci_devices -ffffffff82668250 r link_speed -ffffffff82668250 r link_speed -ffffffff82668250 r link_speed -ffffffff82668290 r drm_fb_xfrm.default_dst_pitch -ffffffff82668290 r non_supported_protection -ffffffff82668390 r tgl_uy_revids -ffffffff826683e0 r bwi_phy_noise_11g_rev1 -ffffffff82668460 r cardslot_process_event.antonym_ev -ffffffff826684f0 r gen11_oa_mux_regs -ffffffff826685e0 r ddr2_cycle_tenths -ffffffff82668650 r rtw_intr_rx.ratetbl -ffffffff826686d0 r abm_config -ffffffff82668740 r getbootinfo.ports.30 -ffffffff82668790 r reg_offsets -ffffffff826687a0 r bwi_rf_lo_measure_11g.rf_lo_adjust -ffffffff826687b0 r init_non_clock_fields.look_up -ffffffff826687c0 r uftdi_8u232am_getrate.roundoff -ffffffff82668810 r zyd_rx_data.rates -ffffffff82668820 r ieee80211_ra_valid_tx_mcs.max_mcs -ffffffff82668860 r mmio_invalidate_full.gen8_regs -ffffffff82668890 r bwi_phy_noise_11g -ffffffff826688a0 r hpt366_pio -ffffffff826688d0 r glk_revids -ffffffff82668920 r bwi_rf_calc_nrssi_slope_11g.save_phy3_regs -ffffffff82668940 r ether_crc32_be_update.rev -ffffffff82668940 r rtw_grf5101_mac_crypt.caesar -ffffffff82668990 r snb_b_fdi_train_param -ffffffff82669000 R qlw_switch -ffffffff8266a000 R isp_2100_risc_code -ffffffff8267cbf0 R isp_2200_risc_code -ffffffff8268f990 R isp_2300_risc_code -ffffffff826a9408 R qla_switch -ffffffff826a9430 r qla_regs_2100 -ffffffff826a9460 r qla_regs_2200 -ffffffff826a9490 r qla_regs_23XX -ffffffff826aa000 R ahci_atascsi_methods -ffffffff826ab000 R nvme_switch -ffffffff826ab028 r nvme_ops -ffffffff826ac000 R mpi_switch -ffffffff826ac100 r intel_hpll_vco.elk_vco -ffffffff826ac160 r pin_offsets -ffffffff826ac1c0 r firmware_list -ffffffff826ac220 r atom_arg_shift -ffffffff826ac220 r atom_arg_shift -ffffffff826ac260 r pf_syncookie_wstab -ffffffff826ac280 r ieee80211_media_init.mopts -ffffffff826ac2e0 r add_entropy_words.twist_table -ffffffff826ac380 r urtw_8225v2_txpwr_cck -ffffffff826ac3a0 r bwfm_pci_prio2fifo -ffffffff826ac3a0 r ieee80211_up_to_ac.up_to_ac -ffffffff826ac460 r paritytab -ffffffff826ac460 r x86emu_parity_tab -ffffffff826ac480 r legacy_connector_convert -ffffffff826ac4c0 r gen7_oa_mux_regs -ffffffff826ac4e0 r hsw_oa_mux_regs -ffffffff826ac500 r notetab -ffffffff826ac520 r urtw_8225v2_txpwr_cck_ch14 -ffffffff826ac540 r bwi_rf_calibval.rf_calibvals -ffffffff826ac5e0 r pf_syncookie_msstab -ffffffff826ac640 r xgmi3x16_pcs_err_status_reg_aldebaran -ffffffff826ac6a0 r uath_wme_init.uath_wme_11g -ffffffff826ac6c0 r gen7_oa_b_counters -ffffffff826ac820 r icl_revids -ffffffff826ac8e0 r rtwn_iq_calib_run.reg_adda -ffffffff826ac920 r atom_def_dst -ffffffff826ac920 r atom_def_dst -ffffffff826ac960 r sha256_initial_hash_value -ffffffff826ac9c0 r otus_edca_def -ffffffff826ac9e0 r intel_hpll_vco.blb_vco -ffffffff826acaa0 r epic_pci_subsys_info -ffffffff826acac0 r atom_arg_mask -ffffffff826acac0 r atom_arg_mask -ffffffff826acb20 r butmap -ffffffff826acb60 r GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS -ffffffff826acba0 r comsoft.lsrmap -ffffffff826acbe0 r tulip_mii_phy_readspecific.table -ffffffff826acc00 r kbl_revids -ffffffff826acca0 r intel_hpll_vco.pnv_vco -ffffffff826acd00 r dmapageport -ffffffff826acdc0 r intel_hpll_vco.ctg_vco -ffffffff826ace80 r drm_calculate_luminance_range.pre_computed_values -ffffffff826ad000 R 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virtual_link_encoder_update_mst_stream_allocation_table +ffffffff8223d240 t virtual_link_encoder_connect_dig_be_to_fe +ffffffff8223d270 t virtual_link_encoder_destroy +ffffffff8223d2c0 t virtual_link_encoder_get_max_link_cap +ffffffff8223e000 T virtual_setup_stream_encoder +ffffffff8223e030 T virtual_setup_stream_attribute +ffffffff8223e060 T virtual_reset_stream_encoder +ffffffff8223e090 T get_virtual_link_hwss +ffffffff8223e0c0 t virtual_disable_link_output +ffffffff8223f000 T virtual_stream_encoder_construct +ffffffff8223f050 T virtual_stream_encoder_create +ffffffff8223f110 t virtual_stream_encoder_dp_set_stream_attribute +ffffffff8223f140 t virtual_stream_encoder_hdmi_set_stream_attribute +ffffffff8223f170 t virtual_stream_encoder_dvi_set_stream_attribute +ffffffff8223f1a0 t virtual_stream_encoder_set_throttled_vcp_size +ffffffff8223f1d0 t virtual_stream_encoder_update_hdmi_info_packets +ffffffff8223f200 t virtual_stream_encoder_stop_hdmi_info_packets +ffffffff8223f230 t virtual_stream_encoder_update_dp_info_packets +ffffffff8223f260 t virtual_stream_encoder_stop_dp_info_packets +ffffffff8223f290 t virtual_stream_encoder_dp_blank +ffffffff8223f2c0 t virtual_stream_encoder_dp_unblank +ffffffff8223f2f0 t virtual_audio_mute_control +ffffffff8223f320 t virtual_setup_stereo_sync +ffffffff8223f350 t virtual_stream_encoder_set_avmute +ffffffff8223f380 t virtual_dig_connect_to_otg +ffffffff8223f3b0 t virtual_stream_encoder_reset_hdmi_stream_attribute +ffffffff8223f3e0 t virtual_stream_encoder_set_dsc_pps_info_packet +ffffffff8223f410 t virtual_enc_dp_set_odm_combine +ffffffff82240000 T dmub_dcn20_use_cached_inbox +ffffffff82240040 T dmub_dcn20_reset +ffffffff82240210 T dmub_dcn20_reset_release +ffffffff822402e0 T dmub_dcn20_backdoor_load +ffffffff82240590 T dmub_dcn20_setup_windows +ffffffff82240b00 T dmub_dcn20_setup_mailbox +ffffffff82240b60 T dmub_dcn20_get_inbox1_rptr +ffffffff82240b90 T dmub_dcn20_set_inbox1_wptr +ffffffff82240bc0 T dmub_dcn20_setup_out_mailbox +ffffffff82240c20 T dmub_dcn20_get_outbox1_wptr +ffffffff82240c50 T dmub_dcn20_set_outbox1_rptr +ffffffff82240c80 T dmub_dcn20_setup_outbox0 +ffffffff82240cd0 T dmub_dcn20_get_outbox0_wptr +ffffffff82240d00 T dmub_dcn20_set_outbox0_rptr +ffffffff82240d30 T dmub_dcn20_is_hw_init +ffffffff82240d90 T dmub_dcn20_is_supported +ffffffff82240df0 T dmub_dcn20_set_gpint +ffffffff82240e20 T dmub_dcn20_is_gpint_acked +ffffffff82240e80 T dmub_dcn20_get_gpint_response +ffffffff82240eb0 T dmub_dcn20_get_fw_boot_status +ffffffff82240ee0 T dmub_dcn20_enable_dmub_boot_options +ffffffff82240f10 T dmub_dcn20_skip_dmub_panel_power_sequence +ffffffff82240f70 T dmub_dcn20_get_current_time +ffffffff82240fa0 T dmub_dcn20_get_diagnostic_data +ffffffff82242000 T dmub_dcn21_is_phy_init +ffffffff82243000 T dmub_dcn30_backdoor_load +ffffffff82243260 T dmub_dcn30_setup_windows +ffffffff82244000 T dmub_dcn31_reset +ffffffff82244280 T dmub_dcn31_reset_release +ffffffff82244350 T dmub_dcn31_backdoor_load +ffffffff822445b0 T dmub_dcn31_setup_windows +ffffffff822448f0 T dmub_dcn31_setup_mailbox +ffffffff82244940 T dmub_dcn31_get_inbox1_rptr +ffffffff82244970 T dmub_dcn31_set_inbox1_wptr +ffffffff822449a0 T dmub_dcn31_setup_out_mailbox +ffffffff822449f0 T dmub_dcn31_get_outbox1_wptr +ffffffff82244a20 T dmub_dcn31_set_outbox1_rptr +ffffffff82244a50 T dmub_dcn31_is_hw_init +ffffffff82244ad0 T dmub_dcn31_is_supported +ffffffff82244b30 T dmub_dcn31_set_gpint +ffffffff82244b60 T dmub_dcn31_is_gpint_acked +ffffffff82244bc0 T dmub_dcn31_get_gpint_response +ffffffff82244bf0 T dmub_dcn31_get_gpint_dataout +ffffffff82244d10 T dmub_dcn31_get_fw_boot_status +ffffffff82244d40 T dmub_dcn31_enable_dmub_boot_options +ffffffff82244dc0 T dmub_dcn31_skip_dmub_panel_power_sequence +ffffffff82244e20 T dmub_dcn31_setup_outbox0 +ffffffff82244e70 T dmub_dcn31_get_outbox0_wptr +ffffffff82244ea0 T dmub_dcn31_set_outbox0_rptr +ffffffff82244ed0 T dmub_dcn31_get_current_time +ffffffff82244f00 T dmub_dcn31_get_diagnostic_data +ffffffff822453a0 T dmub_dcn31_should_detect +ffffffff82246000 T dmub_dcn32_reset +ffffffff82246200 T dmub_dcn32_reset_release +ffffffff822462d0 T dmub_dcn32_backdoor_load +ffffffff82246530 T dmub_dcn32_backdoor_load_zfb_mode +ffffffff82246720 T dmub_dcn32_setup_windows +ffffffff82246a60 T dmub_dcn32_setup_mailbox +ffffffff82246ab0 T dmub_dcn32_get_inbox1_rptr +ffffffff82246ae0 T dmub_dcn32_set_inbox1_wptr +ffffffff82246b10 T dmub_dcn32_setup_out_mailbox +ffffffff82246b60 T dmub_dcn32_get_outbox1_wptr +ffffffff82246b90 T dmub_dcn32_set_outbox1_rptr +ffffffff82246bc0 T dmub_dcn32_is_hw_init +ffffffff82246c40 T dmub_dcn32_is_supported +ffffffff82246ca0 T dmub_dcn32_set_gpint +ffffffff82246cd0 T dmub_dcn32_is_gpint_acked +ffffffff82246d30 T dmub_dcn32_get_gpint_response +ffffffff82246d60 T dmub_dcn32_get_gpint_dataout +ffffffff82246e80 T dmub_dcn32_get_fw_boot_status +ffffffff82246eb0 T dmub_dcn32_enable_dmub_boot_options +ffffffff82246ee0 T dmub_dcn32_skip_dmub_panel_power_sequence +ffffffff82246f40 T dmub_dcn32_setup_outbox0 +ffffffff82246f90 T dmub_dcn32_get_outbox0_wptr +ffffffff82246fc0 T dmub_dcn32_set_outbox0_rptr +ffffffff82246ff0 T dmub_dcn32_get_current_time +ffffffff82247020 T dmub_dcn32_get_diagnostic_data +ffffffff822474c0 T dmub_dcn32_configure_dmub_in_system_memory +ffffffff822474f0 T dmub_dcn32_send_inbox0_cmd +ffffffff82247520 T dmub_dcn32_clear_inbox0_ack_register +ffffffff82247550 T dmub_dcn32_read_inbox0_ack_register +ffffffff82248000 T dmub_reg_update +ffffffff82248170 T dmub_reg_set +ffffffff822482d0 T dmub_reg_get +ffffffff82249000 T dmub_flush_buffer_mem +ffffffff82249030 T dmub_srv_create +ffffffff82249560 T dmub_srv_destroy +ffffffff82249580 T dmub_srv_calc_region_info +ffffffff822497f0 T dmub_srv_calc_fb_info +ffffffff82249990 T dmub_srv_has_hw_support +ffffffff82249a00 T dmub_srv_is_hw_init +ffffffff82249a80 T dmub_srv_hw_init +ffffffff82249ed0 T dmub_srv_hw_reset +ffffffff82249f60 T dmub_srv_cmd_queue +ffffffff8224a070 T dmub_srv_cmd_execute +ffffffff8224a130 T dmub_srv_wait_for_auto_load +ffffffff8224a1d0 T dmub_srv_wait_for_phy_init +ffffffff8224a280 T dmub_srv_wait_for_idle +ffffffff8224a330 T dmub_srv_send_gpint_command +ffffffff8224a420 T dmub_srv_get_gpint_response +ffffffff8224a480 T dmub_srv_get_gpint_dataout +ffffffff8224a4e0 T dmub_srv_get_fw_boot_status +ffffffff8224a550 T dmub_srv_cmd_with_reply_data +ffffffff8224a7c0 T dmub_srv_get_outbox0_msg +ffffffff8224a860 T dmub_srv_get_diagnostic_data +ffffffff8224a8c0 T dmub_srv_should_detect +ffffffff8224a910 T dmub_srv_clear_inbox0_ack +ffffffff8224a960 T dmub_srv_wait_for_inbox0_ack +ffffffff8224a9f0 T dmub_srv_send_inbox0_cmd +ffffffff8224b000 T dmub_srv_stat_get_notification +ffffffff8224c000 T setup_x_points_distribution +ffffffff8224c170 T log_x_points_distribution +ffffffff8224c1a0 T precompute_pq +ffffffff8224c370 t compute_pq +ffffffff8224c580 T precompute_de_pq +ffffffff8224c6e0 t compute_de_pq +ffffffff8224c9a0 T calculate_user_regamma_coeff +ffffffff8224cd70 t apply_lut_1d +ffffffff8224d0a0 T calculate_user_regamma_ramp +ffffffff8224d9e0 T mod_color_calculate_degamma_params +ffffffff8224dfb0 t build_evenly_distributed_points +ffffffff8224e130 t scale_gamma +ffffffff8224e2e0 t build_degamma +ffffffff8224e6b0 t build_hlg_degamma +ffffffff8224e8d0 t map_regamma_hw_to_x_user +ffffffff8224f030 T mod_color_calculate_regamma_params +ffffffff822511a0 T mod_color_calculate_degamma_curve +ffffffff82251660 t translate_from_linear_space +ffffffff822519a0 t build_coefficients +ffffffff82251b20 t calculate_mapped_value +ffffffff82252000 T mod_color_is_table_init +ffffffff82252050 T mod_color_get_table +ffffffff822520a0 T mod_color_set_table_init_state +ffffffff82253000 T mod_freesync_create +ffffffff82253070 T mod_freesync_destroy +ffffffff822530b0 T mod_freesync_calc_v_total_from_refresh +ffffffff82253140 T mod_freesync_get_vmin_vmax +ffffffff82253180 T mod_freesync_get_v_position +ffffffff82253200 T mod_freesync_build_vrr_infopacket +ffffffff82253950 T mod_freesync_build_vrr_params +ffffffff82253cd0 T mod_freesync_calc_nominal_field_rate +ffffffff82253d30 T mod_freesync_handle_preflip +ffffffff82254150 T mod_freesync_handle_v_update +ffffffff82254610 T mod_freesync_get_settings +ffffffff82254680 T mod_freesync_calc_field_rate_from_timing +ffffffff822546d0 T mod_freesync_get_freesync_enabled +ffffffff82254700 T mod_freesync_is_valid_range +ffffffff82255000 T mod_build_vsc_infopacket +ffffffff82255200 T mod_build_hf_vsif_infopacket +ffffffff82256000 T dmub_init_abm_config +ffffffff82256540 t fill_iram_v_2_3 +ffffffff822569a0 T dmcu_load_iram +ffffffff82257180 T is_psr_su_specific_panel +ffffffff82257210 T mod_power_calc_psr_configs +ffffffff82257310 T mod_power_only_edp +ffffffff82257360 T psr_su_set_y_granularity +ffffffff82258000 T mod_vmid_get_for_ptb +ffffffff82258230 T mod_vmid_reset +ffffffff822582f0 T mod_vmid_create +ffffffff82258430 T mod_vmid_destroy +ffffffff82259000 T amdgpu_dpm_get_sclk +ffffffff82259090 T amdgpu_dpm_get_mclk +ffffffff82259120 T amdgpu_dpm_set_powergating_by_smu +ffffffff82259200 T amdgpu_dpm_set_gfx_power_up_by_imu +ffffffff82259310 T amdgpu_dpm_baco_enter +ffffffff822593a0 T amdgpu_dpm_baco_exit +ffffffff82259430 T amdgpu_dpm_set_mp1_state +ffffffff822594d0 T amdgpu_dpm_is_baco_supported +ffffffff82259580 T amdgpu_dpm_mode2_reset +ffffffff82259610 T amdgpu_dpm_baco_reset +ffffffff822596c0 T amdgpu_dpm_is_mode1_reset_supported +ffffffff82259730 T amdgpu_dpm_mode1_reset +ffffffff822597b0 T amdgpu_dpm_switch_power_profile +ffffffff82259860 T amdgpu_dpm_set_xgmi_pstate +ffffffff82259900 T amdgpu_dpm_set_df_cstate +ffffffff822599a0 T amdgpu_dpm_allow_xgmi_power_down +ffffffff82259a20 T amdgpu_dpm_enable_mgpu_fan_boost +ffffffff82259ab0 T amdgpu_dpm_set_clockgating_by_smu +ffffffff82259b50 T amdgpu_dpm_smu_i2c_bus_access +ffffffff82259bf0 T amdgpu_pm_acpi_event_handler +ffffffff82259cb0 T amdgpu_dpm_read_sensor +ffffffff82259d70 T amdgpu_dpm_compute_clocks +ffffffff82259e50 T amdgpu_dpm_enable_uvd +ffffffff8225a040 T amdgpu_dpm_enable_vce +ffffffff8225a230 T amdgpu_dpm_enable_jpeg +ffffffff8225a330 T amdgpu_pm_load_smu_firmware +ffffffff8225a3e0 T amdgpu_dpm_handle_passthrough_sbr +ffffffff8225a460 T amdgpu_dpm_send_hbm_bad_pages_num +ffffffff8225a4e0 T amdgpu_dpm_send_hbm_bad_channel_flag +ffffffff8225a560 T amdgpu_dpm_get_dpm_freq_range +ffffffff8225a600 T amdgpu_dpm_set_soft_freq_range +ffffffff8225a6a0 T amdgpu_dpm_write_watermarks_table +ffffffff8225a720 T amdgpu_dpm_wait_for_event +ffffffff8225a7b0 T amdgpu_dpm_set_residency_gfxoff +ffffffff8225a830 T amdgpu_dpm_get_residency_gfxoff +ffffffff8225a8b0 T amdgpu_dpm_get_entrycount_gfxoff +ffffffff8225a930 T amdgpu_dpm_get_status_gfxoff +ffffffff8225a9b0 T amdgpu_dpm_get_thermal_throttling_counter +ffffffff8225aa00 T amdgpu_dpm_gfx_state_change +ffffffff8225aa70 T amdgpu_dpm_get_ecc_info +ffffffff8225aaf0 T amdgpu_dpm_get_vce_clock_state +ffffffff8225ab80 T amdgpu_dpm_get_current_power_state +ffffffff8225abf0 T amdgpu_dpm_set_power_state +ffffffff8225ad50 T amdgpu_dpm_dispatch_task +ffffffff8225adf0 T amdgpu_dpm_get_performance_level +ffffffff8225ae80 T amdgpu_dpm_force_performance_level +ffffffff8225b060 T amdgpu_dpm_get_pp_num_states +ffffffff8225b0f0 T amdgpu_dpm_get_pp_table +ffffffff8225b180 T amdgpu_dpm_set_fine_grain_clk_vol +ffffffff8225b220 T amdgpu_dpm_odn_edit_dpm_table +ffffffff8225b2c0 T amdgpu_dpm_print_clock_levels +ffffffff8225b350 T amdgpu_dpm_emit_clock_levels +ffffffff8225b3f0 T amdgpu_dpm_set_ppfeature_status +ffffffff8225b480 T amdgpu_dpm_get_ppfeature_status +ffffffff8225b510 T amdgpu_dpm_force_clock_level +ffffffff8225b5a0 T amdgpu_dpm_get_sclk_od +ffffffff8225b620 T amdgpu_dpm_set_sclk_od +ffffffff8225b7a0 T amdgpu_dpm_get_mclk_od +ffffffff8225b820 T amdgpu_dpm_set_mclk_od +ffffffff8225b9a0 T amdgpu_dpm_get_power_profile_mode +ffffffff8225ba30 T amdgpu_dpm_set_power_profile_mode +ffffffff8225bad0 T amdgpu_dpm_get_gpu_metrics +ffffffff8225bb60 T amdgpu_dpm_get_fan_control_mode +ffffffff8225bbf0 T amdgpu_dpm_set_fan_speed_pwm +ffffffff8225bc80 T amdgpu_dpm_get_fan_speed_pwm +ffffffff8225bd10 T amdgpu_dpm_get_fan_speed_rpm +ffffffff8225bda0 T amdgpu_dpm_set_fan_speed_rpm +ffffffff8225be30 T amdgpu_dpm_set_fan_control_mode +ffffffff8225bec0 T amdgpu_dpm_get_power_limit +ffffffff8225bf70 T amdgpu_dpm_set_power_limit +ffffffff8225c000 T amdgpu_dpm_is_cclk_dpm_supported +ffffffff8225c070 T amdgpu_dpm_debugfs_print_current_performance_level +ffffffff8225c100 T amdgpu_dpm_get_smu_prv_buf_details +ffffffff8225c1a0 T amdgpu_dpm_is_overdrive_supported +ffffffff8225c210 T amdgpu_dpm_set_pp_table +ffffffff8225c2b0 T amdgpu_dpm_get_num_cpu_cores +ffffffff8225c300 T amdgpu_dpm_stb_debug_fs_init +ffffffff8225c350 T amdgpu_dpm_display_configuration_change +ffffffff8225c3e0 T amdgpu_dpm_get_clock_by_type +ffffffff8225c480 T amdgpu_dpm_get_display_mode_validation_clks +ffffffff8225c510 T amdgpu_dpm_get_clock_by_type_with_latency +ffffffff8225c5b0 T amdgpu_dpm_get_clock_by_type_with_voltage +ffffffff8225c650 T amdgpu_dpm_set_watermarks_for_clocks_ranges +ffffffff8225c6e0 T amdgpu_dpm_display_clock_voltage_request +ffffffff8225c770 T amdgpu_dpm_get_current_clocks +ffffffff8225c800 T amdgpu_dpm_notify_smu_enable_pwe +ffffffff8225c880 T amdgpu_dpm_set_active_display_count +ffffffff8225c910 T amdgpu_dpm_set_min_deep_sleep_dcefclk +ffffffff8225c9a0 T amdgpu_dpm_set_hard_min_dcefclk_by_freq +ffffffff8225ca40 T amdgpu_dpm_set_hard_min_fclk_by_freq +ffffffff8225cae0 T amdgpu_dpm_display_disable_memory_clock_switch +ffffffff8225cb70 T amdgpu_dpm_get_max_sustainable_clocks_by_dc +ffffffff8225cc00 T amdgpu_dpm_get_uclk_dpm_states +ffffffff8225cca0 T amdgpu_dpm_get_dpm_clock_table +ffffffff8225d000 T amdgpu_dpm_get_active_displays +ffffffff8225d0a0 T amdgpu_dpm_get_vblank_time +ffffffff8225d150 T amdgpu_dpm_get_vrefresh +ffffffff8225e000 T amdgpu_pm_sysfs_init +ffffffff8225e030 T amdgpu_pm_sysfs_fini +ffffffff8225e060 T amdgpu_debugfs_pm_init +ffffffff8225f000 T amdgpu_dpm_print_class_info +ffffffff8225f2b0 T amdgpu_dpm_print_cap_info +ffffffff8225f340 T amdgpu_dpm_print_ps_status +ffffffff8225f3d0 T amdgpu_pm_print_power_states +ffffffff8225f490 T amdgpu_get_platform_caps +ffffffff8225f530 T amdgpu_parse_extended_power_table +ffffffff82260540 T amdgpu_free_extended_power_table +ffffffff82260650 T amdgpu_add_thermal_controller +ffffffff82260a80 T amdgpu_get_vce_clock_state +ffffffff82260ac0 T amdgpu_legacy_dpm_compute_clocks +ffffffff82260f30 T amdgpu_dpm_thermal_work_handler +ffffffff82262000 t pp_early_init +ffffffff82262100 t pp_late_init +ffffffff82262220 t pp_sw_init +ffffffff82262240 t pp_sw_fini +ffffffff822622d0 t pp_hw_init +ffffffff82262330 t pp_hw_fini +ffffffff82262370 t pp_late_fini +ffffffff822623d0 t pp_suspend +ffffffff822623f0 t pp_resume +ffffffff82262410 t pp_is_idle +ffffffff82262440 t pp_wait_for_idle +ffffffff82262470 t pp_sw_reset +ffffffff822624a0 t pp_set_clockgating_state +ffffffff822624d0 t pp_set_powergating_state +ffffffff82262500 t pp_dpm_set_fan_control_mode +ffffffff82262570 t pp_dpm_get_fan_control_mode +ffffffff822625e0 t pp_dpm_set_fan_speed_pwm +ffffffff82262640 t pp_dpm_get_fan_speed_pwm +ffffffff822626a0 t pp_dpm_force_clock_level +ffffffff82262700 t pp_dpm_print_clock_levels +ffffffff82262760 t pp_dpm_emit_clock_levels +ffffffff822627c0 t pp_dpm_force_performance_level +ffffffff82262860 t pp_dpm_get_sclk_od +ffffffff822628c0 t pp_dpm_set_sclk_od +ffffffff82262920 t pp_dpm_get_mclk_od +ffffffff82262980 t pp_dpm_set_mclk_od +ffffffff822629e0 t pp_dpm_read_sensor +ffffffff82262a80 t pp_dpm_get_performance_level +ffffffff82262ac0 t pp_dpm_get_current_power_state +ffffffff82262b40 t pp_dpm_get_fan_speed_rpm +ffffffff82262ba0 t pp_dpm_set_fan_speed_rpm +ffffffff82262c00 t pp_dpm_get_pp_num_states +ffffffff82262d40 t pp_dpm_get_pp_table +ffffffff82262d90 t pp_dpm_set_pp_table +ffffffff82262ec0 t pp_dpm_switch_power_profile +ffffffff82263000 t pp_dpm_get_vce_clock_state +ffffffff82263050 t pp_dpm_dispatch_tasks +ffffffff82263090 t pp_dpm_load_fw +ffffffff82263100 t pp_dpm_fw_loading_complete +ffffffff82263130 t pp_set_powergating_by_smu +ffffffff822632b0 t pp_set_clockgating_by_smu +ffffffff82263320 t pp_set_power_limit +ffffffff822633e0 t pp_get_power_limit +ffffffff82263480 t pp_get_power_profile_mode +ffffffff822634e0 t pp_set_power_profile_mode +ffffffff82263540 t pp_set_fine_grain_clk_vol +ffffffff822635a0 t pp_odn_edit_dpm_table +ffffffff82263600 t pp_dpm_set_mp1_state +ffffffff82263660 t pp_smu_i2c_bus_access +ffffffff822636c0 t pp_gfx_state_change_set +ffffffff82263720 t pp_dpm_get_sclk +ffffffff82263770 t pp_dpm_get_mclk +ffffffff822637c0 t pp_display_configuration_change +ffffffff82263810 t pp_get_display_power_level +ffffffff82263850 t pp_get_current_clocks +ffffffff82263970 t pp_get_clock_by_type +ffffffff822639c0 t pp_get_clock_by_type_with_latency +ffffffff82263a10 t pp_get_clock_by_type_with_voltage +ffffffff82263a60 t pp_set_watermarks_for_clocks_ranges +ffffffff82263aa0 t pp_display_clock_voltage_request +ffffffff82263ae0 t pp_get_display_mode_validation_clocks +ffffffff82263b40 t pp_notify_smu_enable_pwe +ffffffff82263ba0 t pp_enable_mgpu_fan_boost +ffffffff82263c00 t pp_set_active_display_count +ffffffff82263c40 t pp_set_hard_min_dcefclk_by_freq +ffffffff82263ca0 t pp_set_hard_min_fclk_by_freq +ffffffff82263d00 t pp_set_min_deep_sleep_dcefclk +ffffffff82263d60 t pp_get_asic_baco_capability +ffffffff82263dd0 t pp_get_asic_baco_state +ffffffff82263e30 t pp_set_asic_baco_state +ffffffff82263ea0 t pp_get_ppfeature_status +ffffffff82263f00 t pp_set_ppfeature_status +ffffffff82263f50 t pp_asic_reset_mode_2 +ffffffff82263fb0 t pp_set_df_cstate +ffffffff82264010 t pp_set_xgmi_pstate +ffffffff82264070 t pp_get_gpu_metrics +ffffffff822640d0 t pp_get_prv_buffer_details +ffffffff82264150 t pp_pm_compute_clocks +ffffffff82265000 T ci_baco_set_state +ffffffff82266000 T baco_program_registers +ffffffff822660d0 t baco_cmd_handler +ffffffff82266250 T soc15_baco_program_registers +ffffffff82267000 T fiji_baco_set_state +ffffffff82268000 T phm_setup_asic +ffffffff82268050 T phm_power_down_asic +ffffffff822680a0 T phm_set_power_state +ffffffff82268110 T phm_enable_dynamic_state_management +ffffffff822681c0 T phm_disable_dynamic_state_management +ffffffff82268260 T phm_force_dpm_levels +ffffffff822682b0 T phm_apply_state_adjust_rules +ffffffff82268300 T phm_apply_clock_adjust_rules +ffffffff82268350 T phm_powerdown_uvd +ffffffff822683a0 T phm_disable_clock_power_gatings +ffffffff822683f0 T phm_pre_display_configuration_changed +ffffffff82268450 T phm_display_configuration_changed +ffffffff822684b0 T phm_notify_smc_display_config_after_ps_adjustment +ffffffff82268510 T phm_stop_thermal_controller +ffffffff82268570 T phm_register_irq_handlers +ffffffff822685c0 T phm_start_thermal_controller +ffffffff82268700 T phm_check_smc_update_required_for_display_configuration +ffffffff82268760 T phm_check_states_equal +ffffffff822687b0 T phm_store_dal_configuration_data +ffffffff82268900 T phm_get_dal_power_level +ffffffff82268960 T phm_set_cpu_power_state +ffffffff822689b0 T phm_get_performance_level +ffffffff82268a10 T phm_get_clock_info +ffffffff82268b90 T phm_get_current_shallow_sleep_clocks +ffffffff82268be0 T phm_get_clock_by_type +ffffffff82268c30 T phm_get_clock_by_type_with_latency +ffffffff82268c80 T phm_get_clock_by_type_with_voltage +ffffffff82268cd0 T phm_set_watermarks_for_clocks_ranges +ffffffff82268d20 T phm_display_clock_voltage_request +ffffffff82268d70 T phm_get_max_high_clocks +ffffffff82268dc0 T phm_disable_smc_firmware_ctf +ffffffff82268e20 T phm_set_active_display_count +ffffffff82269000 T hwmgr_early_init +ffffffff82269470 T hwmgr_sw_init +ffffffff822694e0 T hwmgr_sw_fini +ffffffff82269530 T hwmgr_hw_init +ffffffff822696f0 T hwmgr_hw_fini +ffffffff822697b0 T hwmgr_suspend +ffffffff82269830 T hwmgr_resume +ffffffff822698d0 T hwmgr_handle_task +ffffffff8226a000 T polaris_baco_set_state +ffffffff8226b000 T pp_override_get_default_fuse_value +ffffffff8226c000 T psm_init_power_state_table +ffffffff8226c2a0 T psm_fini_power_state_table +ffffffff8226c360 T psm_set_boot_states +ffffffff8226c420 T psm_set_performance_states +ffffffff8226c4e0 T psm_set_user_performance_state +ffffffff8226c580 T psm_adjust_power_state_dynamic +ffffffff8226d000 T atomctrl_initialize_mc_reg_table +ffffffff8226d210 T atomctrl_initialize_mc_reg_table_v2_2 +ffffffff8226d420 T atomctrl_set_engine_dram_timings_rv770 +ffffffff8226d490 T atomctrl_get_memory_pll_dividers_si +ffffffff8226d570 T atomctrl_get_memory_pll_dividers_vi +ffffffff8226d5f0 T atomctrl_get_memory_pll_dividers_ai +ffffffff8226d6a0 T atomctrl_get_engine_pll_dividers_kong +ffffffff8226d720 T atomctrl_get_engine_pll_dividers_vi +ffffffff8226d7e0 T atomctrl_get_engine_pll_dividers_ai +ffffffff8226d8c0 T atomctrl_get_dfs_pll_dividers_vi +ffffffff8226d980 T atomctrl_get_reference_clock +ffffffff8226d9e0 T atomctrl_is_voltage_controlled_by_gpio_v3 +ffffffff8226daa0 T atomctrl_get_voltage_table_v3 +ffffffff8226dc00 T atomctrl_get_pp_assign_pin +ffffffff8226dcf0 T atomctrl_calculate_voltage_evv_on_sclk +ffffffff8226e070 T atomctrl_get_voltage_evv_on_sclk +ffffffff8226e0f0 T atomctrl_get_voltage_evv +ffffffff8226e1a0 T atomctrl_get_mpll_reference_clock +ffffffff8226e210 T atomctrl_is_asic_internal_ss_supported +ffffffff8226e260 T atomctrl_get_memory_clock_spread_spectrum +ffffffff8226e360 T atomctrl_get_engine_clock_spread_spectrum +ffffffff8226e460 T atomctrl_read_efuse +ffffffff8226e510 T atomctrl_set_ac_timing_ai +ffffffff8226e570 T atomctrl_get_voltage_evv_on_sclk_ai +ffffffff8226e5f0 T atomctrl_get_smc_sclk_range_table +ffffffff8226e6b0 T atomctrl_get_vddc_shared_railinfo +ffffffff8226e720 T atomctrl_get_avfs_information +ffffffff8226e8a0 T atomctrl_get_svi2_info +ffffffff8226e980 T atomctrl_get_leakage_id_from_efuse +ffffffff8226e9e0 T atomctrl_get_leakage_vddc_base_on_leakage +ffffffff8226eb80 T atomctrl_get_voltage_range +ffffffff8226ec40 T atomctrl_get_edc_hilo_leakage_offset_table +ffffffff8226ecc0 T atomctrl_get_edc_leakage_table +ffffffff8226f000 T pp_atomfwctrl_is_voltage_controlled_by_gpio_v4 +ffffffff8226f0d0 T pp_atomfwctrl_get_voltage_table_v4 +ffffffff8226f290 T pp_atomfwctrl_get_pp_assign_pin +ffffffff8226f370 T pp_atomfwctrl_enter_self_refresh +ffffffff8226f3a0 T pp_atomfwctrl_get_gpu_pll_dividers_vega10 +ffffffff8226f450 T pp_atomfwctrl_get_avfs_information +ffffffff8226f780 T pp_atomfwctrl_get_gpio_information +ffffffff8226f820 T pp_atomfwctrl_get_clk_information_by_clkid +ffffffff8226f8a0 T pp_atomfwctrl_get_vbios_bootup_values +ffffffff8226fc20 T pp_atomfwctrl_get_smc_dpm_information +ffffffff82270000 T encode_pcie_lane_width +ffffffff82270030 T decode_pcie_lane_width +ffffffff82271000 t pp_tables_v1_0_initialize +ffffffff82272430 t pp_tables_v1_0_uninitialize +ffffffff822725e0 T get_number_of_powerplay_table_entries_v1_0 +ffffffff82272690 T get_powerplay_table_entry_v1_0 +ffffffff82273000 T pp_tables_get_response_times +ffffffff822730d0 T pp_tables_get_num_of_entries +ffffffff82273190 T pp_tables_get_entry +ffffffff822734f0 t init_non_clock_fields +ffffffff82273670 t pp_tables_initialize +ffffffff82274ad0 t pp_tables_uninitialize +ffffffff82274cd0 t get_number_of_vce_state_table_entries +ffffffff82274dd0 t get_vce_state_table_entry +ffffffff82275000 T smu10_init_function_pointers +ffffffff82275040 t smu10_hwmgr_backend_init +ffffffff82275710 t smu10_hwmgr_backend_fini +ffffffff82275850 t smu10_setup_asic_task +ffffffff822758c0 t smu10_get_power_state_size +ffffffff822758f0 t smu10_apply_state_adjust_rules +ffffffff82275920 t smu10_dpm_force_dpm_level +ffffffff82275ea0 t smu10_enable_dpm_tasks +ffffffff82275f20 t smu10_disable_dpm_tasks +ffffffff82275f50 t smu10_dpm_patch_boot_state +ffffffff82275f80 t smu10_dpm_get_pp_table_entry +ffffffff82275fe0 t smu10_dpm_get_num_of_pp_table_entries +ffffffff82276030 t smu10_powergate_vcn +ffffffff822760d0 t smu10_dpm_get_mclk +ffffffff82276130 t smu10_dpm_get_sclk +ffffffff82276180 t smu10_set_power_state_tasks +ffffffff822761f0 t smu10_set_cpu_power_state +ffffffff82276220 t smu10_store_cc6_data +ffffffff82276290 t smu10_get_dal_power_level +ffffffff822762c0 t smu10_get_performance_level +ffffffff82276350 t smu10_get_current_shallow_sleep_clocks +ffffffff822763b0 t smu10_get_clock_by_type_with_latency +ffffffff82276500 t smu10_get_clock_by_type_with_voltage +ffffffff82276610 t smu10_set_watermarks_for_clocks_ranges +ffffffff822766e0 t smu10_display_clock_voltage_request +ffffffff82276780 t smu10_get_max_high_clocks +ffffffff822767b0 t smu10_power_off_asic +ffffffff82276800 t smu10_force_clock_level +ffffffff822769c0 t smu10_print_clock_levels +ffffffff82276d60 t smu10_gfx_off_control +ffffffff82276e70 t smu10_read_sensor +ffffffff82276ff0 t smu10_set_active_display_count +ffffffff82277050 t smu10_set_min_deep_sleep_dcefclk +ffffffff822770b0 t smu10_get_power_profile_mode +ffffffff822770f0 t smu10_set_power_profile_mode +ffffffff82277240 t smu10_set_fine_grain_clk_vol +ffffffff82277450 t smu10_powergate_mmhub +ffffffff82277470 t smu10_smus_notify_pwe +ffffffff82277490 t smu10_powergate_sdma +ffffffff822774b0 t smu10_set_hard_min_dcefclk_by_freq +ffffffff82277510 t smu10_set_hard_min_fclk_by_freq +ffffffff82277570 t smu10_set_hard_min_gfxclk_by_freq +ffffffff822775d0 t smu10_set_soft_max_gfxclk_by_freq +ffffffff82277630 t smu10_asic_reset +ffffffff82277650 t smu10_gfx_state_change +ffffffff82277690 t smu10_dpm_get_pp_table_entry_callback +ffffffff82278000 T smu7_baco_get_capability +ffffffff82278060 T smu7_baco_get_state +ffffffff822780b0 T smu7_baco_set_state +ffffffff82279000 T smu7_powerdown_uvd +ffffffff82279050 T smu7_disable_clock_power_gating +ffffffff822790e0 T smu7_powergate_uvd +ffffffff822791d0 T smu7_powergate_vce +ffffffff822792c0 T smu7_update_clock_gatings +ffffffff82279670 T smu7_powergate_gfx +ffffffff8227a000 T smu7_get_sleep_divider_id_from_clock +ffffffff8227a0a0 T smu7_init_function_pointers +ffffffff8227a100 t smu7_hwmgr_backend_init +ffffffff8227bf50 t smu7_hwmgr_backend_fini +ffffffff8227bfc0 t smu7_setup_asic_task +ffffffff8227c330 t smu7_get_power_state_size +ffffffff8227c360 t smu7_apply_state_adjust_rules +ffffffff8227c7e0 t smu7_force_dpm_level +ffffffff8227cc10 t smu7_enable_dpm_tasks +ffffffff8227f380 t smu7_disable_dpm_tasks +ffffffff8227fac0 t smu7_dpm_patch_boot_state +ffffffff8227fc00 t smu7_get_pp_table_entry +ffffffff82280000 t smu7_get_number_of_powerplay_table_entries +ffffffff82280070 t smu7_dpm_get_mclk +ffffffff82280110 t smu7_dpm_get_sclk +ffffffff822801b0 t smu7_set_power_state_tasks +ffffffff82280f40 t smu7_notify_smc_display_config_after_ps_adjustment +ffffffff82280f70 t smu7_display_configuration_changed_task +ffffffff82281130 t smu7_set_max_fan_rpm_output +ffffffff82281160 t smu7_set_max_fan_pwm_output +ffffffff82281180 t smu7_set_fan_control_mode +ffffffff82281210 t smu7_get_fan_control_mode +ffffffff82281250 t smu7_register_irq_handlers +ffffffff82281300 t smu7_check_smc_update_required_for_display_configuration +ffffffff822813c0 t smu7_check_states_equal +ffffffff82281560 t smu7_get_performance_level +ffffffff82281600 t smu7_get_clock_by_type +ffffffff822817c0 t smu7_get_clock_by_type_with_latency +ffffffff82281960 t smu7_set_watermarks_for_clocks_ranges +ffffffff82281ba0 t smu7_get_max_high_clocks +ffffffff82281c20 t smu7_power_off_asic +ffffffff82281c80 t smu7_force_clock_level +ffffffff82281d90 t smu7_print_clock_levels +ffffffff82282370 t smu7_get_sclk_od +ffffffff822823e0 t smu7_set_sclk_od +ffffffff822824a0 t smu7_get_mclk_od +ffffffff82282510 t smu7_set_mclk_od +ffffffff822825d0 t smu7_read_sensor +ffffffff822828a0 t smu7_avfs_control +ffffffff82282970 t smu7_notify_cac_buffer_info +ffffffff82282b10 t smu7_get_thermal_temperature_range +ffffffff82282ba0 t smu7_get_power_profile_mode +ffffffff82282be0 t smu7_set_power_profile_mode +ffffffff82282e40 t smu7_odn_edit_dpm_table +ffffffff82282ff0 t phm_add_voltage +ffffffff82283100 t smu7_get_profiling_clk +ffffffff822832c0 t smu7_check_dpm_table_updated +ffffffff82283410 t smu7_odn_initial_default_setting +ffffffff82283540 t smu7_set_dpm_event_sources +ffffffff82283660 t smu7_get_pp_table_entry_callback_func_v0 +ffffffff82283b60 t smu7_get_pp_table_entry_callback_func_v1 +ffffffff82285000 T smu7_enable_didt_config +ffffffff822853c0 t smu7_program_pt_config_registers +ffffffff822855b0 t smu7_enable_didt +ffffffff822857a0 T smu7_disable_didt_config +ffffffff82285860 T smu7_enable_smc_cac +ffffffff822858f0 T smu7_disable_smc_cac +ffffffff82285980 T smu7_set_power_limit +ffffffff822859e0 T smu7_enable_power_containment +ffffffff82285b70 T smu7_disable_power_containment +ffffffff82285c90 T smu7_power_control_set_level +ffffffff82286000 T smu7_fan_ctrl_get_fan_speed_info +ffffffff82286080 T smu7_fan_ctrl_get_fan_speed_pwm +ffffffff82286140 T smu7_fan_ctrl_get_fan_speed_rpm +ffffffff822861f0 T smu7_fan_ctrl_set_static_mode +ffffffff82286320 T smu7_fan_ctrl_set_default_mode +ffffffff82286400 T smu7_fan_ctrl_start_smc_fan_control +ffffffff82286530 T smu7_fan_ctrl_stop_smc_fan_control +ffffffff82286550 T smu7_fan_ctrl_set_fan_speed_pwm +ffffffff82286740 T smu7_fan_ctrl_reset_fan_speed_to_default +ffffffff82286930 T smu7_fan_ctrl_set_fan_speed_rpm +ffffffff82286b10 T smu7_thermal_get_temperature +ffffffff82286b70 T smu7_thermal_disable_alert +ffffffff82286c10 T smu7_thermal_stop_thermal_controller +ffffffff82286d90 T smu7_start_thermal_controller +ffffffff82287140 T smu7_thermal_ctrl_uninitialize_thermal_controller +ffffffff82288000 T smu8_init_function_pointers +ffffffff82288040 t smu8_hwmgr_backend_init +ffffffff82288520 t smu8_hwmgr_backend_fini +ffffffff822885a0 t smu8_setup_asic_task +ffffffff82288ac0 t smu8_get_power_state_size +ffffffff82288af0 t smu8_apply_state_adjust_rules +ffffffff82288c40 t smu8_dpm_force_dpm_level +ffffffff82288f40 t smu8_enable_dpm_tasks +ffffffff82289090 t smu8_disable_dpm_tasks +ffffffff82289170 t smu8_dpm_patch_boot_state +ffffffff822891d0 t smu8_dpm_get_pp_table_entry +ffffffff82289230 t smu8_dpm_get_num_of_pp_table_entries +ffffffff82289280 t smu8_dpm_powerdown_uvd +ffffffff822892d0 t smu8_dpm_powergate_vce +ffffffff822894a0 t smu8_dpm_powergate_uvd +ffffffff822896d0 t smu8_dpm_powergate_acp +ffffffff82289730 t smu8_dpm_get_mclk +ffffffff82289760 t smu8_dpm_get_sclk +ffffffff822897d0 t smu8_set_power_state_tasks +ffffffff82289b20 t smu8_set_cpu_power_state +ffffffff82289ba0 t smu8_store_cc6_data +ffffffff82289c20 t smu8_get_dal_power_level +ffffffff82289ca0 t smu8_get_performance_level +ffffffff82289d90 t smu8_get_current_shallow_sleep_clocks +ffffffff82289df0 t smu8_get_clock_by_type +ffffffff82289f30 t smu8_get_max_high_clocks +ffffffff82289ff0 t smu8_power_off_asic +ffffffff8228a070 t smu8_force_clock_level +ffffffff8228a0e0 t smu8_print_clock_levels +ffffffff8228a2b0 t smu8_read_sensor +ffffffff8228a5b0 t smu8_notify_cac_buffer_info +ffffffff8228a660 t smu8_get_thermal_temperature_range +ffffffff8228a6e0 t smu8_dpm_get_pp_table_entry_callback +ffffffff8228b000 T smu9_baco_get_capability +ffffffff8228b0d0 T smu9_baco_get_state +ffffffff8228c000 T convert_to_vid +ffffffff8228c050 T convert_to_vddc +ffffffff8228c0a0 T phm_copy_clock_limits_array +ffffffff8228c180 T phm_copy_overdrive_settings_limits_array +ffffffff8228c260 T phm_set_field_to_u32 +ffffffff8228c2c0 T phm_wait_on_register +ffffffff8228c3d0 T phm_wait_on_indirect_register +ffffffff8228c500 T phm_wait_for_register_unequal +ffffffff8228c600 T phm_wait_for_indirect_register_unequal +ffffffff8228c730 T phm_cf_want_uvd_power_gating +ffffffff8228c770 T phm_cf_want_vce_power_gating +ffffffff8228c7b0 T phm_trim_voltage_table +ffffffff8228c8e0 T phm_get_svi2_mvdd_voltage_table +ffffffff8228ca70 T phm_get_svi2_vddci_voltage_table +ffffffff8228cc00 T phm_get_svi2_vdd_voltage_table +ffffffff8228cca0 T phm_trim_voltage_table_to_fit_state_table +ffffffff8228cd80 T phm_reset_single_dpm_table +ffffffff8228ce50 T phm_setup_pcie_table_entry +ffffffff8228ce90 T phm_get_dpm_level_enable_mask_value +ffffffff8228cfb0 T phm_get_voltage_index +ffffffff8228d030 T phm_get_voltage_id +ffffffff8228d0b0 T phm_find_closest_vddci +ffffffff8228d110 T phm_find_boot_level +ffffffff8228d180 T phm_get_sclk_for_voltage_evv +ffffffff8228d230 T phm_initializa_dynamic_state_adjustment_rule_settings +ffffffff8228d340 T phm_get_lowest_enabled_level +ffffffff8228d380 T phm_apply_dal_min_voltage_request +ffffffff8228d450 T phm_get_voltage_evv_on_sclk +ffffffff8228d500 T phm_irq_process +ffffffff8228d700 t orderly_poweroff +ffffffff8228d710 T smu9_register_irq_handlers +ffffffff8228d7c0 T smu_atom_get_data_table +ffffffff8228d830 T smu_get_voltage_dependency_table_ppt_v1 +ffffffff8228d910 T smu_set_watermarks_for_clocks_ranges +ffffffff8228e000 T tonga_baco_set_state +ffffffff8228f000 T vega10_baco_set_state +ffffffff82290000 T vega10_enable_disable_vce_dpm +ffffffff82290090 T vega10_hwmgr_init +ffffffff822900f0 t vega10_hwmgr_backend_init +ffffffff82290ef0 t vega10_hwmgr_backend_fini +ffffffff82290f60 t vega10_setup_asic_task +ffffffff82291090 t vega10_get_power_state_size +ffffffff822910c0 t vega10_apply_state_adjust_rules +ffffffff82291450 t vega10_dpm_force_dpm_level +ffffffff82291980 t vega10_enable_dpm_tasks +ffffffff822942f0 t vega10_disable_dpm_tasks +ffffffff822948d0 t vega10_patch_boot_state +ffffffff82294900 t vega10_get_pp_table_entry +ffffffff82294970 t vega10_power_gate_vce +ffffffff82294a10 t vega10_power_gate_uvd +ffffffff82294ab0 t vega10_dpm_get_mclk +ffffffff82294b50 t vega10_dpm_get_sclk +ffffffff82294bf0 t vega10_set_power_state_tasks +ffffffff82295680 t vega10_notify_smc_display_config_after_ps_adjustment +ffffffff82295830 t vega10_display_configuration_changed_task +ffffffff82295900 t vega10_set_fan_control_mode +ffffffff82295970 t vega10_get_fan_control_mode +ffffffff822959b0 t vega10_check_smc_update_required_for_display_configuration +ffffffff82295a10 t vega10_check_states_equal +ffffffff82295b70 t vega10_get_dal_power_level +ffffffff82295bb0 t vega10_get_performance_level +ffffffff82295c50 t vega10_get_clock_by_type_with_latency +ffffffff82295e80 t vega10_get_clock_by_type_with_voltage +ffffffff82295f60 t vega10_set_watermarks_for_clocks_ranges +ffffffff82295fc0 t vega10_display_clock_voltage_request +ffffffff82296040 t vega10_power_off_asic +ffffffff822960b0 t vega10_force_clock_level +ffffffff822961e0 t vega10_emit_clock_levels +ffffffff82296350 t vega10_print_clock_levels +ffffffff82296b30 t vega10_get_sclk_od +ffffffff82296ba0 t vega10_set_sclk_od +ffffffff82296ca0 t vega10_get_mclk_od +ffffffff82296d10 t vega10_set_mclk_od +ffffffff82296e00 t vega10_read_sensor +ffffffff82297050 t vega10_avfs_enable +ffffffff82297110 t vega10_notify_cac_buffer_info +ffffffff822971c0 t vega10_get_thermal_temperature_range +ffffffff822972a0 t vega10_get_power_profile_mode +ffffffff822972e0 t vega10_set_power_profile_mode +ffffffff82297400 t vega10_odn_edit_dpm_table +ffffffff822979c0 t vega10_get_ppfeature_status +ffffffff82297a40 t vega10_set_ppfeature_status +ffffffff82297ae0 t vega10_set_mp1_state +ffffffff82297b50 t vega10_disable_power_features_for_compute_performance +ffffffff82297d40 t vega10_upload_dpm_bootup_level +ffffffff82297e50 t vega10_upload_dpm_max_level +ffffffff82297f30 t vega10_trim_voltage_table_to_fit_state_table +ffffffff82298030 t vega10_odn_initial_default_setting +ffffffff82298200 t vega10_populate_all_graphic_levels +ffffffff82298400 t vega10_populate_all_memory_levels +ffffffff82298560 t vega10_populate_single_gfx_level +ffffffff822986b0 t vega10_populate_single_soc_level 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vega12_fan_ctrl_start_smc_fan_control +ffffffff822a70e0 T vega12_fan_ctrl_stop_smc_fan_control +ffffffff822a7110 T vega12_fan_ctrl_reset_fan_speed_to_default +ffffffff822a7140 T vega12_thermal_get_temperature +ffffffff822a71d0 T vega12_thermal_disable_alert +ffffffff822a7260 T vega12_thermal_stop_thermal_controller +ffffffff822a72f0 T vega12_start_thermal_controller +ffffffff822a8000 T vega20_baco_get_capability +ffffffff822a80c0 T vega20_baco_get_state +ffffffff822a8150 T vega20_baco_set_state +ffffffff822a8350 T vega20_baco_apply_vdci_flush_workaround +ffffffff822a9000 T vega20_hwmgr_init +ffffffff822a9040 t vega20_hwmgr_backend_init +ffffffff822a9980 t vega20_hwmgr_backend_fini +ffffffff822a99e0 t vega20_setup_asic_task +ffffffff822a9ad0 t vega20_apply_clocks_adjust_rules +ffffffff822a9fc0 t vega20_dpm_force_dpm_level +ffffffff822aa730 t vega20_enable_dpm_tasks +ffffffff822abba0 t vega20_disable_dpm_tasks +ffffffff822abd40 t vega20_power_gate_vce +ffffffff822abe70 t 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amdgpu_smu_stb_debug_fs_init +ffffffff822dc6b0 T smu_send_hbm_bad_pages_num +ffffffff822dc700 T smu_send_hbm_bad_channel_flag +ffffffff822dc750 t smu_set_fan_control_mode +ffffffff822dc810 t smu_get_fan_control_mode +ffffffff822dc890 t smu_set_fan_speed_pwm +ffffffff822dc940 t smu_get_fan_speed_pwm +ffffffff822dc9a0 t smu_force_ppclk_levels +ffffffff822dcac0 t smu_print_ppclk_levels +ffffffff822dcb30 t smu_emit_ppclk_levels +ffffffff822dcba0 t smu_force_performance_level +ffffffff822dce40 t smu_read_sensor +ffffffff822dd040 t smu_get_performance_level +ffffffff822dd0b0 t smu_get_current_power_state +ffffffff822dd110 t smu_get_fan_speed_rpm +ffffffff822dd170 t smu_set_fan_speed_rpm +ffffffff822dd220 t smu_get_power_num_states +ffffffff822dd2a0 t smu_sys_get_pp_table +ffffffff822dd310 t smu_sys_set_pp_table +ffffffff822dd500 t smu_switch_power_profile +ffffffff822dd610 t smu_handle_dpm_task +ffffffff822dd6c0 t smu_load_microcode +ffffffff822dd7b0 t smu_dpm_set_power_gate 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smu_set_watermarks_for_clock_ranges +ffffffff822de730 t smu_display_disable_memory_clock_switch +ffffffff822de790 t smu_get_max_sustainable_clocks_by_dc +ffffffff822de7f0 t smu_get_uclk_dpm_states +ffffffff822de850 t smu_get_dpm_clock_table +ffffffff822de8b0 t smu_get_prv_buffer_details +ffffffff822de920 t smu_adjust_power_state_dynamic +ffffffff822deb80 t smu_throttling_logging_work_fn +ffffffff822debd0 t smu_interrupt_work_fn +ffffffff822dec20 t smu_smc_hw_setup +ffffffff822df580 t smu_smc_hw_cleanup +ffffffff822e0000 T arcturus_set_ppt_funcs +ffffffff822e0050 t arcturus_run_btc +ffffffff822e0100 t arcturus_get_allowed_feature_mask +ffffffff822e0150 t arcturus_set_default_dpm_table +ffffffff822e0360 t arcturus_populate_umd_state_clk +ffffffff822e0420 t arcturus_print_clk_levels +ffffffff822e0670 t arcturus_force_clk_levels +ffffffff822e08b0 t arcturus_get_power_profile_mode +ffffffff822e0b40 t arcturus_set_power_profile_mode +ffffffff822e0e30 t arcturus_dpm_set_vcn_enable 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navi10_print_clk_levels +ffffffff822e5b20 t navi10_emit_clk_levels +ffffffff822e5d60 t navi10_force_clk_levels +ffffffff822e5e90 t navi10_od_edit_dpm_table +ffffffff822e6510 t navi10_get_clock_by_type_with_latency +ffffffff822e6610 t navi10_get_power_profile_mode +ffffffff822e6860 t navi10_set_power_profile_mode +ffffffff822e6b30 t navi10_dpm_set_vcn_enable +ffffffff822e6bc0 t navi10_dpm_set_jpeg_enable +ffffffff822e6c40 t navi10_read_sensor +ffffffff822e6dc0 t navi10_pre_display_config_changed +ffffffff822e6e60 t navi10_display_config_changed +ffffffff822e6ee0 t navi10_notify_smc_display_config +ffffffff822e7070 t navi10_is_dpm_running +ffffffff822e70c0 t navi10_get_fan_speed_rpm +ffffffff822e7160 t navi10_set_watermarks_table +ffffffff822e7310 t navi10_get_thermal_temperature_range +ffffffff822e7400 t navi10_get_uclk_dpm_states +ffffffff822e7510 t navi10_set_default_od_settings +ffffffff822e7770 t navi10_display_disable_memory_clock_switch +ffffffff822e77f0 t navi10_get_power_limit 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sienna_cichlid_set_default_dpm_table +ffffffff822ea920 t sienna_cichlid_populate_umd_state_clk +ffffffff822ea9e0 t sienna_cichlid_print_clk_levels +ffffffff822eabc0 t sienna_cichlid_force_clk_levels +ffffffff822eacf0 t sienna_cichlid_od_edit_dpm_table +ffffffff822eb290 t sienna_cichlid_restore_user_od_settings +ffffffff822eb320 t sienna_cichlid_get_power_profile_mode +ffffffff822eb570 t sienna_cichlid_set_power_profile_mode +ffffffff822eb840 t sienna_cichlid_dpm_set_vcn_enable +ffffffff822eb900 t sienna_cichlid_dpm_set_jpeg_enable +ffffffff822eb980 t sienna_cichlid_read_sensor +ffffffff822ebc80 t sienna_cichlid_pre_display_config_changed +ffffffff822ebcb0 t sienna_cichlid_display_config_changed +ffffffff822ebd10 t sienna_cichlid_notify_smc_display_config +ffffffff822ebea0 t sienna_cichlid_is_dpm_running +ffffffff822ebef0 t sienna_cichlid_get_fan_speed_rpm +ffffffff822ec000 t sienna_cichlid_set_watermarks_table +ffffffff822ec1a0 t sienna_cichlid_get_thermal_temperature_range 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sienna_cichlid_get_dpm_ultimate_freq +ffffffff822ed690 t sienna_cichlid_get_gpu_metrics +ffffffff822edb10 t sienna_cichlid_enable_mgpu_fan_boost +ffffffff822edb60 t sienna_cichlid_get_fan_parameters +ffffffff822edba0 t sienna_cichlid_gpo_control +ffffffff822edc50 t sienna_cichlid_get_ecc_info +ffffffff822edd40 t sienna_cichlid_stb_get_data_direct +ffffffff822edde0 t sienna_cichlid_get_default_config_table_settings +ffffffff822ede50 t sienna_cichlid_set_config_table +ffffffff822edf20 t sienna_cichlid_get_smu_metrics_data +ffffffff822ee360 t sienna_cichlid_get_throttler_status_locked +ffffffff822ee4e0 t sienna_cichlid_get_smartshift_power_percentage +ffffffff822ee610 t sienna_cichlid_i2c_xfer +ffffffff822ee8c0 t sienna_cichlid_i2c_func +ffffffff822ef000 T smu_v11_0_init_microcode +ffffffff822ef2b0 T smu_v11_0_fini_microcode +ffffffff822ef330 T smu_v11_0_load_microcode +ffffffff822ef480 T smu_v11_0_check_fw_status +ffffffff822ef4d0 T smu_v11_0_check_fw_version +ffffffff822ef680 T smu_v11_0_setup_pptable +ffffffff822ef7b0 T smu_v11_0_init_smc_tables +ffffffff822ef910 T smu_v11_0_fini_smc_tables +ffffffff822efb40 T smu_v11_0_init_power +ffffffff822efbd0 T smu_v11_0_fini_power +ffffffff822efc30 T smu_v11_0_get_vbios_bootup_values +ffffffff822eff90 T smu_v11_0_notify_memory_pool_location +ffffffff822f0080 T smu_v11_0_set_min_deep_sleep_dcefclk +ffffffff822f0100 T smu_v11_0_set_driver_table_location +ffffffff822f0170 T smu_v11_0_set_tool_table_location +ffffffff822f01e0 T smu_v11_0_init_display_count +ffffffff822f0240 T smu_v11_0_set_allowed_mask +ffffffff822f0310 T smu_v11_0_system_features_control +ffffffff822f0330 T smu_v11_0_notify_display_change +ffffffff822f03a0 T smu_v11_0_init_max_sustainable_clocks +ffffffff822f0610 t smu_v11_0_get_max_sustainable_clock +ffffffff822f0730 T smu_v11_0_get_current_power_limit +ffffffff822f0800 T smu_v11_0_set_power_limit +ffffffff822f0940 T smu_v11_0_interrupt_work +ffffffff822f09c0 T smu_v11_0_enable_thermal_alert +ffffffff822f0a60 T smu_v11_0_disable_thermal_alert +ffffffff822f0a80 T smu_v11_0_get_gfx_vdd +ffffffff822f0b40 T smu_v11_0_display_clock_voltage_request +ffffffff822f0c80 T smu_v11_0_set_hard_freq_limited_range +ffffffff822f0d60 T smu_v11_0_gfx_off_control +ffffffff822f0dd0 T smu_v11_0_get_fan_control_mode +ffffffff822f0e20 T smu_v11_0_set_fan_speed_pwm +ffffffff822f0fc0 t smu_v11_0_set_fan_static_mode +ffffffff822f1170 T smu_v11_0_set_fan_speed_rpm +ffffffff822f1290 T smu_v11_0_get_fan_speed_pwm +ffffffff822f13d0 T smu_v11_0_get_fan_speed_rpm +ffffffff822f14d0 T smu_v11_0_set_fan_control_mode +ffffffff822f1670 T smu_v11_0_set_xgmi_pstate +ffffffff822f1690 T smu_v11_0_register_irq_handler +ffffffff822f1750 T smu_v11_0_get_max_sustainable_clocks_by_dc +ffffffff822f17e0 T smu_v11_0_set_azalia_d3_pme +ffffffff822f1800 T smu_v11_0_baco_set_armd3_sequence +ffffffff822f1820 T smu_v11_0_baco_is_support +ffffffff822f18b0 T smu_v11_0_baco_get_state +ffffffff822f18e0 T smu_v11_0_baco_set_state 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T smu_v11_0_set_smu_mailbox_registers +ffffffff822f2ca0 t smu_v11_0_set_irq_state +ffffffff822f3220 t smu_v11_0_irq_process +ffffffff822f3520 t orderly_poweroff +ffffffff822f4000 T vangogh_set_ppt_funcs +ffffffff822f4040 t vangogh_set_default_dpm_tables +ffffffff822f4070 t vangogh_common_print_clk_levels +ffffffff822f44c0 t vangogh_force_clk_levels +ffffffff822f46f0 t vangogh_od_edit_dpm_table +ffffffff822f4c50 t vangogh_get_power_profile_mode +ffffffff822f4d20 t vangogh_set_power_profile_mode +ffffffff822f4e50 t vangogh_dpm_set_vcn_enable +ffffffff822f4ea0 t vangogh_dpm_set_jpeg_enable +ffffffff822f4ef0 t vangogh_read_sensor +ffffffff822f5020 t vangogh_is_dpm_running +ffffffff822f5080 t vangogh_set_watermarks_table +ffffffff822f5210 t vangogh_set_performance_level +ffffffff822f5b40 t vangogh_get_power_limit +ffffffff822f5cc0 t vangogh_get_ppt_limit +ffffffff822f5d30 t vangogh_get_dpm_clock_table +ffffffff822f5ea0 t vangogh_init_smc_tables +ffffffff822f60f0 t vangogh_system_features_control +ffffffff822f6140 t vangogh_set_power_limit +ffffffff822f62a0 t vangogh_get_gfxoff_status +ffffffff822f6330 t vangogh_get_gfxoff_entrycount +ffffffff822f63a0 t vangogh_set_gfxoff_residency +ffffffff822f6410 t vangogh_get_gfxoff_residency +ffffffff822f6450 t vangogh_mode2_reset +ffffffff822f6590 t vangogh_common_get_gpu_metrics +ffffffff822f6be0 t vangogh_post_smu_init +ffffffff822f6d90 t vangogh_set_fine_grain_gfx_freq_parameters +ffffffff822f6e00 t vangogh_common_get_smu_metrics_data +ffffffff822f7150 t vangogh_force_dpm_limit_value +ffffffff822f7290 t vangogh_get_dpm_ultimate_freq +ffffffff822f7650 t vangogh_set_soft_freq_limited_range +ffffffff822f8000 T renoir_set_ppt_funcs +ffffffff822f80a0 t renoir_get_current_power_state +ffffffff822f8120 t renoir_print_clk_levels +ffffffff822f8390 t renoir_force_clk_levels +ffffffff822f85c0 t renoir_od_edit_dpm_table +ffffffff822f88c0 t renoir_get_power_profile_mode +ffffffff822f8990 t renoir_set_power_profile_mode +ffffffff822f8ac0 t renoir_dpm_set_vcn_enable +ffffffff822f8b40 t renoir_dpm_set_jpeg_enable +ffffffff822f8bc0 t renoir_read_sensor +ffffffff822f8fb0 t renoir_is_dpm_running +ffffffff822f8ff0 t renoir_set_watermarks_table +ffffffff822f91a0 t renoir_set_performance_level +ffffffff822f96e0 t renoir_get_dpm_clock_table +ffffffff822f9a30 t renoir_init_smc_tables +ffffffff822f9ba0 t renoir_get_enabled_mask +ffffffff822f9be0 t renoir_get_dpm_ultimate_freq +ffffffff822f9e80 t renoir_get_gpu_metrics +ffffffff822fa0a0 t renoir_gfx_state_change_set +ffffffff822fa0d0 t renoir_set_fine_grain_gfx_freq_parameters +ffffffff822fa170 t renoir_force_dpm_limit_value +ffffffff822fb000 T smu_v12_0_check_fw_status +ffffffff822fb050 T smu_v12_0_check_fw_version +ffffffff822fb110 T smu_v12_0_powergate_sdma +ffffffff822fb150 T smu_v12_0_set_gfx_cgpg +ffffffff822fb1b0 T smu_v12_0_get_gfxoff_status +ffffffff822fb240 T smu_v12_0_gfx_off_control +ffffffff822fb360 T smu_v12_0_fini_smc_tables +ffffffff822fb410 T smu_v12_0_set_default_dpm_tables +ffffffff822fb440 T smu_v12_0_mode2_reset +ffffffff822fb460 T smu_v12_0_set_soft_freq_limited_range +ffffffff822fb5a0 T smu_v12_0_set_driver_table_location +ffffffff822fb610 T smu_v12_0_get_vbios_bootup_values +ffffffff822fc000 T aldebaran_set_ppt_funcs +ffffffff822fc040 t aldebaran_get_allowed_feature_mask +ffffffff822fc090 t aldebaran_set_default_dpm_table +ffffffff822fc290 t aldebaran_populate_umd_state_clk +ffffffff822fc390 t aldebaran_print_clk_levels +ffffffff822fc550 t aldebaran_force_clk_levels +ffffffff822fc700 t aldebaran_usr_edit_dpm_table +ffffffff822fc920 t aldebaran_read_sensor +ffffffff822fcbc0 t aldebaran_is_dpm_running +ffffffff822fcc10 t aldebaran_get_thermal_temperature_range +ffffffff822fcce0 t aldebaran_set_performance_level +ffffffff822fcd90 t aldebaran_get_power_limit +ffffffff822fcf20 t aldebaran_set_df_cstate +ffffffff822fcfa0 t aldebaran_allow_xgmi_power_down +ffffffff822fd040 t aldebaran_i2c_control_init +ffffffff822fd100 t aldebaran_i2c_control_fini +ffffffff822fd140 t aldebaran_get_unique_id +ffffffff822fd220 t aldebaran_init_smc_tables +ffffffff822fd3b0 t aldebaran_set_mp1_state +ffffffff822fd3f0 t aldebaran_setup_pptable +ffffffff822fd4c0 t aldebaran_system_features_control +ffffffff822fd620 t aldebaran_set_power_limit +ffffffff822fd6b0 t aldebaran_is_baco_supported +ffffffff822fd6e0 t aldebaran_is_mode1_reset_supported +ffffffff822fd710 t aldebaran_is_mode2_reset_supported +ffffffff822fd740 t aldebaran_mode1_reset +ffffffff822fd820 t aldebaran_mode2_reset +ffffffff822fd9e0 t aldebaran_set_soft_freq_limited_range +ffffffff822fdbf0 t aldebaran_log_thermal_throttling_event +ffffffff822fdf00 t aldebaran_get_gpu_metrics +ffffffff822fe190 t aldebaran_smu_handle_passthrough_sbr +ffffffff822fe1b0 t aldebaran_smu_send_hbm_bad_page_num +ffffffff822fe240 t aldebaran_get_ecc_info +ffffffff822fe3a0 t aldebaran_send_hbm_bad_channel_flag +ffffffff822fe480 t aldebaran_get_current_clk_freq_by_table +ffffffff822fe5c0 t aldebaran_get_smu_metrics_data +ffffffff822fe810 t aldebaran_upload_dpm_level +ffffffff822fe900 t aldebaran_i2c_xfer +ffffffff822febb0 t aldebaran_i2c_func +ffffffff822ff000 T smu_v13_0_init_microcode +ffffffff822ff1d0 T smu_v13_0_fini_microcode +ffffffff822ff250 T smu_v13_0_load_microcode +ffffffff822ff280 T smu_v13_0_init_pptable_microcode +ffffffff822ff430 T smu_v13_0_get_pptable_from_firmware +ffffffff822ff560 T smu_v13_0_check_fw_status +ffffffff822ff5d0 T smu_v13_0_check_fw_version +ffffffff822ff700 T smu_v13_0_setup_pptable +ffffffff822ff8a0 T smu_v13_0_init_smc_tables +ffffffff822ff9f0 T smu_v13_0_fini_smc_tables +ffffffff822ffbe0 T smu_v13_0_init_power +ffffffff822ffc60 T smu_v13_0_fini_power +ffffffff822ffce0 T smu_v13_0_get_vbios_bootup_values +ffffffff822fff90 T smu_v13_0_notify_memory_pool_location +ffffffff82300050 T smu_v13_0_set_min_deep_sleep_dcefclk +ffffffff823000d0 T smu_v13_0_set_driver_table_location +ffffffff82300140 T smu_v13_0_set_tool_table_location +ffffffff823001b0 T smu_v13_0_init_display_count +ffffffff823001f0 T smu_v13_0_set_allowed_mask +ffffffff823002c0 T smu_v13_0_gfx_off_control +ffffffff82300330 T smu_v13_0_system_features_control +ffffffff82300350 T smu_v13_0_notify_display_change +ffffffff823003c0 T smu_v13_0_init_max_sustainable_clocks +ffffffff82300630 t smu_v13_0_get_max_sustainable_clock +ffffffff82300750 T smu_v13_0_get_current_power_limit +ffffffff82300820 T smu_v13_0_set_power_limit +ffffffff82300940 T smu_v13_0_enable_thermal_alert +ffffffff823009d0 T smu_v13_0_disable_thermal_alert +ffffffff82300a10 T smu_v13_0_get_gfx_vdd +ffffffff82300ad0 T smu_v13_0_display_clock_voltage_request +ffffffff82300c10 T smu_v13_0_set_hard_freq_limited_range +ffffffff82300cf0 T smu_v13_0_get_fan_control_mode +ffffffff82300d40 T smu_v13_0_set_fan_speed_pwm +ffffffff82300f50 t smu_v13_0_set_fan_static_mode +ffffffff82301110 T smu_v13_0_set_fan_control_mode +ffffffff82301270 T smu_v13_0_set_fan_speed_rpm +ffffffff82301410 T smu_v13_0_set_xgmi_pstate +ffffffff82301430 T smu_v13_0_register_irq_handler +ffffffff82301500 T smu_v13_0_get_max_sustainable_clocks_by_dc +ffffffff82301590 T smu_v13_0_set_azalia_d3_pme +ffffffff823015b0 T smu_v13_0_wait_for_event +ffffffff82301610 T smu_v13_0_get_dpm_ultimate_freq +ffffffff82301770 T smu_v13_0_set_soft_freq_limited_range +ffffffff82301850 T smu_v13_0_set_performance_level +ffffffff82301fe0 T smu_v13_0_set_power_source +ffffffff82302040 T smu_v13_0_set_single_dpm_table +ffffffff823022d0 T smu_v13_0_get_dpm_level_range +ffffffff82302450 T smu_v13_0_get_current_pcie_link_width_level +ffffffff823024a0 T smu_v13_0_get_current_pcie_link_width +ffffffff82302500 T smu_v13_0_get_current_pcie_link_speed_level +ffffffff82302550 T smu_v13_0_get_current_pcie_link_speed +ffffffff823025a0 T smu_v13_0_set_vcn_enable +ffffffff82302650 T smu_v13_0_set_jpeg_enable +ffffffff82302670 T smu_v13_0_run_btc +ffffffff823026f0 T smu_v13_0_gpo_control +ffffffff82302780 T smu_v13_0_deep_sleep_control +ffffffff823029f0 T smu_v13_0_gfx_ulv_control +ffffffff82302a60 T smu_v13_0_baco_set_armd3_sequence +ffffffff82302a80 T smu_v13_0_baco_is_support +ffffffff82302b10 T smu_v13_0_baco_get_state +ffffffff82302b40 T smu_v13_0_baco_set_state +ffffffff82302c00 T smu_v13_0_baco_enter +ffffffff82302d10 T smu_v13_0_baco_exit +ffffffff82302db0 T smu_v13_0_set_gfx_power_up_by_imu +ffffffff82302df0 T smu_v13_0_od_edit_dpm_table +ffffffff823030b0 T smu_v13_0_set_default_dpm_tables +ffffffff823030e0 T smu_v13_0_set_smu_mailbox_registers +ffffffff82303150 T smu_v13_0_mode1_reset +ffffffff823031d0 t smu_v13_0_set_irq_state +ffffffff82303750 t smu_v13_0_irq_process +ffffffff82303a50 t orderly_poweroff +ffffffff82304000 T smu_v13_0_0_set_ppt_funcs +ffffffff823040e0 t smu_v13_0_0_get_allowed_feature_mask +ffffffff82304220 t smu_v13_0_0_set_default_dpm_table +ffffffff82304650 t smu_v13_0_0_populate_umd_state_clk +ffffffff82304780 t smu_v13_0_0_print_clk_levels +ffffffff823048a0 t smu_v13_0_0_force_clk_levels +ffffffff82304a20 t smu_v13_0_0_get_power_profile_mode +ffffffff82304c70 t smu_v13_0_0_set_power_profile_mode +ffffffff82304ec0 t smu_v13_0_0_read_sensor +ffffffff823050e0 t smu_v13_0_0_is_dpm_running +ffffffff82305130 t smu_v13_0_0_get_fan_speed_pwm +ffffffff82305210 t smu_v13_0_0_get_fan_speed_rpm +ffffffff82305280 t smu_v13_0_0_get_thermal_temperature_range +ffffffff82305380 t smu_v13_0_0_dump_pptable +ffffffff823053b0 t smu_v13_0_0_get_power_limit +ffffffff82305490 t smu_v13_0_0_set_df_cstate +ffffffff823054b0 t smu_v13_0_0_update_pcie_parameters +ffffffff823055a0 t smu_v13_0_0_i2c_control_init +ffffffff823056d0 t smu_v13_0_0_i2c_control_fini +ffffffff82305710 t smu_v13_0_0_get_unique_id +ffffffff823057c0 t smu_v13_0_0_init_smc_tables +ffffffff823059b0 t smu_v13_0_0_set_mp1_state +ffffffff823059f0 t smu_v13_0_0_setup_pptable +ffffffff82305b30 t smu_v13_0_0_system_features_control +ffffffff82305b40 t smu_v13_0_0_baco_enter +ffffffff82305b90 t smu_v13_0_0_baco_exit +ffffffff82305bf0 t smu_v13_0_0_is_mode1_reset_supported +ffffffff82305c50 t smu_v13_0_0_mode1_reset +ffffffff82305ce0 t smu_v13_0_0_get_dpm_ultimate_freq +ffffffff82305e00 t smu_v13_0_0_get_gpu_metrics +ffffffff82306230 t smu_v13_0_0_enable_mgpu_fan_boost +ffffffff82306280 t smu_v13_0_0_smu_send_bad_mem_page_num +ffffffff82306310 t smu_v13_0_0_send_bad_mem_channel_flag +ffffffff823063a0 t smu_v13_0_0_get_smu_metrics_data +ffffffff82306710 t smu_v13_0_get_throttler_status +ffffffff823068d0 t smu_v13_0_0_i2c_xfer +ffffffff82306b80 t smu_v13_0_0_i2c_func +ffffffff82307000 T smu_v13_0_4_set_ppt_funcs +ffffffff823070b0 t smu_v13_0_4_print_clk_levels +ffffffff82307170 t smu_v13_0_4_force_clk_levels +ffffffff82307410 t smu_v13_0_4_read_sensor +ffffffff823076c0 t smu_v13_0_4_is_dpm_running +ffffffff82307710 t smu_v13_0_4_set_watermarks_table +ffffffff823078a0 t smu_v13_0_4_set_performance_level +ffffffff82307de0 t smu_v13_0_4_init_smc_tables +ffffffff82307f50 t smu_v13_0_4_fini_smc_tables +ffffffff82308000 t smu_v13_0_4_system_features_control +ffffffff82308050 t smu_v13_0_4_mode2_reset +ffffffff82308070 t smu_v13_0_4_get_dpm_ultimate_freq +ffffffff82308490 t smu_v13_0_4_get_gpu_metrics +ffffffff82308660 t smu_v13_0_4_set_fine_grain_gfx_freq_parameters +ffffffff823086c0 t smu_v13_0_4_get_smu_metrics_data +ffffffff82309000 T smu_v13_0_5_set_ppt_funcs +ffffffff82309090 t smu_v13_0_5_set_default_dpm_tables +ffffffff823090c0 t smu_v13_0_5_print_clk_levels +ffffffff82309170 t smu_v13_0_5_force_clk_levels +ffffffff823092d0 t smu_v13_0_5_od_edit_dpm_table +ffffffff82309590 t smu_v13_0_5_dpm_set_vcn_enable +ffffffff823095b0 t smu_v13_0_5_dpm_set_jpeg_enable +ffffffff823095d0 t smu_v13_0_5_read_sensor +ffffffff823097f0 t smu_v13_0_5_is_dpm_running +ffffffff82309840 t smu_v13_0_5_set_watermarks_table +ffffffff823099d0 t smu_v13_0_5_set_performance_level +ffffffff82309bb0 t smu_v13_0_5_init_smc_tables +ffffffff82309d20 t smu_v13_0_5_fini_smc_tables +ffffffff82309dd0 t smu_v13_0_5_system_features_control +ffffffff82309e20 t smu_v13_0_5_mode2_reset +ffffffff82309ea0 t smu_v13_0_5_get_dpm_ultimate_freq +ffffffff8230a2e0 t smu_v13_0_5_get_gpu_metrics +ffffffff8230a420 t smu_v13_0_5_set_fine_grain_gfx_freq_parameters +ffffffff8230a480 t smu_v13_0_5_get_smu_metrics_data +ffffffff8230b000 T smu_v13_0_7_set_ppt_funcs +ffffffff8230b050 t smu_v13_0_7_get_allowed_feature_mask +ffffffff8230b1c0 t smu_v13_0_7_set_default_dpm_table +ffffffff8230b5f0 t smu_v13_0_7_populate_umd_state_clk +ffffffff8230b720 t smu_v13_0_7_print_clk_levels +ffffffff8230b840 t smu_v13_0_7_force_clk_levels +ffffffff8230b9c0 t smu_v13_0_7_get_power_profile_mode +ffffffff8230bca0 t smu_v13_0_7_set_power_profile_mode +ffffffff8230bee0 t smu_v13_0_7_read_sensor +ffffffff8230c0f0 t smu_v13_0_7_is_dpm_running +ffffffff8230c140 t smu_v13_0_7_get_fan_speed_pwm +ffffffff8230c220 t smu_v13_0_7_get_fan_speed_rpm +ffffffff8230c290 t smu_v13_0_7_get_thermal_temperature_range +ffffffff8230c380 t smu_v13_0_7_dump_pptable +ffffffff8230c3b0 t smu_v13_0_7_get_power_limit +ffffffff8230c490 t smu_v13_0_7_set_df_cstate +ffffffff8230c4b0 t smu_v13_0_7_update_pcie_parameters +ffffffff8230c5a0 t smu_v13_0_7_init_smc_tables +ffffffff8230c790 t smu_v13_0_7_check_fw_status +ffffffff8230c7e0 t smu_v13_0_7_set_mp1_state +ffffffff8230c820 t smu_v13_0_7_setup_pptable +ffffffff8230c980 t smu_v13_0_7_baco_enter +ffffffff8230c9d0 t smu_v13_0_7_baco_exit +ffffffff8230ca30 t smu_v13_0_7_is_mode1_reset_supported +ffffffff8230ca70 t smu_v13_0_7_get_dpm_ultimate_freq +ffffffff8230cb90 t smu_v13_0_7_get_gpu_metrics +ffffffff8230cfa0 t smu_v13_0_7_enable_mgpu_fan_boost +ffffffff8230cff0 t smu_v13_0_7_get_smu_metrics_data +ffffffff8230d340 t smu_v13_0_7_get_throttler_status +ffffffff8230e000 T yellow_carp_set_ppt_funcs +ffffffff8230e040 t yellow_carp_set_default_dpm_tables +ffffffff8230e070 t yellow_carp_print_clk_levels +ffffffff8230e130 t yellow_carp_force_clk_levels +ffffffff8230e3d0 t yellow_carp_od_edit_dpm_table +ffffffff8230e690 t yellow_carp_dpm_set_vcn_enable +ffffffff8230e6b0 t yellow_carp_dpm_set_jpeg_enable +ffffffff8230e6d0 t yellow_carp_read_sensor +ffffffff8230ea70 t yellow_carp_is_dpm_running +ffffffff8230eac0 t yellow_carp_set_watermarks_table +ffffffff8230ec50 t yellow_carp_set_performance_level +ffffffff8230f190 t yellow_carp_init_smc_tables +ffffffff8230f300 t yellow_carp_fini_smc_tables +ffffffff8230f3b0 t yellow_carp_system_features_control +ffffffff8230f400 t yellow_carp_get_gfxoff_status +ffffffff8230f490 t yellow_carp_mode2_reset +ffffffff8230f510 t yellow_carp_get_dpm_ultimate_freq +ffffffff8230f960 t yellow_carp_get_gpu_metrics +ffffffff8230fb20 t yellow_carp_post_smu_init +ffffffff8230fba0 t yellow_carp_set_fine_grain_gfx_freq_parameters +ffffffff8230fc00 t yellow_carp_get_smu_metrics_data +ffffffff82310000 T smu_cmn_send_msg_without_waiting +ffffffff82310170 T smu_cmn_wait_for_response +ffffffff823102b0 T smu_cmn_send_smc_msg_with_param +ffffffff823105d0 T smu_cmn_to_asic_specific_index +ffffffff823106e0 t __smu_cmn_reg_print_error +ffffffff82310930 T smu_cmn_send_smc_msg +ffffffff82310950 T smu_cmn_send_debug_smc_msg +ffffffff823109d0 T smu_cmn_feature_is_supported +ffffffff82310a80 T smu_cmn_feature_is_enabled +ffffffff82310b80 T smu_cmn_clk_dpm_is_enabled +ffffffff82310c80 T smu_cmn_get_enabled_mask +ffffffff82310d70 T smu_cmn_get_indep_throttler_status +ffffffff82310e20 T smu_cmn_feature_update_enable_state +ffffffff82310ec0 T smu_cmn_feature_set_enabled +ffffffff82310f90 T smu_cmn_get_pp_feature_mask +ffffffff82311140 T smu_cmn_set_pp_feature_mask +ffffffff82311240 T smu_cmn_disable_all_features_with_exception +ffffffff823112f0 T smu_cmn_get_smc_version +ffffffff823113c0 T smu_cmn_update_table +ffffffff82311520 T smu_cmn_write_watermarks_table +ffffffff823115f0 T smu_cmn_write_pptable +ffffffff823116b0 T smu_cmn_get_metrics_table +ffffffff82311810 T smu_cmn_get_combo_pptable +ffffffff823118e0 T smu_cmn_init_soft_gpu_metrics +ffffffff823119c0 T smu_cmn_set_mp1_state +ffffffff82311a60 T smu_cmn_is_audio_func_enabled +ffffffff82312000 T pci_mcfg_init +ffffffff82312050 T pci_lookup_segment +ffffffff823120b0 T pci_attach_hook +ffffffff823120e0 T pci_bus_maxdevs +ffffffff82312110 T pci_make_tag +ffffffff82312180 T pci_decompose_tag +ffffffff823121e0 T pci_conf_size +ffffffff82312240 T pci_mcfg_map_bus +ffffffff823122c0 T pci_conf_read +ffffffff82312410 T pci_conf_write +ffffffff82312550 T pci_msix_table_map +ffffffff82312670 T pci_msix_table_unmap +ffffffff82312710 T msi_hwmask +ffffffff82312740 T msi_hwunmask +ffffffff82312770 T msi_addroute +ffffffff82312870 T msi_delroute +ffffffff823128e0 T pci_intr_map_msi +ffffffff82312960 T msix_hwmask +ffffffff82312990 T msix_hwunmask +ffffffff823129c0 T msix_addroute +ffffffff82312bc0 T msix_delroute +ffffffff82312d20 T pci_intr_map_msix +ffffffff82312df0 T pci_intr_map +ffffffff82313010 T pci_intr_string +ffffffff823130f0 T pci_intr_establish +ffffffff82313140 T pci_intr_establish_cpu +ffffffff823132a0 T pci_intr_disestablish +ffffffff823132c0 T pci_init_extents +ffffffff823134a0 T pci_probe_device_hook +ffffffff823134e0 T pci_dev_postattach +ffffffff823134f0 T pci_min_powerstate +ffffffff82313500 T pci_set_powerstate_md +ffffffff82314000 T pciide_machdep_compat_intr_establish +ffffffff82314060 T pciide_machdep_compat_intr_disestablish +ffffffff82315000 T vga_post_init +ffffffff82315310 t vm86_emu_inb +ffffffff82315360 t vm86_emu_inw +ffffffff823153a0 t vm86_emu_inl +ffffffff823153e0 t vm86_emu_outb +ffffffff82315430 t vm86_emu_outw +ffffffff82315470 t vm86_emu_outl +ffffffff823154b0 T vga_post_call +ffffffff82315520 T vga_post_free +ffffffff82315590 T ddb_vgapost +ffffffff82316000 T pchbmatch +ffffffff82316040 T pchbattach +ffffffff823164b0 T pchbactivate +ffffffff82316520 T pchb_amd64ht_attach +ffffffff82316670 T pchb_rnd +ffffffff823166f0 T pchb_print +ffffffff82317000 T amas_match +ffffffff82317050 T amas_attach +ffffffff823170b0 T amas_intl_nodes +ffffffff82317140 T amas_get_pagerange +ffffffff82318000 T agp_flush_cache +ffffffff82318030 T agp_flush_cache_range +ffffffff82318040 T agp_init_map +ffffffff82318110 T agp_destroy_map +ffffffff82318150 T agp_map_subregion +ffffffff82318180 T agp_unmap_subregion +ffffffff823181b0 T agp_map_atomic +ffffffff823181e0 T agp_unmap_atomic +ffffffff82319000 T cardslotmatch +ffffffff82319050 T cardslotattach +ffffffff823192a0 T cardslot_event +ffffffff82319300 T cardslot_cb_print +ffffffff82319350 T cardslot_16_print +ffffffff823193a0 T cardslot_16_submatch +ffffffff823193f0 T cardslot_event_throw +ffffffff82319490 T cardslot_process_event +ffffffff8231a000 T cardbusmatch +ffffffff8231a050 T cardbusattach +ffffffff8231a130 T cardbus_read_tuples +ffffffff8231a4e0 T parse_tuple +ffffffff8231a760 T cardbus_attach_card +ffffffff8231aee0 T enable_function +ffffffff8231af80 T decode_tuples +ffffffff8231b050 T cardbusprint +ffffffff8231b140 T cardbussubmatch +ffffffff8231b1a0 T disable_function +ffffffff8231b200 T cardbus_detach_card +ffffffff8231b2e0 T cardbus_intr_establish +ffffffff8231b310 T cardbus_intr_disestablish +ffffffff8231b330 T cardbus_function_enable +ffffffff8231b410 T cardbus_function_disable +ffffffff8231b470 T cardbus_matchbyid +ffffffff8231b4e0 T decode_tuple +ffffffff8231c000 T cardbus_mapreg_map +ffffffff8231c1b0 T cardbus_mapreg_unmap +ffffffff8231d000 T cardbus_read_exrom +ffffffff8231e000 T rbus_space_alloc +ffffffff8231e060 T rbus_space_alloc_subregion +ffffffff8231e240 T rbus_space_free +ffffffff8231e2d0 T rbus_new_body +ffffffff8231e360 T rbus_new_root_delegate +ffffffff8231e430 T rbus_new_root_share +ffffffff8231f000 T com_cardbus_match +ffffffff8231f070 T com_cardbus_attach +ffffffff8231f220 T com_cardbus_detach +ffffffff8231f2c0 T com_cardbus_find_csdev +ffffffff8231f440 T com_cardbus_gofigure +ffffffff8231f900 T com_cardbus_enable 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rbus_pccbb_parent_mem +ffffffff82331060 T rbus_pccbb_parent_io +ffffffff823310d0 T pccbb_attach_hook +ffffffff82332000 T pcmcia_match +ffffffff82332050 T pcmcia_attach +ffffffff823320d0 T pcmcia_activate +ffffffff82332180 T pcmcia_ccr_read +ffffffff823321d0 T pcmcia_ccr_write +ffffffff82332240 T pcmcia_card_attach +ffffffff82332450 T pcmcia_print +ffffffff823326b0 T pcmcia_submatch +ffffffff82332700 T pcmcia_card_detach +ffffffff823327b0 T pcmcia_card_deactivate +ffffffff82332820 T pcmcia_card_gettype +ffffffff82332880 T pcmcia_function_init +ffffffff823328d0 T pcmcia_function_enable +ffffffff82332d00 T pcmcia_function_disable +ffffffff82332e20 T pcmcia_io_map +ffffffff82333060 T pcmcia_intr_establish +ffffffff823332d0 T pcmcia_card_intr +ffffffff823333f0 T pcmcia_intr_disestablish +ffffffff82333610 T pcmcia_intr_string +ffffffff82334000 T pcmcia_cis_read_1 +ffffffff823340f0 T pcmcia_read_cis +ffffffff823341e0 T pcmcia_scan_cis +ffffffff82335cc0 T pcmcia_parse_cis_tuple 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lm_isa_match +ffffffff823641b0 T lm_isa_attach +ffffffff82364380 T lm_wbsio_match +ffffffff82364540 T lm_isa_writereg +ffffffff823645a0 T lm_isa_readreg +ffffffff82364600 T lm_isa_remove_alias +ffffffff82365000 T it_match +ffffffff823652d0 T it_enter +ffffffff82365360 T it_readreg +ffffffff823653a0 T it_writereg +ffffffff823653f0 T it_exit +ffffffff82365440 T it_attach +ffffffff82365aa0 T it_wdog_cb +ffffffff82365d40 T it_ec_refresh +ffffffff82366360 T it_ec_writereg +ffffffff823663b0 T it_ec_readreg +ffffffff82366400 T it_activate +ffffffff82367000 T uguru_refresh_temp +ffffffff823670d0 T uguru_refresh_volt +ffffffff82367180 T uguru_refresh_fan +ffffffff82367250 T uguru_match +ffffffff823673e0 T uguru_attach +ffffffff82367970 T uguru_read_multi +ffffffff82367a50 T uguru_ac5_read +ffffffff82367cc0 T uguru_read_sensor +ffffffff82367fe0 T uguru_ac5_read_sensor +ffffffff82368070 T uguru_refresh +ffffffff82368100 T uguru_write_multi +ffffffff82369000 T aps_match +ffffffff82369100 T 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hid_is_collection +ffffffff8239c000 T hidkbd_attach +ffffffff8239c0f0 T hidkbd_parse_desc +ffffffff8239c460 T hidkbd_delayed_decode +ffffffff8239c480 T hidkbd_attach_wskbd +ffffffff8239c510 T hidkbd_detach +ffffffff8239c5b0 T hidkbd_translate +ffffffff8239c600 T hidkbd_apple_translate +ffffffff8239c690 T hidkbd_apple_munge +ffffffff8239c7f0 T hidkbd_apple_tb_munge +ffffffff8239c9d0 T hidkbd_apple_iso_munge +ffffffff8239cc10 T hidkbd_apple_mba_munge +ffffffff8239cd70 T hidkbd_apple_iso_mba_munge +ffffffff8239cfb0 T hidkbd_input +ffffffff8239d0b0 T hidkbd_decode +ffffffff8239d420 T hidkbd_enable +ffffffff8239d460 T hidkbd_set_leds +ffffffff8239d540 T hidkbd_ioctl +ffffffff8239d5e0 T hidkbd_bell +ffffffff8239d630 T hidkbd_cngetc +ffffffff8239d6c0 T hidkbd_hookup_bell +ffffffff8239e000 T hidms_setup +ffffffff8239e5c0 T hidms_attach +ffffffff8239e710 T hidms_detach +ffffffff8239e750 T hidms_input +ffffffff8239ea00 T hidms_enable +ffffffff8239ea40 T hidms_ioctl +ffffffff8239ec10 T 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usbd_interface2endpoint_descriptor +ffffffff823a52c0 T usbd_clear_endpoint_stall +ffffffff823a5350 T usbd_clear_endpoint_toggle +ffffffff823a5390 T usbd_do_request +ffffffff823a53b0 T usbd_clear_endpoint_stall_async +ffffffff823a5470 T usbd_request_async +ffffffff823a5580 T usbd_device2interface_handle +ffffffff823a5610 T usbd_set_interface +ffffffff823a56f0 T usbd_get_no_alts +ffffffff823a5760 T usbd_get_interface_altindex +ffffffff823a5790 T usbd_start_next +ffffffff823a5860 T usb_insert_transfer +ffffffff823a5910 T usbd_do_request_flags +ffffffff823a5b90 T usbd_request_async_cb +ffffffff823a5c10 T usbd_get_quirks +ffffffff823a5c60 T usbd_set_polling +ffffffff823a5cc0 T usbd_get_endpoint_descriptor +ffffffff823a5d20 T usbd_ratecheck +ffffffff823a5d40 T usbd_match_device +ffffffff823a5db0 T usbd_desc_iter_init +ffffffff823a5e20 T usbd_desc_iter_next +ffffffff823a5ea0 T usbd_str +ffffffff823a6000 T usbd_get_desc +ffffffff823a6070 T usbd_get_device_status +ffffffff823a60c0 T usbd_get_hub_descriptor +ffffffff823a6130 T usbd_get_hub_ss_descriptor +ffffffff823a61a0 T usbd_get_port_status +ffffffff823a61f0 T usbd_set_hub_depth +ffffffff823a6240 T usbd_clear_port_feature +ffffffff823a6290 T usbd_clear_endpoint_feature +ffffffff823a62e0 T usbd_set_port_feature +ffffffff823a6330 T usbd_set_idle +ffffffff823a6390 T usbd_get_report_descriptor +ffffffff823a63e0 T usbd_get_hid_descriptor +ffffffff823a6460 T usbd_get_config +ffffffff823a64b0 T usb_detach_wait +ffffffff823a6530 T usb_detach_wakeup +ffffffff823a7000 T usb_block_allocmem +ffffffff823a7260 T usb_block_freemem +ffffffff823a72c0 T usb_allocmem +ffffffff823a7500 T usb_freemem +ffffffff823a75c0 T usb_syncmem +ffffffff823a8000 T usbd_errstr +ffffffff823a8070 T usbd_get_string_desc +ffffffff823a8130 T usbd_get_string +ffffffff823a8320 T usbd_cache_devinfo +ffffffff823a8680 T usbd_printBCD +ffffffff823a8710 T usbd_devinfo +ffffffff823a88b0 T usb_delay_ms +ffffffff823a8910 T usbd_delay_ms +ffffffff823a89d0 T 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toshiba_fn_key_video_output +ffffffff8250cf10 T toshiba_get_video_output +ffffffff8250d080 T toshiba_set_video_output +ffffffff8250e000 T acpisony_match +ffffffff8250e070 T acpisony_attach +ffffffff8250e0e0 T acpisony_activate +ffffffff8250e120 T acpisony_notify_setup +ffffffff8250e310 T acpisony_notify +ffffffff8250e6c0 T acpisony_find_offset +ffffffff8250e7d0 T acpisony_set_hotkey +ffffffff8250e9c0 T acpisony_brightness_down +ffffffff8250ead0 T acpisony_get_brightness +ffffffff8250eb50 T acpisony_set_brightness +ffffffff8250f000 T acpivideo_match +ffffffff8250f070 T acpivideo_attach +ffffffff8250f1d0 T acpivideo_getpcibus +ffffffff8250f210 T acpivideo_notify +ffffffff8250f270 T acpivideo_set_policy +ffffffff8250f340 T acpi_foundvout +ffffffff8250f410 T acpivideo_print +ffffffff82510000 T acpivout_match +ffffffff82510070 T acpivout_attach +ffffffff825101c0 T acpivout_notify +ffffffff82510270 T acpivout_get_bcl +ffffffff82510390 T acpivout_get_brightness +ffffffff82510430 T acpivout_get_param +ffffffff825104e0 T acpivout_set_param +ffffffff82510650 T acpivout_select_brightness +ffffffff82510720 T acpivout_find_brightness +ffffffff825107b0 T acpivout_set_brightness +ffffffff82511000 T acpipwrres_match +ffffffff82511070 T acpipwrres_attach +ffffffff825112b0 T acpipwrres_foundcons +ffffffff82511440 T acpipwrres_ref_incr +ffffffff825114d0 T acpipwrres_hascons +ffffffff82511520 T acpipwrres_ref_decr +ffffffff825115b0 T acpipwrres_addcons +ffffffff82512000 T aibs_match +ffffffff82512030 T aibs_attach +ffffffff82512140 T aibs_probe +ffffffff825122a0 T aibs_attach_new +ffffffff825123c0 T aibs_attach_sif +ffffffff82512590 T aibs_notify +ffffffff82512600 T aibs_add_sensor +ffffffff82512850 T aibs_getpack +ffffffff825128d0 T aibs_refresh +ffffffff82512930 T aibs_refresh_r +ffffffff82512a70 T aibs_getvalue +ffffffff82512bc0 T aibs_find_cb +ffffffff82513000 T aplgpio_match +ffffffff82513060 T aplgpio_attach +ffffffff82513300 T aplgpio_intr +ffffffff82513440 T aplgpio_read_pin +ffffffff82513490 T aplgpio_write_pin +ffffffff82513500 T aplgpio_intr_establish +ffffffff82513620 T aplgpio_intr_enable +ffffffff825136b0 T aplgpio_intr_disable +ffffffff82514000 T bytgpio_match +ffffffff82514060 T bytgpio_attach +ffffffff82514320 T bytgpio_intr +ffffffff82514450 T bytgpio_read_pin +ffffffff825144b0 T bytgpio_write_pin +ffffffff82514530 T bytgpio_intr_establish +ffffffff825145a0 T bytgpio_intr_enable +ffffffff82514690 T bytgpio_intr_disable +ffffffff82515000 T chvgpio_match +ffffffff82515060 T chvgpio_attach +ffffffff82515300 T chvgpio_intr +ffffffff825153d0 T chvgpio_read_pin +ffffffff82515480 T chvgpio_write_pin +ffffffff82515540 T chvgpio_intr_establish +ffffffff82515710 T chvgpio_intr_enable +ffffffff825157e0 T chvgpio_intr_disable +ffffffff825158b0 T chvgpio_opreg_handler +ffffffff82515940 T chvgpio_check_pin +ffffffff82516000 T glkgpio_match +ffffffff82516060 T glkgpio_attach +ffffffff82516300 T glkgpio_intr +ffffffff82516440 T glkgpio_read_pin +ffffffff825164a0 T glkgpio_write_pin +ffffffff82516510 T glkgpio_intr_establish +ffffffff82516630 T glkgpio_intr_enable +ffffffff825166c0 T glkgpio_intr_disable +ffffffff82517000 T pchgpio_match +ffffffff82517060 T pchgpio_attach +ffffffff825174b0 T pchgpio_activate +ffffffff82517560 T pchgpio_intr +ffffffff82517780 T pchgpio_read_pin +ffffffff82517870 T pchgpio_write_pin +ffffffff82517980 T pchgpio_intr_establish +ffffffff82517bb0 T pchgpio_intr_enable +ffffffff82517cf0 T pchgpio_intr_disable +ffffffff82517e30 T pchgpio_save +ffffffff82517ea0 T pchgpio_restore +ffffffff82517f10 T pchgpio_find_group +ffffffff82517f90 T pchgpio_intr_handle +ffffffff82518070 T pchgpio_save_pin +ffffffff82518240 T pchgpio_restore_pin +ffffffff82519000 T tipmic_match +ffffffff82519050 T tipmic_attach +ffffffff82519250 T tipmic_write_1 +ffffffff82519310 T tipmic_intr +ffffffff82519470 T tipmic_get_lpat +ffffffff825195a0 T tipmic_read_pin +ffffffff825195d0 T tipmic_write_pin +ffffffff82519600 T tipmic_thermal_opreg_handler +ffffffff82519e70 T tipmic_power_opreg_handler +ffffffff8251a110 T tipmic_read_1 +ffffffff8251a1d0 T tipmic_raw_to_temp +ffffffff8251b000 T ccpmic_match +ffffffff8251b050 T ccpmic_attach +ffffffff8251b130 T ccpmic_get_lpat +ffffffff8251b250 T ccpmic_read_pin +ffffffff8251b3d0 T ccpmic_write_pin +ffffffff8251b530 T ccpmic_thermal_opreg_handler +ffffffff8251b770 T ccpmic_power_opreg_handler +ffffffff8251b960 T ccpmic_read_1 +ffffffff8251ba20 T ccpmic_write_1 +ffffffff8251bae0 T ccpmic_raw_to_temp +ffffffff8251c000 T com_acpi_match +ffffffff8251c120 T com_acpi_attach +ffffffff8251c3a0 T com_acpi_is_designware +ffffffff8251c400 T com_acpi_intr_designware +ffffffff8251c430 T com_acpi_is_console +ffffffff8251d000 T sdhc_acpi_match +ffffffff8251d060 T sdhc_acpi_attach +ffffffff8251d360 T sdhc_acpi_parse_resources +ffffffff8251d420 T sdhc_acpi_card_detect_gpio +ffffffff8251d480 T sdhc_acpi_card_detect_intr +ffffffff8251d4c0 T sdhc_acpi_power_on +ffffffff8251d540 T sdhc_acpi_explore +ffffffff8251d570 T sdhc_acpi_card_detect_nonremovable +ffffffff8251d5a0 T sdhc_acpi_do_explore +ffffffff8251e000 T dwiic_acpi_match +ffffffff8251e050 T dwiic_acpi_attach +ffffffff8251e410 T dwiic_acpi_parse_crs +ffffffff8251e540 T dwiic_acpi_power +ffffffff8251e650 T dwiic_acpi_get_params +ffffffff8251e790 T dwiic_i2c_intr_establish +ffffffff8251e810 T dwiic_i2c_intr_disestablish +ffffffff8251e830 T dwiic_i2c_intr_string +ffffffff8251e8c0 T dwiic_acpi_acquire_bus +ffffffff8251e910 T dwiic_acpi_release_bus +ffffffff8251e940 T dwiic_acpi_bus_scan +ffffffff8251e980 T dwiic_acpi_found_hid +ffffffff8251ecb0 T dwiic_matchhids +ffffffff8251ed40 T dwiic_acpi_found_ihidev +ffffffff8251efc0 T dwiic_acpi_found_iatp +ffffffff82520000 T acpicbkbd_match +ffffffff82520030 T acpicbkbd_attach +ffffffff825200d0 T acpicbkbd_activate +ffffffff82520120 T acpicbkbd_get_backlight +ffffffff825201a0 T acpicbkbd_set_backlight +ffffffff82520240 T acpicbkbd_write_backlight +ffffffff82521000 T acpials_match +ffffffff82521090 T acpials_attach +ffffffff82521230 T acpials_read +ffffffff825212b0 T acpials_addtask +ffffffff825212f0 T acpials_notify +ffffffff82521380 T acpials_update +ffffffff82522000 T tpm_match +ffffffff82522050 T tpm_attach +ffffffff82522320 T tpm_activate +ffffffff82522430 T tpm2_start_method +ffffffff825224b0 T tpm_probe +ffffffff82522560 T tpm_init_tis +ffffffff825227d0 T tpm_init_crb +ffffffff82522b10 T tpm_suspend +ffffffff82522c00 T tpm_resume +ffffffff82522c30 T tpm_write_tis +ffffffff82522fb0 T tpm_read_tis +ffffffff82523190 T tpm_write_crb +ffffffff825235a0 T tpm_read_crb +ffffffff825238a0 T tpm_request_locality_tis +ffffffff82523990 T tpm_request_locality_crb +ffffffff82523a90 T tpm_release_locality_crb +ffffffff82523ae0 T tpm_release_locality_tis +ffffffff82523b50 T tpm_getburst +ffffffff82523c00 T tpm_status +ffffffff82523c20 T tpm_waitfor +ffffffff82523d00 T tpm_waitfor_status +ffffffff82524000 T acpihve_match +ffffffff825240b0 T acpihve_attach +ffffffff82525000 T acpisbs_match +ffffffff82525030 T acpisbs_attach +ffffffff825252a0 T acpisbs_activate +ffffffff82525380 T acpisbs_read +ffffffff82525440 T acpisbs_setup_sensors +ffffffff82525560 T acpisbs_refresh_sensors +ffffffff825256d0 T acpisbs_notify +ffffffff82525810 T acpi_smbus_read +ffffffff82526000 T surface_match +ffffffff82526060 T surface_attach +ffffffff825260c0 T surface_hotkey +ffffffff82527000 T ipmi_acpi_match +ffffffff82527030 T ipmi_acpi_attach +ffffffff82527260 T ipmi_acpi_parse_crs +ffffffff82528000 T amdgpio_match +ffffffff82528060 T amdgpio_attach +ffffffff825282a0 T amdgpio_activate +ffffffff82528390 T amdgpio_intr +ffffffff82528530 T amdgpio_read_pin +ffffffff82528580 T amdgpio_write_pin +ffffffff825285f0 T amdgpio_intr_establish +ffffffff825286e0 T amdgpio_intr_enable +ffffffff82528760 T amdgpio_intr_disable +ffffffff825287e0 T amdgpio_save +ffffffff82528860 T amdgpio_restore +ffffffff825288f0 T amdgpio_save_pin +ffffffff82528960 T amdgpio_restore_pin +ffffffff825289d0 T amdgpio_pin_intr +ffffffff82529000 T acpihid_match +ffffffff82529030 T acpihid_attach +ffffffff82529210 T acpihid_init_dsm +ffffffff82529370 T acpihid_eval +ffffffff82529590 T acpihid_notify +ffffffff825295f0 T acpihid_button_array_enable +ffffffff8252a000 t iosf_acpi_match +ffffffff8252a050 t iosf_acpi_attach +ffffffff8252a140 t iosf_acpi_mbi_mdr_rd +ffffffff8252a1b0 t iosf_acpi_mbi_mdr_wr +ffffffff8252b000 T acpi_match +ffffffff8252b060 T acpi_attach +ffffffff8252b0a0 T acpi_probe +ffffffff8252b240 T acpi_map +ffffffff8252b330 T acpi_unmap +ffffffff8252b380 T acpi_bus_space_map +ffffffff8252b3a0 T acpi_bus_space_unmap +ffffffff8252b3c0 T acpi_intr_establish +ffffffff8252b510 T acpi_intr_disestablish +ffffffff8252b520 T acpi_scan +ffffffff8252b6d0 T acpi_acquire_glk +ffffffff8252b730 T acpi_release_glk +ffffffff8252b780 T acpi_attach_machdep +ffffffff8252b910 T acpi_sleep_cpu +ffffffff8252bab0 T acpi_resume_cpu +ffffffff8252bbb0 T sleep_mp +ffffffff8252bcb0 T resume_mp +ffffffff8252bda0 T acpi_iommu_device_map +ffffffff8252c000 T hibernate_resume_machdep +ffffffff8252c050 T hibernate_drop_to_real_mode +ffffffff8252c060 T hibernate_activate_resume_pt_machdep +ffffffff8252c0a0 T hibernate_switch_stack_machdep +ffffffff8252c0e0 T hibernate_flush +ffffffff8252c110 T acpi_savecpu +ffffffff8252d000 T sleep_showstate +ffffffff8252d100 T sleep_setstate +ffffffff8252d160 T gosleep +ffffffff8252d220 T sleep_abort +ffffffff8252d250 T sleep_resume +ffffffff8252d2c0 T suspend_finish +ffffffff8252e000 T acpipci_match +ffffffff8252e030 T acpipci_attach +ffffffff8252e2f0 T acpipci_osc +ffffffff8252e430 T acpipci_parse_resources +ffffffff8252e540 T acpipci_attach_bus +ffffffff8252e710 T acpipci_print +ffffffff8252e780 T acpipci_attach_busses +ffffffff8252f000 T efiopen +ffffffff8252f040 T eficlose +ffffffff8252f070 T efiioctl +ffffffff8252f110 T efiioc_get_table +ffffffff8252f270 T efiioc_var_get +ffffffff8252f4f0 T efiioc_var_next +ffffffff8252f710 T efiioc_var_set +ffffffff8252f9c0 T efi_adapt_error +ffffffff82530000 T efi_match +ffffffff82530060 T efi_attach +ffffffff825302f0 T efi_map_runtime +ffffffff82530470 T efi_enter +ffffffff82530500 T efi_leave +ffffffff82530560 T efi_fault +ffffffff82531000 T vmm_probe +ffffffff82531050 T vmm_attach +ffffffff82531170 T vmm_activate +ffffffff825312b0 T vmmopen +ffffffff82531300 T vmmclose +ffffffff82531330 T vm_find +ffffffff82531450 T vmmioctl +ffffffff825316d0 T vm_create +ffffffff82531a80 T vm_get_info +ffffffff82531cd0 T vm_terminate +ffffffff82531e40 T vm_resetcpu +ffffffff82531f60 T vm_share_mem +ffffffff825320b0 T pledge_ioctl_vmm +ffffffff825321a0 T vm_find_vcpu +ffffffff82532200 T vm_create_check_mem_ranges +ffffffff82532360 T vm_teardown +ffffffff82532490 T vcpu_must_stop +ffffffff82533000 T vmm_enabled +ffffffff82533090 T vmm_attach_machdep +ffffffff82533250 T vmm_quiesce_vmx +ffffffff82533420 T vmm_activate_machdep +ffffffff82533550 T vmm_stop +ffffffff825336a0 T vmm_start +ffffffff82533790 T vmmioctl_machdep +ffffffff82533860 T vm_intr_pending +ffffffff82533900 T vm_mprotect_ept +ffffffff82533ba0 T pledge_ioctl_vmm_machdep +ffffffff82533bf0 T vm_rwvmparams +ffffffff82533d80 T vmm_init_pvclock +ffffffff82533e60 T vm_rwregs +ffffffff82533f70 T vcpu_readregs_vmx +ffffffff825343a0 T vcpu_writeregs_vmx +ffffffff82534810 T vcpu_readregs_svm +ffffffff82534cc0 T vcpu_writeregs_svm +ffffffff82535190 T vmm_get_guest_memtype +ffffffff82535210 T vmx_mprotect_ept +ffffffff82535490 T vmx_pmap_find_pte_ept +ffffffff82535560 T start_vmm_on_cpu +ffffffff82535640 T stop_vmm_on_cpu +ffffffff825356e0 T vmclear_on_cpu +ffffffff82535760 T vm_impl_init_vmx +ffffffff82535880 T vm_impl_init_svm +ffffffff825359a0 T vm_impl_init +ffffffff82535a40 T vm_impl_deinit +ffffffff82535a70 T vcpu_reload_vmcs_vmx +ffffffff82535bb0 T vcpu_reset_regs_svm +ffffffff82535f40 T svm_setmsrbrw +ffffffff825360b0 T svm_setmsrbr +ffffffff82536180 T vmm_alloc_vpid +ffffffff82536290 T svm_setmsrbw +ffffffff82536370 T vmx_setmsrbr +ffffffff82536420 T vmx_setmsrbw +ffffffff825364d0 T vmx_setmsrbrw +ffffffff825365e0 T svm_set_clean +ffffffff82536630 T svm_set_dirty +ffffffff82536680 T vcpu_reset_regs_vmx +ffffffff82537230 T vcpu_vmx_check_cap +ffffffff82537330 T vcpu_vmx_compute_ctrl +ffffffff82537510 T vcpu_init_vmx +ffffffff825378b0 T vcpu_deinit_vmx +ffffffff82537a30 T vcpu_reset_regs +ffffffff82537a70 T vcpu_init_svm +ffffffff82537c00 T vcpu_deinit_svm +ffffffff82537d40 T vcpu_init +ffffffff82537e00 T vmm_free_vpid +ffffffff82537e70 T vcpu_deinit +ffffffff82537eb0 T vm_run +ffffffff82538060 T vcpu_run_vmx +ffffffff825387e0 T vcpu_run_svm +ffffffff82538d90 T vmm_fpurestore +ffffffff82538e60 T vmm_fpusave +ffffffff82538ee0 T vmm_translate_gva +ffffffff82539200 T vmm_update_pvclock +ffffffff82539300 T vmx_get_exit_info +ffffffff82539360 T vmx_handle_exit +ffffffff825397a0 T vmx_instruction_error_decode +ffffffff82539970 T vmm_get_guest_cpu_cpl +ffffffff82539a60 T vmx_handle_intr +ffffffff82539af0 T svm_handle_hlt +ffffffff82539b40 T vmx_handle_hlt +ffffffff82539bf0 T svm_handle_exit +ffffffff82539f10 T svm_handle_np_fault +ffffffff8253a0a0 T vmm_handle_cpuid +ffffffff8253a730 T svm_handle_msr +ffffffff8253a9f0 T svm_handle_xsetbv +ffffffff8253aa90 T svm_handle_inout +ffffffff8253ab90 T vmm_inject_ud +ffffffff8253abc0 T vmm_inject_db +ffffffff8253abf0 T vmx_handle_np_fault +ffffffff8253ad60 T vmx_handle_inout +ffffffff8253aef0 T vmx_handle_cr +ffffffff8253b160 T vmx_handle_rdmsr +ffffffff8253b230 T vmx_handle_wrmsr +ffffffff8253b490 T vmx_handle_xsetbv +ffffffff8253b560 T vmm_inject_gp +ffffffff8253b590 T vmx_get_exit_qualification +ffffffff8253b5f0 T vmx_get_guest_faulttype +ffffffff8253b690 T svm_get_guest_faulttype +ffffffff8253b6c0 T svm_fault_page +ffffffff8253b750 T vmx_fault_page +ffffffff8253b8b0 T vmm_get_guest_cpu_mode +ffffffff8253b9b0 T vmx_load_pdptes +ffffffff8253bc30 T vmx_handle_cr0_write +ffffffff8253be40 T vmx_handle_cr4_write +ffffffff8253bee0 T vmm_handle_xsetbv +ffffffff8253bf70 T vmx_handle_misc_enable_msr +ffffffff8253bfd0 T vmm_pat_is_valid +ffffffff8253c0b0 T vmm_gpa_is_valid +ffffffff8253c120 T vmx_exit_reason_decode +ffffffff8253c160 T svm_exit_reason_decode +ffffffff8253cf70 T vcpu_state_decode +ffffffff8253d000 T vmm_dispatch_intr +ffffffff8253d020 T vmxon +ffffffff8253d050 T vmxoff +ffffffff8253d080 T vmclear +ffffffff8253d0b0 T vmptrld +ffffffff8253d0e0 T vmptrst +ffffffff8253d110 T vmwrite +ffffffff8253d140 T vmread +ffffffff8253d170 T invvpid +ffffffff8253d1a0 T invept +ffffffff8253d1d0 T vmx_enter_guest +ffffffff8253d1fb t skip_init +ffffffff8253d2c8 t no_l1df_msr +ffffffff8253d2cb t l1df_tlb_loop +ffffffff8253d2e4 t l1df_tlb_done +ffffffff8253d2ec t l1df_load_cache +ffffffff8253d303 t done_flush +ffffffff8253d396 t do_resume +ffffffff8253d41b t fail_launch_or_resume +ffffffff8253d45d t fail_launch_unknown +ffffffff8253d46a t fail_launch_invalid_vmcs +ffffffff8253d477 t fail_launch_valid_vmcs +ffffffff8253d494 t vmx_exit_handler_asm +ffffffff8253d559 t restore_host +ffffffff8253d5f0 T svm_enter_guest +ffffffff8253d780 t restore_host_svm +ffffffff8253e000 T sdmmc_match +ffffffff8253e050 T sdmmc_attach +ffffffff8253e390 T sdmmc_detach +ffffffff8253e440 T sdmmc_activate +ffffffff8253e510 T sdmmc_discover_task +ffffffff8253e5d0 T sdmmc_create_thread +ffffffff8253e640 T sdmmc_holds_root_device +ffffffff8253e6a0 T sdmmc_task_thread +ffffffff8253e890 T sdmmc_needs_discover +ffffffff8253e940 T sdmmc_del_task +ffffffff8253e9f0 T sdmmc_card_detach +ffffffff8253ead0 T sdmmc_add_task +ffffffff8253eb50 T sdmmc_card_attach +ffffffff8253ec60 T sdmmc_enable +ffffffff8253edb0 T sdmmc_scan +ffffffff8253ee40 T sdmmc_init +ffffffff8253ef40 T sdmmc_disable +ffffffff8253f0a0 T sdmmc_function_free +ffffffff8253f0c0 T sdmmc_delay +ffffffff8253f110 T sdmmc_select_card +ffffffff8253f290 T sdmmc_set_bus_power +ffffffff8253f450 T sdmmc_function_alloc +ffffffff8253f4e0 T sdmmc_app_command +ffffffff8253f670 T sdmmc_mmc_command +ffffffff8253f6f0 T sdmmc_go_idle_state +ffffffff8253f810 T sdmmc_send_if_cond +ffffffff8253f960 T sdmmc_set_relative_addr +ffffffff82540000 T sdmmc_cisptr +ffffffff825400a0 T sdmmc_read_cis +ffffffff825403b0 T sdmmc_print_cis +ffffffff82540520 T sdmmc_check_cis_quirks +ffffffff82541000 T sdmmc_io_enable +ffffffff825412a0 T sdmmc_io_reset +ffffffff825413d0 T sdmmc_io_send_op_cond +ffffffff82541540 T sdmmc_io_scan +ffffffff82541690 T sdmmc_io_init +ffffffff825417c0 T sdmmc_io_set_highspeed +ffffffff82541a70 T sdmmc_io_set_bus_width +ffffffff82541d00 T sdmmc_io_function_ready +ffffffff82541e80 T sdmmc_io_read_1 +ffffffff82541fd0 T sdmmc_io_function_enable +ffffffff825423a0 T sdmmc_io_write_1 +ffffffff82542520 T sdmmc_io_function_disable +ffffffff825427a0 T sdmmc_io_attach +ffffffff82542890 T sdmmc_print +ffffffff82542ae0 T sdmmc_submatch +ffffffff82542b60 T sdmmc_io_detach +ffffffff82542c10 T sdmmc_io_rw_direct +ffffffff82542db0 T sdmmc_io_rw_extended_subr +ffffffff82542f50 T sdmmc_io_rw_extended +ffffffff82543340 T sdmmc_io_read_2 +ffffffff825434a0 T sdmmc_io_write_2 +ffffffff82543600 T sdmmc_io_read_4 +ffffffff82543760 T sdmmc_io_write_4 +ffffffff825438c0 T sdmmc_io_read_multi_1 +ffffffff825439b0 T sdmmc_io_write_multi_1 +ffffffff82543aa0 T sdmmc_io_read_region_1 +ffffffff82543b90 T sdmmc_io_write_region_1 +ffffffff82543c80 T sdmmc_io_xchg +ffffffff82543e10 T sdmmc_intr_enable +ffffffff82544080 T sdmmc_intr_disable +ffffffff825442f0 T sdmmc_intr_establish +ffffffff825443f0 T sdmmc_intr_disestablish +ffffffff825444e0 T sdmmc_card_intr +ffffffff82544530 T sdmmc_intr_task +ffffffff825445c0 T sdmmc_io_set_blocklen +ffffffff82545000 T sdmmc_mem_enable +ffffffff825454e0 T sdmmc_mem_send_op_cond +ffffffff82545690 T sdmmc_mem_signal_voltage +ffffffff82545750 T sdmmc_mem_scan +ffffffff82545a60 T sdmmc_decode_csd +ffffffff82545e70 T sdmmc_decode_cid +ffffffff825462b0 T sdmmc_mem_send_scr +ffffffff825463f0 T sdmmc_mem_decode_scr +ffffffff82546470 T sdmmc_mem_send_cxd_data +ffffffff825465e0 T sdmmc_mem_set_bus_width +ffffffff82546700 T sdmmc_mem_sd_switch +ffffffff825469b0 T sdmmc_be512_to_bitfield512 +ffffffff82546a60 T sdmmc_mem_mmc_switch +ffffffff82546b50 T sdmmc_mem_init +ffffffff82546ca0 T sdmmc_mem_set_blocklen +ffffffff82546da0 T sdmmc_mem_sd_init +ffffffff82547350 T sdmmc_mem_mmc_init +ffffffff82547c70 T sdmmc_mem_select_transfer_mode +ffffffff82547cf0 T sdmmc_mem_execute_tuning +ffffffff82547d80 T sdmmc_mem_read_block_subr +ffffffff825480e0 T sdmmc_mem_single_read_block +ffffffff825481b0 T sdmmc_mem_read_block +ffffffff82548370 T sdmmc_mem_write_block_subr +ffffffff825486c0 T sdmmc_mem_single_write_block +ffffffff82548790 T sdmmc_mem_write_block +ffffffff82548950 T sdmmc_mem_hibernate_write +ffffffff82549000 T sdmmc_scsi_cmd +ffffffff825491f0 T sdmmc_minphys +ffffffff82549270 T sdmmc_scsi_attach +ffffffff82549460 T sdmmc_alloc_ccbs +ffffffff825495a0 T sdmmc_free_ccbs +ffffffff82549600 T sdmmc_scsi_detach +ffffffff82549760 T sdmmc_stimeout +ffffffff825497e0 T sdmmc_ccb_alloc +ffffffff82549890 T sdmmc_ccb_free +ffffffff82549970 T sdmmc_inquiry +ffffffff82549be0 T sdmmc_start_xs +ffffffff82549cd0 T sdmmc_complete_xs +ffffffff82549da0 T sdmmc_done_xs +ffffffff82549df0 T sdmmc_scsi_hibernate_io +ffffffff8254a000 T bwfm_sdio_preinit +ffffffff8254a4f0 T bwfm_sdio_txcheck +ffffffff8254a530 T bwfm_sdio_txdata +ffffffff8254a5a0 T bwfm_sdio_txctl +ffffffff8254a6f0 T bwfm_sdio_buscore_read +ffffffff8254a700 T bwfm_sdio_buscore_write +ffffffff8254a720 T bwfm_sdio_buscore_prepare +ffffffff8254a860 T bwfm_sdio_buscore_activate +ffffffff8254a8e0 T bwfm_sdio_match +ffffffff8254a9b0 T bwfm_sdio_attach +ffffffff8254ac70 T bwfm_sdio_detach +ffffffff8254acd0 T bwfm_sdio_task +ffffffff8254ae30 T bwfm_sdio_write_1 +ffffffff8254ae60 T bwfm_sdio_read_1 +ffffffff8254ae90 T bwfm_sdio_write_4 +ffffffff8254af40 T bwfm_sdio_read_4 +ffffffff8254aff0 T bwfm_sdio_load_microcode +ffffffff8254b250 T bwfm_sdio_clkctl +ffffffff8254b380 T bwfm_sdio_dev_write +ffffffff8254b3d0 T bwfm_sdio_intr +ffffffff8254b410 T bwfm_sdio_ram_read_write +ffffffff8254b640 T bwfm_sdio_htclk +ffffffff8254b8a0 T bwfm_sdio_readshared +ffffffff8254b970 T bwfm_sdio_dev_read +ffffffff8254b9b0 T bwfm_sdio_rx_frames +ffffffff8254bd40 T bwfm_sdio_tx_frames +ffffffff8254be20 T bwfm_sdio_backplane +ffffffff8254bed0 T bwfm_sdio_buf_read +ffffffff8254bfb0 T bwfm_sdio_buf_write +ffffffff8254c060 T bwfm_sdio_frame_read_write +ffffffff8254c1e0 T bwfm_sdio_newbuf +ffffffff8254c260 T bwfm_sdio_tx_ok +ffffffff8254c2b0 T bwfm_sdio_tx_ctrlframe +ffffffff8254c3b0 T bwfm_sdio_tx_dataframe +ffffffff8254c500 T bwfm_sdio_rx_glom +ffffffff8254d000 T onewire_match +ffffffff8254d050 T onewire_attach +ffffffff8254d0f0 T onewire_detach +ffffffff8254d160 T onewire_activate +ffffffff8254d180 T onewire_scan +ffffffff8254d390 T onewire_createthread +ffffffff8254d400 T onewire_print +ffffffff8254d4d0 T onewirebus_print +ffffffff8254d520 T onewire_lock +ffffffff8254d540 T onewire_unlock +ffffffff8254d560 T onewire_reset +ffffffff8254d580 T onewire_bit +ffffffff8254d5a0 T onewire_read_byte +ffffffff8254d6e0 T onewire_write_byte +ffffffff8254d7c0 T onewire_read_block +ffffffff8254d860 T onewire_write_block +ffffffff8254d900 T onewire_triplet +ffffffff8254d9e0 T onewire_matchrom +ffffffff8254db30 T onewire_search +ffffffff8254dec0 T onewire_thread +ffffffff8254e000 T onewire_crc +ffffffff8254e0e0 T onewire_crc16 +ffffffff8254e1c0 T onewire_famname +ffffffff8254e200 T onewire_matchbyfam +ffffffff8254f000 T owid_match +ffffffff8254f030 T owid_attach +ffffffff8254f100 T owid_detach +ffffffff8254f140 T owid_activate +ffffffff82550000 T owsbm_match +ffffffff82550030 T owsbm_attach +ffffffff825501d0 T owsbm_detach +ffffffff82550240 T owsbm_activate +ffffffff82550270 T owsbm_update +ffffffff82551000 T owtemp_match +ffffffff82551030 T owtemp_attach +ffffffff82551130 T owtemp_detach +ffffffff825511a0 T owtemp_activate +ffffffff825511d0 T owtemp_update +ffffffff82552000 T owctr_match +ffffffff82552030 T owctr_attach +ffffffff82552180 T owctr_detach +ffffffff825521f0 T owctr_activate +ffffffff82552220 T owctr_update +ffffffff82552250 T owctr_update_counter +ffffffff82553000 A __text_page_start +ffffffff82553000 T Xsyscall_meltdown +ffffffff8255300c T Xsyscall +ffffffff8255326e t Xsyscall_trampback +ffffffff82553280 T intr_user_exit +ffffffff825532c2 t intr_user_exit_post_ast +ffffffff825533ee t Xiretq_trampback +ffffffff825533fa T doreti_iret +ffffffff82554000 T alltraps +ffffffff82554138 T recall_trap +ffffffff82554150 T alltraps_kern +ffffffff82554153 T alltraps_kern_meltdown +ffffffff82555000 ? Xsyscall32 +ffffffff82555000 A __kutext_start +ffffffff82555000 A __text_page_end +ffffffff82556000 ? Xtrap00 +ffffffff82556010 ? Xtrap01 +ffffffff82556020 ? Xtrap02 +ffffffff82556028 c calltrap_specstk +ffffffff825560f0 ? calltrap_specstk_tramp +ffffffff82556110 ? Xtrap03 +ffffffff82556120 ? Xtrap04 +ffffffff82556130 ? Xtrap05 +ffffffff82556140 ? Xtrap06 +ffffffff82556150 ? Xtrap07 +ffffffff82556160 ? Xtrap08 +ffffffff82556170 ? Xtrap09 +ffffffff82556180 ? Xtrap0a +ffffffff82556190 ? Xtrap0b +ffffffff825561a0 ? Xtrap0c +ffffffff825561b0 ? Xtrap0d +ffffffff82556240 ? Xtrap0e +ffffffff82556250 ? Xintrspurious +ffffffff82556250 ? Xtrap0f +ffffffff82556260 ? Xtrap10 +ffffffff82556270 ? Xtrap11 +ffffffff82556280 ? Xtrap12 +ffffffff82556290 ? Xtrap13 +ffffffff825562a0 ? Xtrap14 +ffffffff825562b0 ? Xtrap15 +ffffffff825562c0 ? Xtrap16 +ffffffff825562c0 ? Xtrap17 +ffffffff825562c0 ? Xtrap18 +ffffffff825562c0 ? Xtrap19 +ffffffff825562c0 ? Xtrap1a +ffffffff825562c0 ? Xtrap1b +ffffffff825562c0 ? Xtrap1c +ffffffff825562c0 ? Xtrap1d +ffffffff825562c0 ? Xtrap1e +ffffffff825562c0 ? Xtrap1f +ffffffff825562d0 ? x2apic_eoi +ffffffff825562f0 ? Xintr_lapic_ipi +ffffffff82556330 ? Xipi_invltlb +ffffffff82556360 ? Xipi_invlpg +ffffffff82556390 ? Xipi_invlrange +ffffffff825563d0 ? Xipi_invltlb_pcid +ffffffff82556410 ? Xipi_invlpg_pcid +ffffffff82556460 ? Xipi_invlrange_pcid +ffffffff825564d0 ? Xintr_lapic_ltimer +ffffffff82556510 ? Xintr_xen_upcall +ffffffff82556550 ? Xintr_hyperv_upcall +ffffffff82556590 ? Xintr_legacy0 +ffffffff825565d0 ? Xintr_legacy1 +ffffffff82556610 ? Xintr_legacy2 +ffffffff82556650 ? Xintr_legacy3 +ffffffff82556690 ? Xintr_legacy4 +ffffffff825566d0 ? Xintr_legacy5 +ffffffff82556710 ? Xintr_legacy6 +ffffffff82556750 ? Xintr_legacy7 +ffffffff82556790 ? Xintr_legacy8 +ffffffff825567d0 ? Xintr_legacy9 +ffffffff82556810 ? Xintr_legacy10 +ffffffff82556850 ? Xintr_legacy11 +ffffffff82556890 ? Xintr_legacy12 +ffffffff825568d0 ? Xintr_legacy13 +ffffffff82556910 ? Xintr_legacy14 +ffffffff82556950 ? Xintr_legacy15 +ffffffff82556990 ? Xintr_ioapic_edge0 +ffffffff825569d0 ? Xintr_ioapic_edge1 +ffffffff82556a10 ? Xintr_ioapic_edge2 +ffffffff82556a50 ? Xintr_ioapic_edge3 +ffffffff82556a90 ? Xintr_ioapic_edge4 +ffffffff82556ad0 ? Xintr_ioapic_edge5 +ffffffff82556b10 ? Xintr_ioapic_edge6 +ffffffff82556b50 ? Xintr_ioapic_edge7 +ffffffff82556b90 ? Xintr_ioapic_edge8 +ffffffff82556bd0 ? Xintr_ioapic_edge9 +ffffffff82556c10 ? Xintr_ioapic_edge10 +ffffffff82556c50 ? Xintr_ioapic_edge11 +ffffffff82556c90 ? Xintr_ioapic_edge12 +ffffffff82556cd0 ? Xintr_ioapic_edge13 +ffffffff82556d10 ? Xintr_ioapic_edge14 +ffffffff82556d50 ? Xintr_ioapic_edge15 +ffffffff82556d90 ? Xintr_ioapic_edge16 +ffffffff82556dd0 ? Xintr_ioapic_edge17 +ffffffff82556e10 ? Xintr_ioapic_edge18 +ffffffff82556e50 ? Xintr_ioapic_edge19 +ffffffff82556e90 ? Xintr_ioapic_edge20 +ffffffff82556ed0 ? Xintr_ioapic_edge21 +ffffffff82556f10 ? Xintr_ioapic_edge22 +ffffffff82556f50 ? Xintr_ioapic_edge23 +ffffffff82556f90 ? Xintr_ioapic_edge24 +ffffffff82556fd0 ? Xintr_ioapic_edge25 +ffffffff82557010 ? Xintr_ioapic_edge26 +ffffffff82557050 ? Xintr_ioapic_edge27 +ffffffff82557090 ? Xintr_ioapic_edge28 +ffffffff825570d0 ? Xintr_ioapic_edge29 +ffffffff82557110 ? Xintr_ioapic_edge30 +ffffffff82557150 ? Xintr_ioapic_edge31 +ffffffff82557190 ? Xintr_ioapic_edge32 +ffffffff825571d0 ? Xintr_ioapic_edge33 +ffffffff82557210 ? Xintr_ioapic_edge34 +ffffffff82557250 ? Xintr_ioapic_edge35 +ffffffff82557290 ? Xintr_ioapic_edge36 +ffffffff825572d0 ? Xintr_ioapic_edge37 +ffffffff82557310 ? Xintr_ioapic_edge38 +ffffffff82557350 ? Xintr_ioapic_edge39 +ffffffff82557390 ? Xintr_ioapic_edge40 +ffffffff825573d0 ? Xintr_ioapic_edge41 +ffffffff82557410 ? Xintr_ioapic_edge42 +ffffffff82557450 ? Xintr_ioapic_edge43 +ffffffff82557490 ? Xintr_ioapic_edge44 +ffffffff825574d0 ? Xintr_ioapic_edge45 +ffffffff82557510 ? Xintr_ioapic_edge46 +ffffffff82557550 ? Xintr_ioapic_edge47 +ffffffff82557590 ? Xintr_ioapic_edge48 +ffffffff825575d0 ? Xintr_ioapic_edge49 +ffffffff82557610 ? Xintr_ioapic_edge50 +ffffffff82557650 ? Xintr_ioapic_edge51 +ffffffff82557690 ? Xintr_ioapic_edge52 +ffffffff825576d0 ? Xintr_ioapic_edge53 +ffffffff82557710 ? Xintr_ioapic_edge54 +ffffffff82557750 ? Xintr_ioapic_edge55 +ffffffff82557790 ? Xintr_ioapic_edge56 +ffffffff825577d0 ? Xintr_ioapic_edge57 +ffffffff82557810 ? Xintr_ioapic_edge58 +ffffffff82557850 ? Xintr_ioapic_edge59 +ffffffff82557890 ? Xintr_ioapic_edge60 +ffffffff825578d0 ? Xintr_ioapic_edge61 +ffffffff82557910 ? Xintr_ioapic_edge62 +ffffffff82557950 ? Xintr_ioapic_edge63 +ffffffff82557990 ? Xintr_ioapic_level0 +ffffffff825579d0 ? Xintr_ioapic_level1 +ffffffff82557a10 ? Xintr_ioapic_level2 +ffffffff82557a50 ? Xintr_ioapic_level3 +ffffffff82557a90 ? Xintr_ioapic_level4 +ffffffff82557ad0 ? Xintr_ioapic_level5 +ffffffff82557b10 ? Xintr_ioapic_level6 +ffffffff82557b50 ? Xintr_ioapic_level7 +ffffffff82557b90 ? Xintr_ioapic_level8 +ffffffff82557bd0 ? Xintr_ioapic_level9 +ffffffff82557c10 ? Xintr_ioapic_level10 +ffffffff82557c50 ? Xintr_ioapic_level11 +ffffffff82557c90 ? Xintr_ioapic_level12 +ffffffff82557cd0 ? Xintr_ioapic_level13 +ffffffff82557d10 ? Xintr_ioapic_level14 +ffffffff82557d50 ? Xintr_ioapic_level15 +ffffffff82557d90 ? Xintr_ioapic_level16 +ffffffff82557dd0 ? Xintr_ioapic_level17 +ffffffff82557e10 ? Xintr_ioapic_level18 +ffffffff82557e50 ? Xintr_ioapic_level19 +ffffffff82557e90 ? Xintr_ioapic_level20 +ffffffff82557ed0 ? Xintr_ioapic_level21 +ffffffff82557f10 ? Xintr_ioapic_level22 +ffffffff82557f50 ? Xintr_ioapic_level23 +ffffffff82557f90 ? Xintr_ioapic_level24 +ffffffff82557fd0 ? Xintr_ioapic_level25 +ffffffff82558010 ? Xintr_ioapic_level26 +ffffffff82558050 ? Xintr_ioapic_level27 +ffffffff82558090 ? Xintr_ioapic_level28 +ffffffff825580d0 ? Xintr_ioapic_level29 +ffffffff82558110 ? Xintr_ioapic_level30 +ffffffff82558150 ? Xintr_ioapic_level31 +ffffffff82558190 ? Xintr_ioapic_level32 +ffffffff825581d0 ? Xintr_ioapic_level33 +ffffffff82558210 ? Xintr_ioapic_level34 +ffffffff82558250 ? Xintr_ioapic_level35 +ffffffff82558290 ? Xintr_ioapic_level36 +ffffffff825582d0 ? Xintr_ioapic_level37 +ffffffff82558310 ? Xintr_ioapic_level38 +ffffffff82558350 ? Xintr_ioapic_level39 +ffffffff82558390 ? Xintr_ioapic_level40 +ffffffff825583d0 ? Xintr_ioapic_level41 +ffffffff82558410 ? Xintr_ioapic_level42 +ffffffff82558450 ? Xintr_ioapic_level43 +ffffffff82558490 ? Xintr_ioapic_level44 +ffffffff825584d0 ? Xintr_ioapic_level45 +ffffffff82558510 ? Xintr_ioapic_level46 +ffffffff82558550 ? Xintr_ioapic_level47 +ffffffff82558590 ? Xintr_ioapic_level48 +ffffffff825585d0 ? Xintr_ioapic_level49 +ffffffff82558610 ? Xintr_ioapic_level50 +ffffffff82558650 ? Xintr_ioapic_level51 +ffffffff82558690 ? Xintr_ioapic_level52 +ffffffff825586d0 ? Xintr_ioapic_level53 +ffffffff82558710 ? Xintr_ioapic_level54 +ffffffff82558750 ? Xintr_ioapic_level55 +ffffffff82558790 ? Xintr_ioapic_level56 +ffffffff825587d0 ? Xintr_ioapic_level57 +ffffffff82558810 ? Xintr_ioapic_level58 +ffffffff82558850 ? Xintr_ioapic_level59 +ffffffff82558890 ? Xintr_ioapic_level60 +ffffffff825588d0 ? Xintr_ioapic_level61 +ffffffff82558910 ? Xintr_ioapic_level62 +ffffffff82558950 ? Xintr_ioapic_level63 +ffffffff82559000 ? codepatch_fill_nop +ffffffff82559000 A __cptext_start +ffffffff82559000 A __kutext_end +ffffffff825590b0 ? codepatch_maprw +ffffffff82559190 ? codepatch_unmaprw +ffffffff82559200 ? codepatch_nop +ffffffff82559360 ? codepatch_replace +ffffffff82559510 ? codepatch_call +ffffffff82559530 ? codepatch_jmp +ffffffff8255a000 A __cptext_end +ffffffff8255a000 A __rodata_start +ffffffff8255a000 C _etext +ffffffff8255a000 C etext +ffffffff8255b000 r seeprom_read +ffffffff8255b004 r icl_mg_pll_find_divisors.div1_vals +ffffffff8255b028 r gen9bc_tgp_ddc_pin_map +ffffffff8255b038 r athn_ac2qid +ffffffff8255b038 r athn_ac2qid +ffffffff8255b038 r athn_ac2qid +ffffffff8255b044 r rtwn_get_rssi.cckoff +ffffffff8255b06c r rsu_ac2qid +ffffffff8255b07c r pckbc_portcmd +ffffffff8255b080 r tht_fifo_write_pad.pad +ffffffff8255b088 r rsu_get_rssi.cckoff +ffffffff8255b09c r adlp_n_revids +ffffffff8255b0ec r apple_iso_trans +ffffffff8255b0f0 r dg2_g12_revid_step_tbl +ffffffff8255b0f8 r wihap_check_tx.txratetable +ffffffff8255b0fc r dmamode +ffffffff8255b124 r gen9_edram_size_mb.sets +ffffffff8255c000 r isomappings +ffffffff8255c080 r unimappings +ffffffff8255c230 r replacements +ffffffff8255fb5f r cmd0646_9_tim_udma +ffffffff825b37eb r pp_r600_decoded_lanes +ffffffff825cebc0 r cmd680_setup_channel.udma_tbl +ffffffff825d6885 r apollo_udma33_tim +ffffffff825dc96d r substchar +ffffffff825dea86 r apollo_udma100_tim +ffffffff8260634a r apollo_udma66_tim +ffffffff8260d836 r apollo_pio_rec +ffffffff8261cbd6 r cy_pio_rec +ffffffff8264c1a7 r apollo_udma133_tim +ffffffff82658de0 R drm_ca +ffffffff82658e08 R drm_filtops +ffffffff82658e38 R drmread_filtops +ffffffff82659000 r vga_emulops +ffffffff82659048 R vga_stdscreen +ffffffff82659078 R vga_stdscreen_mono +ffffffff826590a8 R vga_stdscreen_bf +ffffffff826590d8 R vga_40lscreen +ffffffff82659108 R vga_40lscreen_mono +ffffffff82659138 R vga_40lscreen_bf +ffffffff82659168 R vga_50lscreen +ffffffff82659198 R vga_50lscreen_mono +ffffffff826591c8 R vga_50lscreen_bf +ffffffff826591f8 R vga_screenlist +ffffffff82659208 R vga_screenlist_mono +ffffffff82659218 R vga_accessops +ffffffff82659278 r i945_wm_info +ffffffff826592b0 r bgansitopc +ffffffff826592b8 r pctoansi +ffffffff826592f8 r sdma_offsets +ffffffff826592f8 r sdma_offsets +ffffffff82659328 r iha_rate_tbl +ffffffff82659360 r i830_a_wm_info +ffffffff82659398 r gen9_edram_size_mb.ways +ffffffff82659400 r aggr_periodic_times +ffffffff82659480 r jsl_ehl_revids +ffffffff826594f8 r michael_final.pad +ffffffff82659520 r rt_copysa.maskarray +ffffffff82659528 r i915_wm_info +ffffffff82659530 r amdgpu_ih_clientid_jpeg +ffffffff82659530 r amdgpu_ih_clientid_uvds +ffffffff82659530 r amdgpu_ih_clientid_vcns +ffffffff82659530 r amdgpu_ih_clientid_vcns +ffffffff82659530 r amdgpu_ih_clientid_vcns +ffffffff82659570 r vga_setfontset.cmaptabb +ffffffff82659588 r tgl_revids +ffffffff826595e0 r i830_bc_wm_info +ffffffff82659650 r hsw_activate_psr2.map +ffffffff82659690 r __drm_universal_plane_init.default_modifiers +ffffffff826596a0 r iwn_tid2fifo +ffffffff826596b8 r vga_setfontset.cmaptaba +ffffffff826596c0 r crtc_offsets +ffffffff826596c0 r crtc_offsets +ffffffff826596c0 r crtc_offsets +ffffffff826596e0 r link_speed +ffffffff826596e0 r link_speed +ffffffff826596e0 r link_speed +ffffffff82659758 r rtwn_r88e_get_rssi.cckoff +ffffffff8265a000 R edid_vendors +ffffffff8265a2c0 R edid_nvendors +ffffffff8265a2d0 R edid_products +ffffffff8265a330 R edid_nproducts +ffffffff8265a340 r _edid_modes +ffffffff8265b000 R videomode_list +ffffffff8265c080 R videomode_count +ffffffff8265d000 r ahc_hard_errors +ffffffff8265d080 r critical_sections +ffffffff8265d0b0 r patches +ffffffff8265dd50 r seqprog +ffffffff8265f000 r ahc_switch +ffffffff82660000 r termstat_strings +ffffffff82660020 r critical_sections +ffffffff82660060 r seqprog +ffffffff82660d50 r patches +ffffffff82662000 r ahd_switch +ffffffff82663000 R aic_switch +ffffffff82664000 R adw_switch +ffffffff82665000 R gdt_switch +ffffffff82666000 R twe_switch +ffffffff82667000 R ciss_switch +ffffffff82667030 R ciss_level +ffffffff82667050 R ciss_stat +ffffffff82668000 R ami_switch +ffffffff82668028 R ami_raw_switch +ffffffff82669000 R mfi_switch +ffffffff82669028 R mfi_pd_switch +ffffffff82669050 r mfi_iop_xscale +ffffffff82669080 r mfi_iop_ppc +ffffffff826690b0 r mfi_iop_gen2 +ffffffff826690e0 r mfi_iop_skinny +ffffffff82669110 r mfi_bbu_indicators +ffffffff826691c0 r bwi_rf_calc_nrssi_slope_11b.save_phy_regs +ffffffff826691f0 r chv_oa_mux_regs +ffffffff82669210 r fiji_clock_stretcher_lookup_table +ffffffff82669210 r tonga_clock_stretcher_lookup_table +ffffffff82669230 r iosf_pci_devices +ffffffff82669250 r link_speed +ffffffff82669250 r link_speed +ffffffff82669250 r link_speed +ffffffff82669290 r drm_fb_xfrm.default_dst_pitch +ffffffff82669290 r non_supported_protection +ffffffff82669390 r tgl_uy_revids +ffffffff826693e0 r bwi_phy_noise_11g_rev1 +ffffffff82669460 r cardslot_process_event.antonym_ev +ffffffff826694f0 r gen11_oa_mux_regs +ffffffff826695e0 r ddr2_cycle_tenths +ffffffff82669650 r rtw_intr_rx.ratetbl +ffffffff826696d0 r abm_config +ffffffff82669740 r getbootinfo.ports.30 +ffffffff82669790 r reg_offsets +ffffffff826697a0 r bwi_rf_lo_measure_11g.rf_lo_adjust +ffffffff826697b0 r init_non_clock_fields.look_up +ffffffff826697c0 r uftdi_8u232am_getrate.roundoff +ffffffff82669810 r zyd_rx_data.rates +ffffffff82669820 r ieee80211_ra_valid_tx_mcs.max_mcs +ffffffff82669860 r mmio_invalidate_full.gen8_regs +ffffffff82669890 r bwi_phy_noise_11g +ffffffff826698a0 r hpt366_pio +ffffffff826698d0 r glk_revids +ffffffff82669920 r bwi_rf_calc_nrssi_slope_11g.save_phy3_regs +ffffffff82669940 r ether_crc32_be_update.rev +ffffffff82669940 r rtw_grf5101_mac_crypt.caesar +ffffffff82669990 r snb_b_fdi_train_param +ffffffff8266a000 R qlw_switch +ffffffff8266b000 R isp_2100_risc_code +ffffffff8267dbf0 R isp_2200_risc_code +ffffffff82690990 R isp_2300_risc_code +ffffffff826aa408 R qla_switch +ffffffff826aa430 r qla_regs_2100 +ffffffff826aa460 r qla_regs_2200 +ffffffff826aa490 r qla_regs_23XX +ffffffff826ab000 R ahci_atascsi_methods +ffffffff826ac000 R nvme_switch +ffffffff826ac028 r nvme_ops +ffffffff826ad000 R mpi_switch +ffffffff826ad100 r intel_hpll_vco.elk_vco +ffffffff826ad160 r pin_offsets +ffffffff826ad1c0 r firmware_list +ffffffff826ad220 r atom_arg_shift +ffffffff826ad220 r atom_arg_shift +ffffffff826ad260 r pf_syncookie_wstab +ffffffff826ad280 r ieee80211_media_init.mopts +ffffffff826ad2e0 r add_entropy_words.twist_table +ffffffff826ad380 r urtw_8225v2_txpwr_cck +ffffffff826ad3a0 r bwfm_pci_prio2fifo +ffffffff826ad3a0 r ieee80211_up_to_ac.up_to_ac +ffffffff826ad460 r paritytab +ffffffff826ad460 r x86emu_parity_tab +ffffffff826ad480 r legacy_connector_convert +ffffffff826ad4c0 r gen7_oa_mux_regs +ffffffff826ad4e0 r hsw_oa_mux_regs +ffffffff826ad500 r notetab +ffffffff826ad520 r urtw_8225v2_txpwr_cck_ch14 +ffffffff826ad540 r bwi_rf_calibval.rf_calibvals +ffffffff826ad5e0 r pf_syncookie_msstab +ffffffff826ad640 r xgmi3x16_pcs_err_status_reg_aldebaran +ffffffff826ad6a0 r uath_wme_init.uath_wme_11g +ffffffff826ad6c0 r gen7_oa_b_counters +ffffffff826ad820 r icl_revids +ffffffff826ad8e0 r rtwn_iq_calib_run.reg_adda +ffffffff826ad920 r atom_def_dst +ffffffff826ad920 r atom_def_dst +ffffffff826ad960 r sha256_initial_hash_value +ffffffff826ad9c0 r otus_edca_def +ffffffff826ad9e0 r intel_hpll_vco.blb_vco +ffffffff826adaa0 r epic_pci_subsys_info +ffffffff826adac0 r atom_arg_mask +ffffffff826adac0 r atom_arg_mask +ffffffff826adb20 r butmap +ffffffff826adb60 r GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS +ffffffff826adba0 r comsoft.lsrmap +ffffffff826adbe0 r tulip_mii_phy_readspecific.table +ffffffff826adc00 r kbl_revids +ffffffff826adca0 r intel_hpll_vco.pnv_vco +ffffffff826add00 r dmapageport +ffffffff826addc0 r intel_hpll_vco.ctg_vco +ffffffff826ade80 r drm_calculate_luminance_range.pre_computed_values +ffffffff826ae000 R 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ar9287_1_1_rx_gain_vals_2g +ffffffff826d61a0 r ar9287_1_1_tx_gain_regs +ffffffff826d6200 r ar9287_1_1_tx_gain_vals_2g +ffffffff826d7000 r athn_rates +ffffffff826d8000 r ar9485_1_1_ini +ffffffff826d8068 r ar9485_1_1_serdes +ffffffff826d8080 r ar9380_2_2_ini +ffffffff826d80e8 r ar9380_2_2_serdes +ffffffff826d8100 r ar9380_2_2_rx_gain_wo_xlna +ffffffff826d8120 r ar9380_2_2_rx_gain +ffffffff826d8140 r ar9485_1_1_rx_gain +ffffffff826d8160 r ar9380_2_2_tx_gain_high_ob_db +ffffffff826d8180 r ar9380_2_2_tx_gain_low_ob_db +ffffffff826d81a0 r ar9380_2_2_tx_gain_high_power +ffffffff826d81c0 r ar9380_2_2_tx_gain +ffffffff826d81e0 r ar9485_1_1_tx_gain +ffffffff826d8200 r ar9485_1_1_regs +ffffffff826d8270 r ar9485_1_1_vals_2g40 +ffffffff826d8350 r ar9485_1_1_vals_2g20 +ffffffff826d8430 r ar9485_1_1_cm_regs +ffffffff826d8720 r ar9485_1_1_cm_vals +ffffffff826d8d00 r ar9485_1_1_serdes_regs +ffffffff826d8d0c r ar9485_1_1_serdes_vals +ffffffff826d8d20 r ar9380_2_2_regs +ffffffff826d8db0 r ar9380_2_2_vals_5g20 +ffffffff826d8ed0 r ar9380_2_2_vals_5g40 +ffffffff826d8ff0 r ar9380_2_2_vals_2g40 +ffffffff826d9110 r ar9380_2_2_vals_2g20 +ffffffff826d9230 r ar9380_2_2_cm_regs +ffffffff826d95d0 r ar9380_2_2_cm_vals +ffffffff826d9d00 r ar9380_2_2_fast_clock_regs +ffffffff826d9d20 r ar9380_2_2_fast_clock_vals_5g20 +ffffffff826d9d50 r ar9380_2_2_fast_clock_vals_5g40 +ffffffff826d9d74 r ar9380_2_2_serdes_regs +ffffffff826d9d80 r ar9380_2_2_serdes_vals +ffffffff826d9d90 r ar9380_2_2_rx_gain_regs +ffffffff826d9f90 r ar9380_2_2_rx_gain_wo_xlna_vals +ffffffff826da390 r ar9380_2_2_rx_gain_vals +ffffffff826da790 r ar9485_1_1_rx_gain_regs +ffffffff826da890 r ar9485_1_1_rx_gain_vals +ffffffff826daa90 r ar9380_2_2_tx_gain_regs +ffffffff826dab60 r ar9380_2_2_tx_gain_high_ob_db_vals_5g +ffffffff826dad00 r ar9380_2_2_tx_gain_high_ob_db_vals_2g +ffffffff826daea0 r ar9380_2_2_tx_gain_low_ob_db_vals_5g +ffffffff826db040 r ar9380_2_2_tx_gain_low_ob_db_vals_2g +ffffffff826db1e0 r ar9380_2_2_tx_gain_high_power_vals_5g +ffffffff826db380 r ar9380_2_2_tx_gain_high_power_vals_2g +ffffffff826db520 r ar9380_2_2_tx_gain_vals_5g +ffffffff826db6c0 r ar9380_2_2_tx_gain_vals_2g +ffffffff826db860 r ar9485_1_1_tx_gain_regs +ffffffff826db8f0 r ar9485_1_1_tx_gain_vals_2g +ffffffff826dba10 r ar9380_def_rom +ffffffff826dbe50 r ar9380_def_rom_h112 +ffffffff826dc290 r ar9380_def_rom_h116 +ffffffff826dc6d0 r ar9380_def_rom_x112 +ffffffff826dcb10 r ar9380_def_rom_x113 +ffffffff826dd000 R atw_txthresh_tab_lo +ffffffff826dd050 R atw_txthresh_tab_hi +ffffffff826dd0a0 r atw_attach.empty_macaddr +ffffffff826dd0b0 r atw_attach.type_strings +ffffffff826dd0d0 r atw_rfmd2958_ifn +ffffffff826dd110 r atw_rfmd2958_rf1r +ffffffff826dd150 r atw_rxintr.rate_tbl +ffffffff826de000 r rtw_identify_sta.empty_macaddr +ffffffff826df000 r rtwn_set_key.etherzeroaddr +ffffffff826df010 r rtl8188eu_rf_prog +ffffffff826df030 r rtl8188ftv_rf_prog +ffffffff826df050 r rtl8192e_rf_prog +ffffffff826df080 r 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rt2560_rf2526_hi_r2 +ffffffff826e1180 r rt2560_rf2526_r2 +ffffffff826e11c0 r rt2560_def_bbp +ffffffff826e1200 r rt2560_def_mac +ffffffff826e2000 r rt2661_rf5225_1 +ffffffff826e2300 r rt2661_rf5225_2 +ffffffff826e2600 r rt2661_def_bbp +ffffffff826e2640 r rt2661_def_mac +ffffffff826e3000 r rt2860_rf2850 +ffffffff826e3430 r rt2860_rates +ffffffff826e34f0 r rt3572_def_rf +ffffffff826e3530 r rt3090_def_rf +ffffffff826e3560 r rt5392_def_rf +ffffffff826e35e0 r rt3290_def_rf +ffffffff826e3640 r rt5390_def_rf +ffffffff826e36c0 r rt5390_def_bbp +ffffffff826e36f0 r rt2860_def_mac +ffffffff826e5000 r acx111_reg +ffffffff826e5040 r acx111_rate_map +ffffffff826e6000 r acx100_reg +ffffffff826e6040 r acx100_txpower_rfmd +ffffffff826e6060 r acx100_txpower_maxim +ffffffff826e6080 r xehp_rcs_offsets +ffffffff826e60b0 r gen8_rcs_offsets +ffffffff826e60e0 r hangpic +ffffffff826e6120 r digits +ffffffff826e6120 r pppdumpb.digits +ffffffff826e6120 r pppdumpm.digits +ffffffff826e6140 r dg2_xcs_offsets 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xhci_root_ctrl_methods +ffffffff826ed060 R xhci_root_intr_methods +ffffffff826ed090 R xhci_device_ctrl_methods +ffffffff826ed0c0 R xhci_device_intr_methods +ffffffff826ed0f0 R xhci_device_bulk_methods +ffffffff826ed120 R xhci_device_isoc_methods +ffffffff826ed150 R xhci_devd +ffffffff826ed162 R xhci_confd +ffffffff826ed16b R xhci_ifcd +ffffffff826ed174 R xhci_endpd +ffffffff826ed17b R xhci_endpcd +ffffffff826ed181 R xhci_hubd +ffffffff826f0000 R radio_ca +ffffffff826f1000 R ipmi_ca +ffffffff826f2000 R vscsi_ca +ffffffff826f2028 R vscsi_switch +ffffffff826f2050 R vscsi_filtops +ffffffff826f3000 R mpath_ca +ffffffff826f3028 R mpath_switch +ffffffff826f4000 R softraid_ca +ffffffff826f4028 R sr_switch +ffffffff826f5000 r spdmem_basic_types +ffffffff826f50a0 r spdmem_parity_types +ffffffff826f50e0 r spdmem_ddr4_decode.ddr4_chipsize +ffffffff826f6000 R kstat_rlock_ops +ffffffff826f6010 R kstat_wlock_ops +ffffffff826f6020 R kstat_mutex_ops +ffffffff826f6030 R kstat_cpu_ops +ffffffff826f6040 r kstat_id_tree_RBT_INFO +ffffffff826f6058 R kstat_id_tree_RBT_TYPE +ffffffff826f6060 r kstat_pv_tree_RBT_INFO +ffffffff826f6078 R kstat_pv_tree_RBT_TYPE +ffffffff826f6080 r kstat_nm_tree_RBT_INFO +ffffffff826f6098 R kstat_nm_tree_RBT_TYPE +ffffffff826f7000 r fuse_rd_filtops +ffffffff826f8000 R fusefs_vfsops +ffffffff826f8070 R fusefs_vars +ffffffff826f9000 R fusefs_vops +ffffffff826f9110 R fusefsread_filtops +ffffffff826f9140 R fusefswrite_filtops +ffffffff826f9170 R fusefsvnode_filtops +ffffffff826fa000 r pf_state_tree_RBT_INFO +ffffffff826fa018 R pf_state_tree_RBT_TYPE +ffffffff826fa020 r pf_state_tree_id_RBT_INFO +ffffffff826fa038 R pf_state_tree_id_RBT_TYPE +ffffffff826fa040 r pf_translate_af.zero +ffffffff826fb000 R hfsc_ops +ffffffff826fb038 R ifq_hfsc_ops +ffffffff826fb040 R hfsc_pf_ops +ffffffff826fb088 R pfq_hfsc_ops +ffffffff826fc000 r fqcodel_ops +ffffffff826fc038 R ifq_fqcodel_ops +ffffffff826fc040 r fqcodel_pf_ops +ffffffff826fc088 R pfq_fqcodel_ops +ffffffff826fc090 r codel_intervals +ffffffff826fd000 R pfsync_acts +ffffffff826fe000 R hotplugread_filtops +ffffffff826ff000 R dtps_static +ffffffff82700000 R db_show_all_cmds +ffffffff82700180 R db_show_cmds +ffffffff827004c0 R db_boot_cmds +ffffffff827005a0 R db_command_table +ffffffff82701000 R ddb_vars +ffffffff82702000 R audio_ca +ffffffff82702028 R audioctlread_filtops +ffffffff82702058 R audiowrite_filtops +ffffffff82702088 R audioread_filtops +ffffffff82703000 R midi_ca +ffffffff82703028 R midiwrite_filtops +ffffffff82703058 R midiread_filtops +ffffffff82704000 r mulawtolin16 +ffffffff82704200 r lintomulaw +ffffffff82705000 R randomread_filtops +ffffffff82705030 R randomwrite_filtops +ffffffff82706000 R video_ca +ffffffff82706028 R video_filtops +ffffffff82707000 R cd9660_vfsops +ffffffff82708000 R cd9660_vops +ffffffff82708110 R cd9660_specvops +ffffffff82708220 R cd9660_fifovops +ffffffff82708330 R cd9660read_filtops +ffffffff82708360 R cd9660write_filtops +ffffffff82708390 R cd9660vnode_filtops +ffffffff82709000 R udf_vfsops +ffffffff8270a000 R udf_vops +ffffffff8270a110 r mon_lens +ffffffff8270b000 r month_days +ffffffff8270c000 R execsw +ffffffff8270d000 r shstrtab +ffffffff8270e000 R copyright +ffffffff8270e0c0 r initpaths +ffffffff8270f000 R sysent +ffffffff82711000 R bufq_impls +ffffffff82712000 R kqueueops +ffffffff82712038 R kqread_filtops +ffffffff82712068 R proc_filtops +ffffffff82712098 R file_filtops +ffffffff827120c8 R timer_filtops +ffffffff82712100 R sysfilt_ops +ffffffff82712148 R seltrue_filtops +ffffffff82712178 R dead_filtops +ffffffff827121a8 R badfd_filtops +ffffffff827121d8 r mutex_klistops +ffffffff827121f0 r rwlock_klistops +ffffffff82713000 R kv_exec +ffffffff82714000 R addrmask +ffffffff82715000 r rw_ops +ffffffff82716000 r proc_printit.pstat +ffffffff82717000 R pledge_syscalls +ffffffff82717a60 r pledgenames +ffffffff82717cb0 r pledgereq +ffffffff82718000 r unvname_rbt_RBT_INFO +ffffffff82718018 R unvname_rbt_RBT_TYPE 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pool_lock_ops_mtx +ffffffff82723000 r pselregister.evf +ffffffff8272300c r pselregister.evff +ffffffff82724000 R pipe_rfiltops +ffffffff82724030 R pipe_wfiltops +ffffffff82724060 R pipe_efiltops +ffffffff82724090 r pipeops +ffffffff82725000 R socketops +ffffffff82726000 R sysvsem_vars +ffffffff82727000 R char_type +ffffffff82727100 R ttyread_filtops +ffffffff82727130 R ttywrite_filtops +ffffffff82727160 R ttyexcept_filtops +ffffffff82728000 R ptcread_filtops +ffffffff82728030 R ptcwrite_filtops +ffffffff82728060 R ptcexcept_filtops +ffffffff8272a000 R domains +ffffffff8272b000 R unixdomain +ffffffff8272b050 R unixsw +ffffffff8272c000 R solisten_filtops +ffffffff8272c030 R soread_filtops +ffffffff8272c060 R sowrite_filtops +ffffffff8272c090 R soexcept_filtops +ffffffff8272c0c0 R socket_klistops +ffffffff8272d000 R sun_noname +ffffffff8272d010 R uipc_usrreqs +ffffffff8272d0b0 R uipc_dgram_usrreqs +ffffffff8272d150 R unpstctl_vars +ffffffff8272d180 R unpsqctl_vars +ffffffff8272d1b0 R unpdgctl_vars +ffffffff8272e000 r namecache_rb_cache_RBT_INFO +ffffffff8272e018 R namecache_rb_cache_RBT_TYPE +ffffffff8272f000 R generic_filtops +ffffffff82730000 r buf_rb_bufs_RBT_INFO +ffffffff82730018 R buf_rb_bufs_RBT_TYPE +ffffffff82730020 r typename +ffffffff82731000 R sync_vops +ffffffff82732000 R vnops +ffffffff82733000 R spec_vops +ffffffff82734000 R dead_vops +ffffffff82735000 R fifo_vops +ffffffff82735110 R fiforead_filtops +ffffffff82735140 R fifowrite_filtops +ffffffff82735170 R fifoexcept_filtops +ffffffff82736000 R regyear +ffffffff82736020 R leapyear +ffffffff82736040 r dos2unix +ffffffff82736140 r u2l +ffffffff82736240 r unix2dos +ffffffff82737008 R msdosfs_vfsops +ffffffff82738000 R msdosfs_vops +ffffffff82738110 R msdosfsread_filtops +ffffffff82738140 R msdosfswrite_filtops +ffffffff82738170 R msdosfsvnode_filtops +ffffffff82739000 r _utf_count +ffffffff8273a000 R ntfs_vfsops +ffffffff8273b000 R ntfs_vops +ffffffff8273c000 R bpfread_filtops +ffffffff8273c030 R bpf_mbuf_ops +ffffffff8273d000 r bpf_mem_ops +ffffffff8273e000 R priq_ops +ffffffff8273e038 R ifq_priq_ops +ffffffff8273e040 r ifq_kstat_tpl +ffffffff8273e158 r ifiq_kstat_tpl +ffffffff8273f000 r ether_crc32_le_update.crctab +ffffffff8273f040 r ether_crc32_be_update.crctab +ffffffff82740000 r lcp +ffffffff82740078 r ipcp +ffffffff827400f0 r ipv6cp +ffffffff82740168 r chap +ffffffff827401e0 r pap +ffffffff82741000 R ifmedia_baudrate_descriptions +ffffffff82742000 r fcstab +ffffffff82744000 R tunread_filtops +ffffffff82744030 R tunwrite_filtops +ffffffff82745000 R bridge_brport +ffffffff82746000 R bstp_etheraddr +ffffffff82747000 r eb_tree_RBT_INFO +ffffffff82747018 R eb_tree_RBT_TYPE +ffffffff82748000 r veb_etherbridge_ops +ffffffff82748028 r veb_pf_ipv4 +ffffffff82748040 r veb_pf_ipv6 +ffffffff82749000 r pipex_pppoe_padding +ffffffff8274a000 r rn_addmask.normal_chars +ffffffff8274b000 R route_src +ffffffff8274b010 R route_usrreqs +ffffffff8274b0b0 R routedomain +ffffffff8274b100 R routesw +ffffffff8274c000 R gre_vars +ffffffff8274c030 r mgre_tree_RBT_INFO +ffffffff8274c048 R mgre_tree_RBT_TYPE +ffffffff8274c050 r egre_tree_RBT_INFO +ffffffff8274c068 R egre_tree_RBT_TYPE +ffffffff8274c070 r nvgre_ucast_tree_RBT_INFO +ffffffff8274c088 R nvgre_ucast_tree_RBT_TYPE +ffffffff8274c090 r nvgre_mcast_tree_RBT_INFO +ffffffff8274c0a8 R nvgre_mcast_tree_RBT_TYPE +ffffffff8274c0b0 r eoip_tree_RBT_INFO +ffffffff8274c0c8 R eoip_tree_RBT_TYPE +ffffffff8274c0d0 r nvgre_etherbridge_ops +ffffffff8274d000 r trunk_protos +ffffffff8274e000 R ethermulticastaddr_slowprotocols +ffffffff8274e006 R lacp_info_tlv_template +ffffffff8274e00e R marker_info_tlv_template +ffffffff8274e012 R marker_response_tlv_template +ffffffff8274e020 R lacp_timer_funcs +ffffffff8274f000 r lacp_rxm_state_names +ffffffff8274f040 r lacp_rxm_event_names +ffffffff8274f090 r aggr_port_selected_names +ffffffff8274f0b0 r lacp_mux_state_names +ffffffff8274f0e0 r lacp_mux_event_names +ffffffff8274f128 r lacp_address_slow +ffffffff82750000 r tpmr_pf_ipv4 +ffffffff82750018 r tpmr_pf_ipv6 +ffffffff82751000 r bpe_tree_RBT_INFO +ffffffff82751018 R bpe_tree_RBT_TYPE +ffffffff82751020 r bpe_etherbridge_ops +ffffffff82752000 R pppx_rd_filtops +ffffffff82752030 R pppx_wr_filtops +ffffffff82752060 r pppx_ifs_RBT_INFO +ffffffff82752078 R pppx_ifs_RBT_TYPE +ffffffff82752080 r pppac_rd_filtops +ffffffff827520b0 r pppac_wr_filtops +ffffffff82753000 r vxlan_peers_RBT_INFO +ffffffff82753018 R vxlan_peers_RBT_TYPE +ffffffff82753020 r vxlan_etherbridge_ops +ffffffff82754000 R stoeplitz_cache +ffffffff82755000 R ieee80211_std_rateset_11a +ffffffff82755010 R ieee80211_std_rateset_11b +ffffffff82755020 R ieee80211_std_rateset_11g +ffffffff82755030 R ieee80211_std_ratesets_11n +ffffffff827553b0 R ieee80211_std_ratesets_11ac +ffffffff827556b0 r ieee80211_setbasicrates.basic +ffffffff82755710 r ieee80211_setmode.chanflags +ffffffff82755730 r ieee80211_rate2media.rates +ffffffff827558c0 r ieee80211_media2rate.ieeerates +ffffffff82756000 r Sbox +ffffffff82758000 r ieee80211_ioctl.empty_macaddr +ffffffff82759000 r ieee80211_find_rxnode.zero +ffffffff82759008 r ieee80211_tree_RBT_INFO +ffffffff82759020 R ieee80211_tree_RBT_TYPE +ffffffff82759028 r ieee80211_ess_tree_RBT_INFO +ffffffff82759040 R ieee80211_ess_tree_RBT_TYPE +ffffffff82759048 r ieee80211_do_slow_print.merge_print_intvl +ffffffff8275a020 R ieee80211_edca_table +ffffffff8275a0e0 R ieee80211_qap_edca_table +ffffffff8275b000 R ieee80211_mgt_subtype_name +ffffffff8275b080 R ieee80211_state_name +ffffffff8275b0b0 R ieee80211_phymode_name +ffffffff8275c000 r ieee80211_r_ctry +ffffffff8275cae0 r ieee80211_r_names +ffffffff8275cf80 r ieee80211_r_map +ffffffff8275e000 R zeroin_addr +ffffffff8275f000 R inetdomain +ffffffff8275f050 R inetsw +ffffffff82760000 R divertctl_vars +ffffffff82760030 R divert_usrreqs +ffffffff82761000 R icmpctl_vars +ffffffff82762000 R ipctl_vars +ffffffff82762150 R inetctlerrmap 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enc_xform_null +ffffffff82779280 R auth_hash_hmac_md5_96 +ffffffff827792c8 R auth_hash_hmac_sha1_96 +ffffffff82779310 R auth_hash_hmac_ripemd_160_96 +ffffffff82779358 R auth_hash_hmac_sha2_256_128 +ffffffff827793a0 R auth_hash_hmac_sha2_384_192 +ffffffff827793e8 R auth_hash_hmac_sha2_512_256 +ffffffff82779430 R auth_hash_gmac_aes_128 +ffffffff82779478 R auth_hash_gmac_aes_192 +ffffffff827794c0 R auth_hash_gmac_aes_256 +ffffffff82779508 R auth_hash_chacha20_poly1305 +ffffffff82779550 R comp_algo_deflate +ffffffff8277a000 r IV +ffffffff8277b000 r idgen32_ftable +ffffffff8277c000 r Chacha20_Poly1305_Update.zeroes +ffffffff8277c010 r pad0 +ffffffff8277d000 r null_point +ffffffff8277d020 r base_point +ffffffff8277e000 R mplsdomain +ffffffff8277f000 R mplsctl_vars +ffffffff82780000 r nfs_nodetree_RBT_INFO +ffffffff82780018 R nfs_nodetree_RBT_TYPE +ffffffff82781000 r nfsread_filtops +ffffffff82781030 r nfswrite_filtops +ffffffff82781060 r nfsvnode_filtops +ffffffff82782000 r nfsrv_v3errmap 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uvm_pmr_addr_RBT_TYPE +ffffffff82798020 r uvm_pmr_size_RBT_INFO +ffffffff82798038 R uvm_pmr_size_RBT_TYPE +ffffffff82798040 r uvm_pmemrange_addr_RBT_INFO +ffffffff82798058 R uvm_pmemrange_addr_RBT_TYPE +ffffffff82799000 R uvm_vnodeops +ffffffff82799048 r uvn_flush.interval +ffffffff8279a000 R zeroin6_addr +ffffffff8279b000 R in6addr_any +ffffffff8279b010 R in6addr_loopback +ffffffff8279b020 R in6addr_intfacelocal_allnodes +ffffffff8279b030 R in6addr_linklocal_allnodes +ffffffff8279b040 R in6addr_linklocal_allrouters +ffffffff8279b050 R in6mask0 +ffffffff8279b060 R in6mask32 +ffffffff8279b070 R in6mask64 +ffffffff8279b080 R in6mask96 +ffffffff8279b090 R in6mask128 +ffffffff8279b0a0 R sa6_any +ffffffff8279c000 R divert6ctl_vars +ffffffff8279c030 R divert6_usrreqs +ffffffff8279d000 R inet6domain +ffffffff8279d050 R inet6sw +ffffffff8279e000 R icmpv6ctl_vars +ffffffff8279f000 R inet6ctlerrmap +ffffffff8279f020 R ipv6ctl_vars +ffffffff827a0000 R rip6_usrreqs +ffffffff827a1000 R pfkey_addr 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R scsi_readsafe_cmd +ffffffff827e7000 R scsibus_ca +ffffffff827e7030 R scsi_quirk_patterns +ffffffff827e8000 R cd_ca +ffffffff827e8030 R cd_patterns +ffffffff827e9000 R ch_ca +ffffffff827e9030 R ch_patterns +ffffffff827ea000 R sd_ca +ffffffff827ea030 R sd_patterns +ffffffff827eb000 R st_quirk_patterns +ffffffff827eb210 R st_ca +ffffffff827eb240 R st_patterns +ffffffff827ec000 R uk_ca +ffffffff827ed000 R safte_ca +ffffffff827ee000 R ses_ca +ffffffff827ef000 R sym_ca +ffffffff827ef028 R sym_mpath_sym_ops +ffffffff827ef048 R sym_mpath_asym_ops +ffffffff827f0000 R rdac_ca +ffffffff827f0028 R rdac_mpath_ops +ffffffff827f1000 R emc_ca +ffffffff827f1028 R emc_mpath_ops +ffffffff827f2000 R hds_ca +ffffffff827f2028 R hds_mpath_ops +ffffffff827f3000 R atapiscsi_ca +ffffffff827f3028 r atapiscsi_switch +ffffffff827f4000 R wd_ca +ffffffff827f5000 R atascsi_switch +ffffffff827f6000 R mainbus_ca +ffffffff827f7000 R bios_ca +ffffffff827f8000 R mpbios_ca +ffffffff827f8030 r loc_where +ffffffff827f9000 R mpbios_icu_table +ffffffff827fa000 R cpu_ca +ffffffff827fb000 R lapic_timer_intrclock +ffffffff827fc000 R ioapic_ca +ffffffff827fd000 R efifb_ca +ffffffff827fd028 R efifb_screen_list +ffffffff827fe000 R pvbus_ca +ffffffff827ff000 R pvclock_ca +ffffffff82800000 R vmt_ca +ffffffff82801000 R xen_ca +ffffffff82802000 R xs_errors +ffffffff82803000 R xnf_ca +ffffffff82804000 R xbf_ca +ffffffff82804028 R xbf_switch +ffffffff82805000 R hyperv_ca +ffffffff82805028 R hv_guid_network +ffffffff82805038 R hv_guid_ide +ffffffff82805048 R hv_guid_scsi +ffffffff82805058 R hv_guid_shutdown +ffffffff82805068 R hv_guid_timesync +ffffffff82805078 R hv_guid_heartbeat +ffffffff82805088 R hv_guid_kvp +ffffffff82806000 r kvp_pools +ffffffff82807000 R hvn_ca +ffffffff82808000 R hvs_ca +ffffffff82808028 R hvs_switch +ffffffff82809000 r virtio_device_name +ffffffff8280a000 R vio_ca +ffffffff8280a030 r virtio_net_feature_names +ffffffff8280b000 R vioblk_ca +ffffffff8280b028 R vioblk_switch +ffffffff8280c000 R viomb_ca +ffffffff8280c030 r viomb_feature_names +ffffffff8280d000 R viornd_ca +ffffffff8280e000 R vioscsi_ca +ffffffff8280e028 R vioscsi_switch +ffffffff8280e050 R vioscsi_vq_names +ffffffff8280f000 R vmmci_ca +ffffffff82810000 R pci_ca +ffffffff82811000 r pci_quirks +ffffffff82812000 R pci_subclass_prehistoric +ffffffff82812050 R pci_subclass_mass_storage +ffffffff82812160 R pci_subclass_network +ffffffff82812250 R pci_subclass_display +ffffffff828122d0 R pci_subclass_multimedia +ffffffff82812360 R pci_subclass_memory +ffffffff828123c0 R pci_subclass_bridge +ffffffff82812510 R pci_subclass_communications +ffffffff828125d0 R pci_subclass_system +ffffffff828126c0 R pci_subclass_input +ffffffff82812770 R pci_subclass_dock +ffffffff828127c0 R pci_subclass_processor +ffffffff82812880 R pci_subclass_serialbus +ffffffff82812990 R pci_subclass_wireless +ffffffff82812a70 R pci_subclass_i2o +ffffffff82812aa0 R pci_subclass_satcom +ffffffff82812b20 R pci_subclass_crypto +ffffffff82812b80 R pci_subclass_dasp +ffffffff82812c10 R pci_class +ffffffff82812e20 r pci_known_vendors +ffffffff828143c0 r pci_known_products +ffffffff82837000 R vga_pci_ca +ffffffff82837030 r vga_devs +ffffffff82838000 R ahc_pci_ident_table +ffffffff828385d0 R ahc_pci_ca +ffffffff82839000 R ahd_pci_ident_table +ffffffff82839198 R ahd_num_pci_devs +ffffffff828391a0 R ahd_pci_ca +ffffffff828391d0 r pci_bus_modes +ffffffff82839210 r pci_status_strings +ffffffff82839250 r pci_status_source +ffffffff82839290 r split_status_strings +ffffffff8283a000 R adw_pci_ca +ffffffff8283a028 R adw_pci_devices +ffffffff8283b000 r adw_3550_Default_EEPROM +ffffffff8283b080 r adw_38C0800_Default_EEPROM +ffffffff8283b100 r adw_38C1600_Default_EEPROM +ffffffff8283c000 R adw_asc3550_mcode +ffffffff8283d3a0 R adw_asc3550_mcode_data +ffffffff8283d3b0 R adw_asc38C0800_mcode +ffffffff8283e888 R adw_asc38C0800_mcode_data +ffffffff8283e8a0 R adw_asc38C1600_mcode +ffffffff82840160 R adw_asc38C1600_mcode_data +ffffffff82841000 R twe_pci_ca +ffffffff82841028 R twe_pci_devices +ffffffff82842000 R arc_ca +ffffffff82842028 R arc_switch +ffffffff82842050 r arc_devices +ffffffff82842190 r arc_intel +ffffffff82842198 r arc_marvell +ffffffff828421a0 r arc_lsi +ffffffff828421a8 r arc_marvell2 +ffffffff82843000 R jmb_ca +ffffffff82843030 r jmb_devices +ffffffff82844000 R ahci_pci_ca +ffffffff82844028 R ahci_jmb_ca +ffffffff82844050 r ahci_devices +ffffffff82845000 R nvme_pci_ca +ffffffff82845028 r nvme_msi_blacklist +ffffffff82846000 R ami_pci_ca +ffffffff82846030 r ami_pci_subsys +ffffffff82846270 r ami_pci_vendors +ffffffff82847000 R mfi_pci_ca +ffffffff82847030 r mfi_pci_devices +ffffffff82848000 R mfii_ca +ffffffff82848028 R mfii_switch +ffffffff82848050 R mfii_pd_switch +ffffffff82848078 R mfii_iop_thunderbolt +ffffffff82848088 R mfii_iop_25 +ffffffff82848098 R mfii_iop_35 +ffffffff828480b0 R mfii_devices +ffffffff82848140 r mfi_bbu_indicators +ffffffff82849000 R ips_ca +ffffffff82849028 r ips_ids +ffffffff82849040 r ips_chips +ffffffff82849090 r ips_names +ffffffff82849128 r ips_switch +ffffffff82849150 r ips_pt_switch +ffffffff8284a000 R eap_ca +ffffffff8284a028 R eap1370_hw_if +ffffffff8284a0e0 R eap1371_hw_if +ffffffff8284a198 R eap_midi_hw_if +ffffffff8284a1d0 R eap_devices +ffffffff8284b000 R auacer_pci_devices +ffffffff8284b008 R auacer_ca +ffffffff8284b030 R auacer_hw_if +ffffffff8284c000 R auich_ca +ffffffff8284c028 R auich_hw_if +ffffffff8284c0e0 r auich_devices +ffffffff8284d000 R azalia_ca +ffffffff8284d028 R azalia_hw_if +ffffffff8284d0e0 R azalia_pci_devices +ffffffff8284d110 r pin_devices +ffffffff8284d190 r line_colors +ffffffff8284d210 r wtypes +ffffffff8284e000 r azalia_codec_init_dolby_atmos.atmos_init +ffffffff8284e050 r azalia_codec_init_dolby_atmos.atmos_v23_v25 +ffffffff8284f000 R envy_ca +ffffffff8284f028 R envy_hw_if +ffffffff8284f0e0 R envy_midi_hw_if +ffffffff82850000 R emuxki_devices +ffffffff82850010 R emu_ca +ffffffff82850038 R emuxki_hw_if +ffffffff828500f0 r emuxki_recbuf_sz +ffffffff82850170 r emuxki_recsrc_szreg +ffffffff8285017c r emuxki_recsrc_bufaddrreg +ffffffff82850190 r emuxki_rate_to_pitch.logMagTable +ffffffff82850390 r emuxki_rate_to_pitch.logSlopeTable +ffffffff82851000 R auixp_pci_devices +ffffffff82851010 R auixp_ca +ffffffff82851038 R auixp_hw_if +ffffffff82852000 R clcs_ca +ffffffff82852028 R cs4280_hw_if +ffffffff828520e0 R cs4280_devices +ffffffff82853000 R yds_ca +ffffffff82853028 r yds_hw_if +ffffffff828530e0 r yds_chip_capability_list +ffffffff82853120 r yds_get_lpfk.lpfkt +ffffffff82853160 r yds_get_lpfq.lpfqt +ffffffff82854000 R auvia_ca +ffffffff82854028 R auvia_hw_if +ffffffff828540e0 R auvia_devices +ffffffff828540f0 r auvia_set_params_sub.slottab +ffffffff82855000 R gdt_pci_ca +ffffffff82856000 R ciss_pci_ca +ffffffff82856030 R ciss_pci_devices +ffffffff82857000 R qlw_pci_ca +ffffffff82857030 r qlw_devices +ffffffff82857050 r isp_1040_risc_code +ffffffff8285c9f0 r isp_1080_risc_code +ffffffff82864470 r isp_12160_risc_code +ffffffff8286c000 R qla_pci_ca +ffffffff8286c030 r qla_devices +ffffffff8286d000 R qle_ca +ffffffff8286d028 R qle_switch +ffffffff8286d050 r qle_devices +ffffffff8286d070 r isp_2400_risc_code +ffffffff8289ca50 r isp_2500_risc_code +ffffffff828cf000 R mpi_pci_ca +ffffffff828cf030 r mpi_devices +ffffffff828d0000 R mpii_ca +ffffffff828d0028 R mpii_switch +ffffffff828d0050 r mpii_devices +ffffffff828d1000 R sili_pci_ca +ffffffff828d1030 r sili_devices +ffffffff828d2000 R aq_devices +ffffffff828d2060 R aq_products +ffffffff828d21d0 R aq_fw1x_ops +ffffffff828d21f8 R aq_fw2x_ops +ffffffff828d2220 R aq2_fw_ops +ffffffff828d2248 R aq_ca +ffffffff828d3000 R de_ca +ffffffff828d3030 r tulip_srom_conninfo +ffffffff828d3120 r tulip_mii_phy_attrlist +ffffffff828d31e0 r tulip_21140_znyx_zx34x_boardsw +ffffffff828d3208 r tulip_21040_10baset_only_boardsw +ffffffff828d3230 r tulip_21040_boardsw +ffffffff828d3258 r tulip_2114x_isv_boardsw +ffffffff828d3280 r tulip_21140_smc9332_boardsw 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piix_isp_dma +ffffffff828d9193 r piix_rtc_dma +ffffffff828d9196 r apollo_pio_set +ffffffff828d919b r cmd0643_9_data_tim_pio +ffffffff828d91a0 r cmd0643_9_data_tim_dma +ffffffff828d91a3 r cmd680_channel_map.init_val +ffffffff828d91b1 r cmd680_setup_channel.udma2_tbl +ffffffff828d91b8 r cmd680_setup_channel.dma_tbl +ffffffff828d91be r cmd680_setup_channel.pio_tbl +ffffffff828d91d0 r satalink_ba5_regmap +ffffffff828d9690 r sii3114_chansetup.channel_names +ffffffff828d96b0 r cy_pio_pulse +ffffffff828d96c0 r sis_udma133new_tim +ffffffff828d96e0 r sis_pio133new_tim +ffffffff828d96f4 r sis_dma133new_tim +ffffffff828d9700 r sis_udma66_tim +ffffffff828d9706 r sis_udma100new_tim +ffffffff828d970c r sis_udma133old_tim +ffffffff828d9713 r sis_pio_act +ffffffff828d9718 r sis_pio_rec +ffffffff828d971d r natsemi_pio_pulse +ffffffff828d9722 r natsemi_pio_recover +ffffffff828d9727 r natsemi_dma_pulse +ffffffff828d972a r natsemi_dma_recover +ffffffff828d9730 r scx200_udma33 +ffffffff828d973c r scx200_dma33 +ffffffff828d9750 r scx200_pio33 +ffffffff828d9778 r acer_udma +ffffffff828d977e r acer_pio +ffffffff828d9790 r hpt370_pio +ffffffff828d97a4 r hpt370_dma +ffffffff828d97b0 r hpt370_udma +ffffffff828d97d0 r hpt372_pio +ffffffff828d97e4 r hpt372_dma +ffffffff828d97f0 r hpt372_udma +ffffffff828d980c r hpt366_dma +ffffffff828d9820 r hpt366_udma +ffffffff828d9840 r hpt374_pio +ffffffff828d9854 r hpt374_dma +ffffffff828d9860 r hpt374_udma +ffffffff828d987c r pdc2xx_pa +ffffffff828d9881 r pdc2xx_pb +ffffffff828d9886 r pdc2xx_dma_mb +ffffffff828d9889 r pdc2xx_dma_mc +ffffffff828d988c r pdc2xx_udma_mc +ffffffff828d9892 r acard_act_udma +ffffffff828d9899 r acard_rec_udma +ffffffff828d98a0 r acard_udma_conf +ffffffff828d98a7 r acard_act_dma +ffffffff828d98aa r acard_rec_dma +ffffffff828d98ad r acard_act_pio +ffffffff828d98b2 r acard_rec_pio +ffffffff828d98b7 r nforce_udma +ffffffff828d98be r nforce_pio +ffffffff828d98c3 r ixp_mdma_timings +ffffffff828d98c6 r ixp_pio_timings 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+ffffffff828ed8b8 r ixl_qsfp_ops +ffffffff828ee000 R xge_ca +ffffffff828ee028 R xge_devices +ffffffff828ee030 r xge_fix_mac +ffffffff828ee110 r xge_xena_dtx_cfg +ffffffff828ee170 r xge_herc_dtx_cfg +ffffffff828ef000 R thtc_ca +ffffffff828ef028 R tht_ca +ffffffff828ef050 r thtc_devices +ffffffff828ef068 r tht_link_state.interval +ffffffff828f0000 R myx_ca +ffffffff828f0028 R myx_devices +ffffffff828f1000 R oce_ca +ffffffff828f1030 R oce_devices +ffffffff828f2000 R dc_pci_ca +ffffffff828f3000 R epic_pci_ca +ffffffff828f3028 R epic_pci_devices +ffffffff828f4000 R ti_pci_ca +ffffffff828f4030 R ti_devices +ffffffff828f5000 R ne_pci_ca +ffffffff828f5030 R ne_pci_prod +ffffffff828f6000 R gem_pci_ca +ffffffff828f6030 R gem_pci_devices +ffffffff828f6050 r gem_promhdr +ffffffff828f6052 r gem_promdat +ffffffff828f605a r gem_promdat2 +ffffffff828f7000 R cas_ca +ffffffff828f7028 R cas_pci_devices +ffffffff828f7030 r cas_promhdr +ffffffff828f7032 r cas_promdat_sun +ffffffff828f703a r cas_promdat_ns +ffffffff828f7042 r cas_promdat2 +ffffffff828f8000 R sf_pci_ca +ffffffff828f8028 R sf_pci_products +ffffffff828f9000 R sis_ca +ffffffff828f9028 R sis_devices +ffffffff828fa000 R se_devices +ffffffff828fa008 R se_ca +ffffffff828fb000 R uhci_pci_ca +ffffffff828fc000 R ohci_pci_ca +ffffffff828fd000 R ehci_pci_ca +ffffffff828fe000 R xhci_pci_ca +ffffffff828ff000 R cbb_pci_ca +ffffffff828ff028 r pccbb_pcmcia_do_io_map.pcic_iowidth +ffffffff82900000 R skc_devices +ffffffff82900030 R skc_ca +ffffffff82900058 R sk_ca +ffffffff82901000 R mskc_devices +ffffffff829010a8 R mskc_ca +ffffffff829010d0 R msk_ca +ffffffff82901100 r msk_mib +ffffffff82902000 R puc_pci_ca +ffffffff82903000 R puc_devs +ffffffff82908000 R com_puc_ca +ffffffff82908030 r puc_port_types +ffffffff82909000 R lpt_puc_ca +ffffffff8290a000 R wi_pci_ca +ffffffff8290a030 r wi_pci_products +ffffffff8290b000 R an_pci_ca +ffffffff8290b030 R an_pci_devices +ffffffff8290c000 R iwi_devices +ffffffff8290c010 R iwi_ca +ffffffff8290d000 R wpi_ca +ffffffff8290d028 r wpi_devices +ffffffff8290d030 r wpi_rates +ffffffff8290d050 r wpi_rf_gain_5ghz +ffffffff8290d0a0 r wpi_dsp_gain_5ghz +ffffffff8290d0f0 r wpi_rf_gain_2ghz +ffffffff8290d140 r wpi_dsp_gain_2ghz +ffffffff8290d190 r wpi_pmgt +ffffffff8290d310 r wpi_bands +ffffffff8290e000 R iwn_mcs2ridx +ffffffff8290e020 R iwn_ca +ffffffff8290e050 r iwn_devices +ffffffff8290e0e8 r iwn4965_sensitivity_limits +ffffffff8290e124 r iwn5000_sensitivity_limits +ffffffff8290e160 r iwn5150_sensitivity_limits +ffffffff8290e19c r iwn1000_sensitivity_limits +ffffffff8290e1d8 r iwn6000_sensitivity_limits +ffffffff8290e214 r iwn2000_sensitivity_limits +ffffffff8290e250 r iwn_fw_errmsg +ffffffff8290e340 r iwn4965_set_txpower.tdiv +ffffffff8290e360 r iwn4965_rf_gain_5ghz +ffffffff8290e3d0 r iwn4965_dsp_gain_5ghz +ffffffff8290e440 r iwn4965_dsp_gain_2ghz +ffffffff8290e4b0 r iwn_pmgt +ffffffff8290e6f0 r iwn4965_post_alive.qid2fifo +ffffffff8290e700 r iwn_bands +ffffffff8290e770 r iwn_rates +ffffffff8290e820 r iwn4965_rf_gain_2ghz +ffffffff8290f000 R iwm_nvm_channels +ffffffff8290f030 R iwm_nvm_channels_8000 +ffffffff8290f070 R iwm_rates +ffffffff8290f0d0 R iwm_ht_mcs2ridx +ffffffff8290f110 R iwm_tid_to_ac +ffffffff8290f118 R iwm_ac_to_tx_fifo +ffffffff8290f120 R iwm_nvm_to_read +ffffffff8290f144 r iwm_set_hw_address_8000.reserved_mac +ffffffff8290f180 r iwm_sf_full_timeout +ffffffff8290f1b0 r iwm_sf_full_timeout_def +ffffffff8290f1e0 r advanced_lookup +ffffffff8290f320 r iwm_devices +ffffffff8290f360 R iwm_ca +ffffffff82910000 R iwx_9560_quz_a0_jf_b0_cfg +ffffffff82910020 R iwx_9560_qu_c0_jf_b0_cfg +ffffffff82910040 R iwx_qu_b0_hr1_b0 +ffffffff82910060 R iwx_qu_b0_hr_b0 +ffffffff82910080 R iwx_ax201_cfg_qu_hr +ffffffff829100a0 R iwx_qu_c0_hr1_b0 +ffffffff829100c0 R iwx_qu_c0_hr_b0 +ffffffff829100e0 R iwx_ax201_cfg_qu_c0_hr_b0 +ffffffff82910100 R iwx_quz_a0_hr1_b0 +ffffffff82910120 R iwx_ax201_cfg_quz_hr +ffffffff82910140 R iwx_cfg_so_a0_hr_b0 +ffffffff82910160 R iwx_cfg_quz_a0_hr_b0 +ffffffff82910180 R iwx_2ax_cfg_so_gf_a0 +ffffffff829101a0 R iwx_2ax_cfg_so_gf_a0_long +ffffffff829101c0 R iwx_2ax_cfg_so_gf4_a0 +ffffffff829101e0 R iwx_2ax_cfg_so_gf4_a0_long +ffffffff82910200 R iwx_2ax_cfg_ty_gf_a0 +ffffffff82910220 R iwx_2ax_cfg_so_jf_b0 +ffffffff82910240 R iwx_nvm_channels_8000 +ffffffff82910280 R iwx_rates +ffffffff829102e0 R iwx_mcs2ridx +ffffffff82910320 R iwx_tid_to_ac +ffffffff82910328 R iwx_ac_to_tx_fifo +ffffffff82910330 r iwx_nvm_channels_uhb +ffffffff8291039e r iwx_is_valid_mac_addr.reserved_mac +ffffffff829103b0 r iwx_sf_full_timeout +ffffffff829103e0 r iwx_sf_full_timeout_def +ffffffff82910410 r advanced_lookup +ffffffff82910550 r iwx_devices +ffffffff82910590 r iwx_dev_info_table +ffffffff82910de8 R iwx_ca +ffffffff82911000 R cmpci_ca +ffffffff82911028 R cmpci_hw_if +ffffffff829110e0 r cmpci_rate_table +ffffffff82911120 R cmpci_devices +ffffffff82911130 r cmpci_query_devinfo.mixer_port_names +ffffffff82911160 r cmpci_query_devinfo.mixer_classes +ffffffff82912000 R iha_pci_ca +ffffffff82912028 R iha_switch +ffffffff82913000 R pcscp_ca +ffffffff82914000 R bge_ca +ffffffff82914030 R bge_devices +ffffffff829141b0 r bge_revisions +ffffffff82914610 r bge_majorrevs +ffffffff82915000 R bnx_devices +ffffffff82915020 R bnx_ca +ffffffff82916000 R vge_ca +ffffffff82916028 R vge_devices +ffffffff82917000 R stge_ca +ffffffff82917028 R stge_mii_bitbang_ops +ffffffff82917050 R stge_devices +ffffffff82918000 R nfe_ca +ffffffff82918030 R nfe_devices +ffffffff82919000 R et_devices +ffffffff82919008 R et_ca +ffffffff8291a000 R jme_devices +ffffffff8291a008 R jme_ca +ffffffff8291b000 R age_devices +ffffffff8291b008 R age_ca +ffffffff8291c000 R alc_devices +ffffffff8291c038 R alc_ca +ffffffff8291d000 R ale_devices +ffffffff8291d008 R ale_ca +ffffffff8291e000 R amdpm_ca +ffffffff8291e030 R amdpm_ids +ffffffff8291f000 R bce_ca +ffffffff8291f028 R bce_devices +ffffffff82920000 R ath_pci_ca +ffffffff82921000 R athn_pci_ca +ffffffff82921030 r athn_pci_devices +ffffffff82922000 R atw_pci_ca +ffffffff82922028 R atw_pci_devices +ffffffff82923000 R rtw_pci_ca +ffffffff82923030 R rtw_pci_products +ffffffff82924000 R rtwn_pci_ca +ffffffff82924030 r rtwn_pci_devices +ffffffff82924040 r rtl8188eu_mac +ffffffff829241b0 r rtl8192cu_mac +ffffffff82924310 r rtl8192ce_mac +ffffffff82924458 r rtl8188eu_bb_prog +ffffffff82924480 r rtl8723a_bb_prog +ffffffff829244a8 r rtl8192ce_bb_prog_1t +ffffffff829244d0 r rtl8192ce_bb_prog_2t +ffffffff82924500 r rtl8188eu_bb_regs +ffffffff82924680 r rtl8188eu_bb_vals +ffffffff82924980 r rtl8188eu_agc_vals +ffffffff82924b80 r rtl8723a_bb_regs +ffffffff82924d00 r rtl8723a_bb_vals +ffffffff82924ff0 r rtl8192ce_agc_vals +ffffffff82925270 r rtl8192ce_bb_regs +ffffffff829253f0 r rtl8192ce_bb_vals_1t +ffffffff829256e0 r rtl8192ce_bb_vals_2t +ffffffff82926000 R ral_pci_ca +ffffffff82926030 R ral_pci_devices +ffffffff82927000 R acx_pci_ca +ffffffff82927028 R acx_pci_devices +ffffffff82928000 R pgt_pci_ca +ffffffff82928028 R pgt_pci_devices +ffffffff82929000 R malo_pci_ca +ffffffff82929028 R malo_pci_devices +ffffffff8292a000 R bwi_pci_ca +ffffffff8292a030 R bwi_pci_devices +ffffffff8292b000 R piixpm_ca +ffffffff8292b030 R piixpm_ids +ffffffff8292c000 R vic_ca +ffffffff8292c028 R vic_devices +ffffffff8292d000 R vmx_devices +ffffffff8292d008 R vmx_ca +ffffffff8292d030 r vmx_tx_kstat_tpl +ffffffff8292d0d0 r vmx_kstat_rate +ffffffff8292d0e0 r vmx_rx_kstat_tpl +ffffffff8292e000 R vmwpvs_ca +ffffffff8292e028 R vmwpvs_switch +ffffffff8292f000 R lii_ca +ffffffff8292f028 R lii_devices +ffffffff82930000 R ichiic_ca +ffffffff82930030 R ichiic_ids +ffffffff82931000 R viapm_ca +ffffffff82931030 R viapm_ids +ffffffff82931070 r val_to_temp +ffffffff82931870 r val_to_uV.mult +ffffffff82932000 R amdiic_ca +ffffffff82932028 R amdiic_ids +ffffffff82933000 R nviic_ca +ffffffff82933030 R nviic_ids +ffffffff82934000 R sdhc_pci_ca +ffffffff82935000 R kate_ca +ffffffff82935030 r kate_proc +ffffffff82936000 R km_ca +ffffffff82936030 r km_devices +ffffffff82937000 R ksmn_ca +ffffffff82937030 r ksmn_devices +ffffffff82938000 R iosf_pci_ca +ffffffff82939000 R itherm_devices +ffffffff82939008 R itherm_ca +ffffffff8293a000 R pchtemp_ca +ffffffff8293a030 R pchtemp_devices +ffffffff8293b000 R rtsx_pci_ca +ffffffff8293c000 R xspd_ca +ffffffff8293c028 R xspd_devices +ffffffff8293d000 R virtio_pci_ca +ffffffff8293e000 R dwiic_pci_ca +ffffffff8293e030 R dwiic_pci_ids +ffffffff8293f000 R bwfm_pci_ca +ffffffff8293f030 r bwfm_pci_devices +ffffffff82940000 R ccp_pci_ca +ffffffff82940030 r ccp_pci_devices +ffffffff82941000 R bnxt_devices +ffffffff82941040 R bnxt_ca +ffffffff82942000 R mcx_ca +ffffffff82942030 r mcx_devices +ffffffff82942060 r mcx_rss_config +ffffffff829420d0 r mcx_eth_cap_map +ffffffff829422d0 r mcx_kstat_ppcnt_ieee8023 +ffffffff829422e8 r mcx_kstat_ppcnt_rfc2863 +ffffffff82942300 r mcx_kstat_ppcnt_rfc2819 +ffffffff82942318 r mcx_kstat_ppcnt_rfc3635 +ffffffff82942330 r mcx_ppcnt_ieee8023_tpl +ffffffff829424b0 r mcx_ppcnt_rfc2863_tpl +ffffffff829425c0 r mcx_ppcnt_rfc2819_tpl +ffffffff82942770 r mcx_ppcnt_rfc3635_tpl +ffffffff829428b0 r mcx_kstat_mtmp_tpl +ffffffff82942950 r mcx_kstat_mtmp_rate +ffffffff82942960 r mcx_queue_kstat_tpl +ffffffff82943000 R iavf_ca +ffffffff82943030 r iavf_devices +ffffffff82943040 r iavf_aq_regs +ffffffff829430b0 r iavf_link_speeds +ffffffff82944000 R rge_ca +ffffffff82944028 R rge_devices +ffffffff82944030 r rtl8125_mac_cfg2_ephy +ffffffff82944090 r rge_phy_config_mac_cfg3.mac_cfg3_a438_value +ffffffff829440b0 r rge_phy_config_mac_cfg3.mac_cfg3_b88e_value +ffffffff82944110 r rge_phy_config_mac_cfg4.mac_cfg4_b87c_value +ffffffff82944170 r rtl8125_mac_cfg4_ephy +ffffffff829441e0 r rtl8125_mac_cfg2_mcu +ffffffff82944e80 r rtl8125_mac_cfg3_mcu +ffffffff82945720 r rtl8125_mac_cfg4_mcu +ffffffff82947d10 r rtl8125_mac_cfg5_mcu +ffffffff82948c10 r rtl8125_mac_bps +ffffffff82948f80 r rtl8125b_mac_bps +ffffffff82949120 r rge_kstats_tpl +ffffffff8294a000 R igc_devices +ffffffff8294a040 R igc_ca +ffffffff8294b000 R ngbe_devices +ffffffff8294b008 R ngbe_ca +ffffffff8294c000 R com_pci_ca +ffffffff8294c030 R com_pci_ids +ffffffff8294d000 r agp_attach.agp_max +ffffffff8294d048 R agp_ca +ffffffff8294e000 R intagp_ca +ffffffff8294f000 r drm_plane_create_rotation_property.props +ffffffff82950000 r drm_bridge_priv_state_funcs +ffffffff82952000 r color_encoding_name +ffffffff82952020 r color_range_name +ffffffff82953000 r drm_subpixel_enum_list +ffffffff82953060 r drm_dpms_enum_list +ffffffff829530a0 r drm_dvi_i_select_enum_list +ffffffff829530d0 r drm_dvi_i_subconnector_enum_list +ffffffff82953100 r drm_tv_select_enum_list +ffffffff82953150 r drm_tv_subconnector_enum_list +ffffffff829531a0 r drm_dp_subconnector_enum_list +ffffffff82953210 r drm_link_status_enum_list +ffffffff82953230 r drm_scaling_mode_enum_list +ffffffff82953270 r drm_aspect_ratio_enum_list +ffffffff829532a0 r hdmi_colorspaces +ffffffff82953370 r dp_colorspaces +ffffffff82953450 r drm_content_type_enum_list +ffffffff829534a0 r drm_panel_orientation_enum_list +ffffffff829534e0 r privacy_screen_enum +ffffffff82954000 r drm_crtc_fence_ops +ffffffff82955000 r drm_dmt_modes +ffffffff82957940 r edid_cea_modes_1 +ffffffff8295b4d0 r edid_cea_modes_193 +ffffffff8295c180 r edid_quirk_list +ffffffff8295c350 r edid_4k_modes +ffffffff8295c5b0 r edid_est_modes +ffffffff8295cdb0 r est3_modes +ffffffff8295cf10 r stereo_mandatory_modes +ffffffff8295cf90 r extra_modes +ffffffff8295d000 r drm_encoder_enum_list +ffffffff8295e000 r drm_fbdev_client_funcs +ffffffff8295e020 r drm_fb_helper_generic_funcs +ffffffff8295e028 r drm_fbdev_fb_ops +ffffffff8295f000 r drm_fb_xrgb8888_to_rgb332.dst_pixsize +ffffffff8295f004 r drm_fb_xrgb8888_to_rgb565.dst_pixsize +ffffffff8295f008 r drm_fb_xrgb8888_to_rgb888.dst_pixsize +ffffffff8295f00c r drm_fb_xrgb8888_to_xrgb2101010.dst_pixsize +ffffffff8295f010 r drm_fb_xrgb8888_to_gray8.dst_pixsize +ffffffff8295f014 r drm_fb_rgb888_to_xrgb8888.dst_pixsize +ffffffff8295f018 r drm_fb_rgb565_to_xrgb8888.dst_pixsize +ffffffff82960000 r __drm_format_info.formats +ffffffff82961000 R drm_pgops +ffffffff82962000 r drm_ioctls +ffffffff82964000 r dma_fence_stub_ops +ffffffff82964038 R dma_fence_array_ops +ffffffff82964070 R dma_fence_chain_ops +ffffffff829640a8 R dmabufops +ffffffff829640e0 R syncfileops +ffffffff82965000 r drm_plane_type_enum_list +ffffffff82966000 r drm_mode_status_names +ffffffff82967000 r primary_plane_funcs +ffffffff82967068 r safe_modeset_formats +ffffffff82968000 r orientation_data +ffffffff8296b5c0 r lcd800x1280_rightside_up +ffffffff8296b5d8 r lcd720x1280_rightside_up +ffffffff8296b5f0 r lcd800x1280_leftside_up +ffffffff8296b608 r lcd1080x1920_leftside_up +ffffffff8296b620 r lcd1200x1920_rightside_up +ffffffff8296b638 r gpd_micropc +ffffffff8296b650 r gpd_pocket +ffffffff8296b668 r gpd_pocket2 +ffffffff8296b680 r gpd_win +ffffffff8296b698 r gpd_win2 +ffffffff8296b6b0 r itworks_tw891 +ffffffff8296b6c8 r lcd1600x2560_rightside_up +ffffffff8296b6e0 r onegx1_pro +ffffffff8296b6f8 r lcd1600x2560_leftside_up +ffffffff8296b710 r lcd1280x1920_rightside_up +ffffffff8296b728 r .compoundliteral +ffffffff8296b738 r .compoundliteral.5 +ffffffff8296b760 r .compoundliteral.9 +ffffffff8296b780 r .compoundliteral.17 +ffffffff8296b7c0 r .compoundliteral.21 +ffffffff8296b7e0 r .compoundliteral.23 +ffffffff8296b7f0 r .compoundliteral.25 +ffffffff8296c000 r drm_gem_prime_dmabuf_ops +ffffffff8296e000 r is_hdmi_adaptor.dp_dual_mode_hdmi_id +ffffffff8296f000 r drm_dp_phy_name.phy_names +ffffffff8296f048 r drm_dp_i2c_algo +ffffffff8296f058 r drm_dp_i2c_lock_ops +ffffffff8296f070 r dp_aux_bl_ops +ffffffff8296f090 r dpcd_quirk_list +ffffffff8296f320 r drm_dp_psr_setup_time.psr_setup_time_us +ffffffff82970000 R drm_dp_mst_topology_state_funcs +ffffffff82970020 r drm_dp_mst_req_type_str.req_type_str +ffffffff829701f0 r drm_dp_mst_sideband_tx_state_str.sideband_reason_str +ffffffff82970220 r drm_dp_mst_nak_reason_str.nak_reason_str +ffffffff82970278 r drm_dp_mst_i2c_algo +ffffffff82971000 r hdmi_colorimetry_val +ffffffff82972000 r ttm_bo_init_reserved.sys_mem +ffffffff82973000 r ttm_bo_pipeline_gutting.sys_mem +ffffffff82974018 R ttm_bo_vm_ops +ffffffff82975000 r ttm_range_manager_func +ffffffff82976018 r ttm_kmap_iter_io_ops +ffffffff82976030 r ttm_kmap_iter_linear_io_ops +ffffffff82977000 r ttm_sys_manager_func +ffffffff82978000 r ttm_kmap_iter_tt_ops +ffffffff82979000 r drm_sched_fence_ops_scheduled +ffffffff82979038 r drm_sched_fence_ops_finished +ffffffff8297a000 R ch7017_ops +ffffffff8297b000 R ch7xxx_ops +ffffffff8297b060 r ch7xxx_ids +ffffffff8297c000 R ivch_ops +ffffffff8297c060 r backup_addresses +ffffffff8297d000 R ns2501_ops +ffffffff8297d060 r mode_agnostic_values +ffffffff8297d0e0 r ns2501_modes +ffffffff8297e000 R sil164_ops +ffffffff8297f000 R tfp410_ops +ffffffff82980000 r chv_dpll +ffffffff82980050 r vlv_dpll +ffffffff829800a0 r g4x_dpll +ffffffff829800f0 r pch_dpll +ffffffff82980138 r intel_dp_enc_funcs +ffffffff82981000 r intel_hdmi_enc_funcs +ffffffff82982000 r vlv_primary_formats +ffffffff82982030 r ivb_primary_formats +ffffffff82982050 r i965_primary_formats +ffffffff82982070 r i8xx_primary_formats +ffffffff82982080 r i965_plane_funcs +ffffffff829820e8 r i8xx_plane_funcs +ffffffff82983000 r gen11_dsi_encoder_funcs +ffffffff82983020 r gen11_dsi_connector_funcs +ffffffff82983098 r gen11_dsi_connector_helper_funcs +ffffffff829830e8 r gen11_dsi_host_ops +ffffffff82984000 r intel_plane_helper_funcs +ffffffff82985000 r g4x_audio_funcs +ffffffff82985010 r ilk_audio_funcs +ffffffff82985020 r hsw_audio_funcs +ffffffff82985030 r hdmi_audio_clock +ffffffff829850a0 r dp_aud_n_m +ffffffff82985250 r hdmi_aud_ncts_36bpp +ffffffff82985330 r hdmi_aud_ncts_30bpp +ffffffff82985410 r hdmi_aud_ncts_24bpp +ffffffff82986000 r intel_backlight_device_ops +ffffffff82986018 r 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dg2_shadowed_regs +ffffffff82a03710 r __xehp_fw_ranges +ffffffff82a039e0 r gen12_shadowed_regs +ffffffff82a03b00 r __gen12_fw_ranges +ffffffff82a03d10 r __gen11_fw_ranges +ffffffff82a03ec0 r gen11_shadowed_regs +ffffffff82a03f80 r __gen9_fw_ranges +ffffffff82a04100 r gen8_shadowed_regs +ffffffff82a04130 r __chv_fw_ranges +ffffffff82a041f0 r __gen6_fw_ranges +ffffffff82a04200 r __vlv_fw_ranges +ffffffff82a04258 r uncore_get_fallback +ffffffff82a04260 r uncore_get_normal +ffffffff82a04268 r uncore_get_thread_status +ffffffff82a05000 r atom_op_names +ffffffff82a053e0 r opcode_table +ffffffff82a05b90 r atom_dst_to_src +ffffffff82a05c10 r atom_io_names +ffffffff82a05c40 r atom_table_names +ffffffff82a05e90 r atom_iio_len +ffffffff82a06000 r vga_control_regs +ffffffff82a06018 r atombios_helper_funcs +ffffffff82a07000 r voltage_names +ffffffff82a07020 r pre_emph_names +ffffffff82a08000 r radeon_atom_backlight_ops +ffffffff82a08018 r radeon_atom_enc_funcs +ffffffff82a08038 r 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ci_program_jump_on_start.data +ffffffff82a0d000 r bonaire_io_mc_regs +ffffffff82a0d120 r hawaii_io_mc_regs +ffffffff82a0d1d0 r mc_cg_registers +ffffffff82a0d200 r bonaire_mgcg_cgcg_init +ffffffff82a0d5e0 r bonaire_golden_registers +ffffffff82a0d7d0 r bonaire_golden_common_registers +ffffffff82a0d800 r bonaire_golden_spm_registers +ffffffff82a0d810 r kalindi_mgcg_cgcg_init +ffffffff82a0dab0 r kalindi_golden_registers +ffffffff82a0dc20 r kalindi_golden_common_registers +ffffffff82a0dc50 r kalindi_golden_spm_registers +ffffffff82a0dc60 r godavari_golden_registers +ffffffff82a0dde0 r spectre_mgcg_cgcg_init +ffffffff82a0e200 r spectre_golden_registers +ffffffff82a0e330 r spectre_golden_common_registers +ffffffff82a0e360 r spectre_golden_spm_registers +ffffffff82a0e370 r hawaii_mgcg_cgcg_init +ffffffff82a0e880 r hawaii_golden_registers +ffffffff82a0ea30 r hawaii_golden_common_registers +ffffffff82a0ea6c r hawaii_golden_spm_registers +ffffffff82a0ea80 r spectre_rlc_save_restore_register_list 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evergreen_hdmi_write_sad_regs.eld_reg_to_type +ffffffff82a1e000 r didt_config_kv +ffffffff82a1f000 r barts_io_mc_regs +ffffffff82a1f0f0 r turks_io_mc_regs +ffffffff82a1f1e0 r caicos_io_mc_regs +ffffffff82a1f2d0 r cayman_io_mc_regs +ffffffff82a1f3c0 r cayman_golden_registers +ffffffff82a1f580 r cayman_golden_registers2 +ffffffff82a1f5d0 r dvst_golden_registers +ffffffff82a1f860 r dvst_golden_registers2 +ffffffff82a1f890 r scrapper_golden_registers +ffffffff82a1fd70 r tn_rlc_save_restore_register_list +ffffffff82a1ff60 r cayman_cs_data +ffffffff82a1ffa0 r SECT_CONTEXT_defs +ffffffff82a20020 r SECT_CLEAR_defs +ffffffff82a20040 r SECT_CTRLCONST_defs +ffffffff82a20060 r SECT_CONTEXT_def_2 +ffffffff82a20080 r SECT_CONTEXT_def_4 +ffffffff82a20210 r SECT_CONTEXT_def_5 +ffffffff82a20230 r SECT_CONTEXT_def_1 +ffffffff82a209d0 r SECT_CONTEXT_def_3 +ffffffff82a20ab0 r SECT_CONTEXT_def_6 +ffffffff82a20b90 r SECT_CONTEXT_def_7 +ffffffff82a21018 r SECT_CLEAR_def_1 +ffffffff82a21024 r SECT_CTRLCONST_def_1 +ffffffff82a21030 r cayman_default_state +ffffffff82a22000 r cac_weights_cayman_xt +ffffffff82a22128 r cac_weights_cayman_pro +ffffffff82a22250 r cac_weights_cayman_le +ffffffff82a22380 r cayman_cgcg_cgls_default +ffffffff82a225c0 r cayman_mgcg_default +ffffffff82a22f20 r cayman_sysls_default +ffffffff82a22ff0 r cayman_cgcg_cgls_enable +ffffffff82a23240 r cayman_cgcg_cgls_disable +ffffffff82a234a0 r cayman_mgcg_enable +ffffffff82a23520 r cayman_mgcg_disable +ffffffff82a235a0 r cayman_sysls_enable +ffffffff82a23670 r cayman_sysls_disable +ffffffff82a24000 r rn50_reg_safe_bm +ffffffff82a241a0 r r100_reg_safe_bm +ffffffff82a25000 r r200_reg_safe_bm +ffffffff82a26000 r r300_reg_safe_bm +ffffffff82a27000 r r420_reg_safe_bm +ffffffff82a29000 r color_formats_table +ffffffff82a29480 r r600_reg_safe_bm +ffffffff82a2c000 R r600_utc +ffffffff82a2c040 R r600_dtc +ffffffff82a2c080 r r600_encode_pci_lane_width.encoded_lanes +ffffffff82a2e000 r r100_gfx_ring +ffffffff82a2e070 r r300_gfx_ring +ffffffff82a2e0e0 r rv515_gfx_ring +ffffffff82a2e150 r r600_gfx_ring +ffffffff82a2e1c0 r r600_dma_ring +ffffffff82a2e230 r rv6xx_uvd_ring +ffffffff82a2e2a0 r rv770_uvd_ring +ffffffff82a2e310 r evergreen_gfx_ring +ffffffff82a2e380 r evergreen_dma_ring +ffffffff82a2e3f0 r cayman_gfx_ring +ffffffff82a2e460 r cayman_dma_ring +ffffffff82a2e4d0 r cayman_uvd_ring +ffffffff82a2e540 r trinity_vce_ring +ffffffff82a2e5b0 r si_gfx_ring +ffffffff82a2e620 r si_dma_ring +ffffffff82a2e690 r ci_gfx_ring +ffffffff82a2e700 r ci_cp_ring +ffffffff82a2e770 r ci_dma_ring +ffffffff82a2e7e0 r ci_vce_ring +ffffffff82a2f000 r object_connector_convert +ffffffff82a2f060 r supported_devices_connector_convert +ffffffff82a2f0a0 r supported_devices_connector_object_id_convert +ffffffff82a2f0c0 r thermal_controller_names +ffffffff82a2f100 r pp_lib_thermal_controller_names +ffffffff82a30000 r pin_offsets +ffffffff82a30020 r radeon_audio_acr.hdmi_predefined_acr +ffffffff82a32000 r thermal_controller_names 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radeon_underscan_enum_list +ffffffff82a35130 r radeon_audio_enum_list +ffffffff82a35160 r radeon_dither_enum_list +ffffffff82a35180 r radeon_output_csc_enum_list +ffffffff82a351c0 r radeon_crtc_funcs +ffffffff82a35280 r hpd_names +ffffffff82a352b0 r encoder_names +ffffffff82a353e0 r radeon_afmt_init.eg_offsets +ffffffff82a36000 r aux_offset +ffffffff82a37000 R radeondrm_ca +ffffffff82a37030 r pciidlist +ffffffff82a3b1d0 r kms_driver +ffffffff82a3b2c0 r radeon_ioctls_kms +ffffffff82a3c000 r radeon_fb_helper_funcs +ffffffff82a3c008 r radeonfb_ops +ffffffff82a3d000 R radeon_fence_ops +ffffffff82a3f000 R radeon_gem_object_funcs +ffffffff82a3f060 r radeon_gem_vm_ops +ffffffff82a40000 r radeon_i2c_algo +ffffffff82a40010 r radeon_atom_i2c_algo +ffffffff82a41000 r legacy_helper_funcs +ffffffff82a42000 r radeon_backlight_ops +ffffffff82a42018 r radeon_legacy_lvds_enc_funcs +ffffffff82a42038 r radeon_legacy_lvds_helper_funcs +ffffffff82a420a0 r radeon_legacy_tmds_int_enc_funcs +ffffffff82a420c0 r radeon_legacy_tmds_int_helper_funcs +ffffffff82a42128 r radeon_legacy_primary_dac_enc_funcs +ffffffff82a42148 r radeon_legacy_primary_dac_helper_funcs +ffffffff82a421b0 r radeon_legacy_tv_dac_enc_funcs +ffffffff82a421d0 r radeon_legacy_tv_dac_helper_funcs +ffffffff82a42238 r radeon_legacy_tmds_ext_enc_funcs +ffffffff82a42258 r radeon_legacy_tmds_ext_helper_funcs +ffffffff82a43000 r SLOPE_value +ffffffff82a43030 r YCOEF_EN_value +ffffffff82a43060 r YCOEF_value +ffffffff82a43090 r available_tv_modes +ffffffff82a43110 r hor_timing_NTSC +ffffffff82a43150 r vert_timing_NTSC +ffffffff82a43190 r hor_timing_PAL +ffffffff82a431d0 r vert_timing_PAL +ffffffff82a45000 r radeon_pm_state_type_name +ffffffff82a46000 r radeon_evict_flags.placements +ffffffff82a49000 r rs600_reg_safe_bm +ffffffff82a4b000 r rv515_reg_safe_bm +ffffffff82a4c000 r dll_speed_table +ffffffff82a4d000 r r7xx_golden_registers +ffffffff82a4d090 r r7xx_golden_dyn_gpr_registers +ffffffff82a4d100 r rv770ce_golden_registers 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tahiti_golden_registers2 +ffffffff82a51db0 r pitcairn_golden_registers +ffffffff82a51f00 r pitcairn_golden_rlc_registers +ffffffff82a51f40 r pitcairn_mgcg_cgcg_init +ffffffff82a523b0 r verde_golden_registers +ffffffff82a52620 r verde_golden_rlc_registers +ffffffff82a52660 r verde_mgcg_cgcg_init +ffffffff82a52ae0 r oland_golden_registers +ffffffff82a52c30 r oland_golden_rlc_registers +ffffffff82a52c70 r oland_mgcg_cgcg_init +ffffffff82a53000 r hainan_golden_registers +ffffffff82a5312c r hainan_golden_registers2 +ffffffff82a53140 r hainan_mgcg_cgcg_init +ffffffff82a534b0 r verde_rlc_save_restore_register_list +ffffffff82a53820 r si_cs_data +ffffffff82a53840 r si_SECT_CONTEXT_defs +ffffffff82a538c0 r si_SECT_CONTEXT_def_1 +ffffffff82a53c10 r si_SECT_CONTEXT_def_3 +ffffffff82a53c30 r si_SECT_CONTEXT_def_4 +ffffffff82a53ea4 r si_SECT_CONTEXT_def_5 +ffffffff82a53ea8 r si_SECT_CONTEXT_def_6 +ffffffff82a53eb0 r si_SECT_CONTEXT_def_2 +ffffffff82a542f0 r si_SECT_CONTEXT_def_7 +ffffffff82a546a0 r mc_cg_registers +ffffffff82a546d0 r si_default_state +ffffffff82a55000 r cac_weights_tahiti +ffffffff82a554d0 r lcac_tahiti +ffffffff82a55ba0 r cac_override_tahiti +ffffffff82a55bb4 r powertune_data_tahiti +ffffffff82a55bf0 r dte_data_tahiti +ffffffff82a55cc0 r dte_data_new_zealand +ffffffff82a55d90 r dte_data_malta +ffffffff82a55e60 r lcac_pitcairn +ffffffff82a56530 r cac_override_pitcairn +ffffffff82a56544 r powertune_data_pitcairn +ffffffff82a56580 r lcac_cape_verde +ffffffff82a569d0 r cac_override_cape_verde +ffffffff82a569e4 r powertune_data_cape_verde +ffffffff82a56a20 r cac_weights_cape_verde_pro +ffffffff82a56ef0 r cac_weights_heathrow +ffffffff82a573c0 r cac_weights_chelsea_xt +ffffffff82a57890 r cac_weights_chelsea_pro +ffffffff82a57d60 r cac_weights_cape_verde +ffffffff82a58230 r cac_weights_mars_pro +ffffffff82a58700 r lcac_mars_pro +ffffffff82a58a60 r cac_override_oland +ffffffff82a58a74 r powertune_data_mars_pro +ffffffff82a58ab0 r cac_weights_mars_xt +ffffffff82a58f80 r cac_weights_oland_pro +ffffffff82a59450 r cac_weights_oland_xt +ffffffff82a59920 r lcac_oland +ffffffff82a59c7c r powertune_data_oland +ffffffff82a59cb8 r dte_data_oland +ffffffff82a59d90 r cac_weights_hainan +ffffffff82a5a254 r powertune_data_hainan +ffffffff82a5a290 r dte_data_aruba_pro +ffffffff82a5a360 r dte_data_tahiti_pro +ffffffff82a5a430 r dte_data_curacao_pro +ffffffff82a5a500 r dte_data_neptune_xt +ffffffff82a5a5d0 r dte_data_sun_xt +ffffffff82a5a6a0 r dte_data_venus_xtx +ffffffff82a5a770 r dte_data_venus_xt +ffffffff82a5a840 r dte_data_venus_pro +ffffffff82a5a910 r dte_data_mars_pro +ffffffff82a5b000 r si_program_jump_on_start.data +ffffffff82a5c000 r sumo_dtc +ffffffff82a5d000 r trinity_mgcg_shls_default +ffffffff82a5d380 r trinity_sysls_enable +ffffffff82a5d450 r trinity_sysls_disable +ffffffff82a5f000 r GC_BASE +ffffffff82a5f0a8 r HDP_BASE +ffffffff82a5f150 r MMHUB_BASE +ffffffff82a5f1f8 r ATHUB_BASE +ffffffff82a5f2a0 r NBIO_BASE +ffffffff82a5f348 r MP0_BASE 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+ffffffff82a81000 R amdgpu_vkms_ip_block +ffffffff82a83000 R amdgpu_vm_cpu_funcs +ffffffff82a85000 R amdgpu_vm_sdma_funcs +ffffffff82a86000 R amdgpu_vram_mgr_attr_group +ffffffff82a86018 r amdgpu_vram_mgr_func +ffffffff82a87000 r xgmi_pcs_err_status_reg_arct +ffffffff82a88000 r GC_BASE +ffffffff82a880c0 r HDP_BASE +ffffffff82a88180 r MMHUB_BASE +ffffffff82a88240 r ATHUB_BASE +ffffffff82a88300 r NBIF0_BASE +ffffffff82a883c0 r MP0_BASE +ffffffff82a88480 r MP1_BASE +ffffffff82a88540 r UVD_BASE +ffffffff82a88600 r DF_BASE +ffffffff82a886c0 r OSSSYS_BASE +ffffffff82a88780 r SDMA0_BASE +ffffffff82a88840 r SDMA1_BASE +ffffffff82a88900 r SDMA2_BASE +ffffffff82a889c0 r SDMA3_BASE +ffffffff82a88a80 r SDMA4_BASE +ffffffff82a88b40 r SDMA5_BASE +ffffffff82a88c00 r SDMA6_BASE +ffffffff82a88cc0 r SDMA7_BASE +ffffffff82a88d80 r SMUIO_BASE +ffffffff82a88e40 r THM_BASE +ffffffff82a88f00 r UMC_BASE +ffffffff82a88fc0 r RSMU_BASE +ffffffff82a8a000 r cz_ih_ip_funcs +ffffffff82a8a0a0 R cz_ih_ip_block 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gfx10_SECT_CONTEXT_def_4 -ffffffff82a8fc08 r gfx10_SECT_CONTEXT_def_5 -ffffffff82a8fc10 r gfx10_SECT_CONTEXT_def_6 -ffffffff82a8fc20 r gfx10_SECT_CONTEXT_def_2 -ffffffff82a90060 r gfx10_SECT_CONTEXT_def_7 -ffffffff82a90170 r gfx10_SECT_CONTEXT_def_8 -ffffffff82a904a0 r gfx_v10_0_gfx_funcs -ffffffff82a904e0 r golden_settings_gc_rlc_spm_10_0_nv10 -ffffffff82a96780 r golden_settings_gc_rlc_spm_10_1_nv14 -ffffffff82a9a1a0 r golden_settings_gc_rlc_spm_10_1_2_nv12 -ffffffff82aa0440 r golden_settings_gc_10_1 -ffffffff82aa0800 r golden_settings_gc_10_0_nv10 -ffffffff82aa0800 r golden_settings_gc_10_1_1 -ffffffff82aa0b90 r golden_settings_gc_10_1_2 -ffffffff82aa0b90 r golden_settings_gc_10_1_nv14 -ffffffff82aa0f80 r golden_settings_gc_10_1_2_nv12 -ffffffff82aa0f80 r golden_settings_gc_10_3 -ffffffff82aa1388 r golden_settings_gc_10_3_sienna_cichlid -ffffffff82aa1390 r golden_settings_gc_10_3_2 -ffffffff82aa1780 r golden_settings_gc_10_3_vangogh -ffffffff82aa19e0 r golden_settings_gc_10_3_3 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-ffffffff82aa3d50 r gfx11_SECT_CONTEXT_def_4 -ffffffff82aa3fd0 r gfx11_SECT_CONTEXT_def_7 -ffffffff82aa4438 r gfx_v11_0_gfx_funcs -ffffffff82aa4480 r golden_settings_gc_11_0_1 -ffffffff82aa5000 r gfx_v8_0_ip_funcs -ffffffff82aa50a0 R gfx_v8_0_ip_block -ffffffff82aa50b8 R gfx_v8_1_ip_block -ffffffff82aa50d0 r gfx_v8_0_gfx_funcs -ffffffff82aa5110 r gfx_v8_0_ring_funcs_kiq -ffffffff82aa5230 r gfx_v8_0_ring_funcs_gfx -ffffffff82aa5350 r gfx_v8_0_ring_funcs_compute -ffffffff82aa5470 r amdgpu_gds_reg_offset -ffffffff82aa5570 r gfx_v8_0_eop_irq_funcs -ffffffff82aa5580 r gfx_v8_0_priv_reg_irq_funcs -ffffffff82aa5590 r gfx_v8_0_priv_inst_irq_funcs -ffffffff82aa55a0 r gfx_v8_0_cp_ecc_error_irq_funcs -ffffffff82aa55b0 r gfx_v8_0_sq_irq_funcs -ffffffff82aa55c0 r sq_edc_source_names -ffffffff82aa55f8 r iceland_rlc_funcs -ffffffff82aa5660 r vi_cs_data -ffffffff82aa5680 r vi_SECT_CONTEXT_defs -ffffffff82aa5700 r vi_SECT_CONTEXT_def_1 -ffffffff82aa5a50 r vi_SECT_CONTEXT_def_3 -ffffffff82aa5a70 r vi_SECT_CONTEXT_def_4 -ffffffff82aa5ce4 r vi_SECT_CONTEXT_def_5 -ffffffff82aa5cec r vi_SECT_CONTEXT_def_6 -ffffffff82aa5cf0 r vi_SECT_CONTEXT_def_2 -ffffffff82aa6140 r vi_SECT_CONTEXT_def_7 -ffffffff82aa64f0 r vgpr_init_compute_shader -ffffffff82aa6600 r vgpr_init_regs -ffffffff82aa6690 r sgpr1_init_regs -ffffffff82aa6720 r sgpr2_init_regs -ffffffff82aa67b0 r sec_ded_counter_registers -ffffffff82aa6820 r iceland_mgcg_cgcg_init -ffffffff82aa6b20 r golden_settings_iceland_a11 -ffffffff82aa6be0 r iceland_golden_common_all -ffffffff82aa6c40 r fiji_mgcg_cgcg_init -ffffffff82aa6df0 r golden_settings_fiji_a10 -ffffffff82aa6e80 r fiji_golden_common_all -ffffffff82aa6f00 r tonga_mgcg_cgcg_init -ffffffff82aa7290 r golden_settings_tonga_a11 -ffffffff82aa7350 r tonga_golden_common_all -ffffffff82aa73b0 r golden_settings_vegam_a11 -ffffffff82aa7480 r vegam_golden_common_all -ffffffff82aa74d0 r golden_settings_polaris11_a11 -ffffffff82aa75a0 r polaris11_golden_common_all -ffffffff82aa75f0 r golden_settings_polaris10_a11 -ffffffff82aa76c0 r polaris10_golden_common_all -ffffffff82aa7720 r cz_mgcg_cgcg_init -ffffffff82aa7ab0 r cz_golden_settings_a11 -ffffffff82aa7b40 r cz_golden_common_all -ffffffff82aa7ba0 r stoney_mgcg_cgcg_init -ffffffff82aa7be0 r stoney_golden_settings_a11 -ffffffff82aa7c60 r stoney_golden_common_all -ffffffff82aa8000 R gfx_v9_0_ras_ops -ffffffff82aa8040 r gfx_v9_0_ip_funcs -ffffffff82aa80e0 R gfx_v9_0_ip_block -ffffffff82aa8100 r ras_gfx_subblocks -ffffffff82aa8b80 r gfx_v9_0_edc_counter_regs -ffffffff82aa8f20 r gfx_v9_0_ras_fields -ffffffff82aaa000 r gfx_v9_0_kiq_pm4_funcs -ffffffff82aaa040 r gfx_v9_0_ring_funcs_kiq -ffffffff82aaa160 r gfx_v9_0_ring_funcs_gfx -ffffffff82aaa280 r gfx_v9_0_ring_funcs_compute -ffffffff82aaa3a0 r gfx_v9_0_eop_irq_funcs -ffffffff82aaa3b0 r gfx_v9_0_priv_reg_irq_funcs -ffffffff82aaa3c0 r gfx_v9_0_priv_inst_irq_funcs -ffffffff82aaa3d0 r gfx_v9_0_cp_ecc_error_irq_funcs -ffffffff82aaa3e0 r gfx_v9_0_rlc_funcs -ffffffff82aaa450 r gfx9_cs_data -ffffffff82aaa470 r gfx9_SECT_CONTEXT_defs -ffffffff82aaa500 r gfx9_SECT_CONTEXT_def_1 -ffffffff82aaa850 r gfx9_SECT_CONTEXT_def_3 -ffffffff82aaa860 r gfx9_SECT_CONTEXT_def_4 -ffffffff82aaaad4 r gfx9_SECT_CONTEXT_def_5 -ffffffff82aaaadc r gfx9_SECT_CONTEXT_def_6 -ffffffff82aaaae0 r gfx9_SECT_CONTEXT_def_7 -ffffffff82aaabf0 r gfx9_SECT_CONTEXT_def_2 -ffffffff82aab060 r gfx9_SECT_CONTEXT_def_8 -ffffffff82aab2d0 r vgpr_init_compute_shader_arcturus -ffffffff82aabb60 r vgpr_init_regs_arcturus -ffffffff82aabcf0 r vgpr_init_regs -ffffffff82aabe80 r sgpr1_init_regs -ffffffff82aac010 r sgpr2_init_regs -ffffffff82aac198 r gfx_v9_0_gfx_funcs -ffffffff82aac1e0 r golden_settings_gc_9_0 -ffffffff82aac3c0 r golden_settings_gc_9_0_vg10 -ffffffff82aac570 r golden_settings_gc_9_2_1 -ffffffff82aac6f0 r golden_settings_gc_9_2_1_vg12 -ffffffff82aac830 r golden_settings_gc_9_0_vg20 -ffffffff82aac940 r golden_settings_gc_9_4_1_arct -ffffffff82aaca50 r golden_settings_gc_9_1 -ffffffff82aacc90 r golden_settings_gc_9_1_rv2 -ffffffff82aace60 r golden_settings_gc_9_1_rv1 -ffffffff82aacf10 r golden_settings_gc_9_1_rn -ffffffff82aad030 r golden_settings_gc_9_x_common -ffffffff82aae000 R gfx_v9_4_ras_ops -ffffffff82aae040 r gfx_v9_4_edc_counter_regs -ffffffff82aae420 r gfx_v9_4_ras_fields -ffffffff82ab0000 R vgpr_init_regs_aldebaran -ffffffff82ab01b0 R sgpr112_init_regs_aldebaran -ffffffff82ab0360 R sgpr96_init_regs_aldebaran -ffffffff82ab0510 R sgpr64_init_regs_aldebaran -ffffffff82ab06c0 r golden_settings_gc_9_4_2_alde -ffffffff82ab0720 r golden_settings_gc_9_4_2_alde_die_0 -ffffffff82ab07b0 r golden_settings_gc_9_4_2_alde_die_1 -ffffffff82ab0840 r sgpr112_init_compute_shader_aldebaran -ffffffff82ab0a60 r sgpr96_init_compute_shader_aldebaran -ffffffff82ab0c50 r sgpr64_init_compute_shader_aldebaran -ffffffff82ab0dc0 r vgpr_init_compute_shader_aldebaran -ffffffff82ab16a0 r gfx_v9_4_2_edc_counter_regs -ffffffff82ab1a20 r gfx_v9_4_2_ras_fields -ffffffff82ab33c0 r gfx_v9_4_2_utc_blocks -ffffffff82ab4000 R gfxhub_v1_0_funcs -ffffffff82ab5000 R gfxhub_v2_0_funcs -ffffffff82ab5060 r gfxhub_v2_0_vmhub_funcs -ffffffff82ab5070 r gfxhub_client_ids -ffffffff82ab6000 R gfxhub_v2_1_funcs -ffffffff82ab6060 r gfxhub_v2_1_vmhub_funcs +ffffffff82a8b500 r pin_offsets +ffffffff82a8b520 r fiji_mgcg_cgcg_init +ffffffff82a8b540 r golden_settings_fiji_a10 +ffffffff82a8b570 r tonga_mgcg_cgcg_init +ffffffff82a8b590 r golden_settings_tonga_a11 +ffffffff82a8c000 r crtc_offsets +ffffffff82a8c020 r dce_v11_0_ip_funcs +ffffffff82a8c0c0 R dce_v11_0_ip_block +ffffffff82a8c0d8 R dce_v11_2_ip_block +ffffffff82a8c0f0 r dce_v11_0_display_funcs +ffffffff82a8c150 r hpd_offsets +ffffffff82a8c168 r dce_v11_0_encoder_funcs +ffffffff82a8c188 r dce_v11_0_dac_helper_funcs +ffffffff82a8c1f0 r dce_v11_0_dig_helper_funcs +ffffffff82a8c258 r dce_v11_0_ext_helper_funcs +ffffffff82a8c2c0 r dce_v11_0_audio_write_sad_regs.eld_reg_to_type +ffffffff82a8c2f0 r dce_v11_0_crtc_irq_funcs +ffffffff82a8c300 r dce_v11_0_pageflip_irq_funcs +ffffffff82a8c310 r dce_v11_0_hpd_irq_funcs +ffffffff82a8c320 r interrupt_status_offsets +ffffffff82a8c380 r dce_v11_0_crtc_funcs +ffffffff82a8c440 r dce_v11_0_crtc_helper_funcs +ffffffff82a8c4c0 r vga_control_regs +ffffffff82a8c4e0 r dig_offsets +ffffffff82a8c510 r cz_mgcg_cgcg_init +ffffffff82a8c530 r cz_golden_settings_a11 +ffffffff82a8c550 r stoney_golden_settings_a11 +ffffffff82a8c570 r polaris11_golden_settings_a11 +ffffffff82a8c5b0 r polaris10_golden_settings_a11 +ffffffff82a8d000 R df_v1_7_funcs +ffffffff82a8d070 r df_v1_7_channel_number +ffffffff82a8e000 R df_v3_6_funcs +ffffffff82a8e070 r df_v3_6_channel_number +ffffffff82a8f000 r GC_BASE +ffffffff82a8f0a8 r HDP_BASE +ffffffff82a8f150 r MMHUB_BASE +ffffffff82a8f1f8 r ATHUB_BASE +ffffffff82a8f2a0 r NBIO_BASE +ffffffff82a8f348 r MP0_BASE +ffffffff82a8f3f0 r MP1_BASE +ffffffff82a8f498 r VCN0_BASE +ffffffff82a8f540 r DF_BASE +ffffffff82a8f5e8 r DCN_BASE +ffffffff82a8f690 r OSSSYS_BASE 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+ffffffff82aa3760 r golden_settings_gc_10_3_7 +ffffffff82aa4000 r gfx_v11_0_ip_funcs +ffffffff82aa40a0 R gfx_v11_0_ip_block +ffffffff82aa40b8 r gfx_v11_0_kiq_pm4_funcs +ffffffff82aa40f8 r gfx_v11_0_ring_funcs_kiq +ffffffff82aa4218 r gfx_v11_0_ring_funcs_gfx +ffffffff82aa4338 r gfx_v11_0_ring_funcs_compute +ffffffff82aa4458 r gfx_v11_0_eop_irq_funcs +ffffffff82aa4468 r gfx_v11_0_priv_reg_irq_funcs +ffffffff82aa4478 r gfx_v11_0_priv_inst_irq_funcs +ffffffff82aa4488 r gfx_v11_0_rlc_funcs +ffffffff82aa44f0 r gfx11_cs_data +ffffffff82aa4510 r gfx11_SECT_CONTEXT_defs +ffffffff82aa4590 r gfx11_SECT_CONTEXT_def_1 +ffffffff82aa48f0 r gfx11_SECT_CONTEXT_def_3 +ffffffff82aa4900 r gfx11_SECT_CONTEXT_def_5 +ffffffff82aa4908 r gfx11_SECT_CONTEXT_def_6 +ffffffff82aa4910 r gfx11_SECT_CONTEXT_def_2 +ffffffff82aa4d50 r gfx11_SECT_CONTEXT_def_4 +ffffffff82aa4fd0 r gfx11_SECT_CONTEXT_def_7 +ffffffff82aa5438 r gfx_v11_0_gfx_funcs +ffffffff82aa5480 r golden_settings_gc_11_0_1 +ffffffff82aa6000 r gfx_v8_0_ip_funcs +ffffffff82aa60a0 R gfx_v8_0_ip_block +ffffffff82aa60b8 R gfx_v8_1_ip_block +ffffffff82aa60d0 r gfx_v8_0_gfx_funcs +ffffffff82aa6110 r gfx_v8_0_ring_funcs_kiq +ffffffff82aa6230 r gfx_v8_0_ring_funcs_gfx +ffffffff82aa6350 r gfx_v8_0_ring_funcs_compute +ffffffff82aa6470 r amdgpu_gds_reg_offset +ffffffff82aa6570 r gfx_v8_0_eop_irq_funcs +ffffffff82aa6580 r gfx_v8_0_priv_reg_irq_funcs +ffffffff82aa6590 r gfx_v8_0_priv_inst_irq_funcs +ffffffff82aa65a0 r gfx_v8_0_cp_ecc_error_irq_funcs +ffffffff82aa65b0 r gfx_v8_0_sq_irq_funcs +ffffffff82aa65c0 r sq_edc_source_names +ffffffff82aa65f8 r iceland_rlc_funcs +ffffffff82aa6660 r vi_cs_data +ffffffff82aa6680 r vi_SECT_CONTEXT_defs +ffffffff82aa6700 r vi_SECT_CONTEXT_def_1 +ffffffff82aa6a50 r vi_SECT_CONTEXT_def_3 +ffffffff82aa6a70 r vi_SECT_CONTEXT_def_4 +ffffffff82aa6ce4 r vi_SECT_CONTEXT_def_5 +ffffffff82aa6cec r vi_SECT_CONTEXT_def_6 +ffffffff82aa6cf0 r vi_SECT_CONTEXT_def_2 +ffffffff82aa7140 r vi_SECT_CONTEXT_def_7 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cz_golden_common_all +ffffffff82aa8ba0 r stoney_mgcg_cgcg_init +ffffffff82aa8be0 r stoney_golden_settings_a11 +ffffffff82aa8c60 r stoney_golden_common_all +ffffffff82aa9000 R gfx_v9_0_ras_ops +ffffffff82aa9040 r gfx_v9_0_ip_funcs +ffffffff82aa90e0 R gfx_v9_0_ip_block +ffffffff82aa9100 r ras_gfx_subblocks +ffffffff82aa9b80 r gfx_v9_0_edc_counter_regs +ffffffff82aa9f20 r gfx_v9_0_ras_fields +ffffffff82aab000 r gfx_v9_0_kiq_pm4_funcs +ffffffff82aab040 r gfx_v9_0_ring_funcs_kiq +ffffffff82aab160 r gfx_v9_0_ring_funcs_gfx +ffffffff82aab280 r gfx_v9_0_ring_funcs_compute +ffffffff82aab3a0 r gfx_v9_0_eop_irq_funcs +ffffffff82aab3b0 r gfx_v9_0_priv_reg_irq_funcs +ffffffff82aab3c0 r gfx_v9_0_priv_inst_irq_funcs +ffffffff82aab3d0 r gfx_v9_0_cp_ecc_error_irq_funcs +ffffffff82aab3e0 r gfx_v9_0_rlc_funcs +ffffffff82aab450 r gfx9_cs_data +ffffffff82aab470 r gfx9_SECT_CONTEXT_defs +ffffffff82aab500 r gfx9_SECT_CONTEXT_def_1 +ffffffff82aab850 r gfx9_SECT_CONTEXT_def_3 +ffffffff82aab860 r gfx9_SECT_CONTEXT_def_4 +ffffffff82aabad4 r gfx9_SECT_CONTEXT_def_5 +ffffffff82aabadc r gfx9_SECT_CONTEXT_def_6 +ffffffff82aabae0 r gfx9_SECT_CONTEXT_def_7 +ffffffff82aabbf0 r gfx9_SECT_CONTEXT_def_2 +ffffffff82aac060 r gfx9_SECT_CONTEXT_def_8 +ffffffff82aac2d0 r vgpr_init_compute_shader_arcturus +ffffffff82aacb60 r vgpr_init_regs_arcturus +ffffffff82aaccf0 r vgpr_init_regs +ffffffff82aace80 r sgpr1_init_regs +ffffffff82aad010 r sgpr2_init_regs +ffffffff82aad198 r gfx_v9_0_gfx_funcs +ffffffff82aad1e0 r golden_settings_gc_9_0 +ffffffff82aad3c0 r golden_settings_gc_9_0_vg10 +ffffffff82aad570 r golden_settings_gc_9_2_1 +ffffffff82aad6f0 r golden_settings_gc_9_2_1_vg12 +ffffffff82aad830 r golden_settings_gc_9_0_vg20 +ffffffff82aad940 r golden_settings_gc_9_4_1_arct +ffffffff82aada50 r golden_settings_gc_9_1 +ffffffff82aadc90 r golden_settings_gc_9_1_rv2 +ffffffff82aade60 r golden_settings_gc_9_1_rv1 +ffffffff82aadf10 r golden_settings_gc_9_1_rn +ffffffff82aae030 r golden_settings_gc_9_x_common +ffffffff82aaf000 R gfx_v9_4_ras_ops +ffffffff82aaf040 r gfx_v9_4_edc_counter_regs +ffffffff82aaf420 r gfx_v9_4_ras_fields +ffffffff82ab1000 R vgpr_init_regs_aldebaran +ffffffff82ab11b0 R sgpr112_init_regs_aldebaran +ffffffff82ab1360 R sgpr96_init_regs_aldebaran +ffffffff82ab1510 R sgpr64_init_regs_aldebaran +ffffffff82ab16c0 r golden_settings_gc_9_4_2_alde +ffffffff82ab1720 r golden_settings_gc_9_4_2_alde_die_0 +ffffffff82ab17b0 r golden_settings_gc_9_4_2_alde_die_1 +ffffffff82ab1840 r sgpr112_init_compute_shader_aldebaran +ffffffff82ab1a60 r sgpr96_init_compute_shader_aldebaran +ffffffff82ab1c50 r sgpr64_init_compute_shader_aldebaran +ffffffff82ab1dc0 r vgpr_init_compute_shader_aldebaran +ffffffff82ab26a0 r gfx_v9_4_2_edc_counter_regs +ffffffff82ab2a20 r gfx_v9_4_2_ras_fields +ffffffff82ab43c0 r gfx_v9_4_2_utc_blocks +ffffffff82ab5000 R gfxhub_v1_0_funcs +ffffffff82ab6000 R gfxhub_v2_0_funcs +ffffffff82ab6060 r gfxhub_v2_0_vmhub_funcs ffffffff82ab6070 r gfxhub_client_ids -ffffffff82ab7000 R gfxhub_v3_0_funcs -ffffffff82ab7060 r gfxhub_v3_0_vmhub_funcs +ffffffff82ab7000 R gfxhub_v2_1_funcs +ffffffff82ab7060 r gfxhub_v2_1_vmhub_funcs ffffffff82ab7070 r gfxhub_client_ids -ffffffff82ab8000 R gfxhub_v3_0_3_funcs -ffffffff82ab8060 r gfxhub_v3_0_3_vmhub_funcs +ffffffff82ab8000 R gfxhub_v3_0_funcs +ffffffff82ab8060 r gfxhub_v3_0_vmhub_funcs ffffffff82ab8070 r gfxhub_client_ids -ffffffff82ab9000 R gmc_v10_0_ip_funcs -ffffffff82ab90a0 R gmc_v10_0_ip_block -ffffffff82ab90b8 r gmc_v10_0_gmc_funcs -ffffffff82ab9100 r gmc_v10_0_irq_funcs -ffffffff82ab9110 r gmc_v10_0_ecc_funcs -ffffffff82aba000 R gmc_v11_0_ip_funcs -ffffffff82aba0a0 R gmc_v11_0_ip_block -ffffffff82aba0b8 r gmc_v11_0_gmc_funcs -ffffffff82aba100 r gmc_v11_0_irq_funcs -ffffffff82aba110 r gmc_v11_0_ecc_funcs -ffffffff82abb000 r gmc_v7_0_ip_funcs -ffffffff82abb0a0 R gmc_v7_0_ip_block -ffffffff82abb0b8 R gmc_v7_4_ip_block -ffffffff82abb0d0 r gmc_v7_0_gmc_funcs -ffffffff82abb118 r gmc_v7_0_irq_funcs -ffffffff82abb128 r iceland_mgcg_cgcg_init -ffffffff82abb140 r golden_settings_iceland_a11 -ffffffff82abb170 r mc_cg_registers -ffffffff82abb1a0 r mc_cg_en -ffffffff82abb1d0 r mc_cg_ls_en -ffffffff82abc000 r gmc_v8_0_ip_funcs -ffffffff82abc0a0 R gmc_v8_0_ip_block -ffffffff82abc0b8 R gmc_v8_1_ip_block -ffffffff82abc0d0 R gmc_v8_5_ip_block -ffffffff82abc0e8 r gmc_v8_0_gmc_funcs -ffffffff82abc130 r gmc_v8_0_irq_funcs -ffffffff82abc140 r fiji_mgcg_cgcg_init -ffffffff82abc150 r golden_settings_fiji_a10 -ffffffff82abc180 r tonga_mgcg_cgcg_init -ffffffff82abc190 r golden_settings_tonga_a11 -ffffffff82abc1f0 r golden_settings_polaris11_a11 -ffffffff82abc220 r golden_settings_polaris10_a11 -ffffffff82abc25c r cz_mgcg_cgcg_init -ffffffff82abc270 r stoney_mgcg_cgcg_init -ffffffff82abc290 r golden_settings_stoney_common -ffffffff82abd000 R gmc_v9_0_ip_funcs -ffffffff82abd0a0 R gmc_v9_0_ip_block -ffffffff82abd0b8 r gmc_v9_0_gmc_funcs -ffffffff82abd100 r gmc_v9_0_irq_funcs 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jpeg_v4_0_ip_block -ffffffff82acd0b8 r jpeg_v4_0_dec_ring_vm_funcs -ffffffff82acd1d8 r jpeg_v4_0_irq_funcs -ffffffff82ace000 R lsdma_v6_0_funcs -ffffffff82acf000 R mca_v3_0_mp0_hw_ops -ffffffff82acf040 R mca_v3_0_mp1_hw_ops -ffffffff82acf080 R mca_v3_0_mpio_hw_ops -ffffffff82acf0c0 R mca_v3_0_funcs -ffffffff82ad0000 r mes_v10_1_ip_funcs -ffffffff82ad00a0 R mes_v10_1_ip_block -ffffffff82ad00b8 r mes_v10_1_funcs -ffffffff82ad00e8 r mes_v10_1_ring_funcs -ffffffff82ad1000 r mes_v11_0_ip_funcs -ffffffff82ad10a0 R mes_v11_0_ip_block -ffffffff82ad10b8 r mes_v11_0_funcs -ffffffff82ad10e8 r mes_v11_0_ring_funcs -ffffffff82ad2000 R mmhub_v1_0_funcs -ffffffff82ad2050 r mmhub_v1_0_edc_cnt_regs -ffffffff82ad20c0 r mmhub_v1_0_ras_fields -ffffffff82ad3000 R mmhub_v1_7_funcs -ffffffff82ad3050 r mmhub_v1_7_edc_cnt_regs -ffffffff82ad3250 r mmhub_v1_7_ras_fields -ffffffff82ad49c0 r mmhub_v1_7_ea_err_status_regs -ffffffff82ad5000 R mmhub_v2_0_funcs -ffffffff82ad5050 r mmhub_v2_0_vmhub_funcs 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-ffffffff82ade000 r xgpu_nv_mailbox_ack_irq_funcs -ffffffff82ade010 r xgpu_nv_mailbox_rcv_irq_funcs -ffffffff82ade020 R xgpu_nv_virt_ops -ffffffff82adf000 r xgpu_fiji_mgcg_cgcg_init -ffffffff82adf240 r xgpu_fiji_golden_settings_a10 -ffffffff82adf370 r xgpu_fiji_golden_common_all -ffffffff82adf3f0 r xgpu_tonga_mgcg_cgcg_init -ffffffff82adf810 r xgpu_tonga_golden_settings_a11 -ffffffff82adf9d0 r xgpu_tonga_golden_common_all -ffffffff82adfa28 r xgpu_vi_mailbox_ack_irq_funcs -ffffffff82adfa38 r xgpu_vi_mailbox_rcv_irq_funcs -ffffffff82adfa48 R xgpu_vi_virt_ops -ffffffff82ae0000 r navi10_ih_ip_funcs -ffffffff82ae00a0 R navi10_ih_ip_block -ffffffff82ae00b8 r navi10_ih_funcs -ffffffff82ae00d8 r navi10_ih_self_irq_funcs -ffffffff82ae1000 R nbio_v2_3_hdp_flush_reg -ffffffff82ae1048 R nbio_v2_3_funcs -ffffffff82ae2000 R nbio_v4_3_hdp_flush_reg -ffffffff82ae2048 R nbio_v4_3_funcs -ffffffff82ae2130 R nbio_v4_3_sriov_funcs -ffffffff82ae3000 R nbio_v6_1_hdp_flush_reg -ffffffff82ae3048 R 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jpeg_v3_0_dec_ring_vm_funcs +ffffffff82acd1d8 r jpeg_v3_0_irq_funcs +ffffffff82ace000 r jpeg_v4_0_ip_funcs +ffffffff82ace0a0 R jpeg_v4_0_ip_block +ffffffff82ace0b8 r jpeg_v4_0_dec_ring_vm_funcs +ffffffff82ace1d8 r jpeg_v4_0_irq_funcs +ffffffff82acf000 R lsdma_v6_0_funcs +ffffffff82ad0000 R mca_v3_0_mp0_hw_ops +ffffffff82ad0040 R mca_v3_0_mp1_hw_ops +ffffffff82ad0080 R mca_v3_0_mpio_hw_ops +ffffffff82ad00c0 R mca_v3_0_funcs +ffffffff82ad1000 r mes_v10_1_ip_funcs +ffffffff82ad10a0 R mes_v10_1_ip_block +ffffffff82ad10b8 r mes_v10_1_funcs +ffffffff82ad10e8 r mes_v10_1_ring_funcs +ffffffff82ad2000 r mes_v11_0_ip_funcs +ffffffff82ad20a0 R mes_v11_0_ip_block +ffffffff82ad20b8 r mes_v11_0_funcs +ffffffff82ad20e8 r mes_v11_0_ring_funcs +ffffffff82ad3000 R mmhub_v1_0_funcs +ffffffff82ad3050 r mmhub_v1_0_edc_cnt_regs +ffffffff82ad30c0 r mmhub_v1_0_ras_fields +ffffffff82ad4000 R mmhub_v1_7_funcs +ffffffff82ad4050 r mmhub_v1_7_edc_cnt_regs +ffffffff82ad4250 r mmhub_v1_7_ras_fields +ffffffff82ad59c0 r mmhub_v1_7_ea_err_status_regs +ffffffff82ad6000 R mmhub_v2_0_funcs +ffffffff82ad6050 r mmhub_v2_0_vmhub_funcs +ffffffff82ad6060 r mmhub_client_ids_navi1x +ffffffff82ad6190 r mmhub_client_ids_sienna_cichlid +ffffffff82ad6450 r mmhub_client_ids_beige_goby +ffffffff82ad7000 R mmhub_v2_3_funcs +ffffffff82ad7050 r mmhub_v2_3_vmhub_funcs +ffffffff82ad7060 r mmhub_client_ids_vangogh +ffffffff82ad8000 R mmhub_v3_0_funcs +ffffffff82ad8050 r mmhub_v3_0_vmhub_funcs +ffffffff82ad8060 r mmhub_client_ids_v3_0_0 +ffffffff82ad9000 R mmhub_v3_0_1_funcs +ffffffff82ad9050 r mmhub_v3_0_1_vmhub_funcs +ffffffff82ad9060 r mmhub_client_ids_v3_0_1 +ffffffff82ada000 R mmhub_v3_0_2_funcs +ffffffff82ada050 r mmhub_v3_0_2_vmhub_funcs +ffffffff82ada060 r mmhub_client_ids_v3_0_2 +ffffffff82adb000 R mmhub_v9_4_ras_hw_ops +ffffffff82adb040 R mmhub_v9_4_funcs +ffffffff82adb090 r mmhub_v9_4_edc_cnt_regs +ffffffff82adb330 r mmhub_v9_4_ras_fields +ffffffff82add3b0 r mmhub_v9_4_err_status_regs +ffffffff82ade000 r xgpu_ai_mailbox_ack_irq_funcs +ffffffff82ade010 r xgpu_ai_mailbox_rcv_irq_funcs +ffffffff82ade020 R xgpu_ai_virt_ops +ffffffff82adf000 r xgpu_nv_mailbox_ack_irq_funcs +ffffffff82adf010 r xgpu_nv_mailbox_rcv_irq_funcs +ffffffff82adf020 R xgpu_nv_virt_ops +ffffffff82ae0000 r xgpu_fiji_mgcg_cgcg_init +ffffffff82ae0240 r xgpu_fiji_golden_settings_a10 +ffffffff82ae0370 r xgpu_fiji_golden_common_all +ffffffff82ae03f0 r xgpu_tonga_mgcg_cgcg_init +ffffffff82ae0810 r xgpu_tonga_golden_settings_a11 +ffffffff82ae09d0 r xgpu_tonga_golden_common_all +ffffffff82ae0a28 r xgpu_vi_mailbox_ack_irq_funcs +ffffffff82ae0a38 r xgpu_vi_mailbox_rcv_irq_funcs +ffffffff82ae0a48 R xgpu_vi_virt_ops +ffffffff82ae1000 r navi10_ih_ip_funcs +ffffffff82ae10a0 R navi10_ih_ip_block +ffffffff82ae10b8 r navi10_ih_funcs +ffffffff82ae10d8 r navi10_ih_self_irq_funcs +ffffffff82ae2000 R nbio_v2_3_hdp_flush_reg +ffffffff82ae2048 R nbio_v2_3_funcs +ffffffff82ae3000 R nbio_v4_3_hdp_flush_reg +ffffffff82ae3048 R nbio_v4_3_funcs +ffffffff82ae3130 R nbio_v4_3_sriov_funcs +ffffffff82ae4000 R nbio_v6_1_hdp_flush_reg +ffffffff82ae4048 R nbio_v6_1_funcs +ffffffff82ae5000 R nbio_v7_0_hdp_flush_reg +ffffffff82ae5048 R nbio_v7_0_funcs +ffffffff82ae6000 R nbio_v7_2_hdp_flush_reg +ffffffff82ae6048 R nbio_v7_2_funcs +ffffffff82ae7000 R nbio_v7_4_hdp_flush_reg +ffffffff82ae7048 R nbio_v7_4_ras_hw_ops +ffffffff82ae7088 R nbio_v7_4_funcs +ffffffff82ae7170 r nbio_v7_4_ras_controller_irq_funcs +ffffffff82ae7180 r nbio_v7_4_ras_err_event_athub_irq_funcs +ffffffff82ae8000 R nbio_v7_7_hdp_flush_reg +ffffffff82ae8048 R nbio_v7_7_funcs +ffffffff82ae9000 r nv_common_ip_funcs +ffffffff82ae90a0 R nv_common_ip_block +ffffffff82ae90b8 r nv_asic_funcs +ffffffff82ae9170 r nv_allowed_read_registers +ffffffff82ae92f0 r nv_video_codecs_encode +ffffffff82ae9300 r sc_video_codecs_decode +ffffffff82ae9310 r yc_video_codecs_decode +ffffffff82ae9320 r bg_video_codecs_encode +ffffffff82ae9330 r bg_video_codecs_decode +ffffffff82ae9340 r nv_video_codecs_decode +ffffffff82ae9350 r nv_video_codecs_encode_array +ffffffff82ae9380 r sc_video_codecs_decode_array +ffffffff82ae9420 r yc_video_codecs_decode_array +ffffffff82ae9490 r bg_video_codecs_decode_array +ffffffff82ae94d0 r nv_video_codecs_decode_array +ffffffff82aea000 r psp_v10_0_funcs +ffffffff82aeb000 r psp_v11_0_funcs +ffffffff82aec000 r psp_v11_0_8_funcs +ffffffff82aed000 r psp_v12_0_funcs +ffffffff82aee000 r psp_v13_0_funcs +ffffffff82aef000 r psp_v13_0_4_funcs +ffffffff82af0000 r psp_v3_1_funcs +ffffffff82af1000 r sdma_v2_4_ip_funcs +ffffffff82af10a0 R sdma_v2_4_ip_block +ffffffff82af10b8 r sdma_v2_4_ring_funcs +ffffffff82af11d8 r sdma_v2_4_buffer_funcs +ffffffff82af11f8 r sdma_v2_4_vm_pte_funcs +ffffffff82af1218 r sdma_v2_4_trap_irq_funcs +ffffffff82af1228 r sdma_v2_4_illegal_inst_irq_funcs +ffffffff82af1240 r iceland_mgcg_cgcg_init +ffffffff82af1260 r golden_settings_iceland_a11 +ffffffff82af2000 r sdma_v3_0_ip_funcs +ffffffff82af20a0 R sdma_v3_0_ip_block +ffffffff82af20b8 R sdma_v3_1_ip_block +ffffffff82af20d0 r sdma_v3_0_ring_funcs +ffffffff82af21f0 r sdma_v3_0_buffer_funcs +ffffffff82af2210 r sdma_v3_0_vm_pte_funcs +ffffffff82af2230 r sdma_v3_0_trap_irq_funcs +ffffffff82af2240 r sdma_v3_0_illegal_inst_irq_funcs +ffffffff82af2250 r fiji_mgcg_cgcg_init +ffffffff82af2270 r golden_settings_fiji_a10 +ffffffff82af22d0 r tonga_mgcg_cgcg_init +ffffffff82af22f0 r golden_settings_tonga_a11 +ffffffff82af2370 r golden_settings_polaris11_a11 +ffffffff82af23f0 r golden_settings_polaris10_a11 +ffffffff82af2470 r cz_mgcg_cgcg_init +ffffffff82af2490 r cz_golden_settings_a11 +ffffffff82af2520 r stoney_mgcg_cgcg_init +ffffffff82af2530 r stoney_golden_settings_a11 +ffffffff82af3000 R sdma_v4_0_ip_funcs +ffffffff82af30a0 R sdma_v4_0_ras_hw_ops +ffffffff82af30e0 R sdma_v4_0_ip_block +ffffffff82af30f8 r sdma_v4_0_ring_funcs_2nd_mmhub +ffffffff82af3218 r sdma_v4_0_ring_funcs +ffffffff82af3338 r sdma_v4_0_page_ring_funcs_2nd_mmhub +ffffffff82af3458 r sdma_v4_0_page_ring_funcs +ffffffff82af3578 r sdma_v4_0_buffer_funcs +ffffffff82af3598 r sdma_v4_0_vm_pte_funcs +ffffffff82af35b8 r sdma_v4_0_trap_irq_funcs +ffffffff82af35c8 r sdma_v4_0_illegal_inst_irq_funcs +ffffffff82af35d8 r sdma_v4_0_ecc_irq_funcs +ffffffff82af35e8 r sdma_v4_0_vm_hole_irq_funcs +ffffffff82af35f8 r sdma_v4_0_doorbell_invalid_irq_funcs +ffffffff82af3608 r sdma_v4_0_pool_timeout_irq_funcs +ffffffff82af3618 r sdma_v4_0_srbm_write_irq_funcs +ffffffff82af3630 r golden_settings_sdma_4 +ffffffff82af3890 r golden_settings_sdma_vg10 +ffffffff82af3940 r golden_settings_sdma_vg12 +ffffffff82af39f0 r golden_settings_sdma0_4_2_init +ffffffff82af3a10 r golden_settings_sdma0_4_2 +ffffffff82af3ca0 r golden_settings_sdma1_4_2 +ffffffff82af3f30 r golden_settings_sdma_arct +ffffffff82af4230 r golden_settings_sdma_aldebaran +ffffffff82af43a0 r golden_settings_sdma_4_1 +ffffffff82af44b0 r golden_settings_sdma_rv2 +ffffffff82af44e0 r golden_settings_sdma_rv1 +ffffffff82af4510 r golden_settings_sdma_4_3 +ffffffff82af4600 r sdma_v4_0_ras_fields +ffffffff82af5000 R sdma_v4_4_ras_hw_ops +ffffffff82af5040 r sdma_v4_4_ras_fields +ffffffff82af6000 R sdma_v5_0_ip_funcs +ffffffff82af60a0 R sdma_v5_0_ip_block +ffffffff82af60b8 r sdma_v5_0_ring_funcs +ffffffff82af61d8 r sdma_v5_0_buffer_funcs +ffffffff82af61f8 r sdma_v5_0_vm_pte_funcs +ffffffff82af6218 r sdma_v5_0_trap_irq_funcs +ffffffff82af6228 r sdma_v5_0_illegal_inst_irq_funcs +ffffffff82af6240 r golden_settings_sdma_5 +ffffffff82af6480 r golden_settings_sdma_nv10 +ffffffff82af64b0 r golden_settings_sdma_nv14 +ffffffff82af64e0 r golden_settings_sdma_5_sriov +ffffffff82af66c0 r golden_settings_sdma_nv12 +ffffffff82af6750 r golden_settings_sdma_cyan_skillfish +ffffffff82af7000 R sdma_v5_2_ip_funcs +ffffffff82af70a0 R sdma_v5_2_ip_block +ffffffff82af70b8 r sdma_v5_2_ring_funcs +ffffffff82af71d8 r sdma_v5_2_buffer_funcs +ffffffff82af71f8 r sdma_v5_2_vm_pte_funcs +ffffffff82af7218 r sdma_v5_2_trap_irq_funcs +ffffffff82af7228 r sdma_v5_2_illegal_inst_irq_funcs +ffffffff82af8000 R sdma_v6_0_ip_funcs +ffffffff82af80a0 R sdma_v6_0_ip_block +ffffffff82af80b8 r sdma_v6_0_ring_funcs +ffffffff82af81d8 r sdma_v6_0_buffer_funcs +ffffffff82af81f8 r sdma_v6_0_vm_pte_funcs +ffffffff82af8218 r sdma_v6_0_trap_irq_funcs +ffffffff82af8228 r sdma_v6_0_illegal_inst_irq_funcs +ffffffff82af9000 r smu_v11_0_i2c_algo +ffffffff82af9010 r smu_v11_0_i2c_i2c_lock_ops +ffffffff82af9028 r smu_v11_0_i2c_control_quirks +ffffffff82afa000 R smuio_v11_0_funcs +ffffffff82afb000 R smuio_v11_0_6_funcs +ffffffff82afc000 R smuio_v13_0_funcs +ffffffff82afd000 R smuio_v13_0_6_funcs +ffffffff82afe000 R smuio_v9_0_funcs +ffffffff82aff000 r soc15_common_ip_funcs +ffffffff82aff0a0 R vega10_common_ip_block +ffffffff82aff0b8 r soc15_asic_funcs +ffffffff82aff170 r vega20_asic_funcs +ffffffff82aff230 r soc15_allowed_read_registers +ffffffff82aff3c0 r vega_video_codecs_encode +ffffffff82aff3d0 r vega_video_codecs_decode +ffffffff82aff3e0 r rv_video_codecs_decode +ffffffff82aff3f0 r rn_video_codecs_decode +ffffffff82aff400 r vega_video_codecs_encode_array +ffffffff82aff430 r vega_video_codecs_decode_array +ffffffff82aff4b0 r rv_video_codecs_decode_array +ffffffff82aff540 r rn_video_codecs_decode_array +ffffffff82b00000 r soc21_common_ip_funcs +ffffffff82b000a0 R soc21_common_ip_block +ffffffff82b000b8 r soc21_asic_funcs +ffffffff82b00170 r soc21_allowed_read_registers +ffffffff82b002f0 r vcn_4_0_0_video_codecs_encode_vcn1 +ffffffff82b00300 r vcn_4_0_0_video_codecs_decode_vcn1 +ffffffff82b00310 r vcn_4_0_0_video_codecs_encode_vcn0 +ffffffff82b00320 r vcn_4_0_0_video_codecs_decode_vcn0 +ffffffff82b00330 r vcn_4_0_0_video_codecs_encode_array_vcn1 +ffffffff82b00360 r vcn_4_0_0_video_codecs_decode_array_vcn1 +ffffffff82b003b0 r vcn_4_0_0_video_codecs_encode_array_vcn0 +ffffffff82b003e0 r vcn_4_0_0_video_codecs_decode_array_vcn0 +ffffffff82b01000 r tonga_ih_ip_funcs +ffffffff82b010a0 R tonga_ih_ip_block +ffffffff82b010b8 r tonga_ih_funcs +ffffffff82b02000 R umc_v6_0_funcs +ffffffff82b03000 R umc_v6_1_channel_idx_tbl +ffffffff82b03080 R umc_v6_1_ras_hw_ops +ffffffff82b04000 R umc_v6_7_channel_idx_tbl_second +ffffffff82b04080 R umc_v6_7_channel_idx_tbl_first +ffffffff82b04100 R umc_v6_7_ras_hw_ops +ffffffff82b05000 R umc_v8_10_channelnum_map_colbit_table +ffffffff82b05040 R umc_v8_10_channel_idx_tbl +ffffffff82b050a0 R umc_v8_10_ras_hw_ops +ffffffff82b06000 R umc_v8_7_channel_idx_tbl +ffffffff82b06040 R umc_v8_7_ras_hw_ops +ffffffff82b07000 r uvd_v5_0_ip_funcs +ffffffff82b070a0 R uvd_v5_0_ip_block +ffffffff82b070b8 r uvd_v5_0_ring_funcs +ffffffff82b071d8 r uvd_v5_0_irq_funcs +ffffffff82b08000 r uvd_v6_0_ip_funcs +ffffffff82b080a0 R uvd_v6_0_ip_block +ffffffff82b080b8 R uvd_v6_2_ip_block +ffffffff82b080d0 R uvd_v6_3_ip_block +ffffffff82b080e8 r uvd_v6_0_ring_vm_funcs +ffffffff82b08208 r uvd_v6_0_ring_phys_funcs +ffffffff82b08328 r uvd_v6_0_enc_ring_vm_funcs +ffffffff82b08448 r uvd_v6_0_irq_funcs +ffffffff82b09000 R uvd_v7_0_ip_funcs +ffffffff82b090a0 R uvd_v7_0_ip_block +ffffffff82b090b8 r uvd_v7_0_ring_vm_funcs +ffffffff82b091d8 r uvd_v7_0_enc_ring_vm_funcs +ffffffff82b092f8 r uvd_v7_0_irq_funcs +ffffffff82b0a000 r vce_v3_0_ip_funcs +ffffffff82b0a0a0 R vce_v3_0_ip_block +ffffffff82b0a0b8 R vce_v3_1_ip_block +ffffffff82b0a0d0 R vce_v3_4_ip_block +ffffffff82b0a0e8 r vce_v3_0_ring_vm_funcs +ffffffff82b0a208 r vce_v3_0_ring_phys_funcs +ffffffff82b0a328 r vce_v3_0_irq_funcs +ffffffff82b0b000 R vce_v4_0_ip_funcs +ffffffff82b0b0a0 R vce_v4_0_ip_block +ffffffff82b0b0b8 r vce_v4_0_ring_vm_funcs +ffffffff82b0b1d8 r vce_v4_0_irq_funcs +ffffffff82b0c000 r vcn_v1_0_ip_funcs +ffffffff82b0c0a0 R vcn_v1_0_ip_block +ffffffff82b0c0b8 r vcn_v1_0_dec_ring_vm_funcs +ffffffff82b0c1d8 r vcn_v1_0_enc_ring_vm_funcs +ffffffff82b0c2f8 r vcn_v1_0_irq_funcs +ffffffff82b0d000 r vcn_v2_0_ip_funcs +ffffffff82b0d0a0 R vcn_v2_0_ip_block +ffffffff82b0d0b8 r vcn_v2_0_dec_ring_vm_funcs +ffffffff82b0d1d8 r vcn_v2_0_enc_ring_vm_funcs +ffffffff82b0d2f8 r vcn_v2_0_irq_funcs +ffffffff82b0e000 r vcn_v2_5_ip_funcs +ffffffff82b0e0a0 R vcn_v2_5_ip_block +ffffffff82b0e0b8 r vcn_v2_6_ip_funcs +ffffffff82b0e158 R vcn_v2_6_ip_block +ffffffff82b0e170 R vcn_v2_6_ras_hw_ops +ffffffff82b0e1b0 r vcn_v2_5_dec_ring_vm_funcs +ffffffff82b0e2d0 r vcn_v2_6_dec_ring_vm_funcs +ffffffff82b0e3f0 r vcn_v2_5_enc_ring_vm_funcs +ffffffff82b0e510 r vcn_v2_6_enc_ring_vm_funcs +ffffffff82b0e630 r vcn_v2_5_irq_funcs +ffffffff82b0f000 r vcn_v3_0_ip_funcs +ffffffff82b0f0a0 R vcn_v3_0_ip_block +ffffffff82b0f0b8 r vcn_v3_0_dec_ring_vm_funcs +ffffffff82b0f1d8 r vcn_v3_0_enc_ring_vm_funcs +ffffffff82b0f2f8 r vcn_v3_0_irq_funcs +ffffffff82b10000 r vcn_v4_0_ip_funcs +ffffffff82b100a0 R vcn_v4_0_ip_block +ffffffff82b100b8 r vcn_v4_0_unified_ring_vm_funcs +ffffffff82b101d8 r vcn_v4_0_irq_funcs +ffffffff82b11000 R vega10_ih_ip_funcs +ffffffff82b110a0 R vega10_ih_ip_block +ffffffff82b110b8 r vega10_ih_funcs +ffffffff82b110d8 r vega10_ih_self_irq_funcs +ffffffff82b12000 r GC_BASE +ffffffff82b12064 r HDP_BASE +ffffffff82b120c8 r MMHUB_BASE +ffffffff82b1212c r ATHUB_BASE +ffffffff82b12190 r NBIO_BASE +ffffffff82b121f4 r MP0_BASE +ffffffff82b12258 r MP1_BASE +ffffffff82b122bc r VCE_BASE +ffffffff82b12320 r VCN_BASE +ffffffff82b12384 r DF_BASE +ffffffff82b123e8 r DCE_BASE +ffffffff82b1244c r OSSSYS_BASE +ffffffff82b124b0 r SDMA0_BASE +ffffffff82b12514 r SDMA1_BASE +ffffffff82b12578 r SMUIO_BASE +ffffffff82b125dc r PWR_BASE +ffffffff82b12640 r NBIF_BASE +ffffffff82b126a4 r THM_BASE +ffffffff82b12708 r CLK_BASE +ffffffff82b13000 R vega20_ih_ip_funcs +ffffffff82b130a0 R vega20_ih_ip_block +ffffffff82b130b8 r vega20_ih_funcs +ffffffff82b130d8 r vega20_ih_self_irq_funcs +ffffffff82b14000 r GC_BASE +ffffffff82b14090 r HDP_BASE +ffffffff82b14120 r MMHUB_BASE +ffffffff82b141b0 r ATHUB_BASE +ffffffff82b14240 r NBIO_BASE +ffffffff82b142d0 r MP0_BASE +ffffffff82b14360 r MP1_BASE +ffffffff82b143f0 r UVD_BASE +ffffffff82b14480 r VCE_BASE +ffffffff82b14510 r DF_BASE +ffffffff82b145a0 r DCE_BASE +ffffffff82b14630 r OSSSYS_BASE +ffffffff82b146c0 r SDMA0_BASE +ffffffff82b14750 r SDMA1_BASE +ffffffff82b147e0 r SMUIO_BASE +ffffffff82b14870 r THM_BASE +ffffffff82b14900 r CLK_BASE +ffffffff82b14990 r UMC_BASE +ffffffff82b14a20 r RSMU_BASE +ffffffff82b15000 r vi_common_ip_block +ffffffff82b15018 r vi_common_ip_funcs +ffffffff82b150b8 r vi_asic_funcs +ffffffff82b15170 r vi_allowed_read_registers +ffffffff82b153d0 r topaz_video_codecs_encode +ffffffff82b153e0 r topaz_video_codecs_decode +ffffffff82b153f0 r tonga_video_codecs_encode +ffffffff82b15400 r tonga_video_codecs_decode +ffffffff82b15410 r polaris_video_codecs_encode +ffffffff82b15420 r cz_video_codecs_decode +ffffffff82b15430 r tonga_video_codecs_encode_array +ffffffff82b15450 r tonga_video_codecs_decode_array +ffffffff82b154a0 r polaris_video_codecs_encode_array +ffffffff82b154d0 r cz_video_codecs_decode_array +ffffffff82b15550 r iceland_mgcg_cgcg_init +ffffffff82b15590 r fiji_mgcg_cgcg_init +ffffffff82b155f0 r tonga_mgcg_cgcg_init +ffffffff82b15650 r cz_mgcg_cgcg_init +ffffffff82b15690 r stoney_mgcg_cgcg_init +ffffffff82b16000 r amdgpu_dm_funcs +ffffffff82b160a0 R dm_ip_block +ffffffff82b160b8 R amdgpu_dm_encoder_helper_funcs +ffffffff82b16120 r dm_display_funcs +ffffffff82b16180 r hpd_disconnect_quirk_table +ffffffff82b16ef0 r amdgpu_dm_mode_funcs +ffffffff82b16f38 r amdgpu_dm_encoder_funcs +ffffffff82b16f58 r amdgpu_dm_connector_funcs +ffffffff82b16fd0 r amdgpu_dm_connector_helper_funcs +ffffffff82b17020 r amdgpu_dm_i2c_algo +ffffffff82b171f0 r add_fs_modes.common_rates +ffffffff82b17220 r amdgpu_dm_backlight_ops +ffffffff82b18000 r amdgpu_dm_crtc_funcs +ffffffff82b180c0 r amdgpu_dm_crtc_helper_funcs +ffffffff82b19000 r dm_dtn_log_begin.msg +ffffffff82b1900d r dm_dtn_log_end.msg +ffffffff82b19018 r SYNAPTICS_DEVICE_ID +ffffffff82b1a000 r dm_crtc_irq_funcs +ffffffff82b1a010 r dm_vline0_irq_funcs +ffffffff82b1a020 r dm_dmub_outbox_irq_funcs +ffffffff82b1a030 r dm_vupdate_irq_funcs +ffffffff82b1a040 r dm_dmub_trace_irq_funcs +ffffffff82b1a050 r dm_pageflip_irq_funcs +ffffffff82b1a060 r dm_hpd_irq_funcs +ffffffff82b1b000 r amdgpu_dm_encoder_funcs +ffffffff82b1b020 r dm_mst_cbs +ffffffff82b1b030 r dm_dp_mst_connector_funcs +ffffffff82b1b0a8 r dm_dp_mst_connector_helper_funcs +ffffffff82b1c000 r dm_plane_funcs +ffffffff82b1c068 r dm_plane_helper_funcs ffffffff82b1e000 r vbios_funcs -ffffffff82b23000 r command_table_helper_funcs +ffffffff82b1f000 r vbios_funcs ffffffff82b24000 r command_table_helper_funcs ffffffff82b25000 r command_table_helper_funcs ffffffff82b26000 r command_table_helper_funcs -ffffffff82b27000 r dce80_max_clks_by_state -ffffffff82b27028 r disp_clk_regs -ffffffff82b2707c r disp_clk_shift -ffffffff82b27088 r disp_clk_mask -ffffffff82b28000 r dce110_max_clks_by_state +ffffffff82b27000 r command_table_helper_funcs +ffffffff82b28000 r dce80_max_clks_by_state ffffffff82b28028 r disp_clk_regs ffffffff82b2807c r disp_clk_shift ffffffff82b28088 r disp_clk_mask -ffffffff82b29000 r dce112_max_clks_by_state +ffffffff82b29000 r dce110_max_clks_by_state ffffffff82b29028 r disp_clk_regs ffffffff82b2907c r disp_clk_shift ffffffff82b29088 r disp_clk_mask -ffffffff82b2a000 r dce120_max_clks_by_state -ffffffff82b2b000 r clk_mgr_regs -ffffffff82b2b054 r clk_mgr_shift -ffffffff82b2b060 r clk_mgr_mask +ffffffff82b2a000 r dce112_max_clks_by_state +ffffffff82b2a028 r disp_clk_regs +ffffffff82b2a07c r disp_clk_shift +ffffffff82b2a088 r disp_clk_mask +ffffffff82b2b000 r dce120_max_clks_by_state ffffffff82b2c000 r clk_mgr_regs ffffffff82b2c054 r clk_mgr_shift ffffffff82b2c060 r clk_mgr_mask ffffffff82b2d000 r clk_mgr_regs ffffffff82b2d054 r clk_mgr_shift ffffffff82b2d060 r clk_mgr_mask -ffffffff82b2e000 r lpddr5_wm_table -ffffffff82b2e0c0 r ddr5_wm_table +ffffffff82b2e000 r clk_mgr_regs +ffffffff82b2e054 r clk_mgr_shift +ffffffff82b2e060 r clk_mgr_mask ffffffff82b2f000 r lpddr5_wm_table ffffffff82b2f0c0 r ddr5_wm_table ffffffff82b30000 r lpddr5_wm_table ffffffff82b300c0 r ddr5_wm_table ffffffff82b31000 r lpddr5_wm_table -ffffffff82b310c0 r ddr4_wm_table -ffffffff82b32000 r clk_mgr_regs_dcn321 -ffffffff82b32054 r clk_mgr_shift_dcn321 -ffffffff82b32060 r clk_mgr_mask_dcn321 -ffffffff82b32084 r clk_mgr_regs_dcn32 -ffffffff82b320d8 r clk_mgr_shift_dcn32 -ffffffff82b320e4 r clk_mgr_mask_dcn32 -ffffffff82b33000 r DC_BUILD_ID -ffffffff82b35000 r output_csc_matrix -ffffffff82b350e0 r black_color_format -ffffffff82b36000 r DP_SINK_BRANCH_DEV_NAME_7580 -ffffffff82b37000 r DP_VGA_DONGLE_BRANCH_DEV_NAME -ffffffff82b37006 r DP_DVI_CONVERTER_ID_4 -ffffffff82b3700d r DP_DVI_CONVERTER_ID_5 -ffffffff82b38000 r DP_VGA_LVDS_CONVERTER_ID_2 -ffffffff82b38007 r DP_VGA_LVDS_CONVERTER_ID_3 -ffffffff82b38010 r dp_lt_fallbacks -ffffffff82b39000 r mandatory_dpcd_partitions -ffffffff82b3b000 r dce_funcs -ffffffff82b3c000 r funcs -ffffffff82b3d000 R video_optimized_pixel_rates -ffffffff82b3d1b0 r dce110_clk_src_funcs -ffffffff82b3d1d8 r dce112_clk_src_funcs -ffffffff82b3d200 r dcn20_clk_src_funcs -ffffffff82b3d228 r dcn3_clk_src_funcs -ffffffff82b3d250 r dcn31_clk_src_funcs -ffffffff82b3e000 r dce_funcs -ffffffff82b3e068 r dcn10_funcs -ffffffff82b3e0d0 r dcn20_funcs -ffffffff82b3e138 r dcn21_funcs -ffffffff82b3f000 r dce_ipp_funcs -ffffffff82b40000 r dce110_lnk_enc_funcs -ffffffff82b41000 r dce_mi_funcs -ffffffff82b41090 r dce112_mi_funcs -ffffffff82b41120 r dce120_mi_funcs -ffffffff82b411b0 r pte_settings -ffffffff82b42000 r funcs -ffffffff82b43000 r dce_link_panel_cntl_funcs -ffffffff82b44000 r filter_3tap_16p_upscale -ffffffff82b44040 r filter_3tap_16p_116 -ffffffff82b44080 r filter_3tap_16p_149 -ffffffff82b440c0 r filter_3tap_16p_183 -ffffffff82b44100 r filter_3tap_64p_upscale -ffffffff82b441d0 r filter_3tap_64p_116 -ffffffff82b442a0 r filter_3tap_64p_149 -ffffffff82b44370 r filter_3tap_64p_183 -ffffffff82b44440 r filter_4tap_16p_upscale -ffffffff82b44490 r filter_4tap_16p_116 -ffffffff82b444e0 r filter_4tap_16p_149 -ffffffff82b44530 r filter_4tap_16p_183 -ffffffff82b44580 r filter_4tap_64p_upscale -ffffffff82b44690 r filter_4tap_64p_116 -ffffffff82b447a0 r filter_4tap_64p_149 -ffffffff82b448b0 r filter_4tap_64p_183 -ffffffff82b449c0 r filter_5tap_64p_upscale -ffffffff82b44b10 r filter_5tap_64p_116 -ffffffff82b44c60 r filter_5tap_64p_149 -ffffffff82b44db0 r filter_5tap_64p_183 -ffffffff82b44f00 r filter_6tap_64p_upscale -ffffffff82b45090 r filter_6tap_64p_116 -ffffffff82b45220 r filter_6tap_64p_149 -ffffffff82b453b0 r filter_6tap_64p_183 -ffffffff82b45540 r filter_7tap_64p_upscale -ffffffff82b45710 r filter_7tap_64p_116 -ffffffff82b458e0 r filter_7tap_64p_149 -ffffffff82b45ab0 r filter_7tap_64p_183 -ffffffff82b45c80 r filter_8tap_64p_upscale -ffffffff82b45e90 r filter_8tap_64p_116 -ffffffff82b460a0 r filter_8tap_64p_149 -ffffffff82b462b0 r filter_8tap_64p_183 -ffffffff82b464c0 r filter_2tap_16p -ffffffff82b464f0 r filter_2tap_64p -ffffffff82b47000 r audio_clock_info_table_48bpc -ffffffff82b47190 r audio_clock_info_table_36bpc -ffffffff82b47320 r audio_clock_info_table -ffffffff82b474e0 r dce110_str_enc_funcs -ffffffff82b48000 r global_color_matrix -ffffffff82b480a8 r dce_transform_funcs -ffffffff82b49000 r abm_funcs -ffffffff82b4a000 r psr_funcs -ffffffff82b4a040 r DP_SINK_DEVICE_STR_ID_1 -ffffffff82b4a045 r DP_SINK_DEVICE_STR_ID_2 -ffffffff82b4b000 r reg_offsets -ffffffff82b4c000 r bios_regs -ffffffff82b4c008 r res_cap -ffffffff82b4c050 r clk_src_regs -ffffffff82b4c14c r dmcu_regs -ffffffff82b4c1a8 r dmcu_shift -ffffffff82b4c1bc r dmcu_mask -ffffffff82b4c208 r abm_regs -ffffffff82b4c248 r abm_shift -ffffffff82b4c25c r abm_mask -ffffffff82b4c2b0 r dce100_tg_offsets -ffffffff82b4c2f8 r plane_cap -ffffffff82b4c328 r res_create_funcs -ffffffff82b4c358 r dce100_res_pool_funcs -ffffffff82b4c440 r panel_cntl_regs -ffffffff82b4c460 r panel_cntl_shift -ffffffff82b4c470 r panel_cntl_mask -ffffffff82b4c4b0 r link_enc_regs -ffffffff82b4c870 r link_enc_aux_regs -ffffffff82b4c8c0 r link_enc_hpd_regs -ffffffff82b4c8d8 r link_enc_feature -ffffffff82b4c8e8 r cs_shift -ffffffff82b4c8f4 r cs_mask -ffffffff82b4c920 r mi_regs -ffffffff82b4cc38 r mi_shifts -ffffffff82b4cc80 r mi_masks -ffffffff82b4cda0 r ipp_regs -ffffffff82b4cf98 r ipp_shift -ffffffff82b4cfc0 r ipp_mask -ffffffff82b4d060 r xfm_regs -ffffffff82b4d600 r xfm_shift -ffffffff82b4d660 r xfm_mask -ffffffff82b4d7e0 r opp_regs -ffffffff82b4d930 r opp_shift -ffffffff82b4d95c r opp_mask -ffffffff82b4da10 r aux_engine_regs -ffffffff82b4db00 r aux_mask -ffffffff82b4db60 r aux_shift -ffffffff82b4db80 r i2c_hw_regs -ffffffff82b4dcd0 r i2c_shifts -ffffffff82b4dcfc r i2c_masks -ffffffff82b4dda0 r audio_regs -ffffffff82b4ded4 r audio_shift -ffffffff82b4deec r audio_mask -ffffffff82b4df30 r stream_enc_regs -ffffffff82b4e5dc r se_shift -ffffffff82b4e660 r se_mask -ffffffff82b4e864 r hwseq_reg -ffffffff82b4ea80 r hwseq_shift -ffffffff82b4eb00 r hwseq_mask -ffffffff82b4f000 r reg_offsets -ffffffff82b4f018 r dce110_compressor_funcs -ffffffff82b50000 r dce110_funcs -ffffffff82b502c0 r dce110_private_funcs -ffffffff82b51000 r dce110_mem_input_v_funcs -ffffffff82b51090 r dvmm_Hw_Setting_1DTiling -ffffffff82b51120 r dvmm_Hw_Setting_2DTiling -ffffffff82b511b0 r dvmm_Hw_Setting_Linear -ffffffff82b52000 r global_color_matrix -ffffffff82b520b0 r input_csc_matrix -ffffffff82b53000 r funcs -ffffffff82b54000 r bios_regs -ffffffff82b54008 r dce110_res_pool_funcs -ffffffff82b540f0 r clk_src_regs -ffffffff82b541ec r dmcu_regs -ffffffff82b54248 r dmcu_shift -ffffffff82b5425c r dmcu_mask -ffffffff82b542a8 r abm_regs -ffffffff82b542e8 r abm_shift -ffffffff82b542fc r abm_mask -ffffffff82b54350 r dce110_tg_offsets -ffffffff82b54398 r res_create_funcs -ffffffff82b543c8 r plane_cap -ffffffff82b543f4 r underlay_plane_cap -ffffffff82b54420 r stoney_resource_cap -ffffffff82b5445c r carrizo_resource_cap -ffffffff82b544a0 r panel_cntl_regs -ffffffff82b544c0 r panel_cntl_shift -ffffffff82b544d0 r panel_cntl_mask -ffffffff82b54510 r link_enc_regs -ffffffff82b548d0 r link_enc_aux_regs -ffffffff82b54920 r link_enc_hpd_regs -ffffffff82b54938 r link_enc_feature -ffffffff82b54948 r cs_shift -ffffffff82b54954 r cs_mask -ffffffff82b54980 r mi_regs -ffffffff82b54b0c r mi_shifts -ffffffff82b54b54 r mi_masks -ffffffff82b54c70 r ipp_regs -ffffffff82b54d6c r ipp_shift -ffffffff82b54d94 r ipp_mask -ffffffff82b54e30 r xfm_regs -ffffffff82b55100 r xfm_shift -ffffffff82b55160 r xfm_mask -ffffffff82b552e0 r opp_regs -ffffffff82b55430 r opp_shift -ffffffff82b5545c r opp_mask -ffffffff82b55510 r aux_engine_regs -ffffffff82b55600 r aux_mask -ffffffff82b55660 r aux_shift -ffffffff82b55680 r i2c_hw_regs -ffffffff82b557d0 r i2c_shifts -ffffffff82b557fc r i2c_masks -ffffffff82b558a0 r audio_regs -ffffffff82b559d4 r audio_shift -ffffffff82b559ec r audio_mask -ffffffff82b55a30 r stream_enc_regs -ffffffff82b55d0c r se_shift -ffffffff82b55d90 r se_mask -ffffffff82b55f94 r hwseq_stoney_reg -ffffffff82b561b0 r hwseq_cz_reg -ffffffff82b563cc r hwseq_shift -ffffffff82b5644c r hwseq_mask -ffffffff82b57000 r dce110_tg_funcs -ffffffff82b58000 r dce110_tg_v_funcs -ffffffff82b59000 r dce110_xfmv_funcs -ffffffff82b5a000 r reg_offsets +ffffffff82b310c0 r ddr5_wm_table +ffffffff82b32000 r lpddr5_wm_table +ffffffff82b320c0 r ddr4_wm_table +ffffffff82b33000 r clk_mgr_regs_dcn321 +ffffffff82b33054 r clk_mgr_shift_dcn321 +ffffffff82b33060 r clk_mgr_mask_dcn321 +ffffffff82b33084 r clk_mgr_regs_dcn32 +ffffffff82b330d8 r clk_mgr_shift_dcn32 +ffffffff82b330e4 r clk_mgr_mask_dcn32 +ffffffff82b34000 r DC_BUILD_ID +ffffffff82b36000 r output_csc_matrix +ffffffff82b360e0 r black_color_format +ffffffff82b37000 r DP_SINK_BRANCH_DEV_NAME_7580 +ffffffff82b38000 r DP_VGA_DONGLE_BRANCH_DEV_NAME +ffffffff82b38006 r DP_DVI_CONVERTER_ID_4 +ffffffff82b3800d r DP_DVI_CONVERTER_ID_5 +ffffffff82b39000 r DP_VGA_LVDS_CONVERTER_ID_2 +ffffffff82b39007 r DP_VGA_LVDS_CONVERTER_ID_3 +ffffffff82b39010 r dp_lt_fallbacks +ffffffff82b3a000 r mandatory_dpcd_partitions +ffffffff82b3c000 r dce_funcs +ffffffff82b3d000 r funcs +ffffffff82b3e000 R video_optimized_pixel_rates +ffffffff82b3e1b0 r dce110_clk_src_funcs +ffffffff82b3e1d8 r dce112_clk_src_funcs +ffffffff82b3e200 r dcn20_clk_src_funcs +ffffffff82b3e228 r dcn3_clk_src_funcs +ffffffff82b3e250 r dcn31_clk_src_funcs +ffffffff82b3f000 r dce_funcs +ffffffff82b3f068 r dcn10_funcs +ffffffff82b3f0d0 r dcn20_funcs +ffffffff82b3f138 r dcn21_funcs +ffffffff82b40000 r dce_ipp_funcs +ffffffff82b41000 r dce110_lnk_enc_funcs +ffffffff82b42000 r dce_mi_funcs +ffffffff82b42090 r dce112_mi_funcs +ffffffff82b42120 r dce120_mi_funcs +ffffffff82b421b0 r pte_settings +ffffffff82b43000 r funcs +ffffffff82b44000 r dce_link_panel_cntl_funcs +ffffffff82b45000 r filter_3tap_16p_upscale +ffffffff82b45040 r filter_3tap_16p_116 +ffffffff82b45080 r filter_3tap_16p_149 +ffffffff82b450c0 r filter_3tap_16p_183 +ffffffff82b45100 r filter_3tap_64p_upscale +ffffffff82b451d0 r filter_3tap_64p_116 +ffffffff82b452a0 r filter_3tap_64p_149 +ffffffff82b45370 r filter_3tap_64p_183 +ffffffff82b45440 r filter_4tap_16p_upscale +ffffffff82b45490 r filter_4tap_16p_116 +ffffffff82b454e0 r filter_4tap_16p_149 +ffffffff82b45530 r filter_4tap_16p_183 +ffffffff82b45580 r filter_4tap_64p_upscale +ffffffff82b45690 r filter_4tap_64p_116 +ffffffff82b457a0 r filter_4tap_64p_149 +ffffffff82b458b0 r filter_4tap_64p_183 +ffffffff82b459c0 r filter_5tap_64p_upscale +ffffffff82b45b10 r filter_5tap_64p_116 +ffffffff82b45c60 r filter_5tap_64p_149 +ffffffff82b45db0 r filter_5tap_64p_183 +ffffffff82b45f00 r filter_6tap_64p_upscale +ffffffff82b46090 r filter_6tap_64p_116 +ffffffff82b46220 r filter_6tap_64p_149 +ffffffff82b463b0 r filter_6tap_64p_183 +ffffffff82b46540 r filter_7tap_64p_upscale +ffffffff82b46710 r filter_7tap_64p_116 +ffffffff82b468e0 r filter_7tap_64p_149 +ffffffff82b46ab0 r filter_7tap_64p_183 +ffffffff82b46c80 r filter_8tap_64p_upscale +ffffffff82b46e90 r filter_8tap_64p_116 +ffffffff82b470a0 r filter_8tap_64p_149 +ffffffff82b472b0 r filter_8tap_64p_183 +ffffffff82b474c0 r filter_2tap_16p +ffffffff82b474f0 r filter_2tap_64p +ffffffff82b48000 r audio_clock_info_table_48bpc +ffffffff82b48190 r audio_clock_info_table_36bpc +ffffffff82b48320 r audio_clock_info_table +ffffffff82b484e0 r dce110_str_enc_funcs +ffffffff82b49000 r global_color_matrix +ffffffff82b490a8 r dce_transform_funcs +ffffffff82b4a000 r abm_funcs +ffffffff82b4b000 r psr_funcs +ffffffff82b4b040 r DP_SINK_DEVICE_STR_ID_1 +ffffffff82b4b045 r DP_SINK_DEVICE_STR_ID_2 +ffffffff82b4c000 r reg_offsets +ffffffff82b4d000 r bios_regs +ffffffff82b4d008 r res_cap +ffffffff82b4d050 r clk_src_regs +ffffffff82b4d14c r dmcu_regs +ffffffff82b4d1a8 r dmcu_shift +ffffffff82b4d1bc r dmcu_mask +ffffffff82b4d208 r abm_regs +ffffffff82b4d248 r abm_shift +ffffffff82b4d25c r abm_mask +ffffffff82b4d2b0 r dce100_tg_offsets +ffffffff82b4d2f8 r plane_cap +ffffffff82b4d328 r res_create_funcs +ffffffff82b4d358 r dce100_res_pool_funcs +ffffffff82b4d440 r panel_cntl_regs +ffffffff82b4d460 r panel_cntl_shift +ffffffff82b4d470 r panel_cntl_mask +ffffffff82b4d4b0 r link_enc_regs +ffffffff82b4d870 r link_enc_aux_regs +ffffffff82b4d8c0 r link_enc_hpd_regs +ffffffff82b4d8d8 r link_enc_feature +ffffffff82b4d8e8 r cs_shift +ffffffff82b4d8f4 r cs_mask +ffffffff82b4d920 r mi_regs +ffffffff82b4dc38 r mi_shifts +ffffffff82b4dc80 r mi_masks +ffffffff82b4dda0 r ipp_regs +ffffffff82b4df98 r ipp_shift +ffffffff82b4dfc0 r ipp_mask +ffffffff82b4e060 r xfm_regs +ffffffff82b4e600 r xfm_shift +ffffffff82b4e660 r xfm_mask +ffffffff82b4e7e0 r opp_regs +ffffffff82b4e930 r opp_shift +ffffffff82b4e95c r opp_mask +ffffffff82b4ea10 r aux_engine_regs +ffffffff82b4eb00 r aux_mask +ffffffff82b4eb60 r aux_shift +ffffffff82b4eb80 r i2c_hw_regs +ffffffff82b4ecd0 r i2c_shifts +ffffffff82b4ecfc r i2c_masks +ffffffff82b4eda0 r audio_regs +ffffffff82b4eed4 r audio_shift +ffffffff82b4eeec r audio_mask +ffffffff82b4ef30 r stream_enc_regs +ffffffff82b4f5dc r se_shift +ffffffff82b4f660 r se_mask +ffffffff82b4f864 r hwseq_reg +ffffffff82b4fa80 r hwseq_shift +ffffffff82b4fb00 r hwseq_mask +ffffffff82b50000 r reg_offsets +ffffffff82b50018 r dce110_compressor_funcs +ffffffff82b51000 r dce110_funcs +ffffffff82b512c0 r dce110_private_funcs +ffffffff82b52000 r dce110_mem_input_v_funcs +ffffffff82b52090 r dvmm_Hw_Setting_1DTiling +ffffffff82b52120 r dvmm_Hw_Setting_2DTiling +ffffffff82b521b0 r dvmm_Hw_Setting_Linear +ffffffff82b53000 r global_color_matrix +ffffffff82b530b0 r input_csc_matrix +ffffffff82b54000 r funcs +ffffffff82b55000 r bios_regs +ffffffff82b55008 r dce110_res_pool_funcs +ffffffff82b550f0 r clk_src_regs +ffffffff82b551ec r dmcu_regs +ffffffff82b55248 r dmcu_shift +ffffffff82b5525c r dmcu_mask +ffffffff82b552a8 r abm_regs +ffffffff82b552e8 r abm_shift +ffffffff82b552fc r abm_mask +ffffffff82b55350 r dce110_tg_offsets +ffffffff82b55398 r res_create_funcs +ffffffff82b553c8 r plane_cap +ffffffff82b553f4 r underlay_plane_cap +ffffffff82b55420 r stoney_resource_cap +ffffffff82b5545c r carrizo_resource_cap +ffffffff82b554a0 r panel_cntl_regs +ffffffff82b554c0 r panel_cntl_shift +ffffffff82b554d0 r panel_cntl_mask +ffffffff82b55510 r link_enc_regs +ffffffff82b558d0 r link_enc_aux_regs +ffffffff82b55920 r link_enc_hpd_regs +ffffffff82b55938 r link_enc_feature +ffffffff82b55948 r cs_shift +ffffffff82b55954 r cs_mask +ffffffff82b55980 r mi_regs +ffffffff82b55b0c r mi_shifts +ffffffff82b55b54 r mi_masks +ffffffff82b55c70 r ipp_regs +ffffffff82b55d6c r ipp_shift +ffffffff82b55d94 r ipp_mask +ffffffff82b55e30 r xfm_regs +ffffffff82b56100 r xfm_shift +ffffffff82b56160 r xfm_mask +ffffffff82b562e0 r opp_regs +ffffffff82b56430 r opp_shift +ffffffff82b5645c r opp_mask +ffffffff82b56510 r aux_engine_regs +ffffffff82b56600 r aux_mask +ffffffff82b56660 r aux_shift +ffffffff82b56680 r i2c_hw_regs +ffffffff82b567d0 r i2c_shifts +ffffffff82b567fc r i2c_masks +ffffffff82b568a0 r audio_regs +ffffffff82b569d4 r audio_shift +ffffffff82b569ec r audio_mask +ffffffff82b56a30 r stream_enc_regs +ffffffff82b56d0c r se_shift +ffffffff82b56d90 r se_mask +ffffffff82b56f94 r hwseq_stoney_reg +ffffffff82b571b0 r hwseq_cz_reg +ffffffff82b573cc r hwseq_shift +ffffffff82b5744c r hwseq_mask +ffffffff82b58000 r dce110_tg_funcs +ffffffff82b59000 r dce110_tg_v_funcs +ffffffff82b5a000 r dce110_xfmv_funcs ffffffff82b5b000 r reg_offsets -ffffffff82b5c000 r bios_regs -ffffffff82b5c010 r clk_src_regs -ffffffff82b5c208 r dmcu_regs -ffffffff82b5c264 r dmcu_shift -ffffffff82b5c278 r dmcu_mask -ffffffff82b5c2c4 r abm_regs -ffffffff82b5c304 r abm_shift -ffffffff82b5c318 r abm_mask -ffffffff82b5c360 r dce112_tg_offsets -ffffffff82b5c3a8 r res_create_funcs -ffffffff82b5c3d8 r plane_cap -ffffffff82b5c404 r polaris_11_resource_cap -ffffffff82b5c440 r polaris_10_resource_cap -ffffffff82b5c480 r dce112_res_pool_funcs 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dcn32_mmhubbub_funcs -ffffffff82c1e000 R dcn32_mpc_funcs -ffffffff82c1f000 r res_cap_dcn32 -ffffffff82c1f040 r debug_defaults_diags -ffffffff82c1f1b8 r dccg_shift -ffffffff82c1f250 r dccg_mask -ffffffff82c1f4ac r abm_shift -ffffffff82c1f4c0 r abm_mask -ffffffff82c1f508 r res_create_funcs -ffffffff82c1f538 r res_create_maximus_funcs -ffffffff82c1f568 r plane_cap -ffffffff82c1f594 r le_shift -ffffffff82c1f684 r le_mask -ffffffff82c1fa3c r link_enc_feature -ffffffff82c1fa50 r debug_defaults_drv -ffffffff82c1fbc8 r cs_shift -ffffffff82c1fbd4 r cs_mask -ffffffff82c1fbfc r hubbub_shift -ffffffff82c1fc84 r hubbub_mask -ffffffff82c1fea0 r vmid_shifts -ffffffff82c1fea8 r vmid_masks -ffffffff82c1fec8 r hubp_shift -ffffffff82c1ffc4 r hubp_mask -ffffffff82c203b4 r tf_shift -ffffffff82c20684 r tf_mask -ffffffff82c211c4 r opp_shift -ffffffff82c211fc r opp_mask -ffffffff82c212d0 r optc_shift -ffffffff82c21390 r optc_mask -ffffffff82c21690 r mpc_shift -ffffffff82c2176c r mpc_mask -ffffffff82c21ad8 r dsc_shift -ffffffff82c21b90 r dsc_mask -ffffffff82c21e68 r dwbc30_shift -ffffffff82c21f9c r dwbc30_mask -ffffffff82c22464 r mcif_wb30_shift -ffffffff82c22510 r mcif_wb30_mask -ffffffff82c227bc r aux_mask -ffffffff82c2281c r aux_shift -ffffffff82c22834 r i2c_shifts -ffffffff82c22860 r i2c_masks -ffffffff82c22904 r audio_shift -ffffffff82c2291c r audio_mask -ffffffff82c22958 r se_shift -ffffffff82c22a34 r se_mask -ffffffff82c22da0 r vpg_shift -ffffffff82c22dc8 r vpg_mask -ffffffff82c22e5c r afmt_shift -ffffffff82c22e70 r afmt_mask -ffffffff82c22eb4 r hpo_dp_se_shift -ffffffff82c22edc r hpo_dp_se_mask -ffffffff82c22f7c r apg_shift -ffffffff82c22f84 r apg_mask -ffffffff82c22f9c r hpo_dp_le_shift -ffffffff82c22fb8 r hpo_dp_le_mask -ffffffff82c2301c r hwseq_shift -ffffffff82c2309c r hwseq_mask -ffffffff82c24000 r dcn321_link_enc_funcs -ffffffff82c25000 r res_cap_dcn321 -ffffffff82c25040 r debug_defaults_diags -ffffffff82c251b8 r dccg_shift -ffffffff82c25250 r dccg_mask -ffffffff82c254ac r abm_shift -ffffffff82c254c0 r abm_mask -ffffffff82c25508 r res_create_funcs -ffffffff82c25538 r res_create_maximus_funcs -ffffffff82c25568 r plane_cap -ffffffff82c25594 r le_shift -ffffffff82c25684 r le_mask -ffffffff82c25a3c r link_enc_feature -ffffffff82c25a50 r debug_defaults_drv -ffffffff82c25bc8 r cs_shift -ffffffff82c25bd4 r cs_mask -ffffffff82c25bfc r hubbub_shift -ffffffff82c25c84 r hubbub_mask -ffffffff82c25ea0 r vmid_shifts -ffffffff82c25ea8 r vmid_masks -ffffffff82c25ec8 r hubp_shift -ffffffff82c25fc4 r hubp_mask -ffffffff82c263b4 r tf_shift -ffffffff82c26684 r tf_mask -ffffffff82c271c4 r opp_shift -ffffffff82c271fc r opp_mask -ffffffff82c272d0 r optc_shift -ffffffff82c27390 r optc_mask -ffffffff82c27690 r mpc_shift -ffffffff82c2776c r mpc_mask -ffffffff82c27ad8 r dsc_shift -ffffffff82c27b90 r dsc_mask -ffffffff82c27e68 r dwbc30_shift -ffffffff82c27f9c r dwbc30_mask -ffffffff82c28464 r mcif_wb30_shift -ffffffff82c28510 r mcif_wb30_mask -ffffffff82c287bc r aux_mask -ffffffff82c2881c r aux_shift -ffffffff82c28834 r i2c_shifts -ffffffff82c28860 r i2c_masks -ffffffff82c28904 r audio_shift -ffffffff82c2891c r audio_mask -ffffffff82c28958 r se_shift -ffffffff82c28a34 r se_mask -ffffffff82c28da0 r vpg_shift -ffffffff82c28dc8 r vpg_mask -ffffffff82c28e5c r afmt_shift -ffffffff82c28e70 r afmt_mask -ffffffff82c28eb4 r hpo_dp_se_shift -ffffffff82c28edc r hpo_dp_se_mask -ffffffff82c28f7c r apg_shift -ffffffff82c28f84 r apg_mask -ffffffff82c28f9c r hpo_dp_le_shift -ffffffff82c28fb8 r hpo_dp_le_mask -ffffffff82c2901c r hwseq_shift -ffffffff82c2909c r hwseq_mask -ffffffff82c2b000 R dcn10_soc_defaults -ffffffff82c2b08c R dcn10_ip_defaults -ffffffff82c36000 R dml20_funcs -ffffffff82c36030 R dml20v2_funcs -ffffffff82c36060 R dml21_funcs -ffffffff82c36090 R dml30_funcs -ffffffff82c360c0 R dml31_funcs -ffffffff82c360f0 R dml314_funcs -ffffffff82c36120 R dml32_funcs -ffffffff82c39000 R qp_table_422_10bpc_min -ffffffff82c39740 R qp_table_444_8bpc_max -ffffffff82c3a080 R qp_table_420_12bpc_max -ffffffff82c3a7c0 R qp_table_444_10bpc_min -ffffffff82c3b400 R qp_table_420_8bpc_max -ffffffff82c3b840 R qp_table_444_8bpc_min -ffffffff82c3c180 R qp_table_444_12bpc_min -ffffffff82c3d0c0 R qp_table_420_12bpc_min -ffffffff82c3d800 R qp_table_422_12bpc_min -ffffffff82c3e140 R qp_table_422_12bpc_max -ffffffff82c3ea80 R qp_table_444_12bpc_max -ffffffff82c3f9c0 R qp_table_420_8bpc_min -ffffffff82c3fe00 R qp_table_422_8bpc_min -ffffffff82c40340 R qp_table_422_10bpc_max -ffffffff82c40a80 R qp_table_420_10bpc_max -ffffffff82c41040 R qp_table_420_10bpc_min -ffffffff82c41600 R qp_table_444_10bpc_max -ffffffff82c42240 R qp_table_422_8bpc_max -ffffffff82c44000 r funcs -ffffffff82c44050 r hpd_regs -ffffffff82c441a0 r hpd_shift -ffffffff82c441b0 r hpd_mask -ffffffff82c441c0 r ddc_data_regs -ffffffff82c443a0 r ddc_clk_regs -ffffffff82c44580 r ddc_shift -ffffffff82c445a8 r ddc_mask +ffffffff82b5c000 r reg_offsets +ffffffff82b5d000 r bios_regs +ffffffff82b5d010 r clk_src_regs +ffffffff82b5d208 r dmcu_regs +ffffffff82b5d264 r dmcu_shift +ffffffff82b5d278 r dmcu_mask +ffffffff82b5d2c4 r abm_regs +ffffffff82b5d304 r abm_shift +ffffffff82b5d318 r abm_mask +ffffffff82b5d360 r dce112_tg_offsets +ffffffff82b5d3a8 r res_create_funcs +ffffffff82b5d3d8 r plane_cap +ffffffff82b5d404 r polaris_11_resource_cap +ffffffff82b5d440 r polaris_10_resource_cap +ffffffff82b5d480 r dce112_res_pool_funcs +ffffffff82b5d560 r panel_cntl_regs +ffffffff82b5d580 r panel_cntl_shift +ffffffff82b5d590 r panel_cntl_mask +ffffffff82b5d5d0 r link_enc_regs +ffffffff82b5d990 r link_enc_aux_regs +ffffffff82b5d9e0 r link_enc_hpd_regs +ffffffff82b5d9f8 r link_enc_feature +ffffffff82b5da08 r cs_shift +ffffffff82b5da14 r cs_mask +ffffffff82b5da40 r mi_regs +ffffffff82b5dd58 r mi_shifts +ffffffff82b5dda0 r mi_masks +ffffffff82b5dec0 r ipp_regs +ffffffff82b5e0b8 r ipp_shift +ffffffff82b5e0e0 r ipp_mask +ffffffff82b5e180 r xfm_regs +ffffffff82b5e720 r xfm_shift +ffffffff82b5e780 r xfm_mask +ffffffff82b5e900 r opp_regs +ffffffff82b5ea50 r opp_shift +ffffffff82b5ea7c r opp_mask +ffffffff82b5eb30 r aux_engine_regs +ffffffff82b5ec20 r aux_mask +ffffffff82b5ec80 r aux_shift +ffffffff82b5eca0 r i2c_hw_regs +ffffffff82b5edf0 r i2c_shifts +ffffffff82b5ee1c r i2c_masks +ffffffff82b5eec0 r audio_regs +ffffffff82b5efc8 r audio_shift +ffffffff82b5efe0 r audio_mask +ffffffff82b5f020 r stream_enc_regs +ffffffff82b5f5d8 r se_shift +ffffffff82b5f65c r se_mask +ffffffff82b5f860 r hwseq_reg +ffffffff82b5fa7c r hwseq_shift +ffffffff82b5fafc r hwseq_mask +ffffffff82b60000 r bios_regs +ffffffff82b60008 r res_cap +ffffffff82b60048 r dce120_res_pool_funcs +ffffffff82b60128 r debug_defaults +ffffffff82b602a0 r clk_src_regs +ffffffff82b60498 r dmcu_regs +ffffffff82b604f4 r dmcu_shift +ffffffff82b60508 r dmcu_mask +ffffffff82b60554 r abm_regs +ffffffff82b60594 r abm_shift +ffffffff82b605a8 r abm_mask +ffffffff82b605f0 r dce120_tg_offsets +ffffffff82b60638 r dce121_res_create_funcs +ffffffff82b60668 r res_create_funcs +ffffffff82b60698 r plane_cap +ffffffff82b606d0 r panel_cntl_regs +ffffffff82b606f0 r panel_cntl_shift +ffffffff82b60700 r panel_cntl_mask +ffffffff82b60740 r link_enc_regs +ffffffff82b60b00 r link_enc_aux_regs +ffffffff82b60b50 r link_enc_hpd_regs +ffffffff82b60b68 r link_enc_feature +ffffffff82b60b78 r cs_shift +ffffffff82b60b84 r cs_mask +ffffffff82b60bb0 r mi_regs +ffffffff82b60ec8 r mi_shifts +ffffffff82b60f10 r mi_masks +ffffffff82b61030 r ipp_regs +ffffffff82b61228 r ipp_shift +ffffffff82b61250 r ipp_mask +ffffffff82b612f0 r xfm_regs +ffffffff82b61890 r xfm_shift +ffffffff82b618f0 r xfm_mask +ffffffff82b61a70 r opp_regs +ffffffff82b61bc0 r opp_shift +ffffffff82b61bec r opp_mask +ffffffff82b61ca0 r aux_engine_regs +ffffffff82b61d90 r aux_mask +ffffffff82b61df0 r aux_shift +ffffffff82b61e10 r i2c_hw_regs +ffffffff82b61f60 r i2c_shifts +ffffffff82b61f8c r i2c_masks +ffffffff82b62030 r audio_regs +ffffffff82b62164 r audio_shift +ffffffff82b6217c r audio_mask +ffffffff82b621c0 r stream_enc_regs +ffffffff82b62778 r se_shift +ffffffff82b627fc r se_mask +ffffffff82b62a00 r dce121_hwseq_reg +ffffffff82b62c1c r dce121_hwseq_shift +ffffffff82b62c9c r dce121_hwseq_mask +ffffffff82b62e90 r hwseq_reg +ffffffff82b630ac r hwseq_shift +ffffffff82b6312c r hwseq_mask +ffffffff82b64000 r dce120_tg_funcs +ffffffff82b65000 r bios_regs +ffffffff82b65008 r res_cap +ffffffff82b65048 r dce80_res_pool_funcs +ffffffff82b65130 r clk_src_regs +ffffffff82b6522c r dmcu_regs +ffffffff82b65288 r dmcu_shift +ffffffff82b6529c r dmcu_mask +ffffffff82b652e8 r abm_regs +ffffffff82b65328 r abm_shift +ffffffff82b6533c r abm_mask +ffffffff82b65390 r dce80_tg_offsets +ffffffff82b653d8 r plane_cap +ffffffff82b65408 r res_create_funcs +ffffffff82b65440 r panel_cntl_regs +ffffffff82b65460 r panel_cntl_shift +ffffffff82b65470 r panel_cntl_mask +ffffffff82b654b0 r link_enc_regs +ffffffff82b65870 r link_enc_aux_regs +ffffffff82b658c0 r link_enc_hpd_regs +ffffffff82b658d8 r link_enc_feature +ffffffff82b658e8 r cs_shift +ffffffff82b658f4 r cs_mask +ffffffff82b65920 r mi_regs +ffffffff82b65c38 r mi_shifts +ffffffff82b65c80 r mi_masks +ffffffff82b65da0 r ipp_regs +ffffffff82b65f98 r ipp_shift +ffffffff82b65fc0 r ipp_mask +ffffffff82b66060 r xfm_regs +ffffffff82b66600 r xfm_shift +ffffffff82b66660 r xfm_mask +ffffffff82b667e0 r opp_regs +ffffffff82b66930 r opp_shift +ffffffff82b6695c r opp_mask +ffffffff82b66a10 r aux_engine_regs +ffffffff82b66b00 r aux_mask +ffffffff82b66b60 r aux_shift +ffffffff82b66b80 r i2c_hw_regs +ffffffff82b66cd0 r i2c_shifts +ffffffff82b66cfc r i2c_masks +ffffffff82b66da0 r audio_regs +ffffffff82b66ed4 r audio_shift +ffffffff82b66eec r audio_mask +ffffffff82b66f30 r stream_enc_regs +ffffffff82b675dc r se_shift +ffffffff82b67660 r se_mask +ffffffff82b67864 r hwseq_reg +ffffffff82b67a80 r hwseq_shift +ffffffff82b67b00 r hwseq_mask +ffffffff82b67cf4 r res_cap_81 +ffffffff82b67d30 r res_cap_83 +ffffffff82b68000 r reg_offsets +ffffffff82b68048 r dce80_tg_funcs +ffffffff82b69000 r dcn10_dpp_funcs +ffffffff82b6a000 r dpp_input_csc_matrix +ffffffff82b6c000 r hubbub1_funcs +ffffffff82b6d000 r dcn10_hubp_funcs +ffffffff82b6e000 r reduceSizeAndFraction.prime_numbers +ffffffff82b70000 r dcn10_funcs +ffffffff82b702c0 r dcn10_private_funcs +ffffffff82b71000 r dcn10_ipp_funcs +ffffffff82b71048 r dcn20_ipp_funcs +ffffffff82b72000 r dcn10_lnk_enc_funcs +ffffffff82b73000 r dcn10_mpc_funcs +ffffffff82b74000 r dcn10_opp_funcs +ffffffff82b75000 r dcn10_tg_funcs +ffffffff82b76000 r bios_regs +ffffffff82b76008 r rv2_res_cap +ffffffff82b76044 r res_cap +ffffffff82b76080 r debug_defaults_drv +ffffffff82b761f8 r debug_defaults_diags +ffffffff82b76370 r clk_src_regs +ffffffff82b764c0 r dmcu_regs +ffffffff82b7651c r dmcu_shift +ffffffff82b76530 r dmcu_mask +ffffffff82b7657c r abm_regs +ffffffff82b765bc r abm_shift +ffffffff82b765d0 r abm_mask +ffffffff82b76618 r res_create_funcs +ffffffff82b76648 r res_create_maximus_funcs +ffffffff82b76678 r plane_cap +ffffffff82b766a8 r dcn10_res_pool_funcs +ffffffff82b76790 r panel_cntl_regs +ffffffff82b767b0 r panel_cntl_shift +ffffffff82b767c0 r panel_cntl_mask +ffffffff82b76800 r link_enc_regs +ffffffff82b76d10 r link_enc_aux_regs +ffffffff82b76d50 r link_enc_hpd_regs +ffffffff82b76d60 r le_shift +ffffffff82b76e50 r le_mask +ffffffff82b77208 r link_enc_feature +ffffffff82b77218 r cs_shift +ffffffff82b77224 r cs_mask +ffffffff82b77250 r hubp_regs +ffffffff82b77900 r hubp_shift +ffffffff82b779c4 r hubp_mask +ffffffff82b77cd0 r ipp_regs +ffffffff82b77db0 r ipp_shift +ffffffff82b77dcc r ipp_mask +ffffffff82b77e40 r tf_regs +ffffffff82b78da0 r tf_shift +ffffffff82b79008 r tf_mask +ffffffff82b799a0 r opp_regs +ffffffff82b79a70 r opp_shift +ffffffff82b79a90 r opp_mask +ffffffff82b79b10 r tg_regs +ffffffff82b7a010 r tg_shift +ffffffff82b7a0d0 r tg_mask +ffffffff82b7a3d0 r aux_engine_regs +ffffffff82b7a4c0 r aux_mask +ffffffff82b7a520 r aux_shift +ffffffff82b7a540 r i2c_hw_regs +ffffffff82b7a690 r i2c_shifts +ffffffff82b7a6bc r i2c_masks +ffffffff82b7a760 r mpc_regs +ffffffff82b7a880 r mpc_shift +ffffffff82b7a898 r mpc_mask +ffffffff82b7a8f4 r hubbub_reg +ffffffff82b7aa68 r hubbub_shift +ffffffff82b7aaf0 r hubbub_mask +ffffffff82b7ad10 r audio_regs +ffffffff82b7adc0 r audio_shift +ffffffff82b7add8 r audio_mask +ffffffff82b7ae20 r stream_enc_regs +ffffffff82b7b370 r se_shift +ffffffff82b7b44c r se_mask +ffffffff82b7b7b8 r hwseq_reg +ffffffff82b7b9d4 r hwseq_shift +ffffffff82b7ba54 r hwseq_mask +ffffffff82b7c000 r audio_clock_info_table_48bpc +ffffffff82b7c190 r audio_clock_info_table_36bpc +ffffffff82b7c320 r audio_clock_info_table +ffffffff82b7c4e0 r dcn10_str_enc_funcs +ffffffff82b7d000 r dccg2_funcs +ffffffff82b7f000 r dpp_input_csc_matrix +ffffffff82b80000 R dcn20_dsc_funcs +ffffffff82b81000 R dcn20_dwbc_funcs +ffffffff82b82000 r filter_12tap_16p_upscale +ffffffff82b820e0 r filter_12tap_16p_117 +ffffffff82b821c0 r filter_12tap_16p_150 +ffffffff82b822a0 r filter_12tap_16p_183 +ffffffff82b82380 r filter_11tap_16p_upscale +ffffffff82b82450 r filter_11tap_16p_117 +ffffffff82b82520 r filter_11tap_16p_150 +ffffffff82b825f0 r filter_11tap_16p_183 +ffffffff82b826c0 r filter_10tap_16p_upscale +ffffffff82b82780 r filter_10tap_16p_117 +ffffffff82b82840 r filter_10tap_16p_150 +ffffffff82b82900 r filter_10tap_16p_183 +ffffffff82b829c0 r filter_9tap_16p_upscale +ffffffff82b82a70 r filter_9tap_16p_117 +ffffffff82b82b20 r filter_9tap_16p_150 +ffffffff82b82bd0 r filter_9tap_16p_183 +ffffffff82b82c80 r filter_8tap_16p_upscale +ffffffff82b82d10 r filter_8tap_16p_117 +ffffffff82b82da0 r filter_8tap_16p_150 +ffffffff82b82e30 r filter_8tap_16p_183 +ffffffff82b82ec0 r filter_7tap_16p_upscale +ffffffff82b82f40 r filter_7tap_16p_117 +ffffffff82b82fc0 r filter_7tap_16p_150 +ffffffff82b83040 r filter_7tap_16p_183 +ffffffff82b830c0 r filter_6tap_16p_upscale +ffffffff82b83130 r filter_6tap_16p_117 +ffffffff82b831a0 r filter_6tap_16p_150 +ffffffff82b83210 r filter_6tap_16p_183 +ffffffff82b83280 r filter_5tap_16p_upscale +ffffffff82b832e0 r filter_5tap_16p_117 +ffffffff82b83340 r filter_5tap_16p_150 +ffffffff82b833a0 r filter_5tap_16p_183 +ffffffff82b83400 r filter_4tap_16p_upscale +ffffffff82b83450 r filter_4tap_16p_117 +ffffffff82b834a0 r filter_4tap_16p_150 +ffffffff82b834f0 r filter_4tap_16p_183 +ffffffff82b83540 r filter_3tap_16p_upscale +ffffffff82b83580 r filter_3tap_16p_117 +ffffffff82b835c0 r filter_3tap_16p_150 +ffffffff82b83600 r filter_3tap_16p_183 +ffffffff82b84000 r hubbub2_funcs +ffffffff82b85000 r dcn20_funcs +ffffffff82b852c0 r dcn20_private_funcs +ffffffff82b86000 r dcn2_mpll_cfg +ffffffff82b86190 r dcn20_link_enc_funcs +ffffffff82b87000 R dcn20_mmhubbub_funcs +ffffffff82b88000 R dcn20_mpc_funcs +ffffffff82b89000 r tf_regs +ffffffff82b8a920 r tf_shift +ffffffff82b8aba4 r tf_mask +ffffffff82b8b5c0 r ipp_regs +ffffffff82b8b710 r ipp_shift +ffffffff82b8b72c r ipp_mask +ffffffff82b8b7a0 r opp_regs +ffffffff82b8b9b0 r opp_shift +ffffffff82b8b9e8 r opp_mask +ffffffff82b8bac0 r aux_engine_regs +ffffffff82b8bbb0 r aux_mask +ffffffff82b8bc10 r aux_shift +ffffffff82b8bc30 r i2c_hw_regs +ffffffff82b8bd80 r i2c_shifts +ffffffff82b8bdac r i2c_masks +ffffffff82b8be50 r mpc_regs +ffffffff82b8c398 r mpc_shift +ffffffff82b8c3e0 r mpc_mask +ffffffff82b8c4f4 r hubbub_reg +ffffffff82b8c668 r hubbub_shift +ffffffff82b8c6f0 r hubbub_mask +ffffffff82b8c90c r res_cap_nv10 +ffffffff82b8c950 r vmid_regs +ffffffff82b8cb10 r vmid_shifts +ffffffff82b8cb18 r vmid_masks +ffffffff82b8cb40 r tg_regs +ffffffff82b8d2c0 r tg_shift +ffffffff82b8d380 r tg_mask +ffffffff82b8d680 r link_enc_regs +ffffffff82b8de20 r link_enc_aux_regs +ffffffff82b8de80 r link_enc_hpd_regs +ffffffff82b8de98 r le_shift +ffffffff82b8df88 r le_mask +ffffffff82b8e340 r stream_enc_regs +ffffffff82b8eb38 r se_shift +ffffffff82b8ec14 r se_mask +ffffffff82b8ef80 r hwseq_reg +ffffffff82b8f19c r hwseq_shift +ffffffff82b8f21c r hwseq_mask +ffffffff82b8f410 r dsc_regs +ffffffff82b8f8a8 r dsc_shift +ffffffff82b8f960 r dsc_mask +ffffffff82b8fc40 r hubp_regs +ffffffff82b90888 r hubp_shift +ffffffff82b90984 r hubp_mask +ffffffff82b90d80 r dwbc20_regs +ffffffff82b90e38 r dwbc20_shift +ffffffff82b90eb8 r dwbc20_mask +ffffffff82b910b0 r mcif_wb20_regs +ffffffff82b91190 r mcif_wb20_shift +ffffffff82b91230 r mcif_wb20_mask +ffffffff82b914b0 r link_enc_feature +ffffffff82b914c0 r bios_regs +ffffffff82b914c8 r dcn20_res_pool_funcs +ffffffff82b915a8 r res_cap_nv14 +ffffffff82b915e8 r debug_defaults_drv +ffffffff82b91760 r debug_defaults_diags +ffffffff82b918e0 r clk_src_regs +ffffffff82b91ad8 r dccg_regs +ffffffff82b91bc4 r dccg_shift +ffffffff82b91c5c r dccg_mask +ffffffff82b91eb8 r dmcu_regs +ffffffff82b91f14 r dmcu_shift +ffffffff82b91f28 r dmcu_mask +ffffffff82b91f74 r abm_regs +ffffffff82b91fb4 r abm_shift +ffffffff82b91fc8 r abm_mask +ffffffff82b92010 r res_create_funcs +ffffffff82b92040 r res_create_maximus_funcs +ffffffff82b92070 r plane_cap +ffffffff82b920a0 r panel_cntl_regs +ffffffff82b920c0 r panel_cntl_shift +ffffffff82b920d0 r panel_cntl_mask +ffffffff82b9210c r cs_shift +ffffffff82b92118 r cs_mask +ffffffff82b92140 r audio_regs +ffffffff82b92274 r audio_shift +ffffffff82b9228c r audio_mask +ffffffff82b93000 r dcn20_str_enc_funcs +ffffffff82b94000 r dccg201_funcs +ffffffff82b95000 r hubbub201_funcs +ffffffff82b96000 r dcn201_funcs +ffffffff82b962c0 r dcn201_private_funcs +ffffffff82b97000 r dcn201_link_enc_funcs +ffffffff82b98000 R dcn201_mpc_funcs +ffffffff82b99000 r bios_regs +ffffffff82b99008 r res_cap_dnc201 +ffffffff82b99048 r debug_defaults_drv +ffffffff82b991c0 r clk_src_regs +ffffffff82b99268 r dccg_regs +ffffffff82b99354 r dccg_shift +ffffffff82b993ec r dccg_mask +ffffffff82b99648 r res_create_funcs +ffffffff82b99678 r res_create_maximus_funcs +ffffffff82b996a8 r plane_cap +ffffffff82b996e0 r link_enc_regs +ffffffff82b99970 r link_enc_aux_regs +ffffffff82b99990 r link_enc_hpd_regs +ffffffff82b99998 r le_shift +ffffffff82b99a88 r le_mask +ffffffff82b99e40 r link_enc_feature +ffffffff82b99e50 r cs_shift +ffffffff82b99e5c r cs_mask +ffffffff82b99e90 r hubp_regs +ffffffff82b9a620 r hubp_shift +ffffffff82b9a6f8 r hubp_mask +ffffffff82b9aa60 r ipp_regs +ffffffff82b9ab40 r ipp_shift +ffffffff82b9ab5c r ipp_mask +ffffffff82b9abd0 r tf_regs +ffffffff82b9bc10 r tf_shift +ffffffff82b9be94 r tf_mask +ffffffff82b9c8b0 r opp_regs +ffffffff82b9c960 r opp_shift +ffffffff82b9c998 r opp_mask +ffffffff82b9ca70 r aux_engine_regs +ffffffff82b9cac0 r aux_mask +ffffffff82b9cb20 r aux_shift +ffffffff82b9cb40 r i2c_hw_regs +ffffffff82b9cbb0 r i2c_shifts +ffffffff82b9cbdc r i2c_masks +ffffffff82b9cc80 r tg_regs +ffffffff82b9cf00 r tg_shift +ffffffff82b9cfc0 r tg_mask +ffffffff82b9d2c0 r mpc_regs +ffffffff82b9d808 r mpc_shift +ffffffff82b9d854 r mpc_mask +ffffffff82b9d97c r hubbub_reg +ffffffff82b9daf0 r hubbub_shift +ffffffff82b9db78 r hubbub_mask +ffffffff82b9dda0 r audio_regs +ffffffff82b9ddf8 r audio_shift +ffffffff82b9de10 r audio_mask +ffffffff82b9de50 r stream_enc_regs +ffffffff82b9e0f8 r se_shift +ffffffff82b9e1d4 r se_mask +ffffffff82b9e540 r hwseq_reg +ffffffff82b9e75c r hwseq_shift +ffffffff82b9e7dc r hwseq_mask +ffffffff82b9f000 r dccg21_funcs +ffffffff82ba0000 r hubbub21_funcs +ffffffff82ba1000 r dcn21_funcs +ffffffff82ba12c0 r dcn21_private_funcs +ffffffff82ba2000 r dcn21_mpll_cfg_ref +ffffffff82ba2190 r dcn21_link_enc_funcs +ffffffff82ba3000 r bios_regs +ffffffff82ba3008 r res_cap_rn +ffffffff82ba3048 r dcn21_res_pool_funcs +ffffffff82ba3128 r debug_defaults_drv +ffffffff82ba32a0 r debug_defaults_diags +ffffffff82ba3420 r clk_src_regs +ffffffff82ba35c4 r dccg_regs +ffffffff82ba36b0 r dccg_shift +ffffffff82ba3748 r dccg_mask +ffffffff82ba39a4 r dmcu_regs +ffffffff82ba3a00 r dmcu_shift +ffffffff82ba3a14 r dmcu_mask +ffffffff82ba3a60 r abm_regs +ffffffff82ba3aa0 r abm_shift +ffffffff82ba3ab4 r abm_mask +ffffffff82ba3b00 r res_create_funcs +ffffffff82ba3b30 r res_create_maximus_funcs +ffffffff82ba3b60 r plane_cap +ffffffff82ba3b90 r panel_cntl_regs +ffffffff82ba3bb0 r panel_cntl_shift +ffffffff82ba3bc0 r panel_cntl_mask +ffffffff82ba3c00 r link_enc_regs +ffffffff82ba4260 r link_enc_aux_regs +ffffffff82ba42b0 r link_enc_hpd_regs +ffffffff82ba42c4 r le_shift +ffffffff82ba43b4 r le_mask +ffffffff82ba476c r link_enc_feature +ffffffff82ba477c r panel_config_defaults +ffffffff82ba47b8 r cs_shift +ffffffff82ba47c4 r cs_mask +ffffffff82ba47f0 r hubp_regs +ffffffff82ba5020 r hubp_shift +ffffffff82ba511c r hubp_mask +ffffffff82ba5510 r ipp_regs +ffffffff82ba55f0 r ipp_shift +ffffffff82ba560c r ipp_mask +ffffffff82ba5680 r tf_regs +ffffffff82ba6740 r tf_shift +ffffffff82ba69c4 r tf_mask +ffffffff82ba73e0 r opp_regs +ffffffff82ba75f0 r opp_shift +ffffffff82ba7628 r opp_mask +ffffffff82ba7700 r tg_regs +ffffffff82ba7c00 r tg_shift +ffffffff82ba7cc0 r tg_mask +ffffffff82ba7fc0 r aux_engine_regs +ffffffff82ba8088 r aux_mask +ffffffff82ba80e8 r aux_shift +ffffffff82ba8100 r i2c_hw_regs +ffffffff82ba8218 r i2c_shifts +ffffffff82ba8244 r i2c_masks +ffffffff82ba82e8 r mpc_regs +ffffffff82ba8830 r mpc_shift +ffffffff82ba8878 r mpc_mask +ffffffff82ba898c r hubbub_reg +ffffffff82ba8b00 r hubbub_shift +ffffffff82ba8b88 r hubbub_mask +ffffffff82ba8db0 r vmid_regs +ffffffff82ba8f70 r vmid_shifts +ffffffff82ba8f78 r vmid_masks +ffffffff82ba8fa0 r dsc_regs +ffffffff82ba9438 r dsc_shift +ffffffff82ba94f0 r dsc_mask +ffffffff82ba97d0 r audio_regs +ffffffff82ba98d8 r audio_shift +ffffffff82ba98f0 r audio_mask +ffffffff82ba9930 r stream_enc_regs +ffffffff82ba9fd4 r se_shift +ffffffff82baa0b0 r se_mask +ffffffff82baa41c r hwseq_reg +ffffffff82baa638 r hwseq_shift +ffffffff82baa6b8 r hwseq_mask +ffffffff82bab000 r dccg3_funcs +ffffffff82bac000 r dcn30_link_enc_funcs +ffffffff82bad000 r dcn30_str_enc_funcs +ffffffff82bae000 r dpp_input_csc_matrix +ffffffff82baf000 R dcn30_dwbc_funcs +ffffffff82bb0000 r hubbub30_funcs +ffffffff82bb2000 r dcn30_funcs +ffffffff82bb22c0 r dcn30_private_funcs +ffffffff82bb3000 R dcn30_mmhubbub_funcs +ffffffff82bb4000 R dcn30_mpc_funcs +ffffffff82bb5000 r bios_regs +ffffffff82bb5008 r res_cap_dcn3 +ffffffff82bb5048 r debug_defaults_drv +ffffffff82bb51c0 r debug_defaults_diags +ffffffff82bb5340 r clk_src_regs +ffffffff82bb5538 r dccg_regs +ffffffff82bb5624 r dccg_shift +ffffffff82bb56bc r dccg_mask +ffffffff82bb5920 r abm_regs +ffffffff82bb5aa0 r abm_shift +ffffffff82bb5ab4 r abm_mask +ffffffff82bb5b00 r res_create_funcs +ffffffff82bb5b30 r res_create_maximus_funcs +ffffffff82bb5b60 r plane_cap +ffffffff82bb5b90 r dcn30_res_pool_funcs +ffffffff82bb5c70 r panel_cntl_regs +ffffffff82bb5c90 r panel_cntl_shift +ffffffff82bb5ca0 r panel_cntl_mask +ffffffff82bb5ce0 r link_enc_regs +ffffffff82bb6480 r link_enc_aux_regs +ffffffff82bb64e0 r link_enc_hpd_regs +ffffffff82bb64f8 r le_shift +ffffffff82bb65e8 r le_mask +ffffffff82bb69a0 r link_enc_feature +ffffffff82bb69b0 r panel_config_defaults +ffffffff82bb69ec r cs_shift +ffffffff82bb69f8 r cs_mask +ffffffff82bb6a20 r hubbub_reg +ffffffff82bb6b94 r hubbub_shift +ffffffff82bb6c1c r hubbub_mask +ffffffff82bb6e40 r vmid_regs +ffffffff82bb7000 r vmid_shifts +ffffffff82bb7008 r vmid_masks +ffffffff82bb7030 r hubp_regs +ffffffff82bb7c78 r hubp_shift +ffffffff82bb7d74 r hubp_mask +ffffffff82bb8170 r dpp_regs +ffffffff82bba0f0 r tf_shift +ffffffff82bba3c0 r tf_mask +ffffffff82bbaf00 r opp_regs +ffffffff82bbb110 r opp_shift +ffffffff82bbb148 r opp_mask +ffffffff82bbb220 r optc_regs +ffffffff82bbb9a0 r optc_shift +ffffffff82bbba60 r optc_mask +ffffffff82bbbd60 r mpc_regs +ffffffff82bbd54c r mpc_shift +ffffffff82bbd628 r mpc_mask +ffffffff82bbd9a0 r dsc_regs +ffffffff82bbde38 r dsc_shift +ffffffff82bbdef0 r dsc_mask +ffffffff82bbe1d0 r dwbc30_regs +ffffffff82bbe3ac r dwbc30_shift +ffffffff82bbe4e0 r dwbc30_mask +ffffffff82bbe9b0 r mcif_wb30_regs +ffffffff82bbeaac r mcif_wb30_shift +ffffffff82bbeb58 r mcif_wb30_mask +ffffffff82bbee10 r aux_engine_regs +ffffffff82bbef00 r aux_mask +ffffffff82bbef60 r aux_shift +ffffffff82bbef80 r i2c_hw_regs +ffffffff82bbf0d0 r i2c_shifts +ffffffff82bbf0fc r i2c_masks +ffffffff82bbf1a0 r audio_regs +ffffffff82bbf2d4 r audio_shift +ffffffff82bbf2ec r audio_mask +ffffffff82bbf330 r stream_enc_regs +ffffffff82bbfb28 r se_shift +ffffffff82bbfc04 r se_mask +ffffffff82bbff70 r vpg_regs +ffffffff82bbfffc r vpg_shift +ffffffff82bc0024 r vpg_mask +ffffffff82bc00c0 r afmt_regs +ffffffff82bc01bc r afmt_shift +ffffffff82bc01d0 r afmt_mask +ffffffff82bc0214 r hwseq_reg +ffffffff82bc0430 r hwseq_shift +ffffffff82bc04b0 r hwseq_mask +ffffffff82bc1000 r dccg301_funcs +ffffffff82bc2000 r dcn301_link_enc_funcs +ffffffff82bc3000 r hubbub301_funcs +ffffffff82bc4000 r dcn301_funcs +ffffffff82bc42c0 r dcn301_private_funcs +ffffffff82bc5000 r dcn301_link_panel_cntl_funcs +ffffffff82bc6000 r bios_regs +ffffffff82bc6008 r debug_defaults_drv +ffffffff82bc6180 r debug_defaults_diags +ffffffff82bc6300 r clk_src_regs +ffffffff82bc6450 r dccg_regs +ffffffff82bc653c r dccg_shift +ffffffff82bc65d4 r dccg_mask +ffffffff82bc6830 r abm_regs +ffffffff82bc6930 r abm_shift +ffffffff82bc6944 r abm_mask +ffffffff82bc6990 r res_create_funcs +ffffffff82bc69c0 r res_create_maximus_funcs +ffffffff82bc69f0 r plane_cap +ffffffff82bc6a20 r panel_cntl_regs +ffffffff82bc6a60 r panel_cntl_shift +ffffffff82bc6a70 r panel_cntl_mask +ffffffff82bc6ab0 r link_enc_regs +ffffffff82bc6fc0 r link_enc_aux_regs +ffffffff82bc7000 r link_enc_hpd_regs +ffffffff82bc7010 r le_shift +ffffffff82bc7100 r le_mask +ffffffff82bc74b8 r link_enc_feature +ffffffff82bc74c8 r cs_shift +ffffffff82bc74d4 r cs_mask +ffffffff82bc74fc r hubbub_reg +ffffffff82bc7670 r hubbub_shift +ffffffff82bc76f8 r hubbub_mask +ffffffff82bc7920 r vmid_regs +ffffffff82bc7ae0 r vmid_shifts +ffffffff82bc7ae8 r vmid_masks +ffffffff82bc7b10 r hubp_regs +ffffffff82bc8340 r hubp_shift +ffffffff82bc843c r hubp_mask +ffffffff82bc8830 r dpp_regs +ffffffff82bc9d30 r tf_shift +ffffffff82bca000 r tf_mask +ffffffff82bcab40 r opp_regs +ffffffff82bcaca0 r opp_shift +ffffffff82bcacd8 r opp_mask +ffffffff82bcadb0 r optc_regs +ffffffff82bcb2b0 r optc_shift +ffffffff82bcb370 r optc_mask +ffffffff82bcb670 r mpc_regs +ffffffff82bcce5c r mpc_shift +ffffffff82bccf38 r mpc_mask +ffffffff82bcd2b0 r dsc_regs +ffffffff82bcd4fc r dsc_shift +ffffffff82bcd5b4 r dsc_mask +ffffffff82bcd890 r dwbc30_regs +ffffffff82bcda6c r dwbc30_shift +ffffffff82bcdba0 r dwbc30_mask +ffffffff82bce070 r mcif_wb30_regs +ffffffff82bce16c r mcif_wb30_shift +ffffffff82bce218 r mcif_wb30_mask +ffffffff82bce4d0 r aux_engine_regs +ffffffff82bce570 r aux_mask +ffffffff82bce5d0 r aux_shift +ffffffff82bce5f0 r i2c_hw_regs +ffffffff82bce6d0 r i2c_shifts +ffffffff82bce6fc r i2c_masks +ffffffff82bce7a0 r audio_regs +ffffffff82bce8d4 r audio_shift +ffffffff82bce8ec r audio_mask +ffffffff82bce930 r stream_enc_regs +ffffffff82bcee80 r se_shift +ffffffff82bcef5c r se_mask +ffffffff82bcf2d0 r vpg_regs +ffffffff82bcf320 r vpg_shift +ffffffff82bcf348 r vpg_mask +ffffffff82bcf3e0 r afmt_regs +ffffffff82bcf470 r afmt_shift +ffffffff82bcf484 r afmt_mask +ffffffff82bcf4c8 r hwseq_reg +ffffffff82bcf6e4 r hwseq_shift +ffffffff82bcf764 r hwseq_mask +ffffffff82bd0000 r bios_regs +ffffffff82bd0008 r res_cap_dcn302 +ffffffff82bd0048 r debug_defaults_drv +ffffffff82bd01c0 r debug_defaults_diags +ffffffff82bd0340 r clk_src_regs +ffffffff82bd04e4 r dccg_regs +ffffffff82bd05d0 r dccg_shift +ffffffff82bd0668 r dccg_mask +ffffffff82bd08d0 r abm_regs +ffffffff82bd0a10 r abm_shift +ffffffff82bd0a24 r abm_mask +ffffffff82bd0a70 r res_create_funcs +ffffffff82bd0aa0 r res_create_maximus_funcs +ffffffff82bd0ad0 r plane_cap +ffffffff82bd0b00 r panel_cntl_regs +ffffffff82bd0b20 r panel_cntl_shift +ffffffff82bd0b30 r panel_cntl_mask +ffffffff82bd0b70 r link_enc_regs +ffffffff82bd11d0 r link_enc_aux_regs +ffffffff82bd1220 r link_enc_hpd_regs +ffffffff82bd1234 r le_shift +ffffffff82bd1324 r le_mask +ffffffff82bd16dc r link_enc_feature +ffffffff82bd16ec r panel_config_defaults +ffffffff82bd1728 r cs_shift +ffffffff82bd1734 r cs_mask +ffffffff82bd175c r hubbub_reg +ffffffff82bd18d0 r hubbub_shift +ffffffff82bd1958 r hubbub_mask +ffffffff82bd1b80 r vmid_regs +ffffffff82bd1d40 r vmid_shifts +ffffffff82bd1d48 r vmid_masks +ffffffff82bd1d70 r hubp_regs +ffffffff82bd27ac r hubp_shift +ffffffff82bd28a8 r hubp_mask +ffffffff82bd2ca0 r dpp_regs +ffffffff82bd46e0 r tf_shift +ffffffff82bd49b0 r tf_mask +ffffffff82bd54f0 r opp_regs +ffffffff82bd56a8 r opp_shift +ffffffff82bd56e0 r opp_mask +ffffffff82bd57c0 r optc_regs +ffffffff82bd5e00 r optc_shift +ffffffff82bd5ec0 r optc_mask +ffffffff82bd61c0 r mpc_regs +ffffffff82bd79ac r mpc_shift +ffffffff82bd7a88 r mpc_mask +ffffffff82bd7e00 r dsc_regs +ffffffff82bd81d4 r dsc_shift +ffffffff82bd828c r dsc_mask +ffffffff82bd8570 r dwbc30_regs +ffffffff82bd874c r dwbc30_shift +ffffffff82bd8880 r dwbc30_mask +ffffffff82bd8d50 r mcif_wb30_regs +ffffffff82bd8e4c r mcif_wb30_shift +ffffffff82bd8ef8 r mcif_wb30_mask +ffffffff82bd91b0 r aux_engine_regs +ffffffff82bd9278 r aux_mask +ffffffff82bd92d8 r aux_shift +ffffffff82bd92f0 r i2c_hw_regs +ffffffff82bd9408 r i2c_shifts +ffffffff82bd9434 r i2c_masks +ffffffff82bd94e0 r audio_regs +ffffffff82bd9614 r audio_shift +ffffffff82bd962c r audio_mask +ffffffff82bd9670 r stream_enc_regs +ffffffff82bd9d14 r se_shift +ffffffff82bd9df0 r se_mask +ffffffff82bda160 r vpg_regs +ffffffff82bda1d8 r vpg_shift +ffffffff82bda200 r vpg_mask +ffffffff82bda2a0 r afmt_regs +ffffffff82bda378 r afmt_shift +ffffffff82bda38c r afmt_mask +ffffffff82bda3d0 r hwseq_reg +ffffffff82bda5ec r hwseq_shift +ffffffff82bda66c r hwseq_mask +ffffffff82bdb000 r bios_regs +ffffffff82bdb008 r res_cap_dcn303 +ffffffff82bdb048 r debug_defaults_drv +ffffffff82bdb1c0 r debug_defaults_diags +ffffffff82bdb340 r clk_src_regs +ffffffff82bdb3e8 r dccg_regs +ffffffff82bdb4d4 r dccg_shift +ffffffff82bdb56c r dccg_mask +ffffffff82bdb7d0 r abm_regs +ffffffff82bdb850 r abm_shift +ffffffff82bdb864 r abm_mask +ffffffff82bdb8b0 r res_create_funcs +ffffffff82bdb8e0 r res_create_maximus_funcs +ffffffff82bdb910 r plane_cap +ffffffff82bdb940 r panel_cntl_regs +ffffffff82bdb960 r panel_cntl_shift +ffffffff82bdb970 r panel_cntl_mask +ffffffff82bdb9b0 r link_enc_regs +ffffffff82bdbc40 r link_enc_aux_regs +ffffffff82bdbc60 r link_enc_hpd_regs +ffffffff82bdbc68 r le_shift +ffffffff82bdbd58 r le_mask +ffffffff82bdc110 r link_enc_feature +ffffffff82bdc120 r panel_config_defaults +ffffffff82bdc15c r cs_shift +ffffffff82bdc168 r cs_mask +ffffffff82bdc190 r hubbub_reg +ffffffff82bdc304 r hubbub_shift +ffffffff82bdc38c r hubbub_mask +ffffffff82bdc5b0 r vmid_regs +ffffffff82bdc770 r vmid_shifts +ffffffff82bdc778 r vmid_masks +ffffffff82bdc7a0 r hubp_regs +ffffffff82bdcbb8 r hubp_shift +ffffffff82bdccb4 r hubp_mask +ffffffff82bdd0b0 r dpp_regs +ffffffff82bddb30 r tf_shift +ffffffff82bdde00 r tf_mask +ffffffff82bde940 r opp_regs +ffffffff82bde9f0 r opp_shift +ffffffff82bdea28 r opp_mask +ffffffff82bdeb00 r optc_regs +ffffffff82bded80 r optc_shift +ffffffff82bdee40 r optc_mask +ffffffff82bdf140 r mpc_regs +ffffffff82be092c r mpc_shift +ffffffff82be0a08 r mpc_mask +ffffffff82be0d80 r dsc_regs +ffffffff82be0f08 r dsc_shift +ffffffff82be0fc0 r dsc_mask +ffffffff82be12a0 r dwbc30_regs +ffffffff82be147c r dwbc30_shift +ffffffff82be15b0 r dwbc30_mask +ffffffff82be1a80 r mcif_wb30_regs +ffffffff82be1b7c r mcif_wb30_shift +ffffffff82be1c28 r mcif_wb30_mask +ffffffff82be1ee0 r aux_engine_regs +ffffffff82be1f30 r aux_mask +ffffffff82be1f90 r aux_shift +ffffffff82be1fb0 r i2c_hw_regs +ffffffff82be2020 r i2c_shifts +ffffffff82be204c r i2c_masks +ffffffff82be20f0 r audio_regs +ffffffff82be2224 r audio_shift +ffffffff82be223c r audio_mask +ffffffff82be2280 r stream_enc_regs +ffffffff82be2528 r se_shift +ffffffff82be2604 r se_mask +ffffffff82be2970 r vpg_regs +ffffffff82be29ac r vpg_shift +ffffffff82be29d4 r vpg_mask +ffffffff82be2a70 r afmt_regs +ffffffff82be2adc r afmt_shift +ffffffff82be2af0 r afmt_mask +ffffffff82be2b34 r hwseq_reg +ffffffff82be2d50 r hwseq_shift +ffffffff82be2dd0 r hwseq_mask +ffffffff82be3000 r dccg31_funcs +ffffffff82be4000 r dcn31_link_enc_funcs +ffffffff82be5000 r dcn30_str_enc_funcs +ffffffff82be6000 r hubbub31_funcs +ffffffff82be7000 r dcn31_funcs +ffffffff82be72c0 r dcn31_private_funcs +ffffffff82be8000 r dcn31_link_panel_cntl_funcs +ffffffff82be9000 r bios_regs +ffffffff82be9008 r res_cap_dcn31 +ffffffff82be9048 r debug_defaults_diags +ffffffff82be91c0 r clk_src_regs +ffffffff82be9370 r clk_src_regs_b0 +ffffffff82be9514 r dccg_regs +ffffffff82be9600 r dccg_shift +ffffffff82be9698 r dccg_mask +ffffffff82be9900 r abm_regs +ffffffff82be9a00 r abm_shift +ffffffff82be9a14 r abm_mask +ffffffff82be9a60 r res_create_funcs +ffffffff82be9a90 r res_create_maximus_funcs +ffffffff82be9ac0 r plane_cap +ffffffff82be9af0 r link_enc_regs +ffffffff82bea150 r link_enc_aux_regs +ffffffff82bea1a0 r link_enc_hpd_regs +ffffffff82bea1b4 r le_shift +ffffffff82bea2a4 r le_mask +ffffffff82bea65c r link_enc_feature +ffffffff82bea66c r panel_config_defaults +ffffffff82bea6a8 r debug_defaults_drv +ffffffff82bea820 r cs_shift +ffffffff82bea82c r cs_mask +ffffffff82bea854 r hubbub_reg +ffffffff82bea9c8 r hubbub_shift +ffffffff82beaa50 r hubbub_mask +ffffffff82beac70 r vmid_regs +ffffffff82beae30 r vmid_shifts +ffffffff82beae38 r vmid_masks +ffffffff82beae60 r hubp_regs +ffffffff82beb690 r hubp_shift +ffffffff82beb78c r hubp_mask +ffffffff82bebb80 r dpp_regs +ffffffff82bed080 r tf_shift +ffffffff82bed350 r tf_mask +ffffffff82bede90 r opp_regs +ffffffff82bedff0 r opp_shift +ffffffff82bee028 r opp_mask +ffffffff82bee100 r optc_regs +ffffffff82bee600 r optc_shift +ffffffff82bee6c0 r optc_mask +ffffffff82bee9c0 r mpc_regs +ffffffff82bf01ac r mpc_shift +ffffffff82bf0288 r mpc_mask +ffffffff82bf0600 r dsc_regs +ffffffff82bf084c r dsc_shift +ffffffff82bf0904 r dsc_mask +ffffffff82bf0be0 r dwbc30_regs +ffffffff82bf0dbc r dwbc30_shift +ffffffff82bf0ef0 r dwbc30_mask +ffffffff82bf13c0 r mcif_wb30_regs +ffffffff82bf14bc r mcif_wb30_shift +ffffffff82bf1568 r mcif_wb30_mask +ffffffff82bf1820 r aux_engine_regs +ffffffff82bf18e8 r aux_mask +ffffffff82bf1948 r aux_shift +ffffffff82bf1960 r i2c_hw_regs +ffffffff82bf1a78 r i2c_shifts +ffffffff82bf1aa4 r i2c_masks +ffffffff82bf1b50 r audio_regs +ffffffff82bf1c84 r audio_shift +ffffffff82bf1c9c r audio_mask +ffffffff82bf1cd8 r se_shift +ffffffff82bf1db4 r se_mask +ffffffff82bf2120 r vpg_regs +ffffffff82bf2210 r vpg_shift +ffffffff82bf2238 r vpg_mask +ffffffff82bf22e0 r afmt_regs +ffffffff82bf23b8 r afmt_shift +ffffffff82bf23cc r afmt_mask +ffffffff82bf2420 r stream_enc_regs +ffffffff82bf3ac0 r hpo_dp_stream_enc_regs +ffffffff82bf3cf0 r hpo_dp_se_shift +ffffffff82bf3d18 r hpo_dp_se_mask +ffffffff82bf3dc0 r apg_regs +ffffffff82bf3e00 r apg_shift +ffffffff82bf3e08 r apg_mask +ffffffff82bf3e20 r hpo_dp_link_enc_regs +ffffffff82bf3f30 r hpo_dp_le_shift +ffffffff82bf3f4c r hpo_dp_le_mask +ffffffff82bf3fb0 r hwseq_reg +ffffffff82bf41cc r hwseq_shift +ffffffff82bf424c r hwseq_mask +ffffffff82bf5000 r dccg314_funcs +ffffffff82bf6000 r dcn314_str_enc_funcs +ffffffff82bf7000 r dcn314_funcs +ffffffff82bf72c0 r dcn314_private_funcs +ffffffff82bf8000 r bios_regs +ffffffff82bf8008 r res_cap_dcn314 +ffffffff82bf8048 r debug_defaults_diags +ffffffff82bf81c0 r clk_src_regs +ffffffff82bf8364 r dccg_regs +ffffffff82bf8450 r dccg_shift +ffffffff82bf84e8 r dccg_mask +ffffffff82bf8750 r abm_regs +ffffffff82bf8850 r abm_shift +ffffffff82bf8864 r abm_mask +ffffffff82bf88b0 r res_create_funcs +ffffffff82bf88e0 r res_create_maximus_funcs +ffffffff82bf8910 r plane_cap +ffffffff82bf8940 r link_enc_regs +ffffffff82bf8fa0 r link_enc_aux_regs +ffffffff82bf8ff0 r link_enc_hpd_regs +ffffffff82bf9004 r le_shift +ffffffff82bf90f4 r le_mask +ffffffff82bf94ac r link_enc_feature +ffffffff82bf94bc r panel_config_defaults +ffffffff82bf94f8 r debug_defaults_drv +ffffffff82bf9670 r cs_shift +ffffffff82bf967c r cs_mask +ffffffff82bf96a4 r hubbub_reg +ffffffff82bf9818 r hubbub_shift +ffffffff82bf98a0 r hubbub_mask +ffffffff82bf9ac0 r vmid_regs +ffffffff82bf9c80 r vmid_shifts +ffffffff82bf9c88 r vmid_masks +ffffffff82bf9cb0 r hubp_regs +ffffffff82bfa4e0 r hubp_shift +ffffffff82bfa5dc r hubp_mask +ffffffff82bfa9d0 r dpp_regs +ffffffff82bfbed0 r tf_shift +ffffffff82bfc1a0 r tf_mask +ffffffff82bfcce0 r opp_regs +ffffffff82bfce40 r opp_shift +ffffffff82bfce78 r opp_mask +ffffffff82bfcf50 r optc_regs +ffffffff82bfd450 r optc_shift +ffffffff82bfd510 r optc_mask +ffffffff82bfd810 r mpc_regs +ffffffff82bfeffc r mpc_shift +ffffffff82bff0d8 r mpc_mask +ffffffff82bff450 r dsc_regs +ffffffff82bff760 r dsc_shift +ffffffff82bff818 r dsc_mask +ffffffff82bffaf0 r dwbc30_regs +ffffffff82bffccc r dwbc30_shift +ffffffff82bffe00 r dwbc30_mask +ffffffff82c002d0 r mcif_wb30_regs +ffffffff82c003cc r mcif_wb30_shift +ffffffff82c00478 r mcif_wb30_mask +ffffffff82c00730 r aux_engine_regs +ffffffff82c007f8 r aux_mask +ffffffff82c00858 r aux_shift +ffffffff82c00870 r i2c_hw_regs +ffffffff82c00988 r i2c_shifts +ffffffff82c009b4 r i2c_masks +ffffffff82c00a60 r audio_regs +ffffffff82c00b94 r audio_shift +ffffffff82c00bac r audio_mask +ffffffff82c00bf0 r stream_enc_regs +ffffffff82c01294 r se_shift +ffffffff82c01370 r se_mask +ffffffff82c016e0 r vpg_regs +ffffffff82c017d0 r vpg_shift +ffffffff82c017f8 r vpg_mask +ffffffff82c018a0 r afmt_regs +ffffffff82c01978 r afmt_shift +ffffffff82c0198c r afmt_mask +ffffffff82c019e0 r hpo_dp_stream_enc_regs +ffffffff82c01c10 r hpo_dp_se_shift +ffffffff82c01c38 r hpo_dp_se_mask +ffffffff82c01ce0 r apg_regs +ffffffff82c01d20 r apg_shift +ffffffff82c01d28 r apg_mask +ffffffff82c01d40 r hpo_dp_link_enc_regs +ffffffff82c01e50 r hpo_dp_le_shift +ffffffff82c01e6c r hpo_dp_le_mask +ffffffff82c01ed0 r hwseq_reg +ffffffff82c020ec r hwseq_shift +ffffffff82c0216c r hwseq_mask +ffffffff82c03000 r bios_regs +ffffffff82c03008 r res_cap_dcn31 +ffffffff82c03048 r debug_defaults_diags +ffffffff82c031c0 r clk_src_regs +ffffffff82c03364 r dccg_regs +ffffffff82c03450 r dccg_shift +ffffffff82c034e8 r dccg_mask +ffffffff82c03750 r abm_regs +ffffffff82c03850 r abm_shift +ffffffff82c03864 r abm_mask +ffffffff82c038b0 r res_create_funcs +ffffffff82c038e0 r res_create_maximus_funcs +ffffffff82c03910 r plane_cap +ffffffff82c03940 r link_enc_regs +ffffffff82c03fa0 r link_enc_aux_regs +ffffffff82c03ff0 r link_enc_hpd_regs +ffffffff82c04004 r le_shift +ffffffff82c040f4 r le_mask +ffffffff82c044ac r link_enc_feature +ffffffff82c044bc r panel_config_defaults +ffffffff82c044f8 r debug_defaults_drv +ffffffff82c04670 r cs_shift +ffffffff82c0467c r cs_mask +ffffffff82c046a4 r hubbub_reg +ffffffff82c04818 r hubbub_shift +ffffffff82c048a0 r hubbub_mask +ffffffff82c04ac0 r vmid_regs +ffffffff82c04c80 r vmid_shifts +ffffffff82c04c88 r vmid_masks +ffffffff82c04cb0 r hubp_regs +ffffffff82c054e0 r hubp_shift +ffffffff82c055dc r hubp_mask +ffffffff82c059d0 r dpp_regs +ffffffff82c06ed0 r tf_shift +ffffffff82c071a0 r tf_mask +ffffffff82c07ce0 r opp_regs +ffffffff82c07e40 r opp_shift +ffffffff82c07e78 r opp_mask +ffffffff82c07f50 r optc_regs +ffffffff82c08450 r optc_shift +ffffffff82c08510 r optc_mask +ffffffff82c08810 r mpc_regs +ffffffff82c09ffc r mpc_shift +ffffffff82c0a0d8 r mpc_mask +ffffffff82c0a450 r dsc_regs +ffffffff82c0a69c r dsc_shift +ffffffff82c0a754 r dsc_mask +ffffffff82c0aa30 r dwbc30_regs +ffffffff82c0ac0c r dwbc30_shift +ffffffff82c0ad40 r dwbc30_mask +ffffffff82c0b210 r mcif_wb30_regs +ffffffff82c0b30c r mcif_wb30_shift +ffffffff82c0b3b8 r mcif_wb30_mask +ffffffff82c0b670 r aux_engine_regs +ffffffff82c0b738 r aux_mask +ffffffff82c0b798 r aux_shift +ffffffff82c0b7b0 r i2c_hw_regs +ffffffff82c0b8c8 r i2c_shifts +ffffffff82c0b8f4 r i2c_masks +ffffffff82c0b9a0 r audio_regs +ffffffff82c0bad4 r audio_shift +ffffffff82c0baec r audio_mask +ffffffff82c0bb30 r stream_enc_regs +ffffffff82c0c1d4 r se_shift +ffffffff82c0c2b0 r se_mask +ffffffff82c0c620 r vpg_regs +ffffffff82c0c710 r vpg_shift +ffffffff82c0c738 r vpg_mask +ffffffff82c0c7e0 r afmt_regs +ffffffff82c0c8b8 r afmt_shift +ffffffff82c0c8cc r afmt_mask +ffffffff82c0c920 r hpo_dp_stream_enc_regs +ffffffff82c0cb50 r hpo_dp_se_shift +ffffffff82c0cb78 r hpo_dp_se_mask +ffffffff82c0cc20 r apg_regs +ffffffff82c0cc60 r apg_shift +ffffffff82c0cc68 r apg_mask +ffffffff82c0cc80 r hpo_dp_link_enc_regs +ffffffff82c0cd90 r hpo_dp_le_shift +ffffffff82c0cdac r hpo_dp_le_mask +ffffffff82c0ce10 r hwseq_reg +ffffffff82c0d02c r hwseq_shift +ffffffff82c0d0ac r hwseq_mask +ffffffff82c0e000 r bios_regs +ffffffff82c0e008 r res_cap_dcn31 +ffffffff82c0e048 r debug_defaults_diags +ffffffff82c0e1c0 r clk_src_regs +ffffffff82c0e364 r dccg_regs +ffffffff82c0e450 r dccg_shift +ffffffff82c0e4e8 r dccg_mask +ffffffff82c0e750 r abm_regs +ffffffff82c0e850 r abm_shift +ffffffff82c0e864 r abm_mask +ffffffff82c0e8b0 r res_create_funcs +ffffffff82c0e8e0 r res_create_maximus_funcs +ffffffff82c0e910 r plane_cap +ffffffff82c0e940 r link_enc_regs +ffffffff82c0efa0 r link_enc_aux_regs +ffffffff82c0eff0 r link_enc_hpd_regs +ffffffff82c0f004 r le_shift +ffffffff82c0f0f4 r le_mask +ffffffff82c0f4ac r link_enc_feature +ffffffff82c0f4bc r panel_config_defaults +ffffffff82c0f4f8 r debug_defaults_drv +ffffffff82c0f670 r cs_shift +ffffffff82c0f67c r cs_mask +ffffffff82c0f6a4 r hubbub_reg +ffffffff82c0f818 r hubbub_shift +ffffffff82c0f8a0 r hubbub_mask +ffffffff82c0fac0 r vmid_regs +ffffffff82c0fc80 r vmid_shifts +ffffffff82c0fc88 r vmid_masks +ffffffff82c0fcb0 r hubp_regs +ffffffff82c104e0 r hubp_shift +ffffffff82c105dc r hubp_mask +ffffffff82c109d0 r dpp_regs +ffffffff82c11ed0 r tf_shift +ffffffff82c121a0 r tf_mask +ffffffff82c12ce0 r opp_regs +ffffffff82c12e40 r opp_shift +ffffffff82c12e78 r opp_mask +ffffffff82c12f50 r optc_regs +ffffffff82c13450 r optc_shift +ffffffff82c13510 r optc_mask +ffffffff82c13810 r mpc_regs +ffffffff82c14ffc r mpc_shift +ffffffff82c150d8 r mpc_mask +ffffffff82c15450 r dsc_regs +ffffffff82c1569c r dsc_shift +ffffffff82c15754 r dsc_mask +ffffffff82c15a30 r dwbc30_regs +ffffffff82c15c0c r dwbc30_shift +ffffffff82c15d40 r dwbc30_mask +ffffffff82c16210 r mcif_wb30_regs +ffffffff82c1630c r mcif_wb30_shift +ffffffff82c163b8 r mcif_wb30_mask +ffffffff82c16670 r aux_engine_regs +ffffffff82c16738 r aux_mask +ffffffff82c16798 r aux_shift +ffffffff82c167b0 r i2c_hw_regs +ffffffff82c168c8 r i2c_shifts +ffffffff82c168f4 r i2c_masks +ffffffff82c169a0 r audio_regs +ffffffff82c16ad4 r audio_shift +ffffffff82c16aec r audio_mask +ffffffff82c16b30 r stream_enc_regs +ffffffff82c171d4 r se_shift +ffffffff82c172b0 r se_mask +ffffffff82c17620 r vpg_regs +ffffffff82c17710 r vpg_shift +ffffffff82c17738 r vpg_mask +ffffffff82c177e0 r afmt_regs +ffffffff82c178b8 r afmt_shift +ffffffff82c178cc r afmt_mask +ffffffff82c17920 r hpo_dp_stream_enc_regs +ffffffff82c17b50 r hpo_dp_se_shift +ffffffff82c17b78 r hpo_dp_se_mask +ffffffff82c17c20 r apg_regs +ffffffff82c17c60 r apg_shift +ffffffff82c17c68 r apg_mask +ffffffff82c17c80 r hpo_dp_link_enc_regs +ffffffff82c17d90 r hpo_dp_le_shift +ffffffff82c17dac r hpo_dp_le_mask +ffffffff82c17e10 r hwseq_reg +ffffffff82c1802c r hwseq_shift +ffffffff82c180ac r hwseq_mask +ffffffff82c19000 r dccg32_funcs +ffffffff82c1a000 r dcn32_link_enc_funcs +ffffffff82c1b000 r dcn32_str_enc_funcs +ffffffff82c1c000 r hubbub32_funcs +ffffffff82c1d000 r dcn32_funcs +ffffffff82c1d2c0 r dcn32_private_funcs +ffffffff82c1e000 R dcn32_mmhubbub_funcs +ffffffff82c1f000 R dcn32_mpc_funcs +ffffffff82c20000 r res_cap_dcn32 +ffffffff82c20040 r debug_defaults_diags +ffffffff82c201b8 r dccg_shift +ffffffff82c20250 r dccg_mask +ffffffff82c204ac r abm_shift +ffffffff82c204c0 r abm_mask +ffffffff82c20508 r res_create_funcs +ffffffff82c20538 r res_create_maximus_funcs +ffffffff82c20568 r plane_cap +ffffffff82c20594 r le_shift +ffffffff82c20684 r le_mask +ffffffff82c20a3c r link_enc_feature +ffffffff82c20a50 r debug_defaults_drv +ffffffff82c20bc8 r cs_shift +ffffffff82c20bd4 r cs_mask +ffffffff82c20bfc r hubbub_shift +ffffffff82c20c84 r hubbub_mask +ffffffff82c20ea0 r vmid_shifts +ffffffff82c20ea8 r vmid_masks +ffffffff82c20ec8 r hubp_shift +ffffffff82c20fc4 r hubp_mask +ffffffff82c213b4 r tf_shift +ffffffff82c21684 r tf_mask +ffffffff82c221c4 r opp_shift +ffffffff82c221fc r opp_mask +ffffffff82c222d0 r optc_shift +ffffffff82c22390 r optc_mask +ffffffff82c22690 r mpc_shift +ffffffff82c2276c r mpc_mask +ffffffff82c22ad8 r dsc_shift +ffffffff82c22b90 r dsc_mask +ffffffff82c22e68 r dwbc30_shift +ffffffff82c22f9c r dwbc30_mask +ffffffff82c23464 r mcif_wb30_shift +ffffffff82c23510 r mcif_wb30_mask +ffffffff82c237bc r aux_mask +ffffffff82c2381c r aux_shift +ffffffff82c23834 r i2c_shifts +ffffffff82c23860 r i2c_masks +ffffffff82c23904 r audio_shift +ffffffff82c2391c r audio_mask +ffffffff82c23958 r se_shift +ffffffff82c23a34 r se_mask +ffffffff82c23da0 r vpg_shift +ffffffff82c23dc8 r vpg_mask +ffffffff82c23e5c r afmt_shift +ffffffff82c23e70 r afmt_mask +ffffffff82c23eb4 r hpo_dp_se_shift +ffffffff82c23edc r hpo_dp_se_mask +ffffffff82c23f7c r apg_shift +ffffffff82c23f84 r apg_mask +ffffffff82c23f9c r hpo_dp_le_shift +ffffffff82c23fb8 r hpo_dp_le_mask +ffffffff82c2401c r hwseq_shift +ffffffff82c2409c r hwseq_mask +ffffffff82c25000 r dcn321_link_enc_funcs +ffffffff82c26000 r res_cap_dcn321 +ffffffff82c26040 r debug_defaults_diags +ffffffff82c261b8 r dccg_shift +ffffffff82c26250 r dccg_mask +ffffffff82c264ac r abm_shift +ffffffff82c264c0 r abm_mask +ffffffff82c26508 r res_create_funcs +ffffffff82c26538 r res_create_maximus_funcs +ffffffff82c26568 r plane_cap +ffffffff82c26594 r le_shift +ffffffff82c26684 r le_mask +ffffffff82c26a3c r link_enc_feature +ffffffff82c26a50 r debug_defaults_drv +ffffffff82c26bc8 r cs_shift +ffffffff82c26bd4 r cs_mask +ffffffff82c26bfc r hubbub_shift +ffffffff82c26c84 r hubbub_mask +ffffffff82c26ea0 r vmid_shifts +ffffffff82c26ea8 r vmid_masks +ffffffff82c26ec8 r hubp_shift +ffffffff82c26fc4 r hubp_mask +ffffffff82c273b4 r tf_shift +ffffffff82c27684 r tf_mask +ffffffff82c281c4 r opp_shift +ffffffff82c281fc r opp_mask +ffffffff82c282d0 r optc_shift +ffffffff82c28390 r optc_mask +ffffffff82c28690 r mpc_shift +ffffffff82c2876c r mpc_mask +ffffffff82c28ad8 r dsc_shift +ffffffff82c28b90 r dsc_mask +ffffffff82c28e68 r dwbc30_shift +ffffffff82c28f9c r dwbc30_mask +ffffffff82c29464 r mcif_wb30_shift +ffffffff82c29510 r mcif_wb30_mask +ffffffff82c297bc r aux_mask +ffffffff82c2981c r aux_shift +ffffffff82c29834 r i2c_shifts +ffffffff82c29860 r i2c_masks +ffffffff82c29904 r audio_shift +ffffffff82c2991c r audio_mask +ffffffff82c29958 r se_shift +ffffffff82c29a34 r se_mask +ffffffff82c29da0 r vpg_shift +ffffffff82c29dc8 r vpg_mask +ffffffff82c29e5c r afmt_shift +ffffffff82c29e70 r afmt_mask +ffffffff82c29eb4 r hpo_dp_se_shift +ffffffff82c29edc r hpo_dp_se_mask +ffffffff82c29f7c r apg_shift +ffffffff82c29f84 r apg_mask +ffffffff82c29f9c r hpo_dp_le_shift +ffffffff82c29fb8 r hpo_dp_le_mask +ffffffff82c2a01c r hwseq_shift +ffffffff82c2a09c r hwseq_mask +ffffffff82c2c000 R dcn10_soc_defaults +ffffffff82c2c08c R dcn10_ip_defaults +ffffffff82c37000 R dml20_funcs +ffffffff82c37030 R dml20v2_funcs +ffffffff82c37060 R dml21_funcs +ffffffff82c37090 R dml30_funcs +ffffffff82c370c0 R dml31_funcs +ffffffff82c370f0 R dml314_funcs +ffffffff82c37120 R dml32_funcs +ffffffff82c3a000 R qp_table_422_10bpc_min +ffffffff82c3a740 R qp_table_444_8bpc_max +ffffffff82c3b080 R qp_table_420_12bpc_max +ffffffff82c3b7c0 R qp_table_444_10bpc_min +ffffffff82c3c400 R qp_table_420_8bpc_max +ffffffff82c3c840 R qp_table_444_8bpc_min +ffffffff82c3d180 R qp_table_444_12bpc_min +ffffffff82c3e0c0 R qp_table_420_12bpc_min +ffffffff82c3e800 R qp_table_422_12bpc_min +ffffffff82c3f140 R qp_table_422_12bpc_max +ffffffff82c3fa80 R qp_table_444_12bpc_max +ffffffff82c409c0 R qp_table_420_8bpc_min +ffffffff82c40e00 R qp_table_422_8bpc_min +ffffffff82c41340 R qp_table_422_10bpc_max +ffffffff82c41a80 R qp_table_420_10bpc_max +ffffffff82c42040 R qp_table_420_10bpc_min +ffffffff82c42600 R qp_table_444_10bpc_max +ffffffff82c43240 R qp_table_422_8bpc_max ffffffff82c45000 r funcs +ffffffff82c45050 r hpd_regs +ffffffff82c451a0 r hpd_shift +ffffffff82c451b0 r hpd_mask +ffffffff82c451c0 r ddc_data_regs +ffffffff82c453a0 r ddc_clk_regs +ffffffff82c45580 r ddc_shift +ffffffff82c455a8 r ddc_mask ffffffff82c46000 r funcs -ffffffff82c46050 r hpd_regs -ffffffff82c461a0 r hpd_shift -ffffffff82c461b0 r hpd_mask -ffffffff82c461c0 r ddc_data_regs -ffffffff82c463a0 r ddc_clk_regs -ffffffff82c46580 r ddc_shift -ffffffff82c465a8 r ddc_mask ffffffff82c47000 r funcs +ffffffff82c47050 r hpd_regs +ffffffff82c471a0 r hpd_shift +ffffffff82c471b0 r hpd_mask +ffffffff82c471c0 r ddc_data_regs +ffffffff82c473a0 r ddc_clk_regs +ffffffff82c47580 r ddc_shift +ffffffff82c475a8 r ddc_mask ffffffff82c48000 r funcs -ffffffff82c48050 r hpd_regs -ffffffff82c481a0 r hpd_shift -ffffffff82c481b0 r hpd_mask -ffffffff82c481c0 r ddc_data_regs -ffffffff82c483a0 r ddc_clk_regs -ffffffff82c48580 r ddc_shift -ffffffff82c485a8 r ddc_mask ffffffff82c49000 r funcs +ffffffff82c49050 r hpd_regs +ffffffff82c491a0 r hpd_shift +ffffffff82c491b0 r hpd_mask +ffffffff82c491c0 r ddc_data_regs +ffffffff82c493a0 r ddc_clk_regs +ffffffff82c49580 r ddc_shift +ffffffff82c495a8 r ddc_mask ffffffff82c4a000 r funcs -ffffffff82c4a050 r hpd_regs -ffffffff82c4a1a0 r hpd_shift -ffffffff82c4a1b0 r hpd_mask -ffffffff82c4a1c0 r ddc_data_regs -ffffffff82c4a3a0 r ddc_clk_regs -ffffffff82c4a580 r ddc_shift -ffffffff82c4a5a8 r ddc_mask -ffffffff82c4a5d0 r generic_regs -ffffffff82c4a640 r generic_shift -ffffffff82c4a650 r generic_mask ffffffff82c4b000 r funcs +ffffffff82c4b050 r hpd_regs +ffffffff82c4b1a0 r hpd_shift +ffffffff82c4b1b0 r hpd_mask +ffffffff82c4b1c0 r ddc_data_regs +ffffffff82c4b3a0 r ddc_clk_regs +ffffffff82c4b580 r ddc_shift +ffffffff82c4b5a8 r ddc_mask +ffffffff82c4b5d0 r generic_regs +ffffffff82c4b640 r generic_shift +ffffffff82c4b650 r generic_mask ffffffff82c4c000 r funcs -ffffffff82c4c050 r hpd_regs -ffffffff82c4c1a0 r hpd_shift -ffffffff82c4c1b0 r hpd_mask -ffffffff82c4c1c0 r ddc_data_regs_dcn -ffffffff82c4c370 r ddc_clk_regs_dcn -ffffffff82c4c520 r ddc_shift -ffffffff82c4c640 r ddc_mask -ffffffff82c4c760 r generic_regs -ffffffff82c4c7d0 r generic_shift -ffffffff82c4c7e0 r generic_mask ffffffff82c4d000 r funcs +ffffffff82c4d050 r hpd_regs +ffffffff82c4d1a0 r hpd_shift +ffffffff82c4d1b0 r hpd_mask +ffffffff82c4d1c0 r ddc_data_regs_dcn +ffffffff82c4d370 r ddc_clk_regs_dcn +ffffffff82c4d520 r ddc_shift +ffffffff82c4d640 r ddc_mask +ffffffff82c4d760 r generic_regs +ffffffff82c4d7d0 r generic_shift +ffffffff82c4d7e0 r generic_mask ffffffff82c4e000 r funcs -ffffffff82c4e050 r hpd_regs -ffffffff82c4e168 r hpd_shift -ffffffff82c4e178 r hpd_mask -ffffffff82c4e190 r ddc_data_regs_dcn -ffffffff82c4e2c0 r ddc_clk_regs_dcn -ffffffff82c4e3f0 r ddc_shift -ffffffff82c4e4e0 r ddc_mask -ffffffff82c4e5d0 r generic_regs -ffffffff82c4e604 r generic_shift -ffffffff82c4e60c r generic_mask ffffffff82c4f000 r funcs +ffffffff82c4f050 r hpd_regs +ffffffff82c4f168 r hpd_shift +ffffffff82c4f178 r hpd_mask +ffffffff82c4f190 r ddc_data_regs_dcn +ffffffff82c4f2c0 r ddc_clk_regs_dcn +ffffffff82c4f3f0 r ddc_shift +ffffffff82c4f4e0 r ddc_mask +ffffffff82c4f5d0 r generic_regs +ffffffff82c4f604 r generic_shift +ffffffff82c4f60c r generic_mask ffffffff82c50000 r funcs -ffffffff82c50050 r hpd_regs -ffffffff82c501a0 r hpd_shift -ffffffff82c501b0 r hpd_mask -ffffffff82c501c0 r ddc_data_regs_dcn -ffffffff82c50370 r ddc_clk_regs_dcn -ffffffff82c50520 r ddc_shift -ffffffff82c50640 r ddc_mask -ffffffff82c50760 r generic_regs -ffffffff82c507d0 r generic_shift -ffffffff82c507e0 r generic_mask ffffffff82c51000 r funcs +ffffffff82c51050 r hpd_regs +ffffffff82c511a0 r hpd_shift +ffffffff82c511b0 r hpd_mask +ffffffff82c511c0 r ddc_data_regs_dcn +ffffffff82c51370 r ddc_clk_regs_dcn +ffffffff82c51520 r ddc_shift +ffffffff82c51640 r ddc_mask +ffffffff82c51760 r generic_regs +ffffffff82c517d0 r generic_shift +ffffffff82c517e0 r generic_mask ffffffff82c52000 r funcs -ffffffff82c52050 r hpd_regs -ffffffff82c52168 r hpd_shift -ffffffff82c52178 r hpd_mask -ffffffff82c52190 r ddc_data_regs_dcn -ffffffff82c52300 r ddc_clk_regs_dcn -ffffffff82c52470 r ddc_shift -ffffffff82c52560 r ddc_mask -ffffffff82c52650 r generic_regs -ffffffff82c526c0 r generic_shift -ffffffff82c526d0 r generic_mask ffffffff82c53000 r funcs +ffffffff82c53050 r hpd_regs +ffffffff82c53168 r hpd_shift +ffffffff82c53178 r hpd_mask +ffffffff82c53190 r ddc_data_regs_dcn +ffffffff82c53300 r ddc_clk_regs_dcn +ffffffff82c53470 r ddc_shift +ffffffff82c53560 r ddc_mask +ffffffff82c53650 r generic_regs +ffffffff82c536c0 r generic_shift +ffffffff82c536d0 r generic_mask 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irq_source_info_dce110 -ffffffff82c5b2a0 r dummy_irq_info_funcs -ffffffff82c5b2b0 r hpd_irq_info_funcs -ffffffff82c5b2c0 r hpd_rx_irq_info_funcs -ffffffff82c5b2d0 r pflip_irq_info_funcs -ffffffff82c5b2e0 r vupdate_irq_info_funcs -ffffffff82c5b2f0 r vblank_irq_info_funcs -ffffffff82c5c000 r irq_service_funcs_dce120 -ffffffff82c5c008 r dummy_irq_info_funcs -ffffffff82c5c018 r hpd_irq_info_funcs -ffffffff82c5c028 r hpd_rx_irq_info_funcs -ffffffff82c5c038 r pflip_irq_info_funcs -ffffffff82c5c048 r vupdate_irq_info_funcs -ffffffff82c5c058 r vblank_irq_info_funcs -ffffffff82c5c070 r irq_source_info_dce120 -ffffffff82c5e000 r irq_service_funcs_dce80 -ffffffff82c5e008 r dummy_irq_info_funcs -ffffffff82c5e018 r hpd_irq_info_funcs -ffffffff82c5e028 r hpd_rx_irq_info_funcs -ffffffff82c5e038 r pflip_irq_info_funcs -ffffffff82c5e048 r vupdate_irq_info_funcs -ffffffff82c5e058 r vblank_irq_info_funcs -ffffffff82c5e070 r irq_source_info_dce80 -ffffffff82c60000 r irq_service_funcs_dcn10 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r vblank_irq_info_funcs -ffffffff82c64068 r vline0_irq_info_funcs -ffffffff82c64080 r irq_source_info_dcn201 -ffffffff82c66000 r irq_source_info_dcn21 -ffffffff82c67290 r irq_service_funcs_dcn21 -ffffffff82c67298 r dummy_irq_info_funcs -ffffffff82c672a8 r hpd_irq_info_funcs -ffffffff82c672b8 r hpd_rx_irq_info_funcs -ffffffff82c672c8 r pflip_irq_info_funcs -ffffffff82c672d8 r vupdate_no_lock_irq_info_funcs -ffffffff82c672e8 r vblank_irq_info_funcs -ffffffff82c672f8 r vline0_irq_info_funcs -ffffffff82c67308 r dmub_outbox_irq_info_funcs -ffffffff82c68000 r irq_source_info_dcn30 -ffffffff82c69290 r irq_service_funcs_dcn30 -ffffffff82c69298 r dummy_irq_info_funcs -ffffffff82c692a8 r hpd_irq_info_funcs -ffffffff82c692b8 r hpd_rx_irq_info_funcs -ffffffff82c692c8 r pflip_irq_info_funcs -ffffffff82c692d8 r vupdate_no_lock_irq_info_funcs -ffffffff82c692e8 r vblank_irq_info_funcs -ffffffff82c692f8 r vline0_irq_info_funcs -ffffffff82c69308 r dmub_trace_irq_info_funcs -ffffffff82c6a000 r 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dmub_srv_dcn303_regs -ffffffff82c82000 R dmub_srv_dcn31_regs -ffffffff82c83000 R dmub_srv_dcn315_regs -ffffffff82c84000 R dmub_srv_dcn316_regs -ffffffff82c85000 R dmub_srv_dcn32_regs -ffffffff82c86000 r numerator01 -ffffffff82c86020 r numerator02 -ffffffff82c86040 r numerator04 -ffffffff82c86060 r numerator05 -ffffffff82c88000 r abm_settings -ffffffff82c88010 r abm_settings_config0 -ffffffff82c88050 r abm_settings_config1 -ffffffff82c88088 r min_reduction_table_v_2_2 -ffffffff82c88095 r max_reduction_table_v_2_2 -ffffffff82c880a2 r min_reduction_table -ffffffff82c880af r max_reduction_table -ffffffff82c89000 R amdgpu_pp_profile_name -ffffffff82c8a000 r pp_lib_thermal_controller_names -ffffffff82c8b000 r pp_ip_funcs -ffffffff82c8b0a0 R pp_smu_ip_block -ffffffff82c8b0b8 r pp_dpm_funcs -ffffffff82c8c000 r gpio_tbl -ffffffff82c8c0f0 r enable_fb_req_rej_tbl -ffffffff82c8c140 r use_bclk_tbl -ffffffff82c8c310 r turn_off_plls_tbl -ffffffff82c8c640 r enter_baco_tbl -ffffffff82c8c730 r exit_baco_tbl -ffffffff82c8c850 r clean_baco_tbl +ffffffff82c59000 r funcs +ffffffff82c5a000 r hdmi_14_protection +ffffffff82c5a010 r dp_11_protection +ffffffff82c5a020 r hdcp_i2c_offsets +ffffffff82c5a050 r hdcp_dpcd_addrs +ffffffff82c5b000 r irq_service_funcs_dce110 +ffffffff82c5b010 r irq_source_info_dce110 +ffffffff82c5c2a0 r dummy_irq_info_funcs +ffffffff82c5c2b0 r hpd_irq_info_funcs +ffffffff82c5c2c0 r hpd_rx_irq_info_funcs +ffffffff82c5c2d0 r pflip_irq_info_funcs +ffffffff82c5c2e0 r vupdate_irq_info_funcs +ffffffff82c5c2f0 r vblank_irq_info_funcs +ffffffff82c5d000 r irq_service_funcs_dce120 +ffffffff82c5d008 r dummy_irq_info_funcs +ffffffff82c5d018 r hpd_irq_info_funcs +ffffffff82c5d028 r hpd_rx_irq_info_funcs +ffffffff82c5d038 r pflip_irq_info_funcs +ffffffff82c5d048 r vupdate_irq_info_funcs +ffffffff82c5d058 r vblank_irq_info_funcs +ffffffff82c5d070 r irq_source_info_dce120 +ffffffff82c5f000 r irq_service_funcs_dce80 +ffffffff82c5f008 r dummy_irq_info_funcs +ffffffff82c5f018 r hpd_irq_info_funcs +ffffffff82c5f028 r hpd_rx_irq_info_funcs +ffffffff82c5f038 r pflip_irq_info_funcs +ffffffff82c5f048 r vupdate_irq_info_funcs +ffffffff82c5f058 r vblank_irq_info_funcs +ffffffff82c5f070 r irq_source_info_dce80 +ffffffff82c61000 r irq_service_funcs_dcn10 +ffffffff82c61008 r dummy_irq_info_funcs +ffffffff82c61018 r hpd_irq_info_funcs +ffffffff82c61028 r hpd_rx_irq_info_funcs +ffffffff82c61038 r pflip_irq_info_funcs +ffffffff82c61048 r vupdate_no_lock_irq_info_funcs +ffffffff82c61058 r vblank_irq_info_funcs +ffffffff82c61068 r vline0_irq_info_funcs +ffffffff82c61080 r irq_source_info_dcn10 +ffffffff82c63000 r irq_service_funcs_dcn20 +ffffffff82c63008 r dummy_irq_info_funcs +ffffffff82c63018 r hpd_irq_info_funcs +ffffffff82c63028 r hpd_rx_irq_info_funcs +ffffffff82c63038 r pflip_irq_info_funcs +ffffffff82c63048 r vupdate_no_lock_irq_info_funcs +ffffffff82c63058 r vblank_irq_info_funcs +ffffffff82c63068 r vline0_irq_info_funcs +ffffffff82c63080 r irq_source_info_dcn20 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r hpd_rx_irq_info_funcs +ffffffff82c6a2c8 r pflip_irq_info_funcs +ffffffff82c6a2d8 r vupdate_no_lock_irq_info_funcs +ffffffff82c6a2e8 r vblank_irq_info_funcs +ffffffff82c6a2f8 r vline0_irq_info_funcs +ffffffff82c6a308 r dmub_trace_irq_info_funcs +ffffffff82c6b000 r irq_source_info_dcn302 +ffffffff82c6c290 r irq_service_funcs_dcn302 +ffffffff82c6c298 r dummy_irq_info_funcs +ffffffff82c6c2a8 r hpd_irq_info_funcs +ffffffff82c6c2b8 r hpd_rx_irq_info_funcs +ffffffff82c6c2c8 r pflip_irq_info_funcs +ffffffff82c6c2d8 r vupdate_no_lock_irq_info_funcs +ffffffff82c6c2e8 r vblank_irq_info_funcs +ffffffff82c6c2f8 r vline0_irq_info_funcs +ffffffff82c6c308 r dmub_trace_irq_info_funcs +ffffffff82c6d000 r irq_service_funcs_dcn303 +ffffffff82c6d008 r dummy_irq_info_funcs +ffffffff82c6d018 r hpd_irq_info_funcs +ffffffff82c6d028 r hpd_rx_irq_info_funcs +ffffffff82c6d038 r pflip_irq_info_funcs +ffffffff82c6d048 r vupdate_no_lock_irq_info_funcs +ffffffff82c6d058 r vblank_irq_info_funcs +ffffffff82c6d068 r vline0_irq_info_funcs +ffffffff82c6d080 r irq_source_info_dcn303 +ffffffff82c6f000 r irq_source_info_dcn31 +ffffffff82c70290 r irq_service_funcs_dcn31 +ffffffff82c70298 r dummy_irq_info_funcs +ffffffff82c702a8 r hpd_irq_info_funcs +ffffffff82c702b8 r hpd_rx_irq_info_funcs +ffffffff82c702c8 r pflip_irq_info_funcs +ffffffff82c702d8 r vupdate_no_lock_irq_info_funcs +ffffffff82c702e8 r vblank_irq_info_funcs +ffffffff82c702f8 r vline0_irq_info_funcs +ffffffff82c70308 r outbox_irq_info_funcs +ffffffff82c71000 r irq_source_info_dcn314 +ffffffff82c72290 r irq_service_funcs_dcn314 +ffffffff82c72298 r dummy_irq_info_funcs +ffffffff82c722a8 r hpd_irq_info_funcs +ffffffff82c722b8 r hpd_rx_irq_info_funcs +ffffffff82c722c8 r pflip_irq_info_funcs +ffffffff82c722d8 r vupdate_no_lock_irq_info_funcs +ffffffff82c722e8 r vblank_irq_info_funcs +ffffffff82c722f8 r vline0_irq_info_funcs +ffffffff82c72308 r outbox_irq_info_funcs +ffffffff82c73000 r irq_source_info_dcn315 +ffffffff82c74290 r irq_service_funcs_dcn315 +ffffffff82c74298 r dummy_irq_info_funcs +ffffffff82c742a8 r hpd_irq_info_funcs +ffffffff82c742b8 r hpd_rx_irq_info_funcs +ffffffff82c742c8 r pflip_irq_info_funcs +ffffffff82c742d8 r vupdate_no_lock_irq_info_funcs +ffffffff82c742e8 r vblank_irq_info_funcs +ffffffff82c742f8 r vline0_irq_info_funcs +ffffffff82c74308 r outbox_irq_info_funcs +ffffffff82c75000 r irq_source_info_dcn32 +ffffffff82c76290 r irq_service_funcs_dcn32 +ffffffff82c76298 r dummy_irq_info_funcs +ffffffff82c762a8 r hpd_irq_info_funcs +ffffffff82c762b8 r hpd_rx_irq_info_funcs +ffffffff82c762c8 r pflip_irq_info_funcs +ffffffff82c762d8 r vupdate_no_lock_irq_info_funcs +ffffffff82c762e8 r vblank_irq_info_funcs +ffffffff82c762f8 r vline0_irq_info_funcs +ffffffff82c76308 r outbox_irq_info_funcs +ffffffff82c77000 r dio_link_hwss +ffffffff82c78000 r dpia_link_hwss +ffffffff82c79000 r hpo_dp_link_hwss +ffffffff82c7a000 r virtual_lnk_enc_funcs +ffffffff82c7b000 r virtual_link_hwss +ffffffff82c7c000 r virtual_str_enc_funcs +ffffffff82c7d000 R dmub_srv_dcn20_regs +ffffffff82c7e000 R dmub_srv_dcn21_regs +ffffffff82c7f000 R dmub_srv_dcn30_regs +ffffffff82c80000 R dmub_srv_dcn301_regs +ffffffff82c81000 R dmub_srv_dcn302_regs +ffffffff82c82000 R dmub_srv_dcn303_regs +ffffffff82c83000 R dmub_srv_dcn31_regs +ffffffff82c84000 R dmub_srv_dcn315_regs +ffffffff82c85000 R dmub_srv_dcn316_regs +ffffffff82c86000 R dmub_srv_dcn32_regs +ffffffff82c87000 r numerator01 +ffffffff82c87020 r numerator02 +ffffffff82c87040 r numerator04 +ffffffff82c87060 r numerator05 +ffffffff82c89000 r abm_settings +ffffffff82c89010 r abm_settings_config0 +ffffffff82c89050 r abm_settings_config1 +ffffffff82c89088 r min_reduction_table_v_2_2 +ffffffff82c89095 r max_reduction_table_v_2_2 +ffffffff82c890a2 r min_reduction_table +ffffffff82c890af r max_reduction_table +ffffffff82c8a000 R amdgpu_pp_profile_name +ffffffff82c8b000 r pp_lib_thermal_controller_names +ffffffff82c8c000 r pp_ip_funcs +ffffffff82c8c0a0 R pp_smu_ip_block +ffffffff82c8c0b8 r pp_dpm_funcs ffffffff82c8d000 r gpio_tbl ffffffff82c8d0f0 r enable_fb_req_rej_tbl ffffffff82c8d140 r use_bclk_tbl -ffffffff82c8d2e0 r turn_off_plls_tbl -ffffffff82c8d370 r clk_req_b_tbl -ffffffff82c8d490 r enter_baco_tbl -ffffffff82c8d5b0 r exit_baco_tbl -ffffffff82c8d6d0 r clean_baco_tbl +ffffffff82c8d310 r turn_off_plls_tbl +ffffffff82c8d640 r enter_baco_tbl +ffffffff82c8d730 r exit_baco_tbl +ffffffff82c8d850 r clean_baco_tbl ffffffff82c8e000 r gpio_tbl ffffffff82c8e0f0 r enable_fb_req_rej_tbl -ffffffff82c8e140 r use_bclk_tbl_vg -ffffffff82c8e200 r turn_off_plls_tbl_vg -ffffffff82c8e350 r use_bclk_tbl -ffffffff82c8e440 r turn_off_plls_tbl -ffffffff82c8e5f0 r clk_req_b_tbl -ffffffff82c8e710 r enter_baco_tbl -ffffffff82c8e830 r exit_baco_tbl -ffffffff82c8e950 r clean_baco_tbl -ffffffff82c8f000 r vega10_fuses_default -ffffffff82c9e000 r pp_r600_encode_lanes -ffffffff82c9f000 R pptable_v1_0_funcs -ffffffff82ca0000 R pptable_funcs -ffffffff82ca0020 r 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+ffffffff82cfa030 R ne2000devs +ffffffff82cfc000 R aic_pcmcia_ca +ffffffff82cfd000 R com_pcmcia_ca +ffffffff82cfe000 R wdc_pcmcia_ca +ffffffff82cff000 R sm_pcmcia_ca +ffffffff82d00000 R xe_pcmcia_ca +ffffffff82d01000 R wi_pcmcia_ca +ffffffff82d01030 r wi_pcmcia_products +ffffffff82d02000 R malo_pcmcia_ca +ffffffff82d03000 R an_pcmcia_ca +ffffffff82d04000 R pcib_ca +ffffffff82d05000 R amdpcib_ca +ffffffff82d05028 R amdpcib_devices +ffffffff82d06000 R tcpcib_ca +ffffffff82d06028 R tcpcib_devices +ffffffff82d07000 R aapic_ca +ffffffff82d08000 R hme_pci_ca +ffffffff82d08028 r hme_promhdr +ffffffff82d0802a r hme_promdat +ffffffff82d09000 R isa_ca +ffffffff82d0a000 R isadma_ca +ffffffff82d0b000 R fdc_ca +ffffffff82d0c000 R fd_ca +ffffffff82d0d000 R com_isa_ca +ffffffff82d0e000 R pckbc_isa_ca +ffffffff82d0f000 R vga_isa_ca +ffffffff82d10000 R wdc_isa_ca +ffffffff82d11000 R mpu_midi_hw_if +ffffffff82d12000 R mpu_isa_ca +ffffffff82d13000 R pcppi_ca +ffffffff82d14000 R spkr_ca +ffffffff82d14030 r pitchtab +ffffffff82d15000 R lpt_isa_ca +ffffffff82d16000 R wbsio_ca +ffffffff82d17000 R schsio_ca +ffffffff82d18000 R lm_isa_ca +ffffffff82d18028 R lm_wbsio_ca +ffffffff82d19000 R it_sensors +ffffffff82d19110 R it_vrfact +ffffffff82d19140 R it_fan_regs +ffffffff82d19160 R it_fan_ext_regs +ffffffff82d19178 R it_ca +ffffffff82d1a000 R abitkv_sensors +ffffffff82d1a200 R abitaa_sensors +ffffffff82d1a480 R abitav_sensors +ffffffff82d1a700 R abitas_sensors +ffffffff82d1a980 R abitax_sensors +ffffffff82d1abc0 R abitm4_sensors +ffffffff82d1ae80 R abitan_sensors +ffffffff82d1b120 R abital_sensors +ffffffff82d1b3a0 R abitaw_sensors +ffffffff82d1b700 R abitni_sensors +ffffffff82d1b9a0 R abitat_sensors +ffffffff82d1bcc0 R abitan2_sensors +ffffffff82d1bf60 R abitab_sensors +ffffffff82d1c220 R abitan3_sensors +ffffffff82d1c500 R abitaw2_sensors +ffffffff82d1c860 R abitat2_sensors +ffffffff82d1cb60 R abitab2_sensors +ffffffff82d1cea0 R abitin_sensors +ffffffff82d1d1e0 R uguru_ca +ffffffff82d1e000 R aps_ca +ffffffff82d1f000 R wsdisplay_emul_ca +ffffffff82d1f030 r charClass +ffffffff82d20000 r usl_syncops +ffffffff82d21000 R wsevent_filtops +ffffffff82d22000 R wskbd_ca +ffffffff82d23000 r latin1_to_upper +ffffffff82d24000 R wsmouse_ca +ffffffff82d25000 R cyrillic_to_koi8 +ffffffff82d25060 R unicode_to_latin2 +ffffffff82d250e0 R unicode_to_latin7 +ffffffff82d26000 R wsemul_vt100_ops +ffffffff82d27000 r decspcgr2uni +ffffffff82d27100 r dectech2uni +ffffffff82d27200 r nrctable +ffffffff82d27320 r nrcovlpos +ffffffff82d28000 r vt100_fkeys +ffffffff82d280c0 r vt100_pfkeys +ffffffff82d280e0 r vt100_numpad +ffffffff82d29000 R pckbd_ca +ffffffff82d29028 R pckbd_accessops +ffffffff82d29040 R pckbd_consops +ffffffff82d29060 R pckbd_keymapdata +ffffffff82d29070 R pckbd_xtbl +ffffffff82d29100 R pckbd_xtbl_ext +ffffffff82d2a000 r pckbd_keydesc_us +ffffffff82d2a250 r pckbd_keydesc_de +ffffffff82d2a2f0 r pckbd_keydesc_de_nodead +ffffffff82d2a310 r pckbd_keydesc_fr +ffffffff82d2a3d0 r pckbd_keydesc_fr_dvorak_bepo +ffffffff82d2a510 r pckbd_keydesc_dk +ffffffff82d2a5a0 r pckbd_keydesc_dk_nodead +ffffffff82d2a5b0 r pckbd_keydesc_it +ffffffff82d2a640 r pckbd_keydesc_uk +ffffffff82d2a6e0 r pckbd_keydesc_jp +ffffffff82d2a750 r pckbd_keydesc_sv +ffffffff82d2a780 r pckbd_keydesc_sv_nodead +ffffffff82d2a790 r pckbd_keydesc_no +ffffffff82d2a7c0 r pckbd_keydesc_no_nodead +ffffffff82d2a7d0 r pckbd_keydesc_us_declk +ffffffff82d2a860 r pckbd_keydesc_us_dvorak +ffffffff82d2a900 r pckbd_keydesc_us_colemak +ffffffff82d2a948 r pckbd_keydesc_swapctrlcaps +ffffffff82d2a960 r pckbd_keydesc_iopener +ffffffff82d2a9b0 r pckbd_keydesc_es +ffffffff82d2aa50 r pckbd_keydesc_be +ffffffff82d2ab10 r pckbd_keydesc_ru +ffffffff82d2ac80 r pckbd_keydesc_ua +ffffffff82d2ae10 r pckbd_keydesc_sg +ffffffff82d2aec0 r pckbd_keydesc_sg_nodead +ffffffff82d2aee0 r pckbd_keydesc_sf +ffffffff82d2af00 r pckbd_keydesc_pt +ffffffff82d2af90 r pckbd_keydesc_lt +ffffffff82d2b070 r pckbd_keydesc_la +ffffffff82d2b100 r pckbd_keydesc_br +ffffffff82d2b180 r pckbd_keydesc_tr +ffffffff82d2b230 r pckbd_keydesc_tr_nodead +ffffffff82d2b250 r pckbd_keydesc_pl +ffffffff82d2b2b0 r pckbd_keydesc_hu +ffffffff82d2b3c0 r pckbd_keydesc_si +ffffffff82d2b4d0 r pckbd_keydesc_cf +ffffffff82d2b5a0 r pckbd_keydesc_cf_nodead +ffffffff82d2b5c0 r pckbd_keydesc_lv +ffffffff82d2b640 r pckbd_keydesc_nl +ffffffff82d2b720 r pckbd_keydesc_nl_nodead +ffffffff82d2b740 r pckbd_keydesc_is +ffffffff82d2b7cc r pckbd_keydesc_is_nodead +ffffffff82d2b7e0 r pckbd_keydesc_ee +ffffffff82d2b890 r pckbd_keydesc_ee_nodead +ffffffff82d2b8b0 R pckbd_keydesctab +ffffffff82d2c000 R pms_ca +ffffffff82d2c028 R pms_accessops +ffffffff82d2c040 R pms_sec_accessops +ffffffff82d2c060 R pms_protocols +ffffffff82d2c1e0 r alps_models +ffffffff82d2d000 R skgpio_led_offset +ffffffff82d2d008 R skgpio_ca +ffffffff82d2e000 R hidkbd_trtab +ffffffff82d2e100 r apple_fn_trans +ffffffff82d2e120 r apple_tb_trans +ffffffff82d2e140 r apple_mba_trans +ffffffff82d2f000 r hidcc_attach_wskbd.accessops +ffffffff82d2f020 r hidcc_keysyms +ffffffff82d30000 R usb_ca +ffffffff82d31000 R usb_known_products +ffffffff82d3cf70 R usb_known_vendors +ffffffff82d3f780 R usbd_error_strs +ffffffff82d40000 R usb_quirks +ffffffff82d40390 R usb_dev_quirks +ffffffff82d40398 R usbd_no_quirk +ffffffff82d41000 R uhub_ca +ffffffff82d41028 R uhub_uhub_ca +ffffffff82d42000 R uaudio_ca +ffffffff82d42028 R uaudio_hw_if +ffffffff82d420e0 R uaudio_rates +ffffffff82d42120 r uaudio_clkname.names +ffffffff82d42140 r uaudio_feature_addent.features +ffffffff82d43000 R uvideo_ca +ffffffff82d43028 R uvideo_hw_if +ffffffff82d43100 R uvideo_devs +ffffffff82d44000 r utvfu_select_norm.pal +ffffffff82d44040 r utvfu_select_norm.ntsc +ffffffff82d44080 r utvfu_setup_capture.setup +ffffffff82d44180 r utvfu_audio_start_chip.setup +ffffffff82d441c8 r utvfu_audio_stop_chip.setup +ffffffff82d441d8 R utvfu_ca +ffffffff82d44200 R utvfu_vid_hw_if +ffffffff82d442d0 R utvfu_au_hw_if +ffffffff82d45000 R udl_ca +ffffffff82d45030 r udl_devs +ffffffff82d450b0 r udl_modes +ffffffff82d46000 R umidi_hw_if +ffffffff82d46030 R umidi_ca +ffffffff82d46060 r umidi_evlen +ffffffff82d46080 r packet_length +ffffffff82d47000 r quirk_name +ffffffff82d48000 R ucom_ca +ffffffff82d49000 R ugen_ca +ffffffff82d49028 R ugenread_intr_filtops +ffffffff82d49058 R ugenread_isoc_filtops +ffffffff82d4a000 R uhidev_ca +ffffffff82d4a030 r uhid_graphire_report_descr +ffffffff82d4a0b0 r uhid_graphire3_4x5_report_descr +ffffffff82d4a160 r uhid_xb360gp_report_descr +ffffffff82d4a210 r uhid_xbonegp_report_descr +ffffffff82d4b000 R uhid_ca +ffffffff82d4b028 R uhidread_filtops +ffffffff82d4c000 R fido_ca +ffffffff82d4d000 R ujoy_ca +ffffffff82d4e000 r ukbd_keydesc_us +ffffffff82d4e290 r ukbd_keydesc_de +ffffffff82d4e340 r ukbd_keydesc_de_nodead +ffffffff82d4e360 r ukbd_keydesc_fr +ffffffff82d4e420 r ukbd_keydesc_fr_apple +ffffffff82d4e560 r ukbd_keydesc_fr_dvorak_bepo +ffffffff82d4e6a0 r ukbd_keydesc_dk +ffffffff82d4e740 r ukbd_keydesc_dk_nodead +ffffffff82d4e750 r ukbd_keydesc_it +ffffffff82d4e7f0 r ukbd_keydesc_uk +ffffffff82d4e8a0 r ukbd_keydesc_jp +ffffffff82d4e910 r ukbd_keydesc_sv +ffffffff82d4e940 r ukbd_keydesc_sv_nodead +ffffffff82d4e950 r ukbd_keydesc_no +ffffffff82d4e980 r ukbd_keydesc_no_nodead +ffffffff82d4e990 r ukbd_keydesc_us_dvorak +ffffffff82d4ea30 r ukbd_keydesc_us_colemak +ffffffff82d4ea78 r ukbd_keydesc_swapctrlcaps +ffffffff82d4ea90 r ukbd_keydesc_iopener +ffffffff82d4eae0 r ukbd_keydesc_es +ffffffff82d4eb80 r ukbd_keydesc_be +ffffffff82d4ec40 r ukbd_keydesc_ru +ffffffff82d4edb0 r ukbd_keydesc_ua +ffffffff82d4ef50 r ukbd_keydesc_sg +ffffffff82d4f010 r ukbd_keydesc_sg_nodead +ffffffff82d4f030 r ukbd_keydesc_sf +ffffffff82d4f050 r ukbd_keydesc_pt +ffffffff82d4f0e0 r ukbd_keydesc_pt_apple +ffffffff82d4f100 r ukbd_keydesc_lt +ffffffff82d4f1e0 r ukbd_keydesc_la +ffffffff82d4f280 r ukbd_keydesc_br +ffffffff82d4f310 r ukbd_keydesc_tr +ffffffff82d4f3d0 r ukbd_keydesc_tr_nodead +ffffffff82d4f3f0 r ukbd_keydesc_pl +ffffffff82d4f450 r ukbd_keydesc_hu +ffffffff82d4f560 r ukbd_keydesc_si +ffffffff82d4f680 r ukbd_keydesc_cf +ffffffff82d4f760 r ukbd_keydesc_cf_nodead +ffffffff82d4f780 r ukbd_keydesc_lv +ffffffff82d4f800 r ukbd_keydesc_nl +ffffffff82d4f8e0 r ukbd_keydesc_nl_nodead +ffffffff82d4f900 r ukbd_keydesc_is +ffffffff82d4f994 r ukbd_keydesc_is_nodead +ffffffff82d4f9a0 r ukbd_keydesc_ee +ffffffff82d4fa50 r ukbd_keydesc_ee_nodead +ffffffff82d4fa70 R ukbd_keydesctab +ffffffff82d50000 R ukbd_countrylayout +ffffffff82d50090 R ukbd_consops +ffffffff82d500b0 R ukbd_accessops +ffffffff82d500c8 R ukbd_ca +ffffffff82d51000 R ums_accessops +ffffffff82d51018 R ums_ca +ffffffff82d52000 R umt_accessops +ffffffff82d52018 R umt_ca +ffffffff82d53000 R uts_devs +ffffffff82d53010 R uts_accessops +ffffffff82d53028 R uts_ca +ffffffff82d54000 R ubcmtp_accessops +ffffffff82d54018 R ubcmtp_ca +ffffffff82d54040 r ubcmtp_devices +ffffffff82d55000 R ucycom_methods +ffffffff82d55040 R ucycom_devs +ffffffff82d55050 R ucycom_ca +ffffffff82d56000 R uslhcom_methods +ffffffff82d56040 R uslhcom_ca +ffffffff82d56068 r uslhcom_devs +ffffffff82d57000 R ulpt_ca +ffffffff82d58000 R umass_ca +ffffffff82d58028 R umass_bbb_methods +ffffffff82d58040 R umass_cbi_methods +ffffffff82d59000 R umass_quirks +ffffffff82d5a000 R umass_scsi_switch +ffffffff82d5b000 R uthum_devs +ffffffff82d5b008 R uthum_ca +ffffffff82d5b030 r uthum_sensor_type_s +ffffffff82d5c000 R ugold_devs +ffffffff82d5c010 R ugold_ca +ffffffff82d5d000 R utrh_devs +ffffffff82d5d008 R utrh_ca +ffffffff82d5e000 R uoakrh_devs +ffffffff82d5e008 R uoakrh_ca +ffffffff82d5e030 R uoakrh_methods +ffffffff82d5f000 R uoaklux_devs +ffffffff82d5f008 R uoaklux_ca +ffffffff82d5f030 R uoaklux_methods +ffffffff82d60000 R uoakv_devs +ffffffff82d60008 R uoakv_ca +ffffffff82d60030 R uoakv_methods +ffffffff82d61000 R uonerng_ca +ffffffff82d62000 R urng_ca +ffffffff82d62030 r urng_devs +ffffffff82d63000 R udcf_ca +ffffffff82d63028 r udcf_devs +ffffffff82d64000 R umbg_ca +ffffffff82d65000 R uvisor_methods +ffffffff82d65040 R uvisor_ca +ffffffff82d65070 r uvisor_devs +ffffffff82d66000 R udsbr_hw_if +ffffffff82d66028 R udsbr_ca +ffffffff82d67000 R utwitch_devs +ffffffff82d67008 R utwitch_ca +ffffffff82d68000 R aue_devs +ffffffff82d681b0 R aue_ca +ffffffff82d69000 R axe_devs +ffffffff82d690d0 R axe_ca +ffffffff82d6a000 R axen_devs +ffffffff82d6a020 R axen_ca +ffffffff82d6b000 R smsc_ca +ffffffff82d6b030 r smsc_devs +ffffffff82d6c000 R cue_ca +ffffffff82d6d000 R kue_devs +ffffffff82d6d088 R kue_ca +ffffffff82d6e000 R cdce_devs +ffffffff82d6e0a0 R cdce_ca +ffffffff82d6f000 R urndis_ca +ffffffff82d6f030 R urndis_class +ffffffff82d70000 R mos_devs +ffffffff82d70018 R mos_ca +ffffffff82d71000 R mue_devs +ffffffff82d71020 R mue_ca +ffffffff82d72000 R udav_ca +ffffffff82d72030 r udav_devs +ffffffff82d73000 R upl_ca +ffffffff82d74000 R ugl_ca +ffffffff82d75000 R url_ca +ffffffff82d75030 r url_devs +ffffffff82d76000 R ure_devs +ffffffff82d760f0 R ure_ca +ffffffff82d77000 R uaq_devs +ffffffff82d77018 R uaq_ca +ffffffff82d78000 R umodem_methods +ffffffff82d78040 R umodem_ca +ffffffff82d79000 R uftdi_methods +ffffffff82d79040 R uftdi_ca +ffffffff82d79070 r uftdi_devs +ffffffff82d7a000 R uplcom_methods +ffffffff82d7a040 R uplcom_ca +ffffffff82d7a070 r uplcom_devs +ffffffff82d7b000 R umct_methods +ffffffff82d7b040 R umct_ca +ffffffff82d7b070 r umct_devs +ffffffff82d7c000 R uvscom_methods +ffffffff82d7c040 R uvscom_ca +ffffffff82d7c070 r uvscom_devs +ffffffff82d7d000 R ubsa_methods +ffffffff82d7d040 R ubsa_devs +ffffffff82d7d060 R ubsa_ca +ffffffff82d7e000 R ukspan_ca +ffffffff82d7e028 r ukspan_devs +ffffffff82d7e030 r ukspan_methods +ffffffff82d7f000 R uslcom_methods +ffffffff82d7f040 R uslcom_ca +ffffffff82d7f070 r uslcom_devs +ffffffff82d80000 R uark_methods +ffffffff82d80040 R uark_ca +ffffffff82d80068 r uark_devs +ffffffff82d81000 R moscom_methods +ffffffff82d81040 R moscom_ca +ffffffff82d81068 r moscom_devs +ffffffff82d82000 R umcs_methods +ffffffff82d82040 R umcs_devs +ffffffff82d82050 R umcs_ca +ffffffff82d83000 R uscom_methods +ffffffff82d83040 R uscom_ca +ffffffff82d83068 r uscom_devs +ffffffff82d84000 R ucrcom_methods +ffffffff82d84040 R ucrcom_ca +ffffffff82d85000 R uxrcom_methods +ffffffff82d85040 R uxrcom_ca +ffffffff82d85068 r uxrcom_devs +ffffffff82d86000 R uipaq_methods +ffffffff82d86040 R uipaq_ca +ffffffff82d86070 r uipaq_devs +ffffffff82d87000 R umsm_methods +ffffffff82d87040 R umsm_ca +ffffffff82d87070 r umsm_devs +ffffffff82d88000 R uchcom_methods +ffffffff82d88040 R uchcom_ca +ffffffff82d88068 r uchcom_devs +ffffffff82d88080 r dividers +ffffffff82d89000 R uticom_methods +ffffffff82d89040 R uticom_ca +ffffffff82d89070 r uticom_devs +ffffffff82d8a000 R wi_usb_devs +ffffffff82d8a0f0 R wi_usb_ca +ffffffff82d8b000 R atu_ca +ffffffff82d8c000 R ural_ca +ffffffff82d8c030 r ural_devs +ffffffff82d8c0a0 r ural_rf2522_r2 +ffffffff82d8c0e0 r ural_rf2524_r2 +ffffffff82d8c120 r ural_rf2525_hi_r2 +ffffffff82d8c160 r ural_rf2525_r2 +ffffffff82d8c1a0 r ural_rf2525e_r2 +ffffffff82d8c1e0 r ural_rf2526_hi_r2 +ffffffff82d8c220 r ural_rf2526_r2 +ffffffff82d8c260 r ural_def_bbp +ffffffff82d8c2a0 r ural_def_mac +ffffffff82d8d000 R rum_ca +ffffffff82d8d030 r rum_devs +ffffffff82d8d110 r rum_rf5225 +ffffffff82d8d460 r rum_rf5226 +ffffffff82d8d7b0 r rum_def_bbp +ffffffff82d8d7f0 r rum_def_mac +ffffffff82d8e000 R run_ca +ffffffff82d8e030 r run_devs +ffffffff82d8e430 r rt2860_rf2850 +ffffffff82d8e860 r rt2860_rates +ffffffff82d8e920 r rt5592_freqs_40mhz +ffffffff82d8ea60 r rt5592_freqs_20mhz +ffffffff82d8eba0 r rt5592_2ghz_def_rf +ffffffff82d8ebe0 r rt5592_chan_5ghz +ffffffff82d8ee30 r rt5592_def_bbp +ffffffff82d8ee70 r rt5592_bbp_r196 +ffffffff82d8eed0 r rt5390_def_bbp +ffffffff82d8ef00 r rt3572_def_rf +ffffffff82d8ef40 r rt3070_def_rf +ffffffff82d8ef70 r rt3593_def_rf +ffffffff82d8efb0 r rt5592_def_rf +ffffffff82d8efe0 r rt5392_def_rf +ffffffff82d8f060 r rt5390_def_rf +ffffffff82d8f0e0 r rt2870_def_mac +ffffffff82d90000 R mtw_ca +ffffffff82d90030 r mtw_devs +ffffffff82d90070 r rt2860_rates +ffffffff82d90130 r mt7601_rf_chan +ffffffff82d901a0 r mt7601_def_bbp +ffffffff82d902d0 r mt7601_rf_bank0 +ffffffff82d90330 r mt7601_rf_bank4 +ffffffff82d903b0 r mt7601_rf_bank5 +ffffffff82d90430 r mt7601_def_mac +ffffffff82d91000 R zyd_ca +ffffffff82d91030 r zyd_devs +ffffffff82d911b0 r zyd_rfmd_init.phyini +ffffffff82d912e0 r zyd_rfmd_init.rfini +ffffffff82d91330 r zyd_rfmd_set_channel.rfprog +ffffffff82d913a0 r zyd_al2230_init.phyini +ffffffff82d91480 r zyd_al2230_init.rfini +ffffffff82d914e0 r zyd_al2230_init_b.phyini +ffffffff82d915d0 r zyd_al2230_init_b.rfini +ffffffff82d91620 r zyd_al2230_set_channel.rfprog +ffffffff82d916d0 r zyd_al7230B_init.phyini_1 +ffffffff82d917b0 r zyd_al7230B_init.rfini_1 +ffffffff82d917f0 r zyd_al7230B_set_channel.rfprog +ffffffff82d91860 r zyd_al7230B_set_channel.rfsc +ffffffff82d91890 r zyd_al2210_init.phyini +ffffffff82d918f0 r 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get_surf_rq_param.__warned.64 +ffffffff836fc084 b get_surf_rq_param.__warned.66 +ffffffff836fc088 b dml1_rq_dlg_get_row_heights.__warned +ffffffff836fc08c b dml1_rq_dlg_get_row_heights.__warned.67 +ffffffff836fc090 b get_swath_need.__warned +ffffffff836fd000 b dc_dsc_parse_dsc_dpcd.__warned +ffffffff836fd001 b dsc_policy_disable_dsc_stream_overhead +ffffffff836fd002 b dsc_policy_enable_dsc_when_not_needed +ffffffff836fd004 b dc_fixpt_sub.__warned +ffffffff836fd008 b dc_fixpt_add.__warned +ffffffff836fd00c b dc_fixpt_ceil.__warned +ffffffff836fe000 b dal_hw_gpio_destruct.__warned +ffffffff836ff000 b update_dio_stream_allocation_table.__warned +ffffffff83700000 b update_dpia_stream_allocation_table.status +ffffffff83700004 b update_dpia_stream_allocation_table.__warned +ffffffff83700008 b update_dpia_stream_allocation_table.__warned.4 +ffffffff83701000 b dmub_srv_hw_init.__warned +ffffffff83702000 b coordinates_x +ffffffff83707050 b dc_fixpt_add.__warned +ffffffff83707054 b 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+ffffffff8372e000 b acpiec_wait.acpiecnowait +ffffffff8372f000 B acpitz_cpu_setperf +ffffffff83730000 B acpimadt_busses +ffffffff83733000 B acpimadt_isa_bus +ffffffff83733030 b lapic_map +ffffffff83734000 B acpidmar_ddb +ffffffff83734010 b dmar_bdf.bdf +ffffffff83734030 B acpidmar_sc +ffffffff83734038 B domain_map_page +ffffffff83734040 b dom_bdf.mmm +ffffffff83734070 b iommu_init.niommu +ffffffff83734078 b acpidmar_pci_attach.dom +ffffffff83734080 b sid_flag +ffffffff83774080 b ivhd_showpage.show +ffffffff83774084 b ivhd_iommu_init.niommu +ffffffff83774088 b acpidmar_intr.ofe.0 +ffffffff83774090 b acpidmar_intr.ofe.1 +ffffffff83775000 b dwiic_i2c_intr_string.irqstr +ffffffff83776000 B acpihve_attached +ffffffff83777000 B efi_jmpbuf +ffffffff83778000 B vm_pool +ffffffff837781a8 B vcpu_pool +ffffffff83778350 B vmm_softc +ffffffff83779000 B l1tf_flush_region +ffffffff8377a000 B sdmmc_verbose +ffffffff8377b000 B utc_offset +ffffffff8377b008 B bufpages +ffffffff8377b010 B utsname +ffffffff8377c000 B mountroot +ffffffff8377d000 B __kernel_bss_end ffffffff83800000 B _end ffffffff83800000 B end