--- 7.3/2023-05-26T14:39:52Z/2023-03-25T00:00:00Z/nm-bsd-ot31.txt Fri May 26 18:04:24 2023 +++ 7.3/2023-05-26T14:39:52Z/2023-04-01T00:00:00Z/nm-bsd-ot31.txt Fri May 26 18:58:38 2023 @@ -2,14 +2,14 @@ 00011006 A mp_pdirpa 0001419d A acpi_pdirpa 01000000 A __kernel_phys_base -02518000 T __kernel_kutext_phys -0251c000 C __kernel_cptext_phys -0251d000 C __kernel_rodata_phys -02dce000 R __kernel_kutext_page_phys -02dd0000 C __kernel_randomdata_phys -03093000 R __kernel_data_phys -033c3000 D __kernel_kudata_phys -033c4000 C __kernel_bss_phys +02524000 T __kernel_kutext_phys +02528000 C __kernel_cptext_phys +02529000 C __kernel_rodata_phys +02ddc000 R __kernel_kutext_page_phys +02dde000 C __kernel_randomdata_phys +030a0000 R __kernel_data_phys +033d1000 D __kernel_kudata_phys +033d2000 C __kernel_bss_phys 03800000 B __kernel_phys_end 80000000 A __kernel_virt_to_phys ffffffff80000000 A __kernel_base @@ -11391,8 +11391,8 @@ ffffffff815ac410 T via_update_sensor ffffffff815ac460 T cpu_freq_ctr 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drm_dp_downstream_444_to_420_conversion -ffffffff81975720 T drm_dp_downstream_rgb_to_ycbcr_conversion -ffffffff81975780 T drm_dp_downstream_mode -ffffffff81975800 T drm_dp_downstream_id -ffffffff81975820 T drm_dp_downstream_debug -ffffffff819758c0 T drm_dp_subconnector_type -ffffffff81975920 T drm_dp_set_subconnector_property -ffffffff81975990 T drm_dp_read_sink_count_cap -ffffffff819759e0 T drm_dp_read_sink_count -ffffffff81975a40 T drm_dp_remote_aux_init -ffffffff81975a70 t drm_dp_aux_crc_work -ffffffff81975be0 T drm_dp_aux_init -ffffffff81975c90 T drm_dp_aux_register -ffffffff81975db0 T drm_dp_aux_unregister -ffffffff81975de0 T drm_dp_psr_setup_time -ffffffff81975e20 T drm_dp_start_crc -ffffffff81975ec0 T drm_dp_stop_crc -ffffffff81975f50 T drm_dp_read_desc -ffffffff81976110 T drm_dp_dsc_sink_max_slice_count -ffffffff819761a0 T drm_dp_dsc_sink_line_buf_depth -ffffffff819761e0 T drm_dp_dsc_sink_supported_input_bpcs -ffffffff81976240 T drm_dp_read_lttpr_common_caps -ffffffff81976300 T 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dce_v11_0_wait_for_idle -ffffffff81d9fee0 t dce_v11_0_soft_reset -ffffffff81da0100 t dce_v11_0_set_clockgating_state -ffffffff81da0130 t dce_v11_0_set_powergating_state -ffffffff81da0160 t dce_v11_0_audio_endpt_rreg -ffffffff81da01f0 t dce_v11_0_audio_endpt_wreg -ffffffff81da0260 t dce_v11_0_bandwidth_update -ffffffff81da0cc0 t dce_v11_0_vblank_get_counter -ffffffff81da0d10 t dce_v11_0_hpd_sense -ffffffff81da0d70 t dce_v11_0_hpd_set_polarity -ffffffff81da0e40 t dce_v11_0_hpd_get_gpio_reg -ffffffff81da0e70 t dce_v11_0_page_flip -ffffffff81da0f60 t dce_v11_0_crtc_get_scanoutpos -ffffffff81da1000 t dce_v11_0_encoder_add -ffffffff81da1230 t dce_v11_0_latency_watermark -ffffffff81da1450 t dce_v11_0_encoder_destroy -ffffffff81da14a0 t dce_v11_0_encoder_prepare -ffffffff81da16a0 t dce_v11_0_encoder_commit -ffffffff81da16d0 t dce_v11_0_encoder_mode_set -ffffffff81da2570 t dce_v11_0_encoder_disable -ffffffff81da2680 t dce_v11_0_ext_dpms -ffffffff81da26b0 t dce_v11_0_ext_prepare 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gfx10_kiq_set_resources -ffffffff81daf7f0 t gfx10_kiq_map_queues -ffffffff81dafb80 t gfx10_kiq_unmap_queues -ffffffff81daff80 t gfx10_kiq_query_status -ffffffff81db0280 t gfx10_kiq_invalidate_tlbs -ffffffff81db03a0 t gfx_v10_0_ring_get_rptr_compute -ffffffff81db03d0 t gfx_v10_0_ring_get_wptr_compute -ffffffff81db0430 t gfx_v10_0_ring_set_wptr_compute -ffffffff81db0570 t gfx_v10_0_ring_emit_ib_compute -ffffffff81db08c0 t gfx_v10_0_ring_emit_fence_kiq -ffffffff81db0cf0 t gfx_v10_0_ring_test_ring -ffffffff81db0f60 t gfx_v10_0_ring_test_ib -ffffffff81db1200 t gfx_v10_0_ring_emit_rreg -ffffffff81db1490 t gfx_v10_0_ring_emit_wreg -ffffffff81db16c0 t gfx_v10_0_ring_emit_reg_wait -ffffffff81db1710 t gfx_v10_0_ring_emit_reg_write_reg_wait -ffffffff81db17a0 t gfx_v10_0_wait_reg_mem -ffffffff81db1ad0 t gfx_v10_0_ring_get_rptr_gfx -ffffffff81db1b00 t gfx_v10_0_ring_get_wptr_gfx -ffffffff81db1c10 t gfx_v10_0_ring_set_wptr_gfx -ffffffff81db1e20 t gfx_v10_0_ring_emit_ib_gfx -ffffffff81db24d0 t gfx_v10_0_ring_emit_fence -ffffffff81db28a0 t gfx_v10_0_ring_emit_pipeline_sync -ffffffff81db2900 t gfx_v10_0_ring_emit_vm_flush -ffffffff81db2ad0 t gfx_v10_0_ring_emit_hdp_flush -ffffffff81db2ba0 t gfx_v10_0_ring_emit_gds_switch -ffffffff81db2c80 t gfx_v10_0_ring_emit_init_cond_exec -ffffffff81db2eb0 t gfx_v10_0_ring_emit_patch_cond_exec -ffffffff81db2f70 t gfx_v10_0_ring_emit_sb -ffffffff81db3050 t gfx_v10_0_ring_emit_cntxcntl -ffffffff81db3530 t gfx_v10_0_ring_emit_frame_cntl -ffffffff81db3640 t gfx_v10_0_ring_soft_recovery -ffffffff81db36b0 t gfx_v10_0_ring_preempt_ib -ffffffff81db3820 t gfx_v10_0_emit_mem_sync -ffffffff81db3b60 t gfx_v10_0_write_data_to_reg -ffffffff81db3d70 t gfx_v10_0_set_eop_interrupt_state -ffffffff81db3e50 t gfx_v10_0_eop_irq -ffffffff81db4020 t gfx_v10_0_set_gfx_eop_interrupt_state -ffffffff81db41b0 t gfx_v10_0_set_compute_eop_interrupt_state -ffffffff81db4360 t gfx_v10_0_kiq_set_interrupt_state -ffffffff81db4630 t gfx_v10_0_kiq_irq -ffffffff81db46b0 t gfx_v10_0_set_priv_reg_fault_state -ffffffff81db47d0 t gfx_v10_0_priv_reg_irq -ffffffff81db4830 t gfx_v10_0_handle_priv_fault -ffffffff81db49c0 t gfx_v10_0_set_priv_inst_fault_state -ffffffff81db4ae0 t gfx_v10_0_priv_inst_irq -ffffffff81db4b40 t gfx_v10_0_is_rlc_enabled -ffffffff81db4bc0 t gfx_v10_0_set_safe_mode -ffffffff81db4e50 t gfx_v10_0_unset_safe_mode -ffffffff81db4f00 t gfx_v10_0_rlc_init -ffffffff81db4f70 t gfx_v10_0_get_csb_size -ffffffff81db4fc0 t gfx_v10_0_get_csb_buffer -ffffffff81db5140 t gfx_v10_0_rlc_resume -ffffffff81db5c40 t gfx_v10_0_rlc_stop -ffffffff81db5d10 t gfx_v10_0_rlc_reset -ffffffff81db5ea0 t gfx_v10_0_rlc_start -ffffffff81db6040 t gfx_v10_0_update_spm_vmid -ffffffff81db6170 t gfx_v10_0_wait_for_rlc_autoload_complete -ffffffff81db6d00 t gfx_v10_0_init_csb -ffffffff81db6fd0 t gfx_v10_0_is_rlcg_access_range -ffffffff81db7000 t gfx_v10_0_gfx_mqd_init -ffffffff81db73e0 t gfx_v10_0_compute_mqd_init -ffffffff81db7880 t amdgpu_bo_unreserve -ffffffff81db7960 t gfx_v10_0_get_gpu_clock_counter -ffffffff81db7e50 t gfx_v10_0_select_se_sh -ffffffff81db7ee0 t gfx_v10_0_read_wave_data -ffffffff81db8140 t gfx_v10_0_read_wave_vgprs -ffffffff81db8170 t gfx_v10_0_read_wave_sgprs -ffffffff81db81f0 t gfx_v10_0_select_me_pipe_q -ffffffff81db8210 t gfx_v10_0_init_spm_golden_registers -ffffffff81db8280 t gfx_v10_0_update_perfmon_mgcg -ffffffff81db83a0 t wave_read_ind -ffffffff81db8480 t wave_read_regs -ffffffff81db85e0 t gfx_v10_0_cp_resume -ffffffff81dbb220 t gfx_v10_3_get_disabled_sa -ffffffff81dbb330 t gfx_v10_0_get_rb_active_bitmap -ffffffff81dbb450 t gfx_v10_0_get_wgp_active_bitmap_per_sh -ffffffff81dbb560 t gfx_v10_0_enable_gui_idle_interrupt -ffffffff81dbb670 t gfx_v10_0_cp_gfx_enable -ffffffff81dbb8b0 t gfx_v10_0_cp_compute_enable -ffffffff81dbba40 t amdgpu_bo_reserve -ffffffff81dbbbc0 t gfx_v10_0_kiq_init_register -ffffffff81dbca30 t gfx_v10_0_cp_gfx_switch_pipe -ffffffff81dbcb30 t gfx_v10_0_cp_gfx_set_doorbell -ffffffff81dbce00 t gfx_v10_0_cp_gfx_start -ffffffff81dbd7e0 t gfx_v10_0_update_fine_grain_clock_gating -ffffffff81dbdb00 t gfx_v10_0_update_medium_grain_clock_gating -ffffffff81dbe220 t gfx_v10_0_update_3d_clock_gating -ffffffff81dbe5e0 t gfx_v10_0_update_coarse_grain_clock_gating -ffffffff81dbf000 t gfx_v11_0_early_init -ffffffff81dbf390 t gfx_v11_0_late_init -ffffffff81dbf400 t gfx_v11_0_sw_init -ffffffff81dc0300 t gfx_v11_0_sw_fini -ffffffff81dc05d0 t gfx_v11_0_hw_init -ffffffff81dc4a40 t gfx_v11_0_hw_fini -ffffffff81dc4cb0 t gfx_v11_0_suspend -ffffffff81dc4cf0 t gfx_v11_0_resume -ffffffff81dc4d00 t gfx_v11_0_is_idle -ffffffff81dc4d80 t gfx_v11_0_wait_for_idle -ffffffff81dc4e60 t gfx_v11_0_check_soft_reset -ffffffff81dc4f90 t gfx_v11_0_soft_reset -ffffffff81dc5c70 t gfx_v11_0_set_clockgating_state -ffffffff81dc6850 t gfx_v11_0_set_powergating_state -ffffffff81dc6a40 t gfx_v11_0_get_clockgating_state -ffffffff81dc6c10 t gfx11_kiq_set_resources -ffffffff81dc6f40 t gfx11_kiq_map_queues -ffffffff81dc72d0 t gfx11_kiq_unmap_queues -ffffffff81dc76d0 t gfx11_kiq_query_status -ffffffff81dc79d0 t gfx11_kiq_invalidate_tlbs -ffffffff81dc7af0 t gfx_v11_0_ring_get_rptr_compute -ffffffff81dc7b20 t gfx_v11_0_ring_get_wptr_compute -ffffffff81dc7b80 t gfx_v11_0_ring_set_wptr_compute -ffffffff81dc7cc0 t gfx_v11_0_ring_emit_ib_compute -ffffffff81dc8010 t gfx_v11_0_ring_emit_fence_kiq -ffffffff81dc8440 t gfx_v11_0_ring_test_ring -ffffffff81dc86d0 t gfx_v11_0_ring_test_ib -ffffffff81dc8990 t gfx_v11_0_ring_emit_rreg -ffffffff81dc8c20 t gfx_v11_0_ring_emit_wreg -ffffffff81dc8e50 t gfx_v11_0_ring_emit_reg_wait -ffffffff81dc8ea0 t gfx_v11_0_ring_emit_reg_write_reg_wait -ffffffff81dc8f00 t gfx_v11_0_wait_reg_mem -ffffffff81dc9230 t gfx_v11_0_ring_get_rptr_gfx -ffffffff81dc9260 t gfx_v11_0_ring_get_wptr_gfx -ffffffff81dc9370 t gfx_v11_0_ring_set_wptr_gfx -ffffffff81dc9580 t gfx_v11_0_ring_emit_ib_gfx -ffffffff81dc9c20 t gfx_v11_0_ring_emit_fence -ffffffff81dc9ff0 t gfx_v11_0_ring_emit_pipeline_sync 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drm_atomic_helper_async_check +ffffffff8190ad40 T drm_atomic_helper_update_legacy_modeset_state +ffffffff8190afb0 T drm_atomic_helper_calc_timestamping_constants +ffffffff8190b050 T drm_atomic_helper_commit_modeset_disables +ffffffff8190b650 T drm_atomic_helper_commit_modeset_enables +ffffffff8190b940 T drm_atomic_helper_wait_for_fences +ffffffff8190ba30 T drm_atomic_helper_wait_for_vblanks +ffffffff8190bd40 T drm_atomic_helper_wait_for_flip_done +ffffffff8190bf00 T drm_atomic_helper_commit_tail +ffffffff8190c080 T drm_atomic_helper_commit_planes +ffffffff8190c340 T drm_atomic_helper_fake_vblank +ffffffff8190c420 T drm_atomic_helper_commit_hw_done +ffffffff8190c5d0 T drm_atomic_helper_cleanup_planes +ffffffff8190c680 T drm_atomic_helper_commit_tail_rpm +ffffffff8190c810 T drm_atomic_helper_async_commit +ffffffff8190ca90 T drm_atomic_helper_commit +ffffffff8190cd50 T drm_atomic_helper_prepare_planes +ffffffff8190cef0 T drm_atomic_helper_setup_commit +ffffffff8190d780 t commit_work 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drm_atomic_helper_bridge_propagate_bus_fmt +ffffffff8190f730 t set_best_encoder +ffffffff81910000 T __drm_atomic_helper_crtc_state_reset +ffffffff81910030 T __drm_atomic_helper_crtc_reset +ffffffff81910090 T drm_atomic_helper_crtc_reset +ffffffff81910120 T __drm_atomic_helper_crtc_duplicate_state +ffffffff819101f0 T drm_atomic_helper_crtc_duplicate_state +ffffffff81910290 T __drm_atomic_helper_crtc_destroy_state +ffffffff81910350 T drm_atomic_helper_crtc_destroy_state +ffffffff81910380 T __drm_atomic_helper_plane_state_reset +ffffffff81910440 T __drm_atomic_helper_plane_reset +ffffffff81910490 T drm_atomic_helper_plane_reset +ffffffff81910570 T __drm_atomic_helper_plane_destroy_state +ffffffff819105d0 T __drm_atomic_helper_plane_duplicate_state +ffffffff81910640 T drm_atomic_helper_plane_duplicate_state +ffffffff81910710 T drm_atomic_helper_plane_destroy_state +ffffffff81910780 T __drm_atomic_helper_connector_state_reset +ffffffff819107b0 T __drm_atomic_helper_connector_reset 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drm_atomic_get_property +ffffffff81911f70 T drm_atomic_connector_commit_dpms +ffffffff819120d0 T drm_atomic_set_property +ffffffff81912b80 T drm_mode_atomic_ioctl +ffffffff81914000 T drm_is_current_master +ffffffff81914050 T drm_getmagic +ffffffff81914120 T drm_authmagic +ffffffff819141e0 T drm_master_create +ffffffff81914280 T drm_setmaster_ioctl +ffffffff81914340 t drm_new_set_master +ffffffff819144d0 T drm_dropmaster_ioctl +ffffffff81914620 T drm_master_open +ffffffff819146d0 T drm_master_get +ffffffff81914700 T drm_master_release +ffffffff81914850 T drm_master_put +ffffffff819148e0 T drm_file_get_master +ffffffff81914940 T drm_master_internal_acquire +ffffffff819149a0 T drm_master_internal_release +ffffffff81915000 T drm_plane_create_alpha_property +ffffffff819150a0 T drm_plane_create_rotation_property +ffffffff819151d0 T drm_rotation_simplify +ffffffff81915250 T drm_plane_create_zpos_property +ffffffff81915300 T drm_plane_create_zpos_immutable_property +ffffffff819153b0 T drm_atomic_normalize_zpos +ffffffff819156b0 T drm_plane_create_blend_mode_property +ffffffff81915850 t drm_atomic_state_zpos_cmp +ffffffff81916000 T drm_bridge_add +ffffffff81916070 T devm_drm_bridge_add +ffffffff81916110 T drm_bridge_remove +ffffffff81916170 T drm_bridge_attach +ffffffff819162f0 T drm_bridge_detach +ffffffff819163d0 T drm_bridge_chain_mode_fixup +ffffffff81916460 T drm_bridge_chain_mode_valid +ffffffff819164f0 T drm_bridge_chain_disable +ffffffff81916580 T drm_bridge_chain_post_disable +ffffffff81916600 T drm_bridge_chain_mode_set +ffffffff81916690 T drm_bridge_chain_pre_enable +ffffffff81916720 T drm_bridge_chain_enable +ffffffff819167a0 T drm_atomic_bridge_chain_disable +ffffffff819168a0 T drm_atomic_bridge_chain_post_disable +ffffffff819169b0 T drm_atomic_bridge_chain_pre_enable +ffffffff81916ab0 T drm_atomic_bridge_chain_enable +ffffffff81916bc0 T drm_atomic_bridge_chain_check +ffffffff81916f10 T drm_bridge_detect +ffffffff81916f60 T drm_bridge_get_modes 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drm_memcpy_from_wc +ffffffff8191a710 T drm_memcpy_init_early +ffffffff8191b000 T drm_client_init +ffffffff8191b110 T drm_client_register +ffffffff8191b180 T drm_client_release +ffffffff8191b210 T drm_client_dev_unregister +ffffffff8191b300 T drm_client_dev_hotplug +ffffffff8191b3e0 T drm_client_dev_restore +ffffffff8191b4c0 T drm_client_buffer_vmap +ffffffff8191b530 T drm_client_buffer_vunmap +ffffffff8191b550 T drm_client_framebuffer_create +ffffffff8191b830 T drm_client_framebuffer_delete +ffffffff8191b930 T drm_client_framebuffer_flush +ffffffff8191c000 T drm_client_modeset_create +ffffffff8191c140 T drm_client_modeset_free +ffffffff8191c250 T drm_client_modeset_probe +ffffffff8191da10 t drm_client_pick_crtcs +ffffffff8191dd00 T drm_client_rotation +ffffffff8191dea0 T drm_client_modeset_check +ffffffff8191df40 t drm_client_modeset_commit_atomic +ffffffff8191e140 T drm_client_modeset_commit_locked +ffffffff8191e2d0 T drm_client_modeset_commit +ffffffff8191e340 T drm_client_modeset_dpms +ffffffff8191e590 t drm_connector_pick_cmdline_mode +ffffffff8191f000 T drm_color_ctm_s31_32_to_qm_n +ffffffff8191f0d0 T drm_crtc_enable_color_mgmt +ffffffff8191f1b0 T drm_mode_crtc_set_gamma_size +ffffffff8191f2d0 T drm_mode_gamma_set_ioctl +ffffffff8191f7c0 T drm_mode_gamma_get_ioctl +ffffffff8191f900 T drm_get_color_encoding_name +ffffffff8191f970 T drm_get_color_range_name +ffffffff8191f9e0 T drm_plane_create_color_properties +ffffffff8191fc30 T drm_color_lut_check +ffffffff81920000 T drm_connector_ida_init +ffffffff81920110 T drm_connector_ida_destroy +ffffffff81920220 T drm_get_connector_type_name +ffffffff81920260 T drm_connector_free_work_fn +ffffffff81920320 T drm_connector_init +ffffffff819203a0 t __drm_connector_init +ffffffff819208b0 T drm_connector_init_with_ddc +ffffffff81920930 T drmm_connector_init +ffffffff819209f0 t drm_connector_cleanup_action +ffffffff81920a00 T drm_connector_attach_edid_property +ffffffff81920a20 T drm_connector_attach_encoder +ffffffff81920aa0 T drm_connector_has_possible_encoder +ffffffff81920ae0 T drm_connector_cleanup +ffffffff81920e00 T drm_connector_unregister +ffffffff81920e90 T drm_mode_put_tile_group +ffffffff81920f20 T drm_connector_register +ffffffff81921010 T drm_connector_unregister_all +ffffffff819211b0 T drm_connector_list_iter_begin +ffffffff819211e0 T drm_connector_list_iter_next +ffffffff819212f0 T drm_connector_list_iter_end +ffffffff819213c0 T drm_connector_register_all +ffffffff81921550 T drm_get_connector_status_name +ffffffff819215a0 T drm_get_connector_force_name +ffffffff819215e0 T drm_get_subpixel_order_name +ffffffff81921610 T drm_get_dpms_name +ffffffff81921650 T drm_display_info_set_bus_formats +ffffffff81921720 T drm_get_dvi_i_select_name +ffffffff81921780 T drm_get_dvi_i_subconnector_name +ffffffff819217e0 T drm_get_tv_select_name +ffffffff81921830 T drm_get_tv_subconnector_name +ffffffff81921880 T drm_get_dp_subconnector_name +ffffffff81921910 T drm_connector_create_standard_properties +ffffffff81921a90 T drm_mode_create_dvi_i_properties +ffffffff81921b20 T drm_connector_attach_dp_subconnector_property +ffffffff81921b80 T drm_connector_attach_content_type_property +ffffffff81921c10 T drm_mode_create_content_type_property +ffffffff81921c90 T drm_connector_attach_tv_margin_properties +ffffffff81921cf0 T drm_mode_create_tv_margin_properties +ffffffff81921e10 T drm_mode_create_tv_properties +ffffffff81922070 T drm_mode_create_scaling_mode_property +ffffffff819220e0 T drm_connector_attach_vrr_capable_property +ffffffff81922170 T drm_connector_attach_scaling_mode_property +ffffffff81922340 T drm_mode_create_aspect_ratio_property +ffffffff819223c0 T drm_mode_create_hdmi_colorspace_property +ffffffff81922440 T drm_mode_create_dp_colorspace_property +ffffffff819224c0 T drm_mode_create_suggested_offset_properties +ffffffff81922580 T drm_connector_set_path_property +ffffffff819225d0 T drm_connector_set_tile_property +ffffffff81922720 T drm_connector_set_link_status_property +ffffffff81922770 T drm_connector_attach_max_bpc_property +ffffffff81922830 T drm_connector_attach_hdr_output_metadata_property +ffffffff81922880 T drm_connector_attach_colorspace_property +ffffffff819228c0 T drm_connector_atomic_hdr_metadata_equal +ffffffff81922930 T drm_connector_set_vrr_capable_property +ffffffff81922970 T drm_connector_set_panel_orientation +ffffffff81922a30 T drm_connector_set_panel_orientation_with_quirk +ffffffff81922b10 T drm_connector_set_orientation_from_panel +ffffffff81922c00 T drm_connector_create_privacy_screen_properties +ffffffff81922ca0 T drm_connector_attach_privacy_screen_properties +ffffffff81922d10 T drm_connector_attach_privacy_screen_provider +ffffffff81922e20 t drm_connector_privacy_screen_notifier +ffffffff81922ec0 T drm_connector_update_privacy_screen +ffffffff81922f30 T drm_connector_set_obj_prop +ffffffff81923010 T drm_connector_property_set_ioctl +ffffffff81923070 T drm_mode_getconnector +ffffffff819235b0 T drm_connector_find_by_fwnode +ffffffff81923660 T drm_connector_oob_hotplug_event +ffffffff81923740 T drm_mode_get_tile_group +ffffffff81923810 T drm_mode_create_tile_group +ffffffff819238d0 t drm_connector_free +ffffffff81923910 t kasprintf +ffffffff81924000 T drm_crtc_from_index +ffffffff81924060 T drm_crtc_force_disable +ffffffff81924170 T drm_mode_set_config_internal +ffffffff819241f0 T drm_crtc_register_all +ffffffff81924270 T drm_crtc_unregister_all +ffffffff819242e0 T drm_crtc_create_fence +ffffffff81924370 T drm_crtc_init_with_planes +ffffffff81924440 t __drm_crtc_init_with_planes +ffffffff81924830 T drmm_crtc_init_with_planes +ffffffff81924930 T __drmm_crtc_alloc_with_planes +ffffffff81924aa0 T drm_crtc_cleanup +ffffffff81924bc0 T drm_mode_getcrtc +ffffffff81924d50 t __drm_mode_set_config_internal +ffffffff81924ef0 T drm_crtc_check_viewport +ffffffff81924fa0 T drm_mode_setcrtc +ffffffff81925700 T drm_mode_crtc_set_obj_prop +ffffffff81925780 T drm_crtc_create_scaling_filter_property +ffffffff819257f0 t drm_crtc_fence_get_driver_name +ffffffff81925860 t drm_crtc_fence_get_timeline_name +ffffffff819258c0 t kasprintf +ffffffff81925990 t drmm_crtc_init_with_planes_cleanup +ffffffff81926000 T drm_helper_encoder_in_use +ffffffff81926170 T drm_helper_crtc_in_use +ffffffff81926290 T drm_helper_disable_unused_functions +ffffffff81926310 t __drm_helper_disable_unused_functions +ffffffff81926410 T drm_crtc_helper_set_mode +ffffffff819268c0 T drm_connector_get_single_encoder +ffffffff819269c0 T drm_crtc_helper_set_config +ffffffff819275e0 T drm_helper_connector_dpms +ffffffff819278d0 T drm_helper_resume_force_mode +ffffffff81927bb0 T drm_helper_force_disable_all +ffffffff81927c80 t drm_encoder_disable +ffffffff81928000 T drm_atomic_helper_check_plane_damage +ffffffff819280a0 T drm_atomic_helper_dirtyfb +ffffffff81928350 T drm_atomic_helper_damage_iter_init +ffffffff81928490 T drm_atomic_helper_damage_iter_next +ffffffff81928530 T drm_atomic_helper_damage_merged +ffffffff81929000 T displayid_iter_edid_begin +ffffffff81929040 T __displayid_iter_next +ffffffff819292d0 T displayid_iter_end +ffffffff8192a000 T drm_mode_create_dumb +ffffffff8192a0c0 T drm_mode_create_dumb_ioctl +ffffffff8192a180 T drm_mode_mmap_dumb_ioctl +ffffffff8192a1f0 T drm_mode_destroy_dumb +ffffffff8192a260 T drm_mode_destroy_dumb_ioctl +ffffffff8192b000 T drm_edid_header_is_valid +ffffffff8192b080 T drm_edid_are_equal +ffffffff8192b0f0 T drm_edid_block_valid +ffffffff8192b2f0 t edid_block_check +ffffffff8192b420 t edid_block_status_print +ffffffff8192b520 T drm_edid_is_valid +ffffffff8192b5a0 T drm_edid_override_set +ffffffff8192b610 T drm_connector_update_edid_property +ffffffff8192b7b0 T drm_edid_override_reset +ffffffff8192b8e0 T drm_add_override_edid_modes +ffffffff8192bac0 T drm_add_edid_modes +ffffffff8192bbb0 T drm_do_get_edid +ffffffff8192bbc0 t _drm_do_get_edid +ffffffff8192c0d0 T drm_edid_raw +ffffffff8192c150 T drm_edid_alloc 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drm_default_rgb_quant_range +ffffffff8192df50 T drm_edid_connector_update +ffffffff8192dfb0 t _drm_edid_connector_update +ffffffff8192fe60 t _drm_update_tile_info +ffffffff819300f0 t _drm_edid_connector_property_update +ffffffff819302a0 T drm_add_modes_noedid +ffffffff81930380 T drm_set_preferred_mode +ffffffff819303e0 T drm_hdmi_avi_infoframe_from_display_mode +ffffffff81930660 T drm_hdmi_avi_infoframe_quant_range +ffffffff81930700 T drm_hdmi_vendor_infoframe_from_display_mode +ffffffff819307c0 t connector_bad_edid +ffffffff81930980 t drm_for_each_detailed_block +ffffffff81930bd0 t __cea_db_iter_next +ffffffff81930e70 t update_display_info +ffffffff81931cf0 t get_monitor_range +ffffffff81931d90 t do_detailed_mode +ffffffff819326b0 t hdmi_mode_alternate_clock +ffffffff81932760 t do_cvt_mode +ffffffff819329b0 t drm_mode_std +ffffffff819336c0 t do_standard_modes +ffffffff81933800 t drm_monitor_supports_rb +ffffffff81933af0 t drm_gtf2_hbreak +ffffffff81933d80 t do_established_modes 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drm_fb_helper_restore_fbdev_mode_unlocked +ffffffff81937310 T drm_fb_helper_blank +ffffffff819373a0 T drm_fb_helper_prepare +ffffffff81937470 t drm_fb_helper_resume_worker +ffffffff819374a0 t drm_fb_helper_damage_work +ffffffff81937820 T drm_fb_helper_init +ffffffff81937890 T drm_fb_helper_alloc_fbi +ffffffff819378f0 T drm_fb_helper_unregister_fbi +ffffffff81937920 T drm_fb_helper_fini +ffffffff81937a10 T drm_fb_helper_set_suspend +ffffffff81937a40 T drm_fb_helper_set_suspend_unlocked +ffffffff81937a70 T drm_fb_helper_set_par +ffffffff81937b60 T drm_fb_helper_pan_display +ffffffff81937c30 T drm_fb_helper_fill_info +ffffffff81937cf0 T drm_fb_helper_initial_config +ffffffff81937d20 t __drm_fb_helper_initial_config_and_unlock +ffffffff81938270 T drm_fb_helper_hotplug_event +ffffffff81938470 t drm_setup_crtcs_fb +ffffffff819385b0 T drm_fb_helper_lastclose +ffffffff81938660 T drm_fb_helper_output_poll_changed +ffffffff81938680 T drm_fbdev_generic_setup +ffffffff81938830 t drm_fbdev_client_hotplug +ffffffff81938a60 t drm_fbdev_client_unregister +ffffffff81938ad0 t drm_fbdev_client_restore +ffffffff81938b70 t drm_fbdev_cleanup +ffffffff81938c10 t drm_fbdev_use_shadow_fb +ffffffff81938c60 t drm_fb_helper_generic_probe +ffffffff81939000 T drm_dev_needs_global_mutex +ffffffff81939060 T drm_file_alloc +ffffffff819392c0 T drm_file_free +ffffffff819394f0 T drm_lastclose +ffffffff81939550 T drm_release +ffffffff819395a0 T drm_release_noglobal +ffffffff819395f0 T drm_read +ffffffff81939640 T drm_event_reserve_init_locked +ffffffff819396b0 T drm_event_reserve_init +ffffffff81939770 T drm_event_cancel_free +ffffffff819397f0 T drm_send_event_timestamp_locked +ffffffff81939800 t drm_send_event_helper +ffffffff819399e0 T drm_send_event_locked +ffffffff819399f0 T drm_send_event +ffffffff81939a40 T mock_drm_getfile +ffffffff8193a000 T drm_flip_work_allocate_task +ffffffff8193a050 T drm_flip_work_queue_task +ffffffff8193a0a0 T drm_flip_work_queue +ffffffff8193a140 T drm_flip_work_commit +ffffffff8193a1c0 T drm_flip_work_init +ffffffff8193a230 t flip_worker +ffffffff8193a310 T drm_flip_work_cleanup +ffffffff8193b000 T drm_fb_clip_offset +ffffffff8193b040 T drm_fb_memcpy +ffffffff8193b2c0 T drm_fb_swab +ffffffff8193b3c0 t drm_fb_swab32_line +ffffffff8193b410 t drm_fb_swab16_line +ffffffff8193b460 t drm_fb_xfrm +ffffffff8193b720 T drm_fb_xrgb8888_to_rgb332 +ffffffff8193b780 t drm_fb_xrgb8888_to_rgb332_line +ffffffff8193b870 T drm_fb_xrgb8888_to_rgb565 +ffffffff8193b8e0 t drm_fb_xrgb8888_to_rgb565_swab_line +ffffffff8193b950 t drm_fb_xrgb8888_to_rgb565_line +ffffffff8193ba40 T drm_fb_xrgb8888_to_rgb888 +ffffffff8193baa0 t drm_fb_xrgb8888_to_rgb888_line +ffffffff8193bb30 T drm_fb_xrgb8888_to_xrgb2101010 +ffffffff8193bb90 t drm_fb_xrgb8888_to_xrgb2101010_line +ffffffff8193bc10 T drm_fb_xrgb8888_to_gray8 +ffffffff8193bc70 t drm_fb_xrgb8888_to_gray8_line +ffffffff8193bce0 T drm_fb_blit +ffffffff8193c130 T drm_fb_xrgb8888_to_mono +ffffffff8193c4c0 T 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pcie_get_width_cap +ffffffff8194dff0 T pcie_aspm_enabled +ffffffff8194e070 T autoremove_wake_function +ffffffff8194e0f0 T wait_on_bit +ffffffff8194e1b0 T wait_on_bit_timeout +ffffffff8194e270 T wake_up_bit +ffffffff8194e2b0 T clear_and_wake_up_bit +ffffffff8194e300 T bit_waitqueue +ffffffff8194e330 T __var_waitqueue +ffffffff8194e360 T drm_linux_init +ffffffff8194e4d0 T drm_linux_exit +ffffffff8194e520 T pci_resize_resource +ffffffff8194e670 T register_shrinker +ffffffff8194e6c0 T unregister_shrinker +ffffffff8194e720 T drmbackoff +ffffffff8194e7b0 T bitmap_zalloc +ffffffff8194e7e0 T bitmap_free +ffffffff8194e800 T atomic_dec_and_mutex_lock +ffffffff8194e870 T interval_tree_iter_first +ffffffff8194e920 T interval_tree_remove +ffffffff8194e940 T interval_tree_insert +ffffffff8194e9b0 T syncfile_read +ffffffff8194e9e0 T syncfile_write +ffffffff8194ea10 T syncfile_ioctl +ffffffff8194ea40 T syncfile_kqfilter +ffffffff8194ea70 T syncfile_stat +ffffffff8194eb20 T syncfile_close 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mipi_dsi_create_packet +ffffffff819512b0 T mipi_dsi_shutdown_peripheral +ffffffff81951350 T mipi_dsi_turn_on_peripheral +ffffffff819513f0 T mipi_dsi_set_maximum_return_packet_size +ffffffff81951490 T mipi_dsi_compression_mode +ffffffff81951540 T mipi_dsi_picture_parameter_set +ffffffff819515f0 T mipi_dsi_generic_write +ffffffff819516a0 T mipi_dsi_generic_read +ffffffff81951750 T mipi_dsi_dcs_write_buffer +ffffffff81951810 T mipi_dsi_dcs_write +ffffffff81951950 T mipi_dsi_dcs_read +ffffffff819519e0 T mipi_dsi_dcs_nop +ffffffff81951a90 T mipi_dsi_dcs_soft_reset +ffffffff81951b40 T mipi_dsi_dcs_get_power_mode +ffffffff81951c00 T mipi_dsi_dcs_get_pixel_format +ffffffff81951cc0 T mipi_dsi_dcs_enter_sleep_mode +ffffffff81951d70 T mipi_dsi_dcs_exit_sleep_mode +ffffffff81951e20 T mipi_dsi_dcs_set_display_off +ffffffff81951ed0 T mipi_dsi_dcs_set_display_on +ffffffff81951f80 T mipi_dsi_dcs_set_column_address +ffffffff81952040 T mipi_dsi_dcs_set_page_address +ffffffff81952100 T mipi_dsi_dcs_set_tear_off +ffffffff819521b0 T mipi_dsi_dcs_set_tear_on +ffffffff81952260 T mipi_dsi_dcs_set_pixel_format +ffffffff81953000 T __drm_mm_interval_first +ffffffff819530b0 T drm_mm_reserve_node +ffffffff81953350 t add_hole +ffffffff819534b0 T drm_mm_insert_node_in_range +ffffffff81953aa0 T drm_mm_remove_node +ffffffff81953bd0 T drm_mm_replace_node +ffffffff81953da0 T drm_mm_scan_init_with_range +ffffffff81953e20 T drm_mm_scan_add_block +ffffffff81953f90 T drm_mm_scan_remove_block +ffffffff81954000 T drm_mm_scan_color_evict +ffffffff819540e0 T drm_mm_init +ffffffff81954180 T drm_mm_takedown +ffffffff819541c0 T drm_mm_print +ffffffff81955000 T drm_modeset_register_all +ffffffff819550a0 T drm_modeset_unregister_all +ffffffff819550d0 T drm_mode_getresources +ffffffff81955380 T drm_mode_config_reset +ffffffff819554d0 T drmm_mode_config_init +ffffffff81955b50 T drm_mode_config_cleanup +ffffffff81955e90 t drm_mode_config_init_release +ffffffff81955ea0 T drm_mode_config_validate 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drm_mode_destroy +ffffffff81959230 T drm_mode_probed_add +ffffffff819592d0 T drm_cvt_mode +ffffffff81959780 T drm_mode_set_name +ffffffff819597d0 T drm_gtf_mode_complex +ffffffff81959ac0 T drm_gtf_mode +ffffffff81959b10 T drm_mode_get_hv_timing +ffffffff81959b60 T drm_mode_init +ffffffff81959c30 T drm_mode_set_crtcinfo +ffffffff81959de0 T drm_mode_copy +ffffffff81959e40 T drm_mode_duplicate +ffffffff81959ec0 T drm_mode_match +ffffffff8195a060 T drm_mode_equal +ffffffff8195a080 T drm_mode_equal_no_clocks +ffffffff8195a0a0 T drm_mode_equal_no_clocks_no_stereo +ffffffff8195a160 T drm_mode_validate_driver +ffffffff8195a240 T drm_mode_validate_size +ffffffff8195a290 T drm_mode_validate_ycbcr420 +ffffffff8195a300 T drm_mode_is_420_only +ffffffff8195a350 T drm_get_mode_status_name +ffffffff8195a3c0 T drm_mode_prune_invalid +ffffffff8195a650 T drm_mode_sort +ffffffff8195a670 t drm_mode_compare +ffffffff8195a800 T drm_connector_list_update +ffffffff8195a9d0 T drm_mode_parse_command_line_for_connector +ffffffff8195aa00 T drm_mode_create_from_cmdline_mode +ffffffff8195aaf0 T drm_mode_convert_to_umode +ffffffff8195ac80 T drm_mode_convert_umode +ffffffff8195ae90 T drm_mode_is_420_also +ffffffff8195aee0 T drm_mode_is_420 +ffffffff8195b000 T drm_helper_move_panel_connectors_to_head +ffffffff8195b0f0 T drm_helper_mode_fill_fb_struct +ffffffff8195b1b0 T drm_crtc_init +ffffffff8195b280 T drm_mode_config_helper_suspend +ffffffff8195b310 T drm_mode_config_helper_resume +ffffffff8195c000 T drm_modeset_lock_all +ffffffff8195c1d0 T drm_modeset_acquire_init +ffffffff8195c260 T drm_modeset_lock_all_ctx +ffffffff8195c3d0 T drm_modeset_backoff +ffffffff8195c4a0 T drm_modeset_acquire_fini +ffffffff8195c4d0 T drm_warn_on_modeset_not_all_locked +ffffffff8195c620 T drm_modeset_unlock_all +ffffffff8195c700 T drm_modeset_drop_locks +ffffffff8195c790 T drm_modeset_unlock +ffffffff8195c850 t modeset_lock +ffffffff8195cae0 T drm_modeset_lock_init +ffffffff8195cb40 T drm_modeset_lock +ffffffff8195cb90 T drm_modeset_lock_single_interruptible +ffffffff8195cbb0 t __ww_mutex_lock +ffffffff8195d000 T drm_mtrr_add +ffffffff8195d070 T drm_mtrr_del +ffffffff8195e000 T drm_panel_init +ffffffff8195e040 T drm_panel_add +ffffffff8195e090 T drm_panel_remove +ffffffff8195e0e0 T drm_panel_prepare +ffffffff8195e130 T drm_panel_unprepare +ffffffff8195e180 T drm_panel_enable +ffffffff8195e220 T drm_panel_disable +ffffffff8195e2b0 T drm_panel_get_modes +ffffffff8195e300 T drm_panel_of_backlight +ffffffff8195f000 T drm_get_panel_orientation_quirk +ffffffff81960000 T drm_pci_set_busid +ffffffff81960090 t kasprintf +ffffffff81961000 T drm_universal_plane_init +ffffffff819610f0 t __drm_universal_plane_init +ffffffff819617e0 T __drmm_universal_plane_alloc +ffffffff81961920 t drmm_universal_plane_alloc_release +ffffffff81961960 T __drm_universal_plane_alloc +ffffffff81961aa0 T drm_plane_register_all +ffffffff81961b90 T drm_plane_unregister_all +ffffffff81961c00 T drm_plane_cleanup +ffffffff81961d50 T drm_plane_from_index +ffffffff81961db0 T drm_plane_force_disable +ffffffff81961ec0 T drm_mode_plane_set_obj_prop +ffffffff81961f40 T drm_mode_getplane_res +ffffffff81962030 T drm_mode_getplane +ffffffff81962190 T drm_plane_check_pixel_format +ffffffff81962250 T drm_any_plane_has_format +ffffffff81962380 T drm_mode_setplane +ffffffff819626e0 T drm_mode_cursor_ioctl +ffffffff81962740 t drm_mode_cursor_common +ffffffff81962dc0 T drm_mode_cursor2_ioctl +ffffffff81962dd0 T drm_mode_page_flip_ioctl +ffffffff81963340 T drm_plane_enable_fb_damage_clips +ffffffff81963360 T drm_plane_get_damage_clips_count +ffffffff819633a0 T __drm_plane_get_damage_clips +ffffffff819633e0 T drm_plane_get_damage_clips +ffffffff81963480 T drm_create_scaling_filter_prop +ffffffff819635d0 T drm_plane_create_scaling_filter_property +ffffffff81963640 t kasprintf +ffffffff81963710 t __setplane_internal +ffffffff81963900 t __setplane_check +ffffffff81964000 T drm_plane_helper_update_primary +ffffffff819644b0 t get_connectors_for_crtc +ffffffff819645c0 T drm_plane_helper_disable_primary +ffffffff81964670 T drm_plane_helper_destroy +ffffffff819646a0 T drm_plane_helper_atomic_check +ffffffff81965000 T drm_prime_remove_buf_handle +ffffffff81965090 T drm_prime_init_file_private +ffffffff819650e0 T drm_prime_destroy_file_private +ffffffff81965140 T drm_gem_dmabuf_export +ffffffff819651a0 T drm_gem_dmabuf_release +ffffffff819651e0 T drm_gem_prime_fd_to_handle +ffffffff819653e0 T drm_gem_prime_import +ffffffff81965440 t drm_prime_add_buf_handle +ffffffff81965590 T drm_prime_fd_to_handle_ioctl +ffffffff819655e0 T drm_gem_prime_handle_to_fd +ffffffff81965810 T drm_prime_handle_to_fd_ioctl +ffffffff81965870 T drm_gem_map_attach +ffffffff81965880 T drm_gem_map_detach +ffffffff81965890 T drm_gem_dmabuf_vmap +ffffffff819658a0 T drm_gem_dmabuf_vunmap +ffffffff819658b0 T drm_gem_prime_mmap +ffffffff81965900 T drm_prime_pages_to_sg +ffffffff81965950 T drm_prime_get_contiguous_size +ffffffff819659a0 T drm_gem_prime_export +ffffffff81965a30 T drm_gem_prime_import_dev +ffffffff81965a90 T drm_prime_sg_to_page_array +ffffffff81965ae0 T drm_prime_sg_to_dma_addr_array +ffffffff81965b30 T drm_prime_gem_destroy +ffffffff81966000 T __drm_puts_coredump +ffffffff819660e0 T __drm_printfn_coredump +ffffffff81966200 T __drm_puts_seq_file +ffffffff81966230 T __drm_printfn_seq_file +ffffffff81966260 T __drm_printfn_info +ffffffff81966290 T __drm_printfn_debug +ffffffff819662c0 T __drm_printfn_err +ffffffff81966300 T drm_puts +ffffffff81966330 T drm_printf +ffffffff819663b0 T drm_print_bits +ffffffff819665d0 T drm_dev_printk +ffffffff81966660 T __drm_dev_dbg +ffffffff819666f0 T ___drm_dbg +ffffffff81966780 T __drm_err +ffffffff81966810 T drm_print_regset32 +ffffffff81967000 T drm_crtc_mode_valid +ffffffff81967040 T drm_encoder_mode_valid +ffffffff81967080 T drm_connector_mode_valid +ffffffff819670f0 T drm_kms_helper_poll_enable +ffffffff819671e0 T drm_helper_probe_detect +ffffffff819673d0 T drm_helper_probe_single_connector_modes +ffffffff81967990 t __drm_helper_update_and_validate +ffffffff81967d40 T drm_kms_helper_hotplug_event +ffffffff81967d80 T drm_kms_helper_connector_hotplug_event +ffffffff81967dc0 T drm_kms_helper_is_poll_worker +ffffffff81967df0 T drm_kms_helper_poll_disable +ffffffff81967e60 T drm_kms_helper_poll_init +ffffffff81967ec0 t output_poll_execute +ffffffff81968150 T drm_kms_helper_poll_fini +ffffffff819681d0 T drm_connector_helper_hpd_irq_event +ffffffff81968290 t check_connector_changed +ffffffff81968470 T drm_helper_hpd_irq_event +ffffffff819685c0 T drm_crtc_helper_mode_valid_fixed +ffffffff81968610 T drm_connector_helper_get_modes_from_ddc +ffffffff81968690 T drm_connector_helper_get_modes_fixed +ffffffff819687f0 T drm_connector_helper_get_modes +ffffffff81968850 t __delayed_work_tick +ffffffff81969000 T drm_property_create +ffffffff819691f0 T drm_property_create_enum +ffffffff819692a0 T drm_property_add_enum +ffffffff819694b0 T drm_property_destroy +ffffffff81969560 T drm_property_create_bitmask +ffffffff81969690 T drm_property_create_range +ffffffff819696f0 T drm_property_create_signed_range +ffffffff81969760 T drm_property_create_object +ffffffff819697f0 T drm_property_create_bool +ffffffff81969850 T drm_mode_getproperty_ioctl +ffffffff81969a60 T drm_property_create_blob +ffffffff81969b90 t drm_property_free_blob +ffffffff81969c00 T drm_property_blob_put +ffffffff81969c30 T drm_property_destroy_user_blobs +ffffffff81969cb0 T drm_property_blob_get +ffffffff81969cf0 T drm_property_lookup_blob +ffffffff81969d10 T drm_property_replace_global_blob +ffffffff81969e60 T drm_property_replace_blob +ffffffff81969ed0 T drm_mode_getblob_ioctl +ffffffff81969f90 T drm_mode_createblob_ioctl +ffffffff8196a090 T drm_mode_destroyblob_ioctl +ffffffff8196a190 T drm_property_change_valid_get +ffffffff8196a3e0 T drm_property_change_valid_put +ffffffff8196b000 T drm_rect_intersect +ffffffff8196b080 T drm_rect_clip_scaled +ffffffff8196b2e0 T drm_rect_calc_hscale +ffffffff8196b3a0 T drm_rect_calc_vscale +ffffffff8196b470 T drm_rect_debug_print +ffffffff8196b580 T drm_rect_rotate +ffffffff8196b640 T drm_rect_rotate_inv +ffffffff8196c000 T drm_self_refresh_helper_update_avg_times +ffffffff8196c140 T drm_self_refresh_helper_alter_state +ffffffff8196c2d0 T drm_self_refresh_helper_init +ffffffff8196c470 t drm_self_refresh_helper_entry_work +ffffffff8196c5d0 T drm_self_refresh_helper_cleanup +ffffffff8196c650 t __delayed_work_tick +ffffffff8196d000 T drm_syncobj_find +ffffffff8196d070 T drm_syncobj_add_point +ffffffff8196d160 t syncobj_wait_syncobj_func +ffffffff8196d210 T drm_syncobj_replace_fence +ffffffff8196d2a0 T drm_syncobj_find_fence +ffffffff8196d600 t drm_syncobj_fence_add_wait +ffffffff8196d6d0 T drm_syncobj_free +ffffffff8196d750 T drm_syncobj_create +ffffffff8196d960 T drm_syncobj_get_handle +ffffffff8196da80 T drm_syncobj_get_fd +ffffffff8196dad0 T drm_syncobj_open +ffffffff8196db00 T drm_syncobj_release +ffffffff8196db30 t drm_syncobj_release_handle +ffffffff8196dbe0 T drm_syncobj_create_ioctl +ffffffff8196dd00 T drm_syncobj_destroy_ioctl +ffffffff8196de20 T drm_syncobj_handle_to_fd_ioctl +ffffffff8196e000 T drm_syncobj_fd_to_handle_ioctl +ffffffff8196e1e0 T drm_syncobj_transfer_ioctl +ffffffff8196e5f0 T drm_timeout_abs_to_jiffies +ffffffff8196e6d0 T drm_syncobj_wait_ioctl +ffffffff8196e860 t drm_syncobj_array_find +ffffffff8196ea90 t drm_syncobj_array_free +ffffffff8196eb70 T drm_syncobj_timeline_wait_ioctl +ffffffff8196ed00 T drm_syncobj_reset_ioctl +ffffffff8196ee50 T drm_syncobj_signal_ioctl +ffffffff8196efd0 T drm_syncobj_timeline_signal_ioctl +ffffffff8196f1f0 T drm_syncobj_query_ioctl +ffffffff8196f3f0 t drm_syncobj_array_wait_timeout +ffffffff8196f860 t syncobj_wait_fence_func +ffffffff81970000 T drm_vblank_count +ffffffff81970090 T drm_crtc_accurate_vblank_count +ffffffff819701a0 t drm_update_vblank_count +ffffffff819705f0 T drm_vblank_disable_and_save +ffffffff81970740 T drm_vblank_init +ffffffff819708c0 t vblank_disable_fn +ffffffff81970940 t drm_vblank_init_release +ffffffff819709c0 T drm_dev_has_vblank +ffffffff819709f0 T drm_crtc_vblank_waitqueue +ffffffff81970a30 T drm_calc_timestamping_constants +ffffffff81970c60 T drm_crtc_vblank_helper_get_vblank_timestamp_internal +ffffffff81971190 T drm_crtc_vblank_helper_get_vblank_timestamp +ffffffff819711b0 T drm_crtc_vblank_count +ffffffff81971240 T drm_crtc_vblank_count_and_time +ffffffff81971300 T drm_crtc_arm_vblank_event +ffffffff819713e0 T drm_crtc_send_vblank_event +ffffffff81971590 T drm_vblank_get +ffffffff819716a0 t drm_vblank_enable +ffffffff81971860 T drm_crtc_vblank_get +ffffffff81971960 T drm_vblank_put +ffffffff81971a90 T drm_crtc_vblank_put +ffffffff81971ab0 T drm_wait_one_vblank +ffffffff81971f00 T drm_crtc_wait_one_vblank +ffffffff81971f20 T drm_crtc_vblank_off +ffffffff81972300 T drm_crtc_vblank_reset +ffffffff81972430 T drm_crtc_set_max_vblank_count +ffffffff81972510 T drm_crtc_vblank_on +ffffffff81972660 t drm_reset_vblank_timestamp +ffffffff81972860 T drm_crtc_vblank_restore +ffffffff81972c40 T drm_legacy_modeset_ctl_ioctl +ffffffff81972e50 T drm_wait_vblank_ioctl +ffffffff81973890 T drm_handle_vblank +ffffffff81973b70 t drm_handle_vblank_events +ffffffff81973e00 T drm_crtc_handle_vblank +ffffffff81973e20 T drm_crtc_get_sequence_ioctl +ffffffff81974010 T drm_crtc_queue_sequence_ioctl +ffffffff819743e0 t __get_vblank_counter +ffffffff81975000 T drm_handle_vblank_works +ffffffff819751b0 T drm_vblank_cancel_pending_works +ffffffff819752f0 T drm_vblank_work_schedule +ffffffff81975570 T drm_vblank_work_cancel_sync +ffffffff819756d0 T drm_vblank_work_flush +ffffffff819757a0 T drm_vblank_work_init +ffffffff81975810 T drm_vblank_worker_init +ffffffff81976000 T drm_vma_offset_manager_init +ffffffff81976040 T drm_vma_offset_manager_destroy +ffffffff81976050 T drm_vma_offset_lookup_locked +ffffffff819760e0 T drm_vma_offset_add +ffffffff81976170 T drm_vma_offset_remove +ffffffff819761c0 T drm_vma_node_allow +ffffffff819761d0 t vma_node_allow +ffffffff81976300 T drm_vma_node_allow_once +ffffffff81976310 T drm_vma_node_revoke +ffffffff81976390 T drm_vma_node_is_allowed +ffffffff81977000 T hdmi_avi_infoframe_init +ffffffff81977070 T hdmi_avi_infoframe_check +ffffffff819770c0 T hdmi_avi_infoframe_pack_only +ffffffff819772c0 T hdmi_avi_infoframe_pack +ffffffff81977320 T hdmi_spd_infoframe_init +ffffffff819773d0 T hdmi_spd_infoframe_check +ffffffff81977420 T hdmi_spd_infoframe_pack_only +ffffffff81977550 T hdmi_spd_infoframe_pack +ffffffff819776a0 T hdmi_audio_infoframe_init +ffffffff819776f0 T hdmi_audio_infoframe_check +ffffffff81977740 T hdmi_audio_infoframe_pack_only +ffffffff81977890 T hdmi_audio_infoframe_pack +ffffffff819778e0 T hdmi_audio_infoframe_pack_for_dp +ffffffff819779d0 T hdmi_vendor_infoframe_init +ffffffff81977a30 T hdmi_vendor_infoframe_check +ffffffff81977ad0 T hdmi_vendor_infoframe_pack_only +ffffffff81977ca0 T hdmi_vendor_infoframe_pack +ffffffff81977d40 T hdmi_drm_infoframe_init +ffffffff81977da0 T hdmi_drm_infoframe_check +ffffffff81977df0 T hdmi_drm_infoframe_pack_only +ffffffff81977fc0 T hdmi_drm_infoframe_pack +ffffffff81978010 T hdmi_infoframe_check +ffffffff81978160 T hdmi_infoframe_pack_only +ffffffff81978370 T hdmi_infoframe_pack +ffffffff819784e0 T hdmi_infoframe_log +ffffffff81979480 T hdmi_drm_infoframe_unpack_only +ffffffff81979560 T hdmi_infoframe_unpack +ffffffff8197a000 T list_sort +ffffffff8197b000 T radix_tree_lookup +ffffffff8197b0b0 T radix_tree_iter_find +ffffffff8197b190 T radix_tree_delete +ffffffff8197b320 T radix_tree_iter_delete +ffffffff8197b340 T radix_tree_insert +ffffffff8197c000 T sort +ffffffff8197c040 t qsort +ffffffff8197e000 T drm_dp_dual_mode_read +ffffffff8197e110 T drm_dp_dual_mode_write +ffffffff8197e1f0 T drm_dp_dual_mode_detect +ffffffff8197e490 T drm_dp_dual_mode_max_tmds_clock +ffffffff8197e5b0 T drm_dp_dual_mode_get_tmds_output +ffffffff8197e6e0 T drm_dp_dual_mode_set_tmds_output +ffffffff8197e970 T drm_dp_get_dual_mode_type_name +ffffffff8197e9e0 T drm_lspcon_get_mode +ffffffff8197eb90 T drm_lspcon_set_mode +ffffffff8197f000 T drm_dp_channel_eq_ok +ffffffff8197f080 T drm_dp_clock_recovery_ok +ffffffff8197f100 T drm_dp_get_adjust_request_voltage +ffffffff8197f140 T drm_dp_get_adjust_request_pre_emphasis +ffffffff8197f180 T drm_dp_get_adjust_tx_ffe_preset +ffffffff8197f1c0 T drm_dp_128b132b_lane_channel_eq_done +ffffffff8197f240 T drm_dp_128b132b_lane_symbol_locked +ffffffff8197f2b0 T drm_dp_128b132b_eq_interlane_align_done +ffffffff8197f2e0 T drm_dp_128b132b_cds_interlane_align_done +ffffffff8197f310 T drm_dp_128b132b_link_training_failed +ffffffff8197f340 T drm_dp_read_clock_recovery_delay +ffffffff8197f440 T drm_dp_read_channel_eq_delay +ffffffff8197f530 T drm_dp_128b132b_read_aux_rd_interval +ffffffff8197f5e0 T drm_dp_link_train_clock_recovery_delay +ffffffff8197f660 t __8b10b_clock_recovery_delay_us +ffffffff8197f6e0 T drm_dp_link_train_channel_eq_delay +ffffffff8197f750 T drm_dp_phy_name +ffffffff8197f790 T drm_dp_lttpr_link_train_clock_recovery_delay +ffffffff8197f7b0 T drm_dp_lttpr_link_train_channel_eq_delay +ffffffff8197f820 T drm_dp_link_rate_to_bw_code +ffffffff8197f880 T drm_dp_bw_code_to_link_rate +ffffffff8197f8e0 T drm_dp_dpcd_probe +ffffffff8197fa20 t drm_dp_dpcd_access +ffffffff8197fb50 T drm_dp_dpcd_read +ffffffff8197fc80 T drm_dp_dpcd_write +ffffffff8197fd90 T drm_dp_dpcd_read_link_status +ffffffff8197fdb0 T drm_dp_dpcd_read_phy_link_status +ffffffff8197feb0 T drm_dp_downstream_is_type +ffffffff8197fef0 T drm_dp_downstream_is_tmds +ffffffff8197ff60 T drm_dp_send_real_edid_checksum +ffffffff819801c0 T drm_dp_read_dpcd_caps +ffffffff81980350 T drm_dp_read_downstream_info +ffffffff81980450 T drm_dp_downstream_max_dotclock +ffffffff819804a0 T drm_dp_downstream_max_tmds_clock +ffffffff81980540 T drm_dp_downstream_min_tmds_clock +ffffffff819805c0 T drm_dp_downstream_max_bpc +ffffffff81980660 T drm_dp_downstream_420_passthrough +ffffffff819806c0 T drm_dp_downstream_444_to_420_conversion +ffffffff81980720 T drm_dp_downstream_rgb_to_ycbcr_conversion +ffffffff81980780 T drm_dp_downstream_mode +ffffffff81980800 T drm_dp_downstream_id +ffffffff81980820 T drm_dp_downstream_debug +ffffffff819808c0 T drm_dp_subconnector_type +ffffffff81980920 T drm_dp_set_subconnector_property +ffffffff81980990 T drm_dp_read_sink_count_cap +ffffffff819809e0 T drm_dp_read_sink_count +ffffffff81980a40 T drm_dp_remote_aux_init +ffffffff81980a70 t drm_dp_aux_crc_work +ffffffff81980be0 T drm_dp_aux_init +ffffffff81980c90 T drm_dp_aux_register +ffffffff81980db0 T drm_dp_aux_unregister +ffffffff81980de0 T drm_dp_psr_setup_time +ffffffff81980e20 T drm_dp_start_crc +ffffffff81980ec0 T drm_dp_stop_crc +ffffffff81980f50 T drm_dp_read_desc +ffffffff81981110 T drm_dp_dsc_sink_max_slice_count +ffffffff819811a0 T drm_dp_dsc_sink_line_buf_depth +ffffffff819811e0 T drm_dp_dsc_sink_supported_input_bpcs +ffffffff81981240 T drm_dp_read_lttpr_common_caps +ffffffff81981300 T drm_dp_read_lttpr_phy_caps +ffffffff819813c0 T drm_dp_lttpr_count +ffffffff81981440 T drm_dp_lttpr_max_link_rate +ffffffff81981490 T drm_dp_lttpr_max_lane_count +ffffffff819814c0 T drm_dp_lttpr_voltage_swing_level_3_supported +ffffffff819814f0 T drm_dp_lttpr_pre_emphasis_level_3_supported +ffffffff81981520 T drm_dp_get_phy_test_pattern +ffffffff81981640 T drm_dp_set_phy_test_pattern +ffffffff81981710 T drm_dp_vsc_sdp_log +ffffffff81981a40 T drm_dp_get_pcon_max_frl_bw +ffffffff81981a80 T drm_dp_pcon_frl_prepare +ffffffff81981ad0 T drm_dp_pcon_is_frl_ready +ffffffff81981b20 T drm_dp_pcon_frl_configure_1 +ffffffff81981c10 T drm_dp_pcon_frl_configure_2 +ffffffff81981c70 T drm_dp_pcon_reset_frl_config +ffffffff81981cc0 T drm_dp_pcon_frl_enable +ffffffff81981d70 T drm_dp_pcon_hdmi_link_active +ffffffff81981dc0 T drm_dp_pcon_hdmi_link_mode +ffffffff81981e30 T drm_dp_pcon_hdmi_frl_link_error_count +ffffffff81981f30 T drm_dp_pcon_enc_is_dsc_1_2 +ffffffff81981f60 T drm_dp_pcon_dsc_max_slices +ffffffff81981ff0 T drm_dp_pcon_dsc_max_slice_width +ffffffff81982020 T drm_dp_pcon_dsc_bpp_incr +ffffffff81982060 T drm_dp_pcon_pps_default +ffffffff819820e0 T drm_dp_pcon_pps_override_buf +ffffffff81982190 T drm_dp_pcon_pps_override_param +ffffffff81982270 T drm_dp_pcon_convert_rgb_to_ycbcr +ffffffff81982300 T drm_edp_backlight_set_level +ffffffff819823e0 T drm_edp_backlight_enable +ffffffff819825f0 t drm_edp_backlight_set_enable +ffffffff81982730 T drm_edp_backlight_disable +ffffffff81982770 T drm_edp_backlight_init +ffffffff81982cc0 T drm_panel_dp_aux_backlight +ffffffff81982e50 t __128b132b_channel_eq_delay_us +ffffffff81982ed0 t __8b10b_channel_eq_delay_us +ffffffff81982f50 t drm_dp_aux_get_crc +ffffffff81983020 t drm_dp_i2c_xfer +ffffffff81983270 t drm_dp_i2c_functionality +ffffffff819832a0 t drm_dp_i2c_do_msg +ffffffff81983680 t lock_bus +ffffffff819836a0 t trylock_bus +ffffffff819836f0 t unlock_bus +ffffffff81983710 t dp_aux_backlight_update_status +ffffffff81984000 T drm_dp_encode_sideband_req +ffffffff81984410 T drm_dp_decode_sideband_req +ffffffff81984950 T drm_dp_dump_sideband_msg_req_body +ffffffff81984d00 T drm_dp_mst_get_port_malloc +ffffffff81984d40 T drm_dp_mst_put_port_malloc +ffffffff81984e30 t kref_put +ffffffff81984e70 T drm_atomic_get_mst_payload_state +ffffffff81984ec0 T drm_dp_mst_dpcd_read +ffffffff81985180 T drm_dp_mst_dpcd_write +ffffffff819851d0 t drm_dp_send_dpcd_write +ffffffff81985410 T drm_dp_mst_connector_late_register +ffffffff81985490 T drm_dp_mst_connector_early_unregister +ffffffff819854d0 T drm_dp_send_power_updown_phy +ffffffff81985710 t drm_dp_mst_topology_put_port +ffffffff81985840 t drm_dp_mst_wait_tx_reply +ffffffff81985b90 T drm_dp_send_query_stream_enc_status +ffffffff81985e50 T drm_dp_add_payload_part1 +ffffffff81986000 T drm_dp_remove_payload +ffffffff81986190 T drm_dp_add_payload_part2 +ffffffff81986340 T drm_dp_get_vc_payload_bw +ffffffff819863d0 T drm_dp_read_mst_cap +ffffffff81986430 T drm_dp_mst_topology_mgr_set_mst +ffffffff819866f0 t drm_dp_dpcd_write_payload +ffffffff81986880 t drm_dp_mst_topology_put_mstb +ffffffff81986980 T drm_dp_mst_topology_mgr_suspend +ffffffff81986a40 t drm_dp_mst_topology_mgr_invalidate_mstb +ffffffff81986ab0 T drm_dp_mst_topology_mgr_resume +ffffffff81986cf0 T drm_dp_mst_hpd_irq +ffffffff81987b60 T drm_dp_mst_detect_port +ffffffff81987cd0 T drm_dp_mst_get_edid +ffffffff81987dd0 T drm_dp_atomic_find_time_slots +ffffffff819880a0 T drm_atomic_get_mst_topology_state +ffffffff819880b0 T drm_dp_atomic_release_time_slots +ffffffff819882d0 T drm_dp_mst_atomic_setup_commit +ffffffff81988460 T drm_dp_mst_atomic_wait_for_dependencies +ffffffff819885e0 T drm_dp_mst_root_conn_atomic_check +ffffffff819886f0 T drm_dp_mst_update_slots +ffffffff81988740 T drm_dp_check_act_status +ffffffff819888f0 T drm_dp_calc_pbn_mode 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+ffffffff8198a9f0 t drm_dp_mst_dump_sideband_msg_tx +ffffffff8198ac00 t process_single_down_tx_qlock +ffffffff8198ad70 t process_single_tx_qlock +ffffffff8198b250 t drm_dp_msg_data_crc4 +ffffffff8198b370 t drm_dp_payload_send_msg +ffffffff8198b7c0 t drm_dp_mst_topology_get_mstb_validated_locked +ffffffff8198b840 t drm_dp_get_one_sb_msg +ffffffff8198bf60 t drm_dp_get_mst_branch_device +ffffffff8198c0d0 t drm_dp_check_and_send_link_address +ffffffff8198c1a0 t drm_dp_send_link_address +ffffffff8198ce50 t drm_dp_send_enum_path_resources +ffffffff8198d0b0 t drm_dp_port_set_pdt +ffffffff8198d390 t drm_dp_mst_port_add_connector +ffffffff8198d570 t drm_dp_mst_i2c_xfer +ffffffff8198dc60 t drm_dp_mst_i2c_functionality +ffffffff8198dc90 t get_mst_branch_device_by_guid_helper +ffffffff8198e000 T drm_dsc_dp_pps_header_init +ffffffff8198e030 T drm_dsc_dp_rc_buffer_size +ffffffff8198e090 T drm_dsc_pps_payload_pack +ffffffff8198e320 T drm_dsc_compute_rc_parameters +ffffffff8198f000 T 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intel_ddi_enable_pipe_clock +ffffffff819ea310 T intel_ddi_disable_pipe_clock +ffffffff819ea370 T intel_ddi_level +ffffffff819ea540 T icl_ddi_combo_get_pll +ffffffff819ea5b0 T hsw_ddi_enable_clock +ffffffff819ea670 T hsw_ddi_disable_clock +ffffffff819ea6b0 T hsw_ddi_is_clock_enabled +ffffffff819ea710 T intel_ddi_enable_clock +ffffffff819ea750 T intel_ddi_disable_clock +ffffffff819ea790 T intel_ddi_sanitize_encoder_pll_mapping +ffffffff819ea970 T dp_tp_ctl_reg +ffffffff819ea9f0 T dp_tp_status_reg +ffffffff819eaa70 T intel_ddi_update_pipe +ffffffff819eaaf0 T intel_ddi_compute_min_voltage_level +ffffffff819eab60 T intel_ddi_get_clock +ffffffff819eac70 T hsw_ddi_get_config +ffffffff819ead50 t intel_ddi_get_config +ffffffff819eb5c0 T intel_ddi_init +ffffffff819ec160 t intel_ddi_hotplug +ffffffff819ec590 t intel_ddi_compute_output_type +ffffffff819ec610 t intel_ddi_compute_config +ffffffff819ec750 t intel_ddi_compute_config_late +ffffffff819eca00 t intel_enable_ddi +ffffffff819ed1e0 t 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bdw_digital_port_connected +ffffffff819f2120 t hsw_digital_port_connected +ffffffff819f2190 t intel_ddi_encoder_reset +ffffffff819f21d0 t intel_ddi_encoder_destroy +ffffffff819f2280 t icl_program_mg_dp_mode +ffffffff819f2510 t intel_ddi_init_dp_buf_reg +ffffffff819f26d0 t intel_disable_ddi_buf +ffffffff819f29f0 t intel_ddi_prepare_link_retrain +ffffffff819f3060 t intel_ddi_set_link_train +ffffffff819f31c0 t intel_ddi_set_idle_link_train +ffffffff819f33e0 t intel_ddi_dp_voltage_max +ffffffff819f34a0 t intel_ddi_dp_preemph_max +ffffffff819f4000 T is_hobl_buf_trans +ffffffff819f4030 T intel_ddi_buf_trans_init +ffffffff819f42f0 t dg2_get_snps_buf_trans +ffffffff819f4360 t adlp_get_combo_buf_trans +ffffffff819f4490 t adlp_get_dkl_buf_trans +ffffffff819f44f0 t adls_get_combo_buf_trans +ffffffff819f4620 t rkl_get_combo_buf_trans +ffffffff819f4750 t dg1_get_combo_buf_trans +ffffffff819f4880 t tgl_get_combo_buf_trans +ffffffff819f49d0 t tgl_get_dkl_buf_trans +ffffffff819f4a30 t jsl_get_combo_buf_trans +ffffffff819f4ae0 t ehl_get_combo_buf_trans +ffffffff819f4b90 t icl_get_combo_buf_trans +ffffffff819f4c40 t icl_get_mg_buf_trans +ffffffff819f4ca0 t bxt_get_buf_trans +ffffffff819f4d30 t kbl_y_get_buf_trans +ffffffff819f4de0 t kbl_u_get_buf_trans +ffffffff819f4e90 t kbl_get_buf_trans +ffffffff819f4f40 t skl_y_get_buf_trans +ffffffff819f4ff0 t skl_u_get_buf_trans +ffffffff819f50a0 t skl_get_buf_trans +ffffffff819f5150 t bdw_get_buf_trans +ffffffff819f51f0 t hsw_get_buf_trans +ffffffff819f6000 T intel_update_watermarks +ffffffff819f6040 T vlv_get_hpll_vco +ffffffff819f6090 T vlv_get_cck_clock +ffffffff819f6140 T vlv_get_cck_clock_hpll +ffffffff819f6240 T is_trans_port_sync_mode +ffffffff819f6280 T intel_crtc_bigjoiner_slave_pipes +ffffffff819f62e0 T intel_crtc_is_bigjoiner_slave +ffffffff819f6340 T intel_crtc_is_bigjoiner_master +ffffffff819f63a0 T intel_master_crtc +ffffffff819f6430 T assert_transcoder +ffffffff819f65e0 T vlv_wait_port_ready +ffffffff819f6730 T intel_enable_transcoder +ffffffff819f6a20 T intel_disable_transcoder +ffffffff819f6d20 T intel_rotation_info_size +ffffffff819f6d60 T intel_remapped_info_size +ffffffff819f6e80 T intel_plane_uses_fence +ffffffff819f6ed0 T intel_fb_xy_to_linear +ffffffff819f6f20 T intel_add_fb_offsets +ffffffff819f6f60 T intel_plane_fb_max_stride +ffffffff819f6fe0 T intel_set_plane_visible +ffffffff819f7030 T intel_plane_fixup_bitmasks +ffffffff819f70d0 T intel_plane_disable_noatomic +ffffffff819f72c0 T intel_plane_fence_y_offset +ffffffff819f7320 T intel_display_prepare_reset +ffffffff819f7500 T intel_display_finish_reset +ffffffff819f7700 t __intel_display_resume +ffffffff819f7810 T intel_modeset_init_hw +ffffffff819f78b0 T intel_has_pending_fb_unpin +ffffffff819f79a0 T intel_get_crtc_new_encoder +ffffffff819f7b30 T ilk_pfit_disable +ffffffff819f7bf0 T intel_phy_is_combo +ffffffff819f7c70 T intel_phy_is_tc +ffffffff819f7ce0 T intel_phy_is_snps +ffffffff819f7d20 T intel_port_to_phy +ffffffff819f7db0 T intel_port_to_tc +ffffffff819f7ea0 T intel_aux_power_domain +ffffffff819f7ee0 T intel_modeset_get_crtc_power_domains +ffffffff819f80f0 T intel_modeset_put_crtc_power_domains +ffffffff819f8110 T intel_display_suspend +ffffffff819f81b0 T intel_encoder_destroy +ffffffff819f81e0 T intel_encoder_get_config +ffffffff819f8210 t intel_crtc_readout_derived_state +ffffffff819f8640 T intel_link_compute_m_n +ffffffff819f8760 T intel_zero_m_n +ffffffff819f87a0 T intel_set_m_n +ffffffff819f8860 T intel_cpu_transcoder_has_m2_n2 +ffffffff819f88c0 T intel_cpu_transcoder_set_m1_n1 +ffffffff819f8a80 T intel_cpu_transcoder_set_m2_n2 +ffffffff819f8be0 T i9xx_set_pipeconf +ffffffff819f8d90 T ilk_set_pipeconf +ffffffff819f8f60 T bdw_get_pipemisc_bpp +ffffffff819f9040 T ilk_get_lanes_required +ffffffff819f90a0 T intel_get_m_n +ffffffff819f91a0 T intel_cpu_transcoder_get_m1_n1 +ffffffff819f9340 T intel_cpu_transcoder_get_m2_n2 +ffffffff819f94b0 T intel_crtc_get_pipe_config +ffffffff819f9520 T intel_get_load_detect_pipe +ffffffff819f9940 T intel_release_load_detect_pipe +ffffffff819f9a10 T i9xx_crtc_clock_get +ffffffff819f9ca0 T intel_dotclock_calculate +ffffffff819f9d00 T intel_crtc_dotclock +ffffffff819f9dd0 T intel_encoder_current_mode +ffffffff819f9f80 T intel_fuzzy_clock_check +ffffffff819f9fd0 T intel_pipe_config_compare +ffffffff819fcac0 t pipe_config_mismatch +ffffffff819fcbb0 t pipe_config_infoframe_mismatch +ffffffff819fcd60 T intel_modeset_all_pipes +ffffffff819fcf00 T intel_atomic_add_affected_planes +ffffffff819fcfd0 T intel_crtc_update_active_timings +ffffffff819fd0d0 T intel_calc_active_pipes +ffffffff819fd150 T intel_crtc_arm_fifo_underrun +ffffffff819fd1f0 T intel_plane_destroy +ffffffff819fd220 T intel_get_pipe_from_crtc_id_ioctl +ffffffff819fd290 T intel_mode_valid_max_plane_size +ffffffff819fd310 T intel_init_display_hooks +ffffffff819fd3f0 T intel_modeset_init_noirq +ffffffff819fd6a0 t intel_atomic_helper_free_state_worker +ffffffff819fd710 T intel_modeset_init_nogem +ffffffff819fe840 T intel_modeset_init +ffffffff819fea60 T i830_enable_pipe +ffffffff819ff090 T i830_disable_pipe +ffffffff819ff3b0 T intel_display_resume +ffffffff819ff4f0 T intel_modeset_driver_remove +ffffffff819ff5a0 T intel_modeset_driver_remove_noirq +ffffffff819ff710 T intel_modeset_driver_remove_nogem +ffffffff819ff740 T intel_modeset_probe_defer +ffffffff819ff770 T intel_display_driver_register +ffffffff819ff7d0 T intel_display_driver_unregister +ffffffff819ff850 T intel_scanout_needs_vtd_wa +ffffffff819ff890 t wait_for_pipe_scanline_moving +ffffffff819ffaf0 t hsw_get_pipe_config +ffffffff81a008e0 t hsw_crtc_enable +ffffffff81a01310 t hsw_crtc_disable +ffffffff81a014c0 t skl_commit_modeset_enables +ffffffff81a01a80 t intel_get_transcoder_timings +ffffffff81a01d50 t ilk_get_pfit_config +ffffffff81a01ed0 t enabled_bigjoiner_pipes +ffffffff81a020e0 t bdw_set_pipemisc +ffffffff81a02220 t ilk_pfit_enable +ffffffff81a02330 t intel_set_transcoder_timings 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intel_display_power_is_enabled +ffffffff81a0b240 T intel_display_power_set_target_dc_state +ffffffff81a0b360 T intel_display_power_get +ffffffff81a0b3e0 t __intel_display_power_get_domain +ffffffff81a0b5c0 T intel_display_power_get_if_enabled +ffffffff81a0b6f0 T __intel_display_power_put_async +ffffffff81a0b8b0 t __intel_display_power_put_domain +ffffffff81a0ba30 T intel_display_power_flush_work +ffffffff81a0bb50 t release_async_put_domains +ffffffff81a0bc30 T intel_display_power_put_unchecked +ffffffff81a0bc80 T intel_display_power_get_in_set +ffffffff81a0bd60 T intel_display_power_get_in_set_if_enabled +ffffffff81a0be10 T intel_display_power_put_mask_in_set +ffffffff81a0bee0 T intel_power_domains_init +ffffffff81a0c120 t intel_display_power_put_async_work +ffffffff81a0c390 T intel_power_domains_cleanup +ffffffff81a0c3b0 T gen9_dbuf_slices_update +ffffffff81a0c5c0 T intel_power_domains_init_hw +ffffffff81a0cd50 t icl_display_core_init +ffffffff81a0d640 t bxt_display_core_init +ffffffff81a0d770 T intel_power_domains_driver_remove +ffffffff81a0d860 T intel_power_domains_sanitize_state +ffffffff81a0d940 T intel_power_domains_enable +ffffffff81a0d990 T intel_power_domains_disable +ffffffff81a0da40 T intel_power_domains_suspend +ffffffff81a0dbd0 t icl_display_core_uninit +ffffffff81a0dc70 t bxt_display_core_uninit +ffffffff81a0dd20 T intel_power_domains_resume +ffffffff81a0ddf0 T intel_display_power_suspend_late +ffffffff81a0dee0 t hsw_enable_pc8 +ffffffff81a0e880 T intel_display_power_resume_early +ffffffff81a0e970 t hsw_disable_pc8 +ffffffff81a0edf0 T intel_display_power_suspend +ffffffff81a0ee70 T intel_display_power_resume +ffffffff81a0ef50 T intel_display_power_debug +ffffffff81a0f010 T intel_display_power_ddi_io_domain +ffffffff81a0f0f0 T intel_display_power_ddi_lanes_domain +ffffffff81a0f1d0 T intel_display_power_legacy_aux_domain +ffffffff81a0f2e0 T intel_display_power_tbt_aux_domain +ffffffff81a0f3f0 t __delayed_work_tick +ffffffff81a10000 T intel_display_power_map_init +ffffffff81a10170 t __set_power_wells +ffffffff81a10550 T intel_display_power_map_cleanup +ffffffff81a11000 T lookup_power_well +ffffffff81a110c0 T intel_power_well_enable +ffffffff81a11150 T intel_power_well_name +ffffffff81a11190 T intel_power_well_disable +ffffffff81a111f0 T intel_power_well_sync_hw +ffffffff81a11260 T intel_power_well_get +ffffffff81a112f0 T intel_power_well_put +ffffffff81a113e0 T intel_power_well_is_enabled +ffffffff81a11400 T intel_power_well_is_enabled_cached +ffffffff81a11430 T intel_display_power_well_is_enabled +ffffffff81a114f0 T intel_power_well_is_always_on +ffffffff81a11520 T intel_power_well_domains +ffffffff81a11550 T intel_power_well_refcount +ffffffff81a11580 T gen9_sanitize_dc_state +ffffffff81a11650 T gen9_set_dc_state +ffffffff81a119a0 T gen9_enable_dc5 +ffffffff81a11c00 T skl_enable_dc6 +ffffffff81a11d50 T bxt_enable_dc9 +ffffffff81a11ef0 T bxt_disable_dc9 +ffffffff81a11fd0 T gen9_disable_dc_states +ffffffff81a123a0 T chv_phy_powergate_ch +ffffffff81a124b0 t assert_chv_phy_status +ffffffff81a12850 T chv_phy_powergate_lanes +ffffffff81a12b00 t i9xx_power_well_sync_hw_noop +ffffffff81a12b30 t i9xx_always_on_power_well_noop +ffffffff81a12b60 t i9xx_always_on_power_well_enabled +ffffffff81a12b90 t chv_pipe_power_well_sync_hw +ffffffff81a12bc0 t chv_pipe_power_well_enable +ffffffff81a12bf0 t chv_pipe_power_well_disable +ffffffff81a12c50 t chv_pipe_power_well_enabled +ffffffff81a12d50 t chv_dpio_cmn_power_well_enable +ffffffff81a12f60 t chv_dpio_cmn_power_well_disable +ffffffff81a13090 t vlv_power_well_enabled +ffffffff81a131a0 t i830_pipes_power_well_sync_hw +ffffffff81a13290 t i830_pipes_power_well_enable +ffffffff81a13350 t i830_pipes_power_well_disable +ffffffff81a13380 t i830_pipes_power_well_enabled +ffffffff81a13420 t hsw_power_well_sync_hw +ffffffff81a13510 t hsw_power_well_enable +ffffffff81a13790 t hsw_power_well_disable +ffffffff81a13840 t hsw_power_well_enabled +ffffffff81a13920 t gen9_dc_off_power_well_enable +ffffffff81a13930 t gen9_dc_off_power_well_disable +ffffffff81a139d0 t gen9_dc_off_power_well_enabled +ffffffff81a13a50 t bxt_dpio_cmn_power_well_enable +ffffffff81a13a80 t bxt_dpio_cmn_power_well_disable +ffffffff81a13ab0 t bxt_dpio_cmn_power_well_enabled +ffffffff81a13ae0 t vlv_display_power_well_enable +ffffffff81a13b10 t vlv_display_power_well_disable +ffffffff81a13b80 t vlv_dpio_cmn_power_well_enable +ffffffff81a13c00 t vlv_dpio_cmn_power_well_disable +ffffffff81a13cf0 t vlv_power_well_enable +ffffffff81a13d10 t vlv_power_well_disable +ffffffff81a13d20 t icl_aux_power_well_enable +ffffffff81a143a0 t icl_aux_power_well_disable +ffffffff81a14640 t tgl_tc_cold_off_power_well_sync_hw +ffffffff81a14660 t tgl_tc_cold_off_power_well_enable +ffffffff81a14680 t tgl_tc_cold_off_power_well_disable +ffffffff81a14690 t tgl_tc_cold_off_power_well_is_enabled +ffffffff81a146c0 t xelpdp_aux_power_well_enable +ffffffff81a147a0 t xelpdp_aux_power_well_disable +ffffffff81a14870 t xelpdp_aux_power_well_enabled +ffffffff81a14920 t chv_set_pipe_power_well +ffffffff81a14b20 t vlv_display_power_well_init +ffffffff81a14db0 t vlv_set_power_well +ffffffff81a14fc0 t hsw_wait_for_power_well_enable +ffffffff81a15100 t hsw_wait_for_power_well_disable +ffffffff81a15390 t tgl_tc_cold_request +ffffffff81a16000 T intel_dkl_phy_read +ffffffff81a16100 T intel_dkl_phy_write +ffffffff81a161f0 T intel_dkl_phy_rmw +ffffffff81a16310 T intel_dkl_phy_posting_read +ffffffff81a17000 T intel_dmc_has_payload +ffffffff81a17030 T intel_dmc_load_program +ffffffff81a17810 t pipedmc_clock_gating_wa +ffffffff81a17a00 T intel_dmc_disable_program +ffffffff81a17c20 T assert_dmc_loaded +ffffffff81a17d70 T intel_dmc_ucode_init +ffffffff81a18040 t dmc_load_work_fn +ffffffff81a188a0 T intel_dmc_ucode_suspend +ffffffff81a18910 T intel_dmc_ucode_resume +ffffffff81a189a0 T intel_dmc_ucode_fini +ffffffff81a18ad0 T intel_dmc_print_error_state +ffffffff81a18b70 T intel_dmc_debugfs_register +ffffffff81a19000 T intel_dp_is_edp +ffffffff81a19030 T intel_dp_is_uhbr +ffffffff81a19060 T intel_dp_max_lane_count +ffffffff81a190c0 T intel_dp_link_required +ffffffff81a19100 T intel_dp_max_data_rate +ffffffff81a19160 T intel_dp_can_bigjoiner +ffffffff81a191b0 T intel_dp_get_link_train_fallback_values +ffffffff81a19590 T intel_dp_mode_to_fec_clock +ffffffff81a195d0 T intel_dp_min_bpp +ffffffff81a19610 T intel_dp_source_supports_tps3 +ffffffff81a19660 T intel_dp_source_supports_tps4 +ffffffff81a19690 T intel_dp_max_link_rate +ffffffff81a19750 T intel_dp_rate_select +ffffffff81a197f0 T intel_dp_compute_rate +ffffffff81a198c0 T intel_dp_adjust_compliance_config +ffffffff81a19a00 T intel_dp_limited_color_range +ffffffff81a19a70 T intel_dp_compute_psr_vsc_sdp +ffffffff81a19ae0 T intel_dp_needs_vsc_sdp +ffffffff81a19b30 t intel_dp_compute_vsc_colorimetry +ffffffff81a19cb0 T intel_dp_compute_config +ffffffff81a1a340 t intel_dp_compute_output_format +ffffffff81a1a570 T intel_dp_set_link_params +ffffffff81a1a5b0 T intel_edp_backlight_on +ffffffff81a1a660 T intel_edp_backlight_off +ffffffff81a1a710 T intel_dp_sink_set_decompression_state +ffffffff81a1a7b0 T intel_dp_wait_source_oui +ffffffff81a1a880 T intel_dp_set_power +ffffffff81a1aa90 T intel_dp_sync_state +ffffffff81a1ab10 t intel_dp_get_dpcd +ffffffff81a1ac70 t intel_dp_reset_max_link_params +ffffffff81a1ad80 T intel_dp_initial_fastset_check +ffffffff81a1ae80 T intel_dp_check_frl_training +ffffffff81a1b410 T intel_dp_pcon_dsc_configure +ffffffff81a1b5e0 T intel_dp_configure_protocol_converter +ffffffff81a1b750 T intel_dp_get_colorimetry_status +ffffffff81a1b7b0 T intel_edp_fixup_vbt_bpp +ffffffff81a1b850 T intel_write_dp_vsc_sdp +ffffffff81a1b9e0 T intel_dp_set_infoframes +ffffffff81a1bb00 t intel_write_dp_sdp +ffffffff81a1bdf0 T intel_read_dp_sdp +ffffffff81a1c120 T intel_dp_retrain_link +ffffffff81a1c7d0 T intel_dp_phy_test +ffffffff81a1ceb0 T intel_digital_port_connected +ffffffff81a1cf50 T intel_dp_encoder_flush_work +ffffffff81a1cfa0 T intel_dp_encoder_suspend +ffffffff81a1cfe0 T intel_dp_encoder_shutdown +ffffffff81a1d020 T intel_dp_hpd_pulse +ffffffff81a1d770 T intel_dp_is_port_edp +ffffffff81a1d7c0 T intel_dp_init_connector +ffffffff81a1e920 t intel_dp_modeset_retry_work_fn +ffffffff81a1e9a0 t intel_dp_set_common_rates +ffffffff81a1eb40 T intel_dp_mst_suspend +ffffffff81a1ebe0 T intel_dp_mst_resume +ffffffff81a1ec90 t intel_dp_compute_link_config +ffffffff81a1f9b0 t intel_dp_dsc_get_slice_count +ffffffff81a1fb20 t intel_dp_set_sink_rates +ffffffff81a1fd50 t intel_dp_check_device_service_irq +ffffffff81a20320 t intel_dp_force +ffffffff81a20460 t intel_dp_connector_register +ffffffff81a20540 t intel_dp_connector_unregister +ffffffff81a20590 t intel_dp_oob_hotplug_event +ffffffff81a20600 t intel_dp_set_edid +ffffffff81a20a30 t intel_dp_get_modes +ffffffff81a20b30 t intel_dp_detect +ffffffff81a21420 t intel_dp_mode_valid +ffffffff81a21bb0 t intel_dp_connector_atomic_check +ffffffff81a21ee0 t intel_dp_get_dsc_sink_cap +ffffffff81a23000 T intel_dp_aux_fini +ffffffff81a23020 T intel_dp_aux_init +ffffffff81a231f0 t xelpdp_aux_ctl_reg +ffffffff81a232b0 t xelpdp_aux_data_reg +ffffffff81a23380 t tgl_aux_ctl_reg +ffffffff81a23400 t tgl_aux_data_reg +ffffffff81a23490 t skl_aux_ctl_reg +ffffffff81a23510 t skl_aux_data_reg +ffffffff81a235a0 t ilk_aux_ctl_reg +ffffffff81a23620 t ilk_aux_data_reg +ffffffff81a236a0 t g4x_aux_ctl_reg +ffffffff81a23720 t g4x_aux_data_reg +ffffffff81a237b0 t skl_get_aux_clock_divider +ffffffff81a237e0 t hsw_get_aux_clock_divider +ffffffff81a23880 t ilk_get_aux_clock_divider +ffffffff81a238e0 t g4x_get_aux_clock_divider +ffffffff81a23930 t skl_get_aux_send_ctl +ffffffff81a239a0 t g4x_get_aux_send_ctl +ffffffff81a239f0 t kasprintf +ffffffff81a23ac0 t intel_dp_aux_transfer +ffffffff81a23d10 t intel_dp_aux_xfer +ffffffff81a25000 T intel_dp_aux_init_backlight_funcs +ffffffff81a25270 t intel_dp_aux_hdr_setup_backlight +ffffffff81a253c0 t intel_dp_aux_hdr_get_backlight +ffffffff81a25530 t intel_dp_aux_hdr_set_backlight +ffffffff81a25620 t intel_dp_aux_hdr_disable_backlight +ffffffff81a256a0 t intel_dp_aux_hdr_enable_backlight +ffffffff81a258e0 t intel_dp_aux_vesa_setup_backlight +ffffffff81a25aa0 t intel_dp_aux_vesa_get_backlight +ffffffff81a25ad0 t intel_dp_aux_vesa_set_backlight +ffffffff81a25b70 t intel_dp_aux_vesa_disable_backlight +ffffffff81a25c20 t intel_dp_aux_vesa_enable_backlight +ffffffff81a26000 T intel_dp_hdcp_init +ffffffff81a260b0 t intel_dp_hdcp_write_an_aksv +ffffffff81a261a0 t intel_dp_hdcp_read_bksv +ffffffff81a26230 t intel_dp_hdcp_read_bstatus +ffffffff81a262c0 t intel_dp_hdcp_repeater_present +ffffffff81a26360 t intel_dp_hdcp_read_ri_prime +ffffffff81a263f0 t intel_dp_hdcp_read_ksv_ready +ffffffff81a26490 t intel_dp_hdcp_read_ksv_fifo +ffffffff81a26580 t intel_dp_hdcp_read_v_prime_part +ffffffff81a26620 t intel_dp_hdcp_toggle_signalling +ffffffff81a26650 t intel_dp_mst_hdcp_stream_encryption +ffffffff81a26850 t intel_dp_hdcp_check_link +ffffffff81a268d0 t intel_dp_hdcp_capable +ffffffff81a26970 t intel_dp_hdcp2_capable +ffffffff81a269f0 t intel_dp_hdcp2_write_msg +ffffffff81a26ab0 t intel_dp_hdcp2_read_msg +ffffffff81a27180 t intel_dp_hdcp2_config_stream_type +ffffffff81a27230 t intel_dp_mst_hdcp2_stream_encryption +ffffffff81a274b0 t intel_dp_mst_hdcp2_check_link +ffffffff81a27570 t get_hdcp2_dp_msg_data +ffffffff81a276b0 t intel_dp_hdcp2_check_link +ffffffff81a28000 T intel_dp_init_lttpr_and_dprx_caps +ffffffff81a282a0 T intel_dp_get_adjust_train +ffffffff81a28960 T intel_dp_program_link_training_pattern +ffffffff81a28a50 T intel_dp_set_signal_levels +ffffffff81a28db0 T intel_dp_dump_link_status +ffffffff81a28e80 T intel_dp_stop_link_train +ffffffff81a290b0 T intel_dp_start_link_train +ffffffff81a2a1f0 t intel_dp_link_train_phy +ffffffff81a2c000 T intel_dp_mst_encoder_active_links +ffffffff81a2c030 T intel_dp_mst_encoder_init +ffffffff81a2c270 T intel_dp_mst_source_support +ffffffff81a2c2a0 T intel_dp_mst_encoder_cleanup +ffffffff81a2c2f0 T intel_dp_mst_is_master_trans +ffffffff81a2c330 T intel_dp_mst_is_slave_trans +ffffffff81a2c370 T intel_dp_mst_add_topology_state_for_crtc +ffffffff81a2c440 t intel_dp_add_mst_connector +ffffffff81a2c650 t intel_dp_mst_poll_hpd_irq +ffffffff81a2c670 t intel_dp_mst_get_hw_state +ffffffff81a2c6d0 t intel_dp_mst_connector_late_register +ffffffff81a2c740 t intel_dp_mst_connector_early_unregister +ffffffff81a2c770 t intel_dp_mst_get_modes +ffffffff81a2c810 t intel_dp_mst_detect +ffffffff81a2c900 t intel_dp_mst_mode_valid_ctx +ffffffff81a2ca50 t intel_mst_atomic_best_encoder +ffffffff81a2caa0 t intel_dp_mst_atomic_check +ffffffff81a2cc20 t intel_dp_mst_compute_config +ffffffff81a2cf30 t intel_dp_mst_compute_config_late +ffffffff81a2d020 t intel_mst_disable_dp +ffffffff81a2d0d0 t intel_mst_post_disable_dp +ffffffff81a2d390 t intel_mst_pre_pll_enable_dp +ffffffff81a2d3e0 t intel_mst_pre_enable_dp +ffffffff81a2d600 t intel_mst_enable_dp +ffffffff81a2d9f0 t intel_dp_mst_enc_get_hw_state +ffffffff81a2da30 t intel_dp_mst_enc_get_config +ffffffff81a2da50 t intel_dp_mst_initial_fastset_check +ffffffff81a2da70 t intel_dp_mst_encoder_destroy +ffffffff81a2e000 T bxt_port_to_phy_channel +ffffffff81a2e130 T bxt_ddi_phy_set_signal_levels +ffffffff81a2e650 T bxt_ddi_phy_is_enabled +ffffffff81a2e7a0 T bxt_ddi_phy_uninit +ffffffff81a2e890 T bxt_ddi_phy_init +ffffffff81a2eac0 t _bxt_ddi_phy_init +ffffffff81a2f0e0 T bxt_ddi_phy_verify_state +ffffffff81a2f420 t __phy_reg_verify_state +ffffffff81a2f520 T bxt_ddi_phy_calc_lane_lat_optim_mask +ffffffff81a2f590 T bxt_ddi_phy_set_lane_optim_mask +ffffffff81a2f8b0 T bxt_ddi_phy_get_lane_lat_optim_mask +ffffffff81a2fb00 T chv_set_phy_signal_level +ffffffff81a2fe60 T chv_data_lane_soft_reset +ffffffff81a30040 T chv_phy_pre_pll_enable +ffffffff81a302d0 T chv_phy_pre_encoder_enable +ffffffff81a30560 T chv_phy_release_cl2_override +ffffffff81a305f0 T chv_phy_post_pll_disable +ffffffff81a306a0 T vlv_set_phy_signal_level +ffffffff81a30820 T vlv_phy_pre_pll_enable +ffffffff81a30930 T vlv_phy_pre_encoder_enable +ffffffff81a30a40 T vlv_phy_reset_lanes +ffffffff81a31000 T pnv_calc_dpll_params +ffffffff81a310b0 T i9xx_calc_dpll_params +ffffffff81a31180 T vlv_calc_dpll_params +ffffffff81a31230 T chv_calc_dpll_params +ffffffff81a31300 T bxt_find_best_dpll +ffffffff81a31320 t chv_find_best_dpll +ffffffff81a31660 T i9xx_dpll_compute_fp +ffffffff81a316a0 T vlv_compute_dpll +ffffffff81a31720 T chv_compute_dpll +ffffffff81a317a0 T intel_dpll_crtc_compute_clock +ffffffff81a31890 T intel_dpll_crtc_get_shared_dpll +ffffffff81a319e0 T intel_dpll_init_clock_hook +ffffffff81a31ad0 T i9xx_enable_pll +ffffffff81a31e80 T vlv_enable_pll +ffffffff81a323e0 T chv_enable_pll +ffffffff81a32a50 T vlv_force_pll_on +ffffffff81a32ba0 T vlv_disable_pll +ffffffff81a32c60 T chv_disable_pll +ffffffff81a32d90 T i9xx_disable_pll +ffffffff81a32e90 T vlv_force_pll_off +ffffffff81a32f80 T assert_pll_enabled +ffffffff81a33060 T assert_pll_disabled +ffffffff81a33140 t intel_pll_is_valid +ffffffff81a33210 t dg2_crtc_compute_clock +ffffffff81a33290 t hsw_crtc_compute_clock +ffffffff81a33350 t hsw_crtc_get_shared_dpll +ffffffff81a333f0 t ilk_crtc_compute_clock +ffffffff81a336e0 t ilk_crtc_get_shared_dpll +ffffffff81a33730 t g4x_find_best_dpll +ffffffff81a33a70 t chv_crtc_compute_clock +ffffffff81a33b70 t vlv_crtc_compute_clock +ffffffff81a34020 t g4x_crtc_compute_clock +ffffffff81a34170 t i9xx_compute_dpll +ffffffff81a343f0 t pnv_crtc_compute_clock +ffffffff81a347a0 t i9xx_crtc_compute_clock +ffffffff81a348c0 t i9xx_find_best_dpll +ffffffff81a34bf0 t i8xx_crtc_compute_clock +ffffffff81a35000 T intel_get_shared_dpll_by_id +ffffffff81a35040 T intel_get_shared_dpll_id +ffffffff81a350d0 T assert_shared_dpll +ffffffff81a351f0 T intel_dpll_get_hw_state +ffffffff81a35210 T icl_tc_port_to_pll_id +ffffffff81a35240 T intel_enable_shared_dpll +ffffffff81a35530 T intel_disable_shared_dpll +ffffffff81a35760 T intel_shared_dpll_swap_state +ffffffff81a35840 T icl_set_active_port_dpll +ffffffff81a35880 T intel_shared_dpll_init +ffffffff81a35a90 T intel_compute_shared_dplls +ffffffff81a35b20 T intel_reserve_shared_dplls +ffffffff81a35bb0 T intel_release_shared_dplls +ffffffff81a35bf0 T intel_update_active_dpll +ffffffff81a35c50 T intel_dpll_get_freq +ffffffff81a35ce0 T intel_dpll_update_ref_clks +ffffffff81a35d20 T intel_dpll_readout_hw_state +ffffffff81a35ea0 T intel_dpll_sanitize_state +ffffffff81a35f80 T intel_dpll_dump_hw_state +ffffffff81a36000 T intel_shared_dpll_state_verify +ffffffff81a36120 t verify_single_dpll_state +ffffffff81a36440 T intel_shared_dpll_verify_disabled +ffffffff81a364b0 t icl_compute_dplls +ffffffff81a37290 t icl_get_dplls +ffffffff81a37a00 t icl_put_dplls +ffffffff81a37ac0 t icl_update_active_dpll +ffffffff81a37b60 t icl_update_dpll_ref_clks +ffffffff81a37b90 t icl_dump_hw_state +ffffffff81a37c50 t combo_pll_enable +ffffffff81a37e70 t combo_pll_disable +ffffffff81a37f60 t combo_pll_get_hw_state +ffffffff81a37ff0 t icl_ddi_combo_pll_get_freq +ffffffff81a381c0 t icl_dpll_write +ffffffff81a38460 t adlp_cmtg_clock_gating_wa +ffffffff81a385c0 t icl_pll_disable +ffffffff81a38760 t icl_pll_get_hw_state +ffffffff81a38aa0 t tbt_pll_enable +ffffffff81a38c50 t tbt_pll_disable +ffffffff81a38c70 t tbt_pll_get_hw_state +ffffffff81a38c90 t icl_ddi_tbt_pll_get_freq +ffffffff81a38d00 t mg_pll_enable +ffffffff81a392b0 t mg_pll_disable +ffffffff81a392f0 t dkl_pll_get_hw_state +ffffffff81a394c0 t icl_ddi_mg_pll_get_freq +ffffffff81a39590 t intel_find_shared_dpll +ffffffff81a398c0 t intel_unreference_shared_dpll +ffffffff81a39a20 t mg_pll_get_hw_state +ffffffff81a39c60 t bxt_compute_dpll +ffffffff81a39f80 t bxt_get_dpll +ffffffff81a3a1e0 t intel_put_dpll +ffffffff81a3a240 t bxt_update_dpll_ref_clks +ffffffff81a3a280 t bxt_dump_hw_state +ffffffff81a3a330 t bxt_ddi_pll_enable +ffffffff81a3ae30 t bxt_ddi_pll_disable +ffffffff81a3b040 t bxt_ddi_pll_get_hw_state +ffffffff81a3b4d0 t bxt_ddi_pll_get_freq +ffffffff81a3b560 t bxt_ddi_set_dpll_hw_state +ffffffff81a3b720 t skl_compute_dpll +ffffffff81a3bea0 t skl_get_dpll +ffffffff81a3c0d0 t skl_update_dpll_ref_clks +ffffffff81a3c100 t skl_dump_hw_state +ffffffff81a3c160 t skl_ddi_dpll0_enable +ffffffff81a3c220 t skl_ddi_dpll0_disable +ffffffff81a3c250 t skl_ddi_dpll0_get_hw_state +ffffffff81a3c350 t skl_ddi_pll_get_freq +ffffffff81a3c3e0 t skl_ddi_wrpll_get_freq +ffffffff81a3c540 t skl_ddi_pll_enable +ffffffff81a3c750 t skl_ddi_pll_disable +ffffffff81a3c7e0 t skl_ddi_pll_get_hw_state +ffffffff81a3c900 t hsw_compute_dpll +ffffffff81a3d150 t hsw_get_dpll +ffffffff81a3d410 t hsw_update_dpll_ref_clks +ffffffff81a3d480 t hsw_dump_hw_state +ffffffff81a3d4b0 t hsw_ddi_wrpll_enable +ffffffff81a3d530 t hsw_ddi_wrpll_disable +ffffffff81a3d610 t hsw_ddi_wrpll_get_hw_state +ffffffff81a3d6b0 t hsw_ddi_wrpll_get_freq +ffffffff81a3d7a0 t hsw_ddi_spll_enable +ffffffff81a3d800 t hsw_ddi_spll_disable +ffffffff81a3d8d0 t hsw_ddi_spll_get_hw_state +ffffffff81a3d950 t hsw_ddi_spll_get_freq +ffffffff81a3d9e0 t hsw_ddi_lcpll_enable +ffffffff81a3da10 t hsw_ddi_lcpll_disable +ffffffff81a3da40 t hsw_ddi_lcpll_get_hw_state +ffffffff81a3da70 t hsw_ddi_lcpll_get_freq +ffffffff81a3daf0 t ibx_compute_dpll +ffffffff81a3db20 t ibx_get_dpll +ffffffff81a3dda0 t ibx_dump_hw_state +ffffffff81a3de00 t ibx_pch_dpll_enable +ffffffff81a3dfb0 t ibx_pch_dpll_disable +ffffffff81a3e030 t ibx_pch_dpll_get_hw_state +ffffffff81a3f000 T intel_dpt_pin +ffffffff81a3f1d0 T intel_dpt_unpin +ffffffff81a3f240 T intel_dpt_resume +ffffffff81a3f310 T intel_dpt_suspend +ffffffff81a3f3e0 T intel_dpt_create +ffffffff81a3f710 t dpt_insert_page +ffffffff81a3f780 t dpt_clear_range +ffffffff81a3f7b0 t dpt_insert_entries +ffffffff81a3f8b0 t dpt_cleanup +ffffffff81a3f900 t dpt_bind_vma +ffffffff81a3f990 t dpt_unbind_vma +ffffffff81a3f9c0 T intel_dpt_destroy +ffffffff81a3fa00 t __ww_mutex_lock +ffffffff81a40000 T intel_drrs_type_str +ffffffff81a40040 T intel_drrs_is_active +ffffffff81a40070 T intel_drrs_activate +ffffffff81a40270 T intel_drrs_deactivate +ffffffff81a40350 t intel_drrs_set_state +ffffffff81a404a0 T intel_drrs_invalidate +ffffffff81a404b0 t intel_drrs_frontbuffer_update +ffffffff81a40610 T intel_drrs_flush +ffffffff81a40620 T intel_crtc_drrs_init +ffffffff81a406c0 t intel_drrs_downclock_work +ffffffff81a40710 t __delayed_work_tick +ffffffff81a41000 T intel_dsb_indexed_reg_write +ffffffff81a41130 T intel_dsb_reg_write +ffffffff81a41210 T intel_dsb_commit +ffffffff81a41650 T intel_dsb_prepare +ffffffff81a417e0 T intel_dsb_cleanup +ffffffff81a42000 T intel_dsi_bitrate +ffffffff81a42090 T intel_dsi_tlpx_ns +ffffffff81a420e0 T intel_dsi_get_modes +ffffffff81a420f0 T intel_dsi_mode_valid +ffffffff81a421b0 T intel_dsi_host_init +ffffffff81a42260 T intel_dsi_get_panel_orientation +ffffffff81a43000 T intel_dsi_dcs_init_backlight_funcs +ffffffff81a43090 t dcs_setup_backlight +ffffffff81a430f0 t dcs_get_backlight +ffffffff81a431e0 t dcs_set_backlight +ffffffff81a432c0 t dcs_disable_backlight +ffffffff81a43630 t dcs_enable_backlight +ffffffff81a44000 T intel_dsi_vbt_exec_sequence +ffffffff81a44020 T intel_dsi_msleep +ffffffff81a44090 T intel_dsi_log_params +ffffffff81a44410 T intel_dsi_vbt_init +ffffffff81a448a0 T intel_dsi_vbt_gpio_init +ffffffff81a448c0 T intel_dsi_vbt_gpio_cleanup +ffffffff81a45000 T intel_dvo_init +ffffffff81a454f0 t intel_disable_dvo +ffffffff81a455a0 t intel_enable_dvo +ffffffff81a45680 t intel_dvo_get_hw_state +ffffffff81a456e0 t intel_dvo_get_config +ffffffff81a45780 t intel_dvo_compute_config +ffffffff81a45800 t intel_dvo_pre_enable +ffffffff81a458f0 t intel_dvo_connector_get_hw_state +ffffffff81a45970 t intel_dvo_enc_destroy +ffffffff81a459b0 t intel_dvo_detect +ffffffff81a45ab0 t intel_dvo_get_modes +ffffffff81a45b10 t intel_dvo_mode_valid +ffffffff81a46000 T intel_fb_get_format_info +ffffffff81a46230 T intel_fb_is_ccs_modifier +ffffffff81a46400 T intel_fb_is_rc_ccs_cc_modifier +ffffffff81a465d0 T intel_fb_is_mc_ccs_modifier +ffffffff81a467a0 T intel_fb_plane_get_modifiers +ffffffff81a468e0 T intel_fb_plane_supports_modifier +ffffffff81a46940 T intel_format_info_is_yuv_semiplanar +ffffffff81a46be0 T intel_fb_is_ccs_aux_plane +ffffffff81a46e20 T intel_fb_rc_ccs_cc_plane +ffffffff81a47080 T is_surface_linear +ffffffff81a473b0 T main_to_ccs_plane +ffffffff81a47690 T skl_ccs_to_main_plane +ffffffff81a47970 T skl_main_to_aux_plane +ffffffff81a47bd0 T intel_tile_size +ffffffff81a47c10 T intel_tile_width_bytes +ffffffff81a47e60 T intel_tile_height +ffffffff81a47ec0 T intel_tile_row_size +ffffffff81a47f40 T intel_fb_align_height +ffffffff81a47fb0 T intel_fb_uses_dpt +ffffffff81a48000 T intel_cursor_alignment +ffffffff81a48060 T intel_surf_alignment +ffffffff81a48270 T intel_fb_plane_get_subsampling +ffffffff81a48640 T intel_plane_adjust_aligned_offset +ffffffff81a486b0 t intel_adjust_aligned_offset +ffffffff81a48860 T intel_plane_compute_aligned_offset +ffffffff81a48960 t intel_compute_aligned_offset +ffffffff81a48b20 T intel_fb_needs_pot_stride_remap +ffffffff81a48b60 T intel_fb_supports_90_270_rotation +ffffffff81a48bb0 T intel_fill_fb_info +ffffffff81a497f0 t calc_plane_remap_info +ffffffff81a4a250 T intel_fb_fill_view +ffffffff81a4a2a0 T intel_plane_compute_gtt +ffffffff81a4ab70 t intel_plane_check_stride +ffffffff81a4aee0 T intel_framebuffer_init +ffffffff81a4c2f0 T intel_user_framebuffer_create +ffffffff81a4c430 T intel_framebuffer_create +ffffffff81a4c4c0 t intel_adjust_tile_offset +ffffffff81a4c600 t intel_user_framebuffer_destroy +ffffffff81a4c660 t intel_user_framebuffer_create_handle +ffffffff81a4c680 t intel_user_framebuffer_dirty +ffffffff81a4d000 T intel_pin_and_fence_fb_obj +ffffffff81a4d310 t i915_gem_object_lock +ffffffff81a4d520 T intel_unpin_fb_vma +ffffffff81a4d590 T intel_plane_pin_fb +ffffffff81a4d8c0 T intel_plane_unpin_fb +ffffffff81a4e000 T intel_fbc_cleanup +ffffffff81a4e1c0 T intel_fbc_pre_update +ffffffff81a4e810 T intel_fbc_post_update +ffffffff81a4ea60 T intel_fbc_invalidate +ffffffff81a4ec80 T intel_fbc_flush +ffffffff81a4ef00 T intel_fbc_atomic_check +ffffffff81a4f470 T intel_fbc_disable +ffffffff81a4f530 t __intel_fbc_disable +ffffffff81a4f6c0 T intel_fbc_update +ffffffff81a4fd80 T intel_fbc_reset_underrun +ffffffff81a4fee0 T intel_fbc_handle_fifo_underrun_irq +ffffffff81a4ff90 T intel_fbc_add_plane +ffffffff81a4ffc0 T intel_fbc_init +ffffffff81a50240 T intel_fbc_sanitize +ffffffff81a50310 T intel_fbc_crtc_debugfs_add +ffffffff81a50340 T intel_fbc_debugfs_register +ffffffff81a50370 t intel_fbc_is_ok +ffffffff81a50490 t intel_fbc_update_state +ffffffff81a50800 t intel_fbc_underrun_work_fn +ffffffff81a50920 t ivb_fbc_activate +ffffffff81a50b80 t ilk_fbc_deactivate +ffffffff81a50c30 t ilk_fbc_is_active +ffffffff81a50c90 t ivb_fbc_is_compressing +ffffffff81a50cf0 t snb_fbc_nuke +ffffffff81a50d60 t ilk_fbc_program_cfb +ffffffff81a50da0 t ivb_fbc_set_false_color +ffffffff81a50e60 t snb_fbc_activate +ffffffff81a50ee0 t ilk_fbc_is_compressing +ffffffff81a50f40 t ilk_fbc_activate +ffffffff81a51070 t i965_fbc_nuke +ffffffff81a51110 t g4x_fbc_activate +ffffffff81a51220 t g4x_fbc_deactivate +ffffffff81a512b0 t g4x_fbc_is_active +ffffffff81a51300 t g4x_fbc_is_compressing +ffffffff81a51360 t g4x_fbc_program_cfb +ffffffff81a51390 t i8xx_fbc_activate +ffffffff81a51500 t i8xx_fbc_deactivate +ffffffff81a515d0 t i8xx_fbc_is_active +ffffffff81a51620 t i8xx_fbc_is_compressing +ffffffff81a51680 t i8xx_fbc_program_cfb +ffffffff81a51700 t i8xx_fbc_nuke +ffffffff81a52000 T intel_fbdev_init +ffffffff81a524d0 t intel_fbdev_suspend_worker +ffffffff81a52500 T intel_fbdev_initial_config_async +ffffffff81a52570 T intel_fbdev_unregister +ffffffff81a525b0 T intel_fbdev_set_suspend +ffffffff81a525e0 T intel_fbdev_fini +ffffffff81a52670 T intel_fbdev_output_poll_changed +ffffffff81a52710 T intel_fbdev_restore_mode +ffffffff81a52790 T intel_fbdev_framebuffer +ffffffff81a527c0 t intelfb_create +ffffffff81a52dc0 t intel_fbdev_set_par +ffffffff81a53000 T assert_fdi_tx_enabled +ffffffff81a530e0 T assert_fdi_tx_disabled +ffffffff81a531c0 T assert_fdi_rx_enabled +ffffffff81a53270 T assert_fdi_rx_disabled +ffffffff81a53320 T assert_fdi_tx_pll_enabled +ffffffff81a533d0 T assert_fdi_rx_pll_enabled +ffffffff81a53490 T assert_fdi_rx_pll_disabled +ffffffff81a53550 T intel_fdi_link_train +ffffffff81a53570 T intel_fdi_pll_freq_update +ffffffff81a53620 T intel_fdi_link_freq +ffffffff81a53660 T ilk_fdi_compute_config +ffffffff81a53990 T intel_fdi_normal_train +ffffffff81a53b10 T hsw_fdi_link_train +ffffffff81a54010 T hsw_fdi_disable +ffffffff81a54170 T ilk_fdi_pll_enable +ffffffff81a54380 T ilk_fdi_pll_disable +ffffffff81a544b0 T ilk_fdi_disable +ffffffff81a54720 T intel_fdi_init_hook +ffffffff81a54780 t ilk_fdi_link_train +ffffffff81a54df0 t gen6_fdi_link_train +ffffffff81a55620 t ivb_manual_fdi_link_train +ffffffff81a55eb0 t cpt_set_fdi_bc_bifurcation +ffffffff81a57000 T intel_set_cpu_fifo_underrun_reporting +ffffffff81a573e0 T intel_set_pch_fifo_underrun_reporting +ffffffff81a57610 T intel_cpu_fifo_underrun_irq_handler +ffffffff81a57800 T intel_pch_fifo_underrun_irq_handler +ffffffff81a57880 T intel_check_cpu_fifo_underruns +ffffffff81a57aa0 T intel_check_pch_fifo_underruns +ffffffff81a58000 T intel_frontbuffer_flip_prepare +ffffffff81a58050 T intel_frontbuffer_flip_complete +ffffffff81a58120 T intel_frontbuffer_flip +ffffffff81a581f0 T __intel_fb_invalidate +ffffffff81a58280 T __intel_fb_flush +ffffffff81a58370 T intel_frontbuffer_get +ffffffff81a584a0 t frontbuffer_active +ffffffff81a584d0 t frontbuffer_retire +ffffffff81a58510 T intel_frontbuffer_put +ffffffff81a58690 T intel_frontbuffer_track +ffffffff81a59000 T intel_atomic_global_obj_init +ffffffff81a59070 T intel_atomic_global_obj_cleanup +ffffffff81a59170 T intel_atomic_get_global_obj_state +ffffffff81a593e0 T intel_atomic_get_old_global_obj_state +ffffffff81a59440 T intel_atomic_get_new_global_obj_state +ffffffff81a594a0 T intel_atomic_swap_global_state +ffffffff81a595f0 T intel_atomic_clear_global_state +ffffffff81a59720 T intel_atomic_lock_global_state +ffffffff81a597a0 T intel_atomic_serialize_global_state +ffffffff81a5a000 T intel_gmbus_is_valid_pin +ffffffff81a5a100 T intel_gmbus_reset +ffffffff81a5a160 T intel_bb_set_bits +ffffffff81a5a290 T intel_bb_set_dir +ffffffff81a5a2c0 T intel_bb_read_bits +ffffffff81a5a440 T intel_acquire_bus +ffffffff81a5a630 T intel_release_bus +ffffffff81a5a7d0 T intel_send_start +ffffffff81a5a7f0 T intel_send_stop +ffffffff81a5a810 T intel_initiate_xfer +ffffffff81a5a830 T intel_read_byte +ffffffff81a5a850 T intel_write_byte +ffffffff81a5a870 T intel_gmbus_output_aksv +ffffffff81a5a940 t do_gmbus_xfer +ffffffff81a5af40 T intel_gmbus_setup +ffffffff81a5b2d0 T intel_gmbus_teardown +ffffffff81a5b340 T intel_gmbus_get_adapter +ffffffff81a5b3c0 T intel_gmbus_force_bit +ffffffff81a5b450 T intel_gmbus_is_forced_bit +ffffffff81a5b480 t gmbus_xfer_read +ffffffff81a5b750 t gmbus_xfer_write +ffffffff81a5b9a0 t gmbus_wait +ffffffff81a5bd80 t gmbus_wait_idle +ffffffff81a5bf20 t gmbus_xfer +ffffffff81a5bff0 t gmbus_func +ffffffff81a5c030 t gmbus_lock_bus +ffffffff81a5c050 t gmbus_trylock_bus +ffffffff81a5c0a0 t gmbus_unlock_bus +ffffffff81a5d000 T intel_hdcp_capable +ffffffff81a5d0a0 t intel_hdcp_read_valid_bksv +ffffffff81a5d320 T intel_hdcp2_capable +ffffffff81a5d400 T is_hdcp_supported +ffffffff81a5d450 T intel_hdcp_component_init +ffffffff81a5d480 T intel_hdcp_init +ffffffff81a5d5b0 t intel_hdcp_check_work +ffffffff81a614b0 t intel_hdcp_prop_work +ffffffff81a61530 T intel_hdcp_enable +ffffffff81a61580 T intel_hdcp_disable +ffffffff81a616b0 t intel_hdcp_update_value +ffffffff81a61870 t _intel_hdcp2_disable +ffffffff81a61c70 t _intel_hdcp_disable +ffffffff81a61f70 T intel_hdcp_update_pipe +ffffffff81a620e0 T intel_hdcp_component_fini +ffffffff81a62120 T intel_hdcp_cleanup +ffffffff81a62260 T intel_hdcp_atomic_check +ffffffff81a622f0 T intel_hdcp_handle_cp_irq +ffffffff81a623f0 t __delayed_work_tick +ffffffff81a62410 t hdcp2_authenticate_repeater_topology +ffffffff81a626f0 t intel_hdcp_get_repeater_ctl +ffffffff81a63000 T hsw_write_infoframe +ffffffff81a63410 t hsw_dip_data_reg +ffffffff81a635d0 T hsw_read_infoframe +ffffffff81a63680 T intel_hdmi_infoframe_enable +ffffffff81a63720 T intel_hdmi_infoframes_enabled +ffffffff81a63830 T intel_read_infoframe +ffffffff81a639c0 T intel_hdmi_read_gcp_infoframe +ffffffff81a63ab0 T intel_dp_dual_mode_set_tmds_output +ffffffff81a63b80 T intel_hdmi_tmds_clock +ffffffff81a63bd0 T intel_hdmi_bpc_possible +ffffffff81a63d00 T intel_hdmi_limited_color_range +ffffffff81a63d70 T intel_hdmi_compute_config +ffffffff81a644c0 t intel_hdmi_compute_output_format +ffffffff81a645f0 T intel_hdmi_encoder_shutdown +ffffffff81a646c0 T intel_hdmi_handle_sink_scrambling +ffffffff81a647e0 T intel_infoframe_init +ffffffff81a64960 t vlv_write_infoframe +ffffffff81a64cc0 t vlv_read_infoframe +ffffffff81a64e90 t vlv_set_infoframes +ffffffff81a65230 t vlv_infoframes_enabled +ffffffff81a652d0 t g4x_write_infoframe +ffffffff81a65580 t g4x_read_infoframe +ffffffff81a656d0 t g4x_set_infoframes +ffffffff81a65970 t g4x_infoframes_enabled +ffffffff81a659e0 t hsw_set_infoframes +ffffffff81a65c80 t hsw_infoframes_enabled +ffffffff81a65d10 t ibx_write_infoframe +ffffffff81a66020 t ibx_read_infoframe +ffffffff81a66190 t ibx_set_infoframes +ffffffff81a66500 t ibx_infoframes_enabled +ffffffff81a66580 t cpt_write_infoframe +ffffffff81a66880 t cpt_read_infoframe +ffffffff81a669f0 t cpt_set_infoframes +ffffffff81a66cf0 t cpt_infoframes_enabled +ffffffff81a66d60 T intel_hdmi_init_connector +ffffffff81a673f0 T intel_hdmi_dsc_get_slice_height +ffffffff81a67440 T intel_hdmi_dsc_get_num_slices +ffffffff81a675c0 T intel_hdmi_dsc_get_bpp +ffffffff81a676b0 t intel_hdmi_compute_clock +ffffffff81a67970 t hdmi_port_clock_valid +ffffffff81a67ba0 t intel_write_infoframe +ffffffff81a67d70 t intel_hdmi_detect +ffffffff81a67f20 t intel_hdmi_force +ffffffff81a68000 t intel_hdmi_connector_register +ffffffff81a68010 t intel_hdmi_connector_unregister +ffffffff81a68020 t intel_hdmi_set_edid +ffffffff81a682c0 t intel_hdmi_get_modes +ffffffff81a68300 t intel_hdmi_mode_valid +ffffffff81a684a0 t intel_hdmi_mode_clock_valid +ffffffff81a68630 t intel_hdmi_hdcp_write_an_aksv +ffffffff81a68780 t intel_hdmi_hdcp_read_bksv +ffffffff81a68850 t intel_hdmi_hdcp_read_bstatus +ffffffff81a68920 t intel_hdmi_hdcp_repeater_present +ffffffff81a68a00 t intel_hdmi_hdcp_read_ri_prime +ffffffff81a68ad0 t intel_hdmi_hdcp_read_ksv_ready +ffffffff81a68bb0 t intel_hdmi_hdcp_read_ksv_fifo +ffffffff81a68c80 t intel_hdmi_hdcp_read_v_prime_part +ffffffff81a68d70 t intel_hdmi_hdcp_toggle_signalling +ffffffff81a68ff0 t intel_hdmi_hdcp_check_link +ffffffff81a69340 t intel_hdmi_hdcp2_capable +ffffffff81a693f0 t intel_hdmi_hdcp2_write_msg +ffffffff81a694d0 t intel_hdmi_hdcp2_read_msg +ffffffff81a69960 t intel_hdmi_hdcp2_check_link +ffffffff81a6a000 T intel_hpd_pin_default +ffffffff81a6a030 T intel_encoder_hotplug +ffffffff81a6a160 T intel_hpd_trigger_irq +ffffffff81a6a1d0 T intel_hpd_irq_handler +ffffffff81a6a5b0 T intel_hpd_init +ffffffff81a6a6c0 T intel_hpd_poll_enable +ffffffff81a6a740 T intel_hpd_poll_disable +ffffffff81a6a790 T intel_hpd_init_work +ffffffff81a6a860 t i915_hotplug_work_func +ffffffff81a6aba0 t i915_digport_work_func +ffffffff81a6ad30 t i915_hpd_poll_init_work +ffffffff81a6ae30 t intel_hpd_irq_storm_reenable_work +ffffffff81a6b170 T intel_hpd_cancel_work +ffffffff81a6b290 T intel_hpd_disable +ffffffff81a6b310 T intel_hpd_enable +ffffffff81a6b380 t __delayed_work_tick +ffffffff81a6c000 T intel_lpe_audio_irq_handler +ffffffff81a6c020 T intel_lpe_audio_init +ffffffff81a6c050 T intel_lpe_audio_teardown +ffffffff81a6c070 T intel_lpe_audio_notify +ffffffff81a6d000 T lspcon_detect_hdr_capability +ffffffff81a6d0a0 T lspcon_write_infoframe +ffffffff81a6d820 T lspcon_read_infoframe +ffffffff81a6d860 T lspcon_set_infoframes +ffffffff81a6dad0 T lspcon_infoframes_enabled +ffffffff81a6dcc0 T lspcon_wait_pcon_mode +ffffffff81a6dcd0 t lspcon_wait_mode +ffffffff81a6df90 T lspcon_init +ffffffff81a6e3a0 T intel_lspcon_infoframes_enabled +ffffffff81a6e3e0 T lspcon_resume +ffffffff81a6e690 t lspcon_change_mode +ffffffff81a6f000 T intel_lvds_port_enabled +ffffffff81a6f080 T intel_get_lvds_encoder +ffffffff81a6f0e0 T intel_is_dual_link_lvds +ffffffff81a6f150 T intel_lvds_init +ffffffff81a6f8c0 t intel_enable_lvds +ffffffff81a6fa00 t intel_pre_enable_lvds +ffffffff81a6fcd0 t intel_lvds_compute_config +ffffffff81a6fe30 t pch_disable_lvds +ffffffff81a6fe50 t pch_post_disable_lvds +ffffffff81a6fe70 t gmch_disable_lvds +ffffffff81a6fea0 t intel_lvds_get_hw_state +ffffffff81a6ff60 t intel_lvds_get_config +ffffffff81a70060 t intel_lvds_shutdown +ffffffff81a70100 t intel_no_lvds_dmi_callback +ffffffff81a70150 t intel_disable_lvds +ffffffff81a70280 t intel_lvds_get_modes +ffffffff81a702b0 t intel_lvds_mode_valid +ffffffff81a70330 t intel_dual_link_lvds_callback +ffffffff81a71000 T intel_modeset_setup_hw_state +ffffffff81a73000 T intel_modeset_verify_crtc +ffffffff81a733b0 t verify_connector_state +ffffffff81a73660 T intel_modeset_verify_disabled +ffffffff81a74000 T intel_opregion_notify_encoder +ffffffff81a74160 t swsci +ffffffff81a74490 T intel_opregion_notify_adapter +ffffffff81a744e0 T intel_opregion_asle_intr +ffffffff81a74530 T intel_opregion_setup +ffffffff81a74d40 t asle_work +ffffffff81a751c0 T intel_opregion_get_panel_type +ffffffff81a752a0 T intel_opregion_get_edid +ffffffff81a75380 T intel_opregion_headless_sku +ffffffff81a753d0 T intel_opregion_register +ffffffff81a75460 T intel_opregion_resume +ffffffff81a754f0 T intel_opregion_suspend +ffffffff81a75590 T intel_opregion_unregister +ffffffff81a75710 t intel_no_opregion_vbt_callback +ffffffff81a75760 t intel_use_opregion_panel_type_callback +ffffffff81a76000 T intel_overlay_reset +ffffffff81a76050 T intel_overlay_switch_off +ffffffff81a76240 t intel_overlay_release_old_vid +ffffffff81a763e0 T intel_overlay_put_image_ioctl +ffffffff81a775a0 T intel_overlay_attrs_ioctl +ffffffff81a77a40 T intel_overlay_setup +ffffffff81a77c90 t intel_overlay_last_flip_retire +ffffffff81a77cd0 T intel_overlay_cleanup +ffffffff81a77d90 T intel_overlay_capture_error_state +ffffffff81a77e70 T intel_overlay_print_error_state +ffffffff81a78240 t intel_overlay_release_old_vid_tail +ffffffff81a78310 t intel_overlay_off_tail +ffffffff81a784b0 t intel_overlay_flip_prepare +ffffffff81a79000 T intel_panel_use_ssc +ffffffff81a79060 T intel_panel_preferred_fixed_mode +ffffffff81a790a0 T intel_panel_fixed_mode +ffffffff81a79160 T intel_panel_downclock_mode +ffffffff81a79240 T intel_panel_highest_mode +ffffffff81a792a0 T intel_panel_get_modes +ffffffff81a79330 T intel_panel_drrs_type +ffffffff81a79380 T intel_panel_compute_config +ffffffff81a79500 T intel_panel_add_edid_fixed_modes +ffffffff81a79a30 T intel_panel_add_vbt_lfp_fixed_mode +ffffffff81a79a90 t intel_panel_add_fixed_mode +ffffffff81a79c10 T intel_panel_add_vbt_sdvo_fixed_mode +ffffffff81a79c70 T intel_panel_add_encoder_fixed_mode +ffffffff81a79cb0 T intel_panel_fitting +ffffffff81a7a300 T intel_panel_detect +ffffffff81a7a390 T intel_panel_mode_valid +ffffffff81a7a4a0 T intel_panel_init_alloc +ffffffff81a7a4f0 T intel_panel_init +ffffffff81a7a5b0 T intel_panel_fini +ffffffff81a7b000 T intel_has_pch_trancoder +ffffffff81a7b050 T intel_crtc_pch_transcoder +ffffffff81a7b090 T intel_pch_transcoder_get_m1_n1 +ffffffff81a7b0d0 T intel_pch_transcoder_get_m2_n2 +ffffffff81a7b110 T ilk_pch_pre_enable +ffffffff81a7b130 T ilk_pch_enable +ffffffff81a7b6d0 t ilk_pch_transcoder_set_timings +ffffffff81a7b950 T ilk_pch_disable +ffffffff81a7b960 T ilk_pch_post_disable +ffffffff81a7bc90 T ilk_pch_get_config +ffffffff81a7be50 T lpt_pch_enable +ffffffff81a7c080 T lpt_pch_disable +ffffffff81a7c190 T lpt_pch_get_config +ffffffff81a7c260 T intel_pch_sanitize +ffffffff81a7c530 t assert_pch_dp_disabled +ffffffff81a7c620 t assert_pch_hdmi_disabled +ffffffff81a7d000 T lpt_disable_iclkip +ffffffff81a7d070 T lpt_iclkip +ffffffff81a7d0f0 T lpt_program_iclkip +ffffffff81a7d370 T lpt_get_iclkip +ffffffff81a7d480 T lpt_disable_clkout_dp +ffffffff81a7d550 T intel_init_pch_refclk +ffffffff81a7f000 T intel_crtc_initial_plane_config +ffffffff81a80000 T intel_pps_lock +ffffffff81a80060 T intel_pps_unlock +ffffffff81a800b0 T intel_pps_reset_all +ffffffff81a80200 T intel_pps_check_power_unlocked +ffffffff81a803c0 T intel_pps_wait_power_cycle +ffffffff81a80580 T intel_pps_vdd_on_unlocked +ffffffff81a80ab0 T intel_pps_vdd_on +ffffffff81a80ba0 T intel_pps_vdd_off_sync +ffffffff81a80c70 t intel_pps_vdd_off_sync_unlocked +ffffffff81a80f50 T intel_pps_vdd_off_unlocked +ffffffff81a81060 T intel_pps_on_unlocked +ffffffff81a81460 T intel_pps_on +ffffffff81a81500 T intel_pps_off_unlocked +ffffffff81a81750 T intel_pps_off +ffffffff81a817f0 T intel_pps_backlight_on +ffffffff81a81a00 T intel_pps_backlight_off +ffffffff81a81c10 T intel_pps_backlight_power +ffffffff81a81de0 T vlv_pps_init +ffffffff81a81f40 t vlv_detach_power_sequencer +ffffffff81a820c0 t vlv_steal_power_sequencer +ffffffff81a821f0 t pps_init_delays +ffffffff81a82660 t pps_init_registers +ffffffff81a82a00 T intel_pps_have_panel_power_or_vdd +ffffffff81a82b50 T intel_pps_encoder_reset +ffffffff81a82ce0 t vlv_initial_power_sequencer_setup +ffffffff81a82f90 t pps_vdd_init +ffffffff81a830a0 T intel_pps_init +ffffffff81a83210 t edp_panel_vdd_work +ffffffff81a832c0 T intel_pps_init_late +ffffffff81a83430 T intel_pps_unlock_regs_wa +ffffffff81a83520 T intel_pps_setup +ffffffff81a83590 T assert_pps_unlocked +ffffffff81a837d0 t intel_pps_get_registers +ffffffff81a83ea0 t wait_panel_status +ffffffff81a84170 t intel_pps_readout_hw_state +ffffffff81a84330 t __delayed_work_tick +ffffffff81a85000 T intel_psr_irq_handler +ffffffff81a85680 T intel_psr_init_dpcd +ffffffff81a85910 T intel_psr_compute_config +ffffffff81a861c0 T intel_psr_get_config +ffffffff81a86370 T intel_psr_disable +ffffffff81a86480 t intel_psr_disable_locked +ffffffff81a868f0 T intel_psr_pause +ffffffff81a86ae0 t intel_psr_exit +ffffffff81a86dc0 T intel_psr_resume +ffffffff81a86e50 t intel_psr_activate +ffffffff81a875f0 T intel_psr2_disable_plane_sel_fetch +ffffffff81a87660 T intel_psr2_program_plane_sel_fetch +ffffffff81a87810 T intel_psr2_program_trans_man_trk_ctl +ffffffff81a87950 T intel_psr2_sel_fetch_update +ffffffff81a87fe0 T intel_psr_pre_plane_update +ffffffff81a881b0 T intel_psr_post_plane_update +ffffffff81a88c30 T intel_psr_wait_for_idle_locked +ffffffff81a88e10 T intel_psr_debug_set +ffffffff81a89040 t psr_irq_control +ffffffff81a89190 T intel_psr_invalidate +ffffffff81a89440 T intel_psr_flush +ffffffff81a89910 T intel_psr_init +ffffffff81a89a40 t intel_psr_work +ffffffff81a89be0 t tgl_dc3co_disable_work +ffffffff81a89c30 T intel_psr_short_pulse +ffffffff81a89ff0 T intel_psr_enabled +ffffffff81a8a070 T intel_psr_lock +ffffffff81a8a150 T intel_psr_unlock +ffffffff81a8a230 t tgl_psr2_disable_dc3co +ffffffff81a8a360 t __delayed_work_tick +ffffffff81a8b000 T intel_lookup_range_min_qp +ffffffff81a8b0b0 T intel_lookup_range_max_qp +ffffffff81a8c000 T intel_init_quirks +ffffffff81a8c0f0 T intel_has_quirk +ffffffff81a8c120 t quirk_ssc_force_disable +ffffffff81a8c150 t quirk_invert_brightness +ffffffff81a8c180 t quirk_backlight_present +ffffffff81a8c1b0 t quirk_increase_t12_delay +ffffffff81a8c1e0 t quirk_increase_ddi_disabled_time +ffffffff81a8c210 t intel_dmi_reverse_brightness +ffffffff81a8c260 t intel_dmi_no_pps_backlight +ffffffff81a8d000 T intel_sdvo_port_enabled +ffffffff81a8d0a0 T intel_sdvo_init +ffffffff81a8dc70 t intel_sdvo_compute_config +ffffffff81a8e1d0 t pch_disable_sdvo +ffffffff81a8e200 t pch_post_disable_sdvo +ffffffff81a8e210 t intel_disable_sdvo +ffffffff81a8e380 t intel_sdvo_pre_enable +ffffffff81a8ed00 t intel_enable_sdvo +ffffffff81a8ef00 t intel_sdvo_get_hw_state +ffffffff81a8eff0 t intel_sdvo_get_config +ffffffff81a8f560 t intel_sdvo_ddc_proxy_xfer +ffffffff81a8f600 t intel_sdvo_ddc_proxy_func +ffffffff81a8f630 t __intel_sdvo_write_cmd +ffffffff81a8faf0 t proxy_lock_bus +ffffffff81a8fb20 t proxy_trylock_bus +ffffffff81a8fb50 t proxy_unlock_bus +ffffffff81a8fb80 t intel_sdvo_enc_destroy +ffffffff81a8fb90 t intel_sdvo_get_preferred_input_mode +ffffffff81a8ff20 t intel_sdvo_get_dtd_from_mode +ffffffff81a90090 t intel_sdvo_read_response +ffffffff81a90530 t intel_sdvo_write_sdvox +ffffffff81a90720 t intel_sdvo_write_infoframe +ffffffff81a908f0 t intel_sdvo_dvi_init +ffffffff81a90b80 t intel_sdvo_tv_init +ffffffff81a90ea0 t intel_sdvo_lvds_init +ffffffff81a91090 t intel_sdvo_hotplug +ffffffff81a910d0 t intel_sdvo_connector_get_hw_state +ffffffff81a91160 t intel_sdvo_detect +ffffffff81a914d0 t intel_sdvo_connector_register +ffffffff81a914e0 t intel_sdvo_connector_unregister +ffffffff81a914f0 t intel_sdvo_connector_duplicate_state +ffffffff81a91570 t intel_sdvo_connector_atomic_set_property +ffffffff81a91740 t intel_sdvo_connector_atomic_get_property +ffffffff81a91960 t intel_sdvo_get_modes +ffffffff81a91c20 t intel_sdvo_mode_valid +ffffffff81a91cf0 t intel_sdvo_atomic_check +ffffffff81a91da0 t intel_sdvo_create_enhance_property +ffffffff81a93000 T intel_snps_phy_wait_for_calibration +ffffffff81a930d0 T intel_snps_phy_update_psr_power_state +ffffffff81a931a0 T intel_snps_phy_set_signal_levels +ffffffff81a933e0 T intel_mpllb_calc_state +ffffffff81a93550 T intel_snps_phy_check_hdmi_link_rate +ffffffff81a935b0 T intel_mpllb_enable +ffffffff81a93810 T intel_mpllb_disable +ffffffff81a939a0 T intel_mpllb_calc_port_clock +ffffffff81a93a60 T intel_mpllb_readout_hw_state +ffffffff81a93bc0 T intel_mpllb_state_verify +ffffffff81a95000 T intel_plane_check_src_coordinates +ffffffff81a951c0 T vlv_plane_min_cdclk +ffffffff81a952a0 T ivb_plane_min_cdclk +ffffffff81a95360 T hsw_plane_min_cdclk +ffffffff81a953f0 T chv_plane_check_rotation +ffffffff81a95460 T intel_sprite_set_colorkey_ioctl +ffffffff81a95730 T intel_sprite_plane_create +ffffffff81a95a80 t vlv_sprite_update_noarm +ffffffff81a95b70 t vlv_sprite_update_arm +ffffffff81a96230 t vlv_sprite_disable_arm +ffffffff81a962c0 t vlv_sprite_get_hw_state +ffffffff81a96380 t vlv_sprite_check +ffffffff81a96610 t ivb_sprite_update_noarm +ffffffff81a96770 t ivb_sprite_update_arm +ffffffff81a96b50 t ivb_sprite_disable_arm +ffffffff81a96c00 t ivb_sprite_get_hw_state +ffffffff81a96cb0 t g4x_sprite_check +ffffffff81a97270 t hsw_sprite_max_stride +ffffffff81a972c0 t g4x_sprite_max_stride +ffffffff81a97330 t ivb_sprite_min_cdclk +ffffffff81a97460 t g4x_sprite_update_noarm +ffffffff81a975d0 t g4x_sprite_update_arm +ffffffff81a97a10 t g4x_sprite_disable_arm +ffffffff81a97ac0 t g4x_sprite_get_hw_state +ffffffff81a97b70 t g4x_sprite_min_cdclk +ffffffff81a97c30 t vlv_sprite_format_mod_supported +ffffffff81a97d60 t snb_sprite_format_mod_supported +ffffffff81a97e40 t g4x_sprite_format_mod_supported +ffffffff81a98000 T intel_tc_port_in_tbt_alt_mode +ffffffff81a98070 T intel_tc_port_in_dp_alt_mode +ffffffff81a980e0 T intel_tc_port_in_legacy_mode +ffffffff81a98150 T intel_tc_cold_requires_aux_pw +ffffffff81a981a0 T intel_tc_port_get_lane_mask +ffffffff81a98300 T intel_tc_port_get_pin_assignment_mask +ffffffff81a98460 T intel_tc_port_fia_max_lane_count +ffffffff81a98590 T intel_tc_port_set_fia_lane_count +ffffffff81a987a0 T intel_tc_port_sanitize +ffffffff81a98df0 T intel_tc_port_connected +ffffffff81a98ee0 T intel_tc_port_lock +ffffffff81a98f00 t tc_port_live_status_mask +ffffffff81a991d0 T intel_tc_port_unlock +ffffffff81a99250 t __intel_tc_port_lock +ffffffff81a99450 T intel_tc_port_flush_work +ffffffff81a99470 T intel_tc_port_ref_held +ffffffff81a994c0 T intel_tc_port_get_link +ffffffff81a99540 T intel_tc_port_put_link +ffffffff81a995d0 T intel_tc_port_init +ffffffff81a99860 t intel_tc_port_disconnect_phy_work +ffffffff81a998b0 t tc_phy_status_complete +ffffffff81a999c0 t tc_phy_take_ownership +ffffffff81a99b60 t intel_tc_port_update_mode +ffffffff81a9a080 t __delayed_work_tick +ffffffff81a9b000 T intel_tv_init +ffffffff81a9b420 t intel_tv_compute_config +ffffffff81a9b8c0 t intel_tv_get_config +ffffffff81a9be60 t intel_tv_pre_enable +ffffffff81a9c790 t intel_enable_tv +ffffffff81a9c7f0 t intel_disable_tv +ffffffff81a9c850 t intel_tv_get_hw_state +ffffffff81a9c8b0 t intel_tv_connector_duplicate_state +ffffffff81a9c930 t intel_tv_mode_to_mode +ffffffff81a9ca80 t intel_tv_get_modes +ffffffff81a9cde0 t intel_tv_detect +ffffffff81a9d240 t intel_tv_mode_valid +ffffffff81a9d2d0 t intel_tv_atomic_check +ffffffff81a9e000 T intel_dsc_source_support +ffffffff81a9e050 T intel_dsc_compute_params +ffffffff81a9e510 T intel_dsc_power_domain +ffffffff81a9e5c0 T intel_dsc_dsi_pps_write +ffffffff81a9e860 T intel_dsc_dp_pps_write +ffffffff81a9e940 T intel_uncompressed_joiner_enable +ffffffff81a9ea50 T intel_dsc_enable +ffffffff81aa0320 T intel_dsc_disable +ffffffff81aa04a0 T intel_dsc_get_config +ffffffff81aa1000 T intel_vga_disable +ffffffff81aa1120 T intel_vga_redisable_power_on +ffffffff81aa11c0 T intel_vga_redisable +ffffffff81aa1280 T intel_vga_reset_io_mem +ffffffff81aa12d0 T intel_vga_register +ffffffff81aa1300 T intel_vga_unregister +ffffffff81aa2000 T intel_vrr_is_capable +ffffffff81aa20a0 T intel_vrr_check_modeset +ffffffff81aa2130 T intel_vrr_vmin_vblank_start +ffffffff81aa2190 T intel_vrr_vmax_vblank_start +ffffffff81aa21f0 T intel_vrr_compute_config +ffffffff81aa2380 T intel_vrr_enable +ffffffff81aa2550 T intel_vrr_send_push +ffffffff81aa25d0 T intel_vrr_is_push_sent +ffffffff81aa2660 T intel_vrr_disable +ffffffff81aa2730 T intel_vrr_get_config +ffffffff81aa3000 T skl_update_scaler_crtc +ffffffff81aa30c0 t skl_update_scaler +ffffffff81aa3370 T skl_update_scaler_plane +ffffffff81aa3760 T skl_pfit_enable +ffffffff81aa3c40 T skl_program_plane_scaler +ffffffff81aa4300 T skl_detach_scalers +ffffffff81aa4440 T skl_scaler_disable +ffffffff81aa5000 T skl_format_to_fourcc +ffffffff81aa5170 T icl_is_nv12_y_plane +ffffffff81aa51e0 T icl_is_hdr_plane +ffffffff81aa5220 T skl_calc_main_surface_offset +ffffffff81aa5460 T skl_universal_plane_create +ffffffff81aa5b50 t icl_plane_min_width +ffffffff81aa5ce0 t icl_hdr_plane_max_width +ffffffff81aa5d30 t icl_sdr_plane_max_width +ffffffff81aa5d60 t icl_plane_max_height +ffffffff81aa5d90 t icl_plane_min_cdclk +ffffffff81aa5dd0 t glk_plane_max_width +ffffffff81aa5e80 t skl_plane_max_height +ffffffff81aa5eb0 t glk_plane_min_cdclk +ffffffff81aa5f30 t skl_plane_max_width +ffffffff81aa6000 t skl_plane_min_cdclk +ffffffff81aa6060 t skl_plane_max_stride +ffffffff81aa60f0 t icl_plane_update_noarm +ffffffff81aa6ab0 t icl_plane_update_arm +ffffffff81aa6c10 t icl_plane_disable_arm +ffffffff81aa6d20 t skl_plane_update_noarm +ffffffff81aa6ec0 t skl_plane_update_arm +ffffffff81aa72c0 t skl_plane_disable_arm +ffffffff81aa7370 t skl_plane_get_hw_state +ffffffff81aa7430 t skl_plane_check +ffffffff81aa8860 t skl_plane_async_flip +ffffffff81aa8980 t skl_plane_enable_flip_done +ffffffff81aa89e0 t skl_plane_disable_flip_done +ffffffff81aa8a40 T skl_get_initial_plane_config +ffffffff81aa90e0 t skl_surf_address +ffffffff81aa9200 t skl_check_main_ccs_coordinates +ffffffff81aa93a0 t gen12_plane_format_mod_supported +ffffffff81aa95f0 t skl_plane_format_mod_supported +ffffffff81aaa000 T intel_enabled_dbuf_slices_mask +ffffffff81aaa130 T intel_sagv_pre_plane_update +ffffffff81aaa2a0 T intel_sagv_post_plane_update +ffffffff81aaa4f0 T intel_can_enable_sagv +ffffffff81aaa560 T skl_ddb_dbuf_slice_mask +ffffffff81aaa610 T skl_write_plane_wm +ffffffff81aaa9e0 T skl_write_cursor_wm +ffffffff81aaad30 T skl_ddb_allocation_overlaps +ffffffff81aaadc0 T skl_wm_get_hw_state +ffffffff81aab3b0 t skl_pipe_wm_get_hw_state +ffffffff81aab740 t skl_compute_dbuf_slices +ffffffff81aabc70 T skl_wm_sanitize +ffffffff81aabec0 T intel_wm_state_verify +ffffffff81aac7e0 T skl_watermark_ipc_enabled +ffffffff81aac810 T skl_watermark_ipc_update +ffffffff81aac8c0 T skl_watermark_ipc_init +ffffffff81aac9c0 T skl_wm_init +ffffffff81aacff0 T intel_atomic_get_dbuf_state +ffffffff81aad010 T intel_dbuf_init +ffffffff81aad080 T intel_dbuf_pre_plane_update +ffffffff81aad350 T intel_dbuf_post_plane_update +ffffffff81aad420 T intel_mbus_dbox_update +ffffffff81aad690 T skl_watermark_ipc_debugfs_register +ffffffff81aad6c0 t skl_sagv_disable +ffffffff81aad7e0 t skl_ddb_entry_for_slices +ffffffff81aad920 t skl_compute_wm +ffffffff81ab0760 t skl_build_plane_wm_single +ffffffff81ab0a90 t skl_compute_wm_params +ffffffff81ab0e80 t skl_compute_plane_wm +ffffffff81ab1360 t intel_dbuf_duplicate_state +ffffffff81ab13f0 t intel_dbuf_destroy_state +ffffffff81ab2000 T pixel_format_from_register_bits +ffffffff81ab2060 T vlv_dsi_wait_for_fifo_empty +ffffffff81ab2120 T vlv_dsi_init +ffffffff81ab2980 t intel_dsi_compute_config +ffffffff81ab2ad0 t intel_dsi_pre_enable +ffffffff81ab4750 t bxt_dsi_enable +ffffffff81ab47b0 t intel_dsi_disable +ffffffff81ab4a60 t intel_dsi_post_disable +ffffffff81ab5740 t intel_dsi_get_hw_state +ffffffff81ab59f0 t intel_dsi_get_config +ffffffff81ab61b0 t intel_dsi_shutdown +ffffffff81ab62a0 t intel_dsi_encoder_destroy +ffffffff81ab62c0 t intel_dsi_prepare +ffffffff81ab6f10 t dpi_send_cmd +ffffffff81ab70a0 t intel_dsi_host_attach +ffffffff81ab70d0 t intel_dsi_host_detach +ffffffff81ab7100 t intel_dsi_host_transfer +ffffffff81ab8000 T vlv_dsi_pll_compute +ffffffff81ab8390 t vlv_dsi_pclk +ffffffff81ab8540 T vlv_dsi_pll_enable +ffffffff81ab8760 T vlv_dsi_pll_disable +ffffffff81ab87d0 T bxt_dsi_pll_is_enabled +ffffffff81ab88a0 T bxt_dsi_pll_disable +ffffffff81ab89a0 T vlv_dsi_get_pclk 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reset_fail_worker_func +ffffffff81b51a30 t guc_timestamp_ping +ffffffff81b51c50 T intel_guc_deregister_done_process_msg +ffffffff81b51fb0 t register_context +ffffffff81b52910 T intel_guc_sched_done_process_msg +ffffffff81b52cc0 T intel_guc_context_reset_process_msg +ffffffff81b52f00 T intel_guc_error_capture_process_msg +ffffffff81b52fb0 T intel_guc_lookup_engine +ffffffff81b52ff0 T intel_guc_engine_failure_process_msg +ffffffff81b53170 T intel_guc_find_hung_context +ffffffff81b53340 T intel_guc_dump_active_requests +ffffffff81b534d0 T intel_guc_submission_print_info +ffffffff81b53610 T intel_guc_submission_print_context_info +ffffffff81b53a40 t emit_bb_start_parent_no_preempt_mid_batch +ffffffff81b53b60 T intel_guc_virtual_engine_has_heartbeat +ffffffff81b53bf0 t guc_virtual_get_sibling +ffffffff81b53c90 t update_context_prio +ffffffff81b53e80 t try_context_registration +ffffffff81b54300 t guc_wq_item_append +ffffffff81b54580 t guc_add_request +ffffffff81b547c0 t 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ilk_enable_vblank +ffffffff81b77d70 T bdw_enable_vblank +ffffffff81b77f20 T i8xx_disable_vblank +ffffffff81b78020 T i915gm_disable_vblank +ffffffff81b78090 T i965_disable_vblank +ffffffff81b78190 T ilk_disable_vblank +ffffffff81b78290 T bdw_disable_vblank +ffffffff81b78410 T gen8_irq_power_well_post_enable +ffffffff81b78590 T gen8_irq_power_well_pre_disable +ffffffff81b78720 T intel_synchronize_irq +ffffffff81b78740 T valleyview_enable_display_irqs +ffffffff81b787b0 t vlv_display_irq_reset +ffffffff81b78970 t vlv_display_irq_postinstall +ffffffff81b78bc0 T valleyview_disable_display_irqs +ffffffff81b78c10 T intel_hpd_irq_setup +ffffffff81b78c50 T intel_irq_init +ffffffff81b78f00 t ivb_parity_work +ffffffff81b79290 T intel_irq_fini +ffffffff81b792d0 T intel_irq_install +ffffffff81b793d0 t intel_irq_reset +ffffffff81b79f30 t intel_irq_postinstall +ffffffff81b7ac30 T intel_irq_uninstall +ffffffff81b7ac90 T intel_runtime_pm_disable_interrupts +ffffffff81b7acc0 T intel_runtime_pm_enable_interrupts +ffffffff81b7acf0 T intel_synchronize_hardirq +ffffffff81b7ad10 t i9xx_pipestat_irq_reset +ffffffff81b7aea0 t kasprintf +ffffffff81b7af70 t i915_hpd_irq_setup +ffffffff81b7b080 t icp_hpd_irq_setup +ffffffff81b7b270 t dg1_hpd_irq_setup +ffffffff81b7b2d0 t gen11_hpd_irq_setup +ffffffff81b7b520 t bxt_hpd_irq_setup +ffffffff81b7b6b0 t bdw_update_port_irq +ffffffff81b7b7f0 t spt_hpd_irq_setup +ffffffff81b7ba00 t ilk_hpd_irq_setup +ffffffff81b7bc60 t gen11_display_irq_reset +ffffffff81b7c1e0 t ibx_irq_reset +ffffffff81b7c320 t cherryview_irq_handler +ffffffff81b7c5f0 t valleyview_irq_handler +ffffffff81b7c950 t i965_irq_handler +ffffffff81b7cec0 t i915_irq_handler +ffffffff81b7d3a0 t i8xx_irq_handler +ffffffff81b7d7a0 t dg1_irq_handler +ffffffff81b7d950 t gen11_irq_handler +ffffffff81b7daa0 t gen8_irq_handler +ffffffff81b7db80 t ilk_irq_handler +ffffffff81b7ea40 t i9xx_pipestat_irq_ack +ffffffff81b7ebc0 t i9xx_hpd_irq_handler +ffffffff81b7ede0 t valleyview_pipestat_irq_handler +ffffffff81b7eff0 t i9xx_pipe_crc_irq_handler +ffffffff81b7f140 t gen8_de_irq_handler +ffffffff81b80590 t cpt_irq_handler +ffffffff81b809d0 t ibx_hpd_irq_handler +ffffffff81b80b70 t gen8_de_irq_postinstall +ffffffff81b82000 T i915_memcpy_from_wc +ffffffff81b82120 T i915_unaligned_memcpy_from_wc +ffffffff81b82240 T i915_memcpy_init_early +ffffffff81b83000 T i915_mitigate_clear_residuals +ffffffff81b84000 T i915_init +ffffffff81b84240 t i915_check_nomodeset +ffffffff81b842c0 t i915_mock_selftests +ffffffff81b842f0 t i915_pmu_init +ffffffff81b84320 t i915_pmu_exit +ffffffff81b85000 T i915_params_dump +ffffffff81b88120 T i915_params_copy +ffffffff81b88ff0 T i915_params_free +ffffffff81b8a000 T i915_pci_register_driver +ffffffff81b8a030 T i915_pci_unregister_driver +ffffffff81b8b000 T i915_oa_config_release +ffffffff81b8b060 T i915_perf_get_oa_config +ffffffff81b8b0b0 T i915_oa_init_reg_state +ffffffff81b8b1c0 T i915_perf_open_ioctl +ffffffff81b8b710 T i915_perf_register +ffffffff81b8b740 T i915_perf_unregister +ffffffff81b8b7b0 T i915_perf_add_config_ioctl +ffffffff81b8b800 T i915_perf_remove_config_ioctl +ffffffff81b8b880 T i915_perf_init +ffffffff81b8bc00 t gen7_is_valid_b_counter_addr +ffffffff81b8bc50 t hsw_is_valid_mux_addr +ffffffff81b8bcd0 t hsw_enable_metric_set +ffffffff81b8bdb0 t hsw_disable_metric_set +ffffffff81b8bec0 t gen7_oa_enable +ffffffff81b8c020 t gen7_oa_disable +ffffffff81b8c0e0 t gen7_oa_read +ffffffff81b8c640 t gen7_oa_hw_tail_read +ffffffff81b8c690 t gen8_oa_read +ffffffff81b8ccc0 t gen8_is_valid_mux_addr +ffffffff81b8cd40 t gen8_is_valid_flex_addr +ffffffff81b8cdc0 t chv_is_valid_mux_addr +ffffffff81b8ce40 t gen8_oa_enable +ffffffff81b8cf80 t gen8_oa_disable +ffffffff81b8d040 t gen8_enable_metric_set +ffffffff81b8d0f0 t gen8_disable_metric_set +ffffffff81b8d180 t gen8_oa_hw_tail_read +ffffffff81b8d1d0 t gen11_is_valid_mux_addr +ffffffff81b8d290 t gen11_disable_metric_set +ffffffff81b8d320 t gen12_is_valid_b_counter_addr +ffffffff81b8d370 t gen12_is_valid_mux_addr +ffffffff81b8d3c0 t gen12_oa_enable +ffffffff81b8d540 t gen12_oa_disable +ffffffff81b8d680 t gen12_enable_metric_set +ffffffff81b8d7b0 t gen12_disable_metric_set +ffffffff81b8d880 t gen12_oa_hw_tail_read +ffffffff81b8d8d0 T i915_perf_sysctl_register +ffffffff81b8d900 T i915_perf_sysctl_unregister +ffffffff81b8d920 T i915_perf_fini +ffffffff81b8da00 t destroy_config +ffffffff81b8da90 T i915_perf_ioctl_version +ffffffff81b8dac0 t emit_oa_config +ffffffff81b8e1a0 t i915_gem_object_lock +ffffffff81b8e3b0 t lrc_configure_all_contexts +ffffffff81b8e570 t oa_configure_all_contexts +ffffffff81b8e890 t gen8_modify_self +ffffffff81b8ea60 t gen8_modify_context +ffffffff81b8ec00 t gen12_configure_oar_context +ffffffff81b8f000 T i915_query_ioctl +ffffffff81b8f110 t query_topology_info +ffffffff81b8f150 t query_engine_info +ffffffff81b8f390 t query_perf_config +ffffffff81b8f680 t query_memregion_info +ffffffff81b8f900 t query_hwconfig_blob +ffffffff81b8f980 t query_geometry_subslices +ffffffff81b8fa10 t fill_topology_info +ffffffff81b8fbb0 t query_perf_config_data +ffffffff81b91000 T i915_request_slab_cache +ffffffff81b91030 t i915_fence_get_driver_name +ffffffff81b91060 t i915_fence_get_timeline_name +ffffffff81b910b0 t i915_fence_enable_signaling +ffffffff81b910c0 t i915_fence_signaled +ffffffff81b91110 t i915_fence_wait +ffffffff81b91130 t i915_fence_release +ffffffff81b91220 T i915_request_notify_execute_cb_imm +ffffffff81b91280 T i915_request_active_engine +ffffffff81b91360 T i915_request_free_capture_list +ffffffff81b913c0 T i915_request_retire +ffffffff81b91580 T i915_request_retire_upto +ffffffff81b915f0 T __i915_request_skip +ffffffff81b91680 T i915_request_set_error_once +ffffffff81b916f0 T i915_request_mark_eio +ffffffff81b91780 T __i915_request_submit +ffffffff81b919d0 T i915_request_submit +ffffffff81b91a10 T __i915_request_unsubmit +ffffffff81b91a80 T i915_request_unsubmit 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i915_save_display +ffffffff81b96360 T i915_restore_display +ffffffff81b97000 T i915_sw_fence_complete +ffffffff81b97040 t __i915_sw_fence_complete +ffffffff81b971c0 T i915_sw_fence_await +ffffffff81b97230 T __i915_sw_fence_init +ffffffff81b972a0 T i915_sw_fence_reinit +ffffffff81b972d0 T i915_sw_fence_commit +ffffffff81b97310 T i915_sw_fence_await_sw_fence +ffffffff81b97320 t __i915_sw_fence_await_sw_fence +ffffffff81b975c0 T i915_sw_fence_await_sw_fence_gfp +ffffffff81b975e0 T i915_sw_fence_await_dma_fence +ffffffff81b97800 t dma_i915_sw_fence_wake +ffffffff81b97870 t irq_i915_sw_fence_work +ffffffff81b978b0 t timer_i915_sw_fence_wake +ffffffff81b97990 t dma_i915_sw_fence_wake_timer +ffffffff81b97a10 T __i915_sw_fence_await_dma_fence +ffffffff81b97b60 t __dma_i915_sw_fence_wake +ffffffff81b97bc0 T i915_sw_fence_await_reservation +ffffffff81b97ca0 t i915_sw_fence_wake +ffffffff81b98000 T dma_fence_work_init +ffffffff81b98080 t fence_notify +ffffffff81b98170 t fence_work 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i915_ttm_buddy_man_debug +ffffffff81b9d000 T i915_user_extensions +ffffffff81b9e000 T __i915_printk +ffffffff81b9e0b0 T add_taint_for_CI +ffffffff81b9e0e0 T cancel_timer +ffffffff81b9e120 T set_timer_ms +ffffffff81b9e1d0 T i915_vtd_active +ffffffff81b9f000 T intel_vgpu_detect +ffffffff81b9f030 T intel_vgpu_register +ffffffff81b9f080 T intel_vgpu_active +ffffffff81b9f0b0 T intel_vgpu_has_full_ppgtt +ffffffff81b9f0e0 T intel_vgpu_has_hwsp_emulation +ffffffff81b9f110 T intel_vgpu_has_huge_gtt +ffffffff81b9f140 T intel_vgt_deballoon +ffffffff81b9f380 T intel_vgt_balloon +ffffffff81ba0000 T i915_vma_instance +ffffffff81ba05a0 T i915_vma_work +ffffffff81ba0610 T i915_vma_wait_for_bind +ffffffff81ba0680 T i915_vma_bind +ffffffff81ba09d0 T i915_vma_pin_iomap +ffffffff81ba0ba0 T i915_vma_flush_writes +ffffffff81ba0c10 T i915_vma_unpin_iomap +ffffffff81ba0c90 T i915_vma_unpin_and_release +ffffffff81ba0d00 T i915_vma_misplaced +ffffffff81ba0da0 T __i915_vma_set_map_and_fenceable +ffffffff81ba0e20 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intel_detect_pch +ffffffff81ba9310 t intel_pch_match +ffffffff81ba9360 t intel_pch_type +ffffffff81baa000 T snb_pcode_read +ffffffff81baa0d0 t __snb_pcode_rw +ffffffff81baa260 T snb_pcode_write_timeout +ffffffff81baa330 T skl_pcode_request +ffffffff81baa670 T intel_pcode_init +ffffffff81baa6d0 T snb_pcode_read_p +ffffffff81baa7d0 T snb_pcode_write_p +ffffffff81bab000 T intel_set_memory_cxsr +ffffffff81bab090 t _intel_set_memory_cxsr +ffffffff81bab340 T intel_wm_plane_visible +ffffffff81bab390 T ilk_wm_max_level +ffffffff81bab400 T intel_print_wm_latency +ffffffff81bab550 T ilk_disable_lp_wm +ffffffff81bab630 T g4x_wm_get_hw_state +ffffffff81babe00 T g4x_wm_sanitize +ffffffff81babf90 t g4x_program_watermarks +ffffffff81bac330 T vlv_wm_get_hw_state +ffffffff81bacff0 t vlv_invalidate_wms +ffffffff81bad150 T vlv_wm_sanitize +ffffffff81bad2a0 t vlv_program_watermarks +ffffffff81bad9f0 T ilk_wm_get_hw_state +ffffffff81bade60 T intel_init_clock_gating +ffffffff81bade80 T intel_suspend_hw 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vlv_init_clock_gating +ffffffff81bb0c80 t gen6_init_clock_gating +ffffffff81bb0e80 t ilk_init_clock_gating +ffffffff81bb1050 t g4x_init_clock_gating +ffffffff81bb1100 t i965gm_init_clock_gating +ffffffff81bb11d0 t i965g_init_clock_gating +ffffffff81bb1240 t gen3_init_clock_gating +ffffffff81bb1330 t i85x_init_clock_gating +ffffffff81bb13d0 t i830_init_clock_gating +ffffffff81bb1400 t nop_init_clock_gating +ffffffff81bb1420 t ilk_compute_pipe_wm +ffffffff81bb1890 t ilk_compute_intermediate_wm +ffffffff81bb1bb0 t ilk_initial_watermarks +ffffffff81bb1c20 t ilk_optimize_watermarks +ffffffff81bb1cd0 t ilk_compute_wm_level +ffffffff81bb2240 t ilk_validate_wm_level +ffffffff81bb2380 t ilk_program_watermarks +ffffffff81bb3140 t ilk_wm_merge +ffffffff81bb33b0 t vlv_compute_pipe_wm +ffffffff81bb41f0 t vlv_compute_intermediate_wm +ffffffff81bb44f0 t vlv_initial_watermarks +ffffffff81bb4560 t vlv_atomic_update_fifo +ffffffff81bb4870 t vlv_optimize_watermarks +ffffffff81bb4930 t g4x_compute_pipe_wm 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fwtable_reg_read_fw_domains +ffffffff81bc0a90 t fwtable_write8 +ffffffff81bc0de0 t fwtable_write16 +ffffffff81bc1130 t fwtable_write32 +ffffffff81bc1480 t fwtable_reg_write_fw_domains +ffffffff81bc1630 t gen6_write8 +ffffffff81bc17f0 t gen6_write16 +ffffffff81bc19b0 t gen6_write32 +ffffffff81bc1b70 t gen6_reg_write_fw_domains +ffffffff81bc1ba0 t i915_pmic_bus_access_notifier +ffffffff81bc1c20 t fw_domains_get_with_thread_status +ffffffff81bc1d60 t fw_domains_get_with_fallback +ffffffff81bc2200 t fw_domain_wait_ack_with_fallback +ffffffff81bc2480 t fw_domains_get_normal +ffffffff81bc27b0 t ___force_wake_auto +ffffffff81bc2840 t __gen6_gt_wait_for_fifo +ffffffff81bc3000 T __intel_wakeref_get_first +ffffffff81bc30a0 T __intel_wakeref_put_last +ffffffff81bc3100 t ____intel_wakeref_put_last +ffffffff81bc31e0 T __intel_wakeref_init +ffffffff81bc3260 t __intel_wakeref_put_work +ffffffff81bc32d0 T intel_wakeref_wait_for_idle +ffffffff81bc3410 T intel_wakeref_auto_init +ffffffff81bc3480 t wakeref_auto_timeout +ffffffff81bc3520 T intel_wakeref_auto +ffffffff81bc3710 T intel_wakeref_auto_fini +ffffffff81bc37c0 t __delayed_work_tick +ffffffff81bc4000 T intel_wopcm_init_early +ffffffff81bc4070 T intel_wopcm_init +ffffffff81bc5000 T vlv_iosf_sb_get +ffffffff81bc5020 T vlv_iosf_sb_put +ffffffff81bc5040 T vlv_punit_read +ffffffff81bc5090 t vlv_sideband_rw +ffffffff81bc5240 T vlv_punit_write +ffffffff81bc5290 T vlv_bunit_read +ffffffff81bc52e0 T vlv_bunit_write +ffffffff81bc5330 T vlv_nc_read +ffffffff81bc5380 T vlv_iosf_sb_read +ffffffff81bc53d0 T vlv_iosf_sb_write +ffffffff81bc5420 T vlv_cck_read +ffffffff81bc5470 T vlv_cck_write +ffffffff81bc54c0 T vlv_ccu_read +ffffffff81bc5510 T vlv_ccu_write +ffffffff81bc5560 T vlv_dpio_read +ffffffff81bc5630 T vlv_dpio_write +ffffffff81bc56a0 T vlv_flisdsi_read +ffffffff81bc56f0 T vlv_flisdsi_write +ffffffff81bc6000 T vlv_suspend_complete +ffffffff81bc6a50 T vlv_resume_prepare +ffffffff81bc7490 T vlv_suspend_init +ffffffff81bc74f0 T vlv_suspend_cleanup +ffffffff81bc7540 t vlv_wait_for_pw_status +ffffffff81bc8000 T atom_execute_table_scratch_unlocked +ffffffff81bc80a0 t atom_execute_table_locked +ffffffff81bc83d0 T atom_execute_table +ffffffff81bc8480 T atom_parse +ffffffff81bc8650 T atom_destroy +ffffffff81bc8690 T atom_asic_init +ffffffff81bc88a0 T atom_parse_data_header +ffffffff81bc8930 T atom_parse_cmd_header +ffffffff81bc89a0 T atom_allocate_fb_scratch +ffffffff81bc8a70 t atom_op_move +ffffffff81bc8c50 t atom_op_and +ffffffff81bc8e30 t atom_op_or +ffffffff81bc9010 t atom_op_shift_left +ffffffff81bc9200 t atom_op_shift_right +ffffffff81bc93f0 t atom_op_mul +ffffffff81bc9540 t atom_op_div +ffffffff81bc96b0 t atom_op_add +ffffffff81bc9890 t atom_op_sub +ffffffff81bc9a70 t atom_op_setport +ffffffff81bc9bf0 t atom_op_setregblock +ffffffff81bc9cb0 t atom_op_setfbbase +ffffffff81bc9d80 t atom_op_compare +ffffffff81bc9f70 t atom_op_switch +ffffffff81bca1c0 t atom_op_jump +ffffffff81bca440 t atom_op_test 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atombios_crtc_program_ss +ffffffff81bceb80 T atombios_crtc_mode_set +ffffffff81bcf5b0 T radeon_atombios_init_crtc +ffffffff81bcf6a0 t radeon_bo_reserve +ffffffff81bcf820 t radeon_bo_unreserve +ffffffff81bcf900 t atombios_crtc_program_pll +ffffffff81bcfbb0 t atombios_crtc_prepare +ffffffff81bcfc60 t atombios_crtc_commit +ffffffff81bcfcd0 t atombios_crtc_mode_fixup +ffffffff81bd0a40 t atombios_crtc_disable +ffffffff81bd0ca0 t radeon_get_shared_nondp_ppll +ffffffff81bd1000 T radeon_atom_copy_swap +ffffffff81bd1010 T radeon_dp_aux_init +ffffffff81bd10f0 t radeon_dp_aux_transfer_atom +ffffffff81bd12c0 T radeon_dp_getsinktype +ffffffff81bd1330 T radeon_dp_getdpcd +ffffffff81bd14a0 T radeon_dp_get_panel_mode +ffffffff81bd15a0 T radeon_dp_set_link_config +ffffffff81bd1620 t radeon_dp_get_dp_link_config +ffffffff81bd17a0 T radeon_dp_mode_valid_helper +ffffffff81bd1850 T radeon_dp_needs_link_train +ffffffff81bd18c0 T radeon_dp_set_rx_power_state +ffffffff81bd1940 T radeon_dp_link_train +ffffffff81bd20c0 t radeon_process_aux_ch +ffffffff81bd2260 t dp_get_adjust_train +ffffffff81bd3000 T atombios_get_backlight_level +ffffffff81bd3060 T atombios_set_backlight_level +ffffffff81bd3210 T atombios_dig_transmitter_setup +ffffffff81bd3230 T radeon_atom_backlight_init +ffffffff81bd3400 t radeon_atom_backlight_get_brightness +ffffffff81bd3460 T atombios_dvo_setup +ffffffff81bd3620 T atombios_digital_setup +ffffffff81bd38c0 T atombios_get_encoder_mode +ffffffff81bd3b50 T atombios_dig_encoder_setup2 +ffffffff81bd3f90 T atombios_dig_encoder_setup +ffffffff81bd3fb0 T atombios_dig_transmitter_setup2 +ffffffff81bd4910 T atombios_set_edp_panel_power +ffffffff81bd4a30 T radeon_atom_release_dig_encoder +ffffffff81bd4a70 T radeon_atom_pick_dig_encoder +ffffffff81bd4cb0 T radeon_atom_encoder_init +ffffffff81bd4d80 t atombios_external_encoder_setup +ffffffff81bd4fe0 T radeon_atom_ext_encoder_setup_ddc +ffffffff81bd5030 T radeon_enc_destroy +ffffffff81bd50e0 T radeon_add_atom_encoder +ffffffff81bd5520 t radeon_atom_backlight_update_status +ffffffff81bd5580 t radeon_atom_encoder_dpms +ffffffff81bd5890 t radeon_atom_mode_fixup +ffffffff81bd59d0 t radeon_atom_encoder_prepare +ffffffff81bd5ea0 t radeon_atom_encoder_commit +ffffffff81bd5ed0 t radeon_atom_encoder_mode_set +ffffffff81bd6480 t radeon_atom_dig_detect +ffffffff81bd6590 t radeon_atom_encoder_disable +ffffffff81bd6840 t radeon_atom_encoder_dpms_avivo +ffffffff81bd6a70 t radeon_atom_encoder_dpms_dig +ffffffff81bd6f70 t radeon_atom_dac_detect +ffffffff81bd7160 t radeon_atom_ext_dpms +ffffffff81bd7190 t radeon_atom_ext_prepare +ffffffff81bd71c0 t radeon_atom_ext_commit +ffffffff81bd71f0 t radeon_atom_ext_mode_set +ffffffff81bd7220 t radeon_atom_ext_disable +ffffffff81bd8000 T radeon_atom_hw_i2c_xfer +ffffffff81bd8160 t radeon_process_i2c_ch +ffffffff81bd8330 T radeon_atom_hw_i2c_func +ffffffff81bd9000 T btc_get_max_clock_from_voltage_dependency_table +ffffffff81bd90d0 T btc_apply_voltage_dependency_rules +ffffffff81bd9140 T btc_skip_blacklist_clocks +ffffffff81bd9230 T btc_adjust_clock_combinations +ffffffff81bd9340 T btc_apply_voltage_delta_rules +ffffffff81bd9470 T btc_program_mgcg_hw_sequence +ffffffff81bd9570 T btc_dpm_enabled +ffffffff81bd9580 T btc_notify_uvd_to_smc +ffffffff81bd95f0 T btc_reset_to_default +ffffffff81bd9640 T btc_read_arb_registers +ffffffff81bd96d0 T btc_dpm_vblank_too_short +ffffffff81bd9730 T btc_dpm_pre_set_power_state +ffffffff81bda610 T btc_dpm_set_power_state +ffffffff81bdaa20 T btc_dpm_post_set_power_state +ffffffff81bdab40 T btc_dpm_enable +ffffffff81bdbd50 T btc_dpm_disable +ffffffff81bdc280 T btc_dpm_setup_asic +ffffffff81bdc350 T btc_dpm_init +ffffffff81bdc750 T btc_dpm_fini +ffffffff81bdc800 T btc_dpm_debugfs_print_current_performance_level +ffffffff81bdc840 T btc_dpm_get_current_sclk +ffffffff81bdc8c0 T btc_dpm_get_current_mclk +ffffffff81bdc940 T btc_dpm_get_sclk +ffffffff81bdc990 T btc_dpm_get_mclk +ffffffff81bdd000 T ci_dpm_powergate_uvd +ffffffff81bdd380 T ci_dpm_vblank_too_short +ffffffff81bdd400 T ci_fan_ctrl_get_fan_speed_percent +ffffffff81bdd4a0 T ci_fan_ctrl_set_fan_speed_percent +ffffffff81bdd570 T ci_fan_ctrl_set_mode +ffffffff81bdd700 t ci_fan_ctrl_set_static_mode +ffffffff81bdd7c0 t ci_thermal_start_smc_fan_control +ffffffff81bdda00 T ci_fan_ctrl_get_mode +ffffffff81bdda50 T ci_dpm_force_performance_level +ffffffff81bde310 t ci_upload_dpm_level_enable_mask +ffffffff81bde640 T ci_dpm_pre_set_power_state +ffffffff81bde940 T ci_dpm_post_set_power_state +ffffffff81bdea10 T ci_dpm_setup_asic +ffffffff81bdec10 T ci_dpm_enable +ffffffff81be2a40 t ci_enable_didt +ffffffff81be2ce0 t ci_enable_power_containment +ffffffff81be3180 T ci_dpm_late_enable +ffffffff81be3370 T ci_dpm_disable +ffffffff81be3a60 T ci_dpm_set_power_state +ffffffff81be4be0 T ci_dpm_display_configuration_changed +ffffffff81be4d80 T ci_dpm_fini +ffffffff81be4e30 T ci_dpm_init +ffffffff81be6500 T ci_dpm_debugfs_print_current_performance_level +ffffffff81be6640 T ci_dpm_print_power_state +ffffffff81be6700 T ci_dpm_get_current_sclk +ffffffff81be67d0 T ci_dpm_get_current_mclk +ffffffff81be68a0 T ci_dpm_get_sclk +ffffffff81be68f0 T ci_dpm_get_mclk +ffffffff81be6940 t ci_populate_all_graphic_levels +ffffffff81be6ec0 t ci_populate_all_memory_levels +ffffffff81be77d0 t ci_do_program_memory_timing_parameters +ffffffff81be79f0 t ci_populate_smc_voltage_table +ffffffff81be7b50 t ci_enable_sclk_mclk_dpm +ffffffff81be8000 T ci_copy_bytes_to_smc +ffffffff81be8250 T ci_start_smc +ffffffff81be8280 T ci_reset_smc +ffffffff81be82b0 T ci_program_jump_on_start +ffffffff81be82e0 T ci_stop_smc_clock +ffffffff81be8310 T ci_start_smc_clock +ffffffff81be8340 T ci_is_smc_running +ffffffff81be83b0 T ci_load_smc_ucode +ffffffff81be8540 T ci_read_smc_sram_dword +ffffffff81be8610 T ci_write_smc_sram_dword +ffffffff81be9000 T cik_get_allowed_info_register +ffffffff81be90a0 T cik_didt_rreg +ffffffff81be9140 T cik_didt_wreg +ffffffff81be91c0 T ci_get_temp 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+ffffffff81bec0d0 T cik_vm_init +ffffffff81bec130 T cik_vm_fini +ffffffff81bec160 T cik_vm_flush +ffffffff81beceb0 T cik_enter_rlc_safe_mode +ffffffff81becf90 T cik_exit_rlc_safe_mode +ffffffff81becfd0 T cik_update_cg +ffffffff81bed4a0 t cik_enable_mgcg +ffffffff81bed9c0 t cik_enable_cgcg +ffffffff81bedd30 T cik_init_cp_pg_table +ffffffff81bedff0 T cik_get_csb_size +ffffffff81bee080 T cik_get_csb_buffer +ffffffff81bee220 T cik_irq_set +ffffffff81beefc0 t cik_disable_interrupt_state +ffffffff81bef480 T cik_irq_process +ffffffff81bf0c20 t cik_irq_ack +ffffffff81bf15a0 T cik_resume +ffffffff81bf1630 t cik_init_golden_registers +ffffffff81bf17f0 t cik_startup +ffffffff81bf7540 T cik_suspend +ffffffff81bf7920 T cik_init +ffffffff81bf8110 t cik_init_microcode +ffffffff81bf9120 t cik_pcie_gart_fini +ffffffff81bf9220 T cik_fini +ffffffff81bf95c0 T dce8_program_fmt +ffffffff81bf96f0 T dce8_bandwidth_update +ffffffff81bfa310 T cik_get_gpu_clock_counter +ffffffff81bfa3d0 T cik_set_uvd_clocks +ffffffff81bfa440 t cik_set_uvd_clock +ffffffff81bfa5b0 T cik_set_vce_clocks +ffffffff81bfa7f0 t cik_wait_for_rlc_serdes +ffffffff81bfa9c0 t radeon_bo_reserve +ffffffff81bfab40 t radeon_bo_unreserve +ffffffff81bfac20 t cik_update_gfx_pg +ffffffff81bfadc0 t cik_compute_stop +ffffffff81bfaf30 t cik_cp_compute_fini +ffffffff81bfb0d0 t dce8_latency_watermark +ffffffff81bfc000 T cik_sdma_get_rptr +ffffffff81bfc070 T cik_sdma_get_wptr +ffffffff81bfc0c0 T cik_sdma_set_wptr +ffffffff81bfc110 T cik_sdma_ring_ib_execute +ffffffff81bfc4f0 T cik_sdma_fence_ring_emit +ffffffff81bfc6d0 t cik_sdma_hdp_flush_ring_emit +ffffffff81bfc910 T cik_sdma_semaphore_ring_emit +ffffffff81bfca30 T cik_sdma_enable +ffffffff81bfcc10 T cik_sdma_resume +ffffffff81bfd0e0 T cik_sdma_fini +ffffffff81bfd120 T cik_copy_dma +ffffffff81bfd4f0 T cik_sdma_ring_test +ffffffff81bfd790 T cik_sdma_ib_test +ffffffff81bfd9e0 T cik_sdma_is_lockup +ffffffff81bfda60 T cik_sdma_vm_copy_pages +ffffffff81bfdb70 T cik_sdma_vm_write_pages +ffffffff81bfdce0 T cik_sdma_vm_set_pages +ffffffff81bfde50 T cik_sdma_vm_pad_ib +ffffffff81bfdea0 T cik_dma_vm_flush +ffffffff81bff000 T cypress_enable_spread_spectrum +ffffffff81bff130 T cypress_start_dpm +ffffffff81bff180 T cypress_enable_sclk_control +ffffffff81bff1e0 T cypress_enable_mclk_control +ffffffff81bff240 T cypress_notify_smc_display_change +ffffffff81bff280 T cypress_program_response_times +ffffffff81bff340 T cypress_advertise_gen2_capability +ffffffff81bff410 T cypress_notify_link_speed_change_after_state_change +ffffffff81bff4d0 T cypress_notify_link_speed_change_before_state_change +ffffffff81bff580 T cypress_get_strobe_mode_settings +ffffffff81bff680 T cypress_get_mclk_frequency_ratio +ffffffff81bff730 T cypress_map_clkf_to_ibias +ffffffff81bff7f0 T cypress_convert_power_level_to_smc +ffffffff81bffbb0 t cypress_populate_mclk_value +ffffffff81bfff80 T cypress_upload_sw_state +ffffffff81c00100 T cypress_upload_mc_reg_table +ffffffff81c001b0 t cypress_convert_mc_reg_table_to_smc +ffffffff81c00450 T cypress_calculate_burst_time +ffffffff81c004d0 T cypress_program_memory_timing_parameters +ffffffff81c00680 T cypress_populate_smc_initial_state +ffffffff81c00a10 T cypress_populate_smc_acpi_state +ffffffff81c00da0 T cypress_construct_voltage_tables +ffffffff81c00e40 t cypress_trim_voltage_table_to_fit_state_table +ffffffff81c01030 T cypress_populate_smc_voltage_tables +ffffffff81c01170 T cypress_get_mvdd_configuration +ffffffff81c01230 T cypress_populate_mc_reg_table +ffffffff81c01490 T cypress_get_table_locations +ffffffff81c01570 T cypress_enable_display_gap +ffffffff81c015c0 T cypress_dpm_setup_asic +ffffffff81c016b0 T cypress_dpm_enable +ffffffff81c02190 t cypress_force_mc_use_s1 +ffffffff81c02410 t cypress_gfx_clock_gating_enable +ffffffff81c02720 t cypress_mg_clock_gating_enable +ffffffff81c029a0 T cypress_dpm_disable +ffffffff81c02bd0 T cypress_dpm_set_power_state +ffffffff81c02e80 T cypress_dpm_display_configuration_changed +ffffffff81c02f60 T cypress_dpm_init +ffffffff81c031d0 T cypress_dpm_fini +ffffffff81c03260 T cypress_dpm_vblank_too_short +ffffffff81c032c0 t cypress_wait_for_mc_sequencer +ffffffff81c04000 T dce3_2_afmt_hdmi_write_speaker_allocation +ffffffff81c04070 T dce3_2_afmt_dp_write_speaker_allocation +ffffffff81c040e0 T dce3_2_afmt_write_sad_regs +ffffffff81c041f0 T dce3_2_audio_set_dto +ffffffff81c04330 T dce3_2_hdmi_update_acr +ffffffff81c04690 T dce3_2_set_audio_packet +ffffffff81c04820 T dce3_2_set_mute +ffffffff81c05000 T dce6_endpoint_rreg +ffffffff81c050d0 T dce6_endpoint_wreg +ffffffff81c051c0 T dce6_audio_get_pin +ffffffff81c05330 T dce6_afmt_select_pin +ffffffff81c053c0 T dce6_afmt_write_latency_fields +ffffffff81c05470 T dce6_afmt_hdmi_write_speaker_allocation +ffffffff81c05540 T dce6_afmt_dp_write_speaker_allocation +ffffffff81c05610 T dce6_afmt_write_sad_regs +ffffffff81c05750 T dce6_audio_enable +ffffffff81c05790 T dce6_hdmi_audio_set_dto +ffffffff81c05800 T dce6_dp_audio_set_dto +ffffffff81c06000 T eg_cg_rreg +ffffffff81c06080 t r100_mm_rreg +ffffffff81c060d0 T eg_cg_wreg +ffffffff81c06130 T eg_pif_phy0_rreg +ffffffff81c061b0 T eg_pif_phy0_wreg +ffffffff81c06210 T eg_pif_phy1_rreg +ffffffff81c06290 T eg_pif_phy1_wreg +ffffffff81c062f0 T evergreen_get_allowed_info_register +ffffffff81c06370 T evergreen_tiling_fields +ffffffff81c06410 T sumo_set_uvd_clocks +ffffffff81c064e0 t sumo_set_uvd_clock +ffffffff81c066a0 T evergreen_set_uvd_clocks +ffffffff81c06c40 T evergreen_fix_pci_max_read_req_size +ffffffff81c06df0 T dce4_program_fmt +ffffffff81c06f00 T dce4_wait_for_vblank +ffffffff81c07180 T evergreen_page_flip +ffffffff81c07310 T evergreen_page_flip_pending +ffffffff81c07380 T evergreen_get_temp +ffffffff81c07450 T sumo_get_temp +ffffffff81c07490 T sumo_pm_init_profile +ffffffff81c075d0 T btc_pm_init_profile +ffffffff81c076e0 T evergreen_pm_misc +ffffffff81c07880 T evergreen_pm_prepare +ffffffff81c07980 T evergreen_pm_finish +ffffffff81c07a80 T evergreen_hpd_sense +ffffffff81c07af0 T evergreen_hpd_set_polarity +ffffffff81c07c30 T evergreen_hpd_init +ffffffff81c07d00 T evergreen_hpd_fini +ffffffff81c07da0 T evergreen_get_number_of_dram_channels +ffffffff81c07de0 T evergreen_bandwidth_update +ffffffff81c07fa0 t evergreen_line_buffer_adjust +ffffffff81c081a0 t evergreen_program_watermarks +ffffffff81c08c50 T evergreen_mc_wait_for_idle +ffffffff81c08ce0 T evergreen_pcie_gart_tlb_flush +ffffffff81c08db0 T evergreen_mc_stop +ffffffff81c098a0 T evergreen_mc_resume +ffffffff81c09fb0 T evergreen_mc_program +ffffffff81c0a3c0 T evergreen_ring_ib_execute +ffffffff81c0a850 T evergreen_mc_init +ffffffff81c0a990 T evergreen_print_gpu_status_regs +ffffffff81c0a9c0 T evergreen_is_display_hung +ffffffff81c0abc0 T evergreen_gpu_check_soft_reset +ffffffff81c0ad20 T evergreen_gpu_pci_config_reset +ffffffff81c0ae90 T evergreen_asic_reset +ffffffff81c0b1a0 T evergreen_gfx_is_lockup +ffffffff81c0b200 T sumo_rlc_fini +ffffffff81c0b3c0 t radeon_bo_reserve +ffffffff81c0b540 t radeon_bo_unreserve +ffffffff81c0b620 T sumo_rlc_init +ffffffff81c0be00 T evergreen_rlc_resume +ffffffff81c0c170 T evergreen_get_vblank_counter +ffffffff81c0c1d0 T evergreen_disable_interrupt_state +ffffffff81c0c4a0 T evergreen_irq_set +ffffffff81c0ca60 T evergreen_irq_suspend +ffffffff81c0cab0 T evergreen_irq_process +ffffffff81c0d5a0 t evergreen_irq_ack +ffffffff81c0dca0 T evergreen_resume +ffffffff81c0dd80 t evergreen_init_golden_registers +ffffffff81c0df90 t evergreen_startup +ffffffff81c10620 T evergreen_suspend +ffffffff81c107c0 T evergreen_init +ffffffff81c10cd0 T evergreen_fini +ffffffff81c10ec0 T evergreen_pcie_gen2_enable +ffffffff81c110f0 T evergreen_program_aspm +ffffffff81c11790 t evergreen_latency_watermark +ffffffff81c12000 T evergreen_cs_parse +ffffffff81c148b0 T evergreen_dma_cs_parse +ffffffff81c15af0 T evergreen_ib_parse +ffffffff81c15fa0 T evergreen_dma_ib_parse +ffffffff81c16160 t evergreen_cs_track_check +ffffffff81c17180 t evergreen_cs_handle_reg +ffffffff81c190c0 t evergreen_surface_value_conv_check +ffffffff81c193a0 t evergreen_surface_check +ffffffff81c19840 t evergreen_cs_track_validate_htile +ffffffff81c19ae0 t evergreen_vm_reg_valid +ffffffff81c1a000 T evergreen_dma_fence_ring_emit +ffffffff81c1a2c0 T evergreen_dma_ring_ib_execute +ffffffff81c1a600 T evergreen_copy_dma +ffffffff81c1a9b0 T evergreen_dma_is_lockup +ffffffff81c1b000 T dce4_audio_enable +ffffffff81c1b080 T evergreen_hdmi_update_acr +ffffffff81c1b290 T dce4_afmt_write_latency_fields +ffffffff81c1b300 T dce4_afmt_hdmi_write_speaker_allocation +ffffffff81c1b370 T dce4_afmt_dp_write_speaker_allocation +ffffffff81c1b3e0 T evergreen_hdmi_write_sad_regs +ffffffff81c1b4f0 T evergreen_set_avi_packet +ffffffff81c1b680 T dce4_hdmi_audio_set_dto +ffffffff81c1b750 T dce4_dp_audio_set_dto +ffffffff81c1b840 T dce4_set_vbi_packet +ffffffff81c1b8a0 T dce4_hdmi_set_color_depth +ffffffff81c1b9f0 T dce4_set_audio_packet +ffffffff81c1bc00 T dce4_set_mute +ffffffff81c1bd00 T evergreen_hdmi_enable +ffffffff81c1c030 T evergreen_dp_enable +ffffffff81c1d000 T kv_dpm_enable_bapm +ffffffff81c1d060 T kv_dpm_enable +ffffffff81c1e5a0 t kv_enable_didt +ffffffff81c1e840 T kv_dpm_late_enable +ffffffff81c1ea20 T kv_dpm_powergate_uvd +ffffffff81c1eb90 T kv_dpm_disable +ffffffff81c1ef00 T kv_dpm_force_performance_level +ffffffff81c1f090 t kv_force_dpm_lowest +ffffffff81c1f160 T kv_dpm_pre_set_power_state +ffffffff81c1f6f0 T kv_dpm_set_power_state +ffffffff81c1fea0 t kv_set_valid_clock_range +ffffffff81c20060 t kv_calculate_ds_divider +ffffffff81c201d0 t kv_calculate_nbps_level_settings +ffffffff81c20360 t kv_update_vce_dpm +ffffffff81c20540 T kv_dpm_post_set_power_state +ffffffff81c205e0 T kv_dpm_setup_asic +ffffffff81c20640 T kv_dpm_init +ffffffff81c20ee0 T kv_dpm_debugfs_print_current_performance_level +ffffffff81c20f50 T kv_dpm_get_current_sclk +ffffffff81c20fc0 T kv_dpm_get_current_mclk +ffffffff81c20ff0 T kv_dpm_print_power_state +ffffffff81c21090 T kv_dpm_fini +ffffffff81c21130 T kv_dpm_display_configuration_changed +ffffffff81c21160 T kv_dpm_get_sclk +ffffffff81c211b0 T kv_dpm_get_mclk +ffffffff81c22000 T kv_notify_message_to_smu +ffffffff81c220c0 T kv_dpm_get_enable_mask +ffffffff81c22190 T kv_send_msg_to_smc_with_parameter +ffffffff81c22260 T kv_read_smc_sram_dword +ffffffff81c222e0 T kv_smc_dpm_enable +ffffffff81c22400 T kv_smc_bapm_enable +ffffffff81c22520 T kv_copy_bytes_to_smc +ffffffff81c23000 T tn_smc_rreg +ffffffff81c23080 T tn_smc_wreg +ffffffff81c230e0 T ni_mc_load_microcode +ffffffff81c232d0 T ni_init_microcode +ffffffff81c23810 T cayman_get_allowed_info_register +ffffffff81c238a0 T tn_get_temp +ffffffff81c23930 T cayman_pcie_gart_tlb_flush +ffffffff81c23980 T cayman_cp_int_cntl_setup +ffffffff81c239d0 T cayman_fence_ring_emit +ffffffff81c23d70 T cayman_ring_ib_execute +ffffffff81c241e0 T cayman_gfx_get_rptr +ffffffff81c24270 T cayman_gfx_get_wptr +ffffffff81c242e0 T cayman_gfx_set_wptr +ffffffff81c24360 T cayman_gpu_check_soft_reset +ffffffff81c244e0 T cayman_asic_reset +ffffffff81c247e0 T cayman_gfx_is_lockup +ffffffff81c24840 T cayman_resume +ffffffff81c248d0 t ni_init_golden_registers +ffffffff81c249b0 t cayman_startup +ffffffff81c270e0 T cayman_suspend +ffffffff81c272d0 T cayman_init +ffffffff81c278d0 T cayman_fini +ffffffff81c27b50 T cayman_vm_init +ffffffff81c27bb0 T cayman_vm_fini +ffffffff81c27be0 T cayman_vm_decode_fault +ffffffff81c27c70 T cayman_vm_flush +ffffffff81c280f0 T tn_set_vce_clocks +ffffffff81c29000 T cayman_dma_get_rptr +ffffffff81c29070 T cayman_dma_get_wptr +ffffffff81c290c0 T cayman_dma_set_wptr +ffffffff81c29110 T cayman_dma_ring_ib_execute +ffffffff81c294a0 T cayman_dma_stop +ffffffff81c29550 T cayman_dma_resume +ffffffff81c297a0 T cayman_dma_fini +ffffffff81c29850 T cayman_dma_is_lockup +ffffffff81c298d0 T cayman_dma_vm_copy_pages +ffffffff81c299c0 T cayman_dma_vm_write_pages +ffffffff81c29b20 T cayman_dma_vm_set_pages +ffffffff81c29c80 T cayman_dma_vm_pad_ib +ffffffff81c29cd0 T cayman_dma_vm_flush +ffffffff81c2b000 T ni_get_pi +ffffffff81c2b030 T ni_get_ps +ffffffff81c2b060 T ni_dpm_vblank_too_short +ffffffff81c2b0c0 T ni_dpm_force_performance_level +ffffffff81c2b200 T ni_copy_and_switch_arb_sets +ffffffff81c2b4d0 T ni_set_uvd_clock_before_set_eng_clock +ffffffff81c2b550 T ni_set_uvd_clock_after_set_eng_clock +ffffffff81c2b5d0 T ni_dpm_setup_asic +ffffffff81c2b7e0 T ni_update_current_ps +ffffffff81c2b890 T ni_update_requested_ps +ffffffff81c2b940 T ni_dpm_enable +ffffffff81c2eb80 t ni_populate_smc_tdp_limits +ffffffff81c2ed40 T ni_dpm_disable +ffffffff81c2f100 T ni_dpm_pre_set_power_state +ffffffff81c2f6e0 T ni_dpm_set_power_state +ffffffff81c307f0 T ni_dpm_post_set_power_state +ffffffff81c308c0 T ni_dpm_init +ffffffff81c31290 T ni_dpm_fini +ffffffff81c31340 T ni_dpm_print_power_state +ffffffff81c31410 T ni_dpm_debugfs_print_current_performance_level +ffffffff81c31450 T ni_dpm_get_current_sclk +ffffffff81c314b0 T ni_dpm_get_current_mclk +ffffffff81c31510 T ni_dpm_get_sclk +ffffffff81c31570 T ni_dpm_get_mclk +ffffffff81c315d0 t ni_do_program_memory_timing_parameters +ffffffff81c31700 t ni_calculate_sclk_params +ffffffff81c31920 t ni_calculate_power_boost_limit +ffffffff81c31ad0 t ni_populate_mclk_value +ffffffff81c32000 T r100_wait_for_vblank +ffffffff81c321a0 T r100_page_flip +ffffffff81c32450 T r100_page_flip_pending +ffffffff81c32500 T r100_pm_get_dynpm_state +ffffffff81c32720 T r100_pm_init_profile +ffffffff81c32800 T r100_pm_misc +ffffffff81c32c30 T r100_pm_prepare +ffffffff81c32ce0 T r100_pm_finish +ffffffff81c32d90 T r100_gui_idle +ffffffff81c32dd0 T r100_hpd_sense +ffffffff81c32e30 T r100_hpd_set_polarity +ffffffff81c32ee0 T r100_hpd_init +ffffffff81c32f70 T r100_hpd_fini +ffffffff81c32fd0 T r100_pci_gart_tlb_flush +ffffffff81c33000 T r100_pci_gart_init +ffffffff81c330d0 T r100_pci_gart_get_page_entry +ffffffff81c33100 T r100_pci_gart_set_page +ffffffff81c33130 T r100_pci_gart_enable +ffffffff81c33210 T r100_pci_gart_disable +ffffffff81c33280 T r100_pci_gart_fini +ffffffff81c332f0 T r100_irq_set +ffffffff81c333c0 T r100_irq_disable +ffffffff81c33430 T r100_irq_process +ffffffff81c33730 T r100_get_vblank_counter +ffffffff81c33780 T r100_fence_ring_emit +ffffffff81c33bf0 T r100_semaphore_ring_emit +ffffffff81c33c20 T r100_copy_blit +ffffffff81c342b0 T r100_ring_start +ffffffff81c343a0 T r100_gfx_get_rptr +ffffffff81c343f0 T r100_gfx_get_wptr +ffffffff81c34430 T r100_gfx_set_wptr +ffffffff81c34470 T r100_cp_init +ffffffff81c349a0 T r100_debugfs_cp_init +ffffffff81c349d0 T r100_cp_fini +ffffffff81c34a70 T r100_cp_disable +ffffffff81c34bb0 T r100_gui_wait_for_idle +ffffffff81c34ca0 T r100_reloc_pitch_offset +ffffffff81c34dd0 T r100_packet3_load_vbpntr +ffffffff81c35070 T r100_cs_parse_packet0 +ffffffff81c35180 T r100_cs_packet_parse_vline +ffffffff81c35370 T r100_cs_track_check_pkt3_indx_buffer +ffffffff81c353e0 T r100_cs_parse +ffffffff81c368a0 T r100_cs_track_clear +ffffffff81c36c30 T r100_cs_track_check +ffffffff81c37610 T r100_mc_wait_for_idle +ffffffff81c376a0 T r100_gpu_is_lockup +ffffffff81c37700 T r100_enable_bm +ffffffff81c37740 T r100_bm_disable +ffffffff81c377e0 T r100_asic_reset +ffffffff81c37b10 T r100_mc_stop +ffffffff81c37cc0 T r100_mc_resume +ffffffff81c37d70 T r100_set_common_regs +ffffffff81c37f20 T r100_vram_init_sizes +ffffffff81c38100 T r100_vga_set_state +ffffffff81c38160 T r100_pll_errata_after_index +ffffffff81c381a0 T r100_pll_rreg +ffffffff81c382c0 T r100_pll_wreg +ffffffff81c383d0 T r100_debugfs_rbbm_init +ffffffff81c38400 T r100_debugfs_mc_info_init +ffffffff81c38430 T r100_set_surface_reg +ffffffff81c38640 T r100_clear_surface_reg +ffffffff81c386f0 T r100_bandwidth_update +ffffffff81c39190 T r100_ring_test +ffffffff81c39440 T r100_ring_ib_execute +ffffffff81c396a0 T r100_ib_test +ffffffff81c399e0 T r100_vga_render_disable +ffffffff81c39a40 T r100_resume +ffffffff81c39c30 t r100_startup +ffffffff81c3a160 T r100_suspend +ffffffff81c3a240 T r100_fini +ffffffff81c3a340 T r100_restore_sanity +ffffffff81c3a3e0 T r100_init +ffffffff81c3a950 T r100_mm_rreg_slow +ffffffff81c3a9c0 T r100_mm_wreg_slow +ffffffff81c3aa20 T r100_io_rreg +ffffffff81c3aac0 T r100_io_wreg +ffffffff81c3ab30 t r100_cs_track_texture_print +ffffffff81c3b000 T r200_copy_dma +ffffffff81c3b460 T r200_packet0_check +ffffffff81c3c470 T r200_set_safe_registers +ffffffff81c3d000 T rv370_pcie_rreg +ffffffff81c3d080 T rv370_pcie_wreg +ffffffff81c3d0e0 T rv370_pcie_gart_tlb_flush +ffffffff81c3d2d0 T rv370_pcie_gart_get_page_entry +ffffffff81c3d330 T rv370_pcie_gart_set_page +ffffffff81c3d370 T rv370_pcie_gart_init +ffffffff81c3d440 T rv370_pcie_gart_enable +ffffffff81c3d7a0 T rv370_pcie_gart_disable +ffffffff81c3d920 T rv370_pcie_gart_fini +ffffffff81c3d950 T r300_fence_ring_emit +ffffffff81c3dee0 T r300_ring_start +ffffffff81c3e8f0 T r300_mc_wait_for_idle +ffffffff81c3e980 T r300_asic_reset +ffffffff81c3eb90 T r300_mc_init +ffffffff81c3ec40 T rv370_set_pcie_lanes +ffffffff81c3ee00 T rv370_get_pcie_lanes +ffffffff81c3eeb0 T r300_cs_parse +ffffffff81c3f210 t r300_packet0_check +ffffffff81c40070 T r300_set_reg_safe +ffffffff81c400b0 T r300_mc_program +ffffffff81c40230 T r300_clock_startup +ffffffff81c402b0 T r300_resume +ffffffff81c40480 t r300_startup +ffffffff81c407e0 T r300_suspend +ffffffff81c40860 T r300_fini +ffffffff81c40940 T r300_init +ffffffff81c41000 T r420_pm_init_profile +ffffffff81c410e0 T r420_pipes_init +ffffffff81c412c0 T r420_mc_rreg +ffffffff81c41340 T r420_mc_wreg +ffffffff81c413b0 T r420_resume +ffffffff81c41580 t r420_startup +ffffffff81c41920 T r420_suspend +ffffffff81c41ac0 T r420_fini +ffffffff81c41ba0 T r420_init +ffffffff81c41e20 T r420_debugfs_pipes_info_init +ffffffff81c42000 T r520_mc_wait_for_idle +ffffffff81c42090 T r520_resume +ffffffff81c42180 t r520_startup +ffffffff81c42570 T r520_init +ffffffff81c43000 T r600_rcu_rreg +ffffffff81c43080 T r600_rcu_wreg +ffffffff81c430f0 T r600_uvd_ctx_rreg +ffffffff81c43170 T r600_uvd_ctx_wreg +ffffffff81c431e0 T r600_get_allowed_info_register +ffffffff81c43250 T r600_get_xclk +ffffffff81c43280 T r600_set_uvd_clocks +ffffffff81c437e0 T dce3_program_fmt +ffffffff81c438f0 T rv6xx_get_temp +ffffffff81c43940 T r600_pm_get_dynpm_state +ffffffff81c43d40 T rs780_pm_init_profile +ffffffff81c43e40 T r600_pm_init_profile +ffffffff81c440d0 T r600_pm_misc +ffffffff81c441a0 T r600_gui_idle +ffffffff81c441e0 T r600_hpd_sense +ffffffff81c44300 T r600_hpd_set_polarity +ffffffff81c44570 T r600_hpd_init +ffffffff81c44780 T r600_hpd_fini +ffffffff81c44930 T r600_pcie_gart_tlb_flush +ffffffff81c44a70 T r600_pcie_gart_init +ffffffff81c44b10 T r600_mc_wait_for_idle +ffffffff81c44ba0 T rs780_mc_rreg +ffffffff81c44c30 T rs780_mc_wreg +ffffffff81c44cb0 T r600_vram_scratch_init +ffffffff81c44db0 t radeon_bo_reserve +ffffffff81c44f30 t radeon_bo_unreserve +ffffffff81c45010 T r600_vram_scratch_fini +ffffffff81c45080 T r600_set_bios_scratch_engine_hung +ffffffff81c450d0 T r600_gpu_check_soft_reset +ffffffff81c45450 T r600_asic_reset +ffffffff81c457e0 t r600_gpu_pci_config_reset +ffffffff81c45a00 T r600_gfx_is_lockup +ffffffff81c45a60 T r6xx_remap_render_backend +ffffffff81c45c40 T r600_count_pipe_bits +ffffffff81c45cb0 T r600_pciep_rreg +ffffffff81c45d30 T r600_pciep_wreg +ffffffff81c45d90 T r600_cp_stop +ffffffff81c45e10 T r600_init_microcode +ffffffff81c462e0 T r600_gfx_get_rptr +ffffffff81c46330 T r600_gfx_get_wptr +ffffffff81c46370 T r600_gfx_set_wptr +ffffffff81c463b0 T r600_cp_start +ffffffff81c46730 T r600_cp_resume +ffffffff81c46a90 T r600_ring_init +ffffffff81c46b30 T r600_cp_fini +ffffffff81c46bb0 T r600_scratch_init +ffffffff81c46c20 T r600_ring_test +ffffffff81c46ec0 T r600_fence_ring_emit +ffffffff81c47780 T r600_semaphore_ring_emit +ffffffff81c47970 T r600_copy_cpdma +ffffffff81c47f20 T r600_set_surface_reg +ffffffff81c47f50 T r600_clear_surface_reg +ffffffff81c47f80 T r600_vga_set_state +ffffffff81c47fe0 T r600_resume +ffffffff81c48070 t r600_startup +ffffffff81c4a080 T r600_suspend +ffffffff81c4a1e0 T r600_irq_suspend +ffffffff81c4a2a0 t r600_pcie_gart_disable +ffffffff81c4a4a0 T r600_init +ffffffff81c4ac90 T r600_ih_ring_init +ffffffff81c4ad00 T r600_irq_fini +ffffffff81c4ae30 T r600_fini +ffffffff81c4afc0 T r600_ring_ib_execute +ffffffff81c4b440 T r600_ib_test +ffffffff81c4b6f0 T r600_ih_ring_alloc +ffffffff81c4b810 T r600_ih_ring_fini +ffffffff81c4b8a0 T r600_rlc_stop +ffffffff81c4ba20 T r600_disable_interrupts +ffffffff81c4bad0 T r600_irq_init +ffffffff81c4bf30 t r600_disable_interrupt_state +ffffffff81c4c220 T r600_irq_disable +ffffffff81c4c2e0 T r600_irq_set +ffffffff81c4ca50 t r600_irq_ack +ffffffff81c4cf40 T r600_irq_process +ffffffff81c4db30 T r600_mmio_hdp_flush +ffffffff81c4dba0 T r600_set_pcie_lanes +ffffffff81c4dcd0 T r600_get_pcie_lanes +ffffffff81c4dda0 T r600_get_gpu_clock_counter +ffffffff81c4e000 T r600_fmt_is_valid_color +ffffffff81c4e040 T r600_fmt_is_valid_texture +ffffffff81c4e090 T r600_fmt_get_blocksize +ffffffff81c4e0d0 T r600_fmt_get_nblocksx +ffffffff81c4e120 T r600_fmt_get_nblocksy +ffffffff81c4e170 T r600_cs_common_vline_parse +ffffffff81c4e430 T r600_mip_minify +ffffffff81c4e490 T r600_cs_parse +ffffffff81c50420 T r600_dma_cs_next_reloc +ffffffff81c504a0 T r600_dma_cs_parse +ffffffff81c50bd0 t r600_cs_track_check +ffffffff81c51d10 t r600_cs_check_reg +ffffffff81c53000 T r600_dma_get_rptr +ffffffff81c53060 T r600_dma_get_wptr +ffffffff81c530a0 T r600_dma_set_wptr +ffffffff81c530e0 T r600_dma_stop +ffffffff81c53170 T r600_dma_resume +ffffffff81c53370 T r600_dma_fini +ffffffff81c533e0 T r600_dma_is_lockup +ffffffff81c53440 T r600_dma_ring_test +ffffffff81c536a0 T r600_dma_fence_ring_emit +ffffffff81c53890 T r600_dma_semaphore_ring_emit +ffffffff81c539b0 T r600_dma_ib_test +ffffffff81c53bc0 T r600_dma_ring_ib_execute +ffffffff81c53f00 T r600_copy_dma +ffffffff81c55000 T r600_dpm_print_class_info +ffffffff81c552b0 T r600_dpm_print_cap_info +ffffffff81c55330 T r600_dpm_print_ps_status +ffffffff81c553c0 T r600_dpm_get_vblank_time +ffffffff81c55480 T r600_dpm_get_vrefresh +ffffffff81c55510 T r600_calculate_u_and_p +ffffffff81c55580 T r600_calculate_at +ffffffff81c55630 T r600_gfx_clockgating_enable +ffffffff81c55740 T r600_dynamicpm_enable +ffffffff81c557a0 T r600_enable_thermal_protection +ffffffff81c55800 T r600_enable_acpi_pm +ffffffff81c55850 T r600_enable_dynamic_pcie_gen2 +ffffffff81c558b0 T r600_dynamicpm_enabled +ffffffff81c558f0 T r600_enable_sclk_control +ffffffff81c55950 T r600_enable_mclk_control +ffffffff81c559b0 T r600_enable_spll_bypass +ffffffff81c55a10 T r600_wait_for_spll_change +ffffffff81c55a90 T r600_set_bsp +ffffffff81c55ad0 T r600_set_at +ffffffff81c55b30 T r600_set_tc +ffffffff81c55b90 T r600_select_td +ffffffff81c55c50 T r600_set_vrc +ffffffff81c55c90 T r600_set_tpu +ffffffff81c55ce0 T r600_set_tpc +ffffffff81c55d30 T r600_set_sstu +ffffffff81c55d80 T r600_set_sst +ffffffff81c55dd0 T r600_set_git +ffffffff81c55e20 T r600_set_fctu +ffffffff81c55e70 T r600_set_fct +ffffffff81c55ec0 T r600_set_ctxcgtt3d_rphc +ffffffff81c55f10 T r600_set_ctxcgtt3d_rsdc +ffffffff81c55f70 T r600_set_vddc3d_oorsu +ffffffff81c55fc0 T r600_set_vddc3d_oorphc +ffffffff81c56010 T r600_set_vddc3d_oorsdc +ffffffff81c56070 T r600_set_mpll_lock_time +ffffffff81c560c0 T r600_set_mpll_reset_time +ffffffff81c56110 T r600_engine_clock_entry_enable +ffffffff81c56210 T r600_engine_clock_entry_enable_pulse_skipping +ffffffff81c56310 T r600_engine_clock_entry_enable_post_divider +ffffffff81c56410 T r600_engine_clock_entry_set_post_divider +ffffffff81c564d0 T r600_engine_clock_entry_set_reference_divider +ffffffff81c56590 T r600_engine_clock_entry_set_feedback_divider +ffffffff81c56650 T r600_engine_clock_entry_set_step_time +ffffffff81c56710 T r600_vid_rt_set_ssu +ffffffff81c56760 T r600_vid_rt_set_vru +ffffffff81c567b0 T r600_vid_rt_set_vrt +ffffffff81c56800 T r600_voltage_control_enable_pins +ffffffff81c56850 T r600_voltage_control_program_voltages +ffffffff81c568e0 T r600_voltage_control_deactivate_static_control +ffffffff81c56970 T r600_power_level_enable +ffffffff81c569e0 T r600_power_level_set_voltage_index +ffffffff81c56a40 T r600_power_level_set_mem_clock_index +ffffffff81c56aa0 T r600_power_level_set_eng_clock_index +ffffffff81c56b10 T r600_power_level_set_watermark_id +ffffffff81c56b80 T r600_power_level_set_pcie_gen2 +ffffffff81c56be0 T r600_power_level_get_current_index +ffffffff81c56c20 T r600_power_level_get_target_index +ffffffff81c56c60 T r600_power_level_set_enter_index +ffffffff81c56cb0 T r600_wait_for_power_level_unequal +ffffffff81c56d90 T r600_wait_for_power_level +ffffffff81c56e70 T r600_start_dpm +ffffffff81c57150 T r600_stop_dpm +ffffffff81c571a0 T r600_dpm_pre_set_power_state +ffffffff81c571d0 T r600_dpm_post_set_power_state +ffffffff81c57200 T r600_is_uvd_state +ffffffff81c57230 T r600_is_internal_thermal_sensor +ffffffff81c57270 T r600_dpm_late_enable +ffffffff81c57380 T r600_get_platform_caps +ffffffff81c57420 T r600_parse_extended_power_table +ffffffff81c58390 T r600_free_extended_power_table +ffffffff81c58490 T r600_get_pcie_gen_support +ffffffff81c584e0 T r600_get_pcie_lane_support +ffffffff81c58540 T r600_encode_pci_lane_width +ffffffff81c59000 T r600_audio_update_hdmi +ffffffff81c59170 t r600_audio_status +ffffffff81c59290 T r600_hdmi_buffer_status_changed +ffffffff81c59330 T r600_hdmi_update_audio_settings +ffffffff81c59700 T r600_audio_enable +ffffffff81c59780 T r600_audio_get_pin +ffffffff81c597b0 T r600_hdmi_update_acr +ffffffff81c59b50 T r600_set_avi_packet +ffffffff81c59d40 T r600_hdmi_audio_workaround +ffffffff81c59e00 T r600_hdmi_audio_set_dto +ffffffff81c59ec0 T r600_set_vbi_packet +ffffffff81c59f70 T r600_set_audio_packet +ffffffff81c5a240 T r600_set_mute +ffffffff81c5a340 T r600_hdmi_enable +ffffffff81c5b000 T radeon_acpi_is_pcie_performance_request_supported +ffffffff81c5b040 T radeon_acpi_pcie_notify_device_ready +ffffffff81c5b170 T radeon_acpi_pcie_performance_request +ffffffff81c5b390 T radeon_acpi_init +ffffffff81c5bae0 t radeon_acpi_event +ffffffff81c5be30 T radeon_acpi_fini +ffffffff81c5c000 T radeon_agp_head_init +ffffffff81c5c050 T radeon_agp_init +ffffffff81c5c0a0 T radeon_agp_resume +ffffffff81c5c140 T radeon_agp_fini +ffffffff81c5c190 T radeon_agp_suspend +ffffffff81c5d000 T radeon_agp_disable +ffffffff81c5d110 T radeon_asic_init +ffffffff81c5d9a0 t radeon_invalid_rreg +ffffffff81c5d9e0 t radeon_invalid_wreg +ffffffff81c5da20 t radeon_invalid_get_allowed_info_register +ffffffff81c5e000 T radeon_atombios_i2c_init +ffffffff81c5e3a0 T radeon_atombios_lookup_gpio +ffffffff81c5e4a0 T radeon_get_atom_connector_info_from_object_table +ffffffff81c5ee00 t radeon_lookup_i2c_gpio +ffffffff81c5f100 t radeon_atom_apply_quirks +ffffffff81c5f530 T radeon_get_atom_connector_info_from_supported_devices_table +ffffffff81c5fa30 T radeon_atom_get_clock_info +ffffffff81c5fdb0 T radeon_atombios_sideport_present +ffffffff81c5fe60 T radeon_atombios_get_tmds_info +ffffffff81c5ffa0 T radeon_atombios_get_ppll_ss_info +ffffffff81c600c0 T radeon_atombios_get_asic_ss_info +ffffffff81c60430 T radeon_atombios_get_lvds_info +ffffffff81c60790 T radeon_atombios_get_primary_dac_info +ffffffff81c60840 T radeon_atom_get_tv_timings +ffffffff81c60a80 T radeon_atombios_get_tv_info +ffffffff81c60b30 T radeon_atombios_get_tv_dac_info +ffffffff81c60c30 T radeon_atombios_get_default_voltages +ffffffff81c60cf0 T radeon_atombios_get_power_modes +ffffffff81c61dc0 T radeon_atom_get_clock_dividers +ffffffff81c620b0 T radeon_atom_get_memory_pll_dividers +ffffffff81c621f0 T radeon_atom_set_clock_gating +ffffffff81c62240 T radeon_atom_get_engine_clock +ffffffff81c62290 T radeon_atom_get_memory_clock +ffffffff81c622e0 T radeon_atom_set_engine_clock +ffffffff81c62330 T radeon_atom_set_memory_clock +ffffffff81c62380 T radeon_atom_set_engine_dram_timings +ffffffff81c623f0 T radeon_atom_update_memory_dll +ffffffff81c62440 T radeon_atom_set_ac_timing +ffffffff81c62490 T radeon_atom_set_voltage +ffffffff81c62560 T radeon_atom_get_max_vddc +ffffffff81c62630 T radeon_atom_get_leakage_vddc_based_on_leakage_idx +ffffffff81c62700 T radeon_atom_get_leakage_id_from_vbios +ffffffff81c627c0 T radeon_atom_get_leakage_vddc_based_on_leakage_params +ffffffff81c629d0 T radeon_atom_get_voltage_evv +ffffffff81c62a80 T radeon_atom_get_voltage_gpio_settings +ffffffff81c62b80 T radeon_atom_is_voltage_gpio +ffffffff81c62d10 T radeon_atom_get_svi2_info +ffffffff81c62df0 T radeon_atom_get_max_voltage +ffffffff81c62f80 T radeon_atom_get_min_voltage +ffffffff81c630c0 T radeon_atom_get_voltage_step +ffffffff81c631b0 T radeon_atom_round_to_true_voltage +ffffffff81c63320 T radeon_atom_get_voltage_table +ffffffff81c63590 T radeon_atom_get_memory_info +ffffffff81c63740 T radeon_atom_get_mclk_range_table +ffffffff81c63990 T radeon_atom_init_mc_reg_table +ffffffff81c63c00 T radeon_atom_initialize_bios_scratch_regs +ffffffff81c63cd0 T radeon_save_bios_scratch_regs +ffffffff81c63db0 T radeon_restore_bios_scratch_regs +ffffffff81c63e90 T radeon_atom_output_lock +ffffffff81c63f20 T radeon_atombios_connected_scratch_regs +ffffffff81c646a0 T radeon_atombios_encoder_crtc_scratch_regs +ffffffff81c647e0 T radeon_atombios_encoder_dpms_scratch_regs +ffffffff81c649f0 t radeon_atombios_parse_misc_flags_1_3 +ffffffff81c64be0 t radeon_atombios_add_pplib_thermal_controller +ffffffff81c64fe0 t radeon_atombios_parse_pplib_clock_info +ffffffff81c652f0 t radeon_atombios_parse_pplib_non_clock_info +ffffffff81c66000 T radeon_audio_init +ffffffff81c66280 T radeon_audio_endpoint_rreg +ffffffff81c662c0 T radeon_audio_endpoint_wreg +ffffffff81c66300 T radeon_audio_get_pin +ffffffff81c66350 T radeon_audio_detect +ffffffff81c66680 T radeon_audio_fini +ffffffff81c667b0 T radeon_audio_mode_set +ffffffff81c667f0 T radeon_audio_dpms +ffffffff81c66840 T radeon_audio_decode_dfs_div +ffffffff81c668a0 t radeon_audio_hdmi_mode_set +ffffffff81c66fd0 t radeon_audio_write_speaker_allocation +ffffffff81c67080 t radeon_audio_write_sad_regs +ffffffff81c67150 t radeon_audio_set_avi_packet +ffffffff81c67290 t radeon_audio_dp_mode_set +ffffffff81c67410 t radeon_audio_rreg +ffffffff81c67460 t radeon_audio_wreg +ffffffff81c68000 T radeon_benchmark +ffffffff81c68940 t radeon_benchmark_move +ffffffff81c68e00 t radeon_bo_reserve +ffffffff81c68f80 t radeon_bo_unreserve +ffffffff81c6a000 T radeon_get_bios +ffffffff81c6b000 t igp_read_bios_from_vram +ffffffff81c6b110 t radeon_read_bios +ffffffff81c6c000 T radeon_legacy_get_engine_clock +ffffffff81c6c0d0 T radeon_legacy_get_memory_clock +ffffffff81c6c1a0 T radeon_get_clock_info +ffffffff81c6c720 T radeon_legacy_set_engine_clock +ffffffff81c6ca70 T radeon_legacy_set_clock_gating +ffffffff81c6e000 T radeon_combios_check_hardcoded_edid +ffffffff81c6e100 T radeon_bios_get_hardcoded_edid +ffffffff81c6e180 T radeon_combios_i2c_init +ffffffff81c6e940 t combios_setup_i2c_bus +ffffffff81c6ec40 T radeon_combios_get_clock_info +ffffffff81c6ee30 T radeon_combios_sideport_present +ffffffff81c6eeb0 T radeon_combios_get_primary_dac_info +ffffffff81c6eff0 T radeon_combios_get_tv_info +ffffffff81c6f0f0 T radeon_combios_get_tv_dac_info +ffffffff81c6f390 T radeon_combios_get_lvds_info +ffffffff81c6f9e0 T radeon_legacy_get_tmds_info_from_table +ffffffff81c6fab0 T radeon_legacy_get_tmds_info_from_combios +ffffffff81c6fcb0 T radeon_legacy_get_ext_tmds_info_from_table +ffffffff81c6fef0 T radeon_legacy_get_ext_tmds_info_from_combios +ffffffff81c70280 T radeon_get_legacy_connector_info_from_table +ffffffff81c72640 T radeon_get_legacy_connector_info_from_bios +ffffffff81c733d0 T radeon_combios_get_power_modes +ffffffff81c73c80 T radeon_external_tmds_setup +ffffffff81c73d40 T radeon_combios_external_tmds_setup +ffffffff81c742f0 T radeon_combios_asic_init +ffffffff81c74910 t combios_parse_mmio_table +ffffffff81c74b30 t combios_parse_pll_table +ffffffff81c74e00 T radeon_combios_initialize_bios_scratch_regs +ffffffff81c74e90 T radeon_combios_output_lock +ffffffff81c74ee0 T radeon_combios_connected_scratch_regs +ffffffff81c75240 T radeon_combios_encoder_crtc_scratch_regs +ffffffff81c75310 T radeon_combios_encoder_dpms_scratch_regs +ffffffff81c76000 T radeon_connector_hotplug +ffffffff81c76100 T radeon_get_monitor_bpc +ffffffff81c76530 T radeon_connector_edid +ffffffff81c765e0 T radeon_connector_encoder_get_dp_bridge_encoder_id +ffffffff81c76650 T radeon_connector_is_dp12_capable +ffffffff81c766f0 T radeon_add_atom_connector +ffffffff81c77540 T radeon_add_legacy_connector +ffffffff81c77a80 t radeon_dp_detect +ffffffff81c77e40 t radeon_dvi_force +ffffffff81c77e80 t radeon_connector_set_property +ffffffff81c786c0 t radeon_connector_unregister +ffffffff81c78720 t radeon_connector_destroy +ffffffff81c78790 t radeon_best_single_encoder +ffffffff81c78810 t radeon_connector_get_edid +ffffffff81c78970 t radeon_dp_get_modes +ffffffff81c78ca0 t radeon_dp_mode_valid +ffffffff81c78e60 t radeon_dvi_encoder +ffffffff81c78f30 t radeon_fixup_lvds_native_mode +ffffffff81c79060 t radeon_add_common_modes +ffffffff81c79150 t radeon_fp_native_mode +ffffffff81c79220 t radeon_lvds_set_property +ffffffff81c79310 t radeon_vga_detect +ffffffff81c795c0 t radeon_connector_analog_encoder_conflict_solve +ffffffff81c797e0 t radeon_vga_get_modes +ffffffff81c798d0 t radeon_vga_mode_valid +ffffffff81c79930 t radeon_dvi_detect +ffffffff81c79fd0 t radeon_dvi_mode_valid +ffffffff81c7a160 t radeon_tv_detect +ffffffff81c7a3a0 t radeon_tv_get_modes +ffffffff81c7a470 t radeon_tv_mode_valid +ffffffff81c7a4c0 t radeon_lvds_detect +ffffffff81c7a660 t radeon_lvds_get_modes +ffffffff81c7a7c0 t radeon_lvds_mode_valid +ffffffff81c7b000 T radeon_cs_parser_init +ffffffff81c7b480 T radeon_cs_ioctl +ffffffff81c7bfb0 t radeon_cs_parser_fini +ffffffff81c7c140 T radeon_cs_packet_parse +ffffffff81c7c2f0 T radeon_cs_packet_next_is_pkt3_nop +ffffffff81c7c340 T radeon_cs_dump_packet +ffffffff81c7c3c0 T radeon_cs_packet_next_reloc +ffffffff81c7c590 t cmp_size_smaller_first +ffffffff81c7d000 T radeon_crtc_cursor_move +ffffffff81c7d070 t radeon_lock_cursor +ffffffff81c7d230 t radeon_cursor_move_locked +ffffffff81c7d780 T radeon_crtc_cursor_set2 +ffffffff81c7da00 t radeon_hide_cursor +ffffffff81c7dac0 t radeon_bo_reserve +ffffffff81c7dc40 t radeon_bo_unreserve +ffffffff81c7dd20 t radeon_show_cursor +ffffffff81c7df70 T radeon_cursor_reset +ffffffff81c7e000 T radeon_is_px +ffffffff81c7e040 T radeon_program_register_sequence +ffffffff81c7e170 T radeon_pci_config_reset +ffffffff81c7e1a0 T radeon_surface_init +ffffffff81c7e360 T radeon_scratch_init +ffffffff81c7e3e0 T radeon_scratch_get +ffffffff81c7e460 T radeon_scratch_free +ffffffff81c7e4b0 T radeon_doorbell_get +ffffffff81c7e550 T radeon_doorbell_free +ffffffff81c7e590 T radeon_wb_disable +ffffffff81c7e5c0 T radeon_wb_fini +ffffffff81c7e650 t radeon_bo_reserve +ffffffff81c7e7d0 t radeon_bo_unreserve +ffffffff81c7e8b0 T radeon_wb_init +ffffffff81c7eba0 T radeon_vram_location +ffffffff81c7ecd0 T radeon_gtt_location +ffffffff81c7ee00 T radeon_device_is_virtual +ffffffff81c7ee30 T radeon_card_posted +ffffffff81c7f040 T radeon_update_bandwidth_info +ffffffff81c7f0c0 T radeon_boot_test_post_card +ffffffff81c7f180 T radeon_dummy_page_init +ffffffff81c7f230 T radeon_dummy_page_fini +ffffffff81c7f290 T radeon_atombios_init +ffffffff81c7f420 t cail_reg_read +ffffffff81c7f480 t cail_reg_write +ffffffff81c7f4e0 t cail_ioreg_read +ffffffff81c7f500 t cail_ioreg_write +ffffffff81c7f520 t cail_mc_read +ffffffff81c7f540 t cail_mc_write +ffffffff81c7f560 t cail_pll_read +ffffffff81c7f580 t cail_pll_write +ffffffff81c7f5a0 T radeon_atombios_fini +ffffffff81c7f640 T radeon_combios_init +ffffffff81c7f680 T radeon_combios_fini +ffffffff81c7f6b0 T radeon_device_init +ffffffff81c80190 T radeon_device_fini +ffffffff81c80290 T radeon_suspend_kms +ffffffff81c80600 T radeon_resume_kms +ffffffff81c80850 T radeon_gpu_reset +ffffffff81c81000 T radeon_crtc_load_lut +ffffffff81c81dc0 T radeon_crtc_handle_vblank +ffffffff81c81f30 T radeon_get_crtc_scanoutpos +ffffffff81c82560 T radeon_crtc_handle_flip +ffffffff81c82690 T radeon_compute_pll_avivo +ffffffff81c82bd0 T radeon_compute_pll_legacy +ffffffff81c83250 T radeon_framebuffer_init +ffffffff81c832c0 T radeon_update_display_priority +ffffffff81c83320 T radeon_modeset_init +ffffffff81c83e40 T radeon_modeset_fini +ffffffff81c83f90 T radeon_crtc_scaling_mode_fixup +ffffffff81c842e0 T radeon_get_crtc_scanout_position +ffffffff81c84340 t radeon_user_framebuffer_create +ffffffff81c844e0 t radeon_crtc_gamma_set +ffffffff81c84520 t radeon_crtc_destroy +ffffffff81c84560 t radeon_crtc_set_config +ffffffff81c84620 t radeon_crtc_page_flip_target +ffffffff81c84ab0 t radeon_flip_work_func +ffffffff81c84cd0 t radeon_unpin_work_func +ffffffff81c84d50 t radeon_bo_reserve +ffffffff81c84ed0 t radeon_bo_unreserve +ffffffff81c85000 T radeon_dp_aux_transfer_native +ffffffff81c86000 T radeondrm_probe +ffffffff81c86060 T radeondrm_attach_kms +ffffffff81c867a0 T radeondrm_detach_kms +ffffffff81c86830 T radeondrm_activate_kms +ffffffff81c868e0 T radeondrm_wsioctl +ffffffff81c86990 T radeondrm_wsmmap +ffffffff81c869c0 T radeondrm_alloc_screen +ffffffff81c869e0 T radeondrm_free_screen +ffffffff81c869f0 T radeondrm_show_screen +ffffffff81c86ad0 T radeondrm_enter_ddb +ffffffff81c86b30 T radeondrm_doswitch +ffffffff81c86bc0 T radeondrm_setpal +ffffffff81c86dc0 T radeondrm_attachhook +ffffffff81c870f0 T radeondrm_forcedetach +ffffffff81c88000 T radeon_setup_encoder_clones +ffffffff81c880b0 T radeon_get_encoder_enum +ffffffff81c88230 T radeon_link_encoder_connector +ffffffff81c88370 T radeon_encoder_set_active_device +ffffffff81c88430 T radeon_get_connector_for_encoder +ffffffff81c884b0 T radeon_get_connector_for_encoder_init +ffffffff81c88530 T radeon_get_external_encoder +ffffffff81c885b0 T radeon_encoder_get_dp_bridge_encoder_id +ffffffff81c88640 T radeon_panel_mode_fixup +ffffffff81c88800 T radeon_dig_monitor_is_duallink +ffffffff81c88920 T radeon_encoder_is_digital +ffffffff81c89000 T radeon_align_pitch +ffffffff81c89080 T radeon_fbdev_init +ffffffff81c891d0 T radeondrm_burner_cb +ffffffff81c891f0 T radeon_fbdev_fini +ffffffff81c89260 T radeon_fbdev_set_suspend +ffffffff81c892a0 T radeon_fbdev_robj_is_fb +ffffffff81c892f0 T radeondrm_burner +ffffffff81c89370 t radeonfb_create +ffffffff81c89770 t radeon_bo_reserve +ffffffff81c898f0 t radeon_bo_unreserve +ffffffff81c8a000 T radeon_fence_emit +ffffffff81c8a120 T radeon_fence_process +ffffffff81c8a1f0 t radeon_fence_activity +ffffffff81c8a390 T radeon_fence_signaled +ffffffff81c8a420 T radeon_fence_wait_timeout +ffffffff81c8a560 t radeon_fence_wait_seq_timeout +ffffffff81c8a980 T radeon_fence_wait +ffffffff81c8aab0 T radeon_fence_wait_any +ffffffff81c8ac00 T radeon_fence_wait_next +ffffffff81c8acc0 T radeon_fence_wait_empty +ffffffff81c8add0 T radeon_fence_ref +ffffffff81c8ae10 T radeon_fence_unref +ffffffff81c8ae50 T radeon_fence_count_emitted +ffffffff81c8aed0 T radeon_fence_need_sync +ffffffff81c8af20 T radeon_fence_note_sync +ffffffff81c8b0f0 T radeon_fence_driver_start_ring +ffffffff81c8b2d0 T radeon_fence_driver_init +ffffffff81c8b410 T radeon_debugfs_fence_init +ffffffff81c8b440 T radeon_fence_driver_fini +ffffffff81c8b690 T radeon_fence_driver_force_completion +ffffffff81c8b790 t radeon_fence_get_driver_name +ffffffff81c8b7c0 t radeon_fence_get_timeline_name +ffffffff81c8b850 t radeon_fence_enable_signaling +ffffffff81c8ba60 t radeon_fence_is_signaled +ffffffff81c8bb20 t radeon_fence_default_wait +ffffffff81c8bcc0 t radeon_fence_any_seq_signaled +ffffffff81c8bec0 t radeon_fence_check_lockup +ffffffff81c8c110 t __delayed_work_tick +ffffffff81c8c130 t radeon_fence_check_signaled +ffffffff81c8c1c0 t radeon_fence_wait_cb +ffffffff81c8d000 T radeon_gart_table_ram_alloc +ffffffff81c8d0c0 T radeon_gart_table_ram_free +ffffffff81c8d120 T radeon_gart_table_vram_alloc +ffffffff81c8d190 T radeon_gart_table_vram_pin +ffffffff81c8d2d0 t radeon_bo_reserve +ffffffff81c8d450 t radeon_bo_unreserve +ffffffff81c8d530 T radeon_gart_table_vram_unpin +ffffffff81c8d5b0 T radeon_gart_table_vram_free +ffffffff81c8d5f0 T radeon_gart_unbind +ffffffff81c8d710 T radeon_gart_bind +ffffffff81c8d860 T radeon_gart_init +ffffffff81c8d990 T radeon_gart_fini +ffffffff81c8e000 T radeon_gem_fault +ffffffff81c8e180 T radeon_gem_vm_reference +ffffffff81c8e1b0 T radeon_gem_vm_detach +ffffffff81c8e1c0 T radeon_gem_object_create +ffffffff81c8e380 T radeon_gem_init +ffffffff81c8e3c0 T radeon_gem_fini +ffffffff81c8e3d0 t radeon_gem_object_free +ffffffff81c8e410 t radeon_gem_object_open +ffffffff81c8e4b0 t radeon_gem_object_close +ffffffff81c8e5a0 t radeon_gem_object_mmap +ffffffff81c8e630 T radeon_gem_info_ioctl +ffffffff81c8e6a0 T radeon_gem_pread_ioctl +ffffffff81c8e6f0 T radeon_gem_pwrite_ioctl +ffffffff81c8e740 T radeon_gem_create_ioctl +ffffffff81c8e860 T radeon_gem_userptr_ioctl +ffffffff81c8e890 T radeon_gem_set_domain_ioctl +ffffffff81c8e9f0 T radeon_mode_dumb_mmap +ffffffff81c8eaa0 T radeon_gem_mmap_ioctl +ffffffff81c8eb50 T radeon_gem_busy_ioctl +ffffffff81c8ec00 T radeon_gem_wait_idle_ioctl +ffffffff81c8ed10 T radeon_gem_set_tiling_ioctl +ffffffff81c8edc0 T radeon_gem_get_tiling_ioctl +ffffffff81c8ee90 t radeon_bo_reserve +ffffffff81c8f0a0 t radeon_bo_unreserve +ffffffff81c8f180 T radeon_gem_va_ioctl +ffffffff81c8f540 T radeon_gem_op_ioctl +ffffffff81c8f630 T radeon_mode_dumb_create +ffffffff81c8f730 T radeon_gem_debugfs_init +ffffffff81c90000 T radeon_ddc_probe +ffffffff81c900c0 T radeon_router_select_ddc_port +ffffffff81c90320 T radeon_bb_set_bits +ffffffff81c90490 T radeon_bb_set_dir +ffffffff81c904c0 T radeon_bb_read_bits +ffffffff81c90590 T radeon_acquire_bus +ffffffff81c909e0 T radeon_release_bus +ffffffff81c90b50 T radeon_send_start +ffffffff81c90b70 T radeon_send_stop +ffffffff81c90b90 T radeon_initiate_xfer +ffffffff81c90bb0 T radeon_read_byte +ffffffff81c90bd0 T radeon_write_byte +ffffffff81c90bf0 T radeon_i2c_create +ffffffff81c90df0 T radeon_i2c_destroy +ffffffff81c90e70 T radeon_i2c_init +ffffffff81c90ec0 T radeon_i2c_fini +ffffffff81c90f70 T radeon_i2c_add +ffffffff81c91120 T radeon_i2c_lookup +ffffffff81c912e0 T radeon_i2c_get_byte +ffffffff81c913a0 T radeon_i2c_put_byte +ffffffff81c91430 T radeon_router_select_cd_port +ffffffff81c91690 t radeon_hw_i2c_xfer +ffffffff81c92250 t radeon_hw_i2c_func +ffffffff81c92280 t r100_hw_i2c_xfer +ffffffff81c92960 t radeon_get_i2c_prescale +ffffffff81c93000 T radeon_ib_get +ffffffff81c93100 T radeon_ib_free +ffffffff81c93150 T radeon_ib_schedule +ffffffff81c933e0 T radeon_ib_pool_init +ffffffff81c93470 T radeon_ib_pool_fini +ffffffff81c934e0 T radeon_ib_ring_tests +ffffffff81c94000 T radeon_driver_irq_handler_kms +ffffffff81c94050 T radeon_msi_ok +ffffffff81c94150 T radeon_irq_kms_init +ffffffff81c943e0 t radeon_hotplug_work_func +ffffffff81c94480 t radeon_dp_work_func +ffffffff81c944b0 T radeon_irq_kms_fini +ffffffff81c94640 T radeon_irq_kms_sw_irq_get +ffffffff81c946e0 T radeon_irq_kms_sw_irq_get_delayed +ffffffff81c94720 T radeon_irq_kms_sw_irq_put +ffffffff81c947b0 T radeon_irq_kms_pflip_irq_get +ffffffff81c94860 T radeon_irq_kms_pflip_irq_put +ffffffff81c94900 T radeon_irq_kms_enable_afmt +ffffffff81c94990 T radeon_irq_kms_disable_afmt +ffffffff81c94a20 T radeon_irq_kms_enable_hpd +ffffffff81c94b00 T radeon_irq_kms_disable_hpd +ffffffff81c94bd0 T radeon_irq_kms_set_irq_n_enabled +ffffffff81c94d40 t __delayed_work_tick +ffffffff81c95000 T radeon_info_ioctl +ffffffff81c95be0 T radeon_driver_lastclose_kms +ffffffff81c95bf0 T radeon_driver_open_kms +ffffffff81c95d20 t radeon_bo_reserve +ffffffff81c95ea0 T radeon_driver_postclose_kms +ffffffff81c960c0 T radeon_get_vblank_counter_kms +ffffffff81c96250 T radeon_enable_vblank_kms +ffffffff81c962f0 T radeon_disable_vblank_kms +ffffffff81c97000 T radeon_crtc_set_base +ffffffff81c97020 T radeon_crtc_do_set_base +ffffffff81c975c0 T radeon_crtc_set_base_atomic +ffffffff81c975e0 t radeon_bo_reserve +ffffffff81c97760 t radeon_bo_unreserve +ffffffff81c97840 T radeon_legacy_init_crtc +ffffffff81c97880 t radeon_crtc_dpms +ffffffff81c97a80 t radeon_crtc_prepare +ffffffff81c97af0 t radeon_crtc_commit +ffffffff81c97b60 t radeon_crtc_mode_fixup +ffffffff81c97b70 t radeon_crtc_mode_set +ffffffff81c98fc0 t radeon_crtc_disable +ffffffff81c9a000 T radeon_legacy_get_backlight_level +ffffffff81c9a040 T radeon_legacy_set_backlight_level +ffffffff81c9a080 t radeon_legacy_lvds_update +ffffffff81c9a3e0 T radeon_legacy_backlight_init +ffffffff81c9a5b0 t radeon_legacy_backlight_get_brightness +ffffffff81c9a610 T radeon_add_legacy_encoder +ffffffff81c9a990 t radeon_legacy_backlight_update_status +ffffffff81c9aa20 t radeon_lvds_enc_destroy +ffffffff81c9aab0 t radeon_legacy_lvds_dpms +ffffffff81c9ab00 t radeon_legacy_mode_fixup +ffffffff81c9ab70 t radeon_legacy_lvds_prepare +ffffffff81c9abf0 t radeon_legacy_lvds_commit +ffffffff81c9ac70 t radeon_legacy_lvds_mode_set +ffffffff81c9ae80 t radeon_legacy_encoder_disable +ffffffff81c9aed0 t radeon_legacy_tmds_int_dpms +ffffffff81c9af90 t radeon_legacy_tmds_int_prepare +ffffffff81c9b050 t radeon_legacy_tmds_int_commit +ffffffff81c9b120 t radeon_legacy_tmds_int_mode_set +ffffffff81c9b380 t radeon_legacy_primary_dac_dpms +ffffffff81c9b4b0 t radeon_legacy_primary_dac_prepare +ffffffff81c9b500 t radeon_legacy_primary_dac_commit +ffffffff81c9b550 t radeon_legacy_primary_dac_mode_set +ffffffff81c9b6f0 t radeon_legacy_primary_dac_detect +ffffffff81c9b8e0 t radeon_legacy_tv_dac_dpms +ffffffff81c9bad0 t radeon_legacy_tv_dac_prepare +ffffffff81c9bb20 t radeon_legacy_tv_dac_commit +ffffffff81c9bb70 t radeon_legacy_tv_dac_mode_set +ffffffff81c9bf10 t radeon_legacy_tv_dac_detect +ffffffff81c9cb30 t radeon_ext_tmds_enc_destroy +ffffffff81c9cb70 t radeon_legacy_tmds_ext_dpms +ffffffff81c9cc40 t radeon_legacy_tmds_ext_prepare +ffffffff81c9cd10 t radeon_legacy_tmds_ext_commit +ffffffff81c9cde0 t radeon_legacy_tmds_ext_mode_set +ffffffff81c9d000 T radeon_legacy_tv_mode_set +ffffffff81c9e0a0 T radeon_legacy_tv_adjust_crtc_reg +ffffffff81c9e1b0 T radeon_legacy_tv_adjust_pll1 +ffffffff81c9e2a0 T radeon_legacy_tv_adjust_pll2 +ffffffff81c9f000 T radeon_ttm_bo_is_radeon_bo +ffffffff81c9f040 t radeon_ttm_bo_destroy +ffffffff81c9f170 T radeon_ttm_placement_from_domain +ffffffff81c9f2e0 T radeon_bo_create +ffffffff81c9f4a0 T radeon_bo_kmap +ffffffff81c9f580 T radeon_bo_check_tiling +ffffffff81c9f650 T radeon_bo_kunmap +ffffffff81c9f6d0 T radeon_bo_ref +ffffffff81c9f710 T radeon_bo_unref +ffffffff81c9f760 T radeon_bo_pin_restricted +ffffffff81c9fa90 T radeon_bo_pin +ffffffff81c9fab0 T radeon_bo_unpin +ffffffff81c9fb20 T radeon_bo_evict_vram +ffffffff81c9fb70 T radeon_bo_force_delete +ffffffff81c9fce0 T radeon_bo_init +ffffffff81c9fdc0 T radeon_bo_fini +ffffffff81c9fe00 T radeon_bo_list_validate +ffffffff81ca00f0 T radeon_bo_get_surface_reg +ffffffff81ca0390 T radeon_bo_set_tiling_flags +ffffffff81ca06b0 T radeon_bo_get_tiling_flags +ffffffff81ca06f0 T radeon_bo_move_notify +ffffffff81ca07b0 T radeon_bo_fault_reserve_notify +ffffffff81ca0ab0 T radeon_bo_fence +ffffffff81ca1000 T radeon_pm_get_type_index +ffffffff81ca1070 T radeon_pm_acpi_event_handler +ffffffff81ca1150 t radeon_pm_update_profile +ffffffff81ca1270 t radeon_pm_set_clocks +ffffffff81ca1c10 T radeon_dpm_enable_uvd +ffffffff81ca1cd0 T radeon_pm_compute_clocks +ffffffff81ca2700 T radeon_dpm_enable_vce +ffffffff81ca2760 T radeon_pm_suspend +ffffffff81ca2860 T radeon_pm_resume +ffffffff81ca2b40 T radeon_pm_init +ffffffff81ca3230 T radeon_pm_late_init +ffffffff81ca32e0 T radeon_pm_fini +ffffffff81ca33f0 t radeon_dpm_thermal_work_handler +ffffffff81ca34d0 t radeon_dynpm_idle_work_handler +ffffffff81ca37c0 t __delayed_work_tick +ffffffff81ca4000 T radeon_gem_prime_get_sg_table +ffffffff81ca4020 T radeon_gem_prime_pin +ffffffff81ca40a0 t radeon_bo_reserve +ffffffff81ca4220 t radeon_bo_unreserve +ffffffff81ca4300 T radeon_gem_prime_unpin +ffffffff81ca4370 T radeon_gem_prime_export +ffffffff81ca5000 T radeon_ring_supports_scratch_reg +ffffffff81ca5030 T radeon_ring_free_size +ffffffff81ca50d0 T radeon_ring_lockup_update +ffffffff81ca5130 T radeon_ring_alloc +ffffffff81ca52b0 T radeon_ring_lock +ffffffff81ca5330 T radeon_ring_commit +ffffffff81ca5430 T radeon_ring_unlock_commit +ffffffff81ca5460 T radeon_ring_undo +ffffffff81ca5490 T radeon_ring_unlock_undo +ffffffff81ca54b0 T radeon_ring_test_lockup +ffffffff81ca55d0 T radeon_ring_backup +ffffffff81ca5790 T radeon_ring_restore +ffffffff81ca5950 T radeon_ring_init +ffffffff81ca5b40 t radeon_bo_reserve +ffffffff81ca5cc0 t radeon_bo_unreserve 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radeon_test_ring_sync2 +ffffffff81cab0c0 t radeon_bo_reserve +ffffffff81cab240 t radeon_bo_unreserve +ffffffff81cac000 T radeon_get_rdev +ffffffff81cac030 T radeon_ttm_tt_set_userptr +ffffffff81cac080 T radeon_ttm_tt_is_bound +ffffffff81cac0c0 T radeon_ttm_tt_has_userptr +ffffffff81cac100 T radeon_ttm_tt_is_readonly +ffffffff81cac140 T radeon_ttm_init +ffffffff81cac350 T radeon_ttm_set_active_vram_size +ffffffff81cac390 t radeon_bo_reserve +ffffffff81cac510 t radeon_bo_unreserve +ffffffff81cac5f0 T radeon_ttm_fini +ffffffff81cac6c0 t radeon_ttm_tt_create +ffffffff81cac7b0 t radeon_ttm_tt_populate +ffffffff81cac860 t radeon_ttm_tt_unpopulate +ffffffff81cac950 t radeon_ttm_tt_destroy +ffffffff81cac9a0 t radeon_evict_flags +ffffffff81cacaf0 t radeon_bo_move +ffffffff81cacf70 t radeon_ttm_io_mem_reserve +ffffffff81cae000 T radeon_ucode_print_mc_hdr +ffffffff81cae0b0 t radeon_ucode_print_common_hdr +ffffffff81cae1e0 T radeon_ucode_print_smc_hdr +ffffffff81cae270 T radeon_ucode_print_gfx_hdr +ffffffff81cae330 T radeon_ucode_print_rlc_hdr +ffffffff81cae430 T radeon_ucode_print_sdma_hdr +ffffffff81cae510 T radeon_ucode_validate +ffffffff81caf000 T radeon_uvd_init +ffffffff81caf4f0 t radeon_uvd_idle_work_handler +ffffffff81caf650 t radeon_bo_reserve +ffffffff81caf860 t radeon_bo_unreserve +ffffffff81caf940 T radeon_uvd_fini +ffffffff81cafa00 T radeon_uvd_suspend +ffffffff81cafbc0 T radeon_uvd_note_usage +ffffffff81cafe00 T radeon_uvd_get_destroy_msg +ffffffff81caff10 T radeon_uvd_resume +ffffffff81caffa0 T radeon_uvd_force_into_uvd_segment +ffffffff81cb0040 T radeon_uvd_free_handles +ffffffff81cb0200 T radeon_uvd_cs_parse +ffffffff81cb0920 T radeon_uvd_get_create_msg +ffffffff81cb0a90 t radeon_uvd_send_msg +ffffffff81cb0c30 T radeon_uvd_calc_upll_dividers +ffffffff81cb0dd0 T radeon_uvd_send_upll_ctlreq +ffffffff81cb1100 t __delayed_work_tick +ffffffff81cb2000 T radeon_vce_init +ffffffff81cb2600 t radeon_vce_idle_work_handler +ffffffff81cb26d0 t radeon_bo_reserve +ffffffff81cb2850 t radeon_bo_unreserve +ffffffff81cb2930 T radeon_vce_fini +ffffffff81cb29b0 T radeon_vce_suspend +ffffffff81cb2a90 T radeon_vce_resume +ffffffff81cb2be0 T radeon_vce_note_usage +ffffffff81cb2d00 T radeon_vce_free_handles +ffffffff81cb2dc0 T radeon_vce_get_destroy_msg +ffffffff81cb3060 T radeon_vce_get_create_msg +ffffffff81cb3420 T radeon_vce_cs_reloc +ffffffff81cb3510 T radeon_vce_cs_parse +ffffffff81cb3d40 T radeon_vce_semaphore_emit +ffffffff81cb3f00 T radeon_vce_ib_execute +ffffffff81cb40a0 T radeon_vce_fence_emit +ffffffff81cb42e0 T radeon_vce_ring_test +ffffffff81cb4420 T radeon_vce_ib_test +ffffffff81cb4530 t __delayed_work_tick +ffffffff81cb5000 T radeon_vm_manager_init +ffffffff81cb5060 T radeon_vm_manager_fini +ffffffff81cb5180 T radeon_vm_get_bos +ffffffff81cb52b0 T radeon_vm_grab_id +ffffffff81cb5440 T radeon_vm_flush +ffffffff81cb55c0 T radeon_vm_fence +ffffffff81cb5670 T radeon_vm_bo_find +ffffffff81cb56d0 T radeon_vm_bo_add +ffffffff81cb57b0 T radeon_vm_bo_set_addr +ffffffff81cb5c10 t radeon_bo_unreserve +ffffffff81cb5cf0 t radeon_vm_clear_bo +ffffffff81cb5ee0 T radeon_vm_map_gart +ffffffff81cb5f20 T radeon_vm_update_page_directory +ffffffff81cb62c0 T radeon_vm_bo_update +ffffffff81cb69a0 T radeon_vm_clear_freed +ffffffff81cb6a80 T radeon_vm_clear_invalids +ffffffff81cb6b20 T radeon_vm_bo_rmv +ffffffff81cb6c00 T radeon_vm_bo_invalidate +ffffffff81cb6cb0 T radeon_vm_init +ffffffff81cb6f10 T radeon_vm_fini +ffffffff81cb71e0 t radeon_bo_reserve +ffffffff81cb7360 t radeon_vm_frag_ptes +ffffffff81cb8000 T rs400_gart_adjust_size +ffffffff81cb80c0 T rs400_gart_tlb_flush +ffffffff81cb8140 T rs400_gart_init +ffffffff81cb8230 T rs400_gart_enable +ffffffff81cb8590 T rs400_gart_disable +ffffffff81cb85f0 T rs400_gart_fini +ffffffff81cb8660 T rs400_gart_get_page_entry +ffffffff81cb86c0 T rs400_gart_set_page +ffffffff81cb86f0 T rs400_mc_wait_for_idle +ffffffff81cb8780 T rs400_mc_rreg +ffffffff81cb8810 T rs400_mc_wreg +ffffffff81cb8890 T rs400_resume +ffffffff81cb89c0 t rs400_mc_program +ffffffff81cb8ac0 t rs400_startup +ffffffff81cb8cb0 T rs400_suspend +ffffffff81cb8d40 T rs400_fini +ffffffff81cb8e30 T rs400_init +ffffffff81cba000 T avivo_wait_for_vblank +ffffffff81cba280 T rs600_page_flip +ffffffff81cba540 T rs600_page_flip_pending +ffffffff81cba5b0 T avivo_program_fmt +ffffffff81cba6d0 T rs600_pm_misc +ffffffff81cbaa10 T rs600_pm_prepare +ffffffff81cbab10 T rs600_pm_finish +ffffffff81cbac10 T rs600_hpd_sense +ffffffff81cbac70 T rs600_hpd_set_polarity +ffffffff81cbad20 T rs600_hpd_init +ffffffff81cbae00 T rs600_hpd_fini +ffffffff81cbaea0 T rs600_asic_reset +ffffffff81cbb110 T rs600_gart_tlb_flush +ffffffff81cbb1d0 T rs600_gart_get_page_entry +ffffffff81cbb230 T rs600_gart_set_page +ffffffff81cbb270 T rs600_irq_set +ffffffff81cbb440 T rs600_irq_disable +ffffffff81cbb4c0 t rs600_irq_ack +ffffffff81cbb670 T rs600_irq_process +ffffffff81cbb9e0 T rs600_get_vblank_counter +ffffffff81cbba30 T rs600_mc_wait_for_idle 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rs780_enable_voltage_scaling +ffffffff81cc0380 T rs780_dpm_setup_asic +ffffffff81cc03b0 T rs780_dpm_display_configuration_changed +ffffffff81cc04f0 T rs780_dpm_init +ffffffff81cc0a50 T rs780_dpm_print_power_state +ffffffff81cc0ae0 T rs780_dpm_fini +ffffffff81cc0b70 T rs780_dpm_get_sclk +ffffffff81cc0bb0 T rs780_dpm_get_mclk +ffffffff81cc0be0 T rs780_dpm_debugfs_print_current_performance_level +ffffffff81cc0c10 T rs780_dpm_get_current_sclk +ffffffff81cc0c90 T rs780_dpm_get_current_mclk +ffffffff81cc0cc0 T rs780_dpm_force_performance_level +ffffffff81cc0ea0 t rs780_force_fbdiv +ffffffff81cc1000 T rv515_ring_start +ffffffff81cc1b30 T rv515_mc_wait_for_idle +ffffffff81cc1bc0 T rv515_vga_render_disable +ffffffff81cc1c10 T rv515_mc_rreg +ffffffff81cc1ca0 T rv515_mc_wreg +ffffffff81cc1d20 T rv515_debugfs +ffffffff81cc1d30 T rv515_mc_stop +ffffffff81cc22c0 T rv515_mc_resume +ffffffff81cc28c0 T rv515_clock_startup +ffffffff81cc2980 T rv515_resume +ffffffff81cc2bc0 t rv515_startup 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+ffffffff81cca660 T rv6xx_dpm_get_current_mclk +ffffffff81cca6d0 T rv6xx_dpm_fini +ffffffff81cca760 T rv6xx_dpm_get_sclk +ffffffff81cca7a0 T rv6xx_dpm_get_mclk +ffffffff81cca7e0 T rv6xx_dpm_force_performance_level +ffffffff81cca960 t rv6xx_generate_steps +ffffffff81ccac70 t rv6xx_output_stepping +ffffffff81ccad90 t rv6xx_program_mclk_stepping_entry +ffffffff81ccb000 t rv6xx_program_engine_spread_spectrum +ffffffff81ccb2e0 t rv6xx_step_sw_voltage +ffffffff81ccc000 T rv730_populate_sclk_value +ffffffff81ccc240 T rv730_populate_mclk_value +ffffffff81ccc460 T rv730_read_clock_registers +ffffffff81ccc580 T rv730_populate_smc_acpi_state +ffffffff81ccc730 T rv730_populate_smc_initial_state +ffffffff81ccc8e0 T rv730_program_memory_timing_parameters +ffffffff81cccac0 T rv730_start_dpm +ffffffff81cccb50 T rv730_stop_dpm +ffffffff81cccc10 T rv730_program_dcodt +ffffffff81cccce0 T rv730_get_odt_values +ffffffff81ccd000 T rv740_get_decoded_reference_divider +ffffffff81ccd0a0 T rv740_get_dll_speed +ffffffff81ccd1d0 T rv740_populate_sclk_value +ffffffff81ccd3e0 T rv740_populate_mclk_value +ffffffff81ccd820 T rv740_read_clock_registers +ffffffff81ccd950 T rv740_populate_smc_acpi_state +ffffffff81ccdb80 T rv740_enable_mclk_spread_spectrum +ffffffff81ccdbe0 T rv740_get_mclk_frequency_ratio +ffffffff81cce000 T rv770_set_uvd_clocks +ffffffff81cce570 T rv770_get_xclk +ffffffff81cce5d0 T rv770_page_flip +ffffffff81cce8e0 T rv770_page_flip_pending +ffffffff81cce950 T rv770_get_temp +ffffffff81cce9b0 T rv770_pm_misc +ffffffff81ccea80 T r700_cp_stop +ffffffff81cceb00 T r700_cp_fini +ffffffff81cceb80 T rv770_set_clk_bypass_mode +ffffffff81cceca0 T r700_vram_gtt_location +ffffffff81ccee30 T rv770_resume +ffffffff81cceec0 t rv770_init_golden_registers +ffffffff81ccf050 t rv770_startup +ffffffff81cd1040 T rv770_suspend +ffffffff81cd1260 T rv770_init +ffffffff81cd1820 T rv770_fini +ffffffff81cd2000 T rv770_copy_dma +ffffffff81cd3000 T rv770_get_ps +ffffffff81cd3030 T rv770_get_pi +ffffffff81cd3060 T evergreen_get_pi +ffffffff81cd3090 T rv770_restore_cgcg +ffffffff81cd3100 T rv770_stop_dpm +ffffffff81cd31c0 T rv770_dpm_enabled +ffffffff81cd3200 T rv770_enable_thermal_protection +ffffffff81cd3260 T rv770_enable_acpi_pm +ffffffff81cd32b0 T rv770_get_seq_value +ffffffff81cd32e0 T rv770_write_smc_soft_register +ffffffff81cd3310 T rv770_populate_smc_t +ffffffff81cd34a0 T rv770_populate_smc_sp +ffffffff81cd3500 T rv770_map_clkf_to_ibias +ffffffff81cd3560 T rv770_populate_vddc_value +ffffffff81cd3600 T rv770_populate_mvdd_value +ffffffff81cd3650 T rv770_calculate_memory_refresh_rate +ffffffff81cd36c0 T rv770_enable_backbias +ffffffff81cd3720 T rv770_setup_bsp +ffffffff81cd3800 T rv770_program_git +ffffffff81cd3850 T rv770_program_tp +ffffffff81cd38d0 T rv770_program_tpp +ffffffff81cd3910 T rv770_program_sstp +ffffffff81cd3950 T rv770_program_engine_speed_parameters +ffffffff81cd39a0 T rv770_program_vc +ffffffff81cd39e0 T rv770_clear_vc +ffffffff81cd3a20 T rv770_upload_firmware +ffffffff81cd3a60 T rv770_populate_initial_mvdd_value +ffffffff81cd3ab0 T rv770_get_memory_module_index +ffffffff81cd3af0 T rv770_enable_voltage_control +ffffffff81cd3b50 T rv770_halt_smc +ffffffff81cd3bb0 T rv770_resume_smc +ffffffff81cd3c00 T rv770_set_sw_state +ffffffff81cd3c60 T rv770_set_boot_state +ffffffff81cd3cb0 T rv770_set_uvd_clock_before_set_eng_clock +ffffffff81cd3d10 T rv770_set_uvd_clock_after_set_eng_clock +ffffffff81cd3d80 T rv770_restrict_performance_levels_before_switch +ffffffff81cd3de0 T rv770_dpm_force_performance_level +ffffffff81cd3ea0 T r7xx_start_smc +ffffffff81cd3ec0 T r7xx_stop_smc +ffffffff81cd3ee0 T rv770_read_voltage_smio_registers +ffffffff81cd3f20 T rv770_reset_smio_status +ffffffff81cd3fd0 T rv770_get_memory_type +ffffffff81cd4020 T rv770_get_pcie_gen2_status +ffffffff81cd4090 T rv770_get_max_vddc +ffffffff81cd40f0 T rv770_program_response_times +ffffffff81cd4230 T rv770_enable_auto_throttle_source +ffffffff81cd43a0 T rv770_dpm_enable +ffffffff81cd5420 T rv770_dpm_late_enable +ffffffff81cd5550 T rv770_dpm_disable +ffffffff81cd58b0 T rv770_dpm_set_power_state +ffffffff81cd5ea0 T rv770_dpm_setup_asic +ffffffff81cd6200 T rv770_dpm_display_configuration_changed +ffffffff81cd6280 T rv7xx_parse_power_table +ffffffff81cd67c0 T rv770_get_engine_memory_ss +ffffffff81cd6850 T rv770_dpm_init +ffffffff81cd6a80 T rv770_dpm_print_power_state +ffffffff81cd6ba0 T rv770_dpm_debugfs_print_current_performance_level +ffffffff81cd6bd0 T rv770_dpm_get_current_sclk +ffffffff81cd6c30 T rv770_dpm_get_current_mclk +ffffffff81cd6c90 T rv770_dpm_fini +ffffffff81cd6d20 T rv770_dpm_get_sclk +ffffffff81cd6d60 T rv770_dpm_get_mclk +ffffffff81cd6da0 T rv770_dpm_vblank_too_short +ffffffff81cd6e00 t rv770_convert_power_level_to_smc +ffffffff81cd8000 T rv770_copy_bytes_to_smc +ffffffff81cd8230 T rv770_start_smc +ffffffff81cd8280 T rv770_reset_smc +ffffffff81cd82d0 T rv770_stop_smc_clock +ffffffff81cd8320 T rv770_start_smc_clock +ffffffff81cd8370 T rv770_is_smc_running +ffffffff81cd83b0 T rv770_send_msg_to_smc +ffffffff81cd8480 T rv770_wait_for_smc_inactive +ffffffff81cd8510 T rv770_load_smc_ucode +ffffffff81cd8690 T rv770_read_smc_sram_dword +ffffffff81cd8740 T rv770_write_smc_sram_dword +ffffffff81cd9000 T si_get_allowed_info_register +ffffffff81cd9090 T si_get_xclk +ffffffff81cd9100 T si_get_temp +ffffffff81cd9140 T si_mc_load_microcode +ffffffff81cd9410 T dce6_bandwidth_update +ffffffff81cd9810 t dce6_program_watermarks +ffffffff81cda2c0 T si_fence_ring_emit +ffffffff81cda730 T si_ring_ib_execute +ffffffff81cdaf00 T si_gpu_check_soft_reset +ffffffff81cdb090 T si_asic_reset +ffffffff81cdb4a0 t si_gpu_pci_config_reset +ffffffff81cdb850 T si_gfx_is_lockup +ffffffff81cdb8b0 T si_vram_gtt_location +ffffffff81cdb950 T si_pcie_gart_tlb_flush +ffffffff81cdb9a0 T si_ib_parse +ffffffff81cdc050 T si_vm_init +ffffffff81cdc090 T si_vm_fini +ffffffff81cdc0c0 T si_vm_flush +ffffffff81cdc7a0 T si_init_uvd_internal_cg +ffffffff81cdc7e0 T si_get_csb_size +ffffffff81cdc870 T si_get_csb_buffer +ffffffff81cdca00 T si_rlc_reset +ffffffff81cdca70 T si_irq_set +ffffffff81cdcf70 t si_disable_interrupt_state +ffffffff81cdd1f0 T si_irq_process +ffffffff81cde3f0 t si_irq_ack +ffffffff81cde9f0 T si_resume +ffffffff81cdea80 t si_init_golden_registers +ffffffff81cdec40 t si_startup +ffffffff81ce3470 T si_suspend +ffffffff81ce37f0 T si_init +ffffffff81ce4cc0 t si_cp_fini +ffffffff81ce4db0 t si_pcie_gart_fini +ffffffff81ce4eb0 T si_fini +ffffffff81ce5150 T si_get_gpu_clock_counter +ffffffff81ce5210 T si_set_uvd_clocks +ffffffff81ce5780 T si_set_vce_clocks +ffffffff81ce5cc0 t si_vce_send_vcepll_ctlreq +ffffffff81ce5f00 t dce6_latency_watermark +ffffffff81ce6130 t si_rlc_stop +ffffffff81ce62e0 t si_vm_reg_valid +ffffffff81ce6440 t si_vm_packet3_cp_dma_check +ffffffff81ce65c0 t si_update_cg +ffffffff81ce6b10 t si_enable_mgcg +ffffffff81ce6f30 t si_enable_cgcg +ffffffff81ce8000 T si_dma_is_lockup +ffffffff81ce8080 T si_dma_vm_copy_pages +ffffffff81ce8160 T si_dma_vm_write_pages +ffffffff81ce82c0 T si_dma_vm_set_pages +ffffffff81ce8420 T si_dma_vm_flush +ffffffff81ce88b0 T si_copy_dma +ffffffff81ce9000 T si_dpm_force_performance_level +ffffffff81ce9160 T si_get_ddr3_mclk_frequency_ratio +ffffffff81ce91b0 T si_get_mclk_frequency_ratio +ffffffff81ce9230 T si_trim_voltage_table_to_fit_state_table +ffffffff81ce9330 T si_dpm_setup_asic +ffffffff81ce94f0 T si_fan_ctrl_get_fan_speed_percent +ffffffff81ce9580 T si_fan_ctrl_set_fan_speed_percent +ffffffff81ce9630 T si_fan_ctrl_set_mode +ffffffff81ce9870 T si_fan_ctrl_get_mode +ffffffff81ce98c0 T si_dpm_enable +ffffffff81ceebc0 t si_populate_smc_tdp_limits +ffffffff81ceedd0 T si_dpm_late_enable +ffffffff81ceef20 T si_dpm_disable +ffffffff81cef290 T si_dpm_pre_set_power_state +ffffffff81cefe90 T si_dpm_set_power_state +ffffffff81cf1410 T si_dpm_post_set_power_state +ffffffff81cf1440 T si_dpm_display_configuration_changed +ffffffff81cf1520 T si_dpm_init +ffffffff81cf2fd0 T si_dpm_fini +ffffffff81cf3080 T si_dpm_debugfs_print_current_performance_level +ffffffff81cf30c0 T si_dpm_get_current_sclk +ffffffff81cf3130 T si_dpm_get_current_mclk +ffffffff81cf31a0 t si_get_std_voltage_value +ffffffff81cf32d0 t si_convert_power_level_to_smc +ffffffff81cf3b70 t si_calculate_sclk_params +ffffffff81cf3d90 t si_convert_mc_reg_table_to_smc +ffffffff81cf3ef0 t si_program_cac_config_registers +ffffffff81cf5000 T si_copy_bytes_to_smc +ffffffff81cf5250 T si_start_smc +ffffffff81cf5280 T si_reset_smc +ffffffff81cf52c0 T si_program_jump_on_start +ffffffff81cf52f0 T si_stop_smc_clock +ffffffff81cf5320 T si_start_smc_clock +ffffffff81cf5350 T si_is_smc_running +ffffffff81cf53b0 T si_send_msg_to_smc +ffffffff81cf5480 T si_wait_for_smc_inactive +ffffffff81cf5520 T si_load_smc_ucode +ffffffff81cf56c0 T si_read_smc_sram_dword +ffffffff81cf5790 T si_write_smc_sram_dword +ffffffff81cf6000 T sumo_get_pi +ffffffff81cf6030 T sumo_gfx_clockgating_initialize +ffffffff81cf6110 T sumo_program_vc +ffffffff81cf6150 T sumo_clear_vc +ffffffff81cf6190 T sumo_program_sstp +ffffffff81cf6210 T sumo_take_smu_control +ffffffff81cf6240 T sumo_get_sleep_divider_from_id +ffffffff81cf6270 T sumo_get_sleep_divider_id_from_clock +ffffffff81cf6320 T sumo_dpm_enable +ffffffff81cf69c0 T sumo_dpm_late_enable +ffffffff81cf6f80 T sumo_dpm_disable +ffffffff81cf72d0 T sumo_dpm_pre_set_power_state +ffffffff81cf7780 T sumo_dpm_set_power_state +ffffffff81cf82c0 T sumo_dpm_post_set_power_state +ffffffff81cf8360 T sumo_dpm_setup_asic +ffffffff81cf8460 T sumo_dpm_display_configuration_changed +ffffffff81cf8490 T sumo_convert_vid2_to_vid7 +ffffffff81cf84f0 T sumo_construct_sclk_voltage_mapping_table +ffffffff81cf85b0 T sumo_construct_vid_mapping_table +ffffffff81cf8730 T sumo_dpm_init +ffffffff81cf8ff0 T sumo_dpm_print_power_state +ffffffff81cf9110 T sumo_dpm_debugfs_print_current_performance_level +ffffffff81cf9140 T sumo_dpm_get_current_sclk +ffffffff81cf91b0 T sumo_dpm_get_current_mclk +ffffffff81cf91e0 T sumo_dpm_get_current_vddc +ffffffff81cf92b0 T sumo_dpm_fini +ffffffff81cf9340 T sumo_dpm_get_sclk +ffffffff81cf9390 T sumo_dpm_get_mclk +ffffffff81cf93c0 T sumo_dpm_force_performance_level +ffffffff81cf97e0 t sumo_power_level_enable +ffffffff81cf9a10 t sumo_program_power_level +ffffffff81cfa000 T sumo_initialize_m3_arb +ffffffff81cfa2b0 T sumo_smu_notify_alt_vddnb_change +ffffffff81cfa340 t sumo_send_msg_to_smu +ffffffff81cfa4e0 T sumo_smu_pg_init +ffffffff81cfa500 T sumo_enable_boost_timer +ffffffff81cfa630 T sumo_set_tdp_limit +ffffffff81cfa6b0 T sumo_boost_state_enable +ffffffff81cfa6f0 T sumo_get_running_fw_version +ffffffff81cfb000 T trinity_dpm_enable_bapm +ffffffff81cfb070 T trinity_dpm_enable +ffffffff81cfb510 T trinity_dpm_late_enable +ffffffff81cfba60 T trinity_dpm_disable +ffffffff81cfbe70 T trinity_dpm_force_performance_level +ffffffff81cfbf20 T trinity_dpm_pre_set_power_state +ffffffff81cfc4e0 T trinity_dpm_set_power_state +ffffffff81cfca70 T trinity_dpm_post_set_power_state +ffffffff81cfcb10 T trinity_dpm_setup_asic +ffffffff81cfcb70 T trinity_dpm_display_configuration_changed +ffffffff81cfcc00 T trinity_dpm_init +ffffffff81cfd4f0 T trinity_dpm_print_power_state +ffffffff81cfd600 T trinity_dpm_debugfs_print_current_performance_level +ffffffff81cfd690 T trinity_dpm_get_current_sclk +ffffffff81cfd6f0 T trinity_dpm_get_current_mclk +ffffffff81cfd720 T trinity_dpm_fini +ffffffff81cfd7c0 T trinity_dpm_get_sclk +ffffffff81cfd810 T trinity_dpm_get_mclk +ffffffff81cfd840 t trinity_program_power_level +ffffffff81cfe000 T trinity_dpm_bapm_enable +ffffffff81cfe140 T trinity_dpm_config +ffffffff81cfe220 T trinity_dpm_force_state +ffffffff81cfe300 T trinity_dpm_n_levels_disabled +ffffffff81cfe3e0 T trinity_uvd_dpm_config +ffffffff81cfe4b0 T trinity_dpm_no_forced_level +ffffffff81cfe580 T trinity_dce_enable_voltage_adjustment +ffffffff81cfe6c0 T trinity_gfx_dynamic_mgpg_config +ffffffff81cfe790 T trinity_acquire_mutex +ffffffff81cfe820 T trinity_release_mutex +ffffffff81cff000 T uvd_v1_0_get_rptr +ffffffff81cff040 T uvd_v1_0_get_wptr +ffffffff81cff080 T uvd_v1_0_set_wptr +ffffffff81cff0c0 T uvd_v1_0_fence_emit +ffffffff81cff4b0 T uvd_v1_0_resume +ffffffff81cff600 T uvd_v1_0_init +ffffffff81cffb90 T uvd_v1_0_start +ffffffff81d00310 T uvd_v1_0_fini +ffffffff81d00480 T uvd_v1_0_stop +ffffffff81d005e0 T uvd_v1_0_ring_test +ffffffff81d007b0 T uvd_v1_0_semaphore_emit +ffffffff81d007e0 T uvd_v1_0_ib_execute +ffffffff81d00970 T uvd_v1_0_ib_test +ffffffff81d01000 T uvd_v2_2_fence_emit +ffffffff81d01470 T uvd_v2_2_semaphore_emit +ffffffff81d01670 T uvd_v2_2_resume +ffffffff81d02000 T uvd_v3_1_semaphore_emit +ffffffff81d03000 T uvd_v4_2_resume +ffffffff81d04000 T vce_v1_0_get_rptr +ffffffff81d04090 T vce_v1_0_get_wptr +ffffffff81d04120 T vce_v1_0_set_wptr +ffffffff81d041b0 T vce_v1_0_enable_mgcg +ffffffff81d04460 T vce_v1_0_load_fw +ffffffff81d04620 T vce_v1_0_bo_size +ffffffff81d04690 T vce_v1_0_resume +ffffffff81d05000 T vce_v1_0_start +ffffffff81d057c0 T vce_v1_0_init +ffffffff81d06000 T vce_v2_0_enable_mgcg +ffffffff81d06070 t vce_v2_0_set_dyn_cg +ffffffff81d06260 T vce_v2_0_bo_size +ffffffff81d062d0 T vce_v2_0_resume +ffffffff81d07000 T aldebaran_reset_init +ffffffff81d070c0 t aldebaran_async_reset +ffffffff81d07120 t aldebaran_get_reset_handler +ffffffff81d071d0 T aldebaran_reset_fini +ffffffff81d07220 t aldebaran_mode2_prepare_hwcontext +ffffffff81d07340 t aldebaran_mode2_perform_reset +ffffffff81d07510 t aldebaran_mode2_restore_hwcontext +ffffffff81d079f0 t aldebaran_mode2_reset +ffffffff81d08000 T aldebaran_reg_base_init +ffffffff81d09000 T amdgpu_acpi_is_pcie_performance_request_supported +ffffffff81d09040 T amdgpu_acpi_is_power_shift_control_supported +ffffffff81d09070 T amdgpu_acpi_pcie_notify_device_ready +ffffffff81d09180 t amdgpu_atcs_call +ffffffff81d09270 T amdgpu_acpi_pcie_performance_request +ffffffff81d094c0 T amdgpu_acpi_power_shift_control +ffffffff81d09560 T amdgpu_acpi_smart_shift_update +ffffffff81d096b0 T amdgpu_acpi_init +ffffffff81d09770 t amdgpu_acpi_event +ffffffff81d09ab0 T amdgpu_acpi_get_backlight_caps +ffffffff81d09af0 T amdgpu_acpi_fini +ffffffff81d09b10 T amdgpu_acpi_should_gpu_reset +ffffffff81d09b50 T amdgpu_acpi_detect +ffffffff81d0b000 T amdgpu_afmt_acr +ffffffff81d0c000 T amdgpu_amdkfd_init +ffffffff81d0c040 T amdgpu_amdkfd_fini +ffffffff81d0c060 T amdgpu_amdkfd_device_probe +ffffffff81d0c090 T amdgpu_amdkfd_device_init +ffffffff81d0c260 t amdgpu_amdkfd_reset_work +ffffffff81d0c2e0 T amdgpu_amdkfd_device_fini_sw +ffffffff81d0c330 T amdgpu_amdkfd_interrupt +ffffffff81d0c360 T amdgpu_amdkfd_suspend +ffffffff81d0c390 T amdgpu_amdkfd_resume_iommu +ffffffff81d0c3c0 T amdgpu_amdkfd_resume +ffffffff81d0c3f0 T amdgpu_amdkfd_pre_reset +ffffffff81d0c420 T amdgpu_amdkfd_post_reset +ffffffff81d0c450 T amdgpu_amdkfd_gpu_reset +ffffffff81d0c4b0 T amdgpu_amdkfd_alloc_gtt_mem +ffffffff81d0c760 t amdgpu_bo_reserve +ffffffff81d0c8c0 t amdgpu_bo_unreserve +ffffffff81d0c9a0 T amdgpu_amdkfd_free_gtt_mem +ffffffff81d0ca10 T amdgpu_amdkfd_alloc_gws +ffffffff81d0caf0 T amdgpu_amdkfd_free_gws +ffffffff81d0cb30 T amdgpu_amdkfd_get_fw_version +ffffffff81d0cbe0 T amdgpu_amdkfd_get_local_mem_info +ffffffff81d0ccb0 T amdgpu_amdkfd_get_gpu_clock_counter +ffffffff81d0ccf0 T amdgpu_amdkfd_get_max_engine_clock_in_mhz +ffffffff81d0cd70 T amdgpu_amdkfd_get_cu_info +ffffffff81d0ceb0 T amdgpu_amdkfd_get_dmabuf_info +ffffffff81d0cff0 T amdgpu_amdkfd_get_xgmi_hops_count +ffffffff81d0d060 T amdgpu_amdkfd_get_xgmi_bandwidth_mbytes +ffffffff81d0d0f0 T amdgpu_amdkfd_get_pcie_bandwidth_mbytes +ffffffff81d0d250 T amdgpu_amdkfd_submit_ib +ffffffff81d0d3b0 T amdgpu_amdkfd_set_compute_idle +ffffffff81d0d400 T amdgpu_amdkfd_is_kfd_vmid +ffffffff81d0d440 T amdgpu_amdkfd_flush_gpu_tlb_vmid +ffffffff81d0d4e0 T amdgpu_amdkfd_flush_gpu_tlb_pasid +ffffffff81d0d510 T amdgpu_amdkfd_have_atomics_support +ffffffff81d0d540 T amdgpu_amdkfd_ras_poison_consumption_handler +ffffffff81d0d5a0 T amdgpu_amdkfd_ras_query_utcl2_poison_status +ffffffff81d0e000 T amdgpu_atom_execute_table +ffffffff81d0e0a0 t amdgpu_atom_execute_table_locked +ffffffff81d0e3f0 T amdgpu_atom_parse +ffffffff81d0e940 T amdgpu_atom_destroy +ffffffff81d0e980 T amdgpu_atom_asic_init +ffffffff81d0ea90 T amdgpu_atom_parse_data_header +ffffffff81d0eb20 T amdgpu_atom_parse_cmd_header +ffffffff81d0eb90 t atom_op_move +ffffffff81d0ed70 t atom_op_and +ffffffff81d0ef50 t atom_op_or +ffffffff81d0f130 t atom_op_shift_left +ffffffff81d0f320 t atom_op_shift_right +ffffffff81d0f510 t atom_op_mul +ffffffff81d0f660 t atom_op_div +ffffffff81d0f7d0 t atom_op_add +ffffffff81d0f9b0 t atom_op_sub +ffffffff81d0fb90 t atom_op_setport +ffffffff81d0fd10 t atom_op_setregblock +ffffffff81d0fdd0 t atom_op_setfbbase +ffffffff81d0fea0 t atom_op_compare +ffffffff81d10090 t atom_op_switch +ffffffff81d102e0 t atom_op_jump +ffffffff81d10560 t atom_op_test +ffffffff81d10720 t atom_op_delay +ffffffff81d10800 t atom_op_calltable +ffffffff81d10940 t atom_op_repeat +ffffffff81d10970 t atom_op_clear +ffffffff81d10a70 t atom_op_nop +ffffffff81d10aa0 t atom_op_eot +ffffffff81d10ad0 t atom_op_mask +ffffffff81d10da0 t atom_op_postcard +ffffffff81d10e50 t atom_op_beep +ffffffff81d10e70 t atom_op_savereg +ffffffff81d10ea0 t atom_op_restorereg +ffffffff81d10ed0 t atom_op_setdatablock +ffffffff81d11010 t atom_op_xor +ffffffff81d111f0 t atom_op_shl +ffffffff81d11400 t atom_op_shr +ffffffff81d11610 t atom_op_debug +ffffffff81d116c0 t atom_op_processds +ffffffff81d11780 t atom_op_mul32 +ffffffff81d118e0 t atom_op_div32 +ffffffff81d11a70 t atom_put_dst +ffffffff81d11f40 t atom_get_src_int +ffffffff81d125f0 t atom_iio_execute +ffffffff81d13000 T amdgpu_atombios_lookup_i2c_gpio +ffffffff81d13260 T amdgpu_atombios_i2c_init +ffffffff81d13530 T amdgpu_atombios_lookup_gpio +ffffffff81d13630 T amdgpu_atombios_has_dce_engine_info +ffffffff81d136b0 T amdgpu_atombios_get_connector_info_from_object_table +ffffffff81d13f00 T amdgpu_atombios_get_clock_info +ffffffff81d14240 T amdgpu_atombios_get_gfx_info +ffffffff81d14300 T amdgpu_atombios_get_vram_width +ffffffff81d14380 T amdgpu_atombios_get_asic_ss_info +ffffffff81d146f0 T amdgpu_atombios_get_clock_dividers +ffffffff81d14910 T amdgpu_atombios_has_gpu_virtualization_table +ffffffff81d14960 T amdgpu_atombios_scratch_regs_lock +ffffffff81d149c0 T amdgpu_atombios_scratch_regs_engine_hung +ffffffff81d14a10 T amdgpu_atombios_scratch_regs_set_backlight_level +ffffffff81d14a60 T amdgpu_atombios_scratch_need_asic_init +ffffffff81d14ab0 T amdgpu_atombios_copy_swap +ffffffff81d14ac0 T amdgpu_atombios_fini +ffffffff81d14b60 T amdgpu_atombios_init +ffffffff81d14e00 t cail_reg_read +ffffffff81d14e20 t cail_reg_write +ffffffff81d14e40 t cail_mc_read +ffffffff81d14e70 t cail_mc_write +ffffffff81d14ea0 t cail_pll_read +ffffffff81d14ed0 t cail_pll_write +ffffffff81d14f00 T amdgpu_atombios_get_data_table +ffffffff81d15000 T amdgpu_atombios_crtc_overscan_setup +ffffffff81d15150 T amdgpu_atombios_crtc_scaler_setup +ffffffff81d151d0 T amdgpu_atombios_crtc_lock +ffffffff81d15230 T amdgpu_atombios_crtc_enable +ffffffff81d15290 T amdgpu_atombios_crtc_blank +ffffffff81d152f0 T amdgpu_atombios_crtc_powergate +ffffffff81d15360 T amdgpu_atombios_crtc_powergate_init +ffffffff81d153c0 T amdgpu_atombios_crtc_set_dtd_timing +ffffffff81d154d0 T amdgpu_atombios_crtc_set_disp_eng_pll +ffffffff81d155c0 T amdgpu_atombios_crtc_set_dce_clock +ffffffff81d156a0 T amdgpu_atombios_crtc_program_pll +ffffffff81d159b0 T amdgpu_atombios_crtc_prepare_pll +ffffffff81d15eb0 T amdgpu_atombios_crtc_set_pll +ffffffff81d17000 T amdgpu_atombios_dp_aux_init +ffffffff81d17090 t amdgpu_atombios_dp_aux_transfer +ffffffff81d17200 T amdgpu_atombios_dp_get_sinktype +ffffffff81d17260 T amdgpu_atombios_dp_get_dpcd +ffffffff81d17410 T amdgpu_atombios_dp_get_panel_mode +ffffffff81d17500 T amdgpu_atombios_dp_set_link_config +ffffffff81d17580 t amdgpu_atombios_dp_get_dp_link_config +ffffffff81d17700 T amdgpu_atombios_dp_mode_valid_helper +ffffffff81d17780 T amdgpu_atombios_dp_needs_link_train +ffffffff81d177f0 T amdgpu_atombios_dp_set_rx_power_state +ffffffff81d17870 T amdgpu_atombios_dp_link_train +ffffffff81d17dc0 t amdgpu_atombios_dp_process_aux_ch +ffffffff81d17f30 t amdgpu_atombios_dp_get_adjust_train +ffffffff81d19000 T amdgpu_atombios_encoder_get_backlight_level_from_reg +ffffffff81d19040 T amdgpu_atombios_encoder_set_backlight_level_to_reg +ffffffff81d19090 T amdgpu_atombios_encoder_get_backlight_level +ffffffff81d190f0 T amdgpu_atombios_encoder_set_backlight_level +ffffffff81d19200 T amdgpu_atombios_encoder_setup_dig_transmitter +ffffffff81d19bd0 T amdgpu_atombios_encoder_init_backlight +ffffffff81d19d60 t amdgpu_atombios_encoder_get_backlight_brightness +ffffffff81d19db0 T amdgpu_atombios_encoder_fini_backlight +ffffffff81d19e40 T amdgpu_atombios_encoder_is_digital +ffffffff81d19e90 T amdgpu_atombios_encoder_mode_fixup +ffffffff81d19f70 T amdgpu_atombios_encoder_get_encoder_mode +ffffffff81d1a110 T amdgpu_atombios_encoder_setup_dig_encoder +ffffffff81d1a5d0 T amdgpu_atombios_encoder_set_edp_panel_power +ffffffff81d1a6d0 T amdgpu_atombios_encoder_dpms +ffffffff81d1a840 t amdgpu_atombios_encoder_setup_dig +ffffffff81d1abb0 t amdgpu_atombios_encoder_setup_dvo +ffffffff81d1ad50 T amdgpu_atombios_encoder_set_crtc_source +ffffffff81d1b130 T amdgpu_atombios_encoder_init_dig +ffffffff81d1b1f0 t amdgpu_atombios_encoder_setup_external_encoder +ffffffff81d1b450 T amdgpu_atombios_encoder_dac_detect +ffffffff81d1b630 T amdgpu_atombios_encoder_dig_detect +ffffffff81d1b730 T amdgpu_atombios_encoder_setup_ext_encoder_ddc +ffffffff81d1b780 T amdgpu_atombios_encoder_set_bios_scratch_regs +ffffffff81d1bd20 T amdgpu_atombios_encoder_get_lcd_info +ffffffff81d1c080 T amdgpu_atombios_encoder_get_dig_info +ffffffff81d1c0f0 t amdgpu_atombios_encoder_update_backlight_status +ffffffff81d1d000 T amdgpu_atombios_i2c_xfer +ffffffff81d1d3a0 T amdgpu_atombios_i2c_func +ffffffff81d1d3d0 T amdgpu_atombios_i2c_channel_trans +ffffffff81d1e000 T amdgpu_atomfirmware_query_firmware_capability +ffffffff81d1e090 T amdgpu_atomfirmware_gpu_virtualization_supported +ffffffff81d1e0c0 T amdgpu_atomfirmware_scratch_regs_init +ffffffff81d1e130 T amdgpu_atomfirmware_allocate_fb_scratch +ffffffff81d1e260 T amdgpu_atomfirmware_get_vram_info +ffffffff81d1e9c0 T amdgpu_atomfirmware_mem_ecc_supported +ffffffff81d1ea70 T amdgpu_atomfirmware_sram_ecc_supported +ffffffff81d1eaa0 T amdgpu_atomfirmware_dynamic_boot_config_supported +ffffffff81d1ead0 T amdgpu_atomfirmware_ras_rom_addr +ffffffff81d1eb70 T amdgpu_atomfirmware_get_clock_info +ffffffff81d1ed90 T amdgpu_atomfirmware_get_gfx_info +ffffffff81d1ef20 T amdgpu_atomfirmware_mem_training_supported +ffffffff81d1ef50 T amdgpu_atomfirmware_get_fw_reserved_fb_size +ffffffff81d1efe0 T amdgpu_atomfirmware_asic_init +ffffffff81d20000 T amdgpu_benchmark +ffffffff81d207a0 t amdgpu_benchmark_move +ffffffff81d21000 T amdgpu_read_bios +ffffffff81d21190 t check_atom_bios +ffffffff81d212a0 T amdgpu_get_bios +ffffffff81d21850 t igp_read_bios_from_vram +ffffffff81d21990 T amdgpu_soc15_read_bios_from_rom +ffffffff81d22000 T amdgpu_bo_list_create +ffffffff81d22280 T amdgpu_bo_list_get +ffffffff81d222e0 T amdgpu_bo_list_get_list +ffffffff81d22440 T amdgpu_bo_list_put +ffffffff81d224f0 T amdgpu_bo_create_list_entry_array +ffffffff81d22630 T amdgpu_bo_list_ioctl +ffffffff81d23000 T amdgpu_cgs_create_device +ffffffff81d23080 T amdgpu_cgs_destroy_device +ffffffff81d230a0 t amdgpu_cgs_read_register +ffffffff81d230c0 t amdgpu_cgs_write_register +ffffffff81d230e0 t amdgpu_cgs_read_ind_register +ffffffff81d231c0 t amdgpu_cgs_write_ind_register +ffffffff81d23260 t amdgpu_cgs_get_firmware_info +ffffffff81d24000 T amdgpu_connector_hotplug +ffffffff81d240f0 T amdgpu_connector_get_monitor_bpc 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amdgpu_device_mm_access +ffffffff81d2f320 T amdgpu_device_wreg +ffffffff81d2f420 T amdgpu_device_rreg +ffffffff81d2f500 T amdgpu_device_aper_access +ffffffff81d2f630 T amdgpu_device_flush_hdp +ffffffff81d2f6c0 T amdgpu_device_invalidate_hdp +ffffffff81d2f730 T amdgpu_device_vram_access +ffffffff81d2f7b0 T amdgpu_device_skip_hw_access +ffffffff81d2f7e0 T amdgpu_mm_rreg8 +ffffffff81d2f850 T amdgpu_mm_wreg8 +ffffffff81d2f8c0 T amdgpu_mm_wreg_mmio_rlc +ffffffff81d2f9a0 T amdgpu_mm_rdoorbell +ffffffff81d2fa10 T amdgpu_mm_wdoorbell +ffffffff81d2fa70 T amdgpu_mm_rdoorbell64 +ffffffff81d2fae0 T amdgpu_mm_wdoorbell64 +ffffffff81d2fb40 T amdgpu_device_indirect_rreg +ffffffff81d2fbc0 T amdgpu_device_indirect_rreg64 +ffffffff81d2fc70 T amdgpu_device_indirect_wreg +ffffffff81d2fce0 T amdgpu_device_indirect_wreg64 +ffffffff81d2fd70 T amdgpu_device_program_register_sequence +ffffffff81d2ffb0 T amdgpu_device_pci_config_reset +ffffffff81d2ffe0 T amdgpu_device_pci_reset +ffffffff81d30030 T amdgpu_device_wb_get +ffffffff81d300d0 T amdgpu_device_wb_free +ffffffff81d30110 T amdgpu_device_resize_fb_bar +ffffffff81d30140 T amdgpu_device_need_post +ffffffff81d30270 T amdgpu_device_should_use_aspm +ffffffff81d302c0 T amdgpu_device_aspm_support_quirk +ffffffff81d30310 T amdgpu_device_ip_set_clockgating_state +ffffffff81d30400 T amdgpu_device_ip_set_powergating_state +ffffffff81d304f0 T amdgpu_device_ip_get_clockgating_state +ffffffff81d30590 T amdgpu_device_ip_wait_for_idle +ffffffff81d30610 T amdgpu_device_ip_is_idle +ffffffff81d30680 T amdgpu_device_ip_get_ip_block +ffffffff81d306e0 T amdgpu_device_ip_block_version_cmp +ffffffff81d30760 T amdgpu_device_ip_block_add +ffffffff81d30810 T amdgpu_device_set_cg_state +ffffffff81d30930 T amdgpu_device_set_pg_state +ffffffff81d30a50 T amdgpu_device_ip_suspend +ffffffff81d30ae0 t amdgpu_device_ip_suspend_phase1 +ffffffff81d30d90 t amdgpu_device_ip_suspend_phase2 +ffffffff81d30f00 T amdgpu_device_asic_has_dc_support +ffffffff81d30f60 T amdgpu_device_has_dc_support +ffffffff81d30ff0 T amdgpu_device_init +ffffffff81d33110 t amdgpu_invalid_rreg +ffffffff81d33140 t amdgpu_invalid_wreg +ffffffff81d33170 t amdgpu_invalid_rreg64 +ffffffff81d331a0 t amdgpu_invalid_wreg64 +ffffffff81d331d0 t amdgpu_block_invalid_rreg +ffffffff81d33210 t amdgpu_block_invalid_wreg +ffffffff81d33250 t amdgpu_device_delayed_init_work_handler +ffffffff81d332b0 t amdgpu_device_delay_enable_gfx_off +ffffffff81d33380 t amdgpu_device_xgmi_reset_func +ffffffff81d33680 t amdgpu_device_ip_late_init +ffffffff81d33ab0 T amdgpu_device_cache_pci_state +ffffffff81d33ae0 T amdgpu_device_fini_hw +ffffffff81d33fd0 t amdgpu_device_unmap_mmio +ffffffff81d340d0 T amdgpu_device_fini_sw +ffffffff81d344b0 T amdgpu_device_suspend +ffffffff81d34650 T amdgpu_device_resume +ffffffff81d34970 T amdgpu_device_has_job_running +ffffffff81d34a40 T amdgpu_device_should_recover_gpu +ffffffff81d34b70 T amdgpu_device_mode1_reset +ffffffff81d34c70 T amdgpu_device_load_pci_state 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amdgpu_display_crtc_scaling_mode_fixup +ffffffff81d3d4e0 T amdgpu_display_get_crtc_scanoutpos +ffffffff81d3d700 T amdgpu_display_crtc_idx_to_irq_type +ffffffff81d3d740 T amdgpu_crtc_get_scanout_position +ffffffff81d3d7a0 T amdgpu_display_suspend_helper +ffffffff81d3d930 T amdgpu_display_resume_helper +ffffffff81d3da90 t __delayed_work_tick +ffffffff81d3dab0 t amdgpu_display_flip_callback +ffffffff81d3daf0 t amdgpu_display_verify_plane +ffffffff81d3e000 T amdgpu_gem_prime_export +ffffffff81d3e080 T amdgpu_gem_prime_import +ffffffff81d3e350 T amdgpu_dmabuf_is_xgmi_accessible +ffffffff81d3f000 t amdgpu_drv_delayed_reset_work_handler +ffffffff81d3f350 t __delayed_work_tick +ffffffff81d3f370 T amdgpu_file_to_fpriv +ffffffff81d3f3c0 T amdgpu_probe +ffffffff81d3f500 T amdgpu_attach +ffffffff81d3fc10 T amdgpu_detach +ffffffff81d3fcb0 T amdgpu_activate +ffffffff81d3fd60 T amdgpu_attachhook +ffffffff81d40210 T amdgpu_forcedetach +ffffffff81d402c0 T amdgpu_wsioctl +ffffffff81d403d0 T amdgpu_wsmmap +ffffffff81d40400 T amdgpu_alloc_screen +ffffffff81d40420 T amdgpu_free_screen +ffffffff81d40430 T amdgpu_show_screen +ffffffff81d40500 T amdgpu_burner +ffffffff81d40580 T amdgpu_enter_ddb +ffffffff81d405e0 T amdgpu_doswitch +ffffffff81d40650 T amdgpu_init_backlight +ffffffff81d40750 T amdgpu_burner_cb +ffffffff81d41000 T amdgpu_eeprom_read +ffffffff81d41020 t amdgpu_eeprom_xfer +ffffffff81d41190 T amdgpu_eeprom_write +ffffffff81d411b0 t __amdgpu_eeprom_xfer +ffffffff81d42000 T amdgpu_link_encoder_connector +ffffffff81d420e0 T amdgpu_encoder_set_active_device +ffffffff81d421a0 T amdgpu_get_connector_for_encoder +ffffffff81d42220 T amdgpu_get_connector_for_encoder_init +ffffffff81d422a0 T amdgpu_get_external_encoder +ffffffff81d42320 T amdgpu_encoder_get_dp_bridge_encoder_id +ffffffff81d423b0 T amdgpu_panel_mode_fixup +ffffffff81d42530 T amdgpu_dig_monitor_is_duallink +ffffffff81d43000 T amdgpu_show_fdinfo +ffffffff81d44000 T amdgpu_fence_slab_init +ffffffff81d44060 T amdgpu_fence_slab_fini +ffffffff81d44080 T amdgpu_fence_emit +ffffffff81d44240 T amdgpu_fence_emit_polling +ffffffff81d44330 T amdgpu_fence_wait_polling +ffffffff81d443c0 T amdgpu_fence_process +ffffffff81d444f0 T amdgpu_fence_wait_empty +ffffffff81d44570 T amdgpu_fence_count_emitted +ffffffff81d445a0 T amdgpu_fence_driver_start_ring +ffffffff81d44670 T amdgpu_fence_driver_init_ring +ffffffff81d44760 t amdgpu_fence_fallback +ffffffff81d447c0 T amdgpu_fence_driver_sw_init +ffffffff81d447f0 T amdgpu_fence_driver_hw_fini +ffffffff81d44910 T amdgpu_fence_driver_force_completion +ffffffff81d44930 T amdgpu_fence_driver_isr_toggle +ffffffff81d44950 T amdgpu_fence_driver_sw_fini +ffffffff81d44a30 T amdgpu_fence_driver_hw_init +ffffffff81d44ab0 T amdgpu_fence_driver_clear_job_fences +ffffffff81d44b30 T amdgpu_debugfs_fence_init +ffffffff81d44b60 t amdgpu_fence_get_driver_name +ffffffff81d44b90 t amdgpu_fence_get_timeline_name +ffffffff81d44be0 t amdgpu_fence_enable_signaling +ffffffff81d44c80 t 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amdgpu_gmc_set_vm_fault_masks +ffffffff81d4df70 T amdgpu_gmc_get_vbios_allocations +ffffffff81d4e0d0 T amdgpu_gmc_init_pdb0 +ffffffff81d4e230 T amdgpu_gmc_vram_pa +ffffffff81d4e280 T amdgpu_gmc_vram_mc2pa +ffffffff81d4e2c0 T amdgpu_gmc_vram_cpu_pa +ffffffff81d4e310 T amdgpu_gmc_vram_checking +ffffffff81d4f000 T amdgpu_gtt_mgr_has_gart_addr +ffffffff81d4f030 T amdgpu_gtt_mgr_recover +ffffffff81d4f0b0 T amdgpu_gtt_mgr_init +ffffffff81d4f230 T amdgpu_gtt_mgr_fini +ffffffff81d4f3b0 t amdgpu_gtt_mgr_new +ffffffff81d4f530 t amdgpu_gtt_mgr_del +ffffffff81d4f5a0 t amdgpu_gtt_mgr_intersects +ffffffff81d4f5e0 t amdgpu_gtt_mgr_compatible +ffffffff81d4f620 t amdgpu_gtt_mgr_debug +ffffffff81d50000 T amdgpu_bb_set_bits +ffffffff81d500c0 T amdgpu_bb_set_dir +ffffffff81d500f0 T amdgpu_bb_read_bits +ffffffff81d50180 T amdgpu_acquire_bus +ffffffff81d50350 T amdgpu_release_bus +ffffffff81d50410 T amdgpu_send_start +ffffffff81d50430 T amdgpu_send_stop +ffffffff81d50450 T amdgpu_initiate_xfer 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amdgpu_jpeg_idle_work_handler +ffffffff81d56190 T amdgpu_jpeg_sw_fini +ffffffff81d56220 T amdgpu_jpeg_suspend +ffffffff81d56280 T amdgpu_jpeg_resume +ffffffff81d562b0 T amdgpu_jpeg_ring_begin_use +ffffffff81d56330 T amdgpu_jpeg_ring_end_use +ffffffff81d56390 T amdgpu_jpeg_dec_ring_test_ring +ffffffff81d56550 T amdgpu_jpeg_dec_ring_test_ib +ffffffff81d567b0 T amdgpu_jpeg_process_poison_irq +ffffffff81d56860 t __delayed_work_tick +ffffffff81d57000 T amdgpu_unregister_gpu_instance +ffffffff81d570a0 T amdgpu_register_gpu_instance +ffffffff81d57120 T amdgpu_info_ioctl +ffffffff81d593d0 T amdgpu_driver_lastclose_kms +ffffffff81d593e0 T amdgpu_driver_open_kms +ffffffff81d595f0 T amdgpu_driver_postclose_kms +ffffffff81d59800 t amdgpu_bo_reserve +ffffffff81d59960 t amdgpu_bo_unreserve +ffffffff81d59a40 T amdgpu_driver_release_kms +ffffffff81d59a50 T amdgpu_get_vblank_counter_kms +ffffffff81d59be0 T amdgpu_enable_vblank_kms +ffffffff81d59c20 T amdgpu_disable_vblank_kms +ffffffff81d59c60 T amdgpu_debugfs_firmware_init +ffffffff81d5a000 T amdgpu_lsdma_wait_for +ffffffff81d5a0a0 T amdgpu_lsdma_copy_mem +ffffffff81d5a130 T amdgpu_lsdma_fill_mem +ffffffff81d5b000 T amdgpu_mca_query_correctable_error_count +ffffffff81d5b060 T amdgpu_mca_query_uncorrectable_error_count +ffffffff81d5b0c0 T amdgpu_mca_reset_error_count +ffffffff81d5b0e0 T amdgpu_mca_query_ras_error_count +ffffffff81d5c000 T amdgpu_mes_doorbell_process_slice +ffffffff81d5c030 T amdgpu_mes_alloc_process_doorbells +ffffffff81d5c080 T amdgpu_mes_free_process_doorbells +ffffffff81d5c0c0 T amdgpu_mes_get_doorbell_dw_offset_in_bar +ffffffff81d5c0f0 T amdgpu_mes_init +ffffffff81d5c4b0 T amdgpu_mes_fini +ffffffff81d5c520 T amdgpu_mes_create_process +ffffffff81d5c780 T amdgpu_mes_destroy_process +ffffffff81d5ca50 T amdgpu_mes_add_gang +ffffffff81d5cc60 T amdgpu_mes_remove_gang +ffffffff81d5cd70 T amdgpu_mes_suspend +ffffffff81d5ce80 T amdgpu_mes_resume +ffffffff81d5cf90 T amdgpu_mes_add_hw_queue +ffffffff81d5d850 T amdgpu_mes_remove_hw_queue +ffffffff81d5da50 T amdgpu_mes_unmap_legacy_queue +ffffffff81d5daf0 T amdgpu_mes_rreg +ffffffff81d5dba0 T amdgpu_mes_wreg +ffffffff81d5dc40 T amdgpu_mes_reg_write_reg_wait +ffffffff81d5dce0 T amdgpu_mes_reg_wait +ffffffff81d5dd80 T amdgpu_mes_ctx_get_offs +ffffffff81d5df50 T amdgpu_mes_add_ring +ffffffff81d5e310 T amdgpu_mes_remove_ring +ffffffff81d5e370 T amdgpu_mes_get_aggregated_doorbell_index +ffffffff81d5e3a0 T amdgpu_mes_ctx_alloc_meta_data +ffffffff81d5e420 T amdgpu_mes_ctx_free_meta_data +ffffffff81d5e460 T amdgpu_mes_ctx_map_meta_data +ffffffff81d5e660 T amdgpu_mes_ctx_unmap_meta_data +ffffffff81d5e870 T amdgpu_mes_self_test +ffffffff81d5f000 T amdgpu_nbio_ras_late_init +ffffffff81d60000 T amdgpu_bo_is_amdgpu_bo +ffffffff81d60060 t amdgpu_bo_destroy +ffffffff81d600e0 t amdgpu_bo_user_destroy +ffffffff81d60180 t amdgpu_bo_vm_destroy +ffffffff81d60270 T amdgpu_bo_placement_from_domain +ffffffff81d60440 T amdgpu_bo_create_reserved +ffffffff81d60810 T amdgpu_bo_unref +ffffffff81d60860 T amdgpu_bo_create +ffffffff81d60d10 t amdgpu_bo_reserve +ffffffff81d60f20 T amdgpu_bo_pin +ffffffff81d60f40 T amdgpu_bo_gpu_offset +ffffffff81d61110 T amdgpu_bo_kmap +ffffffff81d611c0 T amdgpu_bo_unpin +ffffffff81d61260 t amdgpu_bo_unreserve +ffffffff81d61340 T amdgpu_bo_create_kernel +ffffffff81d613a0 T amdgpu_bo_create_kernel_at +ffffffff81d615c0 T amdgpu_bo_kunmap +ffffffff81d61600 T amdgpu_bo_free_kernel +ffffffff81d61730 T amdgpu_bo_support_uswc +ffffffff81d61760 T amdgpu_bo_create_user +ffffffff81d617c0 T amdgpu_bo_create_vm +ffffffff81d61860 T amdgpu_bo_add_to_shadow_list +ffffffff81d618e0 T amdgpu_bo_restore_shadow +ffffffff81d61970 T amdgpu_bo_kptr +ffffffff81d619a0 T amdgpu_bo_ref +ffffffff81d619e0 T amdgpu_bo_pin_restricted +ffffffff81d61d70 T amdgpu_bo_get_preferred_domain +ffffffff81d61dd0 T amdgpu_bo_init +ffffffff81d61ea0 T amdgpu_bo_fini +ffffffff81d61f20 T amdgpu_bo_set_tiling_flags +ffffffff81d61fb0 T amdgpu_bo_get_tiling_flags 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psp_rlc_autoload_start +ffffffff81d66fb0 T psp_update_vcn_sram +ffffffff81d67030 T psp_ring_cmd_submit +ffffffff81d671c0 T psp_init_asd_microcode +ffffffff81d67390 T psp_init_toc_microcode +ffffffff81d67560 T psp_init_sos_microcode +ffffffff81d67c40 T psp_init_ta_microcode +ffffffff81d68040 T psp_init_cap_microcode +ffffffff81d68260 T is_psp_fw_valid +ffffffff81d68290 T amdgpu_psp_sysfs_init +ffffffff81d68300 t psp_early_init +ffffffff81d68500 t psp_sw_init +ffffffff81d68970 t psp_sw_fini +ffffffff81d68b90 t psp_hw_init +ffffffff81d691e0 t psp_hw_fini +ffffffff81d69720 t psp_suspend +ffffffff81d69c00 t psp_resume +ffffffff81d6a120 t psp_set_clockgating_state +ffffffff81d6a150 t psp_set_powergating_state +ffffffff81d6a180 T amdgpu_psp_sysfs_fini +ffffffff81d6a1b0 t psp_get_runtime_db_entry +ffffffff81d6a3a0 t psp_hw_start +ffffffff81d6a8a0 t psp_load_non_psp_fw +ffffffff81d6abc0 t psp_ras_initialize +ffffffff81d6af90 t psp_rap_initialize +ffffffff81d6b190 t psp_load_smu_fw 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amdgpu_ras_need_emergency_restart +ffffffff81d71a60 t __delayed_work_tick +ffffffff81d72000 T amdgpu_ras_eeprom_reset_table +ffffffff81d720c0 t __write_table_header +ffffffff81d721a0 T amdgpu_ras_debugfs_set_ret_size +ffffffff81d721d0 T amdgpu_ras_eeprom_check_err_threshold +ffffffff81d722b0 T amdgpu_ras_eeprom_append +ffffffff81d72830 T amdgpu_ras_eeprom_read +ffffffff81d72a80 t __amdgpu_ras_eeprom_read +ffffffff81d72b80 T amdgpu_ras_eeprom_max_record_count +ffffffff81d72bb0 T amdgpu_ras_eeprom_init +ffffffff81d73030 t __verify_ras_table_checksum +ffffffff81d73190 t __amdgpu_ras_eeprom_write +ffffffff81d74000 T amdgpu_reset_add_handler +ffffffff81d74050 T amdgpu_reset_init +ffffffff81d740a0 T amdgpu_reset_fini +ffffffff81d740f0 T amdgpu_reset_prepare_hwcontext +ffffffff81d74170 T amdgpu_reset_perform_reset +ffffffff81d74230 T amdgpu_reset_destroy_reset_domain +ffffffff81d74260 T amdgpu_reset_create_reset_domain +ffffffff81d74360 T amdgpu_device_lock_reset_domain +ffffffff81d74380 T amdgpu_device_unlock_reset_domain +ffffffff81d75000 T amdgpu_ring_alloc +ffffffff81d750d0 T amdgpu_ring_insert_nop +ffffffff81d75180 T amdgpu_ring_generic_pad_ib +ffffffff81d751e0 T amdgpu_ring_commit +ffffffff81d75270 T amdgpu_ring_undo +ffffffff81d752c0 T amdgpu_ring_init +ffffffff81d759b0 T amdgpu_ring_fini +ffffffff81d75ab0 T amdgpu_ring_emit_reg_write_reg_wait_helper +ffffffff81d75b10 T amdgpu_ring_soft_recovery +ffffffff81d75c60 T amdgpu_debugfs_ring_init +ffffffff81d75c90 T amdgpu_ring_test_helper +ffffffff81d75d30 T amdgpu_ring_init_mqd +ffffffff81d76000 T amdgpu_gfx_rlc_enter_safe_mode +ffffffff81d76080 T amdgpu_gfx_rlc_exit_safe_mode +ffffffff81d76100 T amdgpu_gfx_rlc_init_sr +ffffffff81d76260 T amdgpu_gfx_rlc_fini +ffffffff81d762d0 t amdgpu_bo_unreserve +ffffffff81d763b0 T amdgpu_gfx_rlc_init_csb +ffffffff81d764e0 T amdgpu_gfx_rlc_init_cpt +ffffffff81d767c0 T amdgpu_gfx_rlc_setup_cp_table +ffffffff81d769d0 T amdgpu_gfx_rlc_init_microcode +ffffffff81d78000 T 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dce_v11_0_disable_dce +ffffffff81daa160 t dce_v11_0_early_init +ffffffff81daa2a0 t dce_v11_0_sw_init +ffffffff81daa720 t dce_v11_0_sw_fini +ffffffff81daa850 t dce_v11_0_hw_init +ffffffff81daac20 t dce_v11_0_hw_fini +ffffffff81daadb0 t dce_v11_0_suspend +ffffffff81daae10 t dce_v11_0_resume +ffffffff81daae80 t dce_v11_0_is_idle +ffffffff81daaeb0 t dce_v11_0_wait_for_idle +ffffffff81daaee0 t dce_v11_0_soft_reset +ffffffff81dab100 t dce_v11_0_set_clockgating_state +ffffffff81dab130 t dce_v11_0_set_powergating_state +ffffffff81dab160 t dce_v11_0_audio_endpt_rreg +ffffffff81dab1f0 t dce_v11_0_audio_endpt_wreg +ffffffff81dab260 t dce_v11_0_bandwidth_update +ffffffff81dabcc0 t dce_v11_0_vblank_get_counter +ffffffff81dabd10 t dce_v11_0_hpd_sense +ffffffff81dabd70 t dce_v11_0_hpd_set_polarity +ffffffff81dabe40 t dce_v11_0_hpd_get_gpio_reg +ffffffff81dabe70 t dce_v11_0_page_flip +ffffffff81dabf60 t dce_v11_0_crtc_get_scanoutpos +ffffffff81dac000 t dce_v11_0_encoder_add +ffffffff81dac230 t dce_v11_0_latency_watermark +ffffffff81dac450 t dce_v11_0_encoder_destroy +ffffffff81dac4a0 t dce_v11_0_encoder_prepare +ffffffff81dac6a0 t dce_v11_0_encoder_commit +ffffffff81dac6d0 t dce_v11_0_encoder_mode_set +ffffffff81dad570 t dce_v11_0_encoder_disable +ffffffff81dad680 t dce_v11_0_ext_dpms +ffffffff81dad6b0 t dce_v11_0_ext_prepare +ffffffff81dad6e0 t dce_v11_0_ext_commit +ffffffff81dad710 t dce_v11_0_ext_mode_set +ffffffff81dad740 t dce_v11_0_ext_disable +ffffffff81dad770 t dce_v11_0_set_crtc_irq_state +ffffffff81dad850 t dce_v11_0_crtc_irq +ffffffff81dada70 t dce_v11_0_set_crtc_vblank_interrupt_state +ffffffff81dadb40 t dce_v11_0_set_crtc_vline_interrupt_state +ffffffff81dadc10 t dce_v11_0_set_pageflip_irq_state +ffffffff81dadcc0 t dce_v11_0_pageflip_irq +ffffffff81dade20 t dce_v11_0_set_hpd_irq_state +ffffffff81dadee0 t dce_v11_0_hpd_irq +ffffffff81dae000 t dce_v11_0_crtc_cursor_set2 +ffffffff81dae370 t dce_v11_0_crtc_cursor_move +ffffffff81dae440 t dce_v11_0_crtc_gamma_set +ffffffff81dae480 t dce_v11_0_crtc_destroy +ffffffff81dae4b0 t amdgpu_bo_reserve +ffffffff81dae6c0 t amdgpu_bo_unreserve +ffffffff81dae7a0 t dce_v11_0_cursor_move_locked +ffffffff81dae8f0 t dce_v11_0_crtc_load_lut +ffffffff81daec60 t dce_v11_0_crtc_dpms +ffffffff81daee30 t dce_v11_0_crtc_prepare +ffffffff81daee70 t dce_v11_0_crtc_commit +ffffffff81daeea0 t dce_v11_0_crtc_mode_fixup +ffffffff81daf110 t dce_v11_0_crtc_mode_set +ffffffff81daf370 t dce_v11_0_crtc_set_base +ffffffff81daf390 t dce_v11_0_crtc_set_base_atomic +ffffffff81daf3b0 t dce_v11_0_crtc_disable +ffffffff81daf550 t dce_v11_0_crtc_do_set_base +ffffffff81db0000 t df_v1_7_sw_init +ffffffff81db0040 t df_v1_7_sw_fini +ffffffff81db0070 t df_v1_7_enable_broadcast_mode +ffffffff81db0190 t df_v1_7_get_fb_channel_number +ffffffff81db0210 t df_v1_7_get_hbm_channel_number +ffffffff81db0260 t df_v1_7_update_medium_grain_clock_gating +ffffffff81db03d0 t df_v1_7_get_clockgating_state +ffffffff81db0460 t df_v1_7_enable_ecc_force_par_wr_rmw +ffffffff81db1000 t df_v3_6_sw_init +ffffffff81db1160 t df_v3_6_sw_fini +ffffffff81db1190 t df_v3_6_enable_broadcast_mode +ffffffff81db12b0 t df_v3_6_get_fb_channel_number +ffffffff81db1380 t df_v3_6_get_hbm_channel_number +ffffffff81db13d0 t df_v3_6_update_medium_grain_clock_gating +ffffffff81db1570 t df_v3_6_get_clockgating_state +ffffffff81db1600 t df_v3_6_pmc_start +ffffffff81db1980 t df_v3_6_pmc_stop +ffffffff81db1c10 t df_v3_6_pmc_get_count +ffffffff81db1d90 t df_v3_6_get_fica +ffffffff81db1e90 t df_v3_6_set_fica +ffffffff81db1f60 t df_v3_6_query_ras_poison_mode +ffffffff81db20d0 t df_v3_6_perfmon_arm_with_status +ffffffff81db3000 T dimgrey_cavefish_reg_base_init +ffffffff81db4000 T emu_soc_asic_init +ffffffff81db5000 t gfx_v10_0_early_init +ffffffff81db5420 t gfx_v10_0_late_init +ffffffff81db5490 t gfx_v10_0_sw_init +ffffffff81db6830 t gfx_v10_0_sw_fini +ffffffff81db6b60 t gfx_v10_0_hw_init +ffffffff81db9710 t gfx_v10_0_hw_fini +ffffffff81db99f0 t gfx_v10_0_suspend +ffffffff81db9a30 t gfx_v10_0_resume +ffffffff81db9a40 t gfx_v10_0_is_idle +ffffffff81db9ac0 t gfx_v10_0_wait_for_idle +ffffffff81db9ba0 t gfx_v10_0_soft_reset +ffffffff81db9ef0 t gfx_v10_0_set_clockgating_state +ffffffff81dba190 t gfx_v10_0_set_powergating_state +ffffffff81dba3b0 t gfx_v10_0_get_clockgating_state +ffffffff81dba4c0 t gfx10_kiq_set_resources +ffffffff81dba7f0 t gfx10_kiq_map_queues +ffffffff81dbab80 t gfx10_kiq_unmap_queues +ffffffff81dbaf80 t gfx10_kiq_query_status +ffffffff81dbb280 t gfx10_kiq_invalidate_tlbs +ffffffff81dbb3a0 t gfx_v10_0_ring_get_rptr_compute +ffffffff81dbb3d0 t gfx_v10_0_ring_get_wptr_compute +ffffffff81dbb430 t gfx_v10_0_ring_set_wptr_compute +ffffffff81dbb570 t gfx_v10_0_ring_emit_ib_compute +ffffffff81dbb8c0 t gfx_v10_0_ring_emit_fence_kiq +ffffffff81dbbcf0 t gfx_v10_0_ring_test_ring +ffffffff81dbbf60 t gfx_v10_0_ring_test_ib +ffffffff81dbc200 t gfx_v10_0_ring_emit_rreg +ffffffff81dbc490 t gfx_v10_0_ring_emit_wreg +ffffffff81dbc6c0 t gfx_v10_0_ring_emit_reg_wait +ffffffff81dbc710 t gfx_v10_0_ring_emit_reg_write_reg_wait +ffffffff81dbc7a0 t gfx_v10_0_wait_reg_mem +ffffffff81dbcad0 t gfx_v10_0_ring_get_rptr_gfx +ffffffff81dbcb00 t gfx_v10_0_ring_get_wptr_gfx +ffffffff81dbcc10 t gfx_v10_0_ring_set_wptr_gfx +ffffffff81dbce20 t gfx_v10_0_ring_emit_ib_gfx +ffffffff81dbd4d0 t gfx_v10_0_ring_emit_fence +ffffffff81dbd8a0 t gfx_v10_0_ring_emit_pipeline_sync +ffffffff81dbd900 t gfx_v10_0_ring_emit_vm_flush +ffffffff81dbdad0 t gfx_v10_0_ring_emit_hdp_flush +ffffffff81dbdba0 t gfx_v10_0_ring_emit_gds_switch +ffffffff81dbdc80 t gfx_v10_0_ring_emit_init_cond_exec +ffffffff81dbdeb0 t gfx_v10_0_ring_emit_patch_cond_exec +ffffffff81dbdf70 t gfx_v10_0_ring_emit_sb +ffffffff81dbe050 t gfx_v10_0_ring_emit_cntxcntl +ffffffff81dbe530 t gfx_v10_0_ring_emit_frame_cntl +ffffffff81dbe640 t gfx_v10_0_ring_soft_recovery +ffffffff81dbe6b0 t gfx_v10_0_ring_preempt_ib +ffffffff81dbe820 t gfx_v10_0_emit_mem_sync +ffffffff81dbeb60 t gfx_v10_0_write_data_to_reg +ffffffff81dbed70 t gfx_v10_0_set_eop_interrupt_state +ffffffff81dbee50 t gfx_v10_0_eop_irq +ffffffff81dbf020 t gfx_v10_0_set_gfx_eop_interrupt_state +ffffffff81dbf1b0 t gfx_v10_0_set_compute_eop_interrupt_state +ffffffff81dbf360 t gfx_v10_0_kiq_set_interrupt_state +ffffffff81dbf630 t gfx_v10_0_kiq_irq +ffffffff81dbf6b0 t gfx_v10_0_set_priv_reg_fault_state +ffffffff81dbf7d0 t gfx_v10_0_priv_reg_irq +ffffffff81dbf830 t gfx_v10_0_handle_priv_fault +ffffffff81dbf9c0 t gfx_v10_0_set_priv_inst_fault_state +ffffffff81dbfae0 t gfx_v10_0_priv_inst_irq +ffffffff81dbfb40 t gfx_v10_0_is_rlc_enabled +ffffffff81dbfbc0 t gfx_v10_0_set_safe_mode +ffffffff81dbfe50 t gfx_v10_0_unset_safe_mode +ffffffff81dbff00 t gfx_v10_0_rlc_init +ffffffff81dbff70 t gfx_v10_0_get_csb_size +ffffffff81dbffc0 t gfx_v10_0_get_csb_buffer +ffffffff81dc0140 t gfx_v10_0_rlc_resume +ffffffff81dc0c40 t gfx_v10_0_rlc_stop +ffffffff81dc0d10 t gfx_v10_0_rlc_reset +ffffffff81dc0ea0 t gfx_v10_0_rlc_start +ffffffff81dc1040 t gfx_v10_0_update_spm_vmid +ffffffff81dc1170 t gfx_v10_0_wait_for_rlc_autoload_complete +ffffffff81dc1d00 t gfx_v10_0_init_csb +ffffffff81dc1fd0 t gfx_v10_0_is_rlcg_access_range +ffffffff81dc2000 t gfx_v10_0_gfx_mqd_init +ffffffff81dc23e0 t gfx_v10_0_compute_mqd_init +ffffffff81dc2880 t amdgpu_bo_unreserve +ffffffff81dc2960 t gfx_v10_0_get_gpu_clock_counter +ffffffff81dc2e50 t gfx_v10_0_select_se_sh +ffffffff81dc2ee0 t gfx_v10_0_read_wave_data +ffffffff81dc3140 t gfx_v10_0_read_wave_vgprs +ffffffff81dc3170 t gfx_v10_0_read_wave_sgprs +ffffffff81dc31f0 t gfx_v10_0_select_me_pipe_q +ffffffff81dc3210 t gfx_v10_0_init_spm_golden_registers +ffffffff81dc3280 t gfx_v10_0_update_perfmon_mgcg +ffffffff81dc33a0 t wave_read_ind +ffffffff81dc3480 t wave_read_regs +ffffffff81dc35e0 t gfx_v10_0_cp_resume +ffffffff81dc6220 t gfx_v10_3_get_disabled_sa +ffffffff81dc6330 t gfx_v10_0_get_rb_active_bitmap +ffffffff81dc6450 t gfx_v10_0_get_wgp_active_bitmap_per_sh +ffffffff81dc6560 t gfx_v10_0_enable_gui_idle_interrupt +ffffffff81dc6670 t gfx_v10_0_cp_gfx_enable +ffffffff81dc68b0 t gfx_v10_0_cp_compute_enable +ffffffff81dc6a40 t amdgpu_bo_reserve +ffffffff81dc6bc0 t gfx_v10_0_kiq_init_register +ffffffff81dc7a30 t gfx_v10_0_cp_gfx_switch_pipe +ffffffff81dc7b30 t gfx_v10_0_cp_gfx_set_doorbell +ffffffff81dc7e00 t gfx_v10_0_cp_gfx_start +ffffffff81dc87e0 t gfx_v10_0_update_fine_grain_clock_gating +ffffffff81dc8b00 t gfx_v10_0_update_medium_grain_clock_gating +ffffffff81dc9220 t gfx_v10_0_update_3d_clock_gating +ffffffff81dc95e0 t gfx_v10_0_update_coarse_grain_clock_gating +ffffffff81dca000 t gfx_v11_0_early_init +ffffffff81dca390 t gfx_v11_0_late_init +ffffffff81dca400 t gfx_v11_0_sw_init +ffffffff81dcb300 t gfx_v11_0_sw_fini +ffffffff81dcb5d0 t gfx_v11_0_hw_init +ffffffff81dcfa40 t gfx_v11_0_hw_fini +ffffffff81dcfcb0 t gfx_v11_0_suspend +ffffffff81dcfcf0 t gfx_v11_0_resume +ffffffff81dcfd00 t gfx_v11_0_is_idle +ffffffff81dcfd80 t gfx_v11_0_wait_for_idle +ffffffff81dcfe60 t gfx_v11_0_check_soft_reset +ffffffff81dcff90 t gfx_v11_0_soft_reset +ffffffff81dd0c70 t gfx_v11_0_set_clockgating_state +ffffffff81dd1850 t gfx_v11_0_set_powergating_state +ffffffff81dd1a40 t gfx_v11_0_get_clockgating_state +ffffffff81dd1c10 t gfx11_kiq_set_resources +ffffffff81dd1f40 t gfx11_kiq_map_queues +ffffffff81dd22d0 t gfx11_kiq_unmap_queues +ffffffff81dd26d0 t gfx11_kiq_query_status +ffffffff81dd29d0 t gfx11_kiq_invalidate_tlbs +ffffffff81dd2af0 t gfx_v11_0_ring_get_rptr_compute +ffffffff81dd2b20 t gfx_v11_0_ring_get_wptr_compute +ffffffff81dd2b80 t gfx_v11_0_ring_set_wptr_compute +ffffffff81dd2cc0 t gfx_v11_0_ring_emit_ib_compute +ffffffff81dd3010 t gfx_v11_0_ring_emit_fence_kiq +ffffffff81dd3440 t gfx_v11_0_ring_test_ring +ffffffff81dd36d0 t gfx_v11_0_ring_test_ib +ffffffff81dd3990 t gfx_v11_0_ring_emit_rreg +ffffffff81dd3c20 t gfx_v11_0_ring_emit_wreg +ffffffff81dd3e50 t gfx_v11_0_ring_emit_reg_wait +ffffffff81dd3ea0 t gfx_v11_0_ring_emit_reg_write_reg_wait +ffffffff81dd3f00 t gfx_v11_0_wait_reg_mem +ffffffff81dd4230 t gfx_v11_0_ring_get_rptr_gfx +ffffffff81dd4260 t gfx_v11_0_ring_get_wptr_gfx +ffffffff81dd4370 t gfx_v11_0_ring_set_wptr_gfx +ffffffff81dd4580 t gfx_v11_0_ring_emit_ib_gfx +ffffffff81dd4c20 t gfx_v11_0_ring_emit_fence +ffffffff81dd4ff0 t gfx_v11_0_ring_emit_pipeline_sync +ffffffff81dd5050 t gfx_v11_0_ring_emit_vm_flush +ffffffff81dd5220 t gfx_v11_0_ring_emit_hdp_flush +ffffffff81dd52f0 t gfx_v11_0_ring_emit_gds_switch +ffffffff81dd53d0 t gfx_v11_0_ring_emit_init_cond_exec +ffffffff81dd5600 t gfx_v11_0_ring_emit_patch_cond_exec +ffffffff81dd56c0 t gfx_v11_0_ring_emit_cntxcntl +ffffffff81dd5820 t gfx_v11_0_ring_emit_frame_cntl +ffffffff81dd5930 t gfx_v11_0_ring_soft_recovery +ffffffff81dd59a0 t gfx_v11_0_ring_preempt_ib +ffffffff81dd5b10 t gfx_v11_0_emit_mem_sync +ffffffff81dd5e50 t gfx_v11_0_write_data_to_reg +ffffffff81dd6060 t gfx_v11_0_set_eop_interrupt_state +ffffffff81dd60f0 t gfx_v11_0_eop_irq +ffffffff81dd62c0 t gfx_v11_0_set_gfx_eop_interrupt_state +ffffffff81dd6450 t gfx_v11_0_set_compute_eop_interrupt_state +ffffffff81dd65e0 t gfx_v11_0_set_priv_reg_fault_state +ffffffff81dd6700 t gfx_v11_0_priv_reg_irq +ffffffff81dd6760 t gfx_v11_0_handle_priv_fault +ffffffff81dd68f0 t gfx_v11_0_set_priv_inst_fault_state +ffffffff81dd6a10 t gfx_v11_0_priv_inst_irq +ffffffff81dd6a70 t gfx_v11_0_is_rlc_enabled +ffffffff81dd6af0 t gfx_v11_0_set_safe_mode +ffffffff81dd6c40 t gfx_v11_0_unset_safe_mode +ffffffff81dd6ca0 t gfx_v11_0_rlc_init +ffffffff81dd6d10 t gfx_v11_0_get_csb_size +ffffffff81dd6d60 t gfx_v11_0_get_csb_buffer +ffffffff81dd6ee0 t gfx_v11_0_rlc_resume +ffffffff81dd7c00 t gfx_v11_0_rlc_stop +ffffffff81dd7cd0 t gfx_v11_0_rlc_reset +ffffffff81dd7e60 t gfx_v11_0_rlc_start +ffffffff81dd8000 t gfx_v11_0_update_spm_vmid +ffffffff81dd8100 t gfx_v11_0_init_csb +ffffffff81dd8280 t gfx_v11_0_gfx_mqd_init +ffffffff81dd8650 t gfx_v11_0_compute_mqd_init +ffffffff81dd8b70 t amdgpu_bo_unreserve +ffffffff81dd8c50 t gfx_v11_0_get_gpu_clock_counter +ffffffff81dd8d80 t gfx_v11_0_select_se_sh +ffffffff81dd8e10 t gfx_v11_0_read_wave_data +ffffffff81dd9050 t gfx_v11_0_read_wave_vgprs +ffffffff81dd9080 t gfx_v11_0_read_wave_sgprs +ffffffff81dd9100 t gfx_v11_0_select_me_pipe_q +ffffffff81dd9120 t gfx_v11_0_update_perf_clk +ffffffff81dd9250 t wave_read_ind +ffffffff81dd9330 t wave_read_regs +ffffffff81dd9490 t gfx_v11_0_disable_gpa_mode +ffffffff81dd9620 t gfx_v11_0_cp_resume +ffffffff81ddd6c0 t gfx_v11_0_config_me_cache +ffffffff81ddda60 t gfx_v11_0_config_pfp_cache +ffffffff81ddde00 t gfx_v11_0_config_mec_cache +ffffffff81dde1a0 t gfx_v11_0_enable_gui_idle_interrupt +ffffffff81dde2b0 t gfx_v11_0_cp_compute_enable +ffffffff81dde480 t gfx_v11_0_cp_gfx_enable +ffffffff81dde670 t amdgpu_bo_reserve +ffffffff81dde7f0 t gfx_v11_0_kiq_init_register +ffffffff81ddf660 t gfx_v11_0_cp_gfx_switch_pipe +ffffffff81ddf740 t gfx_v11_0_cp_gfx_set_doorbell +ffffffff81ddf920 t gfx_v11_0_cp_gfx_start +ffffffff81de1000 t gfx_v8_0_early_init +ffffffff81de1310 t gfx_v8_0_late_init +ffffffff81de1a10 t gfx_v8_0_sw_init +ffffffff81de30e0 t gfx_v8_0_sw_fini +ffffffff81de3390 t gfx_v8_0_hw_init +ffffffff81de55c0 t gfx_v8_0_hw_fini +ffffffff81de5ab0 t gfx_v8_0_suspend +ffffffff81de5af0 t gfx_v8_0_resume +ffffffff81de5b00 t gfx_v8_0_is_idle +ffffffff81de5b70 t gfx_v8_0_wait_for_idle +ffffffff81de5c10 t gfx_v8_0_check_soft_reset +ffffffff81de5cf0 t gfx_v8_0_pre_soft_reset +ffffffff81de5e70 t gfx_v8_0_soft_reset +ffffffff81de6020 t gfx_v8_0_post_soft_reset +ffffffff81de61d0 t gfx_v8_0_set_clockgating_state +ffffffff81de6490 t gfx_v8_0_set_powergating_state +ffffffff81de6840 t gfx_v8_0_get_clockgating_state +ffffffff81de6920 t gfx_v8_0_get_gpu_clock_counter +ffffffff81de69b0 t gfx_v8_0_select_se_sh +ffffffff81de6a10 t gfx_v8_0_read_wave_data +ffffffff81de6eb0 t gfx_v8_0_read_wave_sgprs +ffffffff81de6f60 t gfx_v8_0_select_me_pipe_q +ffffffff81de6f80 t gfx_v8_0_ring_get_rptr +ffffffff81de6fb0 t gfx_v8_0_ring_get_wptr_compute +ffffffff81de6fe0 t gfx_v8_0_ring_set_wptr_compute +ffffffff81de7010 t gfx_v8_0_ring_emit_fence_kiq +ffffffff81de7440 t gfx_v8_0_ring_test_ring +ffffffff81de7640 t gfx_v8_0_ring_emit_rreg +ffffffff81de78d0 t gfx_v8_0_ring_emit_wreg +ffffffff81de7b00 t gfx_v8_0_ring_get_wptr_gfx +ffffffff81de7b50 t gfx_v8_0_ring_set_wptr_gfx +ffffffff81de7bc0 t gfx_v8_0_ring_emit_ib_gfx +ffffffff81de8120 t gfx_v8_0_ring_emit_fence_gfx +ffffffff81de8620 t gfx_v8_0_ring_emit_pipeline_sync +ffffffff81de8910 t gfx_v8_0_ring_emit_vm_flush +ffffffff81de8cc0 t gfx_v8_0_ring_emit_hdp_flush +ffffffff81de8fe0 t gfx_v8_0_ring_emit_gds_switch +ffffffff81de97a0 t gfx_v8_0_ring_test_ib +ffffffff81de9950 t gfx_v8_0_ring_emit_init_cond_exec +ffffffff81de9b80 t gfx_v8_0_ring_emit_patch_cond_exec +ffffffff81de9c30 t gfx_v8_ring_emit_sb +ffffffff81de9d10 t gfx_v8_ring_emit_cntxcntl +ffffffff81dea2b0 t gfx_v8_0_ring_soft_recovery +ffffffff81dea2d0 t gfx_v8_0_emit_mem_sync +ffffffff81dea4d0 t gfx_v8_0_ring_emit_ib_compute +ffffffff81dea7d0 t gfx_v8_0_ring_emit_fence_compute +ffffffff81deaad0 t gfx_v8_0_emit_mem_sync_compute +ffffffff81dead90 t gfx_v8_0_emit_wave_limit +ffffffff81deaf40 t gfx_v8_0_set_eop_interrupt_state +ffffffff81deb150 t gfx_v8_0_eop_irq +ffffffff81deb280 t gfx_v8_0_set_priv_reg_fault_state +ffffffff81deb2f0 t gfx_v8_0_priv_reg_irq +ffffffff81deb410 t gfx_v8_0_set_priv_inst_fault_state +ffffffff81deb480 t gfx_v8_0_priv_inst_irq +ffffffff81deb5a0 t gfx_v8_0_set_cp_ecc_int_state +ffffffff81deb810 t gfx_v8_0_cp_ecc_error_irq +ffffffff81deb850 t gfx_v8_0_set_sq_int_state +ffffffff81deb8d0 t gfx_v8_0_sq_irq +ffffffff81deb960 t gfx_v8_0_parse_sq_irq +ffffffff81debbb0 t gfx_v8_0_is_rlc_enabled +ffffffff81debbf0 t gfx_v8_0_set_safe_mode +ffffffff81debce0 t gfx_v8_0_unset_safe_mode +ffffffff81debd80 t gfx_v8_0_rlc_init +ffffffff81debe20 t gfx_v8_0_get_csb_size +ffffffff81debe70 t gfx_v8_0_get_csb_buffer +ffffffff81debff0 t gfx_v8_0_cp_jump_table_num +ffffffff81dec030 t gfx_v8_0_rlc_resume +ffffffff81dec3b0 t gfx_v8_0_rlc_stop +ffffffff81dec420 t gfx_v8_0_rlc_reset +ffffffff81dec4a0 t gfx_v8_0_rlc_start +ffffffff81dec520 t gfx_v8_0_update_spm_vmid +ffffffff81dec590 t gfx_v8_0_init_save_restore_list +ffffffff81dec9b0 t gfx_v8_0_wait_for_rlc_serdes +ffffffff81decbd0 t gfx_v8_0_sq_irq_work_func +ffffffff81decbf0 t amdgpu_bo_unreserve +ffffffff81deccd0 t gfx_v8_0_kiq_resume +ffffffff81decf30 t gfx_v8_0_cp_gfx_resume +ffffffff81deda50 t gfx_v8_0_kcq_resume +ffffffff81dee480 t amdgpu_bo_reserve +ffffffff81dee600 t gfx_v8_0_mqd_commit +ffffffff81dee7e0 t gfx_v8_0_mqd_init +ffffffff81deec00 t gfx_v8_0_deactivate_hqd +ffffffff81deecc0 t gfx_v8_0_update_medium_grain_clock_gating +ffffffff81deeff0 t gfx_v8_0_update_coarse_grain_clock_gating +ffffffff81df0000 t gfx_v9_0_ras_error_inject +ffffffff81df01a0 t gfx_v9_0_query_ras_error_count +ffffffff81df0d40 t gfx_v9_0_reset_ras_error_count +ffffffff81df1780 T gfx_v9_0_select_se_sh +ffffffff81df1820 t gfx_v9_0_early_init +ffffffff81df1c70 t gfx_v9_0_late_init +ffffffff81df2980 t gfx_v9_0_sw_init +ffffffff81df3fe0 t gfx_v9_0_sw_fini +ffffffff81df4280 t gfx_v9_0_hw_init +ffffffff81df7320 t gfx_v9_0_hw_fini +ffffffff81df7a80 t gfx_v9_0_suspend +ffffffff81df7ac0 t gfx_v9_0_resume +ffffffff81df7ad0 t gfx_v9_0_is_idle +ffffffff81df7b50 t gfx_v9_0_wait_for_idle +ffffffff81df7c30 t gfx_v9_0_soft_reset +ffffffff81df7fb0 t gfx_v9_0_set_clockgating_state +ffffffff81df8070 t gfx_v9_0_set_powergating_state +ffffffff81df8460 t gfx_v9_0_get_clockgating_state +ffffffff81df8570 t gfx_v9_0_kiq_set_resources +ffffffff81df88a0 t gfx_v9_0_kiq_map_queues +ffffffff81df8be0 t gfx_v9_0_kiq_unmap_queues +ffffffff81df8f60 t gfx_v9_0_kiq_query_status +ffffffff81df9260 t gfx_v9_0_kiq_invalidate_tlbs +ffffffff81df9380 t gfx_v9_0_ring_get_rptr_compute +ffffffff81df93b0 t gfx_v9_0_ring_get_wptr_compute +ffffffff81df9410 t gfx_v9_0_ring_set_wptr_compute +ffffffff81df9470 t gfx_v9_0_ring_emit_fence_kiq +ffffffff81df98a0 t gfx_v9_0_ring_test_ring +ffffffff81df9ad0 t gfx_v9_0_ring_emit_rreg +ffffffff81df9d60 t gfx_v9_0_ring_emit_wreg +ffffffff81df9f90 t gfx_v9_0_ring_emit_reg_wait +ffffffff81df9fe0 t gfx_v9_0_ring_emit_reg_write_reg_wait +ffffffff81dfa080 t gfx_v9_0_wait_reg_mem +ffffffff81dfa3b0 t gfx_v9_0_ring_get_rptr_gfx +ffffffff81dfa3e0 t gfx_v9_0_ring_get_wptr_gfx +ffffffff81dfa4f0 t gfx_v9_0_ring_set_wptr_gfx +ffffffff81dfa610 t gfx_v9_0_ring_emit_ib_gfx +ffffffff81dfab30 t gfx_v9_0_ring_emit_fence +ffffffff81dfaef0 t gfx_v9_0_ring_emit_pipeline_sync +ffffffff81dfaf50 t gfx_v9_0_ring_emit_vm_flush +ffffffff81dfb060 t gfx_v9_0_ring_emit_hdp_flush +ffffffff81dfb130 t gfx_v9_0_ring_emit_gds_switch +ffffffff81dfb210 t gfx_v9_0_ring_test_ib +ffffffff81dfb3c0 t gfx_v9_0_ring_emit_init_cond_exec +ffffffff81dfb5f0 t gfx_v9_0_ring_emit_patch_cond_exec +ffffffff81dfb6c0 t gfx_v9_ring_emit_sb +ffffffff81dfb7a0 t gfx_v9_ring_emit_cntxcntl +ffffffff81dfbb90 t gfx_v9_0_ring_emit_frame_cntl +ffffffff81dfbca0 t gfx_v9_0_ring_soft_recovery +ffffffff81dfbd10 t gfx_v9_0_emit_mem_sync +ffffffff81dfbfd0 t gfx_v9_0_write_data_to_reg +ffffffff81dfc1e0 t gfx_v9_0_ring_emit_ib_compute +ffffffff81dfc510 t gfx_v9_0_emit_wave_limit +ffffffff81dfc6e0 t gfx_v9_0_set_eop_interrupt_state +ffffffff81dfc8b0 t gfx_v9_0_eop_irq +ffffffff81dfc9e0 t gfx_v9_0_set_compute_eop_interrupt_state +ffffffff81dfcb90 t gfx_v9_0_set_priv_reg_fault_state +ffffffff81dfccb0 t gfx_v9_0_priv_reg_irq +ffffffff81dfcdd0 t gfx_v9_0_set_priv_inst_fault_state +ffffffff81dfcef0 t gfx_v9_0_priv_inst_irq +ffffffff81dfd010 t gfx_v9_0_set_cp_ecc_error_state +ffffffff81dfd840 t gfx_v9_0_is_rlc_enabled +ffffffff81dfd8c0 t gfx_v9_0_set_safe_mode +ffffffff81dfda10 t gfx_v9_0_unset_safe_mode +ffffffff81dfda70 t gfx_v9_0_rlc_init +ffffffff81dfe280 t gfx_v9_0_get_csb_size +ffffffff81dfe2d0 t gfx_v9_0_get_csb_buffer +ffffffff81dfe420 t gfx_v9_0_cp_jump_table_num +ffffffff81dfe470 t gfx_v9_0_rlc_resume +ffffffff81dff200 t gfx_v9_0_rlc_stop +ffffffff81dff690 t gfx_v9_0_rlc_reset +ffffffff81dff820 t gfx_v9_0_rlc_start +ffffffff81dff960 t gfx_v9_0_update_spm_vmid +ffffffff81dffa90 t gfx_v9_0_is_rlcg_access_range +ffffffff81dffae0 t gfx_v9_0_init_always_on_cu_mask +ffffffff81dffe40 t gfx_v9_0_init_csb +ffffffff81dfffd0 t gfx_v9_0_enable_lbpw +ffffffff81e000c0 t gfx_v9_0_enable_gui_idle_interrupt +ffffffff81e001c0 t amdgpu_bo_unreserve +ffffffff81e002a0 t gfx_v9_0_get_gpu_clock_counter +ffffffff81e00a20 t gfx_v9_0_read_wave_data +ffffffff81e00c60 t gfx_v9_0_read_wave_vgprs +ffffffff81e00c80 t gfx_v9_0_read_wave_sgprs +ffffffff81e00cd0 t gfx_v9_0_select_me_pipe_q +ffffffff81e00cf0 t wave_read_ind +ffffffff81e00e00 t wave_read_regs +ffffffff81e00f70 t gfx_v9_0_cp_gfx_enable +ffffffff81e01050 t amdgpu_bo_reserve +ffffffff81e011d0 t gfx_v9_0_kiq_init_register +ffffffff81e01e50 t gfx_v9_0_mqd_init +ffffffff81e02390 t gfx_v9_0_update_medium_grain_clock_gating +ffffffff81e028a0 t gfx_v9_0_update_3d_clock_gating +ffffffff81e02c80 t gfx_v9_0_update_coarse_grain_clock_gating +ffffffff81e04000 t gfx_v9_4_ras_error_inject +ffffffff81e04130 t gfx_v9_4_query_ras_error_count +ffffffff81e04ef0 t gfx_v9_4_query_ras_error_status +ffffffff81e050b0 t gfx_v9_4_reset_ras_error_count +ffffffff81e06000 T gfx_v9_4_2_do_edc_gpr_workarounds +ffffffff81e06790 T gfx_v9_4_2_init_golden_registers +ffffffff81e06820 T gfx_v9_4_2_debug_trap_config_init +ffffffff81e068c0 T gfx_v9_4_2_set_power_brake_sequence +ffffffff81e06a90 t gfx_v9_4_2_ras_error_inject +ffffffff81e06bc0 t gfx_v9_4_2_query_ras_error_count +ffffffff81e06c70 t gfx_v9_4_2_query_ras_error_status +ffffffff81e074b0 t gfx_v9_4_2_reset_ras_error_count +ffffffff81e07510 t gfx_v9_4_2_reset_ras_error_status +ffffffff81e079d0 t gfx_v9_4_2_enable_watchdog_timer +ffffffff81e07bf0 t gfx_v9_4_2_query_uctl2_poison_status +ffffffff81e07c70 t gfx_v9_4_2_run_shader +ffffffff81e07ff0 t gfx_v9_4_2_wait_for_waves_assigned +ffffffff81e08630 t gfx_v9_4_2_query_sram_edc_count +ffffffff81e08980 t gfx_v9_4_2_query_utc_edc_count +ffffffff81e08b60 t wave_read_ind +ffffffff81e09000 t gfxhub_v1_0_get_mc_fb_offset +ffffffff81e09080 t gfxhub_v1_0_setup_vm_pt_regs +ffffffff81e091b0 t gfxhub_v1_0_gart_enable +ffffffff81e0a690 t gfxhub_v1_0_gart_disable +ffffffff81e0a910 t gfxhub_v1_0_set_fault_enable_default +ffffffff81e0aa00 t gfxhub_v1_0_init +ffffffff81e0b000 T gfxhub_v1_1_get_xgmi_info +ffffffff81e0c000 t gfxhub_v2_0_get_fb_location +ffffffff81e0c090 t gfxhub_v2_0_get_mc_fb_offset +ffffffff81e0c110 t gfxhub_v2_0_setup_vm_pt_regs +ffffffff81e0c240 t gfxhub_v2_0_gart_enable +ffffffff81e0d440 t gfxhub_v2_0_gart_disable +ffffffff81e0d670 t gfxhub_v2_0_set_fault_enable_default +ffffffff81e0d760 t gfxhub_v2_0_init +ffffffff81e0d820 t gfxhub_v2_0_print_l2_protection_fault_status +ffffffff81e0da00 t gfxhub_v2_0_get_invalidate_req +ffffffff81e0e000 t gfxhub_v2_1_get_fb_location +ffffffff81e0e090 t gfxhub_v2_1_get_mc_fb_offset +ffffffff81e0e110 t gfxhub_v2_1_setup_vm_pt_regs +ffffffff81e0e240 t gfxhub_v2_1_gart_enable +ffffffff81e0f520 t gfxhub_v2_1_gart_disable +ffffffff81e0f7a0 t gfxhub_v2_1_set_fault_enable_default +ffffffff81e0f8b0 t gfxhub_v2_1_init +ffffffff81e0f970 t gfxhub_v2_1_get_xgmi_info +ffffffff81e0faa0 t gfxhub_v2_1_utcl2_harvest +ffffffff81e0fc70 t gfxhub_v2_1_save_regs +ffffffff81e106a0 t gfxhub_v2_1_restore_regs +ffffffff81e11270 t gfxhub_v2_1_halt +ffffffff81e11630 t gfxhub_v2_1_print_l2_protection_fault_status +ffffffff81e11810 t gfxhub_v2_1_get_invalidate_req +ffffffff81e12000 t gfxhub_v3_0_get_fb_location +ffffffff81e12090 t gfxhub_v3_0_get_mc_fb_offset +ffffffff81e12110 t gfxhub_v3_0_setup_vm_pt_regs +ffffffff81e12240 t gfxhub_v3_0_gart_enable +ffffffff81e134c0 t gfxhub_v3_0_gart_disable +ffffffff81e13740 t gfxhub_v3_0_set_fault_enable_default +ffffffff81e13ae0 t gfxhub_v3_0_init +ffffffff81e13ba0 t gfxhub_v3_0_print_l2_protection_fault_status +ffffffff81e13d80 t gfxhub_v3_0_get_invalidate_req +ffffffff81e14000 t gfxhub_v3_0_3_get_fb_location +ffffffff81e14090 t gfxhub_v3_0_3_get_mc_fb_offset +ffffffff81e14110 t gfxhub_v3_0_3_setup_vm_pt_regs +ffffffff81e14240 t gfxhub_v3_0_3_gart_enable +ffffffff81e154c0 t gfxhub_v3_0_3_gart_disable +ffffffff81e15760 t gfxhub_v3_0_3_set_fault_enable_default +ffffffff81e15870 t gfxhub_v3_0_3_init +ffffffff81e15930 t gfxhub_v3_0_3_print_l2_protection_fault_status +ffffffff81e15b10 t gfxhub_v3_0_3_get_invalidate_req +ffffffff81e16000 t gmc_v10_0_early_init +ffffffff81e161f0 t gmc_v10_0_late_init +ffffffff81e16260 t gmc_v10_0_sw_init +ffffffff81e16680 t gmc_v10_0_sw_fini +ffffffff81e166d0 t gmc_v10_0_hw_init +ffffffff81e16890 t gmc_v10_0_hw_fini +ffffffff81e16930 t gmc_v10_0_suspend +ffffffff81e169d0 t gmc_v10_0_resume +ffffffff81e16a20 t gmc_v10_0_is_idle +ffffffff81e16a50 t gmc_v10_0_wait_for_idle +ffffffff81e16a80 t gmc_v10_0_soft_reset +ffffffff81e16ab0 t gmc_v10_0_set_clockgating_state +ffffffff81e16b60 t gmc_v10_0_set_powergating_state +ffffffff81e16b90 t gmc_v10_0_get_clockgating_state +ffffffff81e16c30 t gmc_v10_0_flush_gpu_tlb +ffffffff81e16ed0 t gmc_v10_0_flush_gpu_tlb_pasid +ffffffff81e170f0 t gmc_v10_0_emit_flush_gpu_tlb +ffffffff81e172a0 t gmc_v10_0_emit_pasid_mapping +ffffffff81e17300 t gmc_v10_0_map_mtype +ffffffff81e17350 t gmc_v10_0_get_vm_pde +ffffffff81e17440 t gmc_v10_0_get_vm_pte +ffffffff81e174e0 t gmc_v10_0_get_vbios_fb_size +ffffffff81e17640 t gmc_v10_0_flush_vm_hub +ffffffff81e17aa0 t gmc_v10_0_vm_fault_interrupt_state +ffffffff81e17b10 t gmc_v10_0_process_interrupt +ffffffff81e17dd0 t gmc_v10_0_ecc_interrupt_state +ffffffff81e18000 t gmc_v11_0_early_init +ffffffff81e18220 t gmc_v11_0_late_init +ffffffff81e18290 t gmc_v11_0_sw_init +ffffffff81e185b0 t gmc_v11_0_sw_fini +ffffffff81e18600 t gmc_v11_0_hw_init +ffffffff81e18740 t gmc_v11_0_hw_fini +ffffffff81e187d0 t gmc_v11_0_suspend +ffffffff81e18860 t gmc_v11_0_resume +ffffffff81e188b0 t gmc_v11_0_is_idle +ffffffff81e188e0 t gmc_v11_0_wait_for_idle +ffffffff81e18910 t gmc_v11_0_soft_reset +ffffffff81e18940 t gmc_v11_0_set_clockgating_state +ffffffff81e189b0 t gmc_v11_0_set_powergating_state +ffffffff81e189e0 t gmc_v11_0_get_clockgating_state +ffffffff81e18a10 t gmc_v11_0_flush_gpu_tlb +ffffffff81e18ee0 t gmc_v11_0_flush_gpu_tlb_pasid +ffffffff81e190d0 t gmc_v11_0_emit_flush_gpu_tlb +ffffffff81e19270 t gmc_v11_0_emit_pasid_mapping +ffffffff81e192d0 t gmc_v11_0_map_mtype +ffffffff81e19320 t gmc_v11_0_get_vm_pde +ffffffff81e19410 t gmc_v11_0_get_vm_pte +ffffffff81e194b0 t gmc_v11_0_get_vbios_fb_size +ffffffff81e194e0 t gmc_v11_0_vm_fault_interrupt_state +ffffffff81e19550 t gmc_v11_0_process_interrupt +ffffffff81e19770 t gmc_v11_0_ecc_interrupt_state +ffffffff81e1a000 t gmc_v7_0_early_init +ffffffff81e1a090 t gmc_v7_0_late_init +ffffffff81e1a0d0 t gmc_v7_0_sw_init +ffffffff81e1a5d0 t gmc_v7_0_sw_fini +ffffffff81e1a680 t gmc_v7_0_hw_init +ffffffff81e1b030 t gmc_v7_0_hw_fini +ffffffff81e1b0f0 t gmc_v7_0_suspend +ffffffff81e1b130 t gmc_v7_0_resume +ffffffff81e1b180 t gmc_v7_0_is_idle +ffffffff81e1b1c0 t gmc_v7_0_wait_for_idle +ffffffff81e1b250 t gmc_v7_0_soft_reset +ffffffff81e1b4b0 t gmc_v7_0_set_clockgating_state +ffffffff81e1b710 t gmc_v7_0_set_powergating_state +ffffffff81e1b740 t gmc_v7_0_flush_gpu_tlb +ffffffff81e1b760 t gmc_v7_0_flush_gpu_tlb_pasid +ffffffff81e1b820 t gmc_v7_0_emit_flush_gpu_tlb +ffffffff81e1b8b0 t gmc_v7_0_emit_pasid_mapping +ffffffff81e1b8d0 t gmc_v7_0_set_prt +ffffffff81e1ba80 t gmc_v7_0_get_vm_pde +ffffffff81e1bae0 t gmc_v7_0_get_vm_pte +ffffffff81e1bb20 t gmc_v7_0_get_vbios_fb_size +ffffffff81e1bb90 t gmc_v7_0_vm_fault_interrupt_state +ffffffff81e1bc60 t gmc_v7_0_process_interrupt +ffffffff81e1c000 t gmc_v8_0_early_init +ffffffff81e1c090 t gmc_v8_0_late_init +ffffffff81e1c0d0 t gmc_v8_0_sw_init +ffffffff81e1c750 t gmc_v8_0_sw_fini +ffffffff81e1c800 t gmc_v8_0_hw_init +ffffffff81e1d4b0 t gmc_v8_0_hw_fini +ffffffff81e1d570 t gmc_v8_0_suspend +ffffffff81e1d5b0 t gmc_v8_0_resume +ffffffff81e1d600 t gmc_v8_0_is_idle +ffffffff81e1d640 t gmc_v8_0_wait_for_idle +ffffffff81e1d6d0 t gmc_v8_0_check_soft_reset +ffffffff81e1d740 t gmc_v8_0_pre_soft_reset +ffffffff81e1d8b0 t gmc_v8_0_soft_reset +ffffffff81e1d970 t gmc_v8_0_post_soft_reset +ffffffff81e1d9e0 t gmc_v8_0_set_clockgating_state +ffffffff81e1df90 t gmc_v8_0_set_powergating_state +ffffffff81e1dfc0 t gmc_v8_0_get_clockgating_state +ffffffff81e1e030 t gmc_v8_0_flush_gpu_tlb +ffffffff81e1e050 t gmc_v8_0_flush_gpu_tlb_pasid +ffffffff81e1e110 t gmc_v8_0_emit_flush_gpu_tlb +ffffffff81e1e1a0 t gmc_v8_0_emit_pasid_mapping +ffffffff81e1e1c0 t gmc_v8_0_set_prt +ffffffff81e1e370 t gmc_v8_0_get_vm_pde +ffffffff81e1e3d0 t gmc_v8_0_get_vm_pte +ffffffff81e1e420 t gmc_v8_0_get_vbios_fb_size +ffffffff81e1e490 t gmc_v8_0_vm_fault_interrupt_state +ffffffff81e1e560 t gmc_v8_0_process_interrupt +ffffffff81e1f000 T gmc_v9_0_restore_registers +ffffffff81e1f150 t gmc_v9_0_early_init +ffffffff81e1f500 t gmc_v9_0_late_init +ffffffff81e1f600 t gmc_v9_0_sw_init +ffffffff81e1fcb0 t gmc_v9_0_sw_fini +ffffffff81e1fd20 t gmc_v9_0_hw_init +ffffffff81e20110 t gmc_v9_0_hw_fini +ffffffff81e201d0 t gmc_v9_0_suspend +ffffffff81e20290 t gmc_v9_0_resume +ffffffff81e202e0 t gmc_v9_0_is_idle +ffffffff81e20310 t gmc_v9_0_wait_for_idle +ffffffff81e20340 t gmc_v9_0_soft_reset +ffffffff81e20370 t gmc_v9_0_set_clockgating_state +ffffffff81e203d0 t gmc_v9_0_set_powergating_state +ffffffff81e20400 t gmc_v9_0_get_clockgating_state +ffffffff81e20430 t gmc_v9_0_flush_gpu_tlb +ffffffff81e20a70 t gmc_v9_0_flush_gpu_tlb_pasid +ffffffff81e20d40 t gmc_v9_0_emit_flush_gpu_tlb +ffffffff81e20f10 t gmc_v9_0_emit_pasid_mapping +ffffffff81e20f80 t gmc_v9_0_map_mtype +ffffffff81e20fc0 t gmc_v9_0_get_vm_pde +ffffffff81e210c0 t gmc_v9_0_get_vm_pte +ffffffff81e21190 t gmc_v9_0_get_vbios_fb_size +ffffffff81e21320 t gmc_v9_0_vm_fault_interrupt_state +ffffffff81e216a0 t gmc_v9_0_process_interrupt +ffffffff81e21ce0 t gmc_v9_0_ecc_interrupt_state +ffffffff81e22000 t hdp_v4_0_query_ras_error_count +ffffffff81e220b0 t hdp_v4_0_reset_ras_error_count +ffffffff81e221c0 t hdp_v4_0_flush_hdp +ffffffff81e22210 t hdp_v4_0_invalidate_hdp +ffffffff81e222d0 t hdp_v4_0_update_clock_gating +ffffffff81e223d0 t hdp_v4_0_get_clockgating_state +ffffffff81e22420 t hdp_v4_0_init_registers +ffffffff81e23000 t hdp_v5_0_flush_hdp +ffffffff81e23050 t hdp_v5_0_invalidate_hdp +ffffffff81e230f0 t hdp_v5_0_update_clock_gating +ffffffff81e234e0 t hdp_v5_0_get_clockgating_state +ffffffff81e23600 t hdp_v5_0_init_registers +ffffffff81e24000 t hdp_v5_2_flush_hdp +ffffffff81e24050 t hdp_v5_2_update_clock_gating +ffffffff81e24440 t hdp_v5_2_get_clockgating_state +ffffffff81e25000 t hdp_v6_0_flush_hdp +ffffffff81e25050 t hdp_v6_0_update_clock_gating +ffffffff81e25360 t hdp_v6_0_get_clockgating_state +ffffffff81e26000 t iceland_ih_early_init +ffffffff81e26050 t iceland_ih_sw_init +ffffffff81e260b0 t iceland_ih_sw_fini +ffffffff81e260f0 t iceland_ih_hw_init +ffffffff81e26310 t iceland_ih_hw_fini +ffffffff81e263e0 t iceland_ih_suspend +ffffffff81e264b0 t iceland_ih_resume +ffffffff81e264f0 t iceland_ih_is_idle +ffffffff81e26530 t iceland_ih_wait_for_idle +ffffffff81e265c0 t iceland_ih_soft_reset +ffffffff81e266a0 t iceland_ih_set_clockgating_state +ffffffff81e266d0 t iceland_ih_set_powergating_state +ffffffff81e26700 t iceland_ih_get_wptr +ffffffff81e267f0 t iceland_ih_decode_iv +ffffffff81e26860 t iceland_ih_set_rptr +ffffffff81e27000 t ih_v6_0_early_init +ffffffff81e27050 t ih_v6_0_sw_init +ffffffff81e271b0 t ih_v6_0_sw_fini +ffffffff81e271f0 t ih_v6_0_hw_init +ffffffff81e277a0 t ih_v6_0_hw_fini +ffffffff81e27800 t ih_v6_0_suspend +ffffffff81e27860 t ih_v6_0_resume +ffffffff81e27870 t ih_v6_0_is_idle +ffffffff81e278a0 t ih_v6_0_wait_for_idle +ffffffff81e278d0 t ih_v6_0_soft_reset +ffffffff81e27900 t ih_v6_0_set_clockgating_state +ffffffff81e27a20 t ih_v6_0_set_powergating_state +ffffffff81e27b90 t ih_v6_0_get_clockgating_state +ffffffff81e27c20 t ih_v6_0_get_wptr +ffffffff81e27d10 t ih_v6_0_set_rptr +ffffffff81e27dd0 t ih_v6_0_self_irq +ffffffff81e27e30 t ih_v6_0_toggle_interrupts +ffffffff81e28010 t force_update_wptr_for_self_int +ffffffff81e29000 t imu_v11_0_init_microcode +ffffffff81e291f0 t imu_v11_0_load_microcode +ffffffff81e29550 t imu_v11_0_setup +ffffffff81e297d0 t imu_v11_0_start +ffffffff81e298c0 t imu_v11_0_program_rlc_ram +ffffffff81e29a70 t imu_v11_0_wait_for_reset_status +ffffffff81e29bb0 t program_imu_rlc_ram +ffffffff81e2a000 T imu_v11_0_3_program_rlc_ram +ffffffff81e2b000 T jpeg_v1_0_early_init +ffffffff81e2b060 T jpeg_v1_0_sw_init +ffffffff81e2b130 T jpeg_v1_0_sw_fini +ffffffff81e2b150 T jpeg_v1_0_start +ffffffff81e2bbc0 t jpeg_v1_0_decode_ring_get_rptr +ffffffff81e2bc40 t jpeg_v1_0_decode_ring_get_wptr +ffffffff81e2bcc0 t jpeg_v1_0_decode_ring_set_wptr +ffffffff81e2bd30 t jpeg_v1_0_decode_ring_emit_ib +ffffffff81e2c640 t jpeg_v1_0_decode_ring_emit_fence +ffffffff81e2cf90 t jpeg_v1_0_decode_ring_emit_vm_flush +ffffffff81e2d000 t jpeg_v1_0_decode_ring_nop +ffffffff81e2d160 t jpeg_v1_0_decode_ring_insert_start +ffffffff81e2d320 t jpeg_v1_0_decode_ring_insert_end +ffffffff81e2d4e0 t jpeg_v1_0_ring_begin_use +ffffffff81e2d5e0 t jpeg_v1_0_decode_ring_emit_wreg +ffffffff81e2d840 t jpeg_v1_0_decode_ring_emit_reg_wait +ffffffff81e2dc50 t jpeg_v1_0_set_interrupt_state +ffffffff81e2dc80 t jpeg_v1_0_process_interrupt +ffffffff81e2e000 T jpeg_v2_0_dec_ring_insert_start +ffffffff81e2e1a0 T jpeg_v2_0_dec_ring_insert_end +ffffffff81e2e340 T jpeg_v2_0_dec_ring_emit_fence +ffffffff81e2ea30 T jpeg_v2_0_dec_ring_emit_ib +ffffffff81e2f210 T jpeg_v2_0_dec_ring_emit_reg_wait +ffffffff81e2f5d0 T jpeg_v2_0_dec_ring_emit_vm_flush +ffffffff81e2f640 T jpeg_v2_0_dec_ring_emit_wreg +ffffffff81e2f880 T jpeg_v2_0_dec_ring_nop +ffffffff81e2f9e0 t jpeg_v2_0_early_init +ffffffff81e2fa50 t jpeg_v2_0_sw_init +ffffffff81e2fb60 t jpeg_v2_0_sw_fini +ffffffff81e2fbb0 t jpeg_v2_0_hw_init +ffffffff81e2fc30 t jpeg_v2_0_hw_fini +ffffffff81e2fd00 t jpeg_v2_0_suspend +ffffffff81e2fd20 t jpeg_v2_0_resume +ffffffff81e2fdb0 t jpeg_v2_0_is_idle +ffffffff81e2fe30 t jpeg_v2_0_wait_for_idle +ffffffff81e2ff20 t jpeg_v2_0_set_clockgating_state +ffffffff81e2ffd0 t jpeg_v2_0_set_powergating_state +ffffffff81e307d0 t jpeg_v2_0_dec_ring_get_rptr +ffffffff81e30850 t jpeg_v2_0_dec_ring_get_wptr +ffffffff81e308f0 t jpeg_v2_0_dec_ring_set_wptr +ffffffff81e30980 t jpeg_v2_0_set_interrupt_state +ffffffff81e309b0 t jpeg_v2_0_process_interrupt +ffffffff81e30a40 t jpeg_v2_0_enable_clock_gating +ffffffff81e30be0 t jpeg_v2_0_disable_clock_gating +ffffffff81e31000 t jpeg_v2_6_query_ras_poison_status +ffffffff81e31140 t jpeg_v2_5_early_init +ffffffff81e31410 t jpeg_v2_5_sw_init +ffffffff81e31630 t jpeg_v2_5_sw_fini +ffffffff81e31680 t jpeg_v2_5_hw_init +ffffffff81e31770 t jpeg_v2_5_hw_fini +ffffffff81e318b0 t jpeg_v2_5_suspend +ffffffff81e318d0 t jpeg_v2_5_resume +ffffffff81e319d0 t jpeg_v2_5_is_idle +ffffffff81e31ac0 t jpeg_v2_5_wait_for_idle +ffffffff81e31bf0 t jpeg_v2_5_set_clockgating_state +ffffffff81e31d60 t jpeg_v2_5_set_powergating_state +ffffffff81e32440 t jpeg_v2_5_dec_ring_get_rptr +ffffffff81e324d0 t jpeg_v2_5_dec_ring_get_wptr +ffffffff81e32580 t jpeg_v2_5_dec_ring_set_wptr +ffffffff81e32620 t jpeg_v2_6_dec_ring_insert_start +ffffffff81e327e0 t jpeg_v2_6_dec_ring_insert_end +ffffffff81e329a0 t jpeg_v2_5_set_interrupt_state +ffffffff81e329d0 t jpeg_v2_5_process_interrupt +ffffffff81e32ab0 t jpeg_v2_5_enable_clock_gating +ffffffff81e32b80 t jpeg_v2_5_disable_clock_gating +ffffffff81e33000 t jpeg_v3_0_early_init +ffffffff81e330e0 t jpeg_v3_0_sw_init +ffffffff81e331f0 t jpeg_v3_0_sw_fini +ffffffff81e33240 t jpeg_v3_0_hw_init +ffffffff81e332c0 t jpeg_v3_0_hw_fini +ffffffff81e33390 t jpeg_v3_0_suspend +ffffffff81e333b0 t jpeg_v3_0_resume +ffffffff81e33440 t jpeg_v3_0_is_idle +ffffffff81e334c0 t jpeg_v3_0_wait_for_idle +ffffffff81e335b0 t jpeg_v3_0_set_clockgating_state +ffffffff81e33660 t jpeg_v3_0_set_powergating_state +ffffffff81e33f10 t jpeg_v3_0_dec_ring_get_rptr +ffffffff81e33f90 t jpeg_v3_0_dec_ring_get_wptr +ffffffff81e34030 t jpeg_v3_0_dec_ring_set_wptr +ffffffff81e340c0 t jpeg_v3_0_set_interrupt_state +ffffffff81e340f0 t jpeg_v3_0_process_interrupt +ffffffff81e34180 t jpeg_v3_0_enable_clock_gating +ffffffff81e34250 t jpeg_v3_0_disable_clock_gating +ffffffff81e35000 t jpeg_v4_0_early_init +ffffffff81e35080 t jpeg_v4_0_sw_init +ffffffff81e35190 t jpeg_v4_0_sw_fini +ffffffff81e351e0 t jpeg_v4_0_hw_init +ffffffff81e352f0 t jpeg_v4_0_hw_fini +ffffffff81e353c0 t jpeg_v4_0_suspend +ffffffff81e353e0 t jpeg_v4_0_resume +ffffffff81e35430 t jpeg_v4_0_is_idle +ffffffff81e354b0 t jpeg_v4_0_wait_for_idle +ffffffff81e355a0 t jpeg_v4_0_set_clockgating_state +ffffffff81e35650 t jpeg_v4_0_set_powergating_state +ffffffff81e35e50 t jpeg_v4_0_dec_ring_get_rptr +ffffffff81e35ed0 t jpeg_v4_0_dec_ring_get_wptr +ffffffff81e35f70 t jpeg_v4_0_dec_ring_set_wptr +ffffffff81e36010 t jpeg_v4_0_set_interrupt_state +ffffffff81e36040 t jpeg_v4_0_process_interrupt +ffffffff81e360e0 t jpeg_v4_0_enable_clock_gating +ffffffff81e36290 t jpeg_v4_0_disable_clock_gating +ffffffff81e37000 t lsdma_v6_0_copy_mem +ffffffff81e37350 t lsdma_v6_0_fill_mem +ffffffff81e37630 t lsdma_v6_0_update_memory_power_gating +ffffffff81e38000 t mca_v3_0_mp0_query_ras_error_count +ffffffff81e38020 t mca_v3_0_ras_block_match +ffffffff81e38060 t mca_v3_0_mp1_query_ras_error_count +ffffffff81e38080 t mca_v3_0_mpio_query_ras_error_count +ffffffff81e380a0 t mca_v3_0_init +ffffffff81e39000 t mes_v10_0_late_init +ffffffff81e39040 t mes_v10_1_sw_init +ffffffff81e39640 t mes_v10_1_sw_fini +ffffffff81e397c0 t mes_v10_1_hw_init +ffffffff81e3a060 t mes_v10_1_hw_fini +ffffffff81e3a120 t mes_v10_1_suspend +ffffffff81e3a1f0 t mes_v10_1_resume +ffffffff81e3a240 t mes_v10_1_kiq_hw_init +ffffffff81e3a640 t mes_v10_1_add_hw_queue +ffffffff81e3a7b0 t mes_v10_1_remove_hw_queue +ffffffff81e3a840 t mes_v10_1_unmap_legacy_queue +ffffffff81e3a920 t mes_v10_1_suspend_gang +ffffffff81e3a950 t mes_v10_1_resume_gang +ffffffff81e3a980 t mes_v10_1_submit_pkt_and_poll_completion +ffffffff81e3ab80 t mes_v10_1_load_microcode +ffffffff81e3b370 t mes_v10_1_enable +ffffffff81e3b7e0 t mes_v10_1_queue_init +ffffffff81e3ba80 t amdgpu_bo_unreserve +ffffffff81e3bb60 t mes_v10_1_ring_get_rptr +ffffffff81e3bb90 t mes_v10_1_ring_get_wptr +ffffffff81e3bbf0 t mes_v10_1_ring_set_wptr +ffffffff81e3c000 t mes_v11_0_late_init +ffffffff81e3c070 t mes_v11_0_sw_init +ffffffff81e3c650 t mes_v11_0_sw_fini +ffffffff81e3c840 t mes_v11_0_hw_init +ffffffff81e3d050 t mes_v11_0_hw_fini +ffffffff81e3d080 t mes_v11_0_suspend +ffffffff81e3d090 t mes_v11_0_resume +ffffffff81e3d0e0 t mes_v11_0_kiq_hw_init +ffffffff81e3d2e0 t mes_v11_0_kiq_hw_fini +ffffffff81e3d720 t mes_v11_0_add_hw_queue +ffffffff81e3d920 t mes_v11_0_remove_hw_queue +ffffffff81e3d9b0 t mes_v11_0_unmap_legacy_queue +ffffffff81e3dab0 t mes_v11_0_suspend_gang +ffffffff81e3dae0 t mes_v11_0_resume_gang +ffffffff81e3db10 t mes_v11_0_misc_op +ffffffff81e3dc80 t mes_v11_0_submit_pkt_and_poll_completion +ffffffff81e3dea0 t mes_v11_0_load_microcode +ffffffff81e3e600 t mes_v11_0_enable +ffffffff81e3eaf0 t mes_v11_0_queue_init +ffffffff81e3f580 t amdgpu_bo_unreserve +ffffffff81e3f660 t mes_v11_0_mqd_init +ffffffff81e3f860 t mes_v11_0_ring_get_rptr +ffffffff81e3f890 t mes_v11_0_ring_get_wptr +ffffffff81e3f8f0 t mes_v11_0_ring_set_wptr +ffffffff81e40000 t mmhub_v1_0_query_ras_error_count +ffffffff81e40150 t mmhub_v1_0_reset_ras_error_count +ffffffff81e401f0 t mmhub_v1_0_get_fb_location +ffffffff81e40300 t mmhub_v1_0_init +ffffffff81e403b0 t mmhub_v1_0_gart_enable +ffffffff81e416e0 t mmhub_v1_0_set_fault_enable_default +ffffffff81e417f0 t mmhub_v1_0_gart_disable +ffffffff81e41a70 t mmhub_v1_0_set_clockgating +ffffffff81e41ef0 t mmhub_v1_0_get_clockgating +ffffffff81e42010 t mmhub_v1_0_setup_vm_pt_regs +ffffffff81e42140 t mmhub_v1_0_update_power_gating +ffffffff81e43000 t mmhub_v1_7_query_ras_error_count +ffffffff81e43150 t mmhub_v1_7_query_ras_error_status +ffffffff81e43230 t mmhub_v1_7_reset_ras_error_count +ffffffff81e432d0 t mmhub_v1_7_reset_ras_error_status +ffffffff81e433c0 t mmhub_v1_7_get_fb_location +ffffffff81e434d0 t mmhub_v1_7_init +ffffffff81e43570 t mmhub_v1_7_gart_enable +ffffffff81e44a50 t mmhub_v1_7_set_fault_enable_default +ffffffff81e44b60 t mmhub_v1_7_gart_disable +ffffffff81e44de0 t mmhub_v1_7_set_clockgating +ffffffff81e45150 t mmhub_v1_7_get_clockgating +ffffffff81e45270 t mmhub_v1_7_setup_vm_pt_regs +ffffffff81e46000 t mmhub_v2_0_init +ffffffff81e460c0 t mmhub_v2_0_gart_enable +ffffffff81e47240 t mmhub_v2_0_set_fault_enable_default +ffffffff81e47350 t mmhub_v2_0_gart_disable +ffffffff81e475d0 t mmhub_v2_0_set_clockgating +ffffffff81e47910 t mmhub_v2_0_get_clockgating +ffffffff81e47aa0 t mmhub_v2_0_setup_vm_pt_regs +ffffffff81e47be0 t mmhub_v2_0_print_l2_protection_fault_status +ffffffff81e47e40 t mmhub_v2_0_get_invalidate_req +ffffffff81e48000 t mmhub_v2_3_init +ffffffff81e480d0 t mmhub_v2_3_gart_enable +ffffffff81e49460 t mmhub_v2_3_set_fault_enable_default +ffffffff81e49550 t mmhub_v2_3_gart_disable +ffffffff81e497e0 t mmhub_v2_3_set_clockgating +ffffffff81e49c60 t mmhub_v2_3_get_clockgating +ffffffff81e49e40 t mmhub_v2_3_setup_vm_pt_regs +ffffffff81e49f80 t mmhub_v2_3_print_l2_protection_fault_status +ffffffff81e4a1a0 t mmhub_v2_3_get_invalidate_req +ffffffff81e4b000 t mmhub_v3_0_get_fb_location +ffffffff81e4b090 t mmhub_v3_0_get_mc_fb_offset +ffffffff81e4b110 t mmhub_v3_0_init +ffffffff81e4b1e0 t mmhub_v3_0_gart_enable +ffffffff81e4c370 t mmhub_v3_0_set_fault_enable_default +ffffffff81e4c480 t mmhub_v3_0_gart_disable +ffffffff81e4c700 t mmhub_v3_0_set_clockgating +ffffffff81e4c8c0 t mmhub_v3_0_get_clockgating +ffffffff81e4c970 t mmhub_v3_0_setup_vm_pt_regs +ffffffff81e4caa0 t mmhub_v3_0_print_l2_protection_fault_status +ffffffff81e4ccb0 t mmhub_v3_0_get_invalidate_req +ffffffff81e4d000 t mmhub_v3_0_1_get_fb_location +ffffffff81e4d090 t mmhub_v3_0_1_get_mc_fb_offset +ffffffff81e4d110 t mmhub_v3_0_1_init +ffffffff81e4d1e0 t mmhub_v3_0_1_gart_enable +ffffffff81e4e460 t mmhub_v3_0_1_set_fault_enable_default +ffffffff81e4e550 t mmhub_v3_0_1_gart_disable +ffffffff81e4e7e0 t mmhub_v3_0_1_set_clockgating +ffffffff81e4e990 t mmhub_v3_0_1_get_clockgating +ffffffff81e4ea40 t mmhub_v3_0_1_setup_vm_pt_regs +ffffffff81e4eb80 t mmhub_v3_0_1_print_l2_protection_fault_status +ffffffff81e4ed90 t mmhub_v3_0_1_get_invalidate_req +ffffffff81e4f000 t mmhub_v3_0_2_get_fb_location +ffffffff81e4f090 t mmhub_v3_0_2_get_mc_fb_offset +ffffffff81e4f110 t mmhub_v3_0_2_init +ffffffff81e4f1e0 t mmhub_v3_0_2_gart_enable +ffffffff81e50360 t mmhub_v3_0_2_set_fault_enable_default +ffffffff81e50470 t mmhub_v3_0_2_gart_disable +ffffffff81e506f0 t mmhub_v3_0_2_set_clockgating +ffffffff81e50720 t mmhub_v3_0_2_get_clockgating +ffffffff81e50750 t mmhub_v3_0_2_setup_vm_pt_regs +ffffffff81e50880 t mmhub_v3_0_2_print_l2_protection_fault_status +ffffffff81e50a70 t mmhub_v3_0_2_get_invalidate_req +ffffffff81e51000 t mmhub_v9_4_query_ras_error_count +ffffffff81e51150 t mmhub_v9_4_query_ras_error_status +ffffffff81e51230 t mmhub_v9_4_reset_ras_error_count +ffffffff81e512f0 t mmhub_v9_4_get_fb_location +ffffffff81e51400 t mmhub_v9_4_init +ffffffff81e51540 t mmhub_v9_4_gart_enable +ffffffff81e529d0 t mmhub_v9_4_set_fault_enable_default +ffffffff81e52bb0 t mmhub_v9_4_gart_disable +ffffffff81e52f10 t mmhub_v9_4_set_clockgating +ffffffff81e533d0 t mmhub_v9_4_get_clockgating +ffffffff81e534f0 t mmhub_v9_4_setup_vm_pt_regs +ffffffff81e53530 t mmhub_v9_4_setup_hubid_vm_pt_regs +ffffffff81e54000 T xgpu_ai_mailbox_set_irq_funcs +ffffffff81e54050 T xgpu_ai_mailbox_add_irq_id +ffffffff81e540e0 T xgpu_ai_mailbox_get_irq +ffffffff81e54190 t xgpu_ai_mailbox_flr_work +ffffffff81e54390 T xgpu_ai_mailbox_put_irq +ffffffff81e543d0 t xgpu_ai_request_full_gpu_access +ffffffff81e543f0 t xgpu_ai_release_full_gpu_access +ffffffff81e54410 t xgpu_ai_request_init_data +ffffffff81e54470 t xgpu_ai_request_reset +ffffffff81e54520 t xgpu_ai_mailbox_trans_msg +ffffffff81e54750 t xgpu_ai_set_mailbox_ack_irq +ffffffff81e547e0 t xgpu_ai_mailbox_ack_irq +ffffffff81e54830 t xgpu_ai_set_mailbox_rcv_irq +ffffffff81e548c0 t xgpu_ai_mailbox_rcv_irq +ffffffff81e549a0 t xgpu_ai_send_access_requests +ffffffff81e54a90 t xgpu_ai_poll_msg +ffffffff81e55000 T xgpu_nv_mailbox_set_irq_funcs +ffffffff81e55050 T xgpu_nv_mailbox_add_irq_id +ffffffff81e550e0 T xgpu_nv_mailbox_get_irq +ffffffff81e55190 t xgpu_nv_mailbox_flr_work +ffffffff81e553b0 T xgpu_nv_mailbox_put_irq +ffffffff81e553f0 t xgpu_nv_request_full_gpu_access +ffffffff81e55410 t xgpu_nv_release_full_gpu_access +ffffffff81e55430 t xgpu_nv_request_init_data +ffffffff81e55450 t xgpu_nv_request_reset +ffffffff81e55550 t xgpu_nv_mailbox_trans_msg +ffffffff81e556f0 t xgpu_nv_set_mailbox_ack_irq +ffffffff81e55760 t xgpu_nv_mailbox_ack_irq +ffffffff81e557b0 t xgpu_nv_set_mailbox_rcv_irq +ffffffff81e55830 t xgpu_nv_mailbox_rcv_irq +ffffffff81e558e0 t xgpu_nv_send_access_requests +ffffffff81e56000 T xgpu_vi_init_golden_registers +ffffffff81e560c0 T xgpu_vi_mailbox_set_irq_funcs +ffffffff81e56110 T xgpu_vi_mailbox_add_irq_id +ffffffff81e561a0 T xgpu_vi_mailbox_get_irq +ffffffff81e56250 t xgpu_vi_mailbox_flr_work +ffffffff81e563a0 T xgpu_vi_mailbox_put_irq +ffffffff81e563e0 t xgpu_vi_request_full_gpu_access +ffffffff81e56400 t xgpu_vi_release_full_gpu_access +ffffffff81e56420 t xgpu_vi_request_reset +ffffffff81e56440 t xgpu_vi_wait_reset_cmpl +ffffffff81e56520 t xgpu_vi_set_mailbox_ack_irq +ffffffff81e56590 t xgpu_vi_mailbox_ack_irq +ffffffff81e565e0 t xgpu_vi_set_mailbox_rcv_irq +ffffffff81e56660 t xgpu_vi_mailbox_rcv_irq +ffffffff81e56700 t xgpu_vi_mailbox_rcv_msg +ffffffff81e56820 t xgpu_vi_send_access_requests +ffffffff81e57000 t navi10_ih_early_init +ffffffff81e57050 t navi10_ih_sw_init +ffffffff81e571c0 t navi10_ih_sw_fini +ffffffff81e57200 t navi10_ih_hw_init +ffffffff81e57630 t navi10_ih_hw_fini +ffffffff81e57690 t navi10_ih_suspend +ffffffff81e576f0 t navi10_ih_resume +ffffffff81e57700 t navi10_ih_is_idle +ffffffff81e57730 t navi10_ih_wait_for_idle +ffffffff81e57760 t navi10_ih_soft_reset +ffffffff81e57790 t navi10_ih_set_clockgating_state +ffffffff81e578b0 t navi10_ih_set_powergating_state +ffffffff81e578e0 t navi10_ih_get_clockgating_state +ffffffff81e57970 t navi10_ih_get_wptr +ffffffff81e57a80 t navi10_ih_set_rptr +ffffffff81e57b50 t navi10_ih_self_irq +ffffffff81e57bc0 t navi10_ih_toggle_interrupts +ffffffff81e57d50 t force_update_wptr_for_self_int +ffffffff81e59000 t nbio_v2_3_get_hdp_flush_req_offset +ffffffff81e59040 t nbio_v2_3_get_hdp_flush_done_offset +ffffffff81e59080 t nbio_v2_3_get_pcie_index_offset +ffffffff81e590b0 t nbio_v2_3_get_pcie_data_offset +ffffffff81e590e0 t nbio_v2_3_get_rev_id +ffffffff81e59130 t nbio_v2_3_mc_access_enable +ffffffff81e591e0 t nbio_v2_3_get_memsize +ffffffff81e59240 t nbio_v2_3_sdma_doorbell_range +ffffffff81e592e0 t nbio_v2_3_vcn_doorbell_range +ffffffff81e59360 t nbio_v2_3_enable_doorbell_aperture +ffffffff81e59450 t nbio_v2_3_enable_doorbell_selfring_aperture +ffffffff81e595b0 t nbio_v2_3_ih_doorbell_range +ffffffff81e596c0 t nbio_v2_3_update_medium_grain_clock_gating +ffffffff81e59760 t nbio_v2_3_update_medium_grain_light_sleep +ffffffff81e59800 t nbio_v2_3_get_clockgating_state +ffffffff81e59880 t nbio_v2_3_ih_control +ffffffff81e599d0 t nbio_v2_3_init_registers +ffffffff81e59a60 t nbio_v2_3_remap_hdp_registers +ffffffff81e59b60 t nbio_v2_3_enable_aspm +ffffffff81e59bf0 t nbio_v2_3_program_aspm +ffffffff81e5a280 t nbio_v2_3_apply_lc_spc_mode_wa +ffffffff81e5a310 t nbio_v2_3_apply_l1_link_width_reconfig_wa +ffffffff81e5a380 t nbio_v2_3_clear_doorbell_interrupt +ffffffff81e5b000 t nbio_v4_3_get_hdp_flush_req_offset +ffffffff81e5b040 t nbio_v4_3_get_hdp_flush_done_offset +ffffffff81e5b080 t nbio_v4_3_get_pcie_index_offset +ffffffff81e5b0b0 t nbio_v4_3_get_pcie_data_offset +ffffffff81e5b0e0 t nbio_v4_3_get_rev_id +ffffffff81e5b160 t nbio_v4_3_mc_access_enable +ffffffff81e5b210 t nbio_v4_3_get_memsize +ffffffff81e5b270 t nbio_v4_3_sdma_doorbell_range +ffffffff81e5b3e0 t nbio_v4_3_vcn_doorbell_range +ffffffff81e5b590 t nbio_v4_3_gc_doorbell_init +ffffffff81e5b680 t nbio_v4_3_enable_doorbell_aperture +ffffffff81e5b770 t nbio_v4_3_enable_doorbell_selfring_aperture +ffffffff81e5b8d0 t nbio_v4_3_ih_doorbell_range +ffffffff81e5b9f0 t nbio_v4_3_update_medium_grain_clock_gating +ffffffff81e5bb20 t nbio_v4_3_update_medium_grain_light_sleep +ffffffff81e5bc50 t nbio_v4_3_get_clockgating_state +ffffffff81e5bd60 t nbio_v4_3_ih_control +ffffffff81e5beb0 t nbio_v4_3_init_registers +ffffffff81e5bfc0 t nbio_v4_3_remap_hdp_registers +ffffffff81e5c0c0 t nbio_v4_3_program_aspm +ffffffff81e5cd50 t nbio_v4_3_get_rom_offset +ffffffff81e5cdd0 t nbio_v4_3_sriov_sdma_doorbell_range +ffffffff81e5ce00 t nbio_v4_3_sriov_vcn_doorbell_range +ffffffff81e5ce30 t nbio_v4_3_sriov_gc_doorbell_init +ffffffff81e5ce60 t nbio_v4_3_sriov_ih_doorbell_range +ffffffff81e5d000 t nbio_v6_1_get_hdp_flush_req_offset +ffffffff81e5d040 t nbio_v6_1_get_hdp_flush_done_offset +ffffffff81e5d080 t nbio_v6_1_get_pcie_index_offset +ffffffff81e5d0b0 t nbio_v6_1_get_pcie_data_offset +ffffffff81e5d0e0 t nbio_v6_1_get_rev_id +ffffffff81e5d160 t nbio_v6_1_mc_access_enable +ffffffff81e5d210 t nbio_v6_1_get_memsize +ffffffff81e5d270 t nbio_v6_1_sdma_doorbell_range +ffffffff81e5d300 t nbio_v6_1_enable_doorbell_aperture +ffffffff81e5d3f0 t nbio_v6_1_enable_doorbell_selfring_aperture +ffffffff81e5d550 t nbio_v6_1_ih_doorbell_range +ffffffff81e5d660 t nbio_v6_1_update_medium_grain_clock_gating +ffffffff81e5d700 t nbio_v6_1_update_medium_grain_light_sleep +ffffffff81e5d7a0 t nbio_v6_1_get_clockgating_state +ffffffff81e5d820 t nbio_v6_1_ih_control +ffffffff81e5d970 t nbio_v6_1_init_registers +ffffffff81e5da40 t nbio_v6_1_remap_hdp_registers +ffffffff81e5db40 t nbio_v6_1_program_aspm +ffffffff81e5e000 t nbio_v7_0_get_hdp_flush_req_offset +ffffffff81e5e040 t nbio_v7_0_get_hdp_flush_done_offset +ffffffff81e5e080 t nbio_v7_0_get_pcie_index_offset +ffffffff81e5e0b0 t nbio_v7_0_get_pcie_data_offset +ffffffff81e5e0e0 t nbio_v7_0_get_rev_id +ffffffff81e5e160 t nbio_v7_0_mc_access_enable +ffffffff81e5e210 t nbio_v7_0_get_memsize +ffffffff81e5e270 t nbio_v7_0_sdma_doorbell_range +ffffffff81e5e300 t nbio_v7_0_vcn_doorbell_range +ffffffff81e5e370 t nbio_v7_0_enable_doorbell_aperture +ffffffff81e5e460 t nbio_v7_0_enable_doorbell_selfring_aperture +ffffffff81e5e490 t nbio_v7_0_ih_doorbell_range +ffffffff81e5e5a0 t nbio_v7_0_update_medium_grain_clock_gating +ffffffff81e5e6e0 t nbio_v7_0_update_medium_grain_light_sleep +ffffffff81e5e780 t nbio_v7_0_get_clockgating_state +ffffffff81e5e800 t nbio_v7_0_ih_control +ffffffff81e5e950 t nbio_v7_0_init_registers +ffffffff81e5e9a0 t nbio_v7_0_remap_hdp_registers +ffffffff81e5eaa0 t nbio_7_0_read_syshub_ind_mmr +ffffffff81e5eb70 t nbio_7_0_write_syshub_ind_mmr +ffffffff81e5f000 t nbio_v7_2_get_hdp_flush_req_offset +ffffffff81e5f040 t nbio_v7_2_get_hdp_flush_done_offset +ffffffff81e5f080 t nbio_v7_2_get_pcie_index_offset +ffffffff81e5f0b0 t nbio_v7_2_get_pcie_data_offset +ffffffff81e5f0e0 t nbio_v7_2_get_pcie_port_index_offset +ffffffff81e5f110 t nbio_v7_2_get_pcie_port_data_offset +ffffffff81e5f140 t nbio_v7_2_get_rev_id +ffffffff81e5f220 t nbio_v7_2_mc_access_enable +ffffffff81e5f360 t nbio_v7_2_get_memsize +ffffffff81e5f3c0 t nbio_v7_2_sdma_doorbell_range +ffffffff81e5f450 t nbio_v7_2_vcn_doorbell_range +ffffffff81e5f4d0 t nbio_v7_2_enable_doorbell_aperture +ffffffff81e5f5b0 t nbio_v7_2_enable_doorbell_selfring_aperture +ffffffff81e5f710 t nbio_v7_2_ih_doorbell_range +ffffffff81e5f790 t nbio_v7_2_update_medium_grain_clock_gating +ffffffff81e5f840 t nbio_v7_2_update_medium_grain_light_sleep +ffffffff81e5f9d0 t nbio_v7_2_get_clockgating_state +ffffffff81e5fa60 t nbio_v7_2_ih_control +ffffffff81e5fbb0 t nbio_v7_2_init_registers +ffffffff81e5fd60 t nbio_v7_2_remap_hdp_registers +ffffffff81e60000 t nbio_v7_4_query_ras_error_count +ffffffff81e601a0 t nbio_v7_4_handle_ras_controller_intr_no_bifring +ffffffff81e603d0 t nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring +ffffffff81e60580 t nbio_v7_4_init_ras_controller_interrupt +ffffffff81e605c0 t nbio_v7_4_init_ras_err_event_athub_interrupt +ffffffff81e60600 t nbio_v7_4_get_hdp_flush_req_offset +ffffffff81e60640 t nbio_v7_4_get_hdp_flush_done_offset +ffffffff81e60680 t nbio_v7_4_get_pcie_index_offset +ffffffff81e606b0 t nbio_v7_4_get_pcie_data_offset +ffffffff81e606e0 t nbio_v7_4_get_rev_id +ffffffff81e607a0 t nbio_v7_4_mc_access_enable +ffffffff81e60850 t nbio_v7_4_get_memsize +ffffffff81e608b0 t nbio_v7_4_sdma_doorbell_range +ffffffff81e60970 t nbio_v7_4_vcn_doorbell_range +ffffffff81e60a10 t nbio_v7_4_enable_doorbell_aperture +ffffffff81e60b00 t nbio_v7_4_enable_doorbell_selfring_aperture +ffffffff81e60c60 t nbio_v7_4_ih_doorbell_range +ffffffff81e60d70 t nbio_v7_4_enable_doorbell_interrupt +ffffffff81e60eb0 t nbio_v7_4_update_medium_grain_clock_gating +ffffffff81e60ee0 t nbio_v7_4_update_medium_grain_light_sleep +ffffffff81e60f80 t nbio_v7_4_get_clockgating_state +ffffffff81e61000 t nbio_v7_4_ih_control +ffffffff81e61150 t nbio_v7_4_init_registers +ffffffff81e61230 t nbio_v7_4_remap_hdp_registers +ffffffff81e61330 t nbio_v7_4_program_aspm +ffffffff81e61730 t nbio_v7_4_set_ras_controller_irq_state +ffffffff81e618c0 t nbio_v7_4_process_ras_controller_irq +ffffffff81e618f0 t nbio_v7_4_set_ras_err_event_athub_irq_state +ffffffff81e61a80 t nbio_v7_4_process_err_event_athub_irq +ffffffff81e62000 t nbio_v7_7_get_hdp_flush_req_offset +ffffffff81e62040 t nbio_v7_7_get_hdp_flush_done_offset +ffffffff81e62080 t nbio_v7_7_get_pcie_index_offset +ffffffff81e620b0 t nbio_v7_7_get_pcie_data_offset +ffffffff81e620e0 t nbio_v7_7_get_pcie_port_index_offset +ffffffff81e62110 t nbio_v7_7_get_pcie_port_data_offset +ffffffff81e62140 t nbio_v7_7_get_rev_id +ffffffff81e621c0 t nbio_v7_7_mc_access_enable +ffffffff81e62270 t nbio_v7_7_get_memsize +ffffffff81e622d0 t nbio_v7_7_sdma_doorbell_range +ffffffff81e62360 t nbio_v7_7_vcn_doorbell_range +ffffffff81e623e0 t nbio_v7_7_enable_doorbell_aperture +ffffffff81e624c0 t nbio_v7_7_enable_doorbell_selfring_aperture +ffffffff81e62620 t nbio_v7_7_ih_doorbell_range +ffffffff81e62730 t nbio_v7_7_update_medium_grain_clock_gating +ffffffff81e62860 t nbio_v7_7_update_medium_grain_light_sleep +ffffffff81e62a60 t nbio_v7_7_get_clockgating_state +ffffffff81e62b70 t nbio_v7_7_ih_control +ffffffff81e62cc0 t nbio_v7_7_init_registers +ffffffff81e62dc0 t nbio_v7_7_remap_hdp_registers +ffffffff81e63000 T nv_grbm_select +ffffffff81e63090 T nv_set_virt_ops +ffffffff81e630c0 t nv_common_early_init +ffffffff81e634a0 t nv_common_late_init +ffffffff81e63500 t nv_common_sw_init +ffffffff81e63540 t nv_common_sw_fini +ffffffff81e63570 t nv_common_hw_init +ffffffff81e63680 t nv_common_hw_fini +ffffffff81e636e0 t nv_common_suspend +ffffffff81e63740 t nv_common_resume +ffffffff81e63780 t nv_common_is_idle +ffffffff81e637b0 t nv_common_wait_for_idle +ffffffff81e637e0 t nv_common_soft_reset +ffffffff81e63810 t nv_common_set_clockgating_state +ffffffff81e638e0 t nv_common_set_powergating_state +ffffffff81e63910 t nv_common_get_clockgating_state +ffffffff81e63980 t nv_pcie_rreg +ffffffff81e639e0 t nv_pcie_wreg +ffffffff81e63a40 t nv_pcie_rreg64 +ffffffff81e63aa0 t nv_pcie_wreg64 +ffffffff81e63b00 t nv_didt_rreg +ffffffff81e63b90 t nv_didt_wreg +ffffffff81e63c10 t nv_read_disabled_bios +ffffffff81e63c40 t nv_read_register +ffffffff81e63d20 t nv_vga_set_state +ffffffff81e63d50 t nv_asic_reset +ffffffff81e63e90 t nv_asic_reset_method +ffffffff81e63f80 t nv_get_xclk +ffffffff81e63fb0 t nv_set_uvd_clocks +ffffffff81e63fe0 t nv_set_vce_clocks +ffffffff81e64010 t nv_get_config_memsize +ffffffff81e64030 t nv_need_full_reset +ffffffff81e64060 t nv_init_doorbell_index +ffffffff81e64190 t nv_need_reset_on_init +ffffffff81e64220 t nv_get_pcie_replay_count +ffffffff81e64250 t nv_pre_asic_init +ffffffff81e64280 t nv_update_umd_stable_pstate +ffffffff81e64330 t nv_query_video_codecs +ffffffff81e65000 T psp_v10_0_set_psp_funcs +ffffffff81e65030 t psp_v10_0_init_microcode +ffffffff81e652a0 t psp_v10_0_ring_init +ffffffff81e65320 t psp_v10_0_ring_create +ffffffff81e65620 t psp_v10_0_ring_stop +ffffffff81e65810 t psp_v10_0_ring_destroy +ffffffff81e65880 t psp_v10_0_mode1_reset +ffffffff81e658c0 t psp_v10_0_ring_get_wptr +ffffffff81e65920 t psp_v10_0_ring_set_wptr +ffffffff81e66000 T psp_v11_0_set_psp_funcs +ffffffff81e66030 t psp_v11_0_init_microcode +ffffffff81e66450 t psp_v11_0_bootloader_load_kdb +ffffffff81e66470 t psp_v11_0_bootloader_load_spl +ffffffff81e66490 t psp_v11_0_bootloader_load_sysdrv +ffffffff81e664b0 t psp_v11_0_bootloader_load_sos +ffffffff81e66800 t psp_v11_0_ring_init +ffffffff81e66880 t psp_v11_0_ring_create +ffffffff81e66f10 t psp_v11_0_ring_stop +ffffffff81e67130 t psp_v11_0_ring_destroy +ffffffff81e671a0 t psp_v11_0_mode1_reset +ffffffff81e67290 t psp_v11_0_memory_training +ffffffff81e67710 t psp_v11_0_ring_get_wptr +ffffffff81e67760 t psp_v11_0_ring_set_wptr +ffffffff81e678a0 t psp_v11_0_load_usbc_pd_fw +ffffffff81e67a90 t psp_v11_0_read_usbc_pd_fw +ffffffff81e67bb0 t psp_v11_0_bootloader_load_component +ffffffff81e67d70 t psp_v11_0_wait_for_bootloader +ffffffff81e67f40 t psp_v11_0_memory_training_send_msg +ffffffff81e69000 T psp_v11_0_8_set_psp_funcs +ffffffff81e69030 t psp_v11_0_8_ring_init +ffffffff81e690b0 t psp_v11_0_8_ring_create +ffffffff81e69740 t psp_v11_0_8_ring_stop +ffffffff81e69ac0 t psp_v11_0_8_ring_destroy +ffffffff81e69b30 t psp_v11_0_8_ring_get_wptr +ffffffff81e69ba0 t psp_v11_0_8_ring_set_wptr +ffffffff81e6a000 T psp_v12_0_set_psp_funcs +ffffffff81e6a030 t psp_v12_0_init_microcode +ffffffff81e6a290 t psp_v12_0_bootloader_load_sysdrv +ffffffff81e6a5b0 t psp_v12_0_bootloader_load_sos +ffffffff81e6a910 t psp_v12_0_ring_init +ffffffff81e6aee0 t psp_v12_0_ring_create +ffffffff81e6b430 t psp_v12_0_ring_stop +ffffffff81e6b650 t psp_v12_0_ring_destroy +ffffffff81e6b6c0 t psp_v12_0_mode1_reset +ffffffff81e6b7b0 t psp_v12_0_ring_get_wptr +ffffffff81e6b820 t psp_v12_0_ring_set_wptr +ffffffff81e6c000 T psp_v13_0_set_psp_funcs +ffffffff81e6c030 t psp_v13_0_init_microcode +ffffffff81e6c160 t psp_v13_0_bootloader_load_kdb +ffffffff81e6c180 t psp_v13_0_bootloader_load_spl +ffffffff81e6c1a0 t psp_v13_0_bootloader_load_sysdrv +ffffffff81e6c1c0 t psp_v13_0_bootloader_load_soc_drv +ffffffff81e6c1e0 t psp_v13_0_bootloader_load_intf_drv +ffffffff81e6c200 t psp_v13_0_bootloader_load_dbg_drv +ffffffff81e6c220 t psp_v13_0_bootloader_load_ras_drv +ffffffff81e6c240 t psp_v13_0_bootloader_load_sos +ffffffff81e6c5a0 t psp_v13_0_ring_init +ffffffff81e6c620 t psp_v13_0_ring_create +ffffffff81e6ccb0 t psp_v13_0_ring_stop +ffffffff81e6d030 t psp_v13_0_ring_destroy +ffffffff81e6d0a0 t psp_v13_0_memory_training +ffffffff81e6d4e0 t psp_v13_0_ring_get_wptr +ffffffff81e6d550 t psp_v13_0_ring_set_wptr +ffffffff81e6d640 t psp_v13_0_load_usbc_pd_fw +ffffffff81e6d830 t psp_v13_0_read_usbc_pd_fw +ffffffff81e6d950 t psp_v13_0_update_spirom +ffffffff81e6db20 t psp_v13_0_vbflash_status +ffffffff81e6db80 t psp_v13_0_bootloader_load_component +ffffffff81e6dd50 t psp_v13_0_wait_for_bootloader +ffffffff81e6df20 t psp_v13_0_memory_training_send_msg +ffffffff81e6e080 t psp_v13_0_exec_spi_cmd +ffffffff81e6f000 T psp_v13_0_4_set_psp_funcs +ffffffff81e6f030 t psp_v13_0_4_init_microcode +ffffffff81e6f100 t psp_v13_0_4_bootloader_load_kdb +ffffffff81e6f120 t psp_v13_0_4_bootloader_load_spl +ffffffff81e6f140 t psp_v13_0_4_bootloader_load_sysdrv +ffffffff81e6f160 t psp_v13_0_4_bootloader_load_soc_drv +ffffffff81e6f180 t psp_v13_0_4_bootloader_load_intf_drv +ffffffff81e6f1a0 t psp_v13_0_4_bootloader_load_dbg_drv +ffffffff81e6f1c0 t psp_v13_0_4_bootloader_load_sos +ffffffff81e6f530 t psp_v13_0_4_ring_init +ffffffff81e6f5b0 t psp_v13_0_4_ring_create +ffffffff81e6fc50 t psp_v13_0_4_ring_stop +ffffffff81e6ffe0 t psp_v13_0_4_ring_destroy +ffffffff81e70050 t psp_v13_0_4_ring_get_wptr +ffffffff81e700c0 t psp_v13_0_4_ring_set_wptr +ffffffff81e701c0 t psp_v13_0_4_bootloader_load_component +ffffffff81e70390 t psp_v13_0_4_wait_for_bootloader +ffffffff81e71000 T psp_v3_1_set_psp_funcs +ffffffff81e71030 t psp_v3_1_init_microcode +ffffffff81e710e0 t psp_v3_1_bootloader_load_sysdrv +ffffffff81e71400 t psp_v3_1_bootloader_load_sos +ffffffff81e71760 t psp_v3_1_ring_init +ffffffff81e717e0 t psp_v3_1_ring_create +ffffffff81e722e0 t psp_v3_1_ring_stop +ffffffff81e72500 t psp_v3_1_ring_destroy +ffffffff81e72570 t psp_v3_1_smu_reload_quirk +ffffffff81e725c0 t psp_v3_1_mode1_reset +ffffffff81e726b0 t psp_v3_1_ring_get_wptr +ffffffff81e72700 t psp_v3_1_ring_set_wptr +ffffffff81e73000 t sdma_v2_4_early_init +ffffffff81e730e0 t sdma_v2_4_sw_init +ffffffff81e73470 t sdma_v2_4_sw_fini +ffffffff81e73550 t sdma_v2_4_hw_init +ffffffff81e73900 t sdma_v2_4_hw_fini +ffffffff81e73940 t sdma_v2_4_suspend +ffffffff81e73980 t sdma_v2_4_resume +ffffffff81e73990 t sdma_v2_4_is_idle +ffffffff81e739d0 t sdma_v2_4_wait_for_idle +ffffffff81e73a60 t sdma_v2_4_soft_reset +ffffffff81e73ba0 t sdma_v2_4_set_clockgating_state +ffffffff81e73bd0 t sdma_v2_4_set_powergating_state +ffffffff81e73c00 t sdma_v2_4_ring_get_rptr +ffffffff81e73c30 t sdma_v2_4_ring_get_wptr +ffffffff81e73c80 t sdma_v2_4_ring_set_wptr +ffffffff81e73cb0 t sdma_v2_4_ring_emit_ib +ffffffff81e73f60 t sdma_v2_4_ring_emit_fence +ffffffff81e74360 t sdma_v2_4_ring_emit_pipeline_sync +ffffffff81e745e0 t sdma_v2_4_ring_emit_vm_flush +ffffffff81e74860 t sdma_v2_4_ring_emit_hdp_flush +ffffffff81e74ae0 t sdma_v2_4_ring_test_ring +ffffffff81e74dc0 t sdma_v2_4_ring_test_ib +ffffffff81e74fa0 t sdma_v2_4_ring_insert_nop +ffffffff81e750c0 t sdma_v2_4_ring_pad_ib +ffffffff81e751e0 t sdma_v2_4_ring_emit_wreg +ffffffff81e75330 t sdma_v2_4_emit_copy_buffer +ffffffff81e753e0 t sdma_v2_4_emit_fill_buffer +ffffffff81e75470 t sdma_v2_4_vm_copy_pte +ffffffff81e75520 t sdma_v2_4_vm_write_pte +ffffffff81e755f0 t sdma_v2_4_vm_set_pte_pde +ffffffff81e756e0 t sdma_v2_4_set_trap_irq_state +ffffffff81e757a0 t sdma_v2_4_process_trap_irq +ffffffff81e75830 t sdma_v2_4_process_illegal_inst_irq +ffffffff81e758b0 t sdma_v2_4_enable +ffffffff81e76000 t sdma_v3_0_early_init +ffffffff81e76140 t sdma_v3_0_sw_init +ffffffff81e764f0 t sdma_v3_0_sw_fini +ffffffff81e765d0 t sdma_v3_0_hw_init +ffffffff81e76700 t sdma_v3_0_hw_fini +ffffffff81e76740 t sdma_v3_0_suspend +ffffffff81e76780 t sdma_v3_0_resume +ffffffff81e76790 t sdma_v3_0_is_idle +ffffffff81e767d0 t sdma_v3_0_wait_for_idle +ffffffff81e76860 t sdma_v3_0_check_soft_reset +ffffffff81e768b0 t sdma_v3_0_pre_soft_reset +ffffffff81e76900 t sdma_v3_0_soft_reset +ffffffff81e769c0 t sdma_v3_0_post_soft_reset +ffffffff81e76a00 t sdma_v3_0_set_clockgating_state +ffffffff81e76c60 t sdma_v3_0_set_powergating_state +ffffffff81e76c90 t sdma_v3_0_get_clockgating_state +ffffffff81e76d10 t sdma_v3_0_ring_get_rptr +ffffffff81e76d40 t sdma_v3_0_ring_get_wptr +ffffffff81e76dc0 t sdma_v3_0_ring_set_wptr +ffffffff81e76e70 t sdma_v3_0_ring_emit_ib +ffffffff81e77120 t sdma_v3_0_ring_emit_fence +ffffffff81e77520 t sdma_v3_0_ring_emit_pipeline_sync +ffffffff81e777a0 t sdma_v3_0_ring_emit_vm_flush +ffffffff81e77a20 t sdma_v3_0_ring_emit_hdp_flush +ffffffff81e77ca0 t sdma_v3_0_ring_test_ring +ffffffff81e77f80 t sdma_v3_0_ring_test_ib +ffffffff81e78160 t sdma_v3_0_ring_insert_nop +ffffffff81e78280 t sdma_v3_0_ring_pad_ib +ffffffff81e783a0 t sdma_v3_0_ring_emit_wreg +ffffffff81e784f0 t sdma_v3_0_emit_copy_buffer +ffffffff81e785a0 t sdma_v3_0_emit_fill_buffer +ffffffff81e78630 t sdma_v3_0_vm_copy_pte +ffffffff81e786e0 t sdma_v3_0_vm_write_pte +ffffffff81e787b0 t sdma_v3_0_vm_set_pte_pde +ffffffff81e788a0 t sdma_v3_0_set_trap_irq_state +ffffffff81e78960 t sdma_v3_0_process_trap_irq +ffffffff81e789f0 t sdma_v3_0_process_illegal_inst_irq +ffffffff81e78a70 t sdma_v3_0_ctx_switch_enable +ffffffff81e78c00 t sdma_v3_0_enable +ffffffff81e78d70 t sdma_v3_0_gfx_resume +ffffffff81e7a000 t sdma_v4_0_early_init +ffffffff81e7a580 t sdma_v4_0_late_init +ffffffff81e7a820 t sdma_v4_0_sw_init +ffffffff81e7ab90 t sdma_v4_0_sw_fini +ffffffff81e7ac50 t sdma_v4_0_hw_init +ffffffff81e7dbf0 t sdma_v4_0_hw_fini +ffffffff81e7dca0 t sdma_v4_0_suspend +ffffffff81e7dcf0 t sdma_v4_0_resume +ffffffff81e7dd60 t sdma_v4_0_is_idle +ffffffff81e7de90 t sdma_v4_0_wait_for_idle +ffffffff81e7e030 t sdma_v4_0_soft_reset +ffffffff81e7e060 t sdma_v4_0_set_clockgating_state +ffffffff81e7e550 t sdma_v4_0_set_powergating_state +ffffffff81e7e610 t sdma_v4_0_get_clockgating_state +ffffffff81e7e6a0 t sdma_v4_0_query_ras_error_count +ffffffff81e7e870 t sdma_v4_0_reset_ras_error_count +ffffffff81e7e9c0 t sdma_v4_0_ring_get_rptr +ffffffff81e7ea20 t sdma_v4_0_ring_get_wptr +ffffffff81e7ec10 t sdma_v4_0_ring_set_wptr +ffffffff81e7ee90 t sdma_v4_0_ring_emit_ib +ffffffff81e7f140 t sdma_v4_0_ring_emit_fence +ffffffff81e7f570 t sdma_v4_0_ring_emit_pipeline_sync +ffffffff81e7f5c0 t sdma_v4_0_ring_emit_vm_flush +ffffffff81e7f5e0 t sdma_v4_0_ring_emit_hdp_flush +ffffffff81e7f680 t sdma_v4_0_ring_test_ring +ffffffff81e7f960 t sdma_v4_0_ring_test_ib +ffffffff81e7fb40 t sdma_v4_0_ring_insert_nop +ffffffff81e7fc60 t sdma_v4_0_ring_pad_ib +ffffffff81e7fd80 t sdma_v4_0_ring_emit_wreg +ffffffff81e7fed0 t sdma_v4_0_ring_emit_reg_wait +ffffffff81e7ff20 t sdma_v4_0_wait_reg_mem +ffffffff81e80250 t sdma_v4_0_page_ring_get_wptr +ffffffff81e80400 t sdma_v4_0_page_ring_set_wptr +ffffffff81e805c0 t sdma_v4_0_emit_copy_buffer +ffffffff81e80680 t sdma_v4_0_emit_fill_buffer +ffffffff81e80710 t sdma_v4_0_vm_copy_pte +ffffffff81e807d0 t sdma_v4_0_vm_write_pte +ffffffff81e808a0 t sdma_v4_0_vm_set_pte_pde +ffffffff81e809a0 t sdma_v4_0_set_trap_irq_state +ffffffff81e80b40 t sdma_v4_0_process_trap_irq +ffffffff81e80c80 t sdma_v4_0_process_illegal_inst_irq +ffffffff81e80da0 t sdma_v4_0_set_ecc_irq_state +ffffffff81e80f40 t sdma_v4_0_process_vm_hole_irq +ffffffff81e81080 t sdma_v4_0_process_doorbell_invalid_irq +ffffffff81e811c0 t sdma_v4_0_process_pool_timeout_irq +ffffffff81e81300 t sdma_v4_0_process_srbm_write_irq +ffffffff81e81440 t sdma_v4_0_process_ras_data_cb +ffffffff81e814b0 t sdma_v4_0_ctx_switch_enable +ffffffff81e81b60 t sdma_v4_0_enable +ffffffff81e82100 t sdma_v4_0_gfx_enable +ffffffff81e83000 t sdma_v4_4_query_ras_error_count +ffffffff81e83270 t sdma_v4_4_reset_ras_error_count +ffffffff81e84000 t sdma_v5_0_early_init +ffffffff81e84170 t sdma_v5_0_sw_init +ffffffff81e84410 t sdma_v5_0_sw_fini +ffffffff81e84490 t sdma_v5_0_hw_init +ffffffff81e85740 t sdma_v5_0_hw_fini +ffffffff81e857a0 t sdma_v5_0_suspend +ffffffff81e85800 t sdma_v5_0_resume +ffffffff81e85810 t sdma_v5_0_is_idle +ffffffff81e858a0 t sdma_v5_0_wait_for_idle +ffffffff81e85960 t sdma_v5_0_soft_reset +ffffffff81e85990 t sdma_v5_0_set_clockgating_state +ffffffff81e85b90 t sdma_v5_0_set_powergating_state +ffffffff81e85bc0 t sdma_v5_0_get_clockgating_state +ffffffff81e85c50 t sdma_v5_0_ring_get_rptr +ffffffff81e85cb0 t sdma_v5_0_ring_get_wptr +ffffffff81e85e50 t sdma_v5_0_ring_set_wptr +ffffffff81e861b0 t sdma_v5_0_ring_emit_ib +ffffffff81e86470 t sdma_v5_0_ring_emit_fence +ffffffff81e868d0 t sdma_v5_0_ring_emit_pipeline_sync +ffffffff81e86b50 t sdma_v5_0_ring_emit_vm_flush +ffffffff81e86b70 t sdma_v5_0_ring_emit_hdp_flush +ffffffff81e86e10 t sdma_v5_0_ring_test_ring +ffffffff81e871e0 t sdma_v5_0_ring_test_ib +ffffffff81e87500 t sdma_v5_0_ring_insert_nop +ffffffff81e87620 t sdma_v5_0_ring_pad_ib +ffffffff81e87740 t sdma_v5_0_ring_init_cond_exec +ffffffff81e87970 t sdma_v5_0_ring_patch_cond_exec +ffffffff81e87a30 t sdma_v5_0_ring_emit_wreg +ffffffff81e87b80 t sdma_v5_0_ring_emit_reg_wait +ffffffff81e87e00 t sdma_v5_0_ring_emit_reg_write_reg_wait +ffffffff81e87e70 t sdma_v5_0_ring_preempt_ib +ffffffff81e87fb0 t sdma_v5_0_ring_emit_mem_sync +ffffffff81e881c0 t sdma_v5_0_emit_copy_buffer +ffffffff81e88280 t sdma_v5_0_emit_fill_buffer +ffffffff81e88310 t sdma_v5_0_vm_copy_pte +ffffffff81e883d0 t sdma_v5_0_vm_write_pte +ffffffff81e884a0 t sdma_v5_0_vm_set_pte_pde +ffffffff81e885a0 t sdma_v5_0_set_trap_irq_state +ffffffff81e88630 t sdma_v5_0_process_trap_irq +ffffffff81e88740 t sdma_v5_0_process_illegal_inst_irq +ffffffff81e88770 t sdma_v5_0_mqd_init +ffffffff81e88850 t sdma_v5_0_ctx_switch_enable +ffffffff81e88b50 t sdma_v5_0_enable +ffffffff81e89000 t sdma_v5_2_early_init +ffffffff81e89170 t sdma_v5_2_sw_init +ffffffff81e893a0 t sdma_v5_2_sw_fini +ffffffff81e89420 t sdma_v5_2_hw_init +ffffffff81e89750 t sdma_v5_2_hw_fini +ffffffff81e897b0 t sdma_v5_2_suspend +ffffffff81e89810 t sdma_v5_2_resume +ffffffff81e89820 t sdma_v5_2_is_idle +ffffffff81e898d0 t sdma_v5_2_wait_for_idle +ffffffff81e899d0 t sdma_v5_2_soft_reset +ffffffff81e89c70 t sdma_v5_2_set_clockgating_state +ffffffff81e89f80 t sdma_v5_2_set_powergating_state +ffffffff81e89fb0 t sdma_v5_2_get_clockgating_state +ffffffff81e8a040 t sdma_v5_2_ring_get_rptr +ffffffff81e8a0a0 t sdma_v5_2_ring_get_wptr +ffffffff81e8a1e0 t sdma_v5_2_ring_set_wptr +ffffffff81e8a3a0 t sdma_v5_2_ring_emit_ib +ffffffff81e8a660 t sdma_v5_2_ring_emit_fence +ffffffff81e8aac0 t sdma_v5_2_ring_emit_pipeline_sync +ffffffff81e8ad40 t sdma_v5_2_ring_emit_vm_flush +ffffffff81e8ad60 t sdma_v5_2_ring_emit_hdp_flush +ffffffff81e8b000 t sdma_v5_2_ring_test_ring +ffffffff81e8b3d0 t sdma_v5_2_ring_test_ib +ffffffff81e8b6f0 t sdma_v5_2_ring_insert_nop +ffffffff81e8b810 t sdma_v5_2_ring_pad_ib +ffffffff81e8b930 t sdma_v5_2_ring_init_cond_exec +ffffffff81e8bb60 t sdma_v5_2_ring_patch_cond_exec +ffffffff81e8bc20 t sdma_v5_2_ring_emit_wreg +ffffffff81e8bd70 t sdma_v5_2_ring_emit_reg_wait +ffffffff81e8bff0 t sdma_v5_2_ring_emit_reg_write_reg_wait +ffffffff81e8c060 t sdma_v5_2_ring_preempt_ib +ffffffff81e8c1d0 t sdma_v5_2_ring_emit_mem_sync +ffffffff81e8c3e0 t sdma_v5_2_emit_copy_buffer +ffffffff81e8c4a0 t sdma_v5_2_emit_fill_buffer +ffffffff81e8c530 t sdma_v5_2_vm_copy_pte +ffffffff81e8c5f0 t sdma_v5_2_vm_write_pte +ffffffff81e8c6c0 t sdma_v5_2_vm_set_pte_pde +ffffffff81e8c7c0 t sdma_v5_2_set_trap_irq_state +ffffffff81e8c880 t sdma_v5_2_process_trap_irq +ffffffff81e8c9c0 t sdma_v5_2_process_illegal_inst_irq +ffffffff81e8c9f0 t sdma_v5_2_mqd_init +ffffffff81e8cad0 t sdma_v5_2_ctx_switch_enable +ffffffff81e8ced0 t sdma_v5_2_enable +ffffffff81e8d2e0 t sdma_v5_2_gfx_resume +ffffffff81e8f000 t sdma_v6_0_early_init +ffffffff81e8f140 t sdma_v6_0_sw_init +ffffffff81e8f320 t sdma_v6_0_sw_fini +ffffffff81e8f3a0 t sdma_v6_0_hw_init +ffffffff81e8f3b0 t sdma_v6_0_hw_fini +ffffffff81e8f400 t sdma_v6_0_suspend +ffffffff81e8f450 t sdma_v6_0_resume +ffffffff81e8f460 t sdma_v6_0_is_idle +ffffffff81e8f4f0 t sdma_v6_0_wait_for_idle +ffffffff81e8f5b0 t sdma_v6_0_check_soft_reset +ffffffff81e8f670 t sdma_v6_0_soft_reset +ffffffff81e8fb10 t sdma_v6_0_set_clockgating_state +ffffffff81e8fb40 t sdma_v6_0_set_powergating_state +ffffffff81e8fb70 t sdma_v6_0_get_clockgating_state +ffffffff81e8fba0 t sdma_v6_0_ring_get_rptr +ffffffff81e8fc00 t sdma_v6_0_ring_get_wptr +ffffffff81e8fc70 t sdma_v6_0_ring_set_wptr +ffffffff81e8ffd0 t sdma_v6_0_ring_emit_ib +ffffffff81e90290 t sdma_v6_0_ring_emit_fence +ffffffff81e906f0 t sdma_v6_0_ring_emit_pipeline_sync +ffffffff81e90970 t sdma_v6_0_ring_emit_vm_flush +ffffffff81e90990 t sdma_v6_0_ring_emit_hdp_flush +ffffffff81e90c30 t sdma_v6_0_ring_test_ring +ffffffff81e91000 t sdma_v6_0_ring_test_ib +ffffffff81e91320 t sdma_v6_0_ring_insert_nop +ffffffff81e91440 t sdma_v6_0_ring_pad_ib +ffffffff81e91560 t sdma_v6_0_ring_init_cond_exec +ffffffff81e91790 t sdma_v6_0_ring_patch_cond_exec +ffffffff81e91850 t sdma_v6_0_ring_emit_wreg +ffffffff81e919a0 t sdma_v6_0_ring_emit_reg_wait +ffffffff81e91c20 t sdma_v6_0_ring_emit_reg_write_reg_wait +ffffffff81e91c90 t sdma_v6_0_ring_preempt_ib +ffffffff81e91de0 t sdma_v6_0_ring_emit_mem_sync +ffffffff81e91ff0 t sdma_v6_0_emit_copy_buffer +ffffffff81e920b0 t sdma_v6_0_emit_fill_buffer +ffffffff81e92140 t sdma_v6_0_vm_copy_pte +ffffffff81e92200 t sdma_v6_0_vm_write_pte +ffffffff81e922d0 t sdma_v6_0_vm_set_pte_pde +ffffffff81e923d0 t sdma_v6_0_set_trap_irq_state +ffffffff81e92460 t sdma_v6_0_process_trap_irq +ffffffff81e92590 t sdma_v6_0_process_illegal_inst_irq +ffffffff81e925c0 t sdma_v6_0_mqd_init +ffffffff81e926d0 t sdma_v6_0_start +ffffffff81e92950 t sdma_v6_0_enable +ffffffff81e92ad0 t sdma_v6_0_gfx_resume +ffffffff81e93b50 t sdma_v6_0_gfx_stop +ffffffff81e94000 T sienna_cichlid_reset_init +ffffffff81e940c0 t sienna_cichlid_async_reset +ffffffff81e94120 t sienna_cichlid_get_reset_handler +ffffffff81e94180 T sienna_cichlid_reset_fini +ffffffff81e941d0 t sienna_cichlid_mode2_prepare_hwcontext +ffffffff81e94320 t sienna_cichlid_mode2_perform_reset +ffffffff81e943a0 t sienna_cichlid_mode2_restore_hwcontext +ffffffff81e946a0 t sienna_cichlid_mode2_reset +ffffffff81e95000 T smu_v11_0_i2c_control_init +ffffffff81e950c0 T smu_v11_0_i2c_control_fini +ffffffff81e95100 t smu_v11_0_i2c_xfer +ffffffff81e961e0 t smu_v11_0_i2c_func +ffffffff81e96210 t smu_v11_0_i2c_enable +ffffffff81e96350 t smu_v11_0_i2c_abort +ffffffff81e96450 t lock_bus +ffffffff81e964e0 t trylock_bus +ffffffff81e96530 t unlock_bus +ffffffff81e97000 t smuio_v11_0_get_rom_index_offset +ffffffff81e97030 t smuio_v11_0_get_rom_data_offset +ffffffff81e97060 t smuio_v11_0_update_rom_clock_gating +ffffffff81e971a0 t smuio_v11_0_get_clock_gating_state +ffffffff81e98000 t smuio_v11_0_6_get_rom_index_offset +ffffffff81e98030 t smuio_v11_0_6_get_rom_data_offset +ffffffff81e98060 t smuio_v11_0_6_update_rom_clock_gating +ffffffff81e981a0 t smuio_v11_0_6_get_clock_gating_state +ffffffff81e99000 t smuio_v13_0_get_rom_index_offset +ffffffff81e99030 t smuio_v13_0_get_rom_data_offset +ffffffff81e99060 t smuio_v13_0_update_rom_clock_gating +ffffffff81e991a0 t smuio_v13_0_get_clock_gating_state +ffffffff81e99230 t smuio_v13_0_get_die_id +ffffffff81e992b0 t smuio_v13_0_get_socket_id +ffffffff81e99330 t smuio_v13_0_is_host_gpu_xgmi_supported +ffffffff81e9a000 t smuio_v13_0_6_get_rom_index_offset +ffffffff81e9a030 t smuio_v13_0_6_get_rom_data_offset +ffffffff81e9b000 t smuio_v9_0_get_rom_index_offset +ffffffff81e9b030 t smuio_v9_0_get_rom_data_offset +ffffffff81e9b060 t smuio_v9_0_update_rom_clock_gating +ffffffff81e9b1a0 t smuio_v9_0_get_clock_gating_state +ffffffff81e9c000 T soc15_grbm_select +ffffffff81e9c080 T soc15_program_register_sequence +ffffffff81e9c280 T soc15_set_virt_ops +ffffffff81e9c2f0 t soc15_common_early_init +ffffffff81e9c680 t soc15_common_late_init +ffffffff81e9c6c0 t soc15_common_sw_init +ffffffff81e9c720 t soc15_common_sw_fini +ffffffff81e9c770 t soc15_common_hw_init +ffffffff81e9c8a0 t soc15_common_hw_fini +ffffffff81e9c970 t soc15_common_suspend +ffffffff81e9c9b0 t soc15_common_resume +ffffffff81e9c9f0 t soc15_common_is_idle +ffffffff81e9ca20 t soc15_common_wait_for_idle +ffffffff81e9ca50 t soc15_common_soft_reset +ffffffff81e9ca80 t soc15_common_set_clockgating_state +ffffffff81e9cdc0 t soc15_common_set_powergating_state +ffffffff81e9cdf0 t soc15_common_get_clockgating_state +ffffffff81e9ced0 t soc15_pcie_rreg +ffffffff81e9cf30 t soc15_pcie_wreg +ffffffff81e9cf90 t soc15_pcie_rreg64 +ffffffff81e9cff0 t soc15_pcie_wreg64 +ffffffff81e9d050 t soc15_uvd_ctx_rreg +ffffffff81e9d0f0 t soc15_uvd_ctx_wreg +ffffffff81e9d170 t soc15_didt_rreg +ffffffff81e9d200 t soc15_didt_wreg +ffffffff81e9d280 t soc15_gc_cac_rreg +ffffffff81e9d390 t soc15_gc_cac_wreg +ffffffff81e9d4a0 t soc15_se_cac_rreg +ffffffff81e9d5b0 t soc15_se_cac_wreg +ffffffff81e9d6c0 t soc15_read_disabled_bios +ffffffff81e9d6f0 t soc15_read_register +ffffffff81e9d7f0 t soc15_vga_set_state +ffffffff81e9d820 t soc15_asic_reset +ffffffff81e9d920 t soc15_asic_reset_method +ffffffff81e9daa0 t soc15_get_xclk +ffffffff81e9daf0 t soc15_set_uvd_clocks +ffffffff81e9db20 t soc15_set_vce_clocks +ffffffff81e9db50 t soc15_get_config_memsize +ffffffff81e9db70 t soc15_need_full_reset +ffffffff81e9dba0 t soc15_get_pcie_usage +ffffffff81e9dcd0 t soc15_need_reset_on_init +ffffffff81e9dd70 t soc15_get_pcie_replay_count +ffffffff81e9dde0 t soc15_supports_baco +ffffffff81e9de40 t soc15_pre_asic_init +ffffffff81e9de50 t soc15_query_video_codecs +ffffffff81e9def0 t vega20_get_pcie_usage +ffffffff81e9f000 T soc21_grbm_select +ffffffff81e9f080 t soc21_common_early_init +ffffffff81e9f2a0 t soc21_common_late_init +ffffffff81e9f2d0 t soc21_common_sw_init +ffffffff81e9f300 t soc21_common_sw_fini +ffffffff81e9f330 t soc21_common_hw_init +ffffffff81e9f3f0 t soc21_common_hw_fini +ffffffff81e9f450 t soc21_common_suspend +ffffffff81e9f4b0 t soc21_common_resume +ffffffff81e9f570 t soc21_common_is_idle +ffffffff81e9f5a0 t soc21_common_wait_for_idle +ffffffff81e9f5d0 t soc21_common_soft_reset +ffffffff81e9f600 t soc21_common_set_clockgating_state +ffffffff81e9f6b0 t soc21_common_set_powergating_state +ffffffff81e9f710 t soc21_common_get_clockgating_state +ffffffff81e9f750 t soc21_pcie_rreg +ffffffff81e9f7b0 t soc21_pcie_wreg +ffffffff81e9f810 t soc21_pcie_rreg64 +ffffffff81e9f870 t soc21_pcie_wreg64 +ffffffff81e9f8d0 t soc21_didt_rreg +ffffffff81e9f960 t soc21_didt_wreg +ffffffff81e9f9e0 t soc21_read_disabled_bios +ffffffff81e9fa10 t soc21_read_register +ffffffff81e9fb00 t soc21_vga_set_state +ffffffff81e9fb30 t soc21_asic_reset +ffffffff81e9fc00 t soc21_asic_reset_method +ffffffff81e9fcc0 t soc21_get_xclk +ffffffff81e9fcf0 t soc21_set_uvd_clocks +ffffffff81e9fd20 t soc21_set_vce_clocks +ffffffff81e9fd50 t soc21_get_config_memsize +ffffffff81e9fd70 t soc21_need_full_reset +ffffffff81e9fdd0 t soc21_init_doorbell_index +ffffffff81e9fef0 t soc21_need_reset_on_init +ffffffff81e9ff80 t soc21_get_pcie_replay_count +ffffffff81e9ffb0 t soc21_pre_asic_init +ffffffff81e9ffe0 t soc21_update_umd_stable_pstate +ffffffff81ea0050 t soc21_query_video_codecs +ffffffff81ea1000 t tonga_ih_early_init +ffffffff81ea1050 t tonga_ih_sw_init +ffffffff81ea10d0 t tonga_ih_sw_fini +ffffffff81ea1110 t tonga_ih_hw_init +ffffffff81ea12f0 t tonga_ih_hw_fini +ffffffff81ea1390 t tonga_ih_suspend +ffffffff81ea1430 t tonga_ih_resume +ffffffff81ea1470 t tonga_ih_is_idle +ffffffff81ea14b0 t tonga_ih_wait_for_idle +ffffffff81ea1540 t tonga_ih_check_soft_reset +ffffffff81ea1590 t tonga_ih_pre_soft_reset +ffffffff81ea1630 t tonga_ih_soft_reset +ffffffff81ea16f0 t tonga_ih_post_soft_reset +ffffffff81ea1730 t tonga_ih_set_clockgating_state +ffffffff81ea1760 t tonga_ih_set_powergating_state +ffffffff81ea1790 t tonga_ih_get_wptr +ffffffff81ea1880 t tonga_ih_decode_iv +ffffffff81ea18f0 t tonga_ih_set_rptr +ffffffff81ea2000 t umc_v6_0_init_registers +ffffffff81ea3000 t umc_v6_1_query_ras_error_count +ffffffff81ea34e0 t umc_v6_1_query_ras_error_address +ffffffff81ea37c0 t umc_v6_1_err_cnt_init +ffffffff81ea4000 t umc_v6_7_query_ras_error_count +ffffffff81ea4410 t umc_v6_7_query_ras_error_address +ffffffff81ea4580 t umc_v6_7_query_ras_poison_mode +ffffffff81ea45d0 t umc_v6_7_convert_error_address +ffffffff81ea48d0 t umc_v6_7_ecc_info_query_ras_error_count +ffffffff81ea4b00 t umc_v6_7_ecc_info_query_ras_error_address +ffffffff81ea5000 t umc_v8_10_query_ras_error_count +ffffffff81ea5280 t umc_v8_10_query_ras_error_address +ffffffff81ea55b0 t umc_v8_10_err_cnt_init +ffffffff81ea5730 t umc_v8_10_query_ras_poison_mode +ffffffff81ea6000 t umc_v8_7_query_ras_error_count +ffffffff81ea6300 t umc_v8_7_query_ras_error_address +ffffffff81ea64b0 t umc_v8_7_err_cnt_init +ffffffff81ea6600 t umc_v8_7_ecc_info_query_ras_error_count +ffffffff81ea6730 t umc_v8_7_ecc_info_query_ras_error_address +ffffffff81ea7000 t uvd_v5_0_early_init +ffffffff81ea7050 t uvd_v5_0_sw_init +ffffffff81ea7130 t uvd_v5_0_sw_fini +ffffffff81ea7180 t uvd_v5_0_hw_init +ffffffff81ea7690 t uvd_v5_0_hw_fini +ffffffff81ea7710 t uvd_v5_0_suspend +ffffffff81ea7800 t uvd_v5_0_resume +ffffffff81ea7850 t uvd_v5_0_is_idle +ffffffff81ea7890 t uvd_v5_0_wait_for_idle +ffffffff81ea7910 t uvd_v5_0_soft_reset +ffffffff81ea79b0 t uvd_v5_0_set_clockgating_state +ffffffff81ea7b50 t uvd_v5_0_set_powergating_state +ffffffff81ea7b90 t uvd_v5_0_get_clockgating_state +ffffffff81ea7c10 t uvd_v5_0_ring_get_rptr +ffffffff81ea7c50 t uvd_v5_0_ring_get_wptr +ffffffff81ea7c90 t uvd_v5_0_ring_set_wptr +ffffffff81ea7cb0 t uvd_v5_0_ring_emit_ib +ffffffff81ea7f20 t uvd_v5_0_ring_emit_fence +ffffffff81ea84d0 t uvd_v5_0_ring_test_ring +ffffffff81ea8670 t uvd_v5_0_ring_insert_nop +ffffffff81ea87d0 t uvd_v5_0_set_interrupt_state +ffffffff81ea8800 t uvd_v5_0_process_interrupt +ffffffff81ea8860 t uvd_v5_0_stop +ffffffff81ea8970 t uvd_v5_0_start +ffffffff81eaa000 t uvd_v6_0_early_init +ffffffff81eaa140 t uvd_v6_0_sw_init +ffffffff81eaa450 t uvd_v6_0_sw_fini +ffffffff81eaa500 t uvd_v6_0_hw_init +ffffffff81eaaac0 t uvd_v6_0_hw_fini +ffffffff81eaab40 t uvd_v6_0_suspend +ffffffff81eaac30 t uvd_v6_0_resume +ffffffff81eaac80 t uvd_v6_0_is_idle +ffffffff81eaacc0 t uvd_v6_0_wait_for_idle +ffffffff81eaad40 t uvd_v6_0_check_soft_reset +ffffffff81eaadb0 t uvd_v6_0_pre_soft_reset +ffffffff81eaadf0 t uvd_v6_0_soft_reset +ffffffff81eaaeb0 t uvd_v6_0_post_soft_reset +ffffffff81eaaf50 t uvd_v6_0_set_clockgating_state +ffffffff81eab0e0 t uvd_v6_0_set_powergating_state +ffffffff81eab150 t uvd_v6_0_get_clockgating_state +ffffffff81eab1e0 t uvd_v6_0_ring_get_rptr +ffffffff81eab220 t uvd_v6_0_ring_get_wptr +ffffffff81eab260 t uvd_v6_0_ring_set_wptr +ffffffff81eab280 t uvd_v6_0_ring_emit_ib +ffffffff81eab5e0 t uvd_v6_0_ring_emit_fence +ffffffff81eabb90 t uvd_v6_0_ring_emit_pipeline_sync +ffffffff81eabf80 t uvd_v6_0_ring_emit_vm_flush +ffffffff81eac2e0 t uvd_v6_0_ring_emit_hdp_flush +ffffffff81eac310 t uvd_v6_0_ring_test_ring +ffffffff81eac4b0 t uvd_v6_0_ring_insert_nop +ffffffff81eac610 t uvd_v6_0_ring_emit_wreg +ffffffff81eac890 t uvd_v6_0_enc_ring_get_rptr +ffffffff81eac8f0 t uvd_v6_0_enc_ring_get_wptr +ffffffff81eac950 t uvd_v6_0_enc_ring_set_wptr +ffffffff81eac990 t uvd_v6_0_enc_ring_emit_ib +ffffffff81eacbd0 t uvd_v6_0_enc_ring_emit_fence +ffffffff81eace10 t uvd_v6_0_enc_ring_emit_pipeline_sync +ffffffff81eacfc0 t uvd_v6_0_enc_ring_emit_vm_flush +ffffffff81ead1d0 t uvd_v6_0_enc_ring_test_ring +ffffffff81ead320 t uvd_v6_0_enc_ring_test_ib +ffffffff81ead8d0 t uvd_v6_0_enc_ring_insert_end +ffffffff81ead960 t uvd_v6_0_set_interrupt_state +ffffffff81ead990 t uvd_v6_0_process_interrupt +ffffffff81eada80 t uvd_v6_0_stop +ffffffff81eadb90 t uvd_v6_0_start +ffffffff81eaf000 t uvd_v7_0_early_init +ffffffff81eaf270 t uvd_v7_0_sw_init +ffffffff81eaf5e0 t uvd_v7_0_sw_fini +ffffffff81eaf6e0 t uvd_v7_0_hw_init +ffffffff81eb2600 t uvd_v7_0_hw_fini +ffffffff81eb2900 t uvd_v7_0_suspend +ffffffff81eb29b0 t uvd_v7_0_resume +ffffffff81eb2a00 t uvd_v7_0_set_clockgating_state +ffffffff81eb2a30 t uvd_v7_0_ring_get_rptr +ffffffff81eb2ac0 t uvd_v7_0_ring_get_wptr +ffffffff81eb2b50 t uvd_v7_0_ring_set_wptr +ffffffff81eb2bd0 t uvd_v7_0_ring_patch_cs_in_place +ffffffff81eb2c50 t uvd_v7_0_ring_emit_ib +ffffffff81eb2ff0 t uvd_v7_0_ring_emit_fence +ffffffff81eb3640 t uvd_v7_0_ring_emit_vm_flush +ffffffff81eb36b0 t uvd_v7_0_ring_emit_hdp_flush +ffffffff81eb36e0 t uvd_v7_0_ring_test_ring +ffffffff81eb3960 t uvd_v7_0_ring_insert_nop +ffffffff81eb3af0 t uvd_v7_0_ring_emit_wreg +ffffffff81eb3dc0 t uvd_v7_0_ring_emit_reg_wait +ffffffff81eb4160 t uvd_v7_0_enc_ring_get_rptr +ffffffff81eb4250 t uvd_v7_0_enc_ring_get_wptr +ffffffff81eb4350 t uvd_v7_0_enc_ring_set_wptr +ffffffff81eb4450 t uvd_v7_0_enc_ring_emit_ib +ffffffff81eb4690 t uvd_v7_0_enc_ring_emit_fence +ffffffff81eb48d0 t uvd_v7_0_enc_ring_emit_vm_flush +ffffffff81eb4940 t uvd_v7_0_enc_ring_test_ring +ffffffff81eb4aa0 t uvd_v7_0_enc_ring_test_ib +ffffffff81eb5050 t uvd_v7_0_enc_ring_insert_end +ffffffff81eb50e0 t uvd_v7_0_enc_ring_emit_wreg +ffffffff81eb5230 t uvd_v7_0_enc_ring_emit_reg_wait +ffffffff81eb53f0 t uvd_v7_0_set_interrupt_state +ffffffff81eb5420 t uvd_v7_0_process_interrupt +ffffffff81eb6000 t vce_v3_0_early_init +ffffffff81eb6180 t vce_v3_0_sw_init +ffffffff81eb62d0 t vce_v3_0_sw_fini +ffffffff81eb6320 t vce_v3_0_hw_init +ffffffff81eb6400 t vce_v3_0_hw_fini +ffffffff81eb64e0 t vce_v3_0_suspend +ffffffff81eb65b0 t vce_v3_0_resume +ffffffff81eb6600 t vce_v3_0_is_idle +ffffffff81eb6660 t vce_v3_0_wait_for_idle +ffffffff81eb6710 t vce_v3_0_check_soft_reset +ffffffff81eb6800 t vce_v3_0_pre_soft_reset +ffffffff81eb68a0 t vce_v3_0_soft_reset +ffffffff81eb6960 t vce_v3_0_post_soft_reset +ffffffff81eb6ac0 t vce_v3_0_set_clockgating_state +ffffffff81eb6da0 t vce_v3_0_set_powergating_state +ffffffff81eb75e0 t vce_v3_0_get_clockgating_state +ffffffff81eb76a0 t vce_v3_0_ring_get_rptr +ffffffff81eb7770 t vce_v3_0_ring_get_wptr +ffffffff81eb7840 t vce_v3_0_ring_set_wptr +ffffffff81eb78f0 t vce_v3_0_ring_emit_ib +ffffffff81eb7b30 t vce_v3_0_emit_pipeline_sync +ffffffff81eb7ce0 t vce_v3_0_emit_vm_flush +ffffffff81eb7f50 t vce_v3_0_set_interrupt_state +ffffffff81eb7fc0 t vce_v3_0_process_interrupt +ffffffff81eb8080 t vce_v3_0_stop +ffffffff81eb9000 t vce_v4_0_early_init +ffffffff81eb90b0 t vce_v4_0_sw_init +ffffffff81eb92e0 t vce_v4_0_sw_fini +ffffffff81eb9360 t vce_v4_0_hw_init +ffffffff81eb9b30 t vce_v4_0_hw_fini +ffffffff81eb9bd0 t vce_v4_0_suspend +ffffffff81eb9df0 t vce_v4_0_resume +ffffffff81eb9e90 t vce_v4_0_set_clockgating_state +ffffffff81eb9ec0 t vce_v4_0_set_powergating_state +ffffffff81eb9fa0 t vce_v4_0_ring_get_rptr +ffffffff81eba000 t vce_v4_0_ring_get_wptr +ffffffff81eba090 t vce_v4_0_ring_set_wptr +ffffffff81eba110 t vce_v4_0_ring_emit_ib +ffffffff81eba350 t vce_v4_0_ring_emit_fence +ffffffff81eba590 t vce_v4_0_emit_vm_flush +ffffffff81eba600 t vce_v4_0_ring_insert_end +ffffffff81eba690 t vce_v4_0_emit_wreg +ffffffff81eba7e0 t vce_v4_0_emit_reg_wait +ffffffff81eba9a0 t vce_v4_0_set_interrupt_state +ffffffff81ebaa30 t vce_v4_0_process_interrupt +ffffffff81ebaac0 t vce_v4_0_start +ffffffff81ebb4a0 t vce_v4_0_stop +ffffffff81ebc000 T vcn_dec_sw_ring_emit_fence +ffffffff81ebc240 T vcn_dec_sw_ring_insert_end +ffffffff81ebc2d0 T vcn_dec_sw_ring_emit_ib +ffffffff81ebc510 T vcn_dec_sw_ring_emit_reg_wait +ffffffff81ebc6d0 T vcn_dec_sw_ring_emit_vm_flush +ffffffff81ebc740 T vcn_dec_sw_ring_emit_wreg +ffffffff81ebd000 T vcn_v1_0_set_pg_for_begin_use +ffffffff81ebd150 T vcn_v1_0_ring_end_use +ffffffff81ebd1c0 t vcn_v1_0_early_init +ffffffff81ebd330 t vcn_v1_0_sw_init +ffffffff81ebd5c0 t vcn_v1_0_sw_fini +ffffffff81ebd620 t vcn_v1_0_hw_init +ffffffff81ebd700 t vcn_v1_0_hw_fini +ffffffff81ebd800 t vcn_v1_0_suspend +ffffffff81ebd870 t vcn_v1_0_resume +ffffffff81ebd960 t vcn_v1_0_is_idle +ffffffff81ebd9e0 t vcn_v1_0_wait_for_idle +ffffffff81ebdad0 t vcn_v1_0_set_clockgating_state +ffffffff81ebdb80 t vcn_v1_0_set_powergating_state +ffffffff81ebe510 t vcn_v1_0_dec_ring_get_rptr +ffffffff81ebe590 t vcn_v1_0_dec_ring_get_wptr +ffffffff81ebe610 t vcn_v1_0_dec_ring_set_wptr +ffffffff81ebe720 t vcn_v1_0_ring_patch_cs_in_place +ffffffff81ebe8e0 t vcn_v1_0_dec_ring_emit_ib +ffffffff81ebec70 t vcn_v1_0_dec_ring_emit_fence +ffffffff81ebf290 t vcn_v1_0_dec_ring_emit_vm_flush +ffffffff81ebf300 t vcn_v1_0_dec_ring_insert_nop +ffffffff81ebf480 t vcn_v1_0_dec_ring_insert_start +ffffffff81ebf650 t vcn_v1_0_dec_ring_insert_end +ffffffff81ebf760 t vcn_v1_0_ring_begin_use +ffffffff81ebf800 t vcn_v1_0_dec_ring_emit_wreg +ffffffff81ebfab0 t vcn_v1_0_dec_ring_emit_reg_wait +ffffffff81ebfe30 t vcn_v1_0_enc_ring_get_rptr +ffffffff81ebff00 t vcn_v1_0_enc_ring_get_wptr +ffffffff81ebffd0 t vcn_v1_0_enc_ring_set_wptr +ffffffff81ec0080 t vcn_v1_0_enc_ring_emit_ib +ffffffff81ec02c0 t vcn_v1_0_enc_ring_emit_fence +ffffffff81ec0500 t vcn_v1_0_enc_ring_emit_vm_flush +ffffffff81ec0570 t vcn_v1_0_enc_ring_insert_end +ffffffff81ec0600 t vcn_v1_0_enc_ring_emit_wreg +ffffffff81ec0750 t vcn_v1_0_enc_ring_emit_reg_wait +ffffffff81ec0910 t vcn_v1_0_set_interrupt_state +ffffffff81ec0940 t vcn_v1_0_process_interrupt +ffffffff81ec09e0 t vcn_v1_0_idle_work_handler +ffffffff81ec0b60 t vcn_v1_0_pause_dpg_mode +ffffffff81ec1c80 t vcn_v1_0_enable_clock_gating +ffffffff81ec2090 t vcn_v1_0_disable_clock_gating +ffffffff81ec2620 t vcn_1_0_enable_static_power_gating +ffffffff81ec2840 t vcn_v1_0_start_dpg_mode +ffffffff81ec6470 t vcn_v1_0_start_spg_mode +ffffffff81ec8690 t vcn_v1_0_clock_gating_dpg_mode +ffffffff81ec9000 T vcn_v2_0_dec_ring_insert_start +ffffffff81ec91c0 T vcn_v2_0_dec_ring_insert_end +ffffffff81ec92c0 T vcn_v2_0_dec_ring_insert_nop +ffffffff81ec9430 T vcn_v2_0_dec_ring_emit_fence +ffffffff81ec99f0 T vcn_v2_0_dec_ring_emit_ib +ffffffff81ec9d50 T vcn_v2_0_dec_ring_emit_reg_wait +ffffffff81eca0a0 T vcn_v2_0_dec_ring_emit_vm_flush +ffffffff81eca110 T vcn_v2_0_dec_ring_emit_wreg +ffffffff81eca3a0 T vcn_v2_0_enc_ring_emit_fence +ffffffff81eca5e0 T vcn_v2_0_enc_ring_insert_end +ffffffff81eca670 T vcn_v2_0_enc_ring_emit_ib +ffffffff81eca8b0 T vcn_v2_0_enc_ring_emit_reg_wait +ffffffff81ecaa70 T vcn_v2_0_enc_ring_emit_vm_flush +ffffffff81ecaae0 T vcn_v2_0_enc_ring_emit_wreg +ffffffff81ecac30 T vcn_v2_0_dec_ring_test_ring +ffffffff81ecaec0 t vcn_v2_0_early_init +ffffffff81ecb030 t vcn_v2_0_sw_init +ffffffff81ecb340 t vcn_v2_0_sw_fini +ffffffff81ecb3c0 t vcn_v2_0_hw_init +ffffffff81ecbd70 t vcn_v2_0_hw_fini +ffffffff81ecbe70 t vcn_v2_0_suspend +ffffffff81ecbe90 t vcn_v2_0_resume +ffffffff81ecbee0 t vcn_v2_0_is_idle +ffffffff81ecbf60 t vcn_v2_0_wait_for_idle +ffffffff81ecc050 t vcn_v2_0_set_clockgating_state +ffffffff81ecc0e0 t vcn_v2_0_set_powergating_state +ffffffff81ece3a0 t vcn_v2_0_dec_ring_get_rptr +ffffffff81ece420 t vcn_v2_0_dec_ring_get_wptr +ffffffff81ece4c0 t vcn_v2_0_dec_ring_set_wptr +ffffffff81ece5f0 t vcn_v2_0_enc_ring_get_rptr +ffffffff81ece6c0 t vcn_v2_0_enc_ring_get_wptr +ffffffff81ece7b0 t vcn_v2_0_enc_ring_set_wptr +ffffffff81ece8a0 t vcn_v2_0_set_interrupt_state +ffffffff81ece8d0 t vcn_v2_0_process_interrupt +ffffffff81ece970 t vcn_v2_0_pause_dpg_mode +ffffffff81ecf2d0 t vcn_v2_0_enable_clock_gating +ffffffff81ecf550 t vcn_v2_0_disable_clock_gating +ffffffff81ecf950 t vcn_v2_0_enable_static_power_gating +ffffffff81ecfb30 t vcn_v2_0_start_dpg_mode +ffffffff81ed45f0 t vcn_v2_0_clock_gating_dpg_mode +ffffffff81ed5000 t vcn_v2_6_query_poison_status +ffffffff81ed50c0 t vcn_v2_5_early_init +ffffffff81ed5400 t vcn_v2_5_sw_init +ffffffff81ed5880 t vcn_v2_5_sw_fini +ffffffff81ed5950 t vcn_v2_5_hw_init +ffffffff81ed6410 t vcn_v2_5_hw_fini +ffffffff81ed6550 t vcn_v2_5_suspend +ffffffff81ed6570 t vcn_v2_5_resume +ffffffff81ed65c0 t vcn_v2_5_is_idle +ffffffff81ed66b0 t vcn_v2_5_wait_for_idle +ffffffff81ed67e0 t vcn_v2_5_set_clockgating_state +ffffffff81ed6850 t vcn_v2_5_set_powergating_state +ffffffff81ed7130 t vcn_v2_5_dec_ring_get_rptr +ffffffff81ed71c0 t vcn_v2_5_dec_ring_get_wptr +ffffffff81ed7270 t vcn_v2_5_dec_ring_set_wptr +ffffffff81ed7310 t vcn_v2_5_enc_ring_get_rptr +ffffffff81ed7400 t vcn_v2_5_enc_ring_get_wptr +ffffffff81ed7500 t vcn_v2_5_enc_ring_set_wptr +ffffffff81ed75f0 t vcn_v2_5_set_interrupt_state +ffffffff81ed7620 t vcn_v2_5_process_interrupt +ffffffff81ed7740 t vcn_v2_5_pause_dpg_mode +ffffffff81ed80b0 t vcn_v2_5_enable_clock_gating +ffffffff81ed83b0 t vcn_v2_5_disable_clock_gating +ffffffff81ed88d0 t vcn_v2_5_start +ffffffff81edc4d0 t vcn_v2_5_clock_gating_dpg_mode +ffffffff81edce70 t vcn_v2_5_mc_resume_dpg_mode +ffffffff81ee0000 t vcn_v3_0_early_init +ffffffff81ee0210 t vcn_v3_0_sw_init +ffffffff81ee06b0 t vcn_v3_0_sw_fini +ffffffff81ee0790 t vcn_v3_0_hw_init +ffffffff81ee1330 t vcn_v3_0_hw_fini +ffffffff81ee1430 t vcn_v3_0_suspend +ffffffff81ee1450 t vcn_v3_0_resume +ffffffff81ee14a0 t vcn_v3_0_is_idle +ffffffff81ee1590 t vcn_v3_0_wait_for_idle +ffffffff81ee16c0 t vcn_v3_0_set_clockgating_state +ffffffff81ee17d0 t vcn_v3_0_set_powergating_state +ffffffff81ee4050 t vcn_v3_0_dec_ring_get_rptr +ffffffff81ee40e0 t vcn_v3_0_dec_ring_get_wptr +ffffffff81ee4190 t vcn_v3_0_dec_ring_set_wptr +ffffffff81ee4300 t vcn_v3_0_ring_patch_cs_in_place +ffffffff81ee45f0 t vcn_v3_0_enc_ring_get_rptr +ffffffff81ee46e0 t vcn_v3_0_enc_ring_get_wptr +ffffffff81ee47e0 t vcn_v3_0_enc_ring_set_wptr +ffffffff81ee48d0 t vcn_v3_0_set_interrupt_state +ffffffff81ee4900 t vcn_v3_0_process_interrupt +ffffffff81ee49f0 t vcn_v3_0_pause_dpg_mode +ffffffff81ee5360 t vcn_v3_0_enable_clock_gating +ffffffff81ee55e0 t vcn_v3_0_disable_clock_gating +ffffffff81ee5b80 t vcn_v3_0_start_dpg_mode +ffffffff81eea920 t vcn_v3_0_clock_gating_dpg_mode +ffffffff81eec000 t vcn_v4_0_early_init +ffffffff81eec120 t vcn_v4_0_sw_init +ffffffff81eec350 t vcn_v4_0_sw_fini +ffffffff81eec430 t vcn_v4_0_hw_init +ffffffff81eece60 t vcn_v4_0_hw_fini +ffffffff81eecf60 t vcn_v4_0_suspend +ffffffff81eecf80 t vcn_v4_0_resume +ffffffff81eecfd0 t vcn_v4_0_is_idle +ffffffff81eed0c0 t vcn_v4_0_wait_for_idle +ffffffff81eed1f0 t vcn_v4_0_set_clockgating_state +ffffffff81eed300 t vcn_v4_0_set_powergating_state +ffffffff81eef8b0 t vcn_v4_0_unified_ring_get_rptr +ffffffff81eef990 t vcn_v4_0_unified_ring_get_wptr +ffffffff81eefa80 t vcn_v4_0_unified_ring_set_wptr +ffffffff81eefb80 t vcn_v4_0_ring_patch_cs_in_place +ffffffff81eefdf0 t vcn_v4_0_set_interrupt_state +ffffffff81eefe20 t vcn_v4_0_process_interrupt +ffffffff81eefed0 t vcn_v4_0_pause_dpg_mode +ffffffff81ef0290 t vcn_v4_0_enable_clock_gating +ffffffff81ef0580 t vcn_v4_0_disable_clock_gating +ffffffff81ef0ad0 t vcn_v4_0_start_dpg_mode +ffffffff81ef5160 t vcn_v4_0_disable_clock_gating_dpg_mode +ffffffff81ef6000 t vega10_ih_early_init +ffffffff81ef6050 t vega10_ih_sw_init +ffffffff81ef6300 t vega10_ih_sw_fini +ffffffff81ef6340 t vega10_ih_hw_init +ffffffff81ef66d0 t vega10_ih_hw_fini +ffffffff81ef6720 t vega10_ih_suspend +ffffffff81ef6770 t vega10_ih_resume +ffffffff81ef6780 t vega10_ih_is_idle +ffffffff81ef67b0 t vega10_ih_wait_for_idle +ffffffff81ef67e0 t vega10_ih_soft_reset +ffffffff81ef6810 t vega10_ih_set_clockgating_state +ffffffff81ef6950 t vega10_ih_set_powergating_state +ffffffff81ef6980 t vega10_ih_get_wptr +ffffffff81ef6a90 t vega10_ih_set_rptr +ffffffff81ef6b60 t vega10_ih_self_irq +ffffffff81ef6bd0 t vega10_ih_toggle_interrupts +ffffffff81ef7000 T vega10_reg_base_init +ffffffff81ef7150 T vega10_doorbell_index_init +ffffffff81ef8000 t vega20_ih_early_init +ffffffff81ef8050 t vega20_ih_sw_init +ffffffff81ef8300 t vega20_ih_sw_fini +ffffffff81ef8340 t vega20_ih_hw_init +ffffffff81ef8a60 t vega20_ih_hw_fini +ffffffff81ef8ab0 t vega20_ih_suspend +ffffffff81ef8b00 t vega20_ih_resume +ffffffff81ef8b10 t vega20_ih_is_idle +ffffffff81ef8b40 t vega20_ih_wait_for_idle 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bios_parser_program_crtc_timing +ffffffff81f2a3c0 t bios_parser_enable_disp_power_gating +ffffffff81f2a400 t firmware_parser_destroy +ffffffff81f2a4c0 t bios_get_board_layout_info +ffffffff81f2a970 t bios_parser_pack_data_tables +ffffffff81f2a9a0 t bios_get_atom_dc_golden_table +ffffffff81f2aae0 t bios_parser_enable_lvtma_control +ffffffff81f2ab30 t bios_parser_get_soc_bb_info +ffffffff81f2ac30 t bios_parser_get_disp_connector_caps_info +ffffffff81f2ad80 t bios_parser_get_lttpr_caps +ffffffff81f2aed0 t bios_parser_get_lttpr_interop +ffffffff81f2b010 t bios_parser_get_connector_speed_cap_info +ffffffff81f2b160 t get_bios_object +ffffffff81f2b2c0 t get_bios_object_from_path_v3 +ffffffff81f2c000 T object_id_from_bios_object_id +ffffffff81f2d000 T bios_get_image +ffffffff81f2d040 T bios_is_accelerated_mode +ffffffff81f2d0a0 T bios_set_scratch_acc_mode_change +ffffffff81f2d0d0 T bios_set_scratch_critical_state +ffffffff81f2d100 T bios_get_vga_enabled_displays +ffffffff81f2e000 T dal_bios_parser_create +ffffffff81f2e070 T dal_bios_parser_destroy +ffffffff81f2f000 T dal_bios_parser_init_cmd_tbl +ffffffff81f2f800 t encoder_control_digx_v3 +ffffffff81f2f900 t encoder_control_digx_v4 +ffffffff81f2fa00 t encoder_control_digx_v5 +ffffffff81f2fb50 t encoder_control_dig1_v1 +ffffffff81f2fbd0 t encoder_control_dig2_v1 +ffffffff81f2fc50 t encoder_control_dig_v1 +ffffffff81f2fcb0 t transmitter_control_v2 +ffffffff81f2fe50 t transmitter_control_v3 +ffffffff81f30010 t transmitter_control_v4 +ffffffff81f301c0 t transmitter_control_v1_5 +ffffffff81f30340 t transmitter_control_v1_6 +ffffffff81f304b0 t set_pixel_clock_v3 +ffffffff81f30620 t set_pixel_clock_v5 +ffffffff81f307c0 t set_pixel_clock_v6 +ffffffff81f30960 t set_pixel_clock_v7 +ffffffff81f30b30 t enable_spread_spectrum_on_ppll_v1 +ffffffff81f30c40 t enable_spread_spectrum_on_ppll_v2 +ffffffff81f30d60 t enable_spread_spectrum_on_ppll_v3 +ffffffff81f30e60 t adjust_display_pll_v2 +ffffffff81f30fb0 t adjust_display_pll_v3 +ffffffff81f31120 t dac1_encoder_control_v1 +ffffffff81f31190 t dac2_encoder_control_v1 +ffffffff81f31200 t dac1_output_control_v1 +ffffffff81f31260 t dac2_output_control_v1 +ffffffff81f312c0 t set_crtc_using_dtd_timing_v3 +ffffffff81f31420 t set_crtc_timing_v1 +ffffffff81f315c0 t enable_crtc_v1 +ffffffff81f31660 t enable_crtc_mem_req_v1 +ffffffff81f31700 t program_clock_v5 +ffffffff81f31800 t program_clock_v6 +ffffffff81f31920 t external_encoder_control_v3 +ffffffff81f31ad0 t enable_disp_power_gating_v2_1 +ffffffff81f31b90 t set_dce_clock_v2_1 +ffffffff81f32000 T dal_firmware_parser_init_cmd_tbl +ffffffff81f323d0 t encoder_control_digx_v1_5 +ffffffff81f325a0 t encoder_control_fallback +ffffffff81f325f0 t transmitter_control_v1_6 +ffffffff81f32790 t transmitter_control_v1_7 +ffffffff81f32980 t transmitter_control_fallback +ffffffff81f329d0 t set_pixel_clock_v7 +ffffffff81f32c20 t set_pixel_clock_fallback +ffffffff81f32c70 t set_crtc_using_dtd_timing_v3 +ffffffff81f32dd0 t enable_crtc_v1 +ffffffff81f32e70 t external_encoder_control_v3 +ffffffff81f32ea0 t enable_disp_power_gating_v2_1 +ffffffff81f33000 t enable_disp_power_gating_fallback +ffffffff81f33050 t set_dce_clock_v2_1 +ffffffff81f33170 t get_smu_clock_info_v3_1 +ffffffff81f331d0 t enable_lvtma_control +ffffffff81f34000 T dal_bios_parser_init_cmd_tbl_helper +ffffffff81f340a0 T dal_cmd_table_helper_controller_id_to_atom +ffffffff81f341b0 T dal_cmd_table_helper_transmitter_bp_to_atom +ffffffff81f34230 T dal_cmd_table_helper_encoder_mode_bp_to_atom +ffffffff81f342c0 T dal_cmd_table_helper_assign_control_parameter +ffffffff81f34380 T dal_cmd_table_helper_clock_source_id_to_ref_clk_src +ffffffff81f34460 T dal_cmd_table_helper_encoder_id_to_atom +ffffffff81f35000 T dal_bios_parser_init_cmd_tbl_helper2 +ffffffff81f350b0 T dal_cmd_table_helper_controller_id_to_atom2 +ffffffff81f351b0 T dal_cmd_table_helper_transmitter_bp_to_atom2 +ffffffff81f35230 T dal_cmd_table_helper_encoder_mode_bp_to_atom2 +ffffffff81f352c0 T dal_cmd_table_helper_clock_source_id_to_ref_clk_src2 +ffffffff81f353a0 T dal_cmd_table_helper_encoder_id_to_atom2 +ffffffff81f36000 T dal_cmd_tbl_helper_dce110_get_table +ffffffff81f36030 t encoder_action_to_atom +ffffffff81f360a0 t engine_bp_to_atom +ffffffff81f360e0 t clock_source_id_to_atom +ffffffff81f36170 t clock_source_id_to_atom_phy_clk_src_id +ffffffff81f361c0 t signal_type_to_atom_dig_mode +ffffffff81f36220 t hpd_sel_to_atom +ffffffff81f36250 t dig_encoder_sel_to_atom +ffffffff81f36280 t phy_id_to_atom +ffffffff81f362c0 t disp_power_gating_action_to_atom +ffffffff81f37000 T dal_cmd_tbl_helper_dce112_get_table2 +ffffffff81f37030 t encoder_action_to_atom +ffffffff81f370a0 t engine_bp_to_atom +ffffffff81f370e0 t clock_source_id_to_atom +ffffffff81f371b0 t clock_source_id_to_atom_phy_clk_src_id +ffffffff81f37200 t signal_type_to_atom_dig_mode +ffffffff81f37260 t hpd_sel_to_atom +ffffffff81f37290 t dig_encoder_sel_to_atom +ffffffff81f372c0 t phy_id_to_atom +ffffffff81f37300 t disp_power_gating_action_to_atom +ffffffff81f37370 t dc_clock_type_to_atom +ffffffff81f373f0 t transmitter_color_depth_to_atom +ffffffff81f38000 T dal_cmd_tbl_helper_dce112_get_table +ffffffff81f38030 t encoder_action_to_atom +ffffffff81f380a0 t engine_bp_to_atom +ffffffff81f380e0 t clock_source_id_to_atom +ffffffff81f381b0 t clock_source_id_to_atom_phy_clk_src_id +ffffffff81f38200 t signal_type_to_atom_dig_mode +ffffffff81f38260 t hpd_sel_to_atom +ffffffff81f38290 t dig_encoder_sel_to_atom +ffffffff81f382c0 t phy_id_to_atom +ffffffff81f38300 t disp_power_gating_action_to_atom +ffffffff81f38370 t dc_clock_type_to_atom +ffffffff81f383f0 t transmitter_color_depth_to_atom +ffffffff81f39000 T dal_cmd_tbl_helper_dce80_get_table +ffffffff81f39030 t encoder_action_to_atom +ffffffff81f390a0 t engine_bp_to_atom +ffffffff81f390e0 t clock_source_id_to_atom +ffffffff81f391b0 t clock_source_id_to_atom_phy_clk_src_id +ffffffff81f39200 t signal_type_to_atom_dig_mode +ffffffff81f39260 t hpd_sel_to_atom +ffffffff81f39290 t dig_encoder_sel_to_atom +ffffffff81f392e0 t phy_id_to_atom +ffffffff81f39320 t disp_power_gating_action_to_atom +ffffffff81f3a000 T clk_mgr_helper_get_active_display_cnt +ffffffff81f3a0e0 T clk_mgr_helper_get_active_plane_cnt +ffffffff81f3a190 T clk_mgr_exit_optimized_pwr_state +ffffffff81f3a290 T clk_mgr_optimize_pwr_state +ffffffff81f3a3a0 T dc_clk_mgr_create +ffffffff81f3aa80 T dc_destroy_clk_mgr +ffffffff81f3b000 T dentist_get_divider_from_did +ffffffff81f3b070 T dce_adjust_dp_ref_freq_for_ss +ffffffff81f3b170 T dce_get_dp_ref_freq_khz +ffffffff81f3b2a0 T dce12_get_dp_ref_freq_khz +ffffffff81f3b2b0 T dce_get_max_pixel_clock_for_all_paths +ffffffff81f3b4c0 T dce_get_required_clocks_state +ffffffff81f3b560 T dce_set_clock +ffffffff81f3b6b0 T dce_clock_read_ss_info +ffffffff81f3b7f0 T dce_clk_mgr_construct +ffffffff81f3b9e0 t dce_update_clocks +ffffffff81f3c000 T dce110_get_min_vblank_time_us +ffffffff81f3c080 T dce110_fill_display_configs +ffffffff81f3c2d0 T dce11_pplib_apply_display_requirements +ffffffff81f3c5c0 T dce110_clk_mgr_construct +ffffffff81f3c670 t dce11_update_clocks +ffffffff81f3d000 T dce112_set_clock +ffffffff81f3d190 T dce112_set_dispclk +ffffffff81f3d2c0 T dce112_set_dprefclk +ffffffff81f3d320 T dce112_clk_mgr_construct +ffffffff81f3d3d0 t dce112_update_clocks +ffffffff81f3e000 T dce120_clk_mgr_construct +ffffffff81f3e090 T dce121_clk_mgr_construct +ffffffff81f3e1c0 t dce12_update_clocks +ffffffff81f3f000 T rv1_clk_mgr_construct +ffffffff81f3f0c0 t rv1_update_clocks +ffffffff81f3f5a0 t rv1_init_clocks +ffffffff81f3f630 t rv1_enable_pme_wa +ffffffff81f40000 T rv1_vbios_smu_set_dispclk +ffffffff81f400f0 t rv1_vbios_smu_send_msg_with_param +ffffffff81f40200 T rv1_vbios_smu_set_dprefclk +ffffffff81f41000 T rv2_clk_mgr_construct +ffffffff81f42000 T dentist_get_did_from_divider +ffffffff81f42090 T dcn20_update_clocks_update_dpp_dto +ffffffff81f42150 T dcn20_update_clocks_update_dentist +ffffffff81f42670 T dcn2_update_clocks +ffffffff81f42bd0 T dcn2_read_clocks_from_hw_dentist +ffffffff81f42ca0 T dcn2_update_clocks_fpga +ffffffff81f42e10 T dcn2_init_clocks +ffffffff81f42eb0 T dcn2_get_clock +ffffffff81f42f20 T dcn20_clk_mgr_construct +ffffffff81f43060 t dcn2_enable_pme_wa +ffffffff81f430b0 t dcn2_are_clock_states_equal +ffffffff81f43120 t dcn2_notify_link_rate_change +ffffffff81f44000 t dcn201_update_clocks +ffffffff81f44240 t dcn201_init_clocks +ffffffff81f442e0 T dcn201_clk_mgr_construct +ffffffff81f45000 T rn_clk_mgr_construct +ffffffff81f458e0 t rn_update_clocks +ffffffff81f45e80 t rn_set_low_power_state +ffffffff81f46050 t rn_init_clocks +ffffffff81f460f0 t rn_enable_pme_wa +ffffffff81f46100 t rn_are_clock_states_equal +ffffffff81f46150 t rn_notify_wm_ranges +ffffffff81f464d0 t rn_notify_link_rate_change +ffffffff81f47000 T rn_vbios_smu_get_smu_version +ffffffff81f47010 t rn_vbios_smu_send_msg_with_param +ffffffff81f471a0 T rn_vbios_smu_set_dispclk +ffffffff81f472d0 T rn_vbios_smu_set_dprefclk +ffffffff81f47330 T rn_vbios_smu_set_hard_min_dcfclk +ffffffff81f473a0 T rn_vbios_smu_set_min_deep_sleep_dcfclk +ffffffff81f47410 T rn_vbios_smu_set_phyclk +ffffffff81f47450 T rn_vbios_smu_set_dppclk +ffffffff81f47510 T rn_vbios_smu_set_dcn_low_power_state +ffffffff81f47530 T rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn +ffffffff81f47550 T rn_vbios_smu_enable_pme_wa +ffffffff81f47570 T rn_vbios_smu_is_periodic_retraining_disabled +ffffffff81f48000 T dcn3_init_clocks +ffffffff81f483d0 t dcn3_init_clocks_fpga +ffffffff81f483e0 T dcn3_clk_mgr_construct +ffffffff81f48540 T dcn3_clk_mgr_destroy +ffffffff81f485a0 t dcn3_update_clocks +ffffffff81f48a00 t dcn3_enable_pme_wa +ffffffff81f48a40 t dcn3_are_clock_states_equal +ffffffff81f48aa0 t dcn3_notify_wm_ranges +ffffffff81f48d30 t dcn30_notify_link_rate_change +ffffffff81f48e40 t dcn3_set_hard_min_memclk +ffffffff81f48ee0 t dcn3_set_hard_max_memclk +ffffffff81f48f30 t dcn3_set_max_memclk +ffffffff81f48f70 t dcn3_set_min_memclk +ffffffff81f48fb0 t dcn3_get_memclk_states_from_smu +ffffffff81f490f0 t dcn3_is_smu_present +ffffffff81f4a000 T dcn30_smu_test_message +ffffffff81f4a060 t dcn30_smu_send_msg_with_param +ffffffff81f4a1c0 T dcn30_smu_get_smu_version +ffffffff81f4a1e0 T dcn30_smu_check_driver_if_version +ffffffff81f4a230 T dcn30_smu_check_msg_header_version +ffffffff81f4a280 T dcn30_smu_set_dram_addr_high +ffffffff81f4a2a0 T dcn30_smu_set_dram_addr_low +ffffffff81f4a2c0 T dcn30_smu_transfer_wm_table_smu_2_dram +ffffffff81f4a2e0 T dcn30_smu_transfer_wm_table_dram_2_smu +ffffffff81f4a300 T dcn30_smu_set_hard_min_by_freq +ffffffff81f4a350 T dcn30_smu_set_hard_max_by_freq +ffffffff81f4a3a0 T dcn30_smu_get_dpm_freq_by_index +ffffffff81f4a3f0 T dcn30_smu_get_dc_mode_max_dpm_freq +ffffffff81f4a440 T dcn30_smu_set_min_deep_sleep_dcef_clk +ffffffff81f4a460 T dcn30_smu_set_num_of_displays +ffffffff81f4a480 T dcn30_smu_set_display_refresh_from_mall +ffffffff81f4a4b0 T dcn30_smu_set_external_client_df_cstate_allow +ffffffff81f4a4d0 T dcn30_smu_set_pme_workaround +ffffffff81f4b000 T dcn301_smu_get_smu_version +ffffffff81f4b070 t dcn301_smu_send_msg_with_param +ffffffff81f4b1f0 T dcn301_smu_set_dispclk +ffffffff81f4b290 T dcn301_smu_set_dprefclk +ffffffff81f4b330 T dcn301_smu_set_hard_min_dcfclk +ffffffff81f4b3d0 T dcn301_smu_set_min_deep_sleep_dcfclk +ffffffff81f4b470 T dcn301_smu_set_dppclk +ffffffff81f4b510 T dcn301_smu_set_display_idle_optimization +ffffffff81f4b560 T dcn301_smu_enable_phy_refclk_pwrdwn +ffffffff81f4b5b0 T dcn301_smu_enable_pme_wa +ffffffff81f4b5d0 T dcn301_smu_set_dram_addr_high +ffffffff81f4b620 T dcn301_smu_set_dram_addr_low +ffffffff81f4b670 T dcn301_smu_transfer_dpm_table_smu_2_dram +ffffffff81f4b690 T dcn301_smu_transfer_wm_table_dram_2_smu +ffffffff81f4c000 T vg_clk_mgr_construct +ffffffff81f4c7f0 T vg_clk_mgr_destroy +ffffffff81f4c840 t vg_update_clocks +ffffffff81f4cbd0 t vg_init_clocks +ffffffff81f4cc70 t vg_enable_pme_wa +ffffffff81f4cc80 t vg_are_clock_states_equal +ffffffff81f4ccd0 t vg_notify_wm_ranges +ffffffff81f4e000 T dcn31_update_clocks +ffffffff81f4e620 T dcn31_init_clocks +ffffffff81f4e6d0 T dcn31_are_clock_states_equal +ffffffff81f4e730 T dcn31_get_dtb_ref_freq_khz +ffffffff81f4e760 T dcn31_clk_mgr_construct +ffffffff81f4edd0 T dcn31_clk_mgr_destroy +ffffffff81f4ee20 t dcn31_set_low_power_state +ffffffff81f4f000 t dcn31_enable_pme_wa +ffffffff81f4f010 t dcn31_notify_wm_ranges +ffffffff81f4f3b0 t find_clk_for_voltage +ffffffff81f50000 T dcn31_smu_get_smu_version +ffffffff81f50010 t dcn31_smu_send_msg_with_param +ffffffff81f50210 T dcn31_smu_set_dispclk +ffffffff81f50280 T dcn31_smu_set_dprefclk +ffffffff81f502f0 T dcn31_smu_set_hard_min_dcfclk +ffffffff81f50370 T dcn31_smu_set_min_deep_sleep_dcfclk +ffffffff81f503f0 T dcn31_smu_set_dppclk +ffffffff81f50460 T dcn31_smu_set_display_idle_optimization +ffffffff81f504b0 T dcn31_smu_enable_phy_refclk_pwrdwn +ffffffff81f504f0 T dcn31_smu_enable_pme_wa +ffffffff81f50530 T dcn31_smu_set_dram_addr_high +ffffffff81f50570 T dcn31_smu_set_dram_addr_low +ffffffff81f505b0 T dcn31_smu_transfer_dpm_table_smu_2_dram +ffffffff81f505f0 T dcn31_smu_transfer_wm_table_dram_2_smu +ffffffff81f50630 T dcn31_smu_set_zstate_support +ffffffff81f50690 T dcn31_smu_set_dtbclk +ffffffff81f51000 T dcn314_update_clocks +ffffffff81f516d0 T dcn314_are_clock_states_equal +ffffffff81f51730 T dcn314_clk_mgr_construct +ffffffff81f52430 T dcn314_clk_mgr_destroy +ffffffff81f52480 t dcn314_enable_pme_wa +ffffffff81f52490 t dcn314_notify_wm_ranges +ffffffff81f53000 T dcn314_smu_get_smu_version +ffffffff81f53010 t dcn314_smu_send_msg_with_param +ffffffff81f53230 T dcn314_smu_set_dispclk +ffffffff81f532a0 T dcn314_smu_set_dprefclk +ffffffff81f53310 T dcn314_smu_set_hard_min_dcfclk +ffffffff81f53390 T dcn314_smu_set_min_deep_sleep_dcfclk +ffffffff81f53410 T dcn314_smu_set_dppclk +ffffffff81f53480 T dcn314_smu_set_display_idle_optimization +ffffffff81f534d0 T dcn314_smu_enable_phy_refclk_pwrdwn +ffffffff81f53510 T dcn314_smu_enable_pme_wa +ffffffff81f53550 T dcn314_smu_set_dram_addr_high +ffffffff81f53590 T dcn314_smu_set_dram_addr_low +ffffffff81f535d0 T dcn314_smu_transfer_dpm_table_smu_2_dram +ffffffff81f53610 T dcn314_smu_transfer_wm_table_dram_2_smu +ffffffff81f53650 T dcn314_smu_set_zstate_support +ffffffff81f536a0 T dcn314_smu_set_dtbclk +ffffffff81f54000 T dcn315_clk_mgr_construct +ffffffff81f549c0 T dcn315_clk_mgr_destroy +ffffffff81f54a10 t dcn315_update_clocks +ffffffff81f54ff0 t dcn315_enable_pme_wa +ffffffff81f55000 t dcn315_notify_wm_ranges +ffffffff81f56000 T dcn315_smu_get_smu_version +ffffffff81f56010 t dcn315_smu_send_msg_with_param +ffffffff81f561a0 T dcn315_smu_set_dispclk +ffffffff81f56210 T dcn315_smu_set_hard_min_dcfclk +ffffffff81f56290 T dcn315_smu_set_min_deep_sleep_dcfclk +ffffffff81f56310 T dcn315_smu_set_dppclk +ffffffff81f56380 T dcn315_smu_set_display_idle_optimization +ffffffff81f563d0 T dcn315_smu_enable_phy_refclk_pwrdwn +ffffffff81f56410 T dcn315_smu_enable_pme_wa +ffffffff81f56450 T dcn315_smu_set_dram_addr_high +ffffffff81f56490 T dcn315_smu_set_dram_addr_low +ffffffff81f564d0 T dcn315_smu_transfer_dpm_table_smu_2_dram +ffffffff81f56510 T dcn315_smu_transfer_wm_table_dram_2_smu +ffffffff81f56550 T dcn315_smu_get_dpref_clk +ffffffff81f565a0 T dcn315_smu_get_dtbclk +ffffffff81f565f0 T dcn315_smu_set_dtbclk +ffffffff81f57000 T dcn316_clk_mgr_construct +ffffffff81f576a0 T dcn316_clk_mgr_destroy +ffffffff81f576f0 t dcn316_update_clocks +ffffffff81f57d20 t dcn316_enable_pme_wa +ffffffff81f57d30 t dcn316_notify_wm_ranges +ffffffff81f580c0 t find_clk_for_voltage +ffffffff81f59000 T dcn316_smu_get_smu_version +ffffffff81f59010 t dcn316_smu_send_msg_with_param +ffffffff81f591a0 T dcn316_smu_set_dispclk +ffffffff81f59210 T dcn316_smu_set_hard_min_dcfclk +ffffffff81f59290 T dcn316_smu_set_min_deep_sleep_dcfclk +ffffffff81f59310 T dcn316_smu_set_dppclk +ffffffff81f59380 T dcn316_smu_set_display_idle_optimization +ffffffff81f593d0 T dcn316_smu_enable_phy_refclk_pwrdwn +ffffffff81f59410 T dcn316_smu_set_dram_addr_high +ffffffff81f59450 T dcn316_smu_set_dram_addr_low +ffffffff81f59490 T dcn316_smu_transfer_dpm_table_smu_2_dram +ffffffff81f594d0 T dcn316_smu_transfer_wm_table_dram_2_smu +ffffffff81f59510 T dcn316_smu_enable_pme_wa +ffffffff81f59550 T dcn316_smu_set_dtbclk +ffffffff81f59590 T dcn316_smu_get_dpref_clk +ffffffff81f595e0 T dcn316_smu_get_smu_fclk +ffffffff81f5a000 T dcn32_init_clocks +ffffffff81f5a4d0 T dcn32_clk_mgr_construct +ffffffff81f5a760 T dcn32_clk_mgr_destroy +ffffffff81f5a7c0 t dcn32_update_clocks +ffffffff81f5af00 t dcn32_dump_clk_registers +ffffffff81f5b120 t dcn32_enable_pme_wa +ffffffff81f5b160 t dcn32_are_clock_states_equal +ffffffff81f5b1c0 t dcn32_notify_wm_ranges +ffffffff81f5b340 t dcn32_set_hard_min_memclk +ffffffff81f5b3e0 t dcn32_set_hard_max_memclk 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dcn10_dmcu_create +ffffffff81fa4160 T dcn20_dmcu_create +ffffffff81fa4210 T dcn21_dmcu_create +ffffffff81fa4300 T dce_dmcu_destroy +ffffffff81fa4350 t dce_dmcu_init +ffffffff81fa4380 t dce_dmcu_load_iram +ffffffff81fa44e0 t dce_dmcu_set_psr_enable +ffffffff81fa4620 t dce_dmcu_setup_psr +ffffffff81fa4940 t dce_get_dmcu_psr_state +ffffffff81fa4a20 t dce_psr_wait_loop +ffffffff81fa4b50 t dce_get_psr_wait_loop +ffffffff81fa4b80 t dce_is_dmcu_initialized +ffffffff81fa4be0 t dcn10_dmcu_init +ffffffff81fa5120 t dcn10_dmcu_load_iram +ffffffff81fa5370 t dcn10_dmcu_set_psr_enable +ffffffff81fa5500 t dcn10_dmcu_setup_psr +ffffffff81fa58c0 t dcn10_get_dmcu_psr_state +ffffffff81fa59e0 t dcn10_psr_wait_loop +ffffffff81fa5af0 t dcn10_get_psr_wait_loop +ffffffff81fa5b20 t dcn10_is_dmcu_initialized +ffffffff81fa5b50 t dcn10_send_edid_cea +ffffffff81fa5cf0 t dcn10_recv_amd_vsdb +ffffffff81fa5da0 t dcn10_recv_edid_cea_ack +ffffffff81fa5e10 t dcn10_get_scp_results +ffffffff81fa5f30 t dcn20_lock_phy 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dce_ipp_destroy +ffffffff81fac0a0 t dce_ipp_cursor_set_position +ffffffff81fac1d0 t dce_ipp_cursor_set_attributes +ffffffff81fac460 t dce_ipp_program_prescale +ffffffff81fac610 t dce_ipp_program_input_lut +ffffffff81facaa0 t dce_ipp_set_degamma +ffffffff81fad000 T dce110_get_dig_frontend +ffffffff81fad0b0 T dce110_link_encoder_set_dp_phy_pattern_training_pattern +ffffffff81fad150 T dce110_psr_program_dp_dphy_fast_training +ffffffff81fad1c0 T dce110_psr_program_secondary_packet +ffffffff81fad220 T dce110_is_dig_enabled +ffffffff81fad270 T dce110_link_encoder_validate_dvi_output +ffffffff81fad320 T dce110_link_encoder_validate_dp_output +ffffffff81fad350 T dce110_link_encoder_construct +ffffffff81fad520 T dce110_link_encoder_validate_output_with_stream +ffffffff81fad6c0 T dce110_link_encoder_hw_init +ffffffff81fad8e0 T dce110_link_encoder_destroy +ffffffff81fad930 T dce110_link_encoder_setup +ffffffff81fada60 T dce110_link_encoder_enable_tmds_output +ffffffff81fadb50 T dce110_link_encoder_enable_lvds_output +ffffffff81fadc40 T dce110_link_encoder_enable_dp_output +ffffffff81faddc0 T dce110_link_encoder_enable_dp_mst_output +ffffffff81fadf30 T dce110_link_encoder_disable_output +ffffffff81fae140 T dce110_link_encoder_dp_set_lane_settings +ffffffff81fae2e0 T dce110_link_encoder_dp_set_phy_pattern +ffffffff81faeae0 t set_dp_phy_pattern_hbr2_compliance_cp2520_2 +ffffffff81faecf0 T dce110_link_encoder_update_mst_stream_allocation_table +ffffffff81faef70 T dce110_link_encoder_connect_dig_be_to_fe +ffffffff81faf0a0 T dce110_link_encoder_enable_hpd +ffffffff81faf0d0 T dce110_link_encoder_disable_hpd +ffffffff81faf100 T dce110_link_encoder_get_max_link_cap +ffffffff81fb0000 T dce_mem_input_construct +ffffffff81fb0050 T dce112_mem_input_construct +ffffffff81fb00a0 T dce120_mem_input_construct +ffffffff81fb00f0 t dce_mi_program_display_marks +ffffffff81fb03c0 t dce_mi_allocate_dmif +ffffffff81fb0600 t dce_mi_free_dmif +ffffffff81fb0760 t dce_mi_program_surface_flip_and_addr +ffffffff81fb0a70 t dce_mi_program_pte_vm +ffffffff81fb0c30 t dce_mi_program_surface_config +ffffffff81fb14b0 t dce_mi_is_flip_pending +ffffffff81fb1540 t program_nbp_watermark +ffffffff81fb1740 t dce112_mi_program_display_marks +ffffffff81fb1c50 t dce120_mi_program_display_marks +ffffffff81fb2110 t dce120_program_stutter_watermark +ffffffff81fb3000 T dce110_opp_set_clamping +ffffffff81fb32b0 T dce110_opp_program_bit_depth_reduction +ffffffff81fb3a70 T dce110_opp_program_clamping_and_pixel_encoding +ffffffff81fb3c00 T dce110_opp_set_dyn_expansion +ffffffff81fb3d50 T dce110_opp_program_fmt +ffffffff81fb3ed0 T dce110_opp_construct +ffffffff81fb3f20 T dce110_opp_destroy +ffffffff81fb4000 T dce_panel_cntl_construct +ffffffff81fb4060 t dce_panel_cntl_destroy +ffffffff81fb40b0 t dce_panel_cntl_hw_init +ffffffff81fb42f0 t dce_is_panel_backlight_on +ffffffff81fb43a0 t dce_is_panel_powered_on +ffffffff81fb4450 t dce_store_backlight_level +ffffffff81fb44f0 t dce_driver_set_backlight +ffffffff81fb4680 t dce_get_16_bit_backlight_from_pwm +ffffffff81fb5000 T get_filter_3tap_16p +ffffffff81fb5090 T get_filter_3tap_64p +ffffffff81fb5120 T get_filter_4tap_16p +ffffffff81fb51b0 T get_filter_4tap_64p +ffffffff81fb5240 T get_filter_5tap_64p +ffffffff81fb52d0 T get_filter_6tap_64p +ffffffff81fb5360 T get_filter_7tap_64p +ffffffff81fb53f0 T get_filter_8tap_64p +ffffffff81fb5480 T get_filter_2tap_16p +ffffffff81fb54b0 T get_filter_2tap_64p +ffffffff81fb6000 T dce110_se_audio_mute_control +ffffffff81fb6040 T dce110_se_dp_audio_setup +ffffffff81fb6050 t dce110_se_audio_setup +ffffffff81fb61e0 T dce110_se_dp_audio_enable +ffffffff81fb6420 T dce110_se_dp_audio_disable +ffffffff81fb6580 T dce110_se_hdmi_audio_setup +ffffffff81fb6a80 T dce110_se_hdmi_audio_disable +ffffffff81fb6ae0 T dce110_stream_encoder_construct +ffffffff81fb6b30 t dce110_stream_encoder_dp_set_stream_attribute +ffffffff81fb7180 t dce110_stream_encoder_hdmi_set_stream_attribute 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dce110_opp_set_csc_adjustment +ffffffff81fba3c0 t program_color_matrix +ffffffff81fba5f0 T dce110_opp_set_csc_default +ffffffff81fba730 T dce110_opp_program_regamma_pwl +ffffffff81fbaff0 T dce110_opp_power_on_regamma_lut +ffffffff81fbb0b0 T dce110_opp_set_regamma_mode +ffffffff81fbb120 T dce_transform_construct +ffffffff81fbb190 t dce_transform_reset +ffffffff81fbb1d0 t dce_transform_set_scaler +ffffffff81fbbc60 t dce_transform_set_pixel_storage_depth +ffffffff81fbc120 t dce_transform_set_gamut_remap +ffffffff81fbc460 t program_multi_taps_filter +ffffffff81fbd000 T dmub_abm_create +ffffffff81fbd0b0 T dmub_abm_destroy +ffffffff81fbd100 t dmub_abm_init +ffffffff81fbd4e0 t dmub_abm_set_level +ffffffff81fbd6a0 t dmub_abm_get_current_backlight +ffffffff81fbd6d0 t dmub_abm_get_target_backlight +ffffffff81fbd700 t dmub_abm_init_config +ffffffff81fbd830 t dmub_abm_set_pause +ffffffff81fbe000 T dmub_hw_lock_mgr_cmd +ffffffff81fbe0b0 T dmub_hw_lock_mgr_inbox0_cmd +ffffffff81fbe0e0 T should_use_dmub_lock +ffffffff81fbf000 T dmub_enable_outbox_notification +ffffffff81fc0000 T dmub_psr_create +ffffffff81fc0090 T dmub_psr_destroy +ffffffff81fc00e0 t dmub_psr_copy_settings +ffffffff81fc0590 t dmub_psr_enable +ffffffff81fc0720 t dmub_psr_get_state +ffffffff81fc0a10 t dmub_psr_set_level +ffffffff81fc0b00 t dmub_psr_force_static +ffffffff81fc0bb0 t dmub_psr_get_residency +ffffffff81fc0c00 t dmub_psr_set_sink_vtotal_in_psr_active +ffffffff81fc0cb0 t dmub_psr_set_power_opt +ffffffff81fc1000 T dce100_enable_display_power_gating +ffffffff81fc10a0 T dce100_prepare_bandwidth +ffffffff81fc10e0 T dce100_optimize_bandwidth +ffffffff81fc1130 T dce100_hw_sequencer_construct +ffffffff81fc2000 T dce100_add_stream_to_ctx +ffffffff81fc2090 T dce100_validate_plane +ffffffff81fc20d0 T dce100_find_first_free_match_stream_enc_for_link +ffffffff81fc2170 T dce100_create_resource_pool +ffffffff81fc2f10 t dce100_resource_destruct +ffffffff81fc31e0 t dce100_destroy_resource_pool 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dce110_edp_wait_for_hpd_ready +ffffffff81fc5410 T dce110_edp_power_control +ffffffff81fc58d0 T dce110_edp_wait_for_T12 +ffffffff81fc5a60 T dce110_edp_backlight_control +ffffffff81fc5d90 T dce110_enable_audio_stream +ffffffff81fc5ea0 T dce110_disable_audio_stream +ffffffff81fc6010 T dce110_disable_stream +ffffffff81fc6140 T dce110_unblank_stream +ffffffff81fc6230 T dce110_blank_stream +ffffffff81fc6380 T dce110_set_avmute +ffffffff81fc63d0 T dce110_enable_accelerated_mode +ffffffff81fc6790 t power_down_all_hw_blocks +ffffffff81fc6950 T dce110_set_safe_displaymarks +ffffffff81fc6aa0 T dce110_apply_ctx_to_hw +ffffffff81fc7370 t enable_fbc +ffffffff81fc7520 T dce110_power_down +ffffffff81fc7620 T dce110_prepare_bandwidth +ffffffff81fc7760 T dce110_optimize_bandwidth +ffffffff81fc7920 T dce110_set_backlight_level +ffffffff81fc7a30 T dce110_set_abm_immediate_disable +ffffffff81fc7ab0 T dce110_set_pipe +ffffffff81fc7b20 T dce110_enable_lvds_link_output +ffffffff81fc7b80 T dce110_enable_tmds_link_output +ffffffff81fc7be0 T dce110_enable_dp_link_output +ffffffff81fc7df0 T dce110_disable_link_output +ffffffff81fc7f00 T dce110_hw_sequencer_construct +ffffffff81fc7f50 t enable_display_pipe_clock_gating +ffffffff81fc7f80 t build_audio_output +ffffffff81fc80e0 t init_hw +ffffffff81fc83a0 t dce110_power_down_fe +ffffffff81fc8460 t dce110_apply_ctx_for_surface +ffffffff81fc8b80 t dce110_post_unlock_program_front_end +ffffffff81fc8bb0 t update_plane_addr +ffffffff81fc8c20 t dce110_wait_for_mpcc_disconnect +ffffffff81fc8c50 t dce110_update_pending_status +ffffffff81fc8d30 t get_position +ffffffff81fc8db0 t dce110_enable_per_frame_crtc_position_reset +ffffffff81fc9060 t dce110_enable_timing_synchronization +ffffffff81fc9370 t set_drr +ffffffff81fc9450 t set_static_screen_control +ffffffff81fc9520 t dce110_set_cursor_position +ffffffff81fc9660 t dce110_set_cursor_attribute +ffffffff81fc9720 t program_gamut_remap +ffffffff81fc9870 t program_output_csc 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dce110_stream_encoder_create +ffffffff81fd0ca0 t dce110_hwseq_create +ffffffff81fd1000 T dce110_timing_generator_set_early_control +ffffffff81fd1070 T dce110_timing_generator_enable_crtc +ffffffff81fd1100 T dce110_timing_generator_program_blank_color +ffffffff81fd1190 T dce110_timing_generator_disable_crtc +ffffffff81fd11e0 T dce110_timing_generator_program_timing_generator +ffffffff81fd13d0 T dce110_timing_generator_set_drr +ffffffff81fd1510 T dce110_timing_generator_set_static_screen_control +ffffffff81fd15a0 T dce110_timing_generator_get_vblank_counter +ffffffff81fd15f0 T dce110_timing_generator_get_position +ffffffff81fd1690 T dce110_timing_generator_get_crtc_scanoutpos +ffffffff81fd1770 T dce110_timing_generator_program_blanking +ffffffff81fd19e0 T dce110_timing_generator_set_test_pattern +ffffffff81fd1cd0 T dce110_timing_generator_validate_timing +ffffffff81fd1da0 T dce110_timing_generator_wait_for_vblank +ffffffff81fd1f10 T dce110_timing_generator_is_counter_moving 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dce110_timing_generator_v_set_colors +ffffffff81fd49b0 t dce110_timing_generator_v_disable_vga +ffffffff81fd49e0 t dce110_timing_generator_v_did_triggered_reset_occur +ffffffff81fd4a20 t dce110_timing_generator_v_setup_global_swap_lock +ffffffff81fd4a40 t dce110_timing_generator_v_enable_reset_trigger +ffffffff81fd4a60 t dce110_timing_generator_v_disable_reset_trigger +ffffffff81fd4a80 t dce110_timing_generator_v_tear_down_global_swap_lock +ffffffff81fd4aa0 t dce110_timing_generator_v_enable_advanced_request +ffffffff81fd5000 T dce110_transform_v_construct +ffffffff81fd5060 t dce110_xfmv_reset +ffffffff81fd50b0 t dce110_xfmv_set_scaler +ffffffff81fd5810 t dce110_xfmv_set_pixel_storage_depth +ffffffff81fd58f0 t dce110_xfmv_set_gamut_remap +ffffffff81fd5920 t program_multi_taps_filter +ffffffff81fd5d10 t program_viewport +ffffffff81fd6000 T dce112_compressor_power_up_fbc +ffffffff81fd6130 T dce112_compressor_enable_fbc +ffffffff81fd62e0 T dce112_compressor_is_fbc_enabled_in_hw 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dpp1_set_hdr_multiplier +ffffffff81feb000 T dpp1_dscl_calc_lb_num_partitions +ffffffff81feb1d0 T dpp1_dscl_is_lb_conf_valid +ffffffff81feb210 T dpp1_dscl_set_scaler_manual_scale +ffffffff81fec5d0 t dpp1_dscl_get_filter_coeffs_64p +ffffffff81fec6a0 t dpp1_dscl_set_scaler_filter +ffffffff81fed000 T hubbub1_wm_read_state +ffffffff81fed380 T hubbub1_allow_self_refresh_control +ffffffff81fed400 T hubbub1_is_allow_self_refresh_enabled +ffffffff81fed460 T hubbub1_verify_allow_pstate_change_high +ffffffff81fed620 T hubbub1_wm_change_req_wa +ffffffff81fed6b0 T hubbub1_program_urgent_watermarks +ffffffff81feda80 T hubbub1_program_stutter_watermarks +ffffffff81fedee0 T hubbub1_program_pstate_watermarks +ffffffff81fee120 T hubbub1_program_watermarks +ffffffff81fee250 T hubbub1_update_dchub +ffffffff81fee480 T hubbub1_toggle_watermark_change_req +ffffffff81fee510 T hubbub1_soft_reset +ffffffff81fee550 T hubbub1_construct +ffffffff81fee5b0 t hubbub1_get_dcc_compression_cap +ffffffff81fee7d0 t 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hubp1_in_blank +ffffffff81ff2c10 T hubp1_soft_reset +ffffffff81ff2c50 T hubp1_set_flip_int +ffffffff81ff2ca0 T hubp1_init +ffffffff81ff2cd0 T dcn10_hubp_construct +ffffffff81ff2d30 t hubp1_setup +ffffffff81ff2df0 t hubp1_setup_interdependent +ffffffff81ff3160 t hubp1_set_vm_system_aperture_settings +ffffffff81ff3380 t hubp1_set_vm_context0_settings +ffffffff81ff3660 t hubp1_set_hubp_blank_en +ffffffff81ff36a0 t hubp1_disconnect +ffffffff81ff3730 t hubp1_disable_control +ffffffff81ff3770 t hubp1_get_underflow_status +ffffffff81ff37e0 t hubp1_wait_pipe_read_start +ffffffff81ff4000 T dcn10_lock_all_pipes +ffffffff81ff40f0 T dcn10_log_hw_state +ffffffff81ff5cf0 T dcn10_did_underflow_occur +ffffffff81ff5d90 T dcn10_enable_power_gating_plane +ffffffff81ff5f30 T dcn10_disable_vga +ffffffff81ff6110 T dcn10_dpp_pg_control +ffffffff81ff6360 T dcn10_hubp_pg_control +ffffffff81ff65b0 T dcn10_bios_golden_init +ffffffff81ff6710 T dcn10_enable_stream_timing +ffffffff81ff6b00 T dcn10_verify_allow_pstate_change_high +ffffffff81ff6e50 T dcn10_plane_atomic_disconnect +ffffffff81ff6f70 T dcn10_plane_atomic_power_down +ffffffff81ff70b0 T dcn10_plane_atomic_disable +ffffffff81ff7200 T dcn10_disable_plane +ffffffff81ff73b0 T dcn10_init_pipes +ffffffff81ff7aa0 T dcn10_init_hw +ffffffff81ff8090 T dcn10_power_down_on_boot +ffffffff81ff8230 T dcn10_reset_hw_ctx_wrap +ffffffff81ff8540 T dcn10_update_plane_addr +ffffffff81ff8660 T dcn10_set_input_transfer_func +ffffffff81ff87c0 T dcn10_set_output_transfer_func +ffffffff81ff8880 T dcn10_pipe_control_lock +ffffffff81ff8940 T dcn10_cursor_lock +ffffffff81ff8b00 T dcn10_enable_vblanks_synchronization +ffffffff81ff9280 T dcn10_enable_timing_synchronization +ffffffff81ff9640 T dcn10_enable_per_frame_crtc_position_reset +ffffffff81ff9820 T dcn10_program_gamut_remap +ffffffff81ff9a20 T dcn10_program_output_csc +ffffffff81ff9b50 T dcn10_update_visual_confirm_color +ffffffff81ff9c40 T dcn10_update_mpcc +ffffffff81ff9eb0 T dcn10_blank_pixel_data +ffffffff81ff9ff0 T dcn10_set_hdr_multiplier +ffffffff81ffa080 T dcn10_program_pipe +ffffffff81ffac40 T dcn10_wait_for_pending_cleared +ffffffff81ffad40 T dcn10_post_unlock_program_front_end +ffffffff81ffafe0 T dcn10_prepare_bandwidth +ffffffff81ffb190 T dcn10_optimize_bandwidth +ffffffff81ffb330 T dcn10_set_drr +ffffffff81ffb430 T dcn10_get_position +ffffffff81ffb4b0 T dcn10_set_static_screen_control +ffffffff81ffb550 T dcn10_setup_stereo +ffffffff81ffb6b0 T dcn10_wait_for_mpcc_disconnect +ffffffff81ffb850 T dcn10_dummy_display_power_gating +ffffffff81ffb880 T dcn10_update_pending_status +ffffffff81ffb9b0 T dcn10_update_dchub +ffffffff81ffb9e0 T dcn10_set_cursor_position +ffffffff81ffbf20 T dcn10_set_cursor_attribute +ffffffff81ffbf70 T dcn10_set_cursor_sdr_white_level +ffffffff81ffc040 T dcn10_get_vupdate_offset_from_vsync +ffffffff81ffc0d0 T dcn10_calc_vupdate_position +ffffffff81ffc160 T dcn10_setup_periodic_interrupt +ffffffff81ffc270 T dcn10_setup_vupdate_interrupt +ffffffff81ffc320 T dcn10_unblank_stream +ffffffff81ffc420 T dcn10_send_immediate_sdp_message +ffffffff81ffc480 T dcn10_set_clock +ffffffff81ffc580 T dcn10_get_clock +ffffffff81ffc5e0 T dcn10_get_dcc_en_bits +ffffffff81ffd000 T snprintf_count +ffffffff81ffd080 T dcn10_clear_status_bits +ffffffff81ffd230 T dcn10_get_hw_state +ffffffff81fff000 T dcn10_hw_sequencer_construct +ffffffff82000000 T dcn10_ipp_construct +ffffffff82000050 T dcn20_ipp_construct +ffffffff820000a0 t dcn10_ipp_destroy +ffffffff82001000 T dcn10_link_encoder_set_dp_phy_pattern_training_pattern +ffffffff820010b0 T dcn10_get_dig_frontend +ffffffff82001170 T enc1_configure_encoder +ffffffff820011f0 T dcn10_psr_program_dp_dphy_fast_training +ffffffff82001270 T dcn10_psr_program_secondary_packet +ffffffff820012f0 T dcn10_is_dig_enabled +ffffffff82001350 T dcn10_link_encoder_validate_dvi_output +ffffffff82001400 T dcn10_link_encoder_validate_dp_output +ffffffff82001440 T dcn10_link_encoder_construct +ffffffff82001630 T dcn10_link_encoder_validate_output_with_stream +ffffffff82001820 T dcn10_link_encoder_hw_init +ffffffff82001a20 T dcn10_aux_initialize +ffffffff82001ab0 T dcn10_link_encoder_destroy +ffffffff82001b00 T dcn10_link_encoder_setup +ffffffff82001c40 T dcn10_link_encoder_enable_tmds_output +ffffffff82001d30 T dcn10_link_encoder_enable_tmds_output_with_clk_pattern_wa +ffffffff82001e50 T dcn10_link_encoder_enable_dp_output +ffffffff82001fd0 T dcn10_link_encoder_enable_dp_mst_output +ffffffff82002150 T dcn10_link_encoder_disable_output +ffffffff82002330 T dcn10_link_encoder_dp_set_lane_settings +ffffffff820024d0 T dcn10_link_encoder_dp_set_phy_pattern +ffffffff82002be0 t set_dp_phy_pattern_hbr2_compliance_cp2520_2 +ffffffff82002de0 T dcn10_link_encoder_update_mst_stream_allocation_table +ffffffff820030c0 T dcn10_link_encoder_connect_dig_be_to_fe +ffffffff820031f0 T dcn10_link_encoder_enable_hpd +ffffffff82003230 T dcn10_link_encoder_disable_hpd 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opp1_program_stereo +ffffffff82006970 T opp1_pipe_clock_control +ffffffff820069b0 T opp1_destroy +ffffffff82006a00 T dcn10_opp_construct +ffffffff82007000 T optc1_program_global_sync +ffffffff82007150 T optc1_setup_vertical_interrupt0 +ffffffff820071e0 T optc1_setup_vertical_interrupt1 +ffffffff82007250 T optc1_setup_vertical_interrupt2 +ffffffff820072c0 T optc1_program_timing +ffffffff82007970 T optc1_is_two_pixels_per_containter +ffffffff820079c0 T optc1_set_vtg_params +ffffffff82007b00 T optc1_set_blank_data_double_buffer +ffffffff82007b40 T optc1_set_timing_double_buffer +ffffffff82007b80 T optc1_set_blank +ffffffff82007c50 T optc1_is_blanked +ffffffff82007cd0 T optc1_enable_optc_clock +ffffffff82007ef0 T optc1_disable_crtc +ffffffff82007fe0 T optc1_program_blank_color +ffffffff82008090 T optc1_validate_timing +ffffffff82008190 T optc1_get_vblank_counter +ffffffff820081f0 T optc1_lock +ffffffff820082d0 T optc1_unlock +ffffffff82008330 T optc1_get_position +ffffffff820083b0 T optc1_is_counter_moving +ffffffff82008420 T optc1_did_triggered_reset_occur +ffffffff820084b0 T optc1_disable_reset_trigger +ffffffff82008570 T optc1_enable_reset_trigger +ffffffff82008680 T optc1_enable_crtc_reset +ffffffff820087e0 T optc1_wait_for_state +ffffffff820088a0 T optc1_set_early_control +ffffffff820088d0 T optc1_set_static_screen_control +ffffffff82008970 T optc1_set_drr +ffffffff82008ba0 T optc1_set_vtotal_min_max +ffffffff82008c40 T optc1_get_crtc_scanoutpos +ffffffff82008d40 T optc1_program_stereo +ffffffff82008f40 T optc1_is_stereo_left_eye +ffffffff82008fb0 T optc1_get_hw_timing +ffffffff820090c0 T optc1_read_otg_state +ffffffff820093d0 T optc1_get_otg_active_size +ffffffff820094e0 T optc1_clear_optc_underflow +ffffffff82009520 T optc1_tg_init +ffffffff820095d0 T optc1_is_tg_enabled +ffffffff82009630 T optc1_is_optc_underflow_occurred +ffffffff820096a0 T optc1_configure_crc +ffffffff82009930 T optc1_get_crc +ffffffff82009a30 T dcn10_timing_generator_init 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hubbub2_wm_read_state +ffffffff8201fc70 T hubbub2_get_dchub_ref_freq +ffffffff8201fd50 T hubbub2_read_state +ffffffff8201fea0 T hubbub2_construct +ffffffff8201fef0 t hubbub2_program_watermarks +ffffffff82021000 T hubp2_set_vm_system_aperture_settings +ffffffff820211e0 T hubp2_program_deadline +ffffffff82021930 T hubp2_vready_at_or_After_vsync +ffffffff820219d0 T hubp2_setup_interdependent +ffffffff82021e30 T hubp2_program_size +ffffffff82021fc0 T hubp2_program_rotation +ffffffff82022130 T hubp2_dcc_control +ffffffff820221f0 T hubp2_program_pixel_format +ffffffff820227b0 T hubp2_program_surface_config +ffffffff820229f0 T hubp2_get_lines_per_chunk +ffffffff82022ab0 T hubp2_cursor_set_attributes +ffffffff82022e70 T hubp2_dmdata_set_attributes +ffffffff82023240 T hubp2_dmdata_load +ffffffff820232d0 T hubp2_dmdata_status_done +ffffffff82023340 T hubp2_program_surface_flip_and_addr +ffffffff82023a90 T hubp2_enable_triplebuffer +ffffffff82023b50 T hubp2_is_triplebuffer_enabled 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dcn20_disable_stream_gating +ffffffff8202ba60 T dcn20_enable_stream_gating +ffffffff8202bb00 T dcn20_set_dmdata_attributes +ffffffff8202bbc0 T dcn20_init_vm_ctx +ffffffff8202bc80 T dcn20_init_sys_ctx +ffffffff8202bd20 T dcn20_update_plane_addr +ffffffff8202be60 T dcn20_unblank_stream +ffffffff8202bfe0 T dcn20_setup_vupdate_interrupt +ffffffff8202c040 T dcn20_reset_hw_ctx_wrap +ffffffff8202c3e0 T dcn20_update_visual_confirm_color +ffffffff8202c4f0 T dcn20_update_mpcc +ffffffff8202c760 T dcn20_enable_stream +ffffffff8202c920 T dcn20_program_dmdata_engine +ffffffff8202c9c0 T dcn20_fpga_init_hw +ffffffff8202cfb0 T dcn20_optimize_timing_for_fsft +ffffffff8202cff0 T dcn20_set_disp_pattern_generator +ffffffff8202e000 T dcn20_hw_sequencer_construct +ffffffff8202f000 T enc2_fec_set_enable +ffffffff8202f080 T enc2_fec_set_ready +ffffffff8202f0c0 T enc2_fec_is_active +ffffffff8202f130 T link_enc2_read_state +ffffffff8202f1e0 T dcn20_link_encoder_enable_dp_output +ffffffff8202f2e0 T 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hubbub3_program_watermarks +ffffffff820662d0 T hubbub3_dcc_support_swizzle +ffffffff82066390 T hubbub3_get_dcc_compression_cap +ffffffff82066570 T hubbub3_force_wm_propagate_to_pipes +ffffffff82066620 T hubbub3_force_pstate_change_control +ffffffff820666a0 T hubbub3_init_watermarks +ffffffff820669e0 T hubbub3_construct +ffffffff82067000 T hubp3_set_vm_system_aperture_settings +ffffffff82067130 T hubp3_program_surface_flip_and_addr +ffffffff82067b60 T hubp3_dcc_control +ffffffff82067c20 T hubp3_dcc_control_sienna_cichlid +ffffffff82067d30 T hubp3_dmdata_set_attributes +ffffffff82067f30 T hubp3_program_surface_config +ffffffff82068230 T hubp3_read_state +ffffffff820684a0 T hubp3_setup +ffffffff82068530 T hubp3_init +ffffffff82068560 T hubp3_construct +ffffffff82069000 T dcn30_set_blend_lut +ffffffff82069060 T dcn30_set_input_transfer_func +ffffffff820691c0 T dcn30_set_output_transfer_func +ffffffff820694e0 T dcn30_update_writeback +ffffffff82069570 t dcn30_set_writeback +ffffffff82069720 T dcn30_mmhubbub_warmup +ffffffff820699d0 T dcn30_enable_writeback +ffffffff82069aa0 T dcn30_disable_writeback +ffffffff82069b80 T dcn30_program_all_writeback_pipes_in_tree +ffffffff82069e60 T dcn30_init_hw +ffffffff8206a750 T dcn30_set_avmute +ffffffff8206a7b0 T dcn30_update_info_frame +ffffffff8206a880 T dcn30_program_dmdata_engine +ffffffff8206a920 T dcn30_apply_idle_power_optimizations +ffffffff8206aea0 T dcn30_does_plane_fit_in_mall +ffffffff8206af50 T dcn30_hardware_release +ffffffff8206b060 T dcn30_set_disp_pattern_generator +ffffffff8206b0d0 T dcn30_prepare_bandwidth +ffffffff8206c000 T dcn30_hw_sequencer_construct +ffffffff8206d000 t mmhubbub3_warmup_mcif +ffffffff8206d210 t mmhubbub3_config_mcif_buf +ffffffff8206d6b0 t mmhubbub3_config_mcif_arb +ffffffff8206daf0 T dcn30_mmhubbub_construct +ffffffff8206e000 T mpc3_is_dwb_idle +ffffffff8206e070 T mpc3_set_dwb_mux +ffffffff8206e0e0 T mpc3_disable_dwb_mux +ffffffff8206e160 T mpc3_set_out_rate_control +ffffffff8206e270 T mpc3_get_ogam_current +ffffffff8206e310 T mpc3_power_on_ogam_lut +ffffffff8206e3e0 T mpc3_set_output_gamma +ffffffff8206ef80 T mpc3_set_denorm +ffffffff8206eff0 T mpc3_set_denorm_clamp +ffffffff8206f140 T mpc3_program_shaper +ffffffff820713a0 t mpc3_power_on_shaper_3dlut +ffffffff82071720 T mpc3_init_mpcc +ffffffff82071790 T mpc3_set_gamut_remap +ffffffff820719d0 T mpc3_program_3dlut +ffffffff82072150 t mpc3_set3dlut_ram12 +ffffffff82072330 T mpc3_set_output_csc +ffffffff820724a0 T mpc3_set_ocsc_default +ffffffff82072610 T mpc3_set_rmu_mux +ffffffff820726b0 T mpc3_get_rmu_mux_status +ffffffff82072750 T mpcc3_acquire_rmu +ffffffff820728b0 t mpcc3_release_rmu +ffffffff82072a20 t mpc3_set_mpc_mem_lp_mode +ffffffff82072bb0 T dcn30_mpc_construct +ffffffff82073000 T optc3_triplebuffer_lock +ffffffff82073120 T optc3_lock_doublebuffer_enable +ffffffff820733b0 T optc3_lock_doublebuffer_disable +ffffffff820734c0 T optc3_lock +ffffffff82073590 T optc3_set_out_mux +ffffffff820735d0 T optc3_program_blank_color +ffffffff82073700 T optc3_set_drr_trigger_window +ffffffff82073790 T optc3_set_vtotal_change_limit +ffffffff82073800 T optc3_set_dsc_config +ffffffff82073850 T optc3_set_odm_bypass +ffffffff820739c0 T optc3_wait_drr_doublebuffer_pending_clear +ffffffff82073a30 T optc3_set_vtotal_min_max +ffffffff82073a40 T optc3_tg_init +ffffffff82073a90 T dcn30_timing_generator_init +ffffffff82073b00 t optc3_set_odm_combine +ffffffff82074000 T dcn30_add_stream_to_ctx +ffffffff82074010 T dcn30_populate_dml_pipes_from_context +ffffffff82074100 T dcn30_populate_dml_writeback_from_context +ffffffff82074160 T dcn30_calc_max_scaled_time +ffffffff820741b0 T dcn30_set_mcif_arb_params +ffffffff82074320 T dcn30_acquire_post_bldn_3dlut +ffffffff82074490 T dcn30_release_post_bldn_3dlut +ffffffff82074530 T dcn30_internal_validate_bw +ffffffff82075300 t dcn30_split_stream_for_mpc_or_odm +ffffffff82075620 T dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch +ffffffff82075740 T dcn30_setup_mclk_switch_using_fw_based_vblank_stretch +ffffffff820757e0 T dcn30_update_soc_for_wm_a +ffffffff82075830 T dcn30_calculate_wm_and_dlg +ffffffff820758a0 T dcn30_validate_bandwidth +ffffffff82075cd0 T dcn30_update_bw_bounding_box +ffffffff820764b0 T dcn30_create_resource_pool +ffffffff82077a70 t dcn30_resource_destruct +ffffffff82077fe0 t dcn30_destroy_resource_pool +ffffffff82078040 t dcn30_panel_cntl_create +ffffffff820780d0 t dcn30_link_encoder_create +ffffffff82078180 t read_dce_straps +ffffffff820781a0 t dcn30_create_audio +ffffffff820781d0 t dcn30_stream_encoder_create +ffffffff82078350 t dcn30_hwseq_create +ffffffff82079000 T vpg3_update_generic_info_packet +ffffffff820799a0 T vpg3_construct +ffffffff8207a000 T dccg301_create +ffffffff8207b000 T dcn301_link_encoder_construct +ffffffff8207c000 T hubbub301_construct +ffffffff8207d000 T dcn301_hw_sequencer_construct +ffffffff8207e000 T dcn301_panel_cntl_construct +ffffffff8207e050 t dcn301_panel_cntl_destroy +ffffffff8207e0a0 t dcn301_panel_cntl_hw_init +ffffffff8207e2a0 t dcn301_is_panel_backlight_on +ffffffff8207e300 t dcn301_is_panel_powered_on +ffffffff8207e3b0 t dcn301_store_backlight_level +ffffffff8207e450 t dcn301_get_16_bit_backlight_from_pwm +ffffffff8207f000 T dcn301_create_resource_pool +ffffffff82080590 t dcn301_destruct +ffffffff82080ad0 t dcn301_destroy_resource_pool +ffffffff82080b30 t dcn301_panel_cntl_create +ffffffff82080bc0 t dcn301_link_encoder_create +ffffffff82080c70 t dcn301_calculate_wm_and_dlg +ffffffff82080ce0 t read_dce_straps +ffffffff82080d00 t dcn301_create_audio +ffffffff82080d30 t dcn301_stream_encoder_create +ffffffff82080eb0 t dcn301_hwseq_create +ffffffff82081000 T dcn302_dpp_pg_control +ffffffff820812a0 T dcn302_hubp_pg_control +ffffffff82081550 T dcn302_dsc_pg_control +ffffffff82082000 T dcn302_hw_sequencer_construct +ffffffff82083000 T dcn302_update_bw_bounding_box +ffffffff82083050 T dcn302_create_resource_pool +ffffffff820843e0 t dcn302_resource_destruct +ffffffff820848f0 t dcn302_destroy_resource_pool +ffffffff82084940 t dcn302_panel_cntl_create +ffffffff820849d0 t dcn302_link_encoder_create +ffffffff82084a80 t read_dce_straps +ffffffff82084aa0 t dcn302_create_audio +ffffffff82084ad0 t dcn302_stream_encoder_create +ffffffff82084c50 t dcn302_hwseq_create +ffffffff82085000 T dcn303_dpp_pg_control +ffffffff82085030 T dcn303_hubp_pg_control +ffffffff82085060 T dcn303_dsc_pg_control +ffffffff82085090 T dcn303_enable_power_gating_plane +ffffffff82086000 T dcn303_hw_sequencer_construct +ffffffff82087000 T dcn303_update_bw_bounding_box +ffffffff82087050 T dcn303_create_resource_pool +ffffffff82088290 t dcn303_resource_destruct +ffffffff820887b0 t dcn303_destroy_resource_pool +ffffffff82088800 t dcn303_panel_cntl_create +ffffffff82088890 t dcn303_link_encoder_create +ffffffff82088940 t read_dce_straps +ffffffff82088960 t dcn303_create_audio +ffffffff82088990 t dcn303_stream_encoder_create +ffffffff82088b10 t dcn303_hwseq_create +ffffffff82089000 T afmt31_powerdown +ffffffff82089080 T afmt31_poweron +ffffffff82089100 T afmt31_construct +ffffffff8208a000 T apg31_construct +ffffffff8208a050 t apg31_se_audio_setup +ffffffff8208a160 t apg31_audio_mute_control +ffffffff8208a1a0 t apg31_enable +ffffffff8208a2b0 t apg31_disable +ffffffff8208b000 T dccg31_update_dpp_dto +ffffffff8208b1b0 T dccg31_set_dpstreamclk +ffffffff8208b330 t dccg31_disable_dpstreamclk +ffffffff8208b480 T dccg31_enable_symclk32_se +ffffffff8208b770 T dccg31_disable_symclk32_se +ffffffff8208ba40 T dccg31_enable_symclk32_le +ffffffff8208bc10 T dccg31_disable_symclk32_le +ffffffff8208bdb0 T dccg31_disable_dscclk +ffffffff8208bf70 T dccg31_enable_dscclk +ffffffff8208c140 T dccg31_set_physymclk +ffffffff8208c650 T dccg31_set_dtbclk_dto +ffffffff8208c900 T dccg31_set_audio_dtbclk_dto +ffffffff8208ca00 T dccg31_get_dccg_ref_freq +ffffffff8208ca30 T dccg31_set_dispclk_change_mode +ffffffff8208ca80 T dccg31_init +ffffffff8208cfe0 T dccg31_otg_add_pixel +ffffffff8208d020 T dccg31_otg_drop_pixel +ffffffff8208d060 T dccg31_create +ffffffff8208e000 T dcn31_link_encoder_set_dio_phy_mux +ffffffff8208e380 T dcn31_link_encoder_construct +ffffffff8208e580 T dcn31_link_encoder_construct_minimal +ffffffff8208e600 T dcn31_link_encoder_enable_dp_output +ffffffff8208e840 T dcn31_link_encoder_enable_dp_mst_output +ffffffff8208ea80 T dcn31_link_encoder_disable_output +ffffffff8208ed10 T dcn31_link_encoder_is_in_alt_mode +ffffffff8208ee50 T dcn31_link_encoder_get_max_link_cap +ffffffff8208efc0 t enc31_hw_init +ffffffff82090000 T dcn31_hpo_dp_link_enc_enable +ffffffff82090150 T dcn31_hpo_dp_link_enc_disable +ffffffff820901c0 T dcn31_hpo_dp_link_enc_set_link_test_pattern +ffffffff82090af0 T dcn31_hpo_dp_link_enc_update_stream_allocation_table +ffffffff82090d80 T dcn31_hpo_dp_link_enc_set_throttled_vcp_size +ffffffff82091020 T dcn31_hpo_dp_link_enc_read_state +ffffffff820912d0 T dcn31_hpo_dp_link_enc_enable_dp_output +ffffffff820913d0 T dcn31_hpo_dp_link_enc_disable_output +ffffffff82091500 T dcn31_hpo_dp_link_enc_set_ffe +ffffffff820915f0 T hpo_dp_link_encoder31_construct +ffffffff82091640 t dcn31_hpo_dp_link_enc_is_in_alt_mode +ffffffff82092000 T dcn31_hpo_dp_stream_encoder_construct +ffffffff82092070 t dcn31_hpo_dp_stream_enc_enable_stream +ffffffff820921b0 t dcn31_hpo_dp_stream_enc_dp_unblank +ffffffff82092460 t dcn31_hpo_dp_stream_enc_dp_blank +ffffffff82092560 t dcn31_hpo_dp_stream_enc_disable +ffffffff820925d0 t dcn31_hpo_dp_stream_enc_set_stream_attribute +ffffffff82092e80 t dcn31_hpo_dp_stream_enc_update_dp_info_packets +ffffffff82093030 t dcn31_hpo_dp_stream_enc_stop_dp_info_packets +ffffffff820931c0 t dcn31_hpo_dp_stream_enc_set_dsc_pps_info_packet +ffffffff82093460 t dcn31_hpo_dp_stream_enc_map_stream_to_link +ffffffff82093560 t dcn31_hpo_dp_stream_enc_mute_control +ffffffff820935d0 t dcn31_hpo_dp_stream_enc_audio_setup +ffffffff82093680 t dcn31_hpo_dp_stream_enc_audio_enable +ffffffff82093750 t dcn31_hpo_dp_stream_enc_audio_disable +ffffffff82093900 t dcn31_hpo_dp_stream_enc_read_state +ffffffff82093a90 t dcn31_set_hblank_min_symbol_width +ffffffff82094000 T hubbub31_init_dchub_sys_ctx +ffffffff820941f0 T hubbub31_construct +ffffffff82094280 t hubbub31_get_dcc_compression_cap +ffffffff82094460 t hubbub31_get_dchub_ref_freq +ffffffff82094530 t hubbub31_program_watermarks +ffffffff82095de0 t hubbub31_verify_allow_pstate_change_high +ffffffff82095fa0 t dcn31_program_det_size +ffffffff82096150 t dcn31_program_compbuf_size +ffffffff820963d0 t dcn31_init_crb +ffffffff82097000 T hubp31_set_unbounded_requesting +ffffffff82097090 T hubp31_soft_reset +ffffffff820970e0 T hubp31_construct +ffffffff82097150 t hubp31_program_extended_blank +ffffffff82098000 T dcn31_init_hw +ffffffff82098960 T dcn31_dsc_pg_control +ffffffff82098ca0 T dcn31_enable_power_gating_plane +ffffffff82098f00 T dcn31_update_info_frame +ffffffff82098fd0 T dcn31_z10_save_init +ffffffff82099090 T dcn31_z10_restore +ffffffff82099170 T dcn31_hubp_pg_control +ffffffff82099480 T dcn31_init_sys_ctx +ffffffff82099530 T dcn31_reset_hw_ctx_wrap +ffffffff820998a0 T dcn31_setup_hpo_hw_control +ffffffff8209a000 T dcn31_hw_sequencer_construct +ffffffff8209b000 T optc31_immediate_disable_crtc +ffffffff8209b0f0 T optc31_set_drr +ffffffff8209b300 T optc3_init_odm +ffffffff8209b470 T dcn31_timing_generator_init +ffffffff8209b4e0 t optc31_enable_crtc +ffffffff8209b5e0 t optc31_disable_crtc +ffffffff8209b6c0 t optc31_set_odm_combine +ffffffff8209c000 T dcn31_panel_cntl_construct +ffffffff8209c040 t dcn31_panel_cntl_destroy +ffffffff8209c090 t dcn31_panel_cntl_hw_init +ffffffff8209c180 t dcn31_is_panel_backlight_on +ffffffff8209c220 t dcn31_is_panel_powered_on +ffffffff8209c2c0 t dcn31_store_backlight_level +ffffffff8209c380 t dcn31_get_16_bit_backlight_from_pwm +ffffffff8209d000 T dcn31_populate_dml_pipes_from_context +ffffffff8209d350 T dcn31_calculate_wm_and_dlg +ffffffff8209d3c0 T dcn31_populate_dml_writeback_from_context +ffffffff8209d420 T dcn31_set_mcif_arb_params +ffffffff8209d480 T dcn31_validate_bandwidth +ffffffff8209d860 T dcn31_create_resource_pool +ffffffff8209ec00 t dcn31_resource_destruct +ffffffff8209f260 t dcn31_destroy_resource_pool +ffffffff8209f2c0 t dcn31_panel_cntl_create +ffffffff8209f330 t dcn31_link_encoder_create +ffffffff8209f3e0 t dcn31_link_enc_create_minimal +ffffffff8209f480 t dcn31_get_panel_config_defaults +ffffffff8209f4f0 t read_dce_straps +ffffffff8209f510 t dcn31_create_audio +ffffffff8209f540 t dcn31_stream_encoder_create +ffffffff8209f6c0 t dcn31_hpo_dp_stream_encoder_create +ffffffff8209f880 t dcn31_hpo_dp_link_encoder_create +ffffffff8209f910 t dcn31_hwseq_create +ffffffff820a0000 T vpg31_powerdown +ffffffff820a0090 T vpg31_poweron +ffffffff820a0120 T vpg31_construct +ffffffff820a1000 T dccg314_create +ffffffff820a10b0 t dccg314_set_dpstreamclk +ffffffff820a1480 t dccg314_set_dtbclk_dto +ffffffff820a1670 t dccg314_set_pixel_rate_div +ffffffff820a19e0 t dccg314_set_valid_pixel_rate +ffffffff820a2000 T dcn314_dio_stream_encoder_construct +ffffffff820a2070 t enc314_stream_encoder_hdmi_set_stream_attribute +ffffffff820a2660 t enc314_stream_encoder_dvi_set_stream_attribute +ffffffff820a2860 t enc314_stream_encoder_dp_blank +ffffffff820a28b0 t enc314_stream_encoder_dp_unblank +ffffffff820a2bf0 t enc314_read_state +ffffffff820a2d50 t enc314_dp_set_dsc_config +ffffffff820a2da0 t enc314_dp_set_odm_combine +ffffffff820a2de0 t enc314_set_dig_input_mode +ffffffff820a2e30 t enc314_enable_fifo +ffffffff820a2ed0 t enc314_disable_fifo +ffffffff820a2f10 t enc314_reset_fifo +ffffffff820a4000 T dcn314_update_odm +ffffffff820a4610 T dcn314_dsc_pg_control +ffffffff820a49d0 T dcn314_enable_power_gating_plane +ffffffff820a4c60 T dcn314_calculate_dccg_k1_k2_values +ffffffff820a4de0 T dcn314_set_pixels_per_cycle +ffffffff820a4ed0 T dcn314_hubp_pg_control +ffffffff820a5000 T dcn314_hw_sequencer_construct +ffffffff820a6000 T dcn314_timing_generator_init +ffffffff820a6070 t optc314_enable_crtc +ffffffff820a6170 t optc314_disable_crtc +ffffffff820a6240 t optc314_phantom_crtc_post_enable +ffffffff820a6300 t optc314_set_odm_bypass +ffffffff820a6470 t optc314_set_odm_combine +ffffffff820a6770 t optc314_set_h_timing_div_manual_mode +ffffffff820a7000 T dcn314_create_resource_pool +ffffffff820a82d0 t dcn314_resource_destruct +ffffffff820a8930 t dcn314_destroy_resource_pool +ffffffff820a8990 t dcn31_panel_cntl_create +ffffffff820a8a00 t dcn31_link_encoder_create +ffffffff820a8ab0 t dcn31_link_enc_create_minimal +ffffffff820a8b50 t dcn314_populate_dml_pipes_from_context +ffffffff820a8be0 t dcn314_update_bw_bounding_box +ffffffff820a8c30 t dcn314_get_panel_config_defaults +ffffffff820a8ca0 t read_dce_straps +ffffffff820a8cc0 t dcn31_create_audio +ffffffff820a8cf0 t dcn314_stream_encoder_create +ffffffff820a8e70 t dcn31_hpo_dp_stream_encoder_create +ffffffff820a9030 t dcn31_hpo_dp_link_encoder_create +ffffffff820a90c0 t dcn314_hwseq_create +ffffffff820aa000 T dcn315_create_resource_pool +ffffffff820ab260 t dcn315_resource_destruct +ffffffff820ab8c0 t dcn315_destroy_resource_pool +ffffffff820ab920 t dcn31_panel_cntl_create +ffffffff820ab990 t dcn31_link_encoder_create +ffffffff820aba40 t dcn31_link_enc_create_minimal +ffffffff820abae0 t dcn315_populate_dml_pipes_from_context +ffffffff820abe20 t dcn315_get_panel_config_defaults +ffffffff820abe90 t read_dce_straps +ffffffff820abeb0 t dcn31_create_audio +ffffffff820abee0 t dcn315_stream_encoder_create +ffffffff820ac060 t dcn31_hpo_dp_stream_encoder_create +ffffffff820ac220 t dcn31_hpo_dp_link_encoder_create +ffffffff820ac2b0 t dcn31_hwseq_create +ffffffff820ad000 T dcn316_create_resource_pool +ffffffff820ae2a0 t dcn316_resource_destruct +ffffffff820ae900 t dcn316_destroy_resource_pool +ffffffff820ae960 t dcn31_panel_cntl_create +ffffffff820ae9d0 t dcn31_link_encoder_create +ffffffff820aea80 t dcn31_link_enc_create_minimal +ffffffff820aeb20 t dcn316_populate_dml_pipes_from_context +ffffffff820aee40 t dcn316_get_panel_config_defaults +ffffffff820aeeb0 t read_dce_straps +ffffffff820aeed0 t dcn31_create_audio +ffffffff820aef00 t dcn316_stream_encoder_create +ffffffff820af080 t dcn31_hpo_dp_stream_encoder_create +ffffffff820af240 t dcn31_hpo_dp_link_encoder_create +ffffffff820af2d0 t dcn31_hwseq_create +ffffffff820b0000 T dccg32_create +ffffffff820b00b0 t dccg32_get_dccg_ref_freq +ffffffff820b00e0 t dccg32_otg_add_pixel +ffffffff820b0120 t dccg32_otg_drop_pixel +ffffffff820b0160 t dccg32_set_dpstreamclk +ffffffff820b0530 t dccg32_set_dtbclk_dto +ffffffff820b0720 t dccg32_set_pixel_rate_div +ffffffff820b0a90 t dccg32_set_valid_pixel_rate +ffffffff820b1000 T enc32_hw_init +ffffffff820b1090 T dcn32_link_encoder_enable_dp_output +ffffffff820b10e0 T dcn32_link_encoder_construct +ffffffff820b12c0 t dcn32_link_encoder_is_in_alt_mode +ffffffff820b1340 t dcn32_link_encoder_get_max_link_cap +ffffffff820b2000 T dcn32_dio_stream_encoder_construct +ffffffff820b2070 t enc32_stream_encoder_hdmi_set_stream_attribute +ffffffff820b25a0 t enc32_stream_encoder_dvi_set_stream_attribute +ffffffff820b2720 t enc32_stream_encoder_dp_unblank +ffffffff820b2bd0 t enc32_read_state +ffffffff820b2d30 t enc32_dp_set_dsc_config +ffffffff820b2d80 t enc32_dp_set_odm_combine +ffffffff820b2dc0 t enc32_set_dig_input_mode +ffffffff820b3000 T dpp32_construct +ffffffff820b3060 t dscl32_calc_lb_num_partitions +ffffffff820b4000 T hpo_dp_link_encoder32_construct +ffffffff820b4050 t dcn32_hpo_dp_link_enc_is_in_alt_mode +ffffffff820b5000 T dcn32_program_det_size +ffffffff820b51a0 T hubbub32_program_urgent_watermarks +ffffffff820b5900 T hubbub32_program_stutter_watermarks +ffffffff820b5d50 T hubbub32_program_pstate_watermarks +ffffffff820b61d0 T hubbub32_program_usr_watermarks +ffffffff820b6420 T hubbub32_force_usr_retraining_allow +ffffffff820b64a0 T hubbub32_force_wm_propagate_to_pipes +ffffffff820b6540 T hubbub32_construct +ffffffff820b65c0 t hubbub32_wm_read_state +ffffffff820b6a30 t hubbub32_program_watermarks +ffffffff820b6b40 t hubbub32_init_watermarks +ffffffff820b6f80 t dcn32_program_compbuf_size +ffffffff820b7200 t dcn32_init_crb +ffffffff820b8000 T hubp32_update_force_pstate_disallow +ffffffff820b8090 T hubp32_update_mall_sel +ffffffff820b8120 T hubp32_prepare_subvp_buffering +ffffffff820b81b0 T hubp32_phantom_hubp_post_enable +ffffffff820b82c0 T hubp32_cursor_set_attributes +ffffffff820b8580 T hubp32_construct +ffffffff820b9000 T dcn32_dsc_pg_control +ffffffff820b9310 T dcn32_enable_power_gating_plane +ffffffff820b94b0 T dcn32_hubp_pg_control +ffffffff820b9720 T dcn32_apply_idle_power_optimizations +ffffffff820b9980 t dcn32_calculate_cab_allocation +ffffffff820b9d30 T dcn32_commit_subvp_config +ffffffff820b9dd0 T dcn32_subvp_pipe_control_lock +ffffffff820b9fa0 T dcn32_set_mcm_luts +ffffffff820ba130 T dcn32_set_input_transfer_func +ffffffff820ba270 T dcn32_set_output_transfer_func +ffffffff820ba470 T dcn32_subvp_update_force_pstate +ffffffff820ba5d0 T dcn32_update_mall_sel +ffffffff820ba750 T dcn32_program_mall_pipe_config +ffffffff820ba830 T dcn32_init_hw +ffffffff820bb010 T dcn32_update_odm +ffffffff820bb620 T dcn32_calculate_dccg_k1_k2_values +ffffffff820bb820 T dcn32_is_dp_dig_pixel_rate_div_policy +ffffffff820bb8b0 T dcn32_set_pixels_per_cycle +ffffffff820bb9f0 T dcn32_unblank_stream +ffffffff820bbbc0 T dcn32_disable_link_output +ffffffff820bbe50 T dcn32_update_phantom_vp_position +ffffffff820bbf70 T dcn32_dsc_pg_status +ffffffff820bc050 T dcn32_update_dsc_pg +ffffffff820bd000 T dcn32_hw_sequencer_init_functions +ffffffff820be000 t mmhubbub32_warmup_mcif +ffffffff820be210 t mmhubbub32_config_mcif_buf +ffffffff820be6b0 t mmhubbub32_config_mcif_arb +ffffffff820beac0 T dcn32_mmhubbub_construct +ffffffff820bf000 t mpc32_mpc_init +ffffffff820bf220 t mpc32_program_post1dlut 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+ffffffff820c5140 t dcn32_resource_construct +ffffffff820d15b0 T dcn32_acquire_idle_pipe_for_head_pipe_in_layer +ffffffff820d17f0 T dcn32_calc_num_avail_chans_for_mall +ffffffff820d1860 t dcn32_mpc_create +ffffffff820d6220 t dcn32_resource_destruct +ffffffff820d6890 t dcn32_destroy_resource_pool +ffffffff820d68f0 t dcn32_link_encoder_create +ffffffff820d7850 t dcn32_update_bw_bounding_box +ffffffff820d78a0 t read_dce_straps +ffffffff820d78d0 t dcn32_create_audio +ffffffff820d7c10 t dcn32_stream_encoder_create +ffffffff820d9a80 t dcn32_hpo_dp_stream_encoder_create +ffffffff820da760 t dcn32_hpo_dp_link_encoder_create +ffffffff820dabe0 t dcn32_hwseq_create +ffffffff820db070 t dcn32_vpg_create +ffffffff820dc000 T dcn32_helper_calculate_num_ways_for_subvp +ffffffff820dc1e0 T dcn32_merge_pipes_for_subvp +ffffffff820dc3b0 T dcn32_all_pipes_have_stream_and_plane +ffffffff820dc440 T dcn32_subvp_in_use +ffffffff820dc4d0 T dcn32_mpo_in_use +ffffffff820dc530 T dcn32_any_surfaces_rotated +ffffffff820dc5c0 T dcn32_determine_det_override +ffffffff820dc900 T dcn32_set_det_allocations +ffffffff820dca80 T dcn32_save_mall_state +ffffffff820dcb30 T dcn32_restore_mall_state +ffffffff820dd000 T dcn321_link_encoder_construct +ffffffff820de000 T dcn321_create_resource_pool +ffffffff820de0b0 t dcn321_resource_construct +ffffffff820ea4c0 t dcn321_mpc_create +ffffffff820eee80 t dcn321_resource_destruct +ffffffff820ef4f0 t dcn321_destroy_resource_pool +ffffffff820ef550 t dcn321_link_encoder_create +ffffffff820f04b0 t dcn321_update_bw_bounding_box +ffffffff820f0500 t read_dce_straps +ffffffff820f0530 t dcn321_create_audio +ffffffff820f0870 t dcn321_stream_encoder_create +ffffffff820f26e0 t dcn321_hpo_dp_stream_encoder_create +ffffffff820f33c0 t dcn321_hpo_dp_link_encoder_create +ffffffff820f3840 t dcn321_hwseq_create +ffffffff820f3cd0 t dcn321_vpg_create +ffffffff820f5000 T bw_int_to_fixed_nonconst +ffffffff820f5090 T bw_frc_to_fixed +ffffffff820f5260 T bw_floor2 +ffffffff820f5310 T bw_ceil2 +ffffffff820f5390 T bw_mul +ffffffff820f6000 T convert_to_custom_float_format +ffffffff820f7000 T bw_calcs_init +ffffffff820f7e30 T bw_calcs +ffffffff820f9760 t calculate_bandwidth +ffffffff82101000 T scaler_settings_calculation +ffffffff82101380 T mode_support_and_system_configuration +ffffffff82107160 T display_pipe_configuration +ffffffff821079a0 T dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation +ffffffff8210d000 T dcn_bw_mod +ffffffff8210d050 T dcn_bw_min2 +ffffffff8210d090 T dcn_bw_max +ffffffff8210d0c0 T dcn_bw_max2 +ffffffff8210d100 T dcn_bw_floor2 +ffffffff8210d1a0 T dcn_bw_floor +ffffffff8210d1d0 T dcn_bw_ceil +ffffffff8210d210 T dcn_bw_ceil2 +ffffffff8210d2c0 T dcn_bw_max3 +ffffffff8210d360 T dcn_bw_max5 +ffffffff8210d4c0 T dcn_bw_pow +ffffffff8210d550 T dcn_bw_fabs +ffffffff8210d5b0 T dcn_bw_log +ffffffff8210e000 T swizzle_mode_to_macro_tile_size +ffffffff8210e090 T dcn_validate_bandwidth +ffffffff82110330 T dcn_bw_sync_calcs_and_dml +ffffffff82110580 t dcn_bw_calc_rq_dlg_ttu +ffffffff82110f00 T dcn_find_dcfclk_suits_all +ffffffff82111360 T dcn_bw_update_from_pplib_fclks +ffffffff821114f0 T dcn_bw_update_from_pplib_dcfclks +ffffffff821115c0 T dcn_get_soc_clks +ffffffff82111640 T dcn_bw_notify_pplib_of_wm_ranges +ffffffff82112000 T dcn20_populate_dml_writeback_from_context +ffffffff82112180 T dcn20_fpu_set_wb_arb_params +ffffffff82112330 T dcn20_calculate_dlg_params +ffffffff82112b10 T dcn20_populate_dml_pipes_from_context +ffffffff82113a10 T dcn20_calculate_wm +ffffffff821141b0 T dcn20_update_bounding_box +ffffffff82114420 T dcn20_cap_soc_clocks +ffffffff821147a0 T dcn20_patch_bounding_box +ffffffff82114910 T dcn20_validate_bandwidth_fp +ffffffff82114aa0 t dcn20_validate_bandwidth_internal +ffffffff82114e80 T dcn20_fpu_set_wm_ranges +ffffffff82114f20 T dcn20_fpu_adjust_dppclk +ffffffff82114fc0 T dcn21_populate_dml_pipes_from_context +ffffffff821150b0 T dcn21_validate_bandwidth_fp +ffffffff82115b30 T dcn21_update_bw_bounding_box +ffffffff82116010 T dcn21_clk_mgr_set_bw_params_wm_table +ffffffff82116070 T dcn201_populate_dml_writeback_from_context_fpu +ffffffff82116380 t calculate_wm_set_for_vlevel +ffffffff82117000 T dml20_recalculate +ffffffff82117740 t dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation +ffffffff8211cda0 T dml20_ModeSupportAndSystemConfigurationFull +ffffffff82123d30 t TruncToValidBPP +ffffffff82123f10 t CalculateVMAndRowBytes +ffffffff821245a0 t CalculatePrefetchSourceLines +ffffffff82124760 t CalculateWriteBackDelay +ffffffff82124a30 t CalculatePrefetchSchedule +ffffffff821258f0 t CalculateFlipSchedule +ffffffff82125ca0 t adjust_ReturnBW +ffffffff82126000 T dml20v2_recalculate +ffffffff82126740 t dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation +ffffffff8212be50 T dml20v2_ModeSupportAndSystemConfigurationFull +ffffffff82132cd0 t TruncToValidBPP +ffffffff82133260 t CalculateVMAndRowBytes +ffffffff821338f0 t CalculatePrefetchSourceLines +ffffffff82133ab0 t CalculateWriteBackDelay +ffffffff82133d80 t CalculateDelayAfterScaler +ffffffff821340d0 t CalculatePrefetchSchedule +ffffffff82134e40 t CalculateFlipSchedule +ffffffff821351f0 t adjust_ReturnBW +ffffffff82136000 T dml20_rq_dlg_get_rq_reg +ffffffff82136490 t dml20_rq_dlg_get_rq_params +ffffffff82136660 T dml20_rq_dlg_get_dlg_reg +ffffffff821385a0 t get_surf_rq_param +ffffffff82138e20 t calculate_ttu_cursor +ffffffff8213a000 T dml20v2_rq_dlg_get_rq_reg +ffffffff8213a490 t dml20v2_rq_dlg_get_rq_params +ffffffff8213a660 T dml20v2_rq_dlg_get_dlg_reg +ffffffff8213c5b0 t get_surf_rq_param +ffffffff8213ce30 t calculate_ttu_cursor +ffffffff8213e000 T dml21_recalculate +ffffffff8213e700 t DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation +ffffffff821440b0 T dml21_ModeSupportAndSystemConfigurationFull +ffffffff8214a190 t TruncToValidBPP +ffffffff8214a720 t CalculateDCFCLKDeepSleep +ffffffff8214aa60 t CalculateVMAndRowBytes +ffffffff8214b2d0 t CalculatePrefetchSourceLines +ffffffff8214b490 t CalculateWriteBackDelay +ffffffff8214b760 t CalculatePrefetchSchedulePerPlane +ffffffff8214bf70 t CalculateUrgentBurstFactor +ffffffff8214c380 t CalculateFlipSchedule +ffffffff8214c870 t CalculateWatermarksAndDRAMSpeedChangeSupport +ffffffff8214d8d0 t CalculatePrefetchSchedule +ffffffff8214f000 T dml21_rq_dlg_get_rq_reg +ffffffff8214f490 t dml_rq_dlg_get_rq_params +ffffffff8214f660 T dml21_rq_dlg_get_dlg_reg +ffffffff821519c0 t get_surf_rq_param +ffffffff82152300 t calculate_ttu_cursor +ffffffff82153000 T optc3_fpu_set_vrr_m_const +ffffffff821534a0 T dcn30_fpu_populate_dml_writeback_from_context +ffffffff821537f0 T dcn30_fpu_set_mcif_arb_params +ffffffff82153960 T dcn30_fpu_update_soc_for_wm_a +ffffffff82153a10 T dcn30_fpu_calculate_wm_and_dlg +ffffffff821542f0 T dcn30_fpu_update_dram_channel_width_bytes +ffffffff82154350 T dcn30_fpu_update_max_clk +ffffffff821543f0 T dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk +ffffffff821544f0 T dcn30_fpu_update_bw_bounding_box +ffffffff821546d0 T dcn30_find_dummy_latency_index_for_fw_based_mclk_switch +ffffffff82154890 T dcn3_fpu_build_wm_range_table +ffffffff82154b70 T patch_dcn30_soc_bounding_box +ffffffff82155000 T dml30_recalculate +ffffffff82155600 t DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation +ffffffff8215bc50 T dml30_CalculateBytePerPixelAnd256BBlockSizes +ffffffff8215bec0 T dml30_CalculateWriteBackDISPCLK +ffffffff8215c040 T dml30_ModeSupportAndSystemConfigurationFull +ffffffff82163440 t CalculateSwathAndDETConfiguration +ffffffff82163ab0 t TruncToValidBPP +ffffffff82163d30 t dscceComputeDelay +ffffffff82163e70 t CalculateVMAndRowBytes +ffffffff82164520 t CalculatePrefetchSourceLines +ffffffff821646e0 t CalculateUrgentBurstFactor +ffffffff82164970 t CalculateDCFCLKDeepSleep +ffffffff82164c90 t UseMinimumDCFCLK +ffffffff82165e90 t CalculatePrefetchSchedule +ffffffff821673f0 t CalculateFlipSchedule +ffffffff821678e0 t CalculateWatermarksAndDRAMSpeedChangeSupport +ffffffff82168700 t CalculateSwathWidth +ffffffff82169000 T dml30_rq_dlg_get_rq_reg +ffffffff821694b0 t dml_rq_dlg_get_rq_params +ffffffff82169720 T dml30_rq_dlg_get_dlg_reg +ffffffff8216bed0 t get_surf_rq_param +ffffffff8216c870 t calculate_ttu_cursor +ffffffff8216d000 T dcn301_update_bw_bounding_box +ffffffff8216d320 T dcn301_fpu_set_wm_ranges +ffffffff8216d3c0 T dcn301_fpu_init_soc_bounding_box +ffffffff8216d460 T dcn301_calculate_wm_and_dlg_fp +ffffffff8216d790 t calculate_wm_set_for_vlevel +ffffffff8216e000 T dcn302_fpu_update_bw_bounding_box +ffffffff8216eac0 T dcn302_fpu_init_soc_bounding_box +ffffffff8216f000 T dcn303_fpu_update_bw_bounding_box +ffffffff8216fb00 T dcn303_fpu_init_soc_bounding_box +ffffffff82170000 T dcn31_zero_pipe_dcc_fraction +ffffffff82170060 T dcn31_update_soc_for_wm_a +ffffffff82170110 T dcn315_update_soc_for_wm_a +ffffffff821701e0 T dcn31_calculate_wm_and_dlg_fp +ffffffff821706e0 T dcn31_update_bw_bounding_box +ffffffff82170ad0 T dcn315_update_bw_bounding_box +ffffffff82170dc0 T dcn316_update_bw_bounding_box +ffffffff82172000 T dml31_recalculate +ffffffff821722a0 t DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation +ffffffff82179060 T dml31_CalculateWriteBackDISPCLK +ffffffff821791e0 T dml31_ModeSupportAndSystemConfigurationFull +ffffffff821814a0 t CalculateSwathAndDETConfiguration +ffffffff82181aa0 t TruncToValidBPP +ffffffff82181d20 t dscceComputeDelay +ffffffff82181e60 t CalculateDCFCLKDeepSleep +ffffffff821821a0 t CalculateVMAndRowBytes +ffffffff821827f0 t CalculatePrefetchSourceLines +ffffffff821829b0 t CalculateUrgentBurstFactor +ffffffff82182c40 t CalculatePrefetchSchedulePerPlane +ffffffff82183370 t CalculateFlipSchedule +ffffffff821838f0 t CalculateWatermarksAndDRAMSpeedChangeSupport +ffffffff82184550 t CalculateSwathWidth +ffffffff82184a60 t CalculatePrefetchSchedule +ffffffff82185ef0 t CalculateVupdateAndDynamicMetadataParameters +ffffffff82187000 T dml31_rq_dlg_get_rq_reg +ffffffff821874b0 t dml_rq_dlg_get_rq_params +ffffffff82187720 T dml31_rq_dlg_get_dlg_reg +ffffffff8218a1f0 t get_surf_rq_param +ffffffff8218b000 T dcn314_update_bw_bounding_box_fpu +ffffffff8218b480 T dcn314_populate_dml_pipes_from_context_fpu +ffffffff8218c000 T dml314_recalculate +ffffffff8218c280 t DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation +ffffffff82192f60 T dml314_CalculateWriteBackDISPCLK +ffffffff821930e0 T dml314_ModeSupportAndSystemConfigurationFull +ffffffff8219b280 t CalculateBytePerPixelAnd256BBlockSizes +ffffffff8219b4f0 t CalculateSwathAndDETConfiguration +ffffffff8219baf0 t TruncToValidBPP +ffffffff8219bd70 t dscceComputeDelay +ffffffff8219beb0 t CalculateDCFCLKDeepSleep +ffffffff8219c1f0 t CalculateVMAndRowBytes +ffffffff8219c840 t CalculatePrefetchSourceLines +ffffffff8219ca00 t CalculateUrgentBurstFactor +ffffffff8219cc90 t CalculateMaxVStartup +ffffffff8219cdd0 t CalculatePrefetchSchedulePerPlane +ffffffff8219d500 t CalculateFlipSchedule +ffffffff8219da80 t CalculateWatermarksAndDRAMSpeedChangeSupport +ffffffff8219e6e0 t CalculateSwathWidth +ffffffff8219ebf0 t CalculatePrefetchSchedule +ffffffff821a0080 t CalculateVupdateAndDynamicMetadataParameters +ffffffff821a1000 T dml314_rq_dlg_get_rq_reg +ffffffff821a14b0 t dml_rq_dlg_get_rq_params +ffffffff821a1720 T dml314_rq_dlg_get_dlg_reg +ffffffff821a4270 t get_surf_rq_param +ffffffff821a5000 T dcn32_build_wm_range_table_fpu +ffffffff821a5390 T dcn32_find_dummy_latency_index_for_fw_based_mclk_switch +ffffffff821a55c0 T dcn32_internal_validate_bw +ffffffff821a72f0 T dcn32_helper_populate_phantom_dlg_params +ffffffff821a7490 T dcn32_predict_pipe_split +ffffffff821a76c0 T insert_entry_into_table_sorted +ffffffff821a7af0 T dcn32_set_phantom_stream_timing +ffffffff821a7d90 t dcn32_split_stream_for_mpc_or_odm +ffffffff821a8120 T dcn32_calculate_wm_and_dlg_fpu +ffffffff821a9630 T dcn32_patch_dpm_table +ffffffff821a9840 T dcn32_update_bw_bounding_box_fpu +ffffffff821ab240 T dcn32_zero_pipe_dcc_fraction +ffffffff821ab2a0 T dcn32_allow_subvp_with_active_margin +ffffffff821ab370 t subvp_drr_schedulable +ffffffff821ac000 T dml32_recalculate +ffffffff821b0320 T dml32_ModeSupportAndSystemConfigurationFull +ffffffff821b8000 T dml32_dscceComputeDelay +ffffffff821b8140 T dml32_dscComputeDelay +ffffffff821b8180 T IsVertical +ffffffff821b81b0 T dml32_CalculateSinglePipeDPPCLKAndSCLThroughput +ffffffff821b84c0 T dml32_CalculateBytePerPixelAndBlockSizes +ffffffff821b87f0 T dml32_CalculateSwathAndDETConfiguration +ffffffff821b9000 T dml32_CalculateSwathWidth +ffffffff821b98a0 T dml32_UnboundedRequest +ffffffff821b9900 T dml32_CalculateDETBufferSize +ffffffff821b9f40 T dml32_CalculateODMMode +ffffffff821ba6a0 T dml32_CalculateRequiredDispclk +ffffffff821ba850 T dml32_RoundToDFSGranularity +ffffffff821ba8e0 T dml32_CalculateOutputLink +ffffffff821bb400 T dml32_TruncToValidBPP +ffffffff821bb750 T dml32_CalculateDPPCLK +ffffffff821bb900 T dml32_RequiredDTBCLK +ffffffff821bbb50 T dml32_DSCDelayRequirement +ffffffff821bc010 T dml32_CalculateSurfaceSizeInMall +ffffffff821bcb20 T dml32_CalculateVMRowAndSwath +ffffffff821bd950 T dml32_CalculateVMAndRowBytes +ffffffff821be590 T dml32_CalculatePrefetchSourceLines +ffffffff821be7e0 T dml32_CalculateMALLUseForStaticScreen +ffffffff821be920 T dml32_CalculateRowBandwidth +ffffffff821bea80 T dml32_CalculateUrgentLatency +ffffffff821beb10 T dml32_CalculateUrgentBurstFactor +ffffffff821bedb0 T dml32_CalculateDCFCLKDeepSleep +ffffffff821bf0f0 T dml32_CalculateWriteBackDelay +ffffffff821bf250 T dml32_UseMinimumDCFCLK +ffffffff821c0110 T dml32_CalculateExtraLatencyBytes +ffffffff821c02e0 T dml32_CalculateTWait +ffffffff821c03c0 T dml32_CalculateVUpdateAndDynamicMetadataParameters +ffffffff821c0620 T dml32_get_return_bw_mbps +ffffffff821c07d0 T dml32_get_return_bw_mbps_vm_only +ffffffff821c08b0 T dml32_CalculateExtraLatency +ffffffff821c0ad0 T dml32_CalculatePrefetchSchedule +ffffffff821c2080 T dml32_CalculateFlipSchedule +ffffffff821c2600 T dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport +ffffffff821c3750 T dml32_CalculateWriteBackDISPCLK +ffffffff821c3910 T dml32_CalculateMinAndMaxPrefetchMode +ffffffff821c3950 T dml32_CalculatePixelDeliveryTimes +ffffffff821c3dc0 T dml32_CalculateMetaAndPTETimes +ffffffff821c4500 T dml32_CalculateVMGroupAndRequestTimes +ffffffff821c49f0 T dml32_CalculateDCCConfiguration +ffffffff821c5000 T dml32_CalculateStutterEfficiency +ffffffff821c5f40 T dml32_CalculateMaxDETAndMinCompressedBufferSize +ffffffff821c6020 T dml32_CalculateVActiveBandwithSupport +ffffffff821c61b0 T dml32_CalculatePrefetchBandwithSupport +ffffffff821c6450 T dml32_CalculateBandwidthAvailableForImmediateFlip +ffffffff821c65a0 T dml32_CalculateImmediateFlipBandwithSupport +ffffffff821c67f0 T dml32_CalculateDETSwathFillLatencyHiding +ffffffff821c7000 T dml32_rq_dlg_get_rq_reg +ffffffff821c76a0 T dml32_rq_dlg_get_dlg_reg +ffffffff821ca000 T dcn321_insert_entry_into_table_sorted +ffffffff821ca430 T dcn321_update_bw_bounding_box_fpu +ffffffff821cc000 T dml_init_instance +ffffffff821cc300 T dml_get_status_message +ffffffff821cc340 T dml_log_pipe_params +ffffffff821cc370 T dml_log_mode_support_params +ffffffff821cd000 T dml_get_voltage_level +ffffffff821cd1e0 t fetch_socbb_params +ffffffff821cd6f0 t fetch_ip_params +ffffffff821cdb90 t fetch_pipe_params +ffffffff821cec90 T PixelClockAdjustmentForProgressiveToInterlaceUnit +ffffffff821ced00 T get_clk_dcf_deepsleep +ffffffff821cee10 T get_wm_urgent +ffffffff821cef20 T get_wm_memory_trip +ffffffff821cf030 T get_wm_writeback_urgent +ffffffff821cf140 T get_wm_stutter_exit +ffffffff821cf250 T get_wm_stutter_enter_exit +ffffffff821cf360 T get_wm_z8_stutter_exit +ffffffff821cf470 T get_wm_z8_stutter_enter_exit +ffffffff821cf580 T get_stutter_efficiency_z8 +ffffffff821cf690 T get_stutter_num_bursts_z8 +ffffffff821cf7a0 T get_wm_dram_clock_change +ffffffff821cf8b0 T get_wm_writeback_dram_clock_change +ffffffff821cf9c0 T get_stutter_efficiency +ffffffff821cfad0 T get_stutter_efficiency_no_vblank +ffffffff821cfbe0 T get_stutter_period +ffffffff821cfcf0 T get_urgent_latency +ffffffff821cfe00 T get_urgent_extra_latency +ffffffff821cff10 T get_nonurgent_latency +ffffffff821d0020 T get_dram_clock_change_latency +ffffffff821d0130 T get_dispclk_calculated +ffffffff821d0240 T get_total_data_read_bw +ffffffff821d0350 T get_return_bw +ffffffff821d0460 T get_tcalc +ffffffff821d0570 T get_fraction_of_urgent_bandwidth +ffffffff821d0680 T get_fraction_of_urgent_bandwidth_imm_flip +ffffffff821d0790 T get_cstate_max_cap_mode +ffffffff821d08b0 T get_comp_buffer_size_kbytes +ffffffff821d09c0 T get_pixel_chunk_size_in_kbyte +ffffffff821d0ad0 T get_alpha_pixel_chunk_size_in_kbyte +ffffffff821d0be0 T get_meta_chunk_size_in_kbyte +ffffffff821d0cf0 T get_min_pixel_chunk_size_in_byte +ffffffff821d0e00 T get_min_meta_chunk_size_in_byte +ffffffff821d0f10 T get_fclk_watermark +ffffffff821d1020 T get_usr_retraining_watermark +ffffffff821d1130 T get_comp_buffer_reserved_space_kbytes +ffffffff821d1240 T get_comp_buffer_reserved_space_64bytes +ffffffff821d1350 T get_comp_buffer_reserved_space_zs +ffffffff821d1460 T get_unbounded_request_enabled +ffffffff821d1580 T get_dsc_delay +ffffffff821d16a0 T get_dppclk_calculated +ffffffff821d17c0 T get_dscclk_calculated +ffffffff821d18e0 T get_min_ttu_vblank +ffffffff821d1a00 T get_min_ttu_vblank_in_us +ffffffff821d1b20 T get_vratio_prefetch_l +ffffffff821d1c40 T get_vratio_prefetch_c +ffffffff821d1d60 T get_dst_x_after_scaler +ffffffff821d1e80 T get_dst_y_after_scaler +ffffffff821d1fa0 T get_dst_y_per_vm_vblank +ffffffff821d20c0 T get_dst_y_per_row_vblank +ffffffff821d21e0 T get_dst_y_prefetch +ffffffff821d2300 T get_dst_y_per_vm_flip +ffffffff821d2420 T get_dst_y_per_row_flip +ffffffff821d2540 T get_refcyc_per_vm_group_vblank +ffffffff821d2660 T get_refcyc_per_vm_group_flip +ffffffff821d2780 T get_refcyc_per_vm_req_vblank +ffffffff821d28a0 T get_refcyc_per_vm_req_flip +ffffffff821d29c0 T get_refcyc_per_vm_group_vblank_in_us +ffffffff821d2ae0 T get_refcyc_per_vm_group_flip_in_us +ffffffff821d2c00 T get_refcyc_per_vm_req_vblank_in_us +ffffffff821d2d20 T get_refcyc_per_vm_req_flip_in_us +ffffffff821d2e40 T get_refcyc_per_vm_dmdata_in_us +ffffffff821d2f60 T get_dmdata_dl_delta_in_us +ffffffff821d3080 T get_refcyc_per_line_delivery_l_in_us +ffffffff821d31a0 T get_refcyc_per_line_delivery_c_in_us +ffffffff821d32c0 T get_refcyc_per_line_delivery_pre_l_in_us +ffffffff821d33e0 T get_refcyc_per_line_delivery_pre_c_in_us +ffffffff821d3500 T get_refcyc_per_req_delivery_l_in_us +ffffffff821d3620 T get_refcyc_per_req_delivery_c_in_us +ffffffff821d3740 T get_refcyc_per_req_delivery_pre_l_in_us +ffffffff821d3860 T get_refcyc_per_req_delivery_pre_c_in_us +ffffffff821d3980 T get_refcyc_per_cursor_req_delivery_in_us +ffffffff821d3aa0 T get_refcyc_per_cursor_req_delivery_pre_in_us +ffffffff821d3bc0 T get_refcyc_per_meta_chunk_nom_l_in_us +ffffffff821d3ce0 T get_refcyc_per_meta_chunk_nom_c_in_us +ffffffff821d3e00 T get_refcyc_per_meta_chunk_vblank_l_in_us +ffffffff821d3f20 T get_refcyc_per_meta_chunk_vblank_c_in_us +ffffffff821d4040 T get_refcyc_per_meta_chunk_flip_l_in_us +ffffffff821d4160 T get_refcyc_per_meta_chunk_flip_c_in_us +ffffffff821d4280 T get_vstartup +ffffffff821d43a0 T get_vupdate_offset +ffffffff821d44c0 T get_vupdate_width +ffffffff821d45e0 T get_vready_offset +ffffffff821d4700 T get_vready_at_or_after_vsync +ffffffff821d4830 T get_min_dst_y_next_start +ffffffff821d4950 T get_dst_y_per_pte_row_nom_l +ffffffff821d4a70 T get_dst_y_per_pte_row_nom_c +ffffffff821d4b90 T get_dst_y_per_meta_row_nom_l +ffffffff821d4cb0 T get_dst_y_per_meta_row_nom_c +ffffffff821d4dd0 T get_refcyc_per_pte_group_nom_l_in_us +ffffffff821d4ef0 T get_refcyc_per_pte_group_nom_c_in_us +ffffffff821d5010 T get_refcyc_per_pte_group_vblank_l_in_us +ffffffff821d5130 T get_refcyc_per_pte_group_vblank_c_in_us +ffffffff821d5250 T get_refcyc_per_pte_group_flip_l_in_us +ffffffff821d5370 T get_refcyc_per_pte_group_flip_c_in_us +ffffffff821d5490 T get_vstartup_calculated +ffffffff821d55b0 T get_dpte_row_height_linear_c +ffffffff821d56d0 T get_swath_height_l +ffffffff821d57f0 T get_swath_height_c +ffffffff821d5910 T get_det_stored_buffer_size_l_bytes +ffffffff821d5a30 T get_det_stored_buffer_size_c_bytes +ffffffff821d5b50 T get_dpte_group_size_in_bytes +ffffffff821d5c70 T get_vm_group_size_in_bytes +ffffffff821d5d90 T get_dpte_row_height_linear_l +ffffffff821d5eb0 T get_pte_buffer_mode +ffffffff821d5fe0 T get_subviewport_lines_needed_in_mall +ffffffff821d6100 T get_total_immediate_flip_bytes +ffffffff821d6210 T get_total_immediate_flip_bw +ffffffff821d63f0 T get_total_prefetch_bw +ffffffff821d65d0 T get_total_surface_size_in_mall_bytes +ffffffff821d6770 T get_det_buffer_size_kbytes +ffffffff821d6890 T get_is_phantom_pipe +ffffffff821d69b0 T Calculate256BBlockSizes +ffffffff821d6aa0 T CalculateMinAndMaxPrefetchMode +ffffffff821d6b10 T ModeSupportAndSystemConfiguration +ffffffff821d6e20 T CalculateWriteBackDISPCLK +ffffffff821d8000 T print__rq_params_st +ffffffff821d8030 T print__data_rq_sizing_params_st +ffffffff821d8060 T print__data_rq_dlg_params_st +ffffffff821d8090 T print__data_rq_misc_params_st +ffffffff821d80c0 T print__rq_dlg_params_st +ffffffff821d80f0 T print__dlg_sys_params_st +ffffffff821d8120 T print__data_rq_regs_st +ffffffff821d8150 T print__rq_regs_st +ffffffff821d8180 T print__dlg_regs_st +ffffffff821d81b0 T print__ttu_regs_st +ffffffff821d9000 T dml1_extract_rq_regs +ffffffff821d9330 T dml1_rq_dlg_get_rq_params +ffffffff821d9500 t get_surf_rq_param +ffffffff821da200 T dml1_rq_dlg_get_dlg_params +ffffffff821dd000 T _do_calc_rc_params +ffffffff821de040 t get_qp_set +ffffffff821df000 T dc_dsc_parse_dsc_dpcd +ffffffff821df2a0 t dsc_throughput_from_dpcd +ffffffff821df460 T dc_dsc_compute_bandwidth_range +ffffffff821df640 t intersect_dsc_caps +ffffffff821df800 t setup_dsc_config +ffffffff821e01d0 T dc_dsc_compute_config +ffffffff821e02c0 T dc_dsc_stream_bandwidth_in_kbps +ffffffff821e0410 T dc_dsc_stream_bandwidth_overhead_in_kbps +ffffffff821e0560 T dc_dsc_get_policy_for_timing +ffffffff821e0600 T dc_dsc_policy_set_max_target_bpp_limit +ffffffff821e0630 T dc_dsc_policy_set_enable_dsc_when_not_needed +ffffffff821e0660 T dc_dsc_policy_set_disable_dsc_stream_overhead +ffffffff821e1000 T calc_rc_params +ffffffff821e2000 T dscc_compute_dsc_parameters +ffffffff821e3000 T dal_hw_factory_dce110_init ffffffff821e3060 t define_hpd_registers ffffffff821e30b0 t define_ddc_registers -ffffffff821e3160 t define_generic_registers -ffffffff821e4000 T dal_hw_translate_dcn30_init +ffffffff821e4000 T dal_hw_translate_dce110_init ffffffff821e4030 t offset_to_id -ffffffff821e42b0 t id_to_offset -ffffffff821e5000 T dal_hw_factory_dcn315_init +ffffffff821e4390 t id_to_offset +ffffffff821e5000 T dal_hw_factory_dce120_init ffffffff821e5060 t define_hpd_registers ffffffff821e50b0 t define_ddc_registers -ffffffff821e5160 t define_generic_registers -ffffffff821e6000 T dal_hw_translate_dcn315_init +ffffffff821e6000 T dal_hw_translate_dce120_init ffffffff821e6030 t offset_to_id -ffffffff821e62a0 t id_to_offset -ffffffff821e7000 T dal_hw_factory_dcn32_init +ffffffff821e63a0 t id_to_offset +ffffffff821e7000 T dal_hw_factory_dce80_init ffffffff821e7060 t define_hpd_registers ffffffff821e70b0 t define_ddc_registers -ffffffff821e7160 t define_generic_registers -ffffffff821e8000 T dal_hw_translate_dcn32_init +ffffffff821e8000 T dal_hw_translate_dce80_init ffffffff821e8030 t offset_to_id -ffffffff821e8280 t id_to_offset -ffffffff821e9000 T dal_gpio_open -ffffffff821e90b0 T dal_gpio_open_ex -ffffffff821e9160 T dal_gpio_get_value -ffffffff821e91e0 T dal_gpio_set_value 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dal_hw_gpio_config_mode -ffffffff821ef180 T dal_hw_gpio_get_value -ffffffff821ef1e0 T dal_hw_gpio_set_value -ffffffff821ef260 T dal_hw_gpio_change_mode -ffffffff821ef270 T dal_hw_gpio_close -ffffffff821ef320 T dal_hw_gpio_construct -ffffffff821ef370 T dal_hw_gpio_destruct -ffffffff821f0000 T dal_hw_hpd_init -ffffffff821f0100 T dal_hw_hpd_get_pin -ffffffff821f0110 t dal_hw_hpd_destroy -ffffffff821f0170 t get_value -ffffffff821f0200 t set_config -ffffffff821f1000 T dal_hw_translate_init -ffffffff821f2000 T dc_process_hdcp_msg -ffffffff821f2180 t hdmi_14_process_transaction -ffffffff821f22d0 t dp_11_process_transaction -ffffffff821f3000 T dal_irq_service_dummy_set -ffffffff821f3050 T dal_irq_service_dummy_ack -ffffffff821f30a0 T dce110_vblank_set -ffffffff821f3170 T to_dal_irq_source_dce110 -ffffffff821f32f0 T dal_irq_service_dce110_create -ffffffff821f3370 t hpd_ack -ffffffff821f4000 T dal_irq_service_dce120_create -ffffffff821f4080 t hpd_ack -ffffffff821f5000 T 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T dal_gpio_create_irq +ffffffff821f6380 T dal_gpio_service_create_generic_mux +ffffffff821f6420 T dal_gpio_destroy_generic_mux +ffffffff821f64b0 T dal_gpio_get_generic_pin_info +ffffffff821f6510 T dal_gpio_service_destroy +ffffffff821f6630 T dal_mux_setup_config +ffffffff821f6690 T dal_gpio_service_lock +ffffffff821f6700 T dal_gpio_service_unlock +ffffffff821f6770 T dal_gpio_service_open +ffffffff821f69a0 T dal_gpio_service_close +ffffffff821f6a30 T dal_irq_get_source +ffffffff821f6aa0 T dal_irq_get_rx_source +ffffffff821f6af0 T dal_irq_setup_hpd_filter +ffffffff821f6b50 T dal_gpio_destroy_irq +ffffffff821f6be0 T dal_gpio_create_ddc +ffffffff821f6d50 T dal_gpio_destroy_ddc +ffffffff821f6e10 T dal_ddc_close +ffffffff821f6e60 T dal_ddc_open +ffffffff821f6fc0 T dal_ddc_change_mode +ffffffff821f7060 T dal_ddc_get_line +ffffffff821f7070 T dal_ddc_set_config +ffffffff821f8000 T dal_hw_ddc_init +ffffffff821f8100 T dal_hw_ddc_get_pin +ffffffff821f8110 t dal_hw_ddc_destroy +ffffffff821f8170 t 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dce110_vblank_set +ffffffff821ff170 T to_dal_irq_source_dce110 +ffffffff821ff2f0 T dal_irq_service_dce110_create +ffffffff821ff370 t hpd_ack +ffffffff82200000 T dal_irq_service_dce120_create ffffffff82200080 t hpd_ack -ffffffff82200130 t to_dal_irq_source_dcn32 -ffffffff82201000 T dal_irq_service_construct -ffffffff82201070 T dal_irq_service_destroy -ffffffff822010f0 T dal_irq_service_set_generic -ffffffff82201160 T dal_irq_service_set -ffffffff82201270 T dal_irq_service_ack -ffffffff82201360 T dal_irq_service_ack_generic -ffffffff822013d0 T dal_irq_service_to_irq_source -ffffffff82202000 T dp_trace_init -ffffffff82202090 T dp_trace_reset -ffffffff82202120 T dc_dp_trace_is_initialized -ffffffff82202150 T dp_trace_detect_lt_init -ffffffff822021a0 T dp_trace_commit_lt_init -ffffffff822021f0 T dp_trace_link_loss_increment -ffffffff82202220 T dp_trace_lt_fail_count_update -ffffffff82202260 T dp_trace_lt_total_count_increment -ffffffff822022a0 T dc_dp_trace_set_is_logged_flag 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bwfm_sdio_tx_ok -ffffffff8250f220 T bwfm_sdio_tx_ctrlframe -ffffffff8250f320 T bwfm_sdio_tx_dataframe -ffffffff8250f470 T bwfm_sdio_rx_glom -ffffffff82510000 T onewire_match -ffffffff82510050 T onewire_attach -ffffffff825100f0 T onewire_detach -ffffffff82510160 T onewire_activate -ffffffff82510180 T onewire_scan -ffffffff82510390 T onewire_createthread -ffffffff825103f0 T onewire_print -ffffffff825104c0 T onewirebus_print -ffffffff82510510 T onewire_lock -ffffffff82510530 T onewire_unlock -ffffffff82510540 T onewire_reset -ffffffff82510560 T onewire_bit -ffffffff82510580 T onewire_read_byte -ffffffff825106c0 T onewire_write_byte -ffffffff82510790 T onewire_read_block -ffffffff82510830 T onewire_write_block -ffffffff825108d0 T onewire_triplet -ffffffff825109b0 T onewire_matchrom -ffffffff82510b00 T onewire_search -ffffffff82510e90 T onewire_thread -ffffffff82511000 T onewire_crc -ffffffff825110e0 T onewire_crc16 -ffffffff825111c0 T onewire_famname -ffffffff82511200 T onewire_matchbyfam -ffffffff82512000 T owid_match -ffffffff82512020 T owid_attach -ffffffff825120f0 T owid_detach -ffffffff82512130 T owid_activate -ffffffff82513000 T owsbm_match -ffffffff82513020 T owsbm_attach -ffffffff825131c0 T owsbm_detach -ffffffff82513230 T owsbm_activate -ffffffff82513260 T owsbm_update -ffffffff82514000 T owtemp_match -ffffffff82514020 T owtemp_attach -ffffffff82514110 T owtemp_detach -ffffffff82514180 T owtemp_activate -ffffffff825141b0 T owtemp_update -ffffffff82515000 T owctr_match -ffffffff82515020 T owctr_attach -ffffffff82515160 T owctr_detach -ffffffff825151d0 T owctr_activate -ffffffff82515200 T owctr_update -ffffffff82515230 T owctr_update_counter -ffffffff82516000 A __text_page_start -ffffffff82516000 T Xsyscall_meltdown -ffffffff8251600c T Xsyscall -ffffffff8251626e t Xsyscall_trampback -ffffffff82516280 T intr_user_exit -ffffffff825162c2 t intr_user_exit_post_ast -ffffffff825163ee t Xiretq_trampback -ffffffff825163fa T doreti_iret -ffffffff82517000 T alltraps -ffffffff82517138 T recall_trap -ffffffff82517150 T alltraps_kern -ffffffff82517153 T alltraps_kern_meltdown -ffffffff82518000 ? Xsyscall32 -ffffffff82518000 A __kutext_start -ffffffff82518000 A __text_page_end -ffffffff82519000 ? Xtrap00 -ffffffff82519010 ? Xtrap01 -ffffffff82519020 ? Xtrap02 -ffffffff82519024 c calltrap_specstk -ffffffff825190f0 ? calltrap_specstk_tramp -ffffffff82519110 ? Xtrap03 -ffffffff82519120 ? Xtrap04 -ffffffff82519130 ? Xtrap05 -ffffffff82519140 ? Xtrap06 -ffffffff82519150 ? Xtrap07 -ffffffff82519160 ? Xtrap08 -ffffffff82519170 ? Xtrap09 -ffffffff82519180 ? Xtrap0a -ffffffff82519190 ? Xtrap0b -ffffffff825191a0 ? Xtrap0c -ffffffff825191b0 ? Xtrap0d -ffffffff82519230 ? Xtrap0e -ffffffff82519240 ? Xintrspurious -ffffffff82519240 ? Xtrap0f -ffffffff82519250 ? Xtrap10 -ffffffff82519260 ? Xtrap11 -ffffffff82519270 ? Xtrap12 -ffffffff82519280 ? Xtrap13 -ffffffff82519290 ? Xtrap14 -ffffffff82519290 ? Xtrap15 -ffffffff82519290 ? Xtrap16 -ffffffff82519290 ? Xtrap17 -ffffffff82519290 ? Xtrap18 -ffffffff82519290 ? Xtrap19 -ffffffff82519290 ? Xtrap1a -ffffffff82519290 ? Xtrap1b -ffffffff82519290 ? Xtrap1c -ffffffff82519290 ? Xtrap1d -ffffffff82519290 ? Xtrap1e -ffffffff82519290 ? Xtrap1f -ffffffff825192a0 ? x2apic_eoi -ffffffff825192c0 ? Xintr_lapic_ipi -ffffffff825192f0 ? Xipi_invltlb -ffffffff82519310 ? Xipi_invlpg -ffffffff82519340 ? Xipi_invlrange -ffffffff82519380 ? Xipi_invltlb_pcid -ffffffff825193c0 ? Xipi_invlpg_pcid -ffffffff82519410 ? Xipi_invlrange_pcid -ffffffff82519480 ? Xintr_lapic_ltimer -ffffffff825194b0 ? Xintr_xen_upcall -ffffffff825194e0 ? Xintr_hyperv_upcall -ffffffff82519510 ? Xintr_legacy0 -ffffffff82519540 ? Xintr_legacy1 -ffffffff82519570 ? Xintr_legacy2 -ffffffff825195a0 ? Xintr_legacy3 -ffffffff825195d0 ? Xintr_legacy4 -ffffffff82519600 ? Xintr_legacy5 -ffffffff82519630 ? Xintr_legacy6 -ffffffff82519660 ? Xintr_legacy7 -ffffffff82519690 ? Xintr_legacy8 -ffffffff825196c0 ? Xintr_legacy9 -ffffffff825196f0 ? Xintr_legacy10 -ffffffff82519720 ? Xintr_legacy11 -ffffffff82519750 ? Xintr_legacy12 -ffffffff82519780 ? Xintr_legacy13 -ffffffff825197b0 ? Xintr_legacy14 -ffffffff825197e0 ? Xintr_legacy15 -ffffffff82519810 ? Xintr_ioapic_edge0 -ffffffff82519840 ? Xintr_ioapic_edge1 -ffffffff82519870 ? Xintr_ioapic_edge2 -ffffffff825198a0 ? Xintr_ioapic_edge3 -ffffffff825198d0 ? Xintr_ioapic_edge4 -ffffffff82519900 ? Xintr_ioapic_edge5 -ffffffff82519930 ? Xintr_ioapic_edge6 -ffffffff82519960 ? Xintr_ioapic_edge7 -ffffffff82519990 ? Xintr_ioapic_edge8 -ffffffff825199c0 ? Xintr_ioapic_edge9 -ffffffff825199f0 ? Xintr_ioapic_edge10 -ffffffff82519a20 ? Xintr_ioapic_edge11 -ffffffff82519a50 ? Xintr_ioapic_edge12 -ffffffff82519a80 ? Xintr_ioapic_edge13 -ffffffff82519ab0 ? Xintr_ioapic_edge14 -ffffffff82519ae0 ? Xintr_ioapic_edge15 -ffffffff82519b10 ? Xintr_ioapic_edge16 -ffffffff82519b40 ? Xintr_ioapic_edge17 -ffffffff82519b70 ? Xintr_ioapic_edge18 -ffffffff82519ba0 ? Xintr_ioapic_edge19 -ffffffff82519bd0 ? Xintr_ioapic_edge20 -ffffffff82519c00 ? Xintr_ioapic_edge21 -ffffffff82519c30 ? Xintr_ioapic_edge22 -ffffffff82519c60 ? Xintr_ioapic_edge23 -ffffffff82519c90 ? Xintr_ioapic_edge24 -ffffffff82519cc0 ? Xintr_ioapic_edge25 -ffffffff82519cf0 ? Xintr_ioapic_edge26 -ffffffff82519d20 ? Xintr_ioapic_edge27 -ffffffff82519d50 ? Xintr_ioapic_edge28 -ffffffff82519d80 ? Xintr_ioapic_edge29 -ffffffff82519db0 ? Xintr_ioapic_edge30 -ffffffff82519de0 ? Xintr_ioapic_edge31 -ffffffff82519e10 ? Xintr_ioapic_edge32 -ffffffff82519e40 ? Xintr_ioapic_edge33 -ffffffff82519e70 ? Xintr_ioapic_edge34 -ffffffff82519ea0 ? Xintr_ioapic_edge35 -ffffffff82519ed0 ? Xintr_ioapic_edge36 -ffffffff82519f00 ? Xintr_ioapic_edge37 -ffffffff82519f30 ? Xintr_ioapic_edge38 -ffffffff82519f60 ? Xintr_ioapic_edge39 -ffffffff82519f90 ? Xintr_ioapic_edge40 -ffffffff82519fc0 ? Xintr_ioapic_edge41 -ffffffff82519ff0 ? Xintr_ioapic_edge42 -ffffffff8251a020 ? Xintr_ioapic_edge43 -ffffffff8251a050 ? Xintr_ioapic_edge44 -ffffffff8251a080 ? Xintr_ioapic_edge45 -ffffffff8251a0b0 ? Xintr_ioapic_edge46 -ffffffff8251a0e0 ? Xintr_ioapic_edge47 -ffffffff8251a110 ? Xintr_ioapic_edge48 -ffffffff8251a140 ? Xintr_ioapic_edge49 -ffffffff8251a170 ? Xintr_ioapic_edge50 -ffffffff8251a1a0 ? Xintr_ioapic_edge51 -ffffffff8251a1d0 ? Xintr_ioapic_edge52 -ffffffff8251a200 ? Xintr_ioapic_edge53 -ffffffff8251a230 ? Xintr_ioapic_edge54 -ffffffff8251a260 ? Xintr_ioapic_edge55 -ffffffff8251a290 ? Xintr_ioapic_edge56 -ffffffff8251a2c0 ? Xintr_ioapic_edge57 -ffffffff8251a2f0 ? Xintr_ioapic_edge58 -ffffffff8251a320 ? Xintr_ioapic_edge59 -ffffffff8251a350 ? Xintr_ioapic_edge60 -ffffffff8251a380 ? Xintr_ioapic_edge61 -ffffffff8251a3b0 ? Xintr_ioapic_edge62 -ffffffff8251a3e0 ? Xintr_ioapic_edge63 -ffffffff8251a410 ? Xintr_ioapic_level0 -ffffffff8251a440 ? Xintr_ioapic_level1 -ffffffff8251a470 ? Xintr_ioapic_level2 -ffffffff8251a4a0 ? Xintr_ioapic_level3 -ffffffff8251a4d0 ? Xintr_ioapic_level4 -ffffffff8251a500 ? Xintr_ioapic_level5 -ffffffff8251a530 ? Xintr_ioapic_level6 -ffffffff8251a560 ? Xintr_ioapic_level7 -ffffffff8251a590 ? Xintr_ioapic_level8 -ffffffff8251a5c0 ? Xintr_ioapic_level9 -ffffffff8251a5f0 ? Xintr_ioapic_level10 -ffffffff8251a620 ? Xintr_ioapic_level11 -ffffffff8251a650 ? Xintr_ioapic_level12 -ffffffff8251a680 ? Xintr_ioapic_level13 -ffffffff8251a6b0 ? Xintr_ioapic_level14 -ffffffff8251a6e0 ? Xintr_ioapic_level15 -ffffffff8251a710 ? Xintr_ioapic_level16 -ffffffff8251a740 ? Xintr_ioapic_level17 -ffffffff8251a770 ? Xintr_ioapic_level18 -ffffffff8251a7a0 ? Xintr_ioapic_level19 -ffffffff8251a7d0 ? Xintr_ioapic_level20 -ffffffff8251a800 ? Xintr_ioapic_level21 -ffffffff8251a830 ? Xintr_ioapic_level22 -ffffffff8251a860 ? Xintr_ioapic_level23 -ffffffff8251a890 ? Xintr_ioapic_level24 -ffffffff8251a8c0 ? Xintr_ioapic_level25 -ffffffff8251a8f0 ? Xintr_ioapic_level26 -ffffffff8251a920 ? Xintr_ioapic_level27 -ffffffff8251a950 ? Xintr_ioapic_level28 -ffffffff8251a980 ? Xintr_ioapic_level29 -ffffffff8251a9b0 ? Xintr_ioapic_level30 -ffffffff8251a9e0 ? Xintr_ioapic_level31 -ffffffff8251aa10 ? Xintr_ioapic_level32 -ffffffff8251aa40 ? Xintr_ioapic_level33 -ffffffff8251aa70 ? Xintr_ioapic_level34 -ffffffff8251aaa0 ? Xintr_ioapic_level35 -ffffffff8251aad0 ? Xintr_ioapic_level36 -ffffffff8251ab00 ? Xintr_ioapic_level37 -ffffffff8251ab30 ? Xintr_ioapic_level38 -ffffffff8251ab60 ? Xintr_ioapic_level39 -ffffffff8251ab90 ? Xintr_ioapic_level40 -ffffffff8251abc0 ? Xintr_ioapic_level41 -ffffffff8251abf0 ? Xintr_ioapic_level42 -ffffffff8251ac20 ? Xintr_ioapic_level43 -ffffffff8251ac50 ? Xintr_ioapic_level44 -ffffffff8251ac80 ? Xintr_ioapic_level45 -ffffffff8251acb0 ? Xintr_ioapic_level46 -ffffffff8251ace0 ? Xintr_ioapic_level47 -ffffffff8251ad10 ? Xintr_ioapic_level48 -ffffffff8251ad40 ? Xintr_ioapic_level49 -ffffffff8251ad70 ? Xintr_ioapic_level50 -ffffffff8251ada0 ? Xintr_ioapic_level51 -ffffffff8251add0 ? Xintr_ioapic_level52 -ffffffff8251ae00 ? Xintr_ioapic_level53 -ffffffff8251ae30 ? Xintr_ioapic_level54 -ffffffff8251ae60 ? Xintr_ioapic_level55 -ffffffff8251ae90 ? Xintr_ioapic_level56 -ffffffff8251aec0 ? Xintr_ioapic_level57 -ffffffff8251aef0 ? Xintr_ioapic_level58 -ffffffff8251af20 ? Xintr_ioapic_level59 -ffffffff8251af50 ? Xintr_ioapic_level60 -ffffffff8251af80 ? Xintr_ioapic_level61 -ffffffff8251afb0 ? Xintr_ioapic_level62 -ffffffff8251afe0 ? Xintr_ioapic_level63 -ffffffff8251c000 ? codepatch_fill_nop -ffffffff8251c000 A __cptext_start -ffffffff8251c000 A __kutext_end -ffffffff8251c0b0 ? codepatch_maprw -ffffffff8251c190 ? codepatch_unmaprw -ffffffff8251c1f0 ? codepatch_nop -ffffffff8251c340 ? codepatch_replace -ffffffff8251c4e0 ? codepatch_call -ffffffff8251c500 ? codepatch_jmp -ffffffff8251d000 A __cptext_end -ffffffff8251d000 A __rodata_start -ffffffff8251d000 C _etext -ffffffff8251d000 C etext -ffffffff8251e000 r seeprom_read -ffffffff8251e004 r icl_mg_pll_find_divisors.div1_vals -ffffffff8251e028 r gen9bc_tgp_ddc_pin_map -ffffffff8251e038 r athn_ac2qid -ffffffff8251e038 r athn_ac2qid -ffffffff8251e038 r athn_ac2qid -ffffffff8251e044 r rtwn_get_rssi.cckoff -ffffffff8251e06c r rsu_ac2qid -ffffffff8251e07c r pckbc_portcmd -ffffffff8251e080 r tht_fifo_write_pad.pad -ffffffff8251e088 r rsu_get_rssi.cckoff -ffffffff8251e09c r adlp_n_revids -ffffffff8251e0ec r apple_iso_trans -ffffffff8251e0f0 r dg2_g12_revid_step_tbl -ffffffff8251e0f8 r wihap_check_tx.txratetable -ffffffff8251e0fc r dmamode -ffffffff8251e124 r gen9_edram_size_mb.sets -ffffffff8251f000 r isomappings -ffffffff8251f080 r unimappings -ffffffff8251f230 r replacements -ffffffff82522aff r cmd0646_9_tim_udma -ffffffff8257611d r pp_r600_decoded_lanes -ffffffff82591355 r cmd680_setup_channel.udma_tbl -ffffffff82598f54 r apollo_udma33_tim -ffffffff8259eff7 r substchar -ffffffff825a109d r apollo_udma100_tim -ffffffff825c88b2 r apollo_udma66_tim -ffffffff825cfd0a r apollo_pio_rec -ffffffff825defc0 r cy_pio_rec -ffffffff8260e2a7 r apollo_udma133_tim -ffffffff8261ad78 R drm_ca -ffffffff8261ada0 R drm_filtops -ffffffff8261add0 R drmread_filtops -ffffffff8261b000 r vga_emulops -ffffffff8261b048 R vga_stdscreen -ffffffff8261b078 R vga_stdscreen_mono -ffffffff8261b0a8 R vga_stdscreen_bf -ffffffff8261b0d8 R vga_40lscreen -ffffffff8261b108 R vga_40lscreen_mono -ffffffff8261b138 R vga_40lscreen_bf -ffffffff8261b168 R vga_50lscreen -ffffffff8261b198 R vga_50lscreen_mono -ffffffff8261b1c8 R vga_50lscreen_bf -ffffffff8261b1f8 R vga_screenlist -ffffffff8261b208 R vga_screenlist_mono -ffffffff8261b218 R vga_accessops -ffffffff8261b278 r i945_wm_info -ffffffff8261b2b0 r bgansitopc -ffffffff8261b2b8 r pctoansi -ffffffff8261b2f8 r sdma_offsets -ffffffff8261b2f8 r sdma_offsets -ffffffff8261b328 r iha_rate_tbl -ffffffff8261b360 r i830_a_wm_info -ffffffff8261b398 r gen9_edram_size_mb.ways -ffffffff8261b400 r aggr_periodic_times -ffffffff8261b480 r jsl_ehl_revids -ffffffff8261b4f8 r michael_final.pad -ffffffff8261b520 r rt_copysa.maskarray -ffffffff8261b528 r i915_wm_info -ffffffff8261b530 r amdgpu_ih_clientid_jpeg -ffffffff8261b530 r amdgpu_ih_clientid_uvds -ffffffff8261b530 r amdgpu_ih_clientid_vcns -ffffffff8261b530 r amdgpu_ih_clientid_vcns -ffffffff8261b530 r amdgpu_ih_clientid_vcns -ffffffff8261b568 r vga_setfontset.cmaptabb -ffffffff8261b580 r tgl_revids -ffffffff8261b5d8 r i830_bc_wm_info -ffffffff8261b680 r __drm_universal_plane_init.default_modifiers -ffffffff8261b690 r iwn_tid2fifo -ffffffff8261b6a8 r vga_setfontset.cmaptaba -ffffffff8261b6b0 r crtc_offsets -ffffffff8261b6b0 r crtc_offsets -ffffffff8261b6b0 r crtc_offsets -ffffffff8261b6d0 r link_speed -ffffffff8261b6d0 r link_speed -ffffffff8261b6d0 r link_speed -ffffffff8261b748 r rtwn_r88e_get_rssi.cckoff -ffffffff8261c000 R edid_vendors -ffffffff8261c2c0 R edid_nvendors -ffffffff8261c2d0 R edid_products -ffffffff8261c330 R edid_nproducts -ffffffff8261c340 r _edid_modes -ffffffff8261d000 R videomode_list -ffffffff8261e080 R videomode_count -ffffffff8261f000 r ahc_hard_errors -ffffffff8261f080 r critical_sections -ffffffff8261f0b0 r patches -ffffffff8261fd50 r seqprog -ffffffff82621000 r ahc_switch -ffffffff82622000 r termstat_strings -ffffffff82622020 r critical_sections -ffffffff82622060 r seqprog -ffffffff82622d50 r patches -ffffffff82624000 r ahd_switch -ffffffff82625000 R aic_switch -ffffffff82626000 R adw_switch -ffffffff82627000 R gdt_switch -ffffffff82628000 R twe_switch -ffffffff82629000 R ciss_switch -ffffffff82629030 R ciss_level -ffffffff82629050 R ciss_stat -ffffffff8262a000 R ami_switch -ffffffff8262a028 R ami_raw_switch -ffffffff8262b000 R mfi_switch -ffffffff8262b028 R mfi_pd_switch -ffffffff8262b050 r mfi_iop_xscale -ffffffff8262b080 r mfi_iop_ppc -ffffffff8262b0b0 r mfi_iop_gen2 -ffffffff8262b0e0 r mfi_iop_skinny -ffffffff8262b110 r mfi_bbu_indicators -ffffffff8262b1c0 r bwi_rf_calc_nrssi_slope_11b.save_phy_regs -ffffffff8262b1f0 r chv_oa_mux_regs -ffffffff8262b210 r fiji_clock_stretcher_lookup_table -ffffffff8262b210 r tonga_clock_stretcher_lookup_table -ffffffff8262b240 r link_speed -ffffffff8262b240 r link_speed -ffffffff8262b240 r link_speed -ffffffff8262b280 r drm_fb_xfrm.default_dst_pitch -ffffffff8262b280 r non_supported_protection -ffffffff8262b380 r tgl_uy_revids -ffffffff8262b3d0 r bwi_phy_noise_11g_rev1 -ffffffff8262b450 r cardslot_process_event.antonym_ev -ffffffff8262b4e0 r gen11_oa_mux_regs -ffffffff8262b5d0 r ddr2_cycle_tenths -ffffffff8262b640 r rtw_intr_rx.ratetbl -ffffffff8262b6c0 r abm_config -ffffffff8262b730 r getbootinfo.ports.30 -ffffffff8262b780 r reg_offsets -ffffffff8262b790 r bwi_rf_lo_measure_11g.rf_lo_adjust -ffffffff8262b7a0 r init_non_clock_fields.look_up -ffffffff8262b7b0 r uftdi_8u232am_getrate.roundoff -ffffffff8262b800 r zyd_rx_data.rates -ffffffff8262b810 r ieee80211_ra_valid_tx_mcs.max_mcs -ffffffff8262b850 r mmio_invalidate_full.gen8_regs -ffffffff8262b880 r bwi_phy_noise_11g -ffffffff8262b890 r hpt366_pio -ffffffff8262b8c0 r glk_revids -ffffffff8262b910 r bwi_rf_calc_nrssi_slope_11g.save_phy3_regs -ffffffff8262b930 r ether_crc32_be_update.rev -ffffffff8262b930 r rtw_grf5101_mac_crypt.caesar -ffffffff8262b980 r snb_b_fdi_train_param -ffffffff8262c000 R qlw_switch -ffffffff8262d000 R isp_2100_risc_code -ffffffff8263fbf0 R isp_2200_risc_code -ffffffff82652990 R isp_2300_risc_code -ffffffff8266c408 R qla_switch -ffffffff8266c430 r qla_regs_2100 -ffffffff8266c460 r qla_regs_2200 -ffffffff8266c490 r qla_regs_23XX -ffffffff8266d000 R ahci_atascsi_methods -ffffffff8266e000 R nvme_switch -ffffffff8266e028 r nvme_ops -ffffffff8266f000 R mpi_switch -ffffffff8266f100 r intel_hpll_vco.elk_vco -ffffffff8266f160 r pin_offsets -ffffffff8266f1c0 r firmware_list -ffffffff8266f220 r atom_arg_shift -ffffffff8266f220 r atom_arg_shift -ffffffff8266f260 r pf_syncookie_wstab -ffffffff8266f280 r ieee80211_media_init.mopts -ffffffff8266f2e0 r add_entropy_words.twist_table -ffffffff8266f380 r urtw_8225v2_txpwr_cck -ffffffff8266f3a0 r bwfm_pci_prio2fifo -ffffffff8266f3a0 r ieee80211_up_to_ac.up_to_ac -ffffffff8266f460 r paritytab -ffffffff8266f460 r x86emu_parity_tab -ffffffff8266f480 r legacy_connector_convert -ffffffff8266f4c0 r gen7_oa_mux_regs -ffffffff8266f4e0 r hsw_oa_mux_regs -ffffffff8266f500 r notetab -ffffffff8266f520 r urtw_8225v2_txpwr_cck_ch14 -ffffffff8266f540 r bwi_rf_calibval.rf_calibvals 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r debug_defaults_diags -ffffffff82b90340 r clk_src_regs -ffffffff82b904e4 r dccg_regs -ffffffff82b905d0 r dccg_shift -ffffffff82b90668 r dccg_mask -ffffffff82b908d0 r abm_regs -ffffffff82b90a10 r abm_shift -ffffffff82b90a24 r abm_mask -ffffffff82b90a70 r res_create_funcs -ffffffff82b90aa0 r res_create_maximus_funcs -ffffffff82b90ad0 r plane_cap -ffffffff82b90b00 r panel_cntl_regs -ffffffff82b90b20 r panel_cntl_shift -ffffffff82b90b30 r panel_cntl_mask -ffffffff82b90b70 r link_enc_regs -ffffffff82b911d0 r link_enc_aux_regs -ffffffff82b91220 r link_enc_hpd_regs -ffffffff82b91234 r le_shift -ffffffff82b91324 r le_mask -ffffffff82b916dc r link_enc_feature -ffffffff82b916ec r cs_shift -ffffffff82b916f8 r cs_mask -ffffffff82b91720 r hubbub_reg -ffffffff82b91894 r hubbub_shift -ffffffff82b9191c r hubbub_mask -ffffffff82b91b40 r vmid_regs -ffffffff82b91d00 r vmid_shifts -ffffffff82b91d08 r vmid_masks -ffffffff82b91d30 r hubp_regs -ffffffff82b9276c r hubp_shift -ffffffff82b92868 r hubp_mask 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mcif_wb30_regs -ffffffff82ba1b2c r mcif_wb30_shift -ffffffff82ba1bd8 r mcif_wb30_mask -ffffffff82ba1e90 r aux_engine_regs -ffffffff82ba1ee0 r aux_mask -ffffffff82ba1f40 r aux_shift -ffffffff82ba1f60 r i2c_hw_regs -ffffffff82ba1fd0 r i2c_shifts -ffffffff82ba1ffc r i2c_masks -ffffffff82ba20a0 r audio_regs -ffffffff82ba21d4 r audio_shift -ffffffff82ba21ec r audio_mask -ffffffff82ba2230 r stream_enc_regs -ffffffff82ba24d8 r se_shift -ffffffff82ba25b4 r se_mask -ffffffff82ba2920 r vpg_regs -ffffffff82ba295c r vpg_shift -ffffffff82ba2984 r vpg_mask -ffffffff82ba2a20 r afmt_regs -ffffffff82ba2a8c r afmt_shift -ffffffff82ba2aa0 r afmt_mask -ffffffff82ba2ae4 r hwseq_reg -ffffffff82ba2d00 r hwseq_shift -ffffffff82ba2d80 r hwseq_mask -ffffffff82ba3000 r dccg31_funcs -ffffffff82ba4000 r dcn31_link_enc_funcs -ffffffff82ba5000 r dcn30_str_enc_funcs -ffffffff82ba6000 r hubbub31_funcs -ffffffff82ba7000 r dcn31_funcs -ffffffff82ba72c0 r dcn31_private_funcs -ffffffff82ba8000 r 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dal_irq_service_dcn31_create +ffffffff82209080 t hpd_ack +ffffffff82209130 t to_dal_irq_source_dcn31 +ffffffff8220a000 T dal_irq_service_dcn314_create +ffffffff8220a080 t hpd_ack +ffffffff8220a130 t to_dal_irq_source_dcn314 +ffffffff8220b000 T dal_irq_service_dcn315_create +ffffffff8220b080 t hpd_ack +ffffffff8220b130 t to_dal_irq_source_dcn315 +ffffffff8220c000 T dal_irq_service_dcn32_create +ffffffff8220c080 t hpd_ack +ffffffff8220c130 t to_dal_irq_source_dcn32 +ffffffff8220d000 T dal_irq_service_construct +ffffffff8220d070 T dal_irq_service_destroy +ffffffff8220d0f0 T dal_irq_service_set_generic +ffffffff8220d160 T dal_irq_service_set +ffffffff8220d270 T dal_irq_service_ack +ffffffff8220d360 T dal_irq_service_ack_generic +ffffffff8220d3d0 T dal_irq_service_to_irq_source +ffffffff8220e000 T dp_trace_init +ffffffff8220e090 T dp_trace_reset +ffffffff8220e120 T dc_dp_trace_is_initialized +ffffffff8220e150 T dp_trace_detect_lt_init +ffffffff8220e1a0 T dp_trace_commit_lt_init +ffffffff8220e1f0 T dp_trace_link_loss_increment +ffffffff8220e220 T dp_trace_lt_fail_count_update +ffffffff8220e260 T dp_trace_lt_total_count_increment +ffffffff8220e2a0 T dc_dp_trace_set_is_logged_flag +ffffffff8220e2e0 T dc_dp_trace_is_logged +ffffffff8220e320 T dp_trace_lt_result_update +ffffffff8220e360 T dp_trace_set_lt_start_timestamp +ffffffff8220e440 T dp_trace_set_lt_end_timestamp +ffffffff8220e520 T dc_dp_trace_get_lt_end_timestamp +ffffffff8220e560 T dc_dp_trace_get_lt_counts +ffffffff8220e5a0 T dc_dp_trace_get_link_loss_count +ffffffff8220e5d0 T dp_trace_set_edp_power_timestamp +ffffffff8220e6b0 T dp_trace_get_edp_poweron_timestamp +ffffffff8220e6e0 T dp_trace_get_edp_poweroff_timestamp +ffffffff8220f000 T set_dio_throttled_vcp_size +ffffffff8220f020 T setup_dio_stream_encoder +ffffffff8220f0d0 T reset_dio_stream_encoder +ffffffff8220f190 T setup_dio_stream_attribute +ffffffff8220f310 T enable_dio_dp_link_output +ffffffff8220f380 T disable_dio_link_output +ffffffff8220f3c0 T set_dio_dp_link_test_pattern +ffffffff8220f400 T set_dio_dp_lane_settings +ffffffff8220f440 T can_use_dio_link_hwss +ffffffff8220f470 T get_dio_link_hwss +ffffffff8220f4a0 t update_dio_stream_allocation_table +ffffffff82210000 T can_use_dpia_link_hwss +ffffffff82210050 T get_dpia_link_hwss +ffffffff82210080 t update_dpia_stream_allocation_table +ffffffff82211000 T can_use_hpo_dp_link_hwss +ffffffff82211030 T get_hpo_dp_link_hwss +ffffffff82211060 t set_hpo_dp_hblank_min_symbol_width +ffffffff82211130 t set_hpo_dp_throttled_vcp_size +ffffffff82211160 t enable_hpo_dp_link_output +ffffffff82211280 t set_hpo_dp_link_test_pattern +ffffffff822112c0 t set_hpo_dp_lane_settings +ffffffff822112f0 t update_hpo_dp_stream_allocation_table +ffffffff82211310 t setup_hpo_dp_stream_encoder +ffffffff82211490 t reset_hpo_dp_stream_encoder +ffffffff82211580 t setup_hpo_dp_stream_attribute +ffffffff822115e0 t disable_hpo_dp_link_output +ffffffff82212000 T virtual_link_encoder_construct +ffffffff82212060 t virtual_link_encoder_validate_output_with_stream +ffffffff82212090 t virtual_link_encoder_hw_init +ffffffff822120c0 t virtual_link_encoder_setup +ffffffff822120f0 t virtual_link_encoder_enable_tmds_output +ffffffff82212120 t virtual_link_encoder_enable_dp_output +ffffffff82212150 t virtual_link_encoder_enable_dp_mst_output +ffffffff82212180 t virtual_link_encoder_disable_output +ffffffff822121b0 t virtual_link_encoder_dp_set_lane_settings +ffffffff822121e0 t virtual_link_encoder_dp_set_phy_pattern +ffffffff82212210 t virtual_link_encoder_update_mst_stream_allocation_table +ffffffff82212240 t virtual_link_encoder_connect_dig_be_to_fe +ffffffff82212270 t virtual_link_encoder_destroy +ffffffff822122c0 t virtual_link_encoder_get_max_link_cap +ffffffff82213000 T virtual_setup_stream_encoder +ffffffff82213030 T virtual_setup_stream_attribute +ffffffff82213060 T virtual_reset_stream_encoder +ffffffff82213090 T get_virtual_link_hwss +ffffffff822130c0 t virtual_disable_link_output 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virtual_stream_encoder_reset_hdmi_stream_attribute +ffffffff822143d0 t virtual_stream_encoder_set_dsc_pps_info_packet +ffffffff82214400 t virtual_enc_dp_set_odm_combine +ffffffff82215000 T dmub_dcn20_use_cached_inbox +ffffffff82215040 T dmub_dcn20_reset +ffffffff82215210 T dmub_dcn20_reset_release +ffffffff822152e0 T dmub_dcn20_backdoor_load +ffffffff82215590 T dmub_dcn20_setup_windows +ffffffff82215b00 T dmub_dcn20_setup_mailbox +ffffffff82215b60 T dmub_dcn20_get_inbox1_rptr +ffffffff82215b80 T dmub_dcn20_set_inbox1_wptr +ffffffff82215ba0 T dmub_dcn20_setup_out_mailbox +ffffffff82215c00 T dmub_dcn20_get_outbox1_wptr +ffffffff82215c20 T dmub_dcn20_set_outbox1_rptr +ffffffff82215c40 T dmub_dcn20_setup_outbox0 +ffffffff82215c90 T dmub_dcn20_get_outbox0_wptr +ffffffff82215cb0 T dmub_dcn20_set_outbox0_rptr +ffffffff82215cd0 T dmub_dcn20_is_hw_init +ffffffff82215d20 T dmub_dcn20_is_supported +ffffffff82215d80 T dmub_dcn20_set_gpint +ffffffff82215db0 T dmub_dcn20_is_gpint_acked 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dmub_dcn32_set_inbox1_wptr +ffffffff8221bac0 T dmub_dcn32_setup_out_mailbox +ffffffff8221bb10 T dmub_dcn32_get_outbox1_wptr +ffffffff8221bb30 T dmub_dcn32_set_outbox1_rptr +ffffffff8221bb50 T dmub_dcn32_is_hw_init +ffffffff8221bbd0 T dmub_dcn32_is_supported +ffffffff8221bc30 T dmub_dcn32_set_gpint +ffffffff8221bc60 T dmub_dcn32_is_gpint_acked +ffffffff8221bcc0 T dmub_dcn32_get_gpint_response +ffffffff8221bcf0 T dmub_dcn32_get_gpint_dataout +ffffffff8221be10 T dmub_dcn32_get_fw_boot_status +ffffffff8221be40 T dmub_dcn32_enable_dmub_boot_options +ffffffff8221be70 T dmub_dcn32_skip_dmub_panel_power_sequence +ffffffff8221bec0 T dmub_dcn32_setup_outbox0 +ffffffff8221bf10 T dmub_dcn32_get_outbox0_wptr +ffffffff8221bf30 T dmub_dcn32_set_outbox0_rptr +ffffffff8221bf50 T dmub_dcn32_get_current_time +ffffffff8221bf80 T dmub_dcn32_get_diagnostic_data +ffffffff8221c420 T dmub_dcn32_configure_dmub_in_system_memory +ffffffff8221c450 T dmub_dcn32_send_inbox0_cmd +ffffffff8221c470 T dmub_dcn32_clear_inbox0_ack_register +ffffffff8221c4a0 T dmub_dcn32_read_inbox0_ack_register +ffffffff8221d000 T dmub_reg_update +ffffffff8221d170 T dmub_reg_set +ffffffff8221d2d0 T dmub_reg_get +ffffffff8221e000 T dmub_flush_buffer_mem +ffffffff8221e030 T dmub_srv_create +ffffffff8221e550 T dmub_srv_destroy +ffffffff8221e570 T dmub_srv_calc_region_info +ffffffff8221e7e0 T dmub_srv_calc_fb_info +ffffffff8221e980 T dmub_srv_has_hw_support +ffffffff8221e9f0 T dmub_srv_is_hw_init +ffffffff8221ea60 T dmub_srv_hw_init +ffffffff8221eeb0 T dmub_srv_hw_reset +ffffffff8221ef40 T dmub_srv_cmd_queue +ffffffff8221f040 T dmub_srv_cmd_execute +ffffffff8221f100 T dmub_srv_wait_for_auto_load +ffffffff8221f1a0 T dmub_srv_wait_for_phy_init +ffffffff8221f250 T dmub_srv_wait_for_idle +ffffffff8221f300 T dmub_srv_send_gpint_command +ffffffff8221f3e0 T dmub_srv_get_gpint_response +ffffffff8221f440 T dmub_srv_get_gpint_dataout +ffffffff8221f4a0 T dmub_srv_get_fw_boot_status +ffffffff8221f510 T dmub_srv_cmd_with_reply_data +ffffffff8221f780 T dmub_srv_get_outbox0_msg +ffffffff8221f820 T dmub_srv_get_diagnostic_data +ffffffff8221f870 T dmub_srv_should_detect +ffffffff8221f8b0 T dmub_srv_clear_inbox0_ack +ffffffff8221f900 T dmub_srv_wait_for_inbox0_ack +ffffffff8221f990 T dmub_srv_send_inbox0_cmd +ffffffff82220000 T dmub_srv_stat_get_notification +ffffffff82221000 T setup_x_points_distribution +ffffffff82221160 T log_x_points_distribution +ffffffff82221190 T precompute_pq +ffffffff82221350 t compute_pq +ffffffff82221560 T precompute_de_pq +ffffffff822216b0 t compute_de_pq +ffffffff82221970 T calculate_user_regamma_coeff +ffffffff82221d40 t apply_lut_1d +ffffffff82222070 T calculate_user_regamma_ramp +ffffffff822229b0 T mod_color_calculate_degamma_params +ffffffff82222f80 t build_evenly_distributed_points +ffffffff82223100 t scale_gamma +ffffffff822232b0 t build_degamma +ffffffff82223680 t build_hlg_degamma +ffffffff822238a0 t map_regamma_hw_to_x_user +ffffffff82224000 T mod_color_calculate_regamma_params +ffffffff82226170 T mod_color_calculate_degamma_curve +ffffffff82226630 t translate_from_linear_space +ffffffff82226970 t build_coefficients +ffffffff82226af0 t calculate_mapped_value +ffffffff82227000 T mod_color_is_table_init +ffffffff82227050 T mod_color_get_table +ffffffff82227090 T mod_color_set_table_init_state +ffffffff82228000 T mod_freesync_create +ffffffff82228070 T mod_freesync_destroy +ffffffff822280b0 T mod_freesync_calc_v_total_from_refresh +ffffffff82228140 T mod_freesync_get_vmin_vmax +ffffffff82228180 T mod_freesync_get_v_position +ffffffff82228200 T mod_freesync_build_vrr_infopacket +ffffffff82228950 T mod_freesync_build_vrr_params +ffffffff82228cd0 T mod_freesync_calc_nominal_field_rate +ffffffff82228d20 T mod_freesync_handle_preflip +ffffffff82229140 T mod_freesync_handle_v_update +ffffffff82229600 T mod_freesync_get_settings +ffffffff82229660 T mod_freesync_calc_field_rate_from_timing +ffffffff822296b0 T mod_freesync_get_freesync_enabled +ffffffff822296e0 T mod_freesync_is_valid_range +ffffffff8222a000 T mod_build_vsc_infopacket +ffffffff8222a200 T mod_build_hf_vsif_infopacket +ffffffff8222b000 T dmub_init_abm_config +ffffffff8222b540 t fill_iram_v_2_3 +ffffffff8222b9a0 T dmcu_load_iram +ffffffff8222c180 T is_psr_su_specific_panel +ffffffff8222c210 T mod_power_calc_psr_configs +ffffffff8222c310 T mod_power_only_edp +ffffffff8222d000 T mod_vmid_get_for_ptb +ffffffff8222d230 T mod_vmid_reset +ffffffff8222d2f0 T mod_vmid_create +ffffffff8222d430 T mod_vmid_destroy +ffffffff8222e000 T amdgpu_dpm_get_sclk +ffffffff8222e090 T amdgpu_dpm_get_mclk +ffffffff8222e120 T amdgpu_dpm_set_powergating_by_smu +ffffffff8222e200 T amdgpu_dpm_set_gfx_power_up_by_imu +ffffffff8222e310 T amdgpu_dpm_baco_enter +ffffffff8222e3a0 T amdgpu_dpm_baco_exit +ffffffff8222e430 T amdgpu_dpm_set_mp1_state +ffffffff8222e4c0 T amdgpu_dpm_is_baco_supported +ffffffff8222e560 T amdgpu_dpm_mode2_reset +ffffffff8222e5f0 T amdgpu_dpm_baco_reset +ffffffff8222e6a0 T amdgpu_dpm_is_mode1_reset_supported +ffffffff8222e710 T amdgpu_dpm_mode1_reset +ffffffff8222e790 T amdgpu_dpm_switch_power_profile +ffffffff8222e830 T amdgpu_dpm_set_xgmi_pstate +ffffffff8222e8c0 T amdgpu_dpm_set_df_cstate +ffffffff8222e960 T amdgpu_dpm_allow_xgmi_power_down +ffffffff8222e9e0 T amdgpu_dpm_enable_mgpu_fan_boost +ffffffff8222ea70 T amdgpu_dpm_set_clockgating_by_smu +ffffffff8222eb10 T amdgpu_dpm_smu_i2c_bus_access +ffffffff8222ebb0 T amdgpu_pm_acpi_event_handler +ffffffff8222ec70 T amdgpu_dpm_read_sensor +ffffffff8222ed20 T amdgpu_dpm_compute_clocks +ffffffff8222ee00 T amdgpu_dpm_enable_uvd +ffffffff8222efe0 T amdgpu_dpm_enable_vce +ffffffff8222f1c0 T amdgpu_dpm_enable_jpeg +ffffffff8222f2b0 T amdgpu_pm_load_smu_firmware +ffffffff8222f360 T amdgpu_dpm_handle_passthrough_sbr +ffffffff8222f3e0 T amdgpu_dpm_send_hbm_bad_pages_num +ffffffff8222f460 T amdgpu_dpm_send_hbm_bad_channel_flag +ffffffff8222f4e0 T amdgpu_dpm_get_dpm_freq_range +ffffffff8222f580 T amdgpu_dpm_set_soft_freq_range +ffffffff8222f620 T amdgpu_dpm_write_watermarks_table +ffffffff8222f690 T amdgpu_dpm_wait_for_event +ffffffff8222f720 T amdgpu_dpm_set_residency_gfxoff +ffffffff8222f7a0 T amdgpu_dpm_get_residency_gfxoff +ffffffff8222f820 T amdgpu_dpm_get_entrycount_gfxoff +ffffffff8222f8a0 T amdgpu_dpm_get_status_gfxoff +ffffffff8222f920 T amdgpu_dpm_get_thermal_throttling_counter +ffffffff8222f970 T amdgpu_dpm_gfx_state_change +ffffffff8222f9d0 T amdgpu_dpm_get_ecc_info +ffffffff8222fa50 T amdgpu_dpm_get_vce_clock_state +ffffffff8222fae0 T amdgpu_dpm_get_current_power_state +ffffffff8222fb50 T amdgpu_dpm_set_power_state +ffffffff8222fca0 T amdgpu_dpm_dispatch_task +ffffffff8222fd40 T amdgpu_dpm_get_performance_level +ffffffff8222fdd0 T amdgpu_dpm_force_performance_level +ffffffff8222ffb0 T amdgpu_dpm_get_pp_num_states +ffffffff82230040 T amdgpu_dpm_get_pp_table +ffffffff822300d0 T amdgpu_dpm_set_fine_grain_clk_vol +ffffffff82230170 T amdgpu_dpm_odn_edit_dpm_table +ffffffff82230210 T amdgpu_dpm_print_clock_levels +ffffffff822302a0 T amdgpu_dpm_emit_clock_levels +ffffffff82230340 T amdgpu_dpm_set_ppfeature_status +ffffffff822303d0 T amdgpu_dpm_get_ppfeature_status +ffffffff82230460 T amdgpu_dpm_force_clock_level +ffffffff822304f0 T amdgpu_dpm_get_sclk_od +ffffffff82230570 T amdgpu_dpm_set_sclk_od +ffffffff822306f0 T amdgpu_dpm_get_mclk_od +ffffffff82230770 T amdgpu_dpm_set_mclk_od +ffffffff822308f0 T amdgpu_dpm_get_power_profile_mode +ffffffff82230980 T amdgpu_dpm_set_power_profile_mode +ffffffff82230a10 T amdgpu_dpm_get_gpu_metrics +ffffffff82230aa0 T amdgpu_dpm_get_fan_control_mode +ffffffff82230b30 T amdgpu_dpm_set_fan_speed_pwm +ffffffff82230bc0 T amdgpu_dpm_get_fan_speed_pwm +ffffffff82230c50 T amdgpu_dpm_get_fan_speed_rpm +ffffffff82230ce0 T amdgpu_dpm_set_fan_speed_rpm +ffffffff82230d70 T amdgpu_dpm_set_fan_control_mode +ffffffff82230e00 T amdgpu_dpm_get_power_limit +ffffffff82230ea0 T amdgpu_dpm_set_power_limit +ffffffff82230f30 T amdgpu_dpm_is_cclk_dpm_supported +ffffffff82230fa0 T amdgpu_dpm_debugfs_print_current_performance_level +ffffffff82231030 T amdgpu_dpm_get_smu_prv_buf_details +ffffffff822310d0 T amdgpu_dpm_is_overdrive_supported +ffffffff82231160 T amdgpu_dpm_set_pp_table +ffffffff82231200 T amdgpu_dpm_get_num_cpu_cores +ffffffff82231250 T amdgpu_dpm_stb_debug_fs_init +ffffffff822312a0 T amdgpu_dpm_display_configuration_change +ffffffff82231330 T amdgpu_dpm_get_clock_by_type +ffffffff822313c0 T amdgpu_dpm_get_display_mode_validation_clks +ffffffff82231450 T amdgpu_dpm_get_clock_by_type_with_latency +ffffffff822314e0 T amdgpu_dpm_get_clock_by_type_with_voltage +ffffffff82231570 T amdgpu_dpm_set_watermarks_for_clocks_ranges +ffffffff82231600 T amdgpu_dpm_display_clock_voltage_request +ffffffff82231690 T amdgpu_dpm_get_current_clocks +ffffffff82231720 T amdgpu_dpm_notify_smu_enable_pwe +ffffffff822317a0 T amdgpu_dpm_set_active_display_count +ffffffff82231830 T amdgpu_dpm_set_min_deep_sleep_dcefclk +ffffffff822318c0 T amdgpu_dpm_set_hard_min_dcefclk_by_freq +ffffffff82231950 T amdgpu_dpm_set_hard_min_fclk_by_freq +ffffffff822319e0 T amdgpu_dpm_display_disable_memory_clock_switch +ffffffff82231a70 T amdgpu_dpm_get_max_sustainable_clocks_by_dc +ffffffff82231b00 T amdgpu_dpm_get_uclk_dpm_states +ffffffff82231ba0 T amdgpu_dpm_get_dpm_clock_table +ffffffff82232000 T amdgpu_dpm_get_active_displays +ffffffff822320a0 T amdgpu_dpm_get_vblank_time +ffffffff82232150 T amdgpu_dpm_get_vrefresh +ffffffff82233000 T amdgpu_pm_sysfs_init +ffffffff82233030 T amdgpu_pm_sysfs_fini +ffffffff82233060 T amdgpu_debugfs_pm_init +ffffffff82234000 T amdgpu_dpm_print_class_info +ffffffff822342b0 T amdgpu_dpm_print_cap_info +ffffffff82234330 T amdgpu_dpm_print_ps_status +ffffffff822343c0 T amdgpu_pm_print_power_states +ffffffff82234470 T amdgpu_get_platform_caps +ffffffff82234510 T amdgpu_parse_extended_power_table +ffffffff82235520 T amdgpu_free_extended_power_table +ffffffff82235630 T amdgpu_add_thermal_controller +ffffffff82235a60 T amdgpu_get_vce_clock_state +ffffffff82235aa0 T amdgpu_legacy_dpm_compute_clocks +ffffffff82235f10 T amdgpu_dpm_thermal_work_handler +ffffffff82236000 t pp_early_init +ffffffff82236100 t pp_late_init +ffffffff82236210 t pp_sw_init +ffffffff82236230 t pp_sw_fini +ffffffff822362b0 t pp_hw_init +ffffffff82236300 t pp_hw_fini +ffffffff82236340 t pp_late_fini +ffffffff822363a0 t pp_suspend +ffffffff822363c0 t pp_resume +ffffffff822363e0 t pp_is_idle +ffffffff82236410 t pp_wait_for_idle +ffffffff82236440 t pp_sw_reset +ffffffff82236470 t pp_set_clockgating_state +ffffffff822364a0 t pp_set_powergating_state +ffffffff822364d0 t pp_dpm_set_fan_control_mode +ffffffff82236540 t pp_dpm_get_fan_control_mode +ffffffff822365b0 t pp_dpm_set_fan_speed_pwm +ffffffff82236610 t pp_dpm_get_fan_speed_pwm +ffffffff82236670 t pp_dpm_force_clock_level +ffffffff822366d0 t pp_dpm_print_clock_levels +ffffffff82236720 t pp_dpm_emit_clock_levels +ffffffff82236780 t pp_dpm_force_performance_level +ffffffff82236810 t pp_dpm_get_sclk_od +ffffffff82236860 t pp_dpm_set_sclk_od +ffffffff822368b0 t pp_dpm_get_mclk_od +ffffffff82236900 t pp_dpm_set_mclk_od +ffffffff82236950 t pp_dpm_read_sensor +ffffffff822369f0 t pp_dpm_get_performance_level +ffffffff82236a30 t pp_dpm_get_current_power_state +ffffffff82236aa0 t pp_dpm_get_fan_speed_rpm +ffffffff82236b00 t pp_dpm_set_fan_speed_rpm +ffffffff82236b60 t pp_dpm_get_pp_num_states +ffffffff82236ca0 t pp_dpm_get_pp_table +ffffffff82236cf0 t pp_dpm_set_pp_table +ffffffff82236e20 t pp_dpm_switch_power_profile +ffffffff82236f60 t pp_dpm_get_vce_clock_state +ffffffff82236fb0 t pp_dpm_dispatch_tasks +ffffffff82236ff0 t pp_dpm_load_fw +ffffffff82237060 t pp_dpm_fw_loading_complete +ffffffff82237090 t pp_set_powergating_by_smu +ffffffff82237200 t pp_set_clockgating_by_smu +ffffffff82237260 t pp_set_power_limit +ffffffff82237320 t pp_get_power_limit +ffffffff822373b0 t pp_get_power_profile_mode +ffffffff82237410 t pp_set_power_profile_mode +ffffffff82237470 t pp_set_fine_grain_clk_vol +ffffffff822374c0 t pp_odn_edit_dpm_table +ffffffff82237510 t pp_dpm_set_mp1_state +ffffffff82237560 t pp_smu_i2c_bus_access +ffffffff822375b0 t pp_gfx_state_change_set +ffffffff82237610 t pp_dpm_get_sclk +ffffffff82237660 t pp_dpm_get_mclk +ffffffff822376b0 t pp_display_configuration_change +ffffffff82237700 t pp_get_display_power_level +ffffffff82237740 t pp_get_current_clocks +ffffffff82237860 t pp_get_clock_by_type +ffffffff822378a0 t pp_get_clock_by_type_with_latency +ffffffff822378e0 t pp_get_clock_by_type_with_voltage +ffffffff82237920 t pp_set_watermarks_for_clocks_ranges +ffffffff82237960 t pp_display_clock_voltage_request +ffffffff822379a0 t pp_get_display_mode_validation_clocks +ffffffff82237a00 t pp_notify_smu_enable_pwe +ffffffff82237a60 t pp_enable_mgpu_fan_boost +ffffffff82237ac0 t pp_set_active_display_count +ffffffff82237b00 t pp_set_hard_min_dcefclk_by_freq +ffffffff82237b60 t pp_set_hard_min_fclk_by_freq +ffffffff82237bc0 t pp_set_min_deep_sleep_dcefclk +ffffffff82237c20 t pp_get_asic_baco_capability +ffffffff82237c90 t pp_get_asic_baco_state +ffffffff82237cf0 t pp_set_asic_baco_state +ffffffff82237d60 t pp_get_ppfeature_status +ffffffff82237db0 t pp_set_ppfeature_status +ffffffff82237e00 t pp_asic_reset_mode_2 +ffffffff82237e50 t pp_set_df_cstate +ffffffff82237eb0 t pp_set_xgmi_pstate +ffffffff82237f10 t pp_get_gpu_metrics +ffffffff82237f70 t pp_get_prv_buffer_details +ffffffff82237ff0 t pp_pm_compute_clocks +ffffffff82239000 T ci_baco_set_state +ffffffff8223a000 T baco_program_registers +ffffffff8223a0d0 t baco_cmd_handler +ffffffff8223a250 T soc15_baco_program_registers +ffffffff8223b000 T fiji_baco_set_state +ffffffff8223c000 T phm_setup_asic +ffffffff8223c050 T phm_power_down_asic +ffffffff8223c0a0 T phm_set_power_state +ffffffff8223c110 T phm_enable_dynamic_state_management +ffffffff8223c1c0 T phm_disable_dynamic_state_management +ffffffff8223c250 T phm_force_dpm_levels +ffffffff8223c2a0 T phm_apply_state_adjust_rules +ffffffff8223c2f0 T phm_apply_clock_adjust_rules +ffffffff8223c340 T phm_powerdown_uvd +ffffffff8223c390 T phm_disable_clock_power_gatings +ffffffff8223c3e0 T phm_pre_display_configuration_changed +ffffffff8223c440 T phm_display_configuration_changed +ffffffff8223c4a0 T phm_notify_smc_display_config_after_ps_adjustment +ffffffff8223c500 T phm_stop_thermal_controller +ffffffff8223c560 T phm_register_irq_handlers +ffffffff8223c5b0 T phm_start_thermal_controller +ffffffff8223c6e0 T phm_check_smc_update_required_for_display_configuration +ffffffff8223c740 T phm_check_states_equal +ffffffff8223c790 T phm_store_dal_configuration_data +ffffffff8223c8e0 T phm_get_dal_power_level +ffffffff8223c930 T phm_set_cpu_power_state +ffffffff8223c980 T phm_get_performance_level +ffffffff8223c9d0 T phm_get_clock_info +ffffffff8223cb50 T phm_get_current_shallow_sleep_clocks +ffffffff8223cba0 T phm_get_clock_by_type +ffffffff8223cbf0 T phm_get_clock_by_type_with_latency +ffffffff8223cc40 T phm_get_clock_by_type_with_voltage +ffffffff8223cc90 T phm_set_watermarks_for_clocks_ranges +ffffffff8223cce0 T phm_display_clock_voltage_request +ffffffff8223cd30 T phm_get_max_high_clocks +ffffffff8223cd80 T phm_disable_smc_firmware_ctf +ffffffff8223cde0 T phm_set_active_display_count +ffffffff8223d000 T hwmgr_early_init +ffffffff8223d470 T hwmgr_sw_init +ffffffff8223d4e0 T hwmgr_sw_fini +ffffffff8223d530 T hwmgr_hw_init +ffffffff8223d6f0 T hwmgr_hw_fini +ffffffff8223d7a0 T hwmgr_suspend +ffffffff8223d820 T hwmgr_resume +ffffffff8223d8c0 T hwmgr_handle_task +ffffffff8223e000 T polaris_baco_set_state +ffffffff8223f000 T pp_override_get_default_fuse_value +ffffffff82240000 T psm_init_power_state_table +ffffffff822402a0 T psm_fini_power_state_table +ffffffff82240360 T psm_set_boot_states +ffffffff82240420 T psm_set_performance_states +ffffffff822404e0 T psm_set_user_performance_state +ffffffff82240570 T psm_adjust_power_state_dynamic +ffffffff82241000 T atomctrl_initialize_mc_reg_table +ffffffff82241200 T atomctrl_initialize_mc_reg_table_v2_2 +ffffffff82241400 T atomctrl_set_engine_dram_timings_rv770 +ffffffff82241460 T atomctrl_get_memory_pll_dividers_si +ffffffff82241540 T atomctrl_get_memory_pll_dividers_vi +ffffffff822415b0 T atomctrl_get_memory_pll_dividers_ai +ffffffff82241660 T atomctrl_get_engine_pll_dividers_kong +ffffffff822416e0 T atomctrl_get_engine_pll_dividers_vi +ffffffff822417a0 T atomctrl_get_engine_pll_dividers_ai +ffffffff82241880 T atomctrl_get_dfs_pll_dividers_vi +ffffffff82241940 T atomctrl_get_reference_clock +ffffffff822419a0 T atomctrl_is_voltage_controlled_by_gpio_v3 +ffffffff82241a50 T atomctrl_get_voltage_table_v3 +ffffffff82241bb0 T atomctrl_get_pp_assign_pin +ffffffff82241ca0 T atomctrl_calculate_voltage_evv_on_sclk +ffffffff82242020 T atomctrl_get_voltage_evv_on_sclk +ffffffff822420a0 T atomctrl_get_voltage_evv +ffffffff82242150 T atomctrl_get_mpll_reference_clock +ffffffff822421c0 T atomctrl_is_asic_internal_ss_supported +ffffffff82242210 T atomctrl_get_memory_clock_spread_spectrum +ffffffff82242310 T atomctrl_get_engine_clock_spread_spectrum +ffffffff82242410 T atomctrl_read_efuse +ffffffff822424c0 T atomctrl_set_ac_timing_ai +ffffffff82242520 T atomctrl_get_voltage_evv_on_sclk_ai +ffffffff82242590 T atomctrl_get_smc_sclk_range_table +ffffffff82242650 T atomctrl_get_vddc_shared_railinfo +ffffffff822426c0 T atomctrl_get_avfs_information +ffffffff82242840 T atomctrl_get_svi2_info +ffffffff82242920 T atomctrl_get_leakage_id_from_efuse +ffffffff82242980 T atomctrl_get_leakage_vddc_base_on_leakage +ffffffff82242b10 T atomctrl_get_voltage_range +ffffffff82242bd0 T atomctrl_get_edc_hilo_leakage_offset_table +ffffffff82242c50 T atomctrl_get_edc_leakage_table +ffffffff82243000 T pp_atomfwctrl_is_voltage_controlled_by_gpio_v4 +ffffffff822430d0 T pp_atomfwctrl_get_voltage_table_v4 +ffffffff82243280 T pp_atomfwctrl_get_pp_assign_pin +ffffffff82243360 T pp_atomfwctrl_enter_self_refresh +ffffffff82243390 T pp_atomfwctrl_get_gpu_pll_dividers_vega10 +ffffffff82243430 T pp_atomfwctrl_get_avfs_information +ffffffff82243760 T pp_atomfwctrl_get_gpio_information +ffffffff82243800 T pp_atomfwctrl_get_clk_information_by_clkid +ffffffff82243880 T pp_atomfwctrl_get_vbios_bootup_values +ffffffff82243c00 T pp_atomfwctrl_get_smc_dpm_information +ffffffff82244000 T encode_pcie_lane_width +ffffffff82244030 T decode_pcie_lane_width +ffffffff82245000 t pp_tables_v1_0_initialize +ffffffff82246420 t pp_tables_v1_0_uninitialize +ffffffff822465c0 T get_number_of_powerplay_table_entries_v1_0 +ffffffff82246670 T get_powerplay_table_entry_v1_0 +ffffffff82247000 T pp_tables_get_response_times +ffffffff822470d0 T pp_tables_get_num_of_entries +ffffffff82247190 T pp_tables_get_entry +ffffffff822474f0 t init_non_clock_fields +ffffffff82247670 t pp_tables_initialize +ffffffff82248ad0 t pp_tables_uninitialize +ffffffff82248cd0 t get_number_of_vce_state_table_entries +ffffffff82248dd0 t get_vce_state_table_entry +ffffffff82249000 T smu10_init_function_pointers +ffffffff82249040 t smu10_hwmgr_backend_init +ffffffff82249710 t smu10_hwmgr_backend_fini +ffffffff82249840 t smu10_setup_asic_task +ffffffff822498b0 t smu10_get_power_state_size +ffffffff822498e0 t smu10_apply_state_adjust_rules +ffffffff82249910 t smu10_dpm_force_dpm_level +ffffffff82249e90 t smu10_enable_dpm_tasks +ffffffff82249f10 t smu10_disable_dpm_tasks +ffffffff82249f40 t smu10_dpm_patch_boot_state +ffffffff82249f70 t smu10_dpm_get_pp_table_entry +ffffffff82249fd0 t smu10_dpm_get_num_of_pp_table_entries +ffffffff8224a020 t smu10_powergate_vcn +ffffffff8224a0c0 t smu10_dpm_get_mclk +ffffffff8224a110 t smu10_dpm_get_sclk +ffffffff8224a160 t smu10_set_power_state_tasks +ffffffff8224a1d0 t smu10_set_cpu_power_state +ffffffff8224a200 t smu10_store_cc6_data +ffffffff8224a270 t smu10_get_dal_power_level +ffffffff8224a2a0 t smu10_get_performance_level +ffffffff8224a330 t smu10_get_current_shallow_sleep_clocks +ffffffff8224a390 t smu10_get_clock_by_type_with_latency +ffffffff8224a4e0 t smu10_get_clock_by_type_with_voltage +ffffffff8224a5e0 t smu10_set_watermarks_for_clocks_ranges +ffffffff8224a6b0 t smu10_display_clock_voltage_request +ffffffff8224a750 t smu10_get_max_high_clocks +ffffffff8224a780 t smu10_power_off_asic +ffffffff8224a7d0 t smu10_force_clock_level +ffffffff8224a990 t smu10_print_clock_levels +ffffffff8224ad30 t smu10_gfx_off_control +ffffffff8224ae40 t smu10_read_sensor +ffffffff8224afb0 t smu10_set_active_display_count +ffffffff8224b000 t smu10_set_min_deep_sleep_dcefclk +ffffffff8224b060 t smu10_get_power_profile_mode +ffffffff8224b0a0 t smu10_set_power_profile_mode +ffffffff8224b1f0 t smu10_set_fine_grain_clk_vol +ffffffff8224b3f0 t smu10_powergate_mmhub +ffffffff8224b410 t smu10_smus_notify_pwe +ffffffff8224b430 t smu10_powergate_sdma +ffffffff8224b450 t smu10_set_hard_min_dcefclk_by_freq +ffffffff8224b4b0 t smu10_set_hard_min_fclk_by_freq +ffffffff8224b510 t smu10_set_hard_min_gfxclk_by_freq +ffffffff8224b570 t smu10_set_soft_max_gfxclk_by_freq +ffffffff8224b5d0 t smu10_asic_reset +ffffffff8224b5f0 t smu10_gfx_state_change +ffffffff8224b630 t smu10_dpm_get_pp_table_entry_callback +ffffffff8224c000 T smu7_baco_get_capability +ffffffff8224c060 T smu7_baco_get_state +ffffffff8224c0b0 T smu7_baco_set_state +ffffffff8224d000 T smu7_powerdown_uvd +ffffffff8224d050 T smu7_disable_clock_power_gating +ffffffff8224d0d0 T smu7_powergate_uvd +ffffffff8224d1c0 T smu7_powergate_vce +ffffffff8224d2b0 T smu7_update_clock_gatings +ffffffff8224d660 T smu7_powergate_gfx +ffffffff8224e000 T smu7_get_sleep_divider_id_from_clock +ffffffff8224e0a0 T smu7_init_function_pointers +ffffffff8224e100 t smu7_hwmgr_backend_init +ffffffff8224ff40 t smu7_hwmgr_backend_fini +ffffffff8224ffb0 t smu7_setup_asic_task +ffffffff82250310 t smu7_get_power_state_size +ffffffff82250340 t smu7_apply_state_adjust_rules +ffffffff822507b0 t smu7_force_dpm_level +ffffffff82250be0 t smu7_enable_dpm_tasks +ffffffff82253340 t smu7_disable_dpm_tasks +ffffffff82253a80 t smu7_dpm_patch_boot_state +ffffffff82253bc0 t smu7_get_pp_table_entry +ffffffff82253fb0 t smu7_get_number_of_powerplay_table_entries +ffffffff82254020 t smu7_dpm_get_mclk +ffffffff822540c0 t smu7_dpm_get_sclk +ffffffff82254160 t smu7_set_power_state_tasks +ffffffff82254ee0 t smu7_notify_smc_display_config_after_ps_adjustment +ffffffff82254f10 t smu7_display_configuration_changed_task +ffffffff822550c0 t smu7_set_max_fan_rpm_output +ffffffff822550f0 t smu7_set_max_fan_pwm_output +ffffffff82255110 t smu7_set_fan_control_mode +ffffffff822551a0 t smu7_get_fan_control_mode +ffffffff822551e0 t smu7_register_irq_handlers +ffffffff82255280 t smu7_check_smc_update_required_for_display_configuration +ffffffff82255330 t smu7_check_states_equal +ffffffff822554d0 t smu7_get_performance_level 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smu7_set_dpm_event_sources +ffffffff82257590 t smu7_get_pp_table_entry_callback_func_v0 +ffffffff82257a90 t smu7_get_pp_table_entry_callback_func_v1 +ffffffff82259000 T smu7_enable_didt_config +ffffffff822593c0 t smu7_program_pt_config_registers +ffffffff822595b0 t smu7_enable_didt +ffffffff822597a0 T smu7_disable_didt_config +ffffffff82259860 T smu7_enable_smc_cac +ffffffff822598f0 T smu7_disable_smc_cac +ffffffff82259980 T smu7_set_power_limit +ffffffff822599e0 T smu7_enable_power_containment +ffffffff82259b60 T smu7_disable_power_containment +ffffffff82259c80 T smu7_power_control_set_level +ffffffff8225a000 T smu7_fan_ctrl_get_fan_speed_info +ffffffff8225a080 T smu7_fan_ctrl_get_fan_speed_pwm +ffffffff8225a140 T smu7_fan_ctrl_get_fan_speed_rpm +ffffffff8225a1f0 T smu7_fan_ctrl_set_static_mode +ffffffff8225a320 T smu7_fan_ctrl_set_default_mode +ffffffff8225a400 T smu7_fan_ctrl_start_smc_fan_control +ffffffff8225a520 T smu7_fan_ctrl_stop_smc_fan_control +ffffffff8225a540 T smu7_fan_ctrl_set_fan_speed_pwm +ffffffff8225a720 T smu7_fan_ctrl_reset_fan_speed_to_default +ffffffff8225a900 T smu7_fan_ctrl_set_fan_speed_rpm +ffffffff8225aae0 T smu7_thermal_get_temperature +ffffffff8225ab40 T smu7_thermal_disable_alert +ffffffff8225abe0 T smu7_thermal_stop_thermal_controller +ffffffff8225ad60 T smu7_start_thermal_controller +ffffffff8225b110 T smu7_thermal_ctrl_uninitialize_thermal_controller +ffffffff8225c000 T smu8_init_function_pointers +ffffffff8225c040 t smu8_hwmgr_backend_init +ffffffff8225c520 t smu8_hwmgr_backend_fini +ffffffff8225c590 t smu8_setup_asic_task +ffffffff8225cab0 t smu8_get_power_state_size +ffffffff8225cae0 t smu8_apply_state_adjust_rules +ffffffff8225cc30 t smu8_dpm_force_dpm_level +ffffffff8225cf30 t smu8_enable_dpm_tasks +ffffffff8225d080 t smu8_disable_dpm_tasks +ffffffff8225d160 t smu8_dpm_patch_boot_state +ffffffff8225d1c0 t smu8_dpm_get_pp_table_entry +ffffffff8225d220 t smu8_dpm_get_num_of_pp_table_entries +ffffffff8225d270 t smu8_dpm_powerdown_uvd +ffffffff8225d2b0 t smu8_dpm_powergate_vce +ffffffff8225d480 t smu8_dpm_powergate_uvd +ffffffff8225d6b0 t smu8_dpm_powergate_acp +ffffffff8225d710 t smu8_dpm_get_mclk +ffffffff8225d740 t smu8_dpm_get_sclk +ffffffff8225d7b0 t smu8_set_power_state_tasks +ffffffff8225daf0 t smu8_set_cpu_power_state +ffffffff8225db60 t smu8_store_cc6_data +ffffffff8225dbe0 t smu8_get_dal_power_level +ffffffff8225dc60 t smu8_get_performance_level +ffffffff8225dd50 t smu8_get_current_shallow_sleep_clocks +ffffffff8225ddb0 t smu8_get_clock_by_type +ffffffff8225def0 t smu8_get_max_high_clocks +ffffffff8225dfb0 t smu8_power_off_asic +ffffffff8225e030 t smu8_force_clock_level +ffffffff8225e090 t smu8_print_clock_levels +ffffffff8225e260 t smu8_read_sensor +ffffffff8225e560 t smu8_notify_cac_buffer_info +ffffffff8225e610 t smu8_get_thermal_temperature_range +ffffffff8225e680 t smu8_dpm_get_pp_table_entry_callback +ffffffff8225f000 T smu9_baco_get_capability +ffffffff8225f0d0 T smu9_baco_get_state +ffffffff82260000 T convert_to_vid +ffffffff82260050 T convert_to_vddc +ffffffff822600a0 T phm_copy_clock_limits_array +ffffffff82260180 T phm_copy_overdrive_settings_limits_array +ffffffff82260260 T phm_set_field_to_u32 +ffffffff822602c0 T phm_wait_on_register +ffffffff822603d0 T phm_wait_on_indirect_register +ffffffff82260500 T phm_wait_for_register_unequal +ffffffff82260600 T phm_wait_for_indirect_register_unequal +ffffffff82260730 T phm_cf_want_uvd_power_gating +ffffffff82260760 T phm_cf_want_vce_power_gating +ffffffff82260790 T phm_trim_voltage_table +ffffffff822608c0 T phm_get_svi2_mvdd_voltage_table +ffffffff82260a50 T phm_get_svi2_vddci_voltage_table +ffffffff82260be0 T phm_get_svi2_vdd_voltage_table +ffffffff82260c80 T phm_trim_voltage_table_to_fit_state_table +ffffffff82260d60 T phm_reset_single_dpm_table +ffffffff82260e30 T phm_setup_pcie_table_entry +ffffffff82260e70 T phm_get_dpm_level_enable_mask_value +ffffffff82260f90 T phm_get_voltage_index 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vega10_get_clock_by_type_with_latency +ffffffff82269e60 t vega10_get_clock_by_type_with_voltage +ffffffff82269f40 t vega10_set_watermarks_for_clocks_ranges +ffffffff82269fa0 t vega10_display_clock_voltage_request +ffffffff8226a010 t vega10_power_off_asic +ffffffff8226a080 t vega10_force_clock_level +ffffffff8226a1b0 t vega10_emit_clock_levels +ffffffff8226a320 t vega10_print_clock_levels +ffffffff8226ab00 t vega10_get_sclk_od +ffffffff8226ab70 t vega10_set_sclk_od +ffffffff8226ac70 t vega10_get_mclk_od +ffffffff8226ace0 t vega10_set_mclk_od +ffffffff8226add0 t vega10_read_sensor +ffffffff8226b020 t vega10_avfs_enable +ffffffff8226b0e0 t vega10_notify_cac_buffer_info +ffffffff8226b190 t vega10_get_thermal_temperature_range +ffffffff8226b260 t vega10_get_power_profile_mode +ffffffff8226b2a0 t vega10_set_power_profile_mode +ffffffff8226b3c0 t vega10_odn_edit_dpm_table +ffffffff8226b980 t vega10_get_ppfeature_status +ffffffff8226ba00 t vega10_set_ppfeature_status +ffffffff8226baa0 t vega10_set_mp1_state +ffffffff8226bb10 t vega10_disable_power_features_for_compute_performance +ffffffff8226bd00 t vega10_upload_dpm_bootup_level +ffffffff8226be10 t vega10_upload_dpm_max_level +ffffffff8226bef0 t vega10_trim_voltage_table_to_fit_state_table +ffffffff8226bff0 t vega10_odn_initial_default_setting +ffffffff8226c1c0 t vega10_populate_all_graphic_levels +ffffffff8226c3c0 t vega10_populate_all_memory_levels +ffffffff8226c520 t vega10_populate_single_gfx_level +ffffffff8226c670 t vega10_populate_single_soc_level +ffffffff8226c7c0 t vega10_populate_single_memory_level +ffffffff8226c930 t vega10_get_pp_table_entry_callback_func +ffffffff8226cb50 t vega10_odn_update_power_state +ffffffff8226d000 T vega10_enable_didt_config +ffffffff8226e870 T vega10_disable_didt_config +ffffffff8226eab0 T vega10_initialize_power_tune_defaults +ffffffff8226ebe0 T vega10_set_power_limit +ffffffff8226ec30 T vega10_enable_power_containment +ffffffff8226ed50 T vega10_disable_power_containment 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vega10_thermal_disable_alert +ffffffff82272f00 T vega10_thermal_stop_thermal_controller +ffffffff82272f60 T vega10_enable_mgpu_fan_boost +ffffffff82273070 T vega10_start_thermal_controller +ffffffff822735f0 T vega10_thermal_ctrl_uninitialize_thermal_controller +ffffffff82274000 T vega12_baco_set_state +ffffffff82275000 T vega12_enable_disable_vce_dpm +ffffffff82275090 T vega12_hwmgr_init +ffffffff822750d0 t vega12_hwmgr_backend_init +ffffffff82275930 t vega12_hwmgr_backend_fini +ffffffff82275980 t vega12_setup_asic_task +ffffffff822759c0 t vega12_apply_clocks_adjust_rules +ffffffff82275da0 t vega12_dpm_force_dpm_level +ffffffff822761e0 t vega12_enable_dpm_tasks +ffffffff82276c50 t vega12_disable_dpm_tasks +ffffffff82276d40 t vega12_patch_boot_state +ffffffff82276d70 t vega12_power_gate_vce +ffffffff82276e10 t vega12_power_gate_uvd +ffffffff82276eb0 t vega12_dpm_get_mclk +ffffffff82276f00 t vega12_dpm_get_sclk +ffffffff82276f50 t vega12_notify_smc_display_config_after_ps_adjustment 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vega12_get_ppfeature_status +ffffffff822788a0 t vega12_set_ppfeature_status +ffffffff82278940 t vega12_set_mp1_state +ffffffff822789b0 t vega12_get_gpu_metrics +ffffffff82278c30 t vega12_upload_dpm_min_level +ffffffff82278e70 t vega12_upload_dpm_max_level +ffffffff82279040 t vega12_setup_single_dpm_table +ffffffff8227a000 t vega12_pp_tables_initialize +ffffffff8227a5f0 t vega12_pp_tables_uninitialize +ffffffff8227b000 T vega12_fan_ctrl_get_fan_speed_info +ffffffff8227b040 T vega12_fan_ctrl_get_fan_speed_rpm +ffffffff8227b0a0 T vega12_fan_ctrl_start_smc_fan_control +ffffffff8227b0d0 T vega12_fan_ctrl_stop_smc_fan_control +ffffffff8227b100 T vega12_fan_ctrl_reset_fan_speed_to_default +ffffffff8227b130 T vega12_thermal_get_temperature +ffffffff8227b1c0 T vega12_thermal_disable_alert +ffffffff8227b240 T vega12_thermal_stop_thermal_controller +ffffffff8227b2c0 T vega12_start_thermal_controller +ffffffff8227c000 T vega20_baco_get_capability +ffffffff8227c0c0 T vega20_baco_get_state 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vega20_enable_mgpu_fan_boost +ffffffff82283430 t vega20_get_ppfeature_status +ffffffff822834b0 t vega20_set_ppfeature_status +ffffffff822835b0 t vega20_set_mp1_state +ffffffff82283630 t vega20_smu_i2c_bus_access +ffffffff822836b0 t vega20_set_df_cstate +ffffffff82283720 t vega20_set_xgmi_pstate +ffffffff82283780 t vega20_get_gpu_metrics +ffffffff82283a20 t vega20_upload_dpm_min_level +ffffffff82283ca0 t vega20_upload_dpm_max_level +ffffffff82283ed0 t vega20_setup_single_dpm_table +ffffffff82284000 T vega20_set_power_limit +ffffffff82284050 T vega20_validate_power_level_request +ffffffff82284080 T vega20_power_control_set_level +ffffffff82285000 t vega20_pp_tables_initialize +ffffffff82285730 t vega20_pp_tables_uninitialize +ffffffff82286000 T vega20_fan_ctrl_stop_smc_fan_control +ffffffff82286090 T vega20_fan_ctrl_start_smc_fan_control +ffffffff82286120 T vega20_fan_ctrl_get_fan_speed_pwm +ffffffff82286240 T vega20_fan_ctrl_set_fan_speed_pwm +ffffffff82286430 t vega20_fan_ctrl_set_static_mode +ffffffff822865e0 T vega20_fan_ctrl_get_fan_speed_info +ffffffff82286620 T vega20_fan_ctrl_get_fan_speed_rpm +ffffffff82286680 T vega20_fan_ctrl_set_fan_speed_rpm +ffffffff82286810 T vega20_thermal_get_temperature +ffffffff822868a0 T vega20_thermal_disable_alert +ffffffff82286920 T vega20_thermal_stop_thermal_controller +ffffffff822869a0 T vega20_start_thermal_controller +ffffffff82287000 t ci_smu_init +ffffffff82287060 t ci_smu_fini +ffffffff822870b0 t ci_start_smu +ffffffff822870e0 t ci_send_msg_to_smc +ffffffff82287180 t ci_send_msg_to_smc_with_parameter +ffffffff82287230 t ci_update_smc_table +ffffffff82287470 t ci_process_firmware_header +ffffffff82287980 t ci_update_sclk_threshold +ffffffff82287bc0 t ci_thermal_setup_fan_table +ffffffff82287e40 t ci_init_smc_table +ffffffff822898e0 t ci_populate_all_graphic_levels +ffffffff82289dc0 t ci_populate_all_memory_levels +ffffffff8228a6b0 t ci_initialize_mc_reg_table +ffffffff8228b230 t ci_get_offsetof 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smum_upload_powerplay_table +ffffffff8229f250 T smum_send_msg_to_smc +ffffffff8229f310 T smum_send_msg_to_smc_with_parameter +ffffffff8229f3e0 T smum_init_smc_table +ffffffff8229f420 T smum_populate_all_graphic_levels +ffffffff8229f460 T smum_populate_all_memory_levels +ffffffff8229f4a0 T smum_initialize_mc_reg_table +ffffffff8229f4e0 T smum_is_dpm_running +ffffffff8229f520 T smum_is_hw_avfs_present +ffffffff8229f560 T smum_update_dpm_settings +ffffffff8229f5a0 T smum_smc_table_manager +ffffffff8229f5f0 T smum_stop_smc +ffffffff822a0000 t tonga_smu_init +ffffffff822a0090 t tonga_start_smu +ffffffff822a0420 t tonga_update_smc_table +ffffffff822a05c0 t tonga_process_firmware_header +ffffffff822a0700 t tonga_update_sclk_threshold +ffffffff822a0940 t tonga_thermal_setup_fan_table +ffffffff822a0bc0 t tonga_init_smc_table +ffffffff822a2a10 t tonga_populate_all_graphic_levels +ffffffff822a2ff0 t tonga_populate_all_memory_levels +ffffffff822a36d0 t tonga_initialize_mc_reg_table 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vega20_get_activity_monitor_coeff +ffffffff822a72b0 T vega20_enable_smc_features +ffffffff822a7380 T vega20_get_enabled_smc_features +ffffffff822a7450 T vega20_set_pptable_driver_address +ffffffff822a74e0 t vega20_smu_init +ffffffff822a78a0 t vega20_smu_fini +ffffffff822a79a0 t vega20_start_smu +ffffffff822a7a80 t vega20_get_argument +ffffffff822a7ae0 t vega20_send_msg_to_smc +ffffffff822a7d30 t vega20_send_msg_to_smc_with_parameter +ffffffff822a7fd0 t vega20_is_dpm_running +ffffffff822a8070 t vega20_smc_table_manager +ffffffff822a9000 t vegam_smu_init +ffffffff822a9090 t vegam_start_smu +ffffffff822a9460 t vegam_update_smc_table +ffffffff822a96d0 t vegam_process_firmware_header +ffffffff822a9810 t vegam_update_sclk_threshold +ffffffff822a98f0 t vegam_thermal_setup_fan_table +ffffffff822a9950 t vegam_thermal_avfs_enable +ffffffff822a99e0 t vegam_init_smc_table +ffffffff822ab2c0 t vegam_populate_all_graphic_levels +ffffffff822ab9f0 t vegam_populate_all_memory_levels +ffffffff822abd30 t vegam_get_offsetof +ffffffff822abdc0 t vegam_get_mac_definition +ffffffff822abe20 t vegam_is_dpm_running +ffffffff822abe70 t vegam_is_hw_avfs_present +ffffffff822abec0 t vegam_program_memory_timing_parameters +ffffffff822ac0e0 t vegam_get_dependency_volt_by_clk +ffffffff822ac2c0 t vegam_calculate_sclk_params +ffffffff822ad000 T smu_set_residency_gfxoff +ffffffff822ad050 T smu_get_residency_gfxoff +ffffffff822ad0a0 T smu_get_entrycount_gfxoff +ffffffff822ad0f0 T smu_get_status_gfxoff +ffffffff822ad140 T smu_set_soft_freq_range +ffffffff822ad180 T smu_get_dpm_freq_range +ffffffff822ad1d0 T smu_set_gfx_power_up_by_imu +ffffffff822ad220 T is_support_sw_smu +ffffffff822ad260 T is_support_cclk_dpm +ffffffff822ad2c0 T smu_allow_xgmi_power_down +ffffffff822ad380 T smu_write_watermarks_table +ffffffff822ad3f0 T smu_set_ac_dc +ffffffff822ad4f0 t smu_early_init +ffffffff822ad750 t smu_late_init +ffffffff822adf00 t smu_sw_init +ffffffff822ae730 t smu_sw_fini +ffffffff822ae980 t smu_hw_init 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smu_emit_ppclk_levels +ffffffff822afa00 t smu_force_performance_level +ffffffff822afc90 t smu_read_sensor +ffffffff822afe80 t smu_get_performance_level +ffffffff822afef0 t smu_get_current_power_state +ffffffff822aff50 t smu_get_fan_speed_rpm +ffffffff822affb0 t smu_set_fan_speed_rpm +ffffffff822b0060 t smu_get_power_num_states +ffffffff822b00e0 t smu_sys_get_pp_table +ffffffff822b0150 t smu_sys_set_pp_table +ffffffff822b0340 t smu_switch_power_profile +ffffffff822b0450 t smu_handle_dpm_task +ffffffff822b0500 t smu_load_microcode +ffffffff822b05e0 t smu_dpm_set_power_gate +ffffffff822b0960 t smu_set_power_limit +ffffffff822b0a90 t smu_get_power_profile_mode +ffffffff822b0af0 t smu_set_power_profile_mode +ffffffff822b0b50 t smu_od_edit_dpm_table +ffffffff822b0bb0 t smu_set_mp1_state +ffffffff822b0c00 t smu_gfx_state_change_set +ffffffff822b0c40 t smu_get_sclk +ffffffff822b0cb0 t smu_get_mclk +ffffffff822b0d30 t smu_display_configuration_change +ffffffff822b0dc0 t smu_get_clock_by_type_with_latency +ffffffff822b0e70 t smu_display_clock_voltage_request +ffffffff822b0ed0 t smu_enable_mgpu_fan_boost +ffffffff822b0f30 t smu_set_display_count +ffffffff822b0f90 t smu_set_deep_sleep_dcefclk +ffffffff822b0ff0 t smu_get_baco_capability +ffffffff822b1050 t smu_baco_set_state +ffffffff822b1130 t smu_sys_get_pp_feature_mask +ffffffff822b11a0 t smu_sys_set_pp_feature_mask +ffffffff822b1200 t smu_mode2_reset +ffffffff822b12a0 t smu_set_df_cstate +ffffffff822b1350 t smu_set_xgmi_pstate +ffffffff822b1400 t smu_sys_get_gpu_metrics +ffffffff822b1460 t smu_set_watermarks_for_clock_ranges +ffffffff822b14e0 t smu_display_disable_memory_clock_switch +ffffffff822b1540 t smu_get_max_sustainable_clocks_by_dc +ffffffff822b15a0 t smu_get_uclk_dpm_states +ffffffff822b1600 t smu_get_dpm_clock_table +ffffffff822b1660 t smu_get_prv_buffer_details +ffffffff822b16d0 t smu_adjust_power_state_dynamic +ffffffff822b1930 t smu_throttling_logging_work_fn +ffffffff822b1980 t smu_interrupt_work_fn +ffffffff822b19d0 t smu_smc_hw_setup +ffffffff822b2330 t smu_smc_hw_cleanup +ffffffff822b3000 T arcturus_set_ppt_funcs +ffffffff822b3050 t arcturus_run_btc +ffffffff822b3100 t arcturus_get_allowed_feature_mask +ffffffff822b3150 t arcturus_set_default_dpm_table +ffffffff822b3360 t arcturus_populate_umd_state_clk +ffffffff822b3420 t arcturus_print_clk_levels +ffffffff822b3670 t arcturus_force_clk_levels +ffffffff822b38b0 t arcturus_get_power_profile_mode +ffffffff822b3b40 t arcturus_set_power_profile_mode +ffffffff822b3e30 t arcturus_dpm_set_vcn_enable +ffffffff822b3f00 t arcturus_read_sensor +ffffffff822b40e0 t arcturus_is_dpm_running +ffffffff822b4130 t arcturus_get_fan_speed_pwm +ffffffff822b4270 t arcturus_get_fan_speed_rpm +ffffffff822b4370 t arcturus_get_thermal_temperature_range +ffffffff822b4460 t arcturus_set_performance_level +ffffffff822b4570 t arcturus_dump_pptable +ffffffff822b45a0 t arcturus_get_power_limit +ffffffff822b46a0 t arcturus_set_df_cstate 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navi10_read_sensor +ffffffff822b9d80 t navi10_pre_display_config_changed +ffffffff822b9e10 t navi10_display_config_changed +ffffffff822b9e90 t navi10_notify_smc_display_config +ffffffff822ba020 t navi10_is_dpm_running +ffffffff822ba070 t navi10_get_fan_speed_rpm +ffffffff822ba100 t navi10_set_watermarks_table +ffffffff822ba2a0 t navi10_get_thermal_temperature_range +ffffffff822ba390 t navi10_get_uclk_dpm_states +ffffffff822ba4a0 t navi10_set_default_od_settings +ffffffff822ba700 t navi10_display_disable_memory_clock_switch +ffffffff822ba780 t navi10_get_power_limit +ffffffff822ba8a0 t navi10_update_pcie_parameters +ffffffff822baa00 t navi10_i2c_control_init +ffffffff822bab30 t navi10_i2c_control_fini +ffffffff822bab70 t navi10_init_smc_tables +ffffffff822bada0 t navi10_setup_pptable +ffffffff822bafb0 t navi10_baco_enter +ffffffff822bb000 t navi10_baco_exit +ffffffff822bb100 t navi1x_get_gpu_metrics +ffffffff822bbaa0 t navi10_enable_mgpu_fan_boost +ffffffff822bbb10 t navi10_get_fan_parameters +ffffffff822bbb50 t navi10_post_smu_init +ffffffff822bbe40 t navi10_get_default_config_table_settings +ffffffff822bbe90 t navi10_set_config_table +ffffffff822bbf40 t navi1x_get_smu_metrics_data +ffffffff822bc3a0 t navi10_get_smu_metrics_data +ffffffff822bc5d0 t navi10_i2c_xfer +ffffffff822bc880 t navi10_i2c_func +ffffffff822bc8b0 t navi10_umc_hybrid_cdr_workaround +ffffffff822bd000 T sienna_cichlid_set_ppt_funcs +ffffffff822bd050 t sienna_cichlid_run_btc +ffffffff822bd0d0 t sienna_cichlid_get_allowed_feature_mask +ffffffff822bd350 t sienna_cichlid_set_default_dpm_table +ffffffff822bd920 t sienna_cichlid_populate_umd_state_clk +ffffffff822bd9d0 t sienna_cichlid_print_clk_levels +ffffffff822bdbb0 t sienna_cichlid_force_clk_levels +ffffffff822bdce0 t sienna_cichlid_od_edit_dpm_table +ffffffff822be270 t sienna_cichlid_restore_user_od_settings +ffffffff822be2f0 t sienna_cichlid_get_power_profile_mode +ffffffff822be550 t sienna_cichlid_set_power_profile_mode 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sienna_cichlid_i2c_control_fini +ffffffff822bf930 t sienna_cichlid_get_unique_id +ffffffff822bfa80 t sienna_cichlid_init_smc_tables +ffffffff822bfd90 t sienna_cichlid_set_mp1_state +ffffffff822bfdd0 t sienna_cichlid_setup_pptable +ffffffff822c0230 t sienna_cichlid_system_features_control +ffffffff822c02c0 t sienna_cichlid_baco_enter +ffffffff822c0310 t sienna_cichlid_baco_exit +ffffffff822c0410 t sienna_cichlid_is_mode1_reset_supported +ffffffff822c0490 t sienna_cichlid_is_mode2_reset_supported +ffffffff822c04c0 t sienna_cichlid_mode2_reset +ffffffff822c05f0 t sienna_cichlid_get_dpm_ultimate_freq +ffffffff822c0600 t sienna_cichlid_get_gpu_metrics +ffffffff822c0a80 t sienna_cichlid_enable_mgpu_fan_boost +ffffffff822c0ad0 t sienna_cichlid_get_fan_parameters +ffffffff822c0b10 t sienna_cichlid_gpo_control +ffffffff822c0bc0 t sienna_cichlid_get_ecc_info +ffffffff822c0cb0 t sienna_cichlid_stb_get_data_direct +ffffffff822c0d50 t sienna_cichlid_get_default_config_table_settings +ffffffff822c0db0 t sienna_cichlid_set_config_table +ffffffff822c0e80 t sienna_cichlid_get_smu_metrics_data +ffffffff822c12c0 t sienna_cichlid_get_throttler_status_locked +ffffffff822c1440 t sienna_cichlid_get_smartshift_power_percentage +ffffffff822c1570 t sienna_cichlid_i2c_xfer +ffffffff822c1820 t sienna_cichlid_i2c_func +ffffffff822c2000 T smu_v11_0_init_microcode +ffffffff822c22a0 T smu_v11_0_fini_microcode +ffffffff822c2320 T smu_v11_0_load_microcode +ffffffff822c2460 T smu_v11_0_check_fw_status +ffffffff822c24b0 T smu_v11_0_check_fw_version +ffffffff822c2660 T smu_v11_0_setup_pptable +ffffffff822c2780 T smu_v11_0_init_smc_tables +ffffffff822c28d0 T smu_v11_0_fini_smc_tables +ffffffff822c2b00 T smu_v11_0_init_power +ffffffff822c2b80 T smu_v11_0_fini_power +ffffffff822c2be0 T smu_v11_0_get_vbios_bootup_values +ffffffff822c2f30 T smu_v11_0_notify_memory_pool_location +ffffffff822c3020 T smu_v11_0_set_min_deep_sleep_dcefclk +ffffffff822c30a0 T smu_v11_0_set_driver_table_location +ffffffff822c3110 T smu_v11_0_set_tool_table_location +ffffffff822c3180 T smu_v11_0_init_display_count +ffffffff822c31d0 T smu_v11_0_set_allowed_mask +ffffffff822c32a0 T smu_v11_0_system_features_control +ffffffff822c32c0 T smu_v11_0_notify_display_change +ffffffff822c3330 T smu_v11_0_init_max_sustainable_clocks +ffffffff822c35a0 t smu_v11_0_get_max_sustainable_clock +ffffffff822c36c0 T smu_v11_0_get_current_power_limit +ffffffff822c3790 T smu_v11_0_set_power_limit +ffffffff822c38d0 T smu_v11_0_interrupt_work +ffffffff822c3950 T smu_v11_0_enable_thermal_alert +ffffffff822c39e0 T smu_v11_0_disable_thermal_alert +ffffffff822c3a00 T smu_v11_0_get_gfx_vdd +ffffffff822c3ac0 T smu_v11_0_display_clock_voltage_request +ffffffff822c3c00 T smu_v11_0_set_hard_freq_limited_range +ffffffff822c3ce0 T smu_v11_0_gfx_off_control +ffffffff822c3d50 T smu_v11_0_get_fan_control_mode +ffffffff822c3da0 T smu_v11_0_set_fan_speed_pwm +ffffffff822c3f30 t smu_v11_0_set_fan_static_mode +ffffffff822c40e0 T smu_v11_0_set_fan_speed_rpm +ffffffff822c4200 T smu_v11_0_get_fan_speed_pwm +ffffffff822c4330 T smu_v11_0_get_fan_speed_rpm +ffffffff822c4430 T smu_v11_0_set_fan_control_mode +ffffffff822c45d0 T smu_v11_0_set_xgmi_pstate +ffffffff822c45f0 T smu_v11_0_register_irq_handler +ffffffff822c46b0 T smu_v11_0_get_max_sustainable_clocks_by_dc +ffffffff822c4740 T smu_v11_0_set_azalia_d3_pme +ffffffff822c4760 T smu_v11_0_baco_set_armd3_sequence +ffffffff822c4780 T smu_v11_0_baco_is_support +ffffffff822c4800 T smu_v11_0_baco_get_state +ffffffff822c4830 T smu_v11_0_baco_set_state +ffffffff822c4ae0 T smu_v11_0_baco_enter +ffffffff822c4bd0 T smu_v11_0_baco_exit +ffffffff822c4c70 T smu_v11_0_mode1_reset +ffffffff822c4cf0 T smu_v11_0_handle_passthrough_sbr +ffffffff822c4d10 T smu_v11_0_get_dpm_ultimate_freq +ffffffff822c4e50 T smu_v11_0_set_soft_freq_limited_range +ffffffff822c4f30 T smu_v11_0_set_performance_level +ffffffff822c5280 T smu_v11_0_set_power_source +ffffffff822c52e0 T smu_v11_0_get_dpm_freq_by_index +ffffffff822c5380 T smu_v11_0_get_dpm_level_count +ffffffff822c5410 T smu_v11_0_set_single_dpm_table +ffffffff822c55f0 T smu_v11_0_get_dpm_level_range +ffffffff822c5750 T smu_v11_0_get_current_pcie_link_width_level +ffffffff822c57a0 T smu_v11_0_get_current_pcie_link_width +ffffffff822c5800 T smu_v11_0_get_current_pcie_link_speed_level +ffffffff822c5850 T smu_v11_0_get_current_pcie_link_speed +ffffffff822c58a0 T smu_v11_0_gfx_ulv_control +ffffffff822c5910 T smu_v11_0_deep_sleep_control +ffffffff822c5ac0 T smu_v11_0_restore_user_od_settings +ffffffff822c5b50 T smu_v11_0_set_smu_mailbox_registers +ffffffff822c5bc0 t smu_v11_0_set_irq_state +ffffffff822c6140 t smu_v11_0_irq_process +ffffffff822c6440 t orderly_poweroff +ffffffff822c7000 T vangogh_set_ppt_funcs +ffffffff822c7040 t vangogh_set_default_dpm_tables +ffffffff822c7060 t vangogh_common_print_clk_levels +ffffffff822c74b0 t vangogh_force_clk_levels +ffffffff822c76e0 t vangogh_od_edit_dpm_table +ffffffff822c7c30 t vangogh_get_power_profile_mode +ffffffff822c7d00 t vangogh_set_power_profile_mode +ffffffff822c7e20 t vangogh_dpm_set_vcn_enable +ffffffff822c7e70 t vangogh_dpm_set_jpeg_enable +ffffffff822c7ec0 t vangogh_read_sensor +ffffffff822c7ff0 t vangogh_is_dpm_running +ffffffff822c8050 t vangogh_set_watermarks_table +ffffffff822c81e0 t vangogh_set_performance_level +ffffffff822c8b00 t vangogh_get_power_limit +ffffffff822c8c80 t vangogh_get_ppt_limit +ffffffff822c8ce0 t vangogh_get_dpm_clock_table +ffffffff822c8e50 t vangogh_init_smc_tables +ffffffff822c90a0 t vangogh_system_features_control +ffffffff822c90f0 t vangogh_set_power_limit +ffffffff822c9250 t vangogh_get_gfxoff_status +ffffffff822c92d0 t vangogh_get_gfxoff_entrycount +ffffffff822c9340 t vangogh_set_gfxoff_residency +ffffffff822c93b0 t vangogh_get_gfxoff_residency +ffffffff822c93e0 t vangogh_mode2_reset +ffffffff822c9520 t vangogh_common_get_gpu_metrics +ffffffff822c9b60 t vangogh_post_smu_init +ffffffff822c9d00 t vangogh_set_fine_grain_gfx_freq_parameters +ffffffff822c9d70 t vangogh_common_get_smu_metrics_data +ffffffff822ca0c0 t vangogh_force_dpm_limit_value +ffffffff822ca200 t vangogh_get_dpm_ultimate_freq +ffffffff822ca5c0 t vangogh_set_soft_freq_limited_range +ffffffff822cb000 T renoir_set_ppt_funcs +ffffffff822cb0a0 t renoir_get_current_power_state +ffffffff822cb110 t renoir_print_clk_levels +ffffffff822cb370 t renoir_force_clk_levels +ffffffff822cb5a0 t renoir_od_edit_dpm_table +ffffffff822cb8a0 t renoir_get_power_profile_mode +ffffffff822cb970 t renoir_set_power_profile_mode +ffffffff822cba90 t renoir_dpm_set_vcn_enable +ffffffff822cbb10 t renoir_dpm_set_jpeg_enable +ffffffff822cbb90 t renoir_read_sensor +ffffffff822cbf80 t renoir_is_dpm_running +ffffffff822cbfb0 t renoir_set_watermarks_table +ffffffff822cc150 t renoir_set_performance_level +ffffffff822cc690 t renoir_get_dpm_clock_table +ffffffff822cc9d0 t renoir_init_smc_tables +ffffffff822ccb40 t renoir_get_enabled_mask +ffffffff822ccb80 t renoir_get_dpm_ultimate_freq +ffffffff822cce20 t renoir_get_gpu_metrics +ffffffff822cd040 t renoir_gfx_state_change_set +ffffffff822cd070 t renoir_set_fine_grain_gfx_freq_parameters +ffffffff822cd100 t renoir_force_dpm_limit_value +ffffffff822ce000 T smu_v12_0_check_fw_status +ffffffff822ce050 T smu_v12_0_check_fw_version +ffffffff822ce110 T smu_v12_0_powergate_sdma +ffffffff822ce150 T smu_v12_0_set_gfx_cgpg +ffffffff822ce1b0 T smu_v12_0_get_gfxoff_status +ffffffff822ce230 T smu_v12_0_gfx_off_control +ffffffff822ce340 T smu_v12_0_fini_smc_tables +ffffffff822ce3f0 T smu_v12_0_set_default_dpm_tables +ffffffff822ce410 T smu_v12_0_mode2_reset +ffffffff822ce430 T smu_v12_0_set_soft_freq_limited_range +ffffffff822ce560 T smu_v12_0_set_driver_table_location +ffffffff822ce5d0 T smu_v12_0_get_vbios_bootup_values +ffffffff822cf000 T aldebaran_set_ppt_funcs +ffffffff822cf040 t aldebaran_get_allowed_feature_mask +ffffffff822cf090 t aldebaran_set_default_dpm_table +ffffffff822cf290 t aldebaran_populate_umd_state_clk +ffffffff822cf390 t aldebaran_print_clk_levels +ffffffff822cf550 t aldebaran_force_clk_levels +ffffffff822cf700 t aldebaran_usr_edit_dpm_table +ffffffff822cf920 t aldebaran_read_sensor +ffffffff822cfbc0 t aldebaran_is_dpm_running +ffffffff822cfc10 t aldebaran_get_thermal_temperature_range +ffffffff822cfcd0 t aldebaran_set_performance_level +ffffffff822cfd70 t aldebaran_get_power_limit +ffffffff822cff00 t aldebaran_set_df_cstate +ffffffff822cff80 t aldebaran_allow_xgmi_power_down +ffffffff822d0010 t aldebaran_i2c_control_init +ffffffff822d00d0 t aldebaran_i2c_control_fini +ffffffff822d0110 t aldebaran_get_unique_id +ffffffff822d01f0 t aldebaran_init_smc_tables +ffffffff822d0380 t aldebaran_set_mp1_state +ffffffff822d03c0 t aldebaran_setup_pptable +ffffffff822d0480 t aldebaran_system_features_control +ffffffff822d05e0 t aldebaran_set_power_limit +ffffffff822d0670 t aldebaran_is_baco_supported +ffffffff822d06a0 t aldebaran_is_mode1_reset_supported +ffffffff822d06d0 t aldebaran_is_mode2_reset_supported +ffffffff822d0700 t aldebaran_mode1_reset +ffffffff822d07e0 t aldebaran_mode2_reset +ffffffff822d0990 t aldebaran_set_soft_freq_limited_range +ffffffff822d0b90 t aldebaran_log_thermal_throttling_event +ffffffff822d0ea0 t aldebaran_get_gpu_metrics +ffffffff822d1130 t aldebaran_smu_handle_passthrough_sbr +ffffffff822d1150 t aldebaran_smu_send_hbm_bad_page_num +ffffffff822d11d0 t aldebaran_get_ecc_info +ffffffff822d1330 t aldebaran_send_hbm_bad_channel_flag +ffffffff822d1410 t aldebaran_get_current_clk_freq_by_table +ffffffff822d1550 t aldebaran_get_smu_metrics_data +ffffffff822d17a0 t aldebaran_upload_dpm_level +ffffffff822d1890 t aldebaran_i2c_xfer +ffffffff822d1b40 t aldebaran_i2c_func +ffffffff822d2000 T smu_v13_0_init_microcode +ffffffff822d21d0 T smu_v13_0_fini_microcode +ffffffff822d2250 T smu_v13_0_load_microcode +ffffffff822d2280 T smu_v13_0_init_pptable_microcode +ffffffff822d2420 T smu_v13_0_get_pptable_from_firmware +ffffffff822d2540 T smu_v13_0_check_fw_status +ffffffff822d25b0 T smu_v13_0_check_fw_version +ffffffff822d26e0 T smu_v13_0_setup_pptable +ffffffff822d2880 T smu_v13_0_init_smc_tables +ffffffff822d29c0 T smu_v13_0_fini_smc_tables +ffffffff822d2bb0 T smu_v13_0_init_power +ffffffff822d2c30 T smu_v13_0_fini_power +ffffffff822d2cb0 T smu_v13_0_get_vbios_bootup_values +ffffffff822d2f50 T smu_v13_0_notify_memory_pool_location +ffffffff822d3010 T smu_v13_0_set_min_deep_sleep_dcefclk +ffffffff822d3090 T smu_v13_0_set_driver_table_location +ffffffff822d3100 T smu_v13_0_set_tool_table_location +ffffffff822d3170 T smu_v13_0_init_display_count +ffffffff822d31b0 T smu_v13_0_set_allowed_mask +ffffffff822d3280 T smu_v13_0_gfx_off_control +ffffffff822d32f0 T smu_v13_0_system_features_control +ffffffff822d3310 T smu_v13_0_notify_display_change +ffffffff822d3380 T smu_v13_0_init_max_sustainable_clocks +ffffffff822d35f0 t smu_v13_0_get_max_sustainable_clock +ffffffff822d3710 T smu_v13_0_get_current_power_limit +ffffffff822d37e0 T smu_v13_0_set_power_limit +ffffffff822d3900 T smu_v13_0_enable_thermal_alert +ffffffff822d3980 T smu_v13_0_disable_thermal_alert +ffffffff822d39c0 T smu_v13_0_get_gfx_vdd +ffffffff822d3a80 T smu_v13_0_display_clock_voltage_request +ffffffff822d3bc0 T smu_v13_0_set_hard_freq_limited_range +ffffffff822d3ca0 T smu_v13_0_get_fan_control_mode +ffffffff822d3ce0 T smu_v13_0_set_fan_speed_pwm +ffffffff822d3ef0 t smu_v13_0_set_fan_static_mode +ffffffff822d40b0 T smu_v13_0_set_fan_control_mode +ffffffff822d4210 T smu_v13_0_set_fan_speed_rpm +ffffffff822d43b0 T smu_v13_0_set_xgmi_pstate +ffffffff822d43d0 T smu_v13_0_register_irq_handler +ffffffff822d4490 T smu_v13_0_get_max_sustainable_clocks_by_dc +ffffffff822d4520 T smu_v13_0_set_azalia_d3_pme +ffffffff822d4540 T smu_v13_0_wait_for_event +ffffffff822d4590 T smu_v13_0_get_dpm_ultimate_freq +ffffffff822d46e0 T smu_v13_0_set_soft_freq_limited_range +ffffffff822d47c0 T smu_v13_0_set_performance_level +ffffffff822d4f50 T smu_v13_0_set_power_source +ffffffff822d4fb0 T smu_v13_0_set_single_dpm_table +ffffffff822d5240 T smu_v13_0_get_dpm_level_range +ffffffff822d53c0 T smu_v13_0_get_current_pcie_link_width_level +ffffffff822d5410 T smu_v13_0_get_current_pcie_link_width +ffffffff822d5470 T smu_v13_0_get_current_pcie_link_speed_level +ffffffff822d54c0 T smu_v13_0_get_current_pcie_link_speed +ffffffff822d5510 T smu_v13_0_set_vcn_enable +ffffffff822d55c0 T smu_v13_0_set_jpeg_enable +ffffffff822d55e0 T smu_v13_0_run_btc +ffffffff822d5660 T smu_v13_0_gpo_control +ffffffff822d56f0 T smu_v13_0_deep_sleep_control +ffffffff822d5950 T smu_v13_0_gfx_ulv_control +ffffffff822d59c0 T smu_v13_0_baco_set_armd3_sequence +ffffffff822d59e0 T smu_v13_0_baco_is_support +ffffffff822d5a60 T smu_v13_0_baco_get_state +ffffffff822d5a90 T smu_v13_0_baco_set_state +ffffffff822d5b50 T smu_v13_0_baco_enter +ffffffff822d5c60 T smu_v13_0_baco_exit +ffffffff822d5cf0 T smu_v13_0_set_gfx_power_up_by_imu +ffffffff822d5d20 T smu_v13_0_od_edit_dpm_table +ffffffff822d5ff0 T smu_v13_0_set_default_dpm_tables +ffffffff822d6010 T smu_v13_0_set_smu_mailbox_registers +ffffffff822d6080 T smu_v13_0_mode1_reset +ffffffff822d6100 t smu_v13_0_set_irq_state +ffffffff822d6680 t smu_v13_0_irq_process +ffffffff822d6970 t orderly_poweroff +ffffffff822d7000 T smu_v13_0_0_set_ppt_funcs +ffffffff822d70e0 t smu_v13_0_0_get_allowed_feature_mask +ffffffff822d7220 t smu_v13_0_0_set_default_dpm_table +ffffffff822d7640 t smu_v13_0_0_populate_umd_state_clk +ffffffff822d7770 t smu_v13_0_0_print_clk_levels +ffffffff822d7890 t smu_v13_0_0_force_clk_levels +ffffffff822d7a10 t smu_v13_0_0_get_power_profile_mode +ffffffff822d7c70 t smu_v13_0_0_set_power_profile_mode +ffffffff822d7ec0 t smu_v13_0_0_read_sensor +ffffffff822d80e0 t smu_v13_0_0_is_dpm_running +ffffffff822d8130 t smu_v13_0_0_get_fan_speed_pwm +ffffffff822d8210 t smu_v13_0_0_get_fan_speed_rpm +ffffffff822d8280 t smu_v13_0_0_get_thermal_temperature_range +ffffffff822d8380 t smu_v13_0_0_dump_pptable +ffffffff822d83b0 t smu_v13_0_0_get_power_limit +ffffffff822d8490 t smu_v13_0_0_set_df_cstate +ffffffff822d84b0 t smu_v13_0_0_update_pcie_parameters +ffffffff822d8590 t smu_v13_0_0_i2c_control_init +ffffffff822d86c0 t smu_v13_0_0_i2c_control_fini +ffffffff822d8700 t smu_v13_0_0_get_unique_id +ffffffff822d87b0 t smu_v13_0_0_init_smc_tables +ffffffff822d89a0 t smu_v13_0_0_set_mp1_state +ffffffff822d89e0 t smu_v13_0_0_setup_pptable +ffffffff822d8b20 t smu_v13_0_0_system_features_control +ffffffff822d8b30 t smu_v13_0_0_baco_enter +ffffffff822d8b80 t smu_v13_0_0_baco_exit +ffffffff822d8be0 t smu_v13_0_0_is_mode1_reset_supported +ffffffff822d8c30 t smu_v13_0_0_mode1_reset +ffffffff822d8cc0 t smu_v13_0_0_get_dpm_ultimate_freq +ffffffff822d8dd0 t smu_v13_0_0_get_gpu_metrics +ffffffff822d91f0 t smu_v13_0_0_enable_mgpu_fan_boost +ffffffff822d9240 t smu_v13_0_0_smu_send_bad_mem_page_num +ffffffff822d92c0 t smu_v13_0_0_send_bad_mem_channel_flag +ffffffff822d9340 t smu_v13_0_0_get_smu_metrics_data +ffffffff822d96b0 t smu_v13_0_get_throttler_status +ffffffff822d9870 t smu_v13_0_0_i2c_xfer +ffffffff822d9b20 t smu_v13_0_0_i2c_func +ffffffff822da000 T smu_v13_0_4_set_ppt_funcs +ffffffff822da0b0 t smu_v13_0_4_print_clk_levels +ffffffff822da170 t smu_v13_0_4_force_clk_levels +ffffffff822da410 t smu_v13_0_4_read_sensor +ffffffff822da6c0 t smu_v13_0_4_is_dpm_running +ffffffff822da710 t smu_v13_0_4_set_watermarks_table +ffffffff822da8a0 t smu_v13_0_4_set_performance_level +ffffffff822dadd0 t smu_v13_0_4_init_smc_tables +ffffffff822daf40 t smu_v13_0_4_fini_smc_tables +ffffffff822daff0 t smu_v13_0_4_system_features_control +ffffffff822db040 t smu_v13_0_4_mode2_reset +ffffffff822db060 t smu_v13_0_4_get_dpm_ultimate_freq +ffffffff822db480 t smu_v13_0_4_get_gpu_metrics +ffffffff822db650 t smu_v13_0_4_set_fine_grain_gfx_freq_parameters +ffffffff822db6a0 t smu_v13_0_4_get_smu_metrics_data +ffffffff822dc000 T smu_v13_0_5_set_ppt_funcs +ffffffff822dc090 t smu_v13_0_5_set_default_dpm_tables +ffffffff822dc0b0 t smu_v13_0_5_print_clk_levels +ffffffff822dc160 t smu_v13_0_5_force_clk_levels +ffffffff822dc2c0 t smu_v13_0_5_od_edit_dpm_table +ffffffff822dc590 t smu_v13_0_5_dpm_set_vcn_enable +ffffffff822dc5b0 t smu_v13_0_5_dpm_set_jpeg_enable +ffffffff822dc5d0 t smu_v13_0_5_read_sensor +ffffffff822dc7f0 t smu_v13_0_5_is_dpm_running +ffffffff822dc840 t smu_v13_0_5_set_watermarks_table +ffffffff822dc9d0 t smu_v13_0_5_set_performance_level +ffffffff822dcbb0 t smu_v13_0_5_init_smc_tables +ffffffff822dcd20 t smu_v13_0_5_fini_smc_tables +ffffffff822dcdd0 t smu_v13_0_5_system_features_control +ffffffff822dce20 t smu_v13_0_5_mode2_reset +ffffffff822dcea0 t smu_v13_0_5_get_dpm_ultimate_freq +ffffffff822dd2e0 t smu_v13_0_5_get_gpu_metrics +ffffffff822dd420 t smu_v13_0_5_set_fine_grain_gfx_freq_parameters +ffffffff822dd470 t smu_v13_0_5_get_smu_metrics_data +ffffffff822de000 T smu_v13_0_7_set_ppt_funcs +ffffffff822de050 t smu_v13_0_7_get_allowed_feature_mask +ffffffff822de1c0 t smu_v13_0_7_set_default_dpm_table +ffffffff822de5b0 t smu_v13_0_7_populate_umd_state_clk +ffffffff822de6b0 t smu_v13_0_7_print_clk_levels +ffffffff822de7d0 t smu_v13_0_7_force_clk_levels +ffffffff822de950 t smu_v13_0_7_get_power_profile_mode +ffffffff822dec30 t smu_v13_0_7_set_power_profile_mode +ffffffff822dee70 t smu_v13_0_7_read_sensor +ffffffff822df080 t smu_v13_0_7_is_dpm_running +ffffffff822df0d0 t smu_v13_0_7_get_fan_speed_pwm +ffffffff822df1b0 t smu_v13_0_7_get_fan_speed_rpm +ffffffff822df220 t smu_v13_0_7_get_thermal_temperature_range +ffffffff822df310 t smu_v13_0_7_dump_pptable +ffffffff822df340 t smu_v13_0_7_get_power_limit +ffffffff822df420 t smu_v13_0_7_set_df_cstate +ffffffff822df440 t smu_v13_0_7_update_pcie_parameters +ffffffff822df520 t smu_v13_0_7_init_smc_tables +ffffffff822df710 t smu_v13_0_7_check_fw_status +ffffffff822df760 t smu_v13_0_7_set_mp1_state +ffffffff822df7a0 t smu_v13_0_7_setup_pptable +ffffffff822df900 t smu_v13_0_7_baco_enter +ffffffff822df950 t smu_v13_0_7_baco_exit +ffffffff822df9b0 t smu_v13_0_7_is_mode1_reset_supported +ffffffff822df9e0 t smu_v13_0_7_get_gpu_metrics +ffffffff822dfdf0 t smu_v13_0_7_enable_mgpu_fan_boost +ffffffff822dfe40 t smu_v13_0_7_get_smu_metrics_data +ffffffff822e0190 t smu_v13_0_7_get_throttler_status +ffffffff822e1000 T yellow_carp_set_ppt_funcs +ffffffff822e1040 t yellow_carp_set_default_dpm_tables +ffffffff822e1060 t yellow_carp_print_clk_levels +ffffffff822e1120 t yellow_carp_force_clk_levels +ffffffff822e13c0 t yellow_carp_od_edit_dpm_table +ffffffff822e1690 t yellow_carp_dpm_set_vcn_enable +ffffffff822e16b0 t yellow_carp_dpm_set_jpeg_enable +ffffffff822e16d0 t yellow_carp_read_sensor +ffffffff822e1a70 t yellow_carp_is_dpm_running +ffffffff822e1ac0 t yellow_carp_set_watermarks_table +ffffffff822e1c50 t yellow_carp_set_performance_level +ffffffff822e2180 t yellow_carp_init_smc_tables +ffffffff822e22f0 t yellow_carp_fini_smc_tables +ffffffff822e23a0 t yellow_carp_system_features_control +ffffffff822e23f0 t yellow_carp_get_gfxoff_status +ffffffff822e2470 t yellow_carp_mode2_reset +ffffffff822e24f0 t yellow_carp_get_dpm_ultimate_freq +ffffffff822e2930 t yellow_carp_get_gpu_metrics +ffffffff822e2ae0 t yellow_carp_post_smu_init +ffffffff822e2b60 t yellow_carp_set_fine_grain_gfx_freq_parameters +ffffffff822e2bb0 t yellow_carp_get_smu_metrics_data +ffffffff822e3000 T smu_cmn_send_msg_without_waiting +ffffffff822e3170 T smu_cmn_wait_for_response +ffffffff822e32a0 T smu_cmn_send_smc_msg_with_param +ffffffff822e35c0 T smu_cmn_to_asic_specific_index +ffffffff822e36c0 t __smu_cmn_reg_print_error +ffffffff822e3910 T smu_cmn_send_smc_msg +ffffffff822e3930 T smu_cmn_send_debug_smc_msg +ffffffff822e39b0 T smu_cmn_feature_is_supported +ffffffff822e3a50 T smu_cmn_feature_is_enabled +ffffffff822e3b40 T smu_cmn_clk_dpm_is_enabled +ffffffff822e3c40 T smu_cmn_get_enabled_mask +ffffffff822e3d30 T smu_cmn_get_indep_throttler_status +ffffffff822e3de0 T smu_cmn_feature_update_enable_state +ffffffff822e3e80 T smu_cmn_feature_set_enabled +ffffffff822e3f50 T smu_cmn_get_pp_feature_mask +ffffffff822e40f0 T smu_cmn_set_pp_feature_mask +ffffffff822e41f0 T smu_cmn_disable_all_features_with_exception +ffffffff822e42a0 T smu_cmn_get_smc_version +ffffffff822e4370 T smu_cmn_update_table +ffffffff822e44d0 T smu_cmn_write_watermarks_table +ffffffff822e4590 T smu_cmn_write_pptable +ffffffff822e4650 T smu_cmn_get_metrics_table +ffffffff822e47b0 T smu_cmn_get_combo_pptable +ffffffff822e4880 T smu_cmn_init_soft_gpu_metrics +ffffffff822e4960 T smu_cmn_set_mp1_state +ffffffff822e4a00 T smu_cmn_is_audio_func_enabled +ffffffff822e5000 T pci_mcfg_init +ffffffff822e5050 T pci_lookup_segment +ffffffff822e50b0 T pci_attach_hook +ffffffff822e50e0 T pci_bus_maxdevs +ffffffff822e5110 T pci_make_tag +ffffffff822e5180 T pci_decompose_tag +ffffffff822e51e0 T pci_conf_size +ffffffff822e5230 T pci_mcfg_map_bus +ffffffff822e52b0 T pci_conf_read +ffffffff822e5400 T pci_conf_write +ffffffff822e5530 T pci_msix_table_map +ffffffff822e5650 T pci_msix_table_unmap +ffffffff822e56f0 T msi_hwmask +ffffffff822e5720 T msi_hwunmask +ffffffff822e5750 T msi_addroute +ffffffff822e5850 T msi_delroute +ffffffff822e58c0 T pci_intr_map_msi +ffffffff822e5940 T msix_hwmask +ffffffff822e5970 T msix_hwunmask +ffffffff822e59a0 T msix_addroute +ffffffff822e5b90 T msix_delroute +ffffffff822e5cf0 T pci_intr_map_msix +ffffffff822e5dc0 T pci_intr_map +ffffffff822e5fd0 T pci_intr_string +ffffffff822e60b0 T pci_intr_establish +ffffffff822e6100 T pci_intr_establish_cpu +ffffffff822e6260 T pci_intr_disestablish +ffffffff822e6270 T pci_init_extents +ffffffff822e6450 T pci_probe_device_hook +ffffffff822e6490 T pci_dev_postattach +ffffffff822e64a0 T pci_min_powerstate +ffffffff822e64b0 T pci_set_powerstate_md +ffffffff822e7000 T pciide_machdep_compat_intr_establish +ffffffff822e7060 T pciide_machdep_compat_intr_disestablish +ffffffff822e8000 T vga_post_init +ffffffff822e8310 t vm86_emu_inb +ffffffff822e8350 t vm86_emu_inw +ffffffff822e8390 t vm86_emu_inl +ffffffff822e83d0 t vm86_emu_outb +ffffffff822e8420 t vm86_emu_outw +ffffffff822e8460 t vm86_emu_outl +ffffffff822e84a0 T vga_post_call +ffffffff822e8510 T vga_post_free +ffffffff822e8580 T ddb_vgapost +ffffffff822e9000 T pchbmatch +ffffffff822e9040 T pchbattach +ffffffff822e94b0 T pchbactivate +ffffffff822e9520 T pchb_amd64ht_attach +ffffffff822e9660 T pchb_rnd +ffffffff822e96e0 T pchb_print +ffffffff822ea000 T amas_match +ffffffff822ea050 T amas_attach +ffffffff822ea0b0 T amas_intl_nodes +ffffffff822ea140 T amas_get_pagerange +ffffffff822eb000 T agp_flush_cache +ffffffff822eb030 T agp_flush_cache_range +ffffffff822eb040 T agp_init_map +ffffffff822eb100 T agp_destroy_map +ffffffff822eb140 T agp_map_subregion +ffffffff822eb170 T agp_unmap_subregion +ffffffff822eb1a0 T agp_map_atomic +ffffffff822eb1d0 T agp_unmap_atomic +ffffffff822ec000 T cardslotmatch +ffffffff822ec050 T cardslotattach +ffffffff822ec2a0 T cardslot_event +ffffffff822ec2f0 T cardslot_cb_print +ffffffff822ec340 T cardslot_16_print +ffffffff822ec390 T cardslot_16_submatch +ffffffff822ec3d0 T cardslot_event_throw +ffffffff822ec470 T cardslot_process_event +ffffffff822ed000 T cardbusmatch +ffffffff822ed050 T cardbusattach +ffffffff822ed130 T cardbus_read_tuples +ffffffff822ed4e0 T parse_tuple +ffffffff822ed750 T cardbus_attach_card +ffffffff822eded0 T enable_function +ffffffff822edf60 T decode_tuples +ffffffff822ee020 T cardbusprint +ffffffff822ee110 T cardbussubmatch +ffffffff822ee170 T disable_function +ffffffff822ee1d0 T cardbus_detach_card +ffffffff822ee2b0 T cardbus_intr_establish +ffffffff822ee2e0 T cardbus_intr_disestablish +ffffffff822ee300 T cardbus_function_enable +ffffffff822ee3d0 T cardbus_function_disable +ffffffff822ee430 T cardbus_matchbyid +ffffffff822ee4a0 T decode_tuple +ffffffff822ef000 T cardbus_mapreg_map +ffffffff822ef1a0 T cardbus_mapreg_unmap +ffffffff822f0000 T cardbus_read_exrom +ffffffff822f1000 T rbus_space_alloc +ffffffff822f1060 T rbus_space_alloc_subregion +ffffffff822f1240 T rbus_space_free +ffffffff822f12d0 T rbus_new_body +ffffffff822f1360 T rbus_new_root_delegate +ffffffff822f1420 T rbus_new_root_share +ffffffff822f2000 T com_cardbus_match +ffffffff822f2070 T com_cardbus_attach +ffffffff822f2220 T com_cardbus_detach +ffffffff822f22b0 T com_cardbus_find_csdev +ffffffff822f2420 T com_cardbus_gofigure +ffffffff822f28d0 T com_cardbus_enable +ffffffff822f29a0 T com_cardbus_disable +ffffffff822f29f0 T com_cardbus_setup +ffffffff822f3000 T xl_cardbus_match +ffffffff822f3090 T xl_cardbus_attach +ffffffff822f3420 T xl_cardbus_detach +ffffffff822f34d0 T xl_cardbus_lookup +ffffffff822f3580 T xl_cardbus_intr_ack +ffffffff822f4000 T dc_cardbus_match +ffffffff822f4020 T dc_cardbus_attach +ffffffff822f43b0 T dc_cardbus_detach +ffffffff822f4440 T dc_cardbus_setup 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athn_cardbus_read +ffffffff822f9370 T athn_cardbus_write +ffffffff822f93a0 T athn_cardbus_write_barrier +ffffffff822f93d0 T athn_cardbus_setup +ffffffff822fa000 T atw_cardbus_match +ffffffff822fa020 T atw_cardbus_attach +ffffffff822fa210 T atw_cardbus_detach +ffffffff822fa2d0 T atw_cardbus_enable +ffffffff822fa3a0 T atw_cardbus_disable +ffffffff822fa3f0 T atw_cardbus_power +ffffffff822fa420 T atw_cardbus_setup +ffffffff822fb000 T rtw_cardbus_match +ffffffff822fb020 T rtw_cardbus_attach +ffffffff822fb260 T rtw_cardbus_detach +ffffffff822fb380 T rtw_cardbus_intr_ack +ffffffff822fb3a0 T rtw_cardbus_funcregen +ffffffff822fb400 T rtw_cardbus_enable +ffffffff822fb550 T rtw_cardbus_disable +ffffffff822fb630 T rtw_cardbus_power +ffffffff822fb660 T rtw_cardbus_setup +ffffffff822fc000 T ral_cardbus_match +ffffffff822fc020 T ral_cardbus_attach +ffffffff822fc220 T ral_cardbus_detach +ffffffff822fc2d0 T ral_cardbus_activate +ffffffff822fc350 T ral_cardbus_enable +ffffffff822fc4b0 T ral_cardbus_disable +ffffffff822fc500 T ral_cardbus_setup +ffffffff822fc5a0 T ral_cardbus_wakeup +ffffffff822fd000 T acx_cardbus_match +ffffffff822fd020 T acx_cardbus_attach +ffffffff822fd250 T acx_cardbus_detach +ffffffff822fd370 T acx_cardbus_enable +ffffffff822fd440 T acx_cardbus_disable +ffffffff822fd490 T acx_cardbus_power +ffffffff822fd4c0 T acx_cardbus_setup +ffffffff822fe000 T pgt_cardbus_match +ffffffff822fe020 T pgt_cardbus_attach +ffffffff822fe220 T pgt_cardbus_detach +ffffffff822fe2c0 T pgt_cardbus_enable +ffffffff822fe410 T pgt_cardbus_disable +ffffffff822fe460 T pgt_cardbus_power +ffffffff822fe4b0 T pgt_cardbus_setup +ffffffff822ff000 T ehci_cardbus_match +ffffffff822ff040 T ehci_cardbus_attach +ffffffff822ff2e0 T ehci_cardbus_detach +ffffffff82300000 T ohci_cardbus_match +ffffffff82300040 T ohci_cardbus_attach +ffffffff823002d0 T ohci_cardbus_detach +ffffffff82301000 T uhci_cardbus_match +ffffffff82301040 T uhci_cardbus_attach +ffffffff82301340 T uhci_cardbus_detach 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ne_pcmcia_detach +ffffffff8230d800 T ne_pcmcia_activate +ffffffff8230d8f0 T ne_pcmcia_get_enaddr +ffffffff8230dad0 T ne_pcmcia_dl10019_get_enaddr +ffffffff8230dd20 T ne_pcmcia_ax88190_set_iobase +ffffffff8230e000 T aic_pcmcia_match +ffffffff8230e0b0 T aic_pcmcia_attach +ffffffff8230e2a0 T aic_pcmcia_detach +ffffffff8230f000 T com_pcmcia_match +ffffffff8230f210 T com_pcmcia_attach +ffffffff8230f4f0 T com_pcmcia_detach +ffffffff8230f580 T com_pcmcia_activate +ffffffff8230f630 T com_pcmcia_enable1 +ffffffff8230f6d0 T com_pcmcia_enable +ffffffff8230f7c0 T com_pcmcia_disable +ffffffff8230f800 T com_pcmcia_disable1 +ffffffff82310000 t wdc_pcmcia_match +ffffffff823100d0 t wdc_pcmcia_attach +ffffffff82310540 T wdc_pcmcia_detach +ffffffff82310640 T wdc_pcmcia_activate +ffffffff82310760 T wdc_pcmcia_disk_device_interface_callback +ffffffff82310800 T wdc_pcmcia_disk_device_interface +ffffffff82310860 T wdc_pcmcia_lookup +ffffffff82311000 T sm_pcmcia_match +ffffffff82311100 T sm_pcmcia_attach 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xe_pcmcia_manfid_ciscallback +ffffffff823154e0 T xe_get +ffffffff823157a0 T xe_set_address +ffffffff82315a60 T xe_cycle_power +ffffffff82316000 T wi_pcmcia_match +ffffffff82316120 T wi_pcmcia_attach +ffffffff823163d0 T wi_pcmcia_detach +ffffffff82316480 T wi_pcmcia_activate +ffffffff82316570 T wi_pcmcia_wakeup +ffffffff82317000 T malo_pcmcia_match +ffffffff82317050 T malo_pcmcia_attach +ffffffff82317220 T malo_pcmcia_detach +ffffffff823172a0 T malo_pcmcia_activate +ffffffff82317500 T cmalo_intr +ffffffff82317760 T cmalo_attach +ffffffff82317c60 T cmalo_detach +ffffffff82317d40 T cmalo_stop +ffffffff82317e80 T malo_pcmcia_wakeup +ffffffff82317f10 T cmalo_init +ffffffff82318290 T cmalo_intr_mask +ffffffff82318320 T cmalo_fw_alloc +ffffffff823183f0 T cmalo_fw_load_helper +ffffffff82318640 T cmalo_fw_load_main +ffffffff82318a90 T cmalo_cmd_get_hwspec +ffffffff82318be0 T cmalo_ioctl +ffffffff82319000 T cmalo_start +ffffffff823190a0 T cmalo_watchdog +ffffffff823190d0 T cmalo_newstate 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iommu_flush_ctx_qi +ffffffff824d0930 T ivhd_invalidate_domain +ffffffff824d0990 T iommu_read_8 +ffffffff824d09b0 T iommu_flush_ctx +ffffffff824d0ad0 T iommu_enable_qi +ffffffff824d0bf0 T iommu_showcfg +ffffffff824d0e00 T iommu_init +ffffffff824d1130 T acpidmar_intr_establish +ffffffff824d1240 T acpidmar_intr +ffffffff824d13e0 T acpidmar_match_devscope +ffffffff824d1520 T domain_create +ffffffff824d1750 t dmar_dmamap_create +ffffffff824d1770 t dmar_dmamap_destroy +ffffffff824d1780 t dmar_dmamap_load +ffffffff824d17e0 t dmar_dmamap_load_mbuf +ffffffff824d1840 t dmar_dmamap_load_uio +ffffffff824d18a0 t dmar_dmamap_load_raw +ffffffff824d1900 t dmar_dmamap_unload +ffffffff824d1930 t dmar_dmamap_sync +ffffffff824d1950 t dmar_dmamem_alloc +ffffffff824d1970 t dmar_dmamem_free +ffffffff824d1980 t dmar_dmamem_map +ffffffff824d19a0 t dmar_dmamem_unmap +ffffffff824d19b0 t dmar_dmamem_mmap +ffffffff824d19d0 T domain_add_device +ffffffff824d1a50 T domain_remove_device +ffffffff824d1b00 T domain_lookup +ffffffff824d1cc0 T _iommu_map +ffffffff824d1d80 T _iommu_domain +ffffffff824d1de0 T domain_map_device +ffffffff824d20e0 T ivhd_flush_devtab +ffffffff824d2130 T acpidmar_pci_hook +ffffffff824d22f0 T acpidmar_parse_devscope +ffffffff824d2410 T acpidmar_drhd +ffffffff824d25e0 T acpidmar_rmrr +ffffffff824d2890 T acpidmar_atsr +ffffffff824d2a20 T acpidmar_init +ffffffff824d2e70 T acpiivhd_intr +ffffffff824d2f50 T ivhd_poll_events +ffffffff824d3010 T ivhd_intr_map +ffffffff824d30c0 T _dumppte +ffffffff824d3230 T ivhd_showpage +ffffffff824d3360 T ivhd_show_event +ffffffff824d3c30 T ivhd_showdte +ffffffff824d3d10 T ivhd_showcmd +ffffffff824d3dc0 T _ivhd_issue_command +ffffffff824d3ea0 T ivhd_issue_command +ffffffff824d4170 T ivhd_invalidate_iommu_all +ffffffff824d4260 T ivhd_invalidate_interrupt_table +ffffffff824d4350 T ivhd_showreg +ffffffff824d4480 T ivhd_checkerr +ffffffff824d46c0 T ivhd_iommu_init +ffffffff824d4b90 T acpiivrs_ivhd +ffffffff824d4c00 T acpiivrs_init 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asmc_backlight +ffffffff824d8bc0 T asmc_init +ffffffff824d8dc0 T asmc_update +ffffffff824d8f70 T asmc_detach +ffffffff824d9130 t asmc_temp +ffffffff824d92b0 t asmc_fan +ffffffff824d9480 t asmc_light +ffffffff824da000 T acpiasus_match +ffffffff824da020 T acpiasus_attach +ffffffff824da140 T acpiasus_activate +ffffffff824da2d0 T acpiasus_init +ffffffff824da3b0 T acpiasus_notify +ffffffff824db000 T thinkpad_match +ffffffff824db0a0 T thinkpad_attach +ffffffff824db2b0 T thinkpad_activate +ffffffff824db420 T thinkpad_sensor_attach +ffffffff824db5c0 T thinkpad_sensor_refresh +ffffffff824db6e0 T thinkpad_get_volume_mute +ffffffff824db750 T thinkpad_attach_deferred +ffffffff824db770 T thinkpad_enable_events +ffffffff824db940 T thinkpad_get_kbd_backlight +ffffffff824db9d0 T thinkpad_set_kbd_backlight +ffffffff824dbaa0 T thinkpad_get_param +ffffffff824dbb00 T thinkpad_set_param +ffffffff824dbbb0 T thinkpad_hotkey +ffffffff824dc1e0 T thinkpad_brightness_up +ffffffff824dc380 T thinkpad_brightness_down +ffffffff824dc530 T thinkpad_toggle_bluetooth +ffffffff824dc640 T thinkpad_volume_mute +ffffffff824dc6f0 T thinkpad_volume_down +ffffffff824dc7a0 T thinkpad_volume_up +ffffffff824dc850 T thinkpad_get_thinklight +ffffffff824dc8a0 T thinkpad_adaptive_change +ffffffff824dc9c0 T thinkpad_get_brightness +ffffffff824dc9f0 T thinkpad_toggle_wan +ffffffff824dcb00 T thinkpad_cmos +ffffffff824dcbb0 T thinkpad_set_brightness +ffffffff824dcca0 T thinkpad_set_thinklight +ffffffff824dd000 T toshiba_match +ffffffff824dd090 T toshiba_attach +ffffffff824dd170 T get_param_brightness +ffffffff824dd1c0 T acpitoshiba_get_param +ffffffff824dd220 T set_param_brightness +ffffffff824dd2b0 T toshiba_update_brightness +ffffffff824dd3b0 T acpitoshiba_set_param +ffffffff824dd440 T toshiba_set_brightness +ffffffff824dd560 T toshiba_enable_events +ffffffff824dd5e0 T toshiba_read_events +ffffffff824dd740 T toshiba_hotkey +ffffffff824dd970 T toshiba_get_brightness +ffffffff824ddae0 T toshiba_fn_key_brightness_up +ffffffff824ddc30 T toshiba_fn_key_brightness_down +ffffffff824ddd80 T toshiba_fn_key_video_output +ffffffff824dded0 T toshiba_get_video_output +ffffffff824de040 T toshiba_set_video_output +ffffffff824df000 T acpisony_match +ffffffff824df070 T acpisony_attach +ffffffff824df0d0 T acpisony_activate +ffffffff824df110 T acpisony_notify_setup +ffffffff824df300 T acpisony_notify +ffffffff824df6a0 T acpisony_find_offset +ffffffff824df7b0 T acpisony_set_hotkey +ffffffff824df9a0 T acpisony_brightness_down +ffffffff824dfab0 T acpisony_get_brightness +ffffffff824dfb30 T acpisony_set_brightness +ffffffff824e0000 T acpivideo_match +ffffffff824e0070 T acpivideo_attach +ffffffff824e01d0 T acpivideo_getpcibus +ffffffff824e0210 T acpivideo_notify +ffffffff824e0270 T acpivideo_set_policy +ffffffff824e0330 T acpi_foundvout +ffffffff824e0400 T acpivideo_print +ffffffff824e1000 T acpivout_match +ffffffff824e1070 T acpivout_attach +ffffffff824e11c0 T acpivout_notify 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aplgpio_match +ffffffff824e4060 T aplgpio_attach +ffffffff824e4300 T aplgpio_intr +ffffffff824e4430 T aplgpio_read_pin +ffffffff824e4480 T aplgpio_write_pin +ffffffff824e44f0 T aplgpio_intr_establish +ffffffff824e4610 T aplgpio_intr_enable +ffffffff824e46a0 T aplgpio_intr_disable +ffffffff824e5000 T bytgpio_match +ffffffff824e5060 T bytgpio_attach +ffffffff824e5310 T bytgpio_intr +ffffffff824e5430 T bytgpio_read_pin +ffffffff824e5490 T bytgpio_write_pin +ffffffff824e5510 T bytgpio_intr_establish +ffffffff824e5580 T bytgpio_intr_enable +ffffffff824e5660 T bytgpio_intr_disable +ffffffff824e6000 T chvgpio_match +ffffffff824e6060 T chvgpio_attach +ffffffff824e6300 T chvgpio_intr +ffffffff824e63d0 T chvgpio_read_pin +ffffffff824e6470 T chvgpio_write_pin +ffffffff824e6530 T chvgpio_intr_establish +ffffffff824e6700 T chvgpio_intr_enable +ffffffff824e67c0 T chvgpio_intr_disable +ffffffff824e6880 T chvgpio_opreg_handler +ffffffff824e6900 T chvgpio_check_pin +ffffffff824e7000 T glkgpio_match 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+ffffffff824f1000 T acpials_match +ffffffff824f1080 T acpials_attach +ffffffff824f1210 T acpials_read +ffffffff824f1290 T acpials_addtask +ffffffff824f12d0 T acpials_notify +ffffffff824f1350 T acpials_update +ffffffff824f2000 T tpm_match +ffffffff824f2050 T tpm_attach +ffffffff824f2320 T tpm_activate +ffffffff824f2420 T tpm2_start_method +ffffffff824f24a0 T tpm_probe +ffffffff824f2550 T tpm_init_tis +ffffffff824f27b0 T tpm_init_crb +ffffffff824f2af0 T tpm_suspend +ffffffff824f2be0 T tpm_resume +ffffffff824f2c10 T tpm_write_tis +ffffffff824f2f90 T tpm_read_tis +ffffffff824f3170 T tpm_write_crb +ffffffff824f3580 T tpm_read_crb +ffffffff824f3870 T tpm_request_locality_tis +ffffffff824f3960 T tpm_request_locality_crb +ffffffff824f3a60 T tpm_release_locality_crb +ffffffff824f3ab0 T tpm_release_locality_tis +ffffffff824f3b20 T tpm_getburst +ffffffff824f3bd0 T tpm_status +ffffffff824f3bf0 T tpm_waitfor +ffffffff824f3cc0 T tpm_waitfor_status +ffffffff824f4000 T acpihve_match +ffffffff824f40b0 T acpihve_attach +ffffffff824f5000 T acpisbs_match +ffffffff824f5020 T acpisbs_attach +ffffffff824f5290 T acpisbs_activate +ffffffff824f5370 T acpisbs_read +ffffffff824f5430 T acpisbs_setup_sensors +ffffffff824f5550 T acpisbs_refresh_sensors +ffffffff824f56c0 T acpisbs_notify +ffffffff824f57f0 T acpi_smbus_read +ffffffff824f6000 T surface_match +ffffffff824f6050 T surface_attach +ffffffff824f60b0 T surface_hotkey +ffffffff824f7000 T ipmi_acpi_match +ffffffff824f7020 T ipmi_acpi_attach +ffffffff824f7240 T ipmi_acpi_parse_crs +ffffffff824f8000 T amdgpio_match +ffffffff824f8060 T amdgpio_attach +ffffffff824f8290 T amdgpio_activate +ffffffff824f8380 T amdgpio_intr +ffffffff824f8520 T amdgpio_read_pin +ffffffff824f8570 T amdgpio_write_pin +ffffffff824f85e0 T amdgpio_intr_establish +ffffffff824f86d0 T amdgpio_intr_enable +ffffffff824f8750 T amdgpio_intr_disable +ffffffff824f87d0 T amdgpio_save +ffffffff824f8850 T amdgpio_restore +ffffffff824f88e0 T amdgpio_save_pin +ffffffff824f8950 T amdgpio_restore_pin +ffffffff824f89c0 T amdgpio_pin_intr +ffffffff824f9000 T acpihid_match +ffffffff824f9020 T acpihid_attach +ffffffff824f9200 T acpihid_init_dsm +ffffffff824f9360 T acpihid_eval +ffffffff824f9580 T acpihid_notify +ffffffff824f95e0 T acpihid_button_array_enable +ffffffff824fa000 T acpi_match +ffffffff824fa060 T acpi_attach +ffffffff824fa0a0 T acpi_probe +ffffffff824fa240 T acpi_map +ffffffff824fa330 T acpi_unmap +ffffffff824fa370 T acpi_bus_space_map +ffffffff824fa390 T acpi_bus_space_unmap +ffffffff824fa3a0 T acpi_intr_establish +ffffffff824fa4e0 T acpi_intr_disestablish +ffffffff824fa4f0 T acpi_scan +ffffffff824fa6a0 T acpi_acquire_glk +ffffffff824fa700 T acpi_release_glk +ffffffff824fa750 T acpi_attach_machdep +ffffffff824fa8e0 T acpi_sleep_cpu +ffffffff824faa80 T acpi_resume_cpu +ffffffff824fab70 T sleep_mp +ffffffff824fac70 T resume_mp +ffffffff824fad60 T acpi_iommu_device_map +ffffffff824fb000 T hibernate_resume_machdep +ffffffff824fb050 T hibernate_drop_to_real_mode +ffffffff824fb060 T hibernate_activate_resume_pt_machdep +ffffffff824fb0a0 T hibernate_switch_stack_machdep +ffffffff824fb0e0 T hibernate_flush +ffffffff824fb110 T acpi_savecpu +ffffffff824fc000 T sleep_showstate +ffffffff824fc100 T sleep_setstate +ffffffff824fc160 T gosleep +ffffffff824fc220 T sleep_abort +ffffffff824fc250 T sleep_resume +ffffffff824fc2c0 T suspend_finish +ffffffff824fd000 T acpipci_match +ffffffff824fd020 T acpipci_attach +ffffffff824fd2e0 T acpipci_osc +ffffffff824fd420 T acpipci_parse_resources +ffffffff824fd530 T acpipci_attach_bus +ffffffff824fd700 T acpipci_print +ffffffff824fd760 T acpipci_attach_busses +ffffffff824fe000 T efiopen +ffffffff824fe040 T eficlose +ffffffff824fe070 T efiioctl +ffffffff824fe110 T efiioc_get_table +ffffffff824fe270 T efiioc_var_get +ffffffff824fe4e0 T efiioc_var_next +ffffffff824fe700 T efiioc_var_set +ffffffff824fe990 T efi_adapt_error +ffffffff824ff000 T efi_match +ffffffff824ff060 T efi_attach +ffffffff824ff410 T efi_map_runtime +ffffffff824ff590 T efi_enter +ffffffff824ff610 T efi_leave +ffffffff824ff670 T efi_gettime +ffffffff824ff840 T efi_settime +ffffffff824ff9a0 T efi_fault +ffffffff82500000 T vmm_probe +ffffffff82500050 T vmm_attach +ffffffff825003e0 T vmm_activate +ffffffff825005f0 T vmm_enabled +ffffffff82500680 T vmm_quiesce_vmx +ffffffff82500850 T vmm_stop +ffffffff82500990 T vmm_start +ffffffff82500a70 T vmmopen +ffffffff82500ac0 T vmmioctl +ffffffff82500ed0 T vm_create +ffffffff82501300 T vm_run +ffffffff825014e0 T vm_get_info +ffffffff82501730 T vm_terminate +ffffffff825018a0 T vm_resetcpu +ffffffff82501a00 T vm_intr_pending +ffffffff82501ad0 T vm_rwregs +ffffffff82501c20 T vm_mprotect_ept +ffffffff82501ec0 T vm_rwvmparams +ffffffff82502070 T pledge_ioctl_vmm +ffffffff82502140 T vmmclose +ffffffff82502170 T vm_find +ffffffff82502280 T vcpu_reset_regs +ffffffff825022d0 T vmm_init_pvclock +ffffffff825023a0 T vcpu_readregs_vmx +ffffffff825027c0 T vcpu_writeregs_vmx +ffffffff82502c30 T vcpu_readregs_svm +ffffffff825030d0 T vcpu_writeregs_svm +ffffffff82503590 T vmm_get_guest_memtype +ffffffff82503610 T vmx_mprotect_ept +ffffffff82503880 T vmx_pmap_find_pte_ept +ffffffff82503950 T start_vmm_on_cpu +ffffffff82503a20 T stop_vmm_on_cpu +ffffffff82503ac0 T vmclear_on_cpu +ffffffff82503b30 T vm_create_check_mem_ranges +ffffffff82503c90 T vm_impl_init +ffffffff82503d30 T vm_teardown +ffffffff82503ee0 T vcpu_init +ffffffff82503fb0 T vm_impl_init_vmx +ffffffff825040d0 T vm_impl_init_svm +ffffffff825041f0 T vm_impl_deinit_vmx +ffffffff82504220 T vm_impl_deinit_svm +ffffffff82504250 T vm_impl_deinit +ffffffff825042b0 T vcpu_reload_vmcs_vmx +ffffffff825043e0 T vcpu_reset_regs_svm +ffffffff82504780 T svm_setmsrbrw +ffffffff825048f0 T svm_setmsrbr +ffffffff825049c0 T vmm_alloc_vpid +ffffffff82504ad0 T svm_setmsrbw +ffffffff82504ba0 T vmx_setmsrbr +ffffffff82504c50 T vmx_setmsrbw +ffffffff82504d00 T vmx_setmsrbrw +ffffffff82504e00 T svm_set_clean +ffffffff82504e50 T svm_set_dirty +ffffffff82504ea0 T vcpu_reset_regs_vmx +ffffffff825059f0 T vcpu_vmx_check_cap +ffffffff82505af0 T vcpu_vmx_compute_ctrl +ffffffff82505cd0 T vcpu_init_vmx +ffffffff82506070 T vcpu_deinit_vmx +ffffffff825061f0 T vcpu_init_svm +ffffffff82506370 T vcpu_deinit_svm +ffffffff825064b0 T vmm_free_vpid +ffffffff82506510 T vcpu_deinit +ffffffff82506560 T vcpu_run_vmx +ffffffff82506d70 T vcpu_run_svm +ffffffff82507350 T vcpu_must_stop +ffffffff825073b0 T vmm_fpurestore +ffffffff82507480 T vmm_fpusave +ffffffff82507500 T vmm_translate_gva +ffffffff82507830 T vmm_update_pvclock +ffffffff82507930 T vmx_get_exit_info +ffffffff82507990 T vmx_handle_exit +ffffffff82507d80 T vmx_instruction_error_decode +ffffffff82507f50 T vmm_get_guest_cpu_cpl +ffffffff82508000 T vmx_handle_intr +ffffffff82508090 T svm_handle_hlt +ffffffff825080e0 T vmx_handle_hlt +ffffffff82508190 T svm_handle_exit +ffffffff82508460 T svm_handle_np_fault +ffffffff82508600 T vmm_handle_cpuid +ffffffff82508c70 T svm_handle_msr +ffffffff82508f20 T svm_handle_xsetbv +ffffffff82508f70 T svm_handle_inout +ffffffff82509080 T vmm_inject_ud +ffffffff825090b0 T vmm_inject_db +ffffffff825090e0 T vmx_handle_np_fault +ffffffff82509250 T vmx_handle_inout +ffffffff825093f0 T vmx_handle_cr +ffffffff82509660 T vmx_handle_rdmsr +ffffffff82509730 T vmx_handle_wrmsr +ffffffff82509980 T vmx_handle_xsetbv +ffffffff82509a10 T vmm_inject_gp +ffffffff82509a40 T vmx_get_exit_qualification +ffffffff82509aa0 T vmx_get_guest_faulttype +ffffffff82509b40 T svm_get_guest_faulttype +ffffffff82509b70 T svm_fault_page +ffffffff82509bf0 T vmx_fault_page +ffffffff82509d50 T vmm_get_guest_cpu_mode +ffffffff82509e50 T vmx_load_pdptes +ffffffff8250a0d0 T vmx_handle_cr0_write +ffffffff8250a2d0 T vmx_handle_cr4_write +ffffffff8250a370 T vmm_handle_xsetbv +ffffffff8250a450 T vmx_handle_misc_enable_msr +ffffffff8250a4b0 T vmm_pat_is_valid +ffffffff8250a590 T vmm_gpa_is_valid +ffffffff8250a600 T vmx_exit_reason_decode +ffffffff8250a640 T svm_exit_reason_decode +ffffffff8250b450 T vcpu_state_decode +ffffffff8250c000 T vmm_dispatch_intr +ffffffff8250c019 T vmxon +ffffffff8250c049 T vmxoff +ffffffff8250c079 T vmclear +ffffffff8250c0a9 T vmptrld +ffffffff8250c0d9 T vmptrst +ffffffff8250c109 T vmwrite +ffffffff8250c139 T vmread +ffffffff8250c169 T invvpid +ffffffff8250c199 T invept +ffffffff8250c1c9 T vmx_enter_guest +ffffffff8250c1f0 t skip_init +ffffffff8250c2bd t no_l1df_msr +ffffffff8250c2c0 t l1df_tlb_loop +ffffffff8250c2d9 t l1df_tlb_done +ffffffff8250c2e1 t l1df_load_cache +ffffffff8250c2f8 t done_flush +ffffffff8250c38b t do_resume +ffffffff8250c410 t fail_launch_or_resume +ffffffff8250c44d t fail_launch_unknown +ffffffff8250c45a t fail_launch_invalid_vmcs +ffffffff8250c467 t fail_launch_valid_vmcs +ffffffff8250c484 t vmx_exit_handler_asm +ffffffff8250c549 t restore_host +ffffffff8250c5e9 T svm_enter_guest +ffffffff8250c775 t restore_host_svm +ffffffff8250d000 T sdmmc_match +ffffffff8250d050 T sdmmc_attach +ffffffff8250d380 T sdmmc_detach +ffffffff8250d430 T sdmmc_activate +ffffffff8250d500 T sdmmc_discover_task +ffffffff8250d5c0 T sdmmc_create_thread +ffffffff8250d630 T sdmmc_holds_root_device +ffffffff8250d680 T sdmmc_task_thread +ffffffff8250d870 T sdmmc_needs_discover +ffffffff8250d920 T sdmmc_del_task +ffffffff8250d9d0 T sdmmc_card_detach +ffffffff8250dab0 T sdmmc_add_task +ffffffff8250db30 T sdmmc_card_attach +ffffffff8250dc40 T sdmmc_enable +ffffffff8250dd90 T sdmmc_scan +ffffffff8250de10 T sdmmc_init +ffffffff8250df10 T sdmmc_disable +ffffffff8250e070 T sdmmc_function_free +ffffffff8250e090 T sdmmc_delay +ffffffff8250e0e0 T sdmmc_select_card +ffffffff8250e260 T sdmmc_set_bus_power +ffffffff8250e420 T sdmmc_function_alloc +ffffffff8250e4a0 T sdmmc_app_command +ffffffff8250e630 T sdmmc_mmc_command +ffffffff8250e6b0 T sdmmc_go_idle_state +ffffffff8250e7c0 T sdmmc_send_if_cond +ffffffff8250e910 T sdmmc_set_relative_addr +ffffffff8250f000 T sdmmc_cisptr +ffffffff8250f0a0 T sdmmc_read_cis +ffffffff8250f3a0 T sdmmc_print_cis +ffffffff8250f510 T sdmmc_check_cis_quirks +ffffffff82510000 T sdmmc_io_enable +ffffffff825102a0 T sdmmc_io_reset +ffffffff825103c0 T sdmmc_io_send_op_cond +ffffffff82510530 T sdmmc_io_scan +ffffffff82510680 T sdmmc_io_init +ffffffff825107a0 T sdmmc_io_set_highspeed +ffffffff82510a40 T sdmmc_io_set_bus_width +ffffffff82510cd0 T sdmmc_io_function_ready +ffffffff82510e40 T sdmmc_io_read_1 +ffffffff82510f90 T sdmmc_io_function_enable +ffffffff82511360 T sdmmc_io_write_1 +ffffffff825114e0 T sdmmc_io_function_disable +ffffffff82511760 T sdmmc_io_attach +ffffffff82511840 T sdmmc_print +ffffffff82511a90 T sdmmc_submatch +ffffffff82511b10 T sdmmc_io_detach +ffffffff82511bb0 T sdmmc_io_rw_direct +ffffffff82511d50 T sdmmc_io_rw_extended_subr +ffffffff82511ef0 T sdmmc_io_rw_extended +ffffffff825122e0 T sdmmc_io_read_2 +ffffffff82512430 T sdmmc_io_write_2 +ffffffff82512590 T sdmmc_io_read_4 +ffffffff825126e0 T sdmmc_io_write_4 +ffffffff82512840 T sdmmc_io_read_multi_1 +ffffffff82512930 T sdmmc_io_write_multi_1 +ffffffff82512a20 T sdmmc_io_read_region_1 +ffffffff82512b10 T sdmmc_io_write_region_1 +ffffffff82512c00 T sdmmc_io_xchg +ffffffff82512d90 T sdmmc_intr_enable +ffffffff82513000 T sdmmc_intr_disable +ffffffff82513270 T sdmmc_intr_establish +ffffffff82513370 T sdmmc_intr_disestablish +ffffffff82513450 T sdmmc_card_intr +ffffffff825134a0 T sdmmc_intr_task +ffffffff82513530 T sdmmc_io_set_blocklen +ffffffff82514000 T sdmmc_mem_enable +ffffffff825144e0 T sdmmc_mem_send_op_cond +ffffffff82514690 T sdmmc_mem_signal_voltage +ffffffff82514750 T sdmmc_mem_scan +ffffffff82514a50 T sdmmc_decode_csd +ffffffff82514e50 T sdmmc_decode_cid +ffffffff82515290 T sdmmc_mem_send_scr +ffffffff825153d0 T sdmmc_mem_decode_scr +ffffffff82515440 T sdmmc_mem_send_cxd_data +ffffffff825155b0 T sdmmc_mem_set_bus_width +ffffffff825156c0 T sdmmc_mem_sd_switch +ffffffff82515970 T sdmmc_be512_to_bitfield512 +ffffffff82515a20 T sdmmc_mem_mmc_switch +ffffffff82515b10 T sdmmc_mem_init +ffffffff82515c60 T sdmmc_mem_set_blocklen +ffffffff82515d60 T sdmmc_mem_sd_init +ffffffff82516310 T sdmmc_mem_mmc_init +ffffffff82516c30 T sdmmc_mem_select_transfer_mode +ffffffff82516cb0 T sdmmc_mem_execute_tuning +ffffffff82516d40 T sdmmc_mem_read_block_subr +ffffffff825170a0 T sdmmc_mem_single_read_block +ffffffff82517160 T sdmmc_mem_read_block +ffffffff82517320 T sdmmc_mem_write_block_subr +ffffffff82517670 T sdmmc_mem_single_write_block +ffffffff82517730 T sdmmc_mem_write_block +ffffffff825178f0 T sdmmc_mem_hibernate_write +ffffffff82518000 T sdmmc_scsi_cmd +ffffffff825181f0 T sdmmc_minphys +ffffffff82518260 T sdmmc_scsi_attach +ffffffff82518450 T sdmmc_alloc_ccbs +ffffffff82518590 T sdmmc_free_ccbs +ffffffff825185f0 T sdmmc_scsi_detach +ffffffff82518740 T sdmmc_stimeout +ffffffff825187c0 T sdmmc_ccb_alloc +ffffffff82518870 T sdmmc_ccb_free +ffffffff82518950 T sdmmc_inquiry +ffffffff82518b70 T sdmmc_start_xs +ffffffff82518c60 T sdmmc_complete_xs +ffffffff82518d20 T sdmmc_done_xs +ffffffff82518d60 T sdmmc_scsi_hibernate_io +ffffffff82519000 T bwfm_sdio_preinit +ffffffff825194f0 T bwfm_sdio_txcheck +ffffffff82519530 T bwfm_sdio_txdata +ffffffff825195a0 T bwfm_sdio_txctl +ffffffff825196f0 T bwfm_sdio_buscore_read +ffffffff82519700 T bwfm_sdio_buscore_write +ffffffff82519710 T bwfm_sdio_buscore_prepare +ffffffff82519840 T bwfm_sdio_buscore_activate +ffffffff825198c0 T bwfm_sdio_match +ffffffff82519980 T bwfm_sdio_attach +ffffffff82519c40 T bwfm_sdio_detach +ffffffff82519ca0 T bwfm_sdio_task +ffffffff82519df0 T bwfm_sdio_write_1 +ffffffff82519e20 T bwfm_sdio_read_1 +ffffffff82519e50 T bwfm_sdio_write_4 +ffffffff82519f00 T bwfm_sdio_read_4 +ffffffff82519fa0 T bwfm_sdio_load_microcode +ffffffff8251a200 T bwfm_sdio_clkctl +ffffffff8251a330 T bwfm_sdio_dev_write +ffffffff8251a370 T bwfm_sdio_intr +ffffffff8251a3b0 T bwfm_sdio_ram_read_write +ffffffff8251a5e0 T bwfm_sdio_htclk +ffffffff8251a840 T bwfm_sdio_readshared +ffffffff8251a900 T bwfm_sdio_dev_read +ffffffff8251a930 T bwfm_sdio_rx_frames +ffffffff8251acc0 T bwfm_sdio_tx_frames +ffffffff8251ada0 T bwfm_sdio_backplane +ffffffff8251ae50 T bwfm_sdio_buf_read +ffffffff8251af20 T bwfm_sdio_buf_write +ffffffff8251afd0 T bwfm_sdio_frame_read_write +ffffffff8251b150 T bwfm_sdio_newbuf +ffffffff8251b1d0 T bwfm_sdio_tx_ok +ffffffff8251b220 T bwfm_sdio_tx_ctrlframe +ffffffff8251b320 T bwfm_sdio_tx_dataframe +ffffffff8251b470 T bwfm_sdio_rx_glom +ffffffff8251c000 T onewire_match +ffffffff8251c050 T onewire_attach +ffffffff8251c0f0 T onewire_detach +ffffffff8251c160 T onewire_activate +ffffffff8251c180 T onewire_scan +ffffffff8251c390 T onewire_createthread +ffffffff8251c3f0 T onewire_print +ffffffff8251c4c0 T onewirebus_print +ffffffff8251c510 T onewire_lock +ffffffff8251c530 T onewire_unlock +ffffffff8251c540 T onewire_reset +ffffffff8251c560 T onewire_bit +ffffffff8251c580 T onewire_read_byte +ffffffff8251c6c0 T onewire_write_byte +ffffffff8251c790 T onewire_read_block +ffffffff8251c830 T onewire_write_block +ffffffff8251c8d0 T onewire_triplet +ffffffff8251c9b0 T onewire_matchrom +ffffffff8251cb00 T onewire_search +ffffffff8251ce90 T onewire_thread +ffffffff8251d000 T onewire_crc +ffffffff8251d0e0 T onewire_crc16 +ffffffff8251d1c0 T onewire_famname +ffffffff8251d200 T onewire_matchbyfam +ffffffff8251e000 T owid_match +ffffffff8251e020 T owid_attach +ffffffff8251e0f0 T owid_detach +ffffffff8251e130 T owid_activate +ffffffff8251f000 T owsbm_match +ffffffff8251f020 T owsbm_attach +ffffffff8251f1c0 T owsbm_detach +ffffffff8251f230 T owsbm_activate +ffffffff8251f260 T owsbm_update +ffffffff82520000 T owtemp_match +ffffffff82520020 T owtemp_attach +ffffffff82520110 T owtemp_detach +ffffffff82520180 T owtemp_activate +ffffffff825201b0 T owtemp_update +ffffffff82521000 T owctr_match +ffffffff82521020 T owctr_attach +ffffffff82521160 T owctr_detach +ffffffff825211d0 T owctr_activate +ffffffff82521200 T owctr_update +ffffffff82521230 T owctr_update_counter +ffffffff82522000 A __text_page_start +ffffffff82522000 T Xsyscall_meltdown +ffffffff8252200c T Xsyscall +ffffffff8252226e t Xsyscall_trampback +ffffffff82522280 T intr_user_exit +ffffffff825222c2 t intr_user_exit_post_ast +ffffffff825223ee t Xiretq_trampback +ffffffff825223fa T doreti_iret +ffffffff82523000 T alltraps +ffffffff82523138 T recall_trap +ffffffff82523150 T alltraps_kern +ffffffff82523153 T alltraps_kern_meltdown +ffffffff82524000 ? Xsyscall32 +ffffffff82524000 A __kutext_start +ffffffff82524000 A __text_page_end +ffffffff82525000 ? Xtrap00 +ffffffff82525010 ? Xtrap01 +ffffffff82525020 ? Xtrap02 +ffffffff82525024 c calltrap_specstk +ffffffff825250f0 ? calltrap_specstk_tramp +ffffffff82525110 ? Xtrap03 +ffffffff82525120 ? Xtrap04 +ffffffff82525130 ? Xtrap05 +ffffffff82525140 ? Xtrap06 +ffffffff82525150 ? Xtrap07 +ffffffff82525160 ? Xtrap08 +ffffffff82525170 ? Xtrap09 +ffffffff82525180 ? Xtrap0a +ffffffff82525190 ? Xtrap0b +ffffffff825251a0 ? Xtrap0c +ffffffff825251b0 ? Xtrap0d +ffffffff82525230 ? Xtrap0e +ffffffff82525240 ? Xintrspurious +ffffffff82525240 ? Xtrap0f +ffffffff82525250 ? Xtrap10 +ffffffff82525260 ? Xtrap11 +ffffffff82525270 ? Xtrap12 +ffffffff82525280 ? Xtrap13 +ffffffff82525290 ? Xtrap14 +ffffffff82525290 ? Xtrap15 +ffffffff82525290 ? Xtrap16 +ffffffff82525290 ? Xtrap17 +ffffffff82525290 ? Xtrap18 +ffffffff82525290 ? Xtrap19 +ffffffff82525290 ? Xtrap1a +ffffffff82525290 ? Xtrap1b +ffffffff82525290 ? Xtrap1c +ffffffff82525290 ? Xtrap1d +ffffffff82525290 ? Xtrap1e +ffffffff82525290 ? Xtrap1f +ffffffff825252a0 ? x2apic_eoi +ffffffff825252c0 ? Xintr_lapic_ipi +ffffffff825252f0 ? Xipi_invltlb +ffffffff82525310 ? Xipi_invlpg +ffffffff82525340 ? Xipi_invlrange +ffffffff82525380 ? Xipi_invltlb_pcid +ffffffff825253c0 ? Xipi_invlpg_pcid +ffffffff82525410 ? Xipi_invlrange_pcid +ffffffff82525480 ? Xintr_lapic_ltimer +ffffffff825254b0 ? Xintr_xen_upcall +ffffffff825254e0 ? Xintr_hyperv_upcall +ffffffff82525510 ? Xintr_legacy0 +ffffffff82525540 ? Xintr_legacy1 +ffffffff82525570 ? Xintr_legacy2 +ffffffff825255a0 ? Xintr_legacy3 +ffffffff825255d0 ? Xintr_legacy4 +ffffffff82525600 ? Xintr_legacy5 +ffffffff82525630 ? Xintr_legacy6 +ffffffff82525660 ? Xintr_legacy7 +ffffffff82525690 ? Xintr_legacy8 +ffffffff825256c0 ? Xintr_legacy9 +ffffffff825256f0 ? Xintr_legacy10 +ffffffff82525720 ? Xintr_legacy11 +ffffffff82525750 ? Xintr_legacy12 +ffffffff82525780 ? Xintr_legacy13 +ffffffff825257b0 ? Xintr_legacy14 +ffffffff825257e0 ? Xintr_legacy15 +ffffffff82525810 ? Xintr_ioapic_edge0 +ffffffff82525840 ? Xintr_ioapic_edge1 +ffffffff82525870 ? Xintr_ioapic_edge2 +ffffffff825258a0 ? Xintr_ioapic_edge3 +ffffffff825258d0 ? Xintr_ioapic_edge4 +ffffffff82525900 ? Xintr_ioapic_edge5 +ffffffff82525930 ? Xintr_ioapic_edge6 +ffffffff82525960 ? Xintr_ioapic_edge7 +ffffffff82525990 ? Xintr_ioapic_edge8 +ffffffff825259c0 ? Xintr_ioapic_edge9 +ffffffff825259f0 ? Xintr_ioapic_edge10 +ffffffff82525a20 ? Xintr_ioapic_edge11 +ffffffff82525a50 ? Xintr_ioapic_edge12 +ffffffff82525a80 ? Xintr_ioapic_edge13 +ffffffff82525ab0 ? Xintr_ioapic_edge14 +ffffffff82525ae0 ? Xintr_ioapic_edge15 +ffffffff82525b10 ? Xintr_ioapic_edge16 +ffffffff82525b40 ? Xintr_ioapic_edge17 +ffffffff82525b70 ? Xintr_ioapic_edge18 +ffffffff82525ba0 ? Xintr_ioapic_edge19 +ffffffff82525bd0 ? Xintr_ioapic_edge20 +ffffffff82525c00 ? Xintr_ioapic_edge21 +ffffffff82525c30 ? Xintr_ioapic_edge22 +ffffffff82525c60 ? Xintr_ioapic_edge23 +ffffffff82525c90 ? Xintr_ioapic_edge24 +ffffffff82525cc0 ? Xintr_ioapic_edge25 +ffffffff82525cf0 ? Xintr_ioapic_edge26 +ffffffff82525d20 ? Xintr_ioapic_edge27 +ffffffff82525d50 ? Xintr_ioapic_edge28 +ffffffff82525d80 ? Xintr_ioapic_edge29 +ffffffff82525db0 ? Xintr_ioapic_edge30 +ffffffff82525de0 ? Xintr_ioapic_edge31 +ffffffff82525e10 ? Xintr_ioapic_edge32 +ffffffff82525e40 ? Xintr_ioapic_edge33 +ffffffff82525e70 ? Xintr_ioapic_edge34 +ffffffff82525ea0 ? Xintr_ioapic_edge35 +ffffffff82525ed0 ? Xintr_ioapic_edge36 +ffffffff82525f00 ? Xintr_ioapic_edge37 +ffffffff82525f30 ? Xintr_ioapic_edge38 +ffffffff82525f60 ? Xintr_ioapic_edge39 +ffffffff82525f90 ? Xintr_ioapic_edge40 +ffffffff82525fc0 ? Xintr_ioapic_edge41 +ffffffff82525ff0 ? Xintr_ioapic_edge42 +ffffffff82526020 ? Xintr_ioapic_edge43 +ffffffff82526050 ? Xintr_ioapic_edge44 +ffffffff82526080 ? Xintr_ioapic_edge45 +ffffffff825260b0 ? Xintr_ioapic_edge46 +ffffffff825260e0 ? Xintr_ioapic_edge47 +ffffffff82526110 ? Xintr_ioapic_edge48 +ffffffff82526140 ? Xintr_ioapic_edge49 +ffffffff82526170 ? Xintr_ioapic_edge50 +ffffffff825261a0 ? Xintr_ioapic_edge51 +ffffffff825261d0 ? Xintr_ioapic_edge52 +ffffffff82526200 ? Xintr_ioapic_edge53 +ffffffff82526230 ? Xintr_ioapic_edge54 +ffffffff82526260 ? Xintr_ioapic_edge55 +ffffffff82526290 ? Xintr_ioapic_edge56 +ffffffff825262c0 ? Xintr_ioapic_edge57 +ffffffff825262f0 ? Xintr_ioapic_edge58 +ffffffff82526320 ? Xintr_ioapic_edge59 +ffffffff82526350 ? Xintr_ioapic_edge60 +ffffffff82526380 ? Xintr_ioapic_edge61 +ffffffff825263b0 ? Xintr_ioapic_edge62 +ffffffff825263e0 ? Xintr_ioapic_edge63 +ffffffff82526410 ? Xintr_ioapic_level0 +ffffffff82526440 ? Xintr_ioapic_level1 +ffffffff82526470 ? Xintr_ioapic_level2 +ffffffff825264a0 ? Xintr_ioapic_level3 +ffffffff825264d0 ? Xintr_ioapic_level4 +ffffffff82526500 ? Xintr_ioapic_level5 +ffffffff82526530 ? Xintr_ioapic_level6 +ffffffff82526560 ? Xintr_ioapic_level7 +ffffffff82526590 ? Xintr_ioapic_level8 +ffffffff825265c0 ? Xintr_ioapic_level9 +ffffffff825265f0 ? Xintr_ioapic_level10 +ffffffff82526620 ? Xintr_ioapic_level11 +ffffffff82526650 ? Xintr_ioapic_level12 +ffffffff82526680 ? Xintr_ioapic_level13 +ffffffff825266b0 ? Xintr_ioapic_level14 +ffffffff825266e0 ? Xintr_ioapic_level15 +ffffffff82526710 ? Xintr_ioapic_level16 +ffffffff82526740 ? Xintr_ioapic_level17 +ffffffff82526770 ? Xintr_ioapic_level18 +ffffffff825267a0 ? Xintr_ioapic_level19 +ffffffff825267d0 ? Xintr_ioapic_level20 +ffffffff82526800 ? Xintr_ioapic_level21 +ffffffff82526830 ? Xintr_ioapic_level22 +ffffffff82526860 ? Xintr_ioapic_level23 +ffffffff82526890 ? Xintr_ioapic_level24 +ffffffff825268c0 ? Xintr_ioapic_level25 +ffffffff825268f0 ? Xintr_ioapic_level26 +ffffffff82526920 ? Xintr_ioapic_level27 +ffffffff82526950 ? Xintr_ioapic_level28 +ffffffff82526980 ? Xintr_ioapic_level29 +ffffffff825269b0 ? Xintr_ioapic_level30 +ffffffff825269e0 ? Xintr_ioapic_level31 +ffffffff82526a10 ? Xintr_ioapic_level32 +ffffffff82526a40 ? Xintr_ioapic_level33 +ffffffff82526a70 ? Xintr_ioapic_level34 +ffffffff82526aa0 ? Xintr_ioapic_level35 +ffffffff82526ad0 ? Xintr_ioapic_level36 +ffffffff82526b00 ? Xintr_ioapic_level37 +ffffffff82526b30 ? Xintr_ioapic_level38 +ffffffff82526b60 ? Xintr_ioapic_level39 +ffffffff82526b90 ? Xintr_ioapic_level40 +ffffffff82526bc0 ? Xintr_ioapic_level41 +ffffffff82526bf0 ? Xintr_ioapic_level42 +ffffffff82526c20 ? Xintr_ioapic_level43 +ffffffff82526c50 ? Xintr_ioapic_level44 +ffffffff82526c80 ? Xintr_ioapic_level45 +ffffffff82526cb0 ? Xintr_ioapic_level46 +ffffffff82526ce0 ? Xintr_ioapic_level47 +ffffffff82526d10 ? Xintr_ioapic_level48 +ffffffff82526d40 ? Xintr_ioapic_level49 +ffffffff82526d70 ? Xintr_ioapic_level50 +ffffffff82526da0 ? Xintr_ioapic_level51 +ffffffff82526dd0 ? Xintr_ioapic_level52 +ffffffff82526e00 ? Xintr_ioapic_level53 +ffffffff82526e30 ? Xintr_ioapic_level54 +ffffffff82526e60 ? Xintr_ioapic_level55 +ffffffff82526e90 ? Xintr_ioapic_level56 +ffffffff82526ec0 ? Xintr_ioapic_level57 +ffffffff82526ef0 ? Xintr_ioapic_level58 +ffffffff82526f20 ? Xintr_ioapic_level59 +ffffffff82526f50 ? Xintr_ioapic_level60 +ffffffff82526f80 ? Xintr_ioapic_level61 +ffffffff82526fb0 ? Xintr_ioapic_level62 +ffffffff82526fe0 ? Xintr_ioapic_level63 +ffffffff82528000 ? codepatch_fill_nop +ffffffff82528000 A __cptext_start +ffffffff82528000 A __kutext_end +ffffffff825280b0 ? codepatch_maprw +ffffffff82528190 ? codepatch_unmaprw +ffffffff825281f0 ? codepatch_nop +ffffffff82528340 ? codepatch_replace +ffffffff825284e0 ? codepatch_call +ffffffff82528500 ? codepatch_jmp +ffffffff82529000 A __cptext_end +ffffffff82529000 A __rodata_start +ffffffff82529000 C _etext +ffffffff82529000 C etext +ffffffff8252a000 r seeprom_read +ffffffff8252a004 r icl_mg_pll_find_divisors.div1_vals +ffffffff8252a028 r gen9bc_tgp_ddc_pin_map +ffffffff8252a038 r athn_ac2qid +ffffffff8252a038 r athn_ac2qid +ffffffff8252a038 r athn_ac2qid +ffffffff8252a044 r rtwn_get_rssi.cckoff +ffffffff8252a06c r rsu_ac2qid +ffffffff8252a07c r pckbc_portcmd +ffffffff8252a080 r tht_fifo_write_pad.pad +ffffffff8252a088 r rsu_get_rssi.cckoff +ffffffff8252a09c r adlp_n_revids +ffffffff8252a0ec r apple_iso_trans +ffffffff8252a0f0 r dg2_g12_revid_step_tbl +ffffffff8252a0f8 r wihap_check_tx.txratetable +ffffffff8252a0fc r dmamode +ffffffff8252a124 r gen9_edram_size_mb.sets +ffffffff8252b000 r isomappings +ffffffff8252b080 r unimappings +ffffffff8252b230 r replacements +ffffffff8252eaff r cmd0646_9_tim_udma +ffffffff8258249e r pp_r600_decoded_lanes +ffffffff8259d797 r cmd680_setup_channel.udma_tbl +ffffffff825a5403 r apollo_udma33_tim +ffffffff825ab4f0 r substchar +ffffffff825ad596 r apollo_udma100_tim +ffffffff825d4e94 r apollo_udma66_tim +ffffffff825dc315 r apollo_pio_rec +ffffffff825eb6a6 r cy_pio_rec +ffffffff8261aa9a r apollo_udma133_tim +ffffffff826275b8 R drm_ca +ffffffff826275e0 R drm_filtops +ffffffff82627610 R drmread_filtops +ffffffff82628000 r vga_emulops +ffffffff82628048 R vga_stdscreen +ffffffff82628078 R vga_stdscreen_mono +ffffffff826280a8 R vga_stdscreen_bf +ffffffff826280d8 R vga_40lscreen +ffffffff82628108 R vga_40lscreen_mono +ffffffff82628138 R vga_40lscreen_bf +ffffffff82628168 R vga_50lscreen +ffffffff82628198 R vga_50lscreen_mono +ffffffff826281c8 R vga_50lscreen_bf +ffffffff826281f8 R vga_screenlist +ffffffff82628208 R vga_screenlist_mono +ffffffff82628218 R vga_accessops +ffffffff82628278 r i945_wm_info +ffffffff826282b0 r bgansitopc +ffffffff826282b8 r pctoansi +ffffffff826282f8 r sdma_offsets +ffffffff826282f8 r sdma_offsets +ffffffff82628328 r iha_rate_tbl +ffffffff82628360 r i830_a_wm_info +ffffffff82628398 r gen9_edram_size_mb.ways +ffffffff82628400 r aggr_periodic_times +ffffffff82628480 r jsl_ehl_revids +ffffffff826284f8 r michael_final.pad +ffffffff82628520 r rt_copysa.maskarray +ffffffff82628528 r i915_wm_info +ffffffff82628530 r amdgpu_ih_clientid_jpeg +ffffffff82628530 r amdgpu_ih_clientid_uvds +ffffffff82628530 r amdgpu_ih_clientid_vcns +ffffffff82628530 r amdgpu_ih_clientid_vcns +ffffffff82628530 r amdgpu_ih_clientid_vcns +ffffffff82628568 r vga_setfontset.cmaptabb +ffffffff82628580 r tgl_revids +ffffffff826285d8 r i830_bc_wm_info +ffffffff82628648 r hsw_activate_psr2.map +ffffffff82628688 r __drm_universal_plane_init.default_modifiers +ffffffff82628698 r iwn_tid2fifo +ffffffff826286b0 r vga_setfontset.cmaptaba +ffffffff826286b8 r crtc_offsets +ffffffff826286b8 r crtc_offsets +ffffffff826286b8 r crtc_offsets +ffffffff826286d8 r link_speed +ffffffff826286d8 r link_speed +ffffffff826286d8 r link_speed +ffffffff82628750 r rtwn_r88e_get_rssi.cckoff +ffffffff82629000 R edid_vendors +ffffffff826292c0 R edid_nvendors +ffffffff826292d0 R edid_products +ffffffff82629330 R edid_nproducts +ffffffff82629340 r _edid_modes +ffffffff8262a000 R videomode_list +ffffffff8262b080 R videomode_count +ffffffff8262c000 r ahc_hard_errors +ffffffff8262c080 r critical_sections +ffffffff8262c0b0 r patches +ffffffff8262cd50 r seqprog +ffffffff8262e000 r ahc_switch +ffffffff8262f000 r termstat_strings +ffffffff8262f020 r critical_sections +ffffffff8262f060 r seqprog +ffffffff8262fd50 r patches +ffffffff82631000 r ahd_switch +ffffffff82632000 R aic_switch +ffffffff82633000 R adw_switch +ffffffff82634000 R gdt_switch +ffffffff82635000 R twe_switch +ffffffff82636000 R ciss_switch +ffffffff82636030 R ciss_level +ffffffff82636050 R ciss_stat +ffffffff82637000 R ami_switch +ffffffff82637028 R ami_raw_switch +ffffffff82638000 R mfi_switch +ffffffff82638028 R mfi_pd_switch +ffffffff82638050 r mfi_iop_xscale +ffffffff82638080 r mfi_iop_ppc +ffffffff826380b0 r mfi_iop_gen2 +ffffffff826380e0 r mfi_iop_skinny +ffffffff82638110 r mfi_bbu_indicators +ffffffff826381c0 r bwi_rf_calc_nrssi_slope_11b.save_phy_regs +ffffffff826381f0 r chv_oa_mux_regs +ffffffff82638210 r fiji_clock_stretcher_lookup_table +ffffffff82638210 r tonga_clock_stretcher_lookup_table +ffffffff82638240 r link_speed +ffffffff82638240 r link_speed +ffffffff82638240 r link_speed +ffffffff82638280 r drm_fb_xfrm.default_dst_pitch +ffffffff82638280 r non_supported_protection +ffffffff82638380 r tgl_uy_revids +ffffffff826383d0 r bwi_phy_noise_11g_rev1 +ffffffff82638450 r cardslot_process_event.antonym_ev +ffffffff826384e0 r gen11_oa_mux_regs +ffffffff826385d0 r ddr2_cycle_tenths +ffffffff82638640 r rtw_intr_rx.ratetbl +ffffffff826386c0 r abm_config +ffffffff82638730 r getbootinfo.ports.30 +ffffffff82638780 r reg_offsets +ffffffff82638790 r bwi_rf_lo_measure_11g.rf_lo_adjust +ffffffff826387a0 r init_non_clock_fields.look_up +ffffffff826387b0 r uftdi_8u232am_getrate.roundoff +ffffffff82638800 r zyd_rx_data.rates +ffffffff82638810 r ieee80211_ra_valid_tx_mcs.max_mcs +ffffffff82638850 r mmio_invalidate_full.gen8_regs +ffffffff82638880 r bwi_phy_noise_11g +ffffffff82638890 r hpt366_pio +ffffffff826388c0 r glk_revids +ffffffff82638910 r bwi_rf_calc_nrssi_slope_11g.save_phy3_regs +ffffffff82638930 r ether_crc32_be_update.rev +ffffffff82638930 r rtw_grf5101_mac_crypt.caesar +ffffffff82638980 r snb_b_fdi_train_param +ffffffff82639000 R qlw_switch +ffffffff8263a000 R isp_2100_risc_code +ffffffff8264cbf0 R isp_2200_risc_code +ffffffff8265f990 R isp_2300_risc_code +ffffffff82679408 R qla_switch +ffffffff82679430 r qla_regs_2100 +ffffffff82679460 r qla_regs_2200 +ffffffff82679490 r qla_regs_23XX +ffffffff8267a000 R ahci_atascsi_methods +ffffffff8267b000 R nvme_switch +ffffffff8267b028 r nvme_ops +ffffffff8267c000 R mpi_switch +ffffffff8267c100 r intel_hpll_vco.elk_vco +ffffffff8267c160 r pin_offsets +ffffffff8267c1c0 r firmware_list +ffffffff8267c220 r atom_arg_shift +ffffffff8267c220 r atom_arg_shift +ffffffff8267c260 r pf_syncookie_wstab +ffffffff8267c280 r ieee80211_media_init.mopts +ffffffff8267c2e0 r add_entropy_words.twist_table +ffffffff8267c380 r urtw_8225v2_txpwr_cck +ffffffff8267c3a0 r bwfm_pci_prio2fifo +ffffffff8267c3a0 r ieee80211_up_to_ac.up_to_ac +ffffffff8267c460 r paritytab +ffffffff8267c460 r x86emu_parity_tab +ffffffff8267c480 r legacy_connector_convert +ffffffff8267c4c0 r gen7_oa_mux_regs +ffffffff8267c4e0 r hsw_oa_mux_regs +ffffffff8267c500 r notetab +ffffffff8267c520 r urtw_8225v2_txpwr_cck_ch14 +ffffffff8267c540 r bwi_rf_calibval.rf_calibvals +ffffffff8267c5e0 r pf_syncookie_msstab +ffffffff8267c640 r xgmi3x16_pcs_err_status_reg_aldebaran +ffffffff8267c6a0 r uath_wme_init.uath_wme_11g +ffffffff8267c6c0 r gen7_oa_b_counters +ffffffff8267c820 r icl_revids +ffffffff8267c8e0 r rtwn_iq_calib_run.reg_adda +ffffffff8267c920 r atom_def_dst +ffffffff8267c920 r atom_def_dst +ffffffff8267c960 r sha256_initial_hash_value +ffffffff8267c9c0 r otus_edca_def +ffffffff8267c9e0 r intel_hpll_vco.blb_vco +ffffffff8267caa0 r epic_pci_subsys_info +ffffffff8267cac0 r atom_arg_mask +ffffffff8267cac0 r atom_arg_mask +ffffffff8267cb20 r butmap +ffffffff8267cb60 r GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS +ffffffff8267cba0 r comsoft.lsrmap +ffffffff8267cbe0 r tulip_mii_phy_readspecific.table +ffffffff8267cc00 r kbl_revids +ffffffff8267cca0 r intel_hpll_vco.pnv_vco +ffffffff8267cd00 r dmapageport +ffffffff8267cdc0 r intel_hpll_vco.ctg_vco +ffffffff8267ce80 r drm_calculate_luminance_range.pre_computed_values +ffffffff8267d000 R sili_atascsi_methods +ffffffff8267e000 R ncr53c9x_switch +ffffffff8267f000 r scf_period +ffffffff82680000 R siop_script +ffffffff826805a0 R lun_switch +ffffffff826805d0 R tag_switch +ffffffff82680660 R load_dsa +ffffffff826806c4 R siop_led_on +ffffffff826806cc R siop_led_off +ffffffff826806d8 R siop_switch +ffffffff82681000 R ep_vortex_media +ffffffff82681100 R ep_default_to_media +ffffffff82682000 R wi_card_ident +ffffffff82684000 R ucode_table +ffffffff82685000 r re_revisions +ffffffff82685290 r re_kstats_tpl +ffffffff82687000 R smc91cxx_media +ffffffff82687010 R smc91cxx_mii_bitbang_ops +ffffffff82688000 R dl10019_mii_bitbang_ops +ffffffff82688028 R dl10022_mii_bitbang_ops +ffffffff82689000 R ax88190_mii_bitbang_ops +ffffffff8268b000 R ac97_audio_default +ffffffff8268b020 R ac97_on_off +ffffffff8268b324 R ac97_mic_select +ffffffff8268b628 R ac97_mono_select +ffffffff8268b92c R ac97_source +ffffffff8268bc30 R ac97_volume_stereo +ffffffff8268bc4c R ac97_volume_mono +ffffffff8268bc70 R source_info +ffffffff8268c470 R ac97_ad +ffffffff8268c580 R ac97_ak +ffffffff8268c610 R ac97_av +ffffffff8268c750 R ac97_rl +ffffffff8268c7a0 R ac97_cm +ffffffff8268c820 R ac97_cr +ffffffff8268c840 R ac97_cs +ffffffff8268c920 R ac97_cx +ffffffff8268c980 R ac97_dt +ffffffff8268c9a0 R ac97_em +ffffffff8268c9d0 R ac97_es +ffffffff8268c9f0 R ac97_is +ffffffff8268ca10 R ac97_ic +ffffffff8268ca90 R ac97_it +ffffffff8268cac0 R ac97_ns +ffffffff8268cb80 R ac97_ps +ffffffff8268cbb0 R ac97_sl +ffffffff8268cbd0 R ac97_st +ffffffff8268cd20 R ac97_vi +ffffffff8268cd50 R ac97_tt +ffffffff8268cdd0 R ac97_ti +ffffffff8268cdf0 R ac97_wb +ffffffff8268ce10 R ac97_wo +ffffffff8268cea0 R ac97_ym +ffffffff8268cef0 R ac97_vendors +ffffffff8268d1f0 R ac97enhancement +ffffffff8268d2f0 R ac97feature +ffffffff8268e000 R lm_chips +ffffffff8268e020 R lm78_sensors +ffffffff8268e1a0 R w83627hf_sensors +ffffffff8268e3a0 R w83627ehf_sensors +ffffffff8268e5c0 R w83627dhg_sensors +ffffffff8268e7c0 R nct6776f_sensors +ffffffff8268ea00 R nct6779d_sensors +ffffffff8268ed60 R w83637hf_sensors +ffffffff8268ef20 R w83697hf_sensors +ffffffff8268f0c0 R w83781d_sensors +ffffffff8268f280 R w83782d_sensors +ffffffff8268f480 R w83783s_sensors +ffffffff8268f600 R w83791d_sensors +ffffffff8268f860 R w83792d_sensors +ffffffff8268fae0 R as99127f_sensors +ffffffff82690000 r ar5k_known_products +ffffffff82690110 r ar5111_gain_opt +ffffffff826901e0 r ar5112_gain_opt +ffffffff826902b0 r ar5k_5ghz_channels +ffffffff82690a00 r ar5k_2ghz_channels +ffffffff82690f10 r ar5111_rf +ffffffff82691350 r ar5112a_rf +ffffffff82691890 r ar5112_rf +ffffffff82691da0 r ar5413_rf +ffffffff826921b0 r ar2413_rf +ffffffff826924d0 r ar2425_rf +ffffffff82692830 r ar5111_rfg +ffffffff82692b30 r ar5112_rfg +ffffffff82692e30 r ar5413_rfg +ffffffff82693130 r ar2413_rfg +ffffffff82693430 r ar5k_rt_11a +ffffffff82693552 r ar5k_rt_11b +ffffffff82693674 r ar5k_rt_11g +ffffffff82693796 r ar5k_rt_xr +ffffffff82694000 r ar5210_ini +ffffffff82695000 r ar5211_mode +ffffffff826952c0 r ar5211_ini +ffffffff82695ad0 r ar5211_rf +ffffffff82696000 r ar5212_pcie +ffffffff82696080 r ar5212_mode +ffffffff82696310 r ar5212_ini +ffffffff82696c80 r ar5212_ar5111_mode +ffffffff82696f20 r ar5212_ar5112_mode +ffffffff826971b0 r ar5413_mode +ffffffff82697b10 r ar2413_mode +ffffffff82698430 r ar2425_mode +ffffffff82698d90 r ar5111_bbgain +ffffffff82699090 r ar5112_bbgain +ffffffff8269a000 r athn_5ghz_chans +ffffffff8269a020 r athn_rates +ffffffff8269b000 r athn_rates +ffffffff8269c000 r ar9160_ini +ffffffff8269c068 r ar5416_ini +ffffffff8269c0d0 r ar5416_serdes +ffffffff8269c0e8 r ar9160_1_1_addac +ffffffff8269c0f8 r ar9160_1_0_addac +ffffffff8269c108 r ar5416_2_2_addac +ffffffff8269c118 r ar5416_2_1_addac +ffffffff8269c128 r ar5416_set_power_calib.chainoffset +ffffffff8269c140 r ar9160_bank6tpc_vals +ffffffff8269c1c0 r ar5416_bank6tpc_vals +ffffffff8269c240 r ar5416_bb_rfgain_vals_2g +ffffffff8269c340 r ar5416_bb_rfgain_vals_5g +ffffffff8269c440 r ar5416_bank6_vals +ffffffff8269c4c0 r ar9160_regs +ffffffff8269c540 r ar9160_vals_5g20 +ffffffff8269c640 r ar9160_vals_5g40 +ffffffff8269c740 r ar9160_vals_2g40 +ffffffff8269c840 r ar9160_vals_2g20 +ffffffff8269c940 r ar9160_cm_regs +ffffffff8269cc30 r ar9160_cm_vals +ffffffff8269d210 r ar5416_regs +ffffffff8269d290 r ar5416_vals_5g20 +ffffffff8269d390 r ar5416_vals_5g40 +ffffffff8269d490 r ar5416_vals_2g40 +ffffffff8269d590 r ar5416_vals_2g20 +ffffffff8269d690 r ar5416_cm_regs +ffffffff8269d980 r ar5416_cm_vals +ffffffff8269df60 r ar5416_serdes_regs +ffffffff8269df90 r ar5416_serdes_vals +ffffffff8269dfc0 r ar9160_1_1_addac_vals +ffffffff8269e040 r ar9160_1_0_addac_vals +ffffffff8269e0c0 r ar5416_2_2_addac_vals +ffffffff8269e150 r ar5416_2_1_addac_vals +ffffffff8269f000 r ar9280_2_0_ini +ffffffff8269f068 r ar9280_2_0_serdes +ffffffff8269f080 r ar9280_2_0_rx_gain_23db_backoff +ffffffff8269f0a0 r ar9280_2_0_rx_gain_13db_backoff +ffffffff8269f0c0 r ar9280_2_0_rx_gain +ffffffff8269f0e0 r ar9280_2_0_tx_gain_high_power +ffffffff8269f100 r ar9280_2_0_tx_gain +ffffffff8269f120 r ar9280_init_from_rom.chainoffset +ffffffff8269f130 r ar9280_2_0_regs +ffffffff8269f190 r ar9280_2_0_vals_5g20 +ffffffff8269f250 r ar9280_2_0_vals_5g40 +ffffffff8269f310 r ar9280_2_0_vals_2g40 +ffffffff8269f3d0 r ar9280_2_0_vals_2g20 +ffffffff8269f490 r ar9280_2_0_cm_regs +ffffffff8269f740 r ar9280_2_0_cm_vals +ffffffff8269fc90 r ar9280_2_0_fast_clock_regs +ffffffff8269fcb0 r ar9280_2_0_fast_clock_vals_5g20 +ffffffff8269fcf0 r ar9280_2_0_fast_clock_vals_5g40 +ffffffff8269fd30 r ar9280_2_0_serdes_regs +ffffffff8269fd60 r ar9280_2_0_serdes_vals +ffffffff8269fd90 r ar9280_2_0_rx_gain_regs +ffffffff8269fea0 r ar9280_2_0_rx_gain_23db_backoff_vals_5g +ffffffff826a00b0 r ar9280_2_0_rx_gain_23db_backoff_vals_2g +ffffffff826a02c0 r ar9280_2_0_rx_gain_13db_backoff_vals_5g +ffffffff826a04d0 r ar9280_2_0_rx_gain_13db_backoff_vals_2g +ffffffff826a06e0 r ar9280_2_0_rx_gain_vals_5g +ffffffff826a08f0 r ar9280_2_0_rx_gain_vals_2g +ffffffff826a0b00 r ar9280_2_0_tx_gain_regs +ffffffff826a0b40 r ar9280_2_0_tx_gain_high_power_vals_5g +ffffffff826a0bc0 r ar9280_2_0_tx_gain_high_power_vals_2g +ffffffff826a0c40 r ar9280_2_0_tx_gain_vals_5g +ffffffff826a0cc0 r ar9280_2_0_tx_gain_vals_2g +ffffffff826a1000 r ar9271_ini +ffffffff826a1068 r ar9285_1_2_ini +ffffffff826a10d0 r ar9280_2_0_serdes +ffffffff826a10e8 r ar9271_tx_gain_high_power +ffffffff826a1108 r ar9271_tx_gain +ffffffff826a1128 r ar9285_2_0_tx_gain_high_power +ffffffff826a1148 r ar9285_2_0_tx_gain +ffffffff826a1168 r ar9285_1_2_tx_gain_high_power +ffffffff826a1188 r ar9285_1_2_tx_gain +ffffffff826a11b0 r ar9271_regs +ffffffff826a1410 r ar9271_vals_2g40 +ffffffff826a18d0 r ar9271_vals_2g20 +ffffffff826a1d90 r ar9271_cm_regs +ffffffff826a2020 r ar9271_cm_vals +ffffffff826a2540 r ar9285_1_2_regs +ffffffff826a27a0 r ar9285_1_2_vals_2g40 +ffffffff826a2c60 r ar9285_1_2_vals_2g20 +ffffffff826a3120 r ar9285_1_2_cm_regs +ffffffff826a33a0 r ar9285_1_2_cm_vals +ffffffff826a3890 r ar9280_2_0_serdes_regs +ffffffff826a38c0 r ar9280_2_0_serdes_vals +ffffffff826a38f0 r ar9271_tx_gain_regs +ffffffff826a3940 r ar9271_tx_gain_high_power_vals_2g +ffffffff826a39d0 r ar9271_tx_gain_vals_2g +ffffffff826a3a60 r ar9285_1_2_tx_gain_regs +ffffffff826a3ab0 r ar9285_2_0_tx_gain_high_power_vals_2g +ffffffff826a3b50 r ar9285_2_0_tx_gain_vals_2g +ffffffff826a3bf0 r ar9285_1_2_tx_gain_high_power_vals_2g +ffffffff826a3c90 r ar9285_1_2_tx_gain_vals_2g +ffffffff826a4000 r ar9287_1_1_ini +ffffffff826a4068 r ar9280_2_0_serdes +ffffffff826a4080 r ar9287_1_1_rx_gain +ffffffff826a40a0 r ar9287_1_1_tx_gain +ffffffff826a40c0 r ar9287_1_1_regs +ffffffff826a4120 r ar9287_1_1_vals_2g40 +ffffffff826a41d0 r ar9287_1_1_vals_2g20 +ffffffff826a4280 r ar9287_1_1_cm_regs +ffffffff826a4560 r ar9287_1_1_cm_vals +ffffffff826a4b20 r ar9280_2_0_serdes_regs +ffffffff826a4b50 r ar9280_2_0_serdes_vals +ffffffff826a4b80 r ar9287_1_1_rx_gain_regs +ffffffff826a4d90 r ar9287_1_1_rx_gain_vals_2g +ffffffff826a51a0 r ar9287_1_1_tx_gain_regs +ffffffff826a5200 r ar9287_1_1_tx_gain_vals_2g +ffffffff826a6000 r athn_rates +ffffffff826a7000 r ar9485_1_1_ini +ffffffff826a7068 r ar9485_1_1_serdes +ffffffff826a7080 r ar9380_2_2_ini +ffffffff826a70e8 r ar9380_2_2_serdes +ffffffff826a7100 r ar9380_2_2_rx_gain_wo_xlna +ffffffff826a7120 r ar9380_2_2_rx_gain +ffffffff826a7140 r ar9485_1_1_rx_gain +ffffffff826a7160 r ar9380_2_2_tx_gain_high_ob_db +ffffffff826a7180 r ar9380_2_2_tx_gain_low_ob_db +ffffffff826a71a0 r ar9380_2_2_tx_gain_high_power +ffffffff826a71c0 r ar9380_2_2_tx_gain +ffffffff826a71e0 r ar9485_1_1_tx_gain +ffffffff826a7200 r ar9485_1_1_regs +ffffffff826a7270 r ar9485_1_1_vals_2g40 +ffffffff826a7350 r ar9485_1_1_vals_2g20 +ffffffff826a7430 r ar9485_1_1_cm_regs +ffffffff826a7720 r ar9485_1_1_cm_vals +ffffffff826a7d00 r ar9485_1_1_serdes_regs +ffffffff826a7d0c r ar9485_1_1_serdes_vals +ffffffff826a7d20 r ar9380_2_2_regs +ffffffff826a7db0 r ar9380_2_2_vals_5g20 +ffffffff826a7ed0 r ar9380_2_2_vals_5g40 +ffffffff826a7ff0 r ar9380_2_2_vals_2g40 +ffffffff826a8110 r ar9380_2_2_vals_2g20 +ffffffff826a8230 r ar9380_2_2_cm_regs +ffffffff826a85d0 r ar9380_2_2_cm_vals +ffffffff826a8d00 r ar9380_2_2_fast_clock_regs +ffffffff826a8d20 r ar9380_2_2_fast_clock_vals_5g20 +ffffffff826a8d50 r ar9380_2_2_fast_clock_vals_5g40 +ffffffff826a8d74 r ar9380_2_2_serdes_regs +ffffffff826a8d80 r ar9380_2_2_serdes_vals +ffffffff826a8d90 r ar9380_2_2_rx_gain_regs +ffffffff826a8f90 r ar9380_2_2_rx_gain_wo_xlna_vals +ffffffff826a9390 r ar9380_2_2_rx_gain_vals +ffffffff826a9790 r ar9485_1_1_rx_gain_regs +ffffffff826a9890 r ar9485_1_1_rx_gain_vals +ffffffff826a9a90 r ar9380_2_2_tx_gain_regs +ffffffff826a9b60 r ar9380_2_2_tx_gain_high_ob_db_vals_5g +ffffffff826a9d00 r ar9380_2_2_tx_gain_high_ob_db_vals_2g +ffffffff826a9ea0 r ar9380_2_2_tx_gain_low_ob_db_vals_5g +ffffffff826aa040 r ar9380_2_2_tx_gain_low_ob_db_vals_2g +ffffffff826aa1e0 r ar9380_2_2_tx_gain_high_power_vals_5g +ffffffff826aa380 r ar9380_2_2_tx_gain_high_power_vals_2g +ffffffff826aa520 r ar9380_2_2_tx_gain_vals_5g +ffffffff826aa6c0 r ar9380_2_2_tx_gain_vals_2g +ffffffff826aa860 r ar9485_1_1_tx_gain_regs +ffffffff826aa8f0 r ar9485_1_1_tx_gain_vals_2g +ffffffff826aaa10 r ar9380_def_rom +ffffffff826aae50 r ar9380_def_rom_h112 +ffffffff826ab290 r ar9380_def_rom_h116 +ffffffff826ab6d0 r ar9380_def_rom_x112 +ffffffff826abb10 r ar9380_def_rom_x113 +ffffffff826ac000 R atw_txthresh_tab_lo +ffffffff826ac050 R atw_txthresh_tab_hi +ffffffff826ac0a0 r atw_attach.empty_macaddr +ffffffff826ac0b0 r atw_attach.type_strings +ffffffff826ac0d0 r atw_rfmd2958_ifn +ffffffff826ac110 r atw_rfmd2958_rf1r +ffffffff826ac150 r atw_rxintr.rate_tbl +ffffffff826ad000 r rtw_identify_sta.empty_macaddr +ffffffff826ae000 r rtwn_set_key.etherzeroaddr +ffffffff826ae010 r rtl8188eu_rf_prog +ffffffff826ae030 r rtl8192e_rf_prog +ffffffff826ae060 r rtl8188ce_rf_prog +ffffffff826ae080 r rtl8188ru_rf_prog +ffffffff826ae0a0 r rtl8188cu_rf_prog +ffffffff826ae0c0 r rtl8192ce_rf_prog +ffffffff826ae0f0 r rtl8188ru_txagc +ffffffff826ae150 r rtl8188eu_rf_regs +ffffffff826ae1b0 r rtl8188eu_rf_vals +ffffffff826ae330 r rtl8192e_rf_regs +ffffffff826ae3a0 r rtl8192e_rf_vals +ffffffff826ae540 r rtl8192e_rf2_regs +ffffffff826ae590 r rtl8192e_rf2_vals +ffffffff826ae6d0 r rtl8192ce_rf1_regs +ffffffff826ae760 r rtl8188ce_rf_vals +ffffffff826ae9a0 r rtl8188ru_rf_vals +ffffffff826aebe0 r rtl8188cu_rf_vals +ffffffff826aee20 r rtl8192ce_rf1_vals +ffffffff826af060 r rtl8192ce_rf2_regs +ffffffff826af090 r rtl8192ce_rf2_vals +ffffffff826af130 r rtl8192cu_txagc +ffffffff826b0000 r rt2560_rf2522_r2 +ffffffff826b0040 r rt2560_rf2524_r2 +ffffffff826b0080 r rt2560_rf2525_hi_r2 +ffffffff826b00c0 r rt2560_rf2525_r2 +ffffffff826b0100 r rt2560_rf2525e_r2 +ffffffff826b0140 r rt2560_rf2526_hi_r2 +ffffffff826b0180 r rt2560_rf2526_r2 +ffffffff826b01c0 r rt2560_def_bbp +ffffffff826b0200 r rt2560_def_mac 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intel_hpll_vco.cl_vco +ffffffff826b6020 r sgpr_init_compute_shader +ffffffff826b60d0 r trinity_override_mgpg_sequences +ffffffff826b6490 r vgpr_init_compute_shader +ffffffff826b6550 r voltage_swing_to_pre_emphasis +ffffffff826b7000 r malo_cmd_string.cmds +ffffffff826b70b0 r malo_cmd_string_result.results +ffffffff826b8000 R bwi_vendor_led_act +ffffffff826b800c R bwi_default_led_act +ffffffff826b8010 R bwi_led_duration +ffffffff826b8380 r bwi_sup_bphy +ffffffff826b83c0 r bwi_phy_freq_11g_rev1 +ffffffff826b85c0 r bwi_phy_rotor_11g_rev1 +ffffffff826b86a0 r bwi_phy_noise_scale_11g_rev2 +ffffffff826b86e0 r bwi_phy_noise_scale_11g_rev7 +ffffffff826b8720 r bwi_phy_noise_scale_11g +ffffffff826b8760 r bwi_phy_sigma_sq_11g_rev2 +ffffffff826b87d0 r bwi_phy_sigma_sq_11g_rev7 +ffffffff826b8840 r bwi_phy_delay_11g_rev1 +ffffffff826b8920 r bwi_rf_get_gains.save_phy_regs +ffffffff826b8940 r bwi_rf_lo_find.map +ffffffff826b8960 r bwi_txpower_map_11b +ffffffff826b89a0 r bwi_txpower_map_11g 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dtps_static +ffffffff826cf000 R db_show_all_cmds +ffffffff826cf180 R db_show_cmds +ffffffff826cf4c0 R db_boot_cmds +ffffffff826cf5a0 R db_command_table +ffffffff826d0000 R ddb_vars +ffffffff826d1000 R audio_ca +ffffffff826d1028 R audioctlread_filtops +ffffffff826d1058 R audiowrite_filtops +ffffffff826d1088 R audioread_filtops +ffffffff826d2000 R midi_ca +ffffffff826d2028 R midiwrite_filtops +ffffffff826d2058 R midiread_filtops +ffffffff826d3000 r mulawtolin16 +ffffffff826d3200 r lintomulaw +ffffffff826d4000 R randomread_filtops +ffffffff826d4030 R randomwrite_filtops +ffffffff826d5000 R video_ca +ffffffff826d5028 R video_filtops +ffffffff826d6000 R cd9660_vfsops +ffffffff826d7000 R cd9660_vops +ffffffff826d7110 R cd9660_specvops +ffffffff826d7220 R cd9660_fifovops +ffffffff826d7330 R cd9660read_filtops +ffffffff826d7360 R cd9660write_filtops +ffffffff826d7390 R cd9660vnode_filtops +ffffffff826d8000 R udf_vfsops +ffffffff826d9000 R udf_vops +ffffffff826d9110 r mon_lens +ffffffff826da000 r month_days +ffffffff826db000 R execsw +ffffffff826dc000 r shstrtab +ffffffff826dd000 R copyright +ffffffff826dd0c0 r initpaths +ffffffff826de000 R sysent +ffffffff826e0000 R bufq_impls +ffffffff826e1000 R kqueueops +ffffffff826e1038 R kqread_filtops +ffffffff826e1068 R proc_filtops +ffffffff826e1098 R file_filtops +ffffffff826e10c8 R timer_filtops +ffffffff826e1100 R sysfilt_ops +ffffffff826e1148 R seltrue_filtops +ffffffff826e1178 R dead_filtops +ffffffff826e11a8 R badfd_filtops +ffffffff826e11d8 r mutex_klistops +ffffffff826e11f0 r rwlock_klistops +ffffffff826e2000 R kv_exec +ffffffff826e3000 R addrmask +ffffffff826e4000 r rw_ops +ffffffff826e5000 r proc_printit.pstat +ffffffff826e6000 R pledge_syscalls +ffffffff826e6a60 r pledgenames +ffffffff826e6cb0 r pledgereq +ffffffff826e7000 r unvname_rbt_RBT_INFO +ffffffff826e7018 R unvname_rbt_RBT_TYPE +ffffffff826e8000 R sig_filtops +ffffffff826e8030 R sigprop +ffffffff826e9000 R kern_vars +ffffffff826e92f0 R hw_vars +ffffffff826ea000 R tc_vars +ffffffff826eb000 r sys_gettimeofday.zerotz +ffffffff826ec000 r taskq_sys_name +ffffffff826ec006 r taskq_sys_mp_name +ffffffff826ec010 R systq +ffffffff826ec018 R systqmp +ffffffff826ee000 r gpt_get_fstype.gpt_uuid_openbsd +ffffffff826ee010 r gpt_get_fstype.gpt_uuid_msdos +ffffffff826ee020 r gpt_get_fstype.gpt_uuid_chromerootfs +ffffffff826ee030 r gpt_get_fstype.gpt_uuid_linux +ffffffff826ee040 r gpt_get_fstype.gpt_uuid_hfs +ffffffff826ee050 r gpt_get_fstype.gpt_uuid_unused +ffffffff826ee060 r gpt_get_fstype.gpt_uuid_efi_system +ffffffff826ee070 r gpt_get_fstype.gpt_uuid_bios_boot +ffffffff826ef000 r hiballoc_addr_RBT_INFO +ffffffff826ef018 R hiballoc_addr_RBT_TYPE +ffffffff826f0000 R logread_filtops +ffffffff826f1000 r phtree_RBT_INFO +ffffffff826f1018 R phtree_RBT_TYPE +ffffffff826f1020 r pool_lock_ops_rw +ffffffff826f1058 r pool_lock_ops_mtx +ffffffff826f2000 r pselregister.evf +ffffffff826f200c r pselregister.evff +ffffffff826f3000 R pipe_rfiltops +ffffffff826f3030 R pipe_wfiltops +ffffffff826f3060 R pipe_efiltops +ffffffff826f3090 r pipeops +ffffffff826f4000 R socketops +ffffffff826f5000 R sysvsem_vars +ffffffff826f6000 R char_type +ffffffff826f6100 R ttyread_filtops +ffffffff826f6130 R ttywrite_filtops +ffffffff826f6160 R ttyexcept_filtops +ffffffff826f7000 R ptcread_filtops +ffffffff826f7030 R ptcwrite_filtops +ffffffff826f7060 R ptcexcept_filtops +ffffffff826f9000 R domains +ffffffff826fa000 R unixdomain +ffffffff826fa050 R unixsw +ffffffff826fb000 R solisten_filtops +ffffffff826fb030 R soread_filtops +ffffffff826fb060 R sowrite_filtops +ffffffff826fb090 R soexcept_filtops +ffffffff826fb0c0 R socket_klistops +ffffffff826fc000 R sun_noname +ffffffff826fc010 R uipc_usrreqs +ffffffff826fc0b0 R uipc_dgram_usrreqs +ffffffff826fc150 R unpstctl_vars +ffffffff826fc180 R unpsqctl_vars +ffffffff826fc1b0 R unpdgctl_vars +ffffffff826fd000 r namecache_rb_cache_RBT_INFO +ffffffff826fd018 R namecache_rb_cache_RBT_TYPE +ffffffff826fe000 R generic_filtops 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egre_tree_RBT_INFO +ffffffff8271b068 R egre_tree_RBT_TYPE +ffffffff8271b070 r nvgre_ucast_tree_RBT_INFO +ffffffff8271b088 R nvgre_ucast_tree_RBT_TYPE +ffffffff8271b090 r nvgre_mcast_tree_RBT_INFO +ffffffff8271b0a8 R nvgre_mcast_tree_RBT_TYPE +ffffffff8271b0b0 r eoip_tree_RBT_INFO +ffffffff8271b0c8 R eoip_tree_RBT_TYPE +ffffffff8271b0d0 r nvgre_etherbridge_ops +ffffffff8271c000 r trunk_protos +ffffffff8271d000 R ethermulticastaddr_slowprotocols +ffffffff8271d006 R lacp_info_tlv_template +ffffffff8271d00e R marker_info_tlv_template +ffffffff8271d012 R marker_response_tlv_template +ffffffff8271d020 R lacp_timer_funcs +ffffffff8271e000 r lacp_rxm_state_names +ffffffff8271e040 r lacp_rxm_event_names +ffffffff8271e090 r aggr_port_selected_names +ffffffff8271e0b0 r lacp_mux_state_names +ffffffff8271e0e0 r lacp_mux_event_names +ffffffff8271e128 r lacp_address_slow +ffffffff8271f000 r tpmr_pf_ipv4 +ffffffff8271f018 r tpmr_pf_ipv6 +ffffffff82720000 r bpe_tree_RBT_INFO +ffffffff82720018 R bpe_tree_RBT_TYPE +ffffffff82720020 r bpe_etherbridge_ops +ffffffff82721000 R pppx_rd_filtops +ffffffff82721030 R pppx_wr_filtops +ffffffff82721060 r pppx_ifs_RBT_INFO +ffffffff82721078 R pppx_ifs_RBT_TYPE +ffffffff82721080 r pppac_rd_filtops +ffffffff827210b0 r pppac_wr_filtops +ffffffff82722000 r vxlan_peers_RBT_INFO +ffffffff82722018 R vxlan_peers_RBT_TYPE +ffffffff82722020 r vxlan_etherbridge_ops +ffffffff82723000 R stoeplitz_cache +ffffffff82724000 R ieee80211_std_rateset_11a +ffffffff82724010 R ieee80211_std_rateset_11b +ffffffff82724020 R ieee80211_std_rateset_11g +ffffffff82724030 R ieee80211_std_ratesets_11n +ffffffff827243b0 R ieee80211_std_ratesets_11ac +ffffffff827246b0 r ieee80211_setbasicrates.basic +ffffffff82724710 r ieee80211_setmode.chanflags +ffffffff82724730 r ieee80211_rate2media.rates +ffffffff827248c0 r ieee80211_media2rate.ieeerates +ffffffff82725000 r Sbox +ffffffff82727000 r ieee80211_ioctl.empty_macaddr +ffffffff82728000 r ieee80211_find_rxnode.zero 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auth_hash_hmac_sha2_256_128 +ffffffff827483a0 R auth_hash_hmac_sha2_384_192 +ffffffff827483e8 R auth_hash_hmac_sha2_512_256 +ffffffff82748430 R auth_hash_gmac_aes_128 +ffffffff82748478 R auth_hash_gmac_aes_192 +ffffffff827484c0 R auth_hash_gmac_aes_256 +ffffffff82748508 R auth_hash_chacha20_poly1305 +ffffffff82748550 R comp_algo_deflate +ffffffff82749000 r IV +ffffffff8274a000 r idgen32_ftable +ffffffff8274b000 r Chacha20_Poly1305_Update.zeroes +ffffffff8274b010 r pad0 +ffffffff8274c000 r null_point +ffffffff8274c020 r base_point +ffffffff8274d000 R mplsdomain +ffffffff8274e000 R mplsctl_vars +ffffffff8274f000 r nfs_nodetree_RBT_INFO +ffffffff8274f018 R nfs_nodetree_RBT_TYPE +ffffffff82750000 r nfsread_filtops +ffffffff82750030 r nfswrite_filtops +ffffffff82750060 r nfsvnode_filtops +ffffffff82751000 r nfsrv_v3errmap +ffffffff827510b0 r nfsrv_v2errmap +ffffffff82752000 R nfs_vfsops +ffffffff82753000 R nfs_vops +ffffffff82753110 R nfs_specvops +ffffffff82753220 R nfs_fifovops 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uaddr_free_rbtree_RBT_TYPE +ffffffff82761000 R aobj_pager +ffffffff82762000 R uvm_deviceops +ffffffff82763000 R kv_any +ffffffff82763018 R kv_intrsafe +ffffffff82763030 R kv_page +ffffffff82763048 R kp_dirty +ffffffff82763070 R kp_dma +ffffffff82763098 R kp_dma_contig +ffffffff827630c0 R kp_dma_zero +ffffffff827630e8 R kp_zero +ffffffff82763110 R kp_pageable +ffffffff82763138 R kp_none +ffffffff82763160 R kd_waitok +ffffffff82763178 R kd_nowait +ffffffff82763190 R kd_trylock +ffffffff82764000 R vmmapbsy +ffffffff82764010 r page_flagbits +ffffffff827640a8 r uvm_map_addr_RBT_INFO +ffffffff827640c0 R uvm_map_addr_RBT_TYPE +ffffffff82765000 R pmap_pager +ffffffff82765048 R bufcache_pager +ffffffff82766000 r uvm_objtree_RBT_INFO +ffffffff82766018 R uvm_objtree_RBT_TYPE +ffffffff82767000 r uvm_pmr_addr_RBT_INFO +ffffffff82767018 R uvm_pmr_addr_RBT_TYPE +ffffffff82767020 r uvm_pmr_size_RBT_INFO +ffffffff82767038 R uvm_pmr_size_RBT_TYPE +ffffffff82767040 r uvm_pmemrange_addr_RBT_INFO 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static_l_desc +ffffffff8277c320 r static_d_desc +ffffffff8277c340 r static_bl_desc +ffffffff8277c360 r static_ltree +ffffffff8277c7e0 r static_dtree +ffffffff8277c860 r extra_lbits +ffffffff8277c8e0 r extra_dbits +ffffffff8277c960 r extra_blbits +ffffffff8277c9b0 r bl_order +ffffffff8277c9d0 r base_length +ffffffff8277ca50 r base_dist +ffffffff8277d000 R nam2blk +ffffffff8277e000 R chrtoblktbl +ffffffff8277e0c0 R nchrtoblktbl +ffffffff8277f000 R cpuctl_vars +ffffffff82781000 R cpu_cpuid_features +ffffffff827811d0 R cpu_ecpuid_features +ffffffff82781260 R cpu_cpuid_ecxfeatures +ffffffff82781450 R cpu_ecpuid_ecxfeatures +ffffffff827815d0 R cpu_seff0_ebxfeatures +ffffffff827817a0 R cpu_seff0_ecxfeatures +ffffffff82781800 R cpu_seff0_edxfeatures +ffffffff827818a0 R cpu_tpm_eaxfeatures +ffffffff827818c0 R cpu_cpuid_perf_eax +ffffffff827818d0 R cpu_cpuid_apmi_edx +ffffffff827818e0 R cpu_amdspec_ebxfeatures +ffffffff82781940 R cpu_xsave_extfeatures +ffffffff82782000 R sigcode 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x86_soft_intr_to_ssir +ffffffff8278a000 R Xexceptions +ffffffff8278a100 r spl_lowered +ffffffff8278a12d R i8259_stubs +ffffffff8278a2ad R ioapic_edge_stubs +ffffffff8278a8ad R ioapic_level_stubs +ffffffff8278b000 R _stac +ffffffff8278b003 R _clac +ffffffff8278c000 R x86_bus_space_io_ops +ffffffff8278c130 R x86_bus_space_mem_ops +ffffffff8278d000 ? cpu_spinup_trampoline +ffffffff8278d0b6 R cpu_spinup_trampoline_end +ffffffff8278d0b6 R mp_tramp_data_start +ffffffff8278d0fc R mp_tramp_data_end +ffffffff8278f000 R db_acpi_cmds +ffffffff8278f0a0 R db_machine_command_table +ffffffff82790000 r i8254_delay.delaytab +ffffffff82791000 R rasops_cmap +ffffffff82792000 r reverse +ffffffff82792100 r ibm437_level1 +ffffffff82792230 r ibm437_level2_0 +ffffffff82792248 r ibm437_level2_1 +ffffffff82792260 r ibm437_level2_3 +ffffffff82792278 r ibm437_level2_32 +ffffffff82792290 r ibm437_level2_34 +ffffffff827922a8 r ibm437_level2_35 +ffffffff827922c0 r ibm437_level2_37 +ffffffff827922e0 r ibm437_chars_0 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rlphys +ffffffff8279d000 R lxtphy_ca +ffffffff8279d028 R lxtphy_funcs +ffffffff8279d040 R lxtphy971_funcs +ffffffff8279d060 r lxtphys +ffffffff8279e000 R luphy_ca +ffffffff8279e028 R luphy_funcs +ffffffff8279e040 r luphys +ffffffff8279f000 R mtdphy_ca +ffffffff8279f028 R mtdphy_funcs +ffffffff8279f040 r mtdphys +ffffffff827a0000 R icsphy_ca +ffffffff827a0028 R icsphy_funcs +ffffffff827a0040 r icsphys +ffffffff827a1000 R sqphy_ca +ffffffff827a1028 R sqphy_funcs +ffffffff827a1040 r sqphys +ffffffff827a2000 R tqphy_ca +ffffffff827a2028 R tqphy_funcs +ffffffff827a2040 r tqphys +ffffffff827a3000 R ukphy_ca +ffffffff827a3028 R ukphy_funcs +ffffffff827a4000 R dcphy_ca +ffffffff827a4028 R dcphy_funcs +ffffffff827a5000 R bmtphy_ca +ffffffff827a5028 R bmtphy_funcs +ffffffff827a5040 r bmtphys +ffffffff827a6000 R brgphy_ca +ffffffff827a6028 R brgphy_copper_funcs +ffffffff827a6040 R brgphy_fiber_funcs +ffffffff827a6058 R brgphy_5708s_funcs +ffffffff827a6070 R brgphy_5709s_funcs +ffffffff827a6090 r brgphys +ffffffff827a6300 r brgphy_bcm5401_dspcode.dspcode +ffffffff827a7000 R xmphy_ca +ffffffff827a7028 R xmphy_funcs +ffffffff827a7040 r xmphys +ffffffff827a8000 R amphy_ca +ffffffff827a8028 R amphy_funcs +ffffffff827a8040 r amphys +ffffffff827a9000 R acphy_ca +ffffffff827a9028 R acphy_funcs +ffffffff827a9040 r acphys +ffffffff827aa000 R nsgphy_ca +ffffffff827aa028 R nsgphy_funcs +ffffffff827aa040 r nsgphys +ffffffff827ab000 R urlphy_ca +ffffffff827ab028 R urlphy_funcs +ffffffff827ac000 R rgephy_ca +ffffffff827ac028 R rgephy_funcs +ffffffff827ac040 r rgephys +ffffffff827ad000 R ciphy_ca +ffffffff827ad028 R ciphy_funcs +ffffffff827ad040 r ciphys +ffffffff827ae000 R ipgphy_ca +ffffffff827ae028 R ipgphy_funcs +ffffffff827ae040 r ipgphys +ffffffff827af000 R etphy_funcs +ffffffff827af018 R etphy_ca +ffffffff827af040 r etphys +ffffffff827af060 r etphy_dspcode +ffffffff827b0000 R jmphy_funcs +ffffffff827b0018 R jmphy_ca +ffffffff827b0040 r jmphys +ffffffff827b1000 R atphy_funcs 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vio_ca +ffffffff827d9030 r virtio_net_feature_names +ffffffff827da000 R vioblk_ca +ffffffff827da028 R vioblk_switch +ffffffff827db000 R viomb_ca +ffffffff827db030 r viomb_feature_names +ffffffff827dc000 R viornd_ca +ffffffff827dd000 R vioscsi_ca +ffffffff827dd028 R vioscsi_switch +ffffffff827dd050 R vioscsi_vq_names +ffffffff827de000 R vmmci_ca +ffffffff827df000 R pci_ca +ffffffff827e0000 r pci_quirks +ffffffff827e1000 R pci_subclass_prehistoric +ffffffff827e1050 R pci_subclass_mass_storage +ffffffff827e1160 R pci_subclass_network +ffffffff827e1250 R pci_subclass_display +ffffffff827e12d0 R pci_subclass_multimedia +ffffffff827e1360 R pci_subclass_memory +ffffffff827e13c0 R pci_subclass_bridge +ffffffff827e1510 R pci_subclass_communications +ffffffff827e15d0 R pci_subclass_system +ffffffff827e16c0 R pci_subclass_input +ffffffff827e1770 R pci_subclass_dock +ffffffff827e17c0 R pci_subclass_processor +ffffffff827e1880 R pci_subclass_serialbus +ffffffff827e1990 R pci_subclass_wireless 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adw_asc38C0800_mcode_data +ffffffff8280d8a0 R adw_asc38C1600_mcode +ffffffff8280f160 R adw_asc38C1600_mcode_data +ffffffff82810000 R twe_pci_ca +ffffffff82810028 R twe_pci_devices +ffffffff82811000 R arc_ca +ffffffff82811028 R arc_switch +ffffffff82811050 r arc_devices +ffffffff82811190 r arc_intel +ffffffff82811198 r arc_marvell +ffffffff828111a0 r arc_lsi +ffffffff828111a8 r arc_marvell2 +ffffffff82812000 R jmb_ca +ffffffff82812030 r jmb_devices +ffffffff82813000 R ahci_pci_ca +ffffffff82813028 R ahci_jmb_ca +ffffffff82813050 r ahci_devices +ffffffff82814000 R nvme_pci_ca +ffffffff82814028 r nvme_msi_blacklist +ffffffff82815000 R ami_pci_ca +ffffffff82815030 r ami_pci_subsys +ffffffff82815270 r ami_pci_vendors +ffffffff82816000 R mfi_pci_ca +ffffffff82816030 r mfi_pci_devices +ffffffff82817000 R mfii_ca +ffffffff82817028 R mfii_switch +ffffffff82817050 R mfii_pd_switch +ffffffff82817078 R mfii_iop_thunderbolt +ffffffff82817088 R mfii_iop_25 +ffffffff82817098 R mfii_iop_35 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qlw_pci_ca +ffffffff82826030 r qlw_devices +ffffffff82826050 r isp_1040_risc_code +ffffffff8282b9f0 r isp_1080_risc_code +ffffffff82833470 r isp_12160_risc_code +ffffffff8283b000 R qla_pci_ca +ffffffff8283b030 r qla_devices +ffffffff8283c000 R qle_ca +ffffffff8283c028 R qle_switch +ffffffff8283c050 r qle_devices +ffffffff8283c070 r isp_2400_risc_code +ffffffff8286ba50 r isp_2500_risc_code +ffffffff8289e000 R mpi_pci_ca +ffffffff8289e030 r mpi_devices +ffffffff8289f000 R mpii_ca +ffffffff8289f028 R mpii_switch +ffffffff8289f050 r mpii_devices +ffffffff828a0000 R sili_pci_ca +ffffffff828a0030 r sili_devices +ffffffff828a1000 R aq_devices +ffffffff828a1040 R aq_products +ffffffff828a1100 R aq_fw1x_ops +ffffffff828a1120 R aq_fw2x_ops +ffffffff828a1140 R aq_ca +ffffffff828a2000 R de_ca +ffffffff828a2030 r tulip_srom_conninfo +ffffffff828a2120 r tulip_mii_phy_attrlist +ffffffff828a21e0 r tulip_21140_znyx_zx34x_boardsw +ffffffff828a2208 r tulip_21040_10baset_only_boardsw +ffffffff828a2230 r tulip_21040_boardsw +ffffffff828a2258 r tulip_2114x_isv_boardsw +ffffffff828a2280 r tulip_21140_smc9332_boardsw +ffffffff828a22a8 r tulip_21040_auibnc_only_boardsw +ffffffff828a22d0 r tulip_21140_cogent_em100_boardsw +ffffffff828a22f8 r tulip_21140_accton_boardsw +ffffffff828a2320 r tulip_21140_eb_boardsw +ffffffff828a2348 r tulip_21041_boardsw +ffffffff828a2370 r tulip_srom_mediums +ffffffff828a23c0 r tulip_read_macaddr.testpat +ffffffff828a23d0 r tulip_vendors +ffffffff828a2480 r tulip_media_to_ifmedia +ffffffff828a24e0 r tulip_chipdescs +ffffffff828a3000 R ep_pci_ca +ffffffff828a3030 R ep_pci_devices +ffffffff828a4000 R pcn_ca +ffffffff828a4028 R pcn_devices +ffffffff828a4030 r pcn_79c970_rcvfw +ffffffff828a4050 r pcn_79c970_xmtsp +ffffffff828a4070 r pcn_79c970_xmtfw +ffffffff828a4090 r pcn_79c971_rcvfw +ffffffff828a40b0 r pcn_79c971_xmtsp_sram +ffffffff828a40d0 r pcn_79c971_xmtsp +ffffffff828a40f0 r pcn_79c971_xmtfw +ffffffff828a4110 r pcn_variants +ffffffff828a5000 R siop_products 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pciide_vendors +ffffffff828a8140 R pciide_pci_ca +ffffffff828a8168 R pciide_jmb_ca +ffffffff828a8190 r piix_isp_dma +ffffffff828a8193 r piix_rtc_dma +ffffffff828a8196 r apollo_pio_set +ffffffff828a819b r cmd0643_9_data_tim_pio +ffffffff828a81a0 r cmd0643_9_data_tim_dma +ffffffff828a81a3 r cmd680_channel_map.init_val +ffffffff828a81b1 r cmd680_setup_channel.udma2_tbl +ffffffff828a81b8 r cmd680_setup_channel.dma_tbl +ffffffff828a81be r cmd680_setup_channel.pio_tbl +ffffffff828a81d0 r satalink_ba5_regmap +ffffffff828a8690 r sii3114_chansetup.channel_names +ffffffff828a86b0 r cy_pio_pulse +ffffffff828a86c0 r sis_udma133new_tim +ffffffff828a86e0 r sis_pio133new_tim +ffffffff828a86f4 r sis_dma133new_tim +ffffffff828a8700 r sis_udma66_tim +ffffffff828a8706 r sis_udma100new_tim +ffffffff828a870c r sis_udma133old_tim +ffffffff828a8713 r sis_pio_act +ffffffff828a8718 r sis_pio_rec +ffffffff828a871d r natsemi_pio_pulse +ffffffff828a8722 r natsemi_pio_recover +ffffffff828a8727 r natsemi_dma_pulse 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nforce_pio +ffffffff828a88c3 r ixp_mdma_timings +ffffffff828a88c6 r ixp_pio_timings +ffffffff828a9000 R ppb_ca +ffffffff828aa000 R cy_pci_ca +ffffffff828aa030 R cy_pci_devices +ffffffff828ab000 R rl_pci_ca +ffffffff828ab030 R rl_pci_devices +ffffffff828ac000 R re_pci_devices +ffffffff828ac030 R re_pci_ca +ffffffff828ad000 R vr_ca +ffffffff828ae000 R txp_ca +ffffffff828ae030 R txp_devices +ffffffff828af000 r cards +ffffffff828b0000 r format_params +ffffffff828b01a0 r pixfmt_table +ffffffff828b0320 r meteor_pixfmt_table +ffffffff828b1000 R bktr_ca +ffffffff828b1028 R bktr_hw_if +ffffffff828b2000 r tuners +ffffffff828b2170 r freqTable +ffffffff828b2260 r nabcst +ffffffff828b22a0 r irccable +ffffffff828b2310 r hrccable +ffffffff828b2380 r weurope +ffffffff828b2420 r jpnbcst +ffffffff828b2460 r jpncable +ffffffff828b24c0 r xussr +ffffffff828b2530 r australia +ffffffff828b2590 r france +ffffffff828b3000 R xl_pci_ca +ffffffff828b3030 R xl_pci_devices +ffffffff828b4000 R fxp_pci_ca +ffffffff828b4030 R fxp_pci_devices +ffffffff828b5000 R em_devices +ffffffff828b52e0 R em_ca +ffffffff828b5310 r em_counters +ffffffff828b6000 r em_igp_cable_length_table +ffffffff828b6100 r em_igp_2_cable_length_table +ffffffff828b7000 R ixgb_devices +ffffffff828b7010 R ixgb_ca +ffffffff828b8000 R ixgbe_devices +ffffffff828b80b8 R ix_ca +ffffffff828b80e0 r ix_counters +ffffffff828b83e0 r ix_rxq_kstats_tpl +ffffffff828b8458 r ix_txq_kstats_tpl +ffffffff828b9000 r ixgbe_mvals_base +ffffffff828b9060 r ixgbe_mvals_X540 +ffffffff828b90c0 r ixgbe_mvals_X550 +ffffffff828b9120 r ixgbe_mvals_X550EM_x +ffffffff828b9180 r ixgbe_mvals_X550EM_a +ffffffff828bc000 R ixl_ca +ffffffff828bc030 R ixl_port_counters +ffffffff828bc2c0 R ixl_vsi_counters +ffffffff828bc380 r ixl_devices +ffffffff828bc4c0 r ixl_710 +ffffffff828bc4e8 r ixl_722 +ffffffff828bc510 r ixl_pf_aq_regs +ffffffff828bc578 r ixl_710_decrepit +ffffffff828bc5a0 r ixl_phy_type_map +ffffffff828bc770 r ixl_speed_type_map +ffffffff828bc7b0 r ixl_hmc_pack_rxq +ffffffff828bc830 r ixl_hmc_pack_txq +ffffffff828bc8a0 r ixl_sfp_ops +ffffffff828bc8b8 r ixl_qsfp_ops +ffffffff828bd000 R xge_ca +ffffffff828bd028 R xge_devices +ffffffff828bd030 r xge_fix_mac +ffffffff828bd110 r xge_xena_dtx_cfg +ffffffff828bd170 r xge_herc_dtx_cfg +ffffffff828be000 R thtc_ca +ffffffff828be028 R tht_ca +ffffffff828be050 r thtc_devices +ffffffff828be068 r tht_link_state.interval +ffffffff828bf000 R myx_ca +ffffffff828bf028 R myx_devices +ffffffff828c0000 R oce_ca +ffffffff828c0030 R oce_devices +ffffffff828c1000 R dc_pci_ca +ffffffff828c2000 R epic_pci_ca +ffffffff828c2028 R epic_pci_devices +ffffffff828c3000 R ti_pci_ca +ffffffff828c3030 R ti_devices +ffffffff828c4000 R ne_pci_ca +ffffffff828c4030 R ne_pci_prod +ffffffff828c5000 R gem_pci_ca +ffffffff828c5030 R gem_pci_devices +ffffffff828c5050 r gem_promhdr +ffffffff828c5052 r gem_promdat +ffffffff828c505a r gem_promdat2 +ffffffff828c6000 R cas_ca +ffffffff828c6028 R cas_pci_devices +ffffffff828c6030 r cas_promhdr +ffffffff828c6032 r cas_promdat_sun +ffffffff828c603a r cas_promdat_ns +ffffffff828c6042 r cas_promdat2 +ffffffff828c7000 R sf_pci_ca +ffffffff828c7028 R sf_pci_products +ffffffff828c8000 R sis_ca +ffffffff828c8028 R sis_devices +ffffffff828c9000 R se_devices +ffffffff828c9008 R se_ca +ffffffff828ca000 R uhci_pci_ca +ffffffff828cb000 R ohci_pci_ca +ffffffff828cc000 R ehci_pci_ca +ffffffff828cd000 R xhci_pci_ca +ffffffff828ce000 R cbb_pci_ca +ffffffff828ce028 r pccbb_pcmcia_do_io_map.pcic_iowidth +ffffffff828cf000 R skc_devices +ffffffff828cf030 R skc_ca +ffffffff828cf058 R sk_ca +ffffffff828d0000 R mskc_devices +ffffffff828d00a8 R mskc_ca +ffffffff828d00d0 R msk_ca +ffffffff828d0100 r msk_mib +ffffffff828d1000 R puc_pci_ca +ffffffff828d2000 R puc_devs +ffffffff828d7000 R com_puc_ca +ffffffff828d7030 r puc_port_types +ffffffff828d8000 R lpt_puc_ca +ffffffff828d9000 R wi_pci_ca +ffffffff828d9030 r wi_pci_products +ffffffff828da000 R an_pci_ca +ffffffff828da030 R an_pci_devices +ffffffff828db000 R iwi_devices +ffffffff828db010 R iwi_ca +ffffffff828dc000 R wpi_ca +ffffffff828dc028 r wpi_devices +ffffffff828dc030 r wpi_rates +ffffffff828dc050 r wpi_rf_gain_5ghz +ffffffff828dc0a0 r wpi_dsp_gain_5ghz +ffffffff828dc0f0 r wpi_rf_gain_2ghz +ffffffff828dc140 r wpi_dsp_gain_2ghz +ffffffff828dc190 r wpi_pmgt +ffffffff828dc310 r wpi_bands +ffffffff828dd000 R iwn_mcs2ridx +ffffffff828dd020 R iwn_ca +ffffffff828dd050 r iwn_devices +ffffffff828dd0e8 r iwn4965_sensitivity_limits +ffffffff828dd124 r iwn5000_sensitivity_limits +ffffffff828dd160 r iwn5150_sensitivity_limits +ffffffff828dd19c r iwn1000_sensitivity_limits +ffffffff828dd1d8 r iwn6000_sensitivity_limits +ffffffff828dd214 r iwn2000_sensitivity_limits +ffffffff828dd250 r iwn_fw_errmsg +ffffffff828dd340 r iwn4965_set_txpower.tdiv +ffffffff828dd360 r iwn4965_rf_gain_5ghz +ffffffff828dd3d0 r iwn4965_dsp_gain_5ghz +ffffffff828dd440 r iwn4965_dsp_gain_2ghz +ffffffff828dd4b0 r iwn_pmgt +ffffffff828dd6f0 r iwn4965_post_alive.qid2fifo +ffffffff828dd700 r iwn_bands +ffffffff828dd770 r iwn_rates +ffffffff828dd820 r iwn4965_rf_gain_2ghz +ffffffff828de000 R iwm_nvm_channels +ffffffff828de030 R iwm_nvm_channels_8000 +ffffffff828de070 R iwm_rates +ffffffff828de0d0 R iwm_ht_mcs2ridx +ffffffff828de110 R iwm_tid_to_ac +ffffffff828de118 R iwm_ac_to_tx_fifo +ffffffff828de120 R iwm_nvm_to_read +ffffffff828de144 r iwm_set_hw_address_8000.reserved_mac +ffffffff828de180 r iwm_sf_full_timeout +ffffffff828de1b0 r iwm_sf_full_timeout_def +ffffffff828de1e0 r advanced_lookup +ffffffff828de320 r iwm_devices +ffffffff828de360 R iwm_ca +ffffffff828df000 R iwx_9560_quz_a0_jf_b0_cfg +ffffffff828df020 R iwx_9560_qu_c0_jf_b0_cfg +ffffffff828df040 R iwx_qu_b0_hr1_b0 +ffffffff828df060 R iwx_qu_b0_hr_b0 +ffffffff828df080 R iwx_ax201_cfg_qu_hr +ffffffff828df0a0 R iwx_qu_c0_hr1_b0 +ffffffff828df0c0 R iwx_qu_c0_hr_b0 +ffffffff828df0e0 R iwx_ax201_cfg_qu_c0_hr_b0 +ffffffff828df100 R iwx_quz_a0_hr1_b0 +ffffffff828df120 R iwx_ax201_cfg_quz_hr +ffffffff828df140 R iwx_cfg_so_a0_hr_b0 +ffffffff828df160 R iwx_cfg_quz_a0_hr_b0 +ffffffff828df180 R iwx_2ax_cfg_so_gf_a0 +ffffffff828df1a0 R iwx_2ax_cfg_so_gf_a0_long +ffffffff828df1c0 R iwx_2ax_cfg_so_gf4_a0 +ffffffff828df1e0 R iwx_2ax_cfg_so_gf4_a0_long +ffffffff828df200 R iwx_2ax_cfg_ty_gf_a0 +ffffffff828df220 R iwx_2ax_cfg_so_jf_b0 +ffffffff828df240 R iwx_nvm_channels_8000 +ffffffff828df280 R iwx_rates +ffffffff828df2e0 R iwx_mcs2ridx +ffffffff828df320 R iwx_tid_to_ac +ffffffff828df328 R iwx_ac_to_tx_fifo +ffffffff828df330 r iwx_nvm_channels_uhb +ffffffff828df39e r iwx_is_valid_mac_addr.reserved_mac +ffffffff828df3b0 r iwx_sf_full_timeout +ffffffff828df3e0 r iwx_sf_full_timeout_def +ffffffff828df410 r advanced_lookup +ffffffff828df550 r iwx_devices +ffffffff828df590 r iwx_dev_info_table +ffffffff828dfde8 R iwx_ca +ffffffff828e0000 R cmpci_ca +ffffffff828e0028 R cmpci_hw_if +ffffffff828e00e0 r cmpci_rate_table +ffffffff828e0120 R cmpci_devices +ffffffff828e0130 r cmpci_query_devinfo.mixer_port_names +ffffffff828e0160 r cmpci_query_devinfo.mixer_classes +ffffffff828e1000 R iha_pci_ca +ffffffff828e1028 R iha_switch +ffffffff828e2000 R pcscp_ca +ffffffff828e3000 R bge_ca +ffffffff828e3030 R bge_devices +ffffffff828e31b0 r bge_revisions +ffffffff828e3610 r bge_majorrevs +ffffffff828e4000 R bnx_devices +ffffffff828e4020 R bnx_ca +ffffffff828e5000 R vge_ca +ffffffff828e5028 R vge_devices +ffffffff828e6000 R stge_ca +ffffffff828e6028 R stge_mii_bitbang_ops +ffffffff828e6050 R stge_devices +ffffffff828e7000 R nfe_ca +ffffffff828e7030 R nfe_devices +ffffffff828e8000 R et_devices +ffffffff828e8008 R et_ca +ffffffff828e9000 R jme_devices +ffffffff828e9008 R jme_ca +ffffffff828ea000 R age_devices +ffffffff828ea008 R age_ca +ffffffff828eb000 R alc_devices +ffffffff828eb038 R alc_ca +ffffffff828ec000 R ale_devices +ffffffff828ec008 R ale_ca +ffffffff828ed000 R amdpm_ca +ffffffff828ed030 R amdpm_ids +ffffffff828ee000 R bce_ca +ffffffff828ee028 R bce_devices +ffffffff828ef000 R ath_pci_ca +ffffffff828f0000 R athn_pci_ca +ffffffff828f0030 r athn_pci_devices +ffffffff828f1000 R atw_pci_ca +ffffffff828f1028 R atw_pci_devices +ffffffff828f2000 R rtw_pci_ca +ffffffff828f2030 R rtw_pci_products +ffffffff828f3000 R rtwn_pci_ca +ffffffff828f3030 r rtwn_pci_devices +ffffffff828f3040 r rtl8188eu_mac +ffffffff828f31b0 r rtl8192cu_mac +ffffffff828f3310 r rtl8192ce_mac +ffffffff828f3458 r rtl8188eu_bb_prog +ffffffff828f3480 r rtl8723a_bb_prog +ffffffff828f34a8 r rtl8192ce_bb_prog_1t +ffffffff828f34d0 r rtl8192ce_bb_prog_2t +ffffffff828f3500 r rtl8188eu_bb_regs +ffffffff828f3680 r rtl8188eu_bb_vals +ffffffff828f3980 r rtl8188eu_agc_vals +ffffffff828f3b80 r rtl8723a_bb_regs +ffffffff828f3d00 r rtl8723a_bb_vals +ffffffff828f3ff0 r rtl8192ce_agc_vals +ffffffff828f4270 r rtl8192ce_bb_regs +ffffffff828f43f0 r rtl8192ce_bb_vals_1t +ffffffff828f46e0 r rtl8192ce_bb_vals_2t +ffffffff828f5000 R ral_pci_ca +ffffffff828f5030 R ral_pci_devices +ffffffff828f6000 R acx_pci_ca +ffffffff828f6028 R acx_pci_devices +ffffffff828f7000 R pgt_pci_ca +ffffffff828f7028 R pgt_pci_devices +ffffffff828f8000 R malo_pci_ca +ffffffff828f8028 R malo_pci_devices +ffffffff828f9000 R bwi_pci_ca +ffffffff828f9030 R bwi_pci_devices +ffffffff828fa000 R piixpm_ca +ffffffff828fa030 R piixpm_ids +ffffffff828fb000 R vic_ca +ffffffff828fb028 R vic_devices +ffffffff828fc000 R vmx_devices +ffffffff828fc008 R vmx_ca +ffffffff828fc030 r vmx_tx_kstat_tpl +ffffffff828fc0d0 r vmx_kstat_rate +ffffffff828fc0e0 r vmx_rx_kstat_tpl +ffffffff828fd000 R vmwpvs_ca +ffffffff828fd028 R vmwpvs_switch +ffffffff828fe000 R lii_ca +ffffffff828fe028 R lii_devices +ffffffff828ff000 R ichiic_ca +ffffffff828ff030 R ichiic_ids +ffffffff82900000 R viapm_ca +ffffffff82900030 R viapm_ids +ffffffff82900070 r val_to_temp +ffffffff82900870 r val_to_uV.mult +ffffffff82901000 R amdiic_ca +ffffffff82901028 R amdiic_ids +ffffffff82902000 R nviic_ca +ffffffff82902030 R nviic_ids +ffffffff82903000 R sdhc_pci_ca +ffffffff82904000 R kate_ca +ffffffff82904030 r kate_proc +ffffffff82905000 R km_ca +ffffffff82905030 r km_devices +ffffffff82906000 R ksmn_ca +ffffffff82906030 r ksmn_devices +ffffffff82907000 R itherm_devices +ffffffff82907008 R itherm_ca +ffffffff82908000 R pchtemp_ca +ffffffff82908030 R pchtemp_devices +ffffffff82909000 R rtsx_pci_ca +ffffffff8290a000 R xspd_ca +ffffffff8290a028 R xspd_devices +ffffffff8290b000 R virtio_pci_ca +ffffffff8290c000 R dwiic_pci_ca +ffffffff8290c030 R dwiic_pci_ids +ffffffff8290d000 R bwfm_pci_ca +ffffffff8290d030 r bwfm_pci_devices +ffffffff8290e000 R ccp_pci_ca +ffffffff8290e030 r ccp_pci_devices +ffffffff8290f000 R bnxt_devices +ffffffff8290f040 R bnxt_ca +ffffffff82910000 R mcx_ca +ffffffff82910030 r mcx_devices +ffffffff82910060 r mcx_rss_config +ffffffff829100d0 r mcx_eth_cap_map +ffffffff829102d0 r mcx_kstat_ppcnt_ieee8023 +ffffffff829102e8 r mcx_kstat_ppcnt_rfc2863 +ffffffff82910300 r mcx_kstat_ppcnt_rfc2819 +ffffffff82910318 r mcx_kstat_ppcnt_rfc3635 +ffffffff82910330 r mcx_ppcnt_ieee8023_tpl +ffffffff829104b0 r mcx_ppcnt_rfc2863_tpl +ffffffff829105c0 r mcx_ppcnt_rfc2819_tpl +ffffffff82910770 r mcx_ppcnt_rfc3635_tpl +ffffffff829108b0 r mcx_kstat_mtmp_tpl +ffffffff82910950 r mcx_kstat_mtmp_rate +ffffffff82910960 r mcx_queue_kstat_tpl +ffffffff82911000 R iavf_ca +ffffffff82911030 r iavf_devices +ffffffff82911040 r iavf_aq_regs +ffffffff829110b0 r iavf_link_speeds +ffffffff82912000 R rge_ca +ffffffff82912028 R rge_devices +ffffffff82912030 r rtl8125_mac_cfg2_ephy +ffffffff82912090 r rge_phy_config_mac_cfg3.mac_cfg3_a438_value +ffffffff829120b0 r rge_phy_config_mac_cfg3.mac_cfg3_b88e_value +ffffffff82912110 r rge_phy_config_mac_cfg4.mac_cfg4_b87c_value +ffffffff82912170 r rtl8125_mac_cfg4_ephy +ffffffff829121e0 r rtl8125_mac_cfg2_mcu +ffffffff82912e80 r rtl8125_mac_cfg3_mcu +ffffffff82913720 r rtl8125_mac_cfg4_mcu +ffffffff82915d10 r rtl8125_mac_cfg5_mcu +ffffffff82916c10 r rtl8125_mac_bps +ffffffff82916f80 r rtl8125b_mac_bps +ffffffff82917120 r rge_kstats_tpl +ffffffff82918000 R igc_devices +ffffffff82918040 R igc_ca +ffffffff82919000 R ngbe_devices +ffffffff82919008 R ngbe_ca +ffffffff8291a000 R com_pci_ca +ffffffff8291a030 R com_pci_ids +ffffffff8291b000 r agp_attach.agp_max +ffffffff8291b048 R agp_ca +ffffffff8291c000 R intagp_ca +ffffffff8291d000 r drm_plane_create_rotation_property.props +ffffffff8291e000 r drm_bridge_priv_state_funcs +ffffffff82920000 r color_encoding_name +ffffffff82920020 r color_range_name +ffffffff82921000 r drm_subpixel_enum_list +ffffffff82921060 r drm_dpms_enum_list +ffffffff829210a0 r drm_dvi_i_select_enum_list +ffffffff829210d0 r drm_dvi_i_subconnector_enum_list +ffffffff82921100 r drm_tv_select_enum_list +ffffffff82921150 r drm_tv_subconnector_enum_list +ffffffff829211a0 r drm_dp_subconnector_enum_list +ffffffff82921210 r drm_link_status_enum_list +ffffffff82921230 r drm_scaling_mode_enum_list +ffffffff82921270 r drm_aspect_ratio_enum_list +ffffffff829212a0 r hdmi_colorspaces +ffffffff82921370 r dp_colorspaces +ffffffff82921450 r drm_content_type_enum_list +ffffffff829214a0 r drm_panel_orientation_enum_list +ffffffff829214e0 r privacy_screen_enum +ffffffff82922000 r drm_crtc_fence_ops +ffffffff82923000 r drm_dmt_modes +ffffffff82925940 r edid_cea_modes_1 +ffffffff829294d0 r edid_cea_modes_193 +ffffffff8292a180 r edid_quirk_list +ffffffff8292a350 r edid_4k_modes +ffffffff8292a5b0 r edid_est_modes +ffffffff8292adb0 r est3_modes +ffffffff8292af10 r stereo_mandatory_modes +ffffffff8292af90 r extra_modes +ffffffff8292b000 r drm_encoder_enum_list +ffffffff8292c000 r drm_fbdev_client_funcs +ffffffff8292c020 r drm_fb_helper_generic_funcs +ffffffff8292c028 r drm_fbdev_fb_ops +ffffffff8292d000 r drm_fb_xrgb8888_to_rgb332.dst_pixsize +ffffffff8292d004 r drm_fb_xrgb8888_to_rgb565.dst_pixsize +ffffffff8292d008 r drm_fb_xrgb8888_to_rgb888.dst_pixsize +ffffffff8292d00c r drm_fb_xrgb8888_to_xrgb2101010.dst_pixsize +ffffffff8292d010 r drm_fb_xrgb8888_to_gray8.dst_pixsize +ffffffff8292d014 r drm_fb_rgb888_to_xrgb8888.dst_pixsize +ffffffff8292d018 r drm_fb_rgb565_to_xrgb8888.dst_pixsize +ffffffff8292e000 r __drm_format_info.formats +ffffffff8292f000 R drm_pgops +ffffffff82930000 r drm_ioctls +ffffffff82932000 r dma_fence_stub_ops +ffffffff82932038 R dma_fence_array_ops +ffffffff82932070 R dma_fence_chain_ops +ffffffff829320a8 R dmabufops +ffffffff829320e0 R syncfileops +ffffffff82933000 r drm_plane_type_enum_list +ffffffff82934000 r drm_mode_status_names +ffffffff82935000 r primary_plane_funcs +ffffffff82935068 r safe_modeset_formats +ffffffff82936000 r orientation_data +ffffffff82939468 r lcd800x1280_rightside_up +ffffffff82939480 r lcd720x1280_rightside_up +ffffffff82939498 r lcd800x1280_leftside_up +ffffffff829394b0 r lcd1080x1920_leftside_up +ffffffff829394c8 r lcd1200x1920_rightside_up +ffffffff829394e0 r gpd_micropc +ffffffff829394f8 r gpd_pocket +ffffffff82939510 r gpd_pocket2 +ffffffff82939528 r gpd_win +ffffffff82939540 r gpd_win2 +ffffffff82939558 r itworks_tw891 +ffffffff82939570 r lcd1600x2560_rightside_up +ffffffff82939588 r onegx1_pro +ffffffff829395a0 r lcd1600x2560_leftside_up +ffffffff829395b8 r lcd1280x1920_rightside_up +ffffffff829395d0 r .compoundliteral +ffffffff829395e0 r .compoundliteral.5 +ffffffff82939608 r .compoundliteral.9 +ffffffff82939628 r .compoundliteral.17 +ffffffff82939668 r .compoundliteral.21 +ffffffff82939688 r .compoundliteral.23 +ffffffff82939698 r .compoundliteral.25 +ffffffff8293a000 r drm_gem_prime_dmabuf_ops +ffffffff8293c000 r is_hdmi_adaptor.dp_dual_mode_hdmi_id +ffffffff8293d000 r drm_dp_phy_name.phy_names +ffffffff8293d048 r drm_dp_i2c_algo +ffffffff8293d058 r drm_dp_i2c_lock_ops +ffffffff8293d070 r dp_aux_bl_ops +ffffffff8293d090 r dpcd_quirk_list +ffffffff8293d320 r drm_dp_psr_setup_time.psr_setup_time_us +ffffffff8293e000 R drm_dp_mst_topology_state_funcs +ffffffff8293e020 r drm_dp_mst_req_type_str.req_type_str +ffffffff8293e1f0 r drm_dp_mst_sideband_tx_state_str.sideband_reason_str +ffffffff8293e220 r drm_dp_mst_nak_reason_str.nak_reason_str +ffffffff8293e278 r drm_dp_mst_i2c_algo +ffffffff8293f000 r hdmi_colorimetry_val +ffffffff82940000 r ttm_bo_init_reserved.sys_mem +ffffffff82941000 r ttm_bo_pipeline_gutting.sys_mem +ffffffff82942018 R ttm_bo_vm_ops +ffffffff82943000 r ttm_range_manager_func +ffffffff82944018 r ttm_kmap_iter_io_ops +ffffffff82944030 r ttm_kmap_iter_linear_io_ops +ffffffff82945000 r ttm_sys_manager_func +ffffffff82946000 r ttm_kmap_iter_tt_ops +ffffffff82947000 r drm_sched_fence_ops_scheduled +ffffffff82947038 r drm_sched_fence_ops_finished +ffffffff82948000 R ch7017_ops +ffffffff82949000 R ch7xxx_ops +ffffffff82949060 r ch7xxx_ids +ffffffff8294a000 R ivch_ops +ffffffff8294a060 r backup_addresses +ffffffff8294b000 R ns2501_ops +ffffffff8294b060 r mode_agnostic_values +ffffffff8294b0e0 r ns2501_modes +ffffffff8294c000 R sil164_ops +ffffffff8294d000 R tfp410_ops +ffffffff8294e000 r chv_dpll +ffffffff8294e050 r vlv_dpll +ffffffff8294e0a0 r g4x_dpll +ffffffff8294e0f0 r pch_dpll +ffffffff8294e138 r intel_dp_enc_funcs +ffffffff8294f000 r intel_hdmi_enc_funcs +ffffffff82950000 r vlv_primary_formats +ffffffff82950030 r ivb_primary_formats +ffffffff82950050 r i965_primary_formats +ffffffff82950070 r i8xx_primary_formats +ffffffff82950080 r i965_plane_funcs +ffffffff829500e8 r i8xx_plane_funcs +ffffffff82951000 r gen11_dsi_encoder_funcs +ffffffff82951020 r gen11_dsi_connector_funcs +ffffffff82951098 r gen11_dsi_connector_helper_funcs +ffffffff829510e8 r gen11_dsi_host_ops +ffffffff82952000 r intel_plane_helper_funcs +ffffffff82953000 r g4x_audio_funcs +ffffffff82953010 r ilk_audio_funcs +ffffffff82953020 r hsw_audio_funcs +ffffffff82953030 r hdmi_audio_clock +ffffffff829530a0 r dp_aud_n_m +ffffffff82953250 r hdmi_aud_ncts_36bpp +ffffffff82953330 r hdmi_aud_ncts_30bpp +ffffffff82953410 r hdmi_aud_ncts_24bpp +ffffffff82954000 r intel_backlight_device_ops +ffffffff82954018 r bxt_pwm_funcs +ffffffff82954048 r cnp_pwm_funcs +ffffffff82954078 r lpt_pwm_funcs +ffffffff829540a8 r spt_pwm_funcs +ffffffff829540d8 r pch_pwm_funcs +ffffffff82954108 r ext_pwm_funcs +ffffffff82954138 r vlv_pwm_funcs +ffffffff82954168 r i965_pwm_funcs +ffffffff82954198 r i9xx_pwm_funcs +ffffffff829541c8 r pwm_bl_funcs +ffffffff82955000 r bdb_blocks +ffffffff82955160 r translate_iboost.mapping +ffffffff82955163 r adlp_ddc_pin_map +ffffffff8295516a r adls_ddc_pin_map +ffffffff82955170 r rkl_pch_tgp_ddc_pin_map +ffffffff82955175 r icp_ddc_pin_map +ffffffff8295517f r cnp_ddc_pin_map +ffffffff82956000 r mtl_sa_info +ffffffff82956006 r adlp_sa_info +ffffffff8295600c r adls_sa_info +ffffffff82956012 r rkl_sa_info +ffffffff82956018 r tgl_sa_info +ffffffff82956020 r intel_bw_funcs +ffffffff82957000 r intel_cdclk_funcs +ffffffff82957010 r dg2_cdclk_table +ffffffff829570c0 r adlp_a_step_cdclk_table +ffffffff82957140 r adlp_cdclk_table +ffffffff82957200 r rkl_cdclk_table +ffffffff829572f0 r icl_cdclk_table +ffffffff829573e0 r glk_cdclk_table +ffffffff82957410 r bxt_cdclk_table +ffffffff82957458 r tgl_cdclk_funcs +ffffffff82957478 r ehl_cdclk_funcs +ffffffff82957498 r icl_cdclk_funcs +ffffffff829574b8 r bxt_cdclk_funcs +ffffffff829574d8 r skl_cdclk_funcs +ffffffff829574f8 r bdw_cdclk_funcs +ffffffff82957518 r hsw_cdclk_funcs +ffffffff82957538 r chv_cdclk_funcs +ffffffff82957558 r vlv_cdclk_funcs +ffffffff82957578 r fixed_400mhz_cdclk_funcs +ffffffff82957598 r ilk_cdclk_funcs +ffffffff829575b8 r gm45_cdclk_funcs +ffffffff829575d8 r g33_cdclk_funcs +ffffffff829575f8 r g33_get_cdclk.div_3200 +ffffffff829575fe r g33_get_cdclk.div_4000 +ffffffff82957604 r g33_get_cdclk.div_4800 +ffffffff8295760a r g33_get_cdclk.div_5333 +ffffffff82957610 r i965gm_cdclk_funcs +ffffffff82957630 r i965gm_get_cdclk.div_3200 +ffffffff82957633 r i965gm_get_cdclk.div_4000 +ffffffff82957636 r i965gm_get_cdclk.div_5333 +ffffffff82957640 r pnv_cdclk_funcs +ffffffff82957660 r i945gm_cdclk_funcs +ffffffff82957680 r i915gm_cdclk_funcs +ffffffff829576a0 r i915g_cdclk_funcs +ffffffff829576c0 r i865g_cdclk_funcs +ffffffff829576e0 r i85x_cdclk_funcs +ffffffff82957700 r i845g_cdclk_funcs +ffffffff82957720 r i830_cdclk_funcs +ffffffff82958000 r chv_color_funcs +ffffffff82958028 r i965_color_funcs +ffffffff82958050 r i9xx_color_funcs +ffffffff82958078 r icl_color_funcs +ffffffff829580a0 r glk_color_funcs +ffffffff829580c8 r skl_color_funcs +ffffffff829580f0 r bdw_color_funcs +ffffffff82958118 r hsw_color_funcs +ffffffff82958140 r ivb_color_funcs +ffffffff82958168 r ilk_color_funcs +ffffffff82958190 r ilk_csc_off_zero +ffffffff829581a0 r ilk_csc_coeff_rgb_to_ycbcr +ffffffff829581b2 r ilk_csc_postoff_rgb_to_ycbcr +ffffffff829581c0 r ilk_csc_coeff_limited_range +ffffffff829581d2 r ilk_csc_postoff_limited_range +ffffffff829581e0 r ilk_csc_coeff_identity +ffffffff82959000 r icl_procmon_values +ffffffff8295a000 r force_audio_names +ffffffff8295a040 r broadcast_rgb_names +ffffffff8295b000 r intel_crt_connector_funcs +ffffffff8295b078 r intel_crt_enc_funcs +ffffffff8295b098 r intel_crt_connector_helper_funcs +ffffffff8295b0f0 r intel_spurious_crt_detect +ffffffff8295c000 r g4x_crtc_funcs +ffffffff8295c0c0 r i965_crtc_funcs +ffffffff8295c180 r i915gm_crtc_funcs +ffffffff8295c240 r i915_crtc_funcs +ffffffff8295c300 r i8xx_crtc_funcs +ffffffff8295c3c0 r bdw_crtc_funcs +ffffffff8295c480 r ilk_crtc_funcs +ffffffff8295d000 r output_type_str +ffffffff8295d060 r output_format_str +ffffffff8295e000 r intel_cursor_plane_funcs +ffffffff8295e068 r intel_cursor_formats +ffffffff8295f000 r intel_ddi_funcs +ffffffff8295f020 r index_to_dp_signal_levels +ffffffff8295f030 r gen9_chicken_trans_reg_by_port.trans +ffffffff82960000 r tgl_combo_phy_trans_edp_hbr2_hobl +ffffffff82960010 r _tgl_combo_phy_trans_edp_hbr2_hobl +ffffffff82960080 r dg2_snps_trans_uhbr +ffffffff82960090 r dg2_snps_trans +ffffffff829600a0 r _dg2_snps_trans_uhbr +ffffffff82960160 r _dg2_snps_trans +ffffffff829601d8 r icl_combo_phy_trans_hdmi +ffffffff829601f0 r _icl_combo_phy_trans_hdmi +ffffffff82960248 r adlp_combo_phy_trans_edp_hbr3 +ffffffff82960258 r adlp_combo_phy_trans_edp_up_to_hbr2 +ffffffff82960270 r _adlp_combo_phy_trans_dp_hbr2_edp_hbr3 +ffffffff829602f0 r _adlp_combo_phy_trans_edp_hbr2 +ffffffff82960368 r adlp_combo_phy_trans_dp_hbr2_hbr3 +ffffffff82960378 r adlp_combo_phy_trans_dp_hbr +ffffffff82960390 r _adlp_combo_phy_trans_dp_hbr2_hbr3 +ffffffff82960410 r _adlp_combo_phy_trans_dp_hbr +ffffffff82960488 r tgl_dkl_phy_trans_hdmi +ffffffff829604a0 r _tgl_dkl_phy_trans_hdmi +ffffffff82960518 r adlp_dkl_phy_trans_dp_hbr2_hbr3 +ffffffff82960528 r adlp_dkl_phy_trans_dp_hbr +ffffffff82960540 r _adlp_dkl_phy_trans_dp_hbr2_hbr3 +ffffffff829605c0 r _adlp_dkl_phy_trans_dp_hbr +ffffffff82960638 r adls_combo_phy_trans_edp_hbr3 +ffffffff82960648 r adls_combo_phy_trans_edp_hbr2 +ffffffff82960660 r _adls_combo_phy_trans_edp_hbr3 +ffffffff829606e0 r _adls_combo_phy_trans_edp_hbr2 +ffffffff82960758 r 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bdw_gt1_info +ffffffff829c17f8 r bdw_gt2_info +ffffffff829c18b8 r bdw_gt3_info +ffffffff829c1978 r bdw_rsvd_info +ffffffff829c1a38 r chv_info +ffffffff829c1af8 r skl_gt1_info +ffffffff829c1bb8 r skl_gt2_info +ffffffff829c1c78 r skl_gt3_info +ffffffff829c1d38 r skl_gt4_info +ffffffff829c1df8 r bxt_info +ffffffff829c1eb8 r glk_info +ffffffff829c1f78 r kbl_gt1_info +ffffffff829c2038 r kbl_gt2_info +ffffffff829c20f8 r kbl_gt3_info +ffffffff829c21b8 r cfl_gt1_info +ffffffff829c2278 r cfl_gt2_info +ffffffff829c2338 r cfl_gt3_info +ffffffff829c23f8 r cml_gt1_info +ffffffff829c24b8 r cml_gt2_info +ffffffff829c2578 r icl_info +ffffffff829c2638 r ehl_info +ffffffff829c26f8 r jsl_info +ffffffff829c27b8 r tgl_info +ffffffff829c2878 r rkl_info +ffffffff829c2938 r adl_s_info +ffffffff829c29f8 r adl_p_info +ffffffff829c2ab8 r dg1_info +ffffffff829c2b78 r dg2_info +ffffffff829c2c38 r ats_m_info +ffffffff829c2d00 r xelpmp_extra_gt +ffffffff829c2d40 r mtl_info +ffffffff829c3000 r oa_formats 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bxt_clock_gating_funcs +ffffffff829ce058 r glk_clock_gating_funcs +ffffffff829ce060 r bdw_clock_gating_funcs +ffffffff829ce068 r chv_clock_gating_funcs +ffffffff829ce070 r hsw_clock_gating_funcs +ffffffff829ce078 r ivb_clock_gating_funcs +ffffffff829ce080 r vlv_clock_gating_funcs +ffffffff829ce088 r gen6_clock_gating_funcs +ffffffff829ce090 r ilk_clock_gating_funcs +ffffffff829ce098 r g4x_clock_gating_funcs +ffffffff829ce0a0 r i965gm_clock_gating_funcs +ffffffff829ce0a8 r i965g_clock_gating_funcs +ffffffff829ce0b0 r gen3_clock_gating_funcs +ffffffff829ce0b8 r i85x_clock_gating_funcs +ffffffff829ce0c0 r i830_clock_gating_funcs +ffffffff829ce0c8 r nop_clock_gating_funcs +ffffffff829ce0d0 r ilk_wm_funcs +ffffffff829ce108 r nop_funcs +ffffffff829ce140 r vlv_wm_funcs +ffffffff829ce178 r g4x_wm_funcs +ffffffff829ce1b0 r pnv_wm_funcs +ffffffff829ce1e8 r i965_wm_funcs +ffffffff829ce220 r i9xx_wm_funcs +ffffffff829ce258 r i845_wm_funcs +ffffffff829ce290 r cxsr_latency_table +ffffffff829cf000 r dg2_g10_revid_step_tbl +ffffffff829cf030 r dg2_g11_revid_step_tbl +ffffffff829cf050 r xehpsdv_revids +ffffffff829cf080 r adlp_revids +ffffffff829cf0c0 r adls_rpls_revids +ffffffff829cf100 r adls_revids +ffffffff829cf140 r rkl_revids +ffffffff829cf160 r bxt_revids +ffffffff829cf1a0 r skl_revids +ffffffff829cf1d0 r pvc_bd_subids +ffffffff829cf1f0 r pvc_ct_subids +ffffffff829d1000 r forcewake_domain_names +ffffffff829d1080 r __pvc_fw_ranges +ffffffff829d1200 r pvc_shadowed_regs +ffffffff829d1320 r __dg2_fw_ranges +ffffffff829d15f0 r dg2_shadowed_regs +ffffffff829d1710 r __xehp_fw_ranges +ffffffff829d19e0 r gen12_shadowed_regs +ffffffff829d1b00 r __gen12_fw_ranges +ffffffff829d1d10 r __gen11_fw_ranges +ffffffff829d1ec0 r gen11_shadowed_regs +ffffffff829d1f80 r __gen9_fw_ranges +ffffffff829d2100 r gen8_shadowed_regs +ffffffff829d2130 r __chv_fw_ranges +ffffffff829d21f0 r __gen6_fw_ranges +ffffffff829d2200 r __vlv_fw_ranges +ffffffff829d2258 r uncore_get_fallback +ffffffff829d2260 r uncore_get_normal +ffffffff829d2268 r uncore_get_thread_status +ffffffff829d3000 r atom_op_names +ffffffff829d33e0 r opcode_table +ffffffff829d3b90 r atom_dst_to_src +ffffffff829d3c10 r atom_io_names +ffffffff829d3c40 r atom_table_names +ffffffff829d3e90 r atom_iio_len +ffffffff829d4000 r vga_control_regs +ffffffff829d4018 r atombios_helper_funcs +ffffffff829d5000 r voltage_names +ffffffff829d5020 r pre_emph_names +ffffffff829d6000 r radeon_atom_backlight_ops +ffffffff829d6018 r radeon_atom_enc_funcs +ffffffff829d6038 r radeon_atom_dig_helper_funcs +ffffffff829d60a0 r radeon_atom_dac_helper_funcs +ffffffff829d6108 r radeon_atom_ext_helper_funcs +ffffffff829d7000 r caicos_cgcg_cgls_default +ffffffff829d7240 r barts_mgcg_default +ffffffff829d7900 r turks_mgcg_default +ffffffff829d7d80 r caicos_mgcg_default +ffffffff829d8110 r turks_sysls_default +ffffffff829d81d0 r caicos_sysls_default +ffffffff829d8280 r caicos_cgcg_cgls_enable +ffffffff829d84d0 r caicos_cgcg_cgls_disable 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SECT_CTRLCONST_defs +ffffffff829e44d0 r SECT_CONTEXT_def_2 +ffffffff829e44f0 r SECT_CONTEXT_def_4 +ffffffff829e4680 r SECT_CONTEXT_def_5 +ffffffff829e46a0 r SECT_CONTEXT_def_6 +ffffffff829e4780 r SECT_CONTEXT_def_1 +ffffffff829e4f20 r SECT_CONTEXT_def_3 +ffffffff829e5000 r SECT_CONTEXT_def_7 +ffffffff829e5488 r SECT_CLEAR_def_1 +ffffffff829e5494 r SECT_CTRLCONST_def_1 +ffffffff829e54a0 r evergreen_default_state +ffffffff829e6000 r cayman_reg_safe_bm +ffffffff829e8000 r evergreen_reg_safe_bm +ffffffff829eb000 r evergreen_hdmi_write_sad_regs.eld_reg_to_type +ffffffff829ec000 r didt_config_kv +ffffffff829ed000 r barts_io_mc_regs +ffffffff829ed0f0 r turks_io_mc_regs +ffffffff829ed1e0 r caicos_io_mc_regs +ffffffff829ed2d0 r cayman_io_mc_regs +ffffffff829ed3c0 r cayman_golden_registers +ffffffff829ed580 r cayman_golden_registers2 +ffffffff829ed5d0 r dvst_golden_registers +ffffffff829ed860 r dvst_golden_registers2 +ffffffff829ed890 r scrapper_golden_registers +ffffffff829edd70 r tn_rlc_save_restore_register_list +ffffffff829edf60 r cayman_cs_data +ffffffff829edfa0 r SECT_CONTEXT_defs +ffffffff829ee020 r SECT_CLEAR_defs +ffffffff829ee040 r SECT_CTRLCONST_defs +ffffffff829ee060 r SECT_CONTEXT_def_2 +ffffffff829ee080 r SECT_CONTEXT_def_4 +ffffffff829ee210 r SECT_CONTEXT_def_5 +ffffffff829ee230 r SECT_CONTEXT_def_1 +ffffffff829ee9d0 r SECT_CONTEXT_def_3 +ffffffff829eeab0 r SECT_CONTEXT_def_6 +ffffffff829eeb90 r SECT_CONTEXT_def_7 +ffffffff829ef018 r SECT_CLEAR_def_1 +ffffffff829ef024 r SECT_CTRLCONST_def_1 +ffffffff829ef030 r cayman_default_state +ffffffff829f0000 r cac_weights_cayman_xt +ffffffff829f0128 r cac_weights_cayman_pro +ffffffff829f0250 r cac_weights_cayman_le +ffffffff829f0380 r cayman_cgcg_cgls_default +ffffffff829f05c0 r cayman_mgcg_default +ffffffff829f0f20 r cayman_sysls_default +ffffffff829f0ff0 r cayman_cgcg_cgls_enable +ffffffff829f1240 r cayman_cgcg_cgls_disable +ffffffff829f14a0 r cayman_mgcg_enable +ffffffff829f1520 r cayman_mgcg_disable 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radeon_lvds_bridge_connector_funcs +ffffffff82a01310 r radeon_vga_connector_funcs +ffffffff82a01388 r radeon_dvi_connector_funcs +ffffffff82a01400 r radeon_edp_connector_funcs +ffffffff82a01478 r radeon_tv_connector_funcs +ffffffff82a014f0 r radeon_lvds_connector_funcs +ffffffff82a02000 r radeon_family_name +ffffffff82a023f0 r radeon_px_quirk_list +ffffffff82a03000 r radeon_fb_funcs +ffffffff82a03018 r radeon_mode_funcs +ffffffff82a03060 r radeon_tmds_pll_enum_list +ffffffff82a03080 r radeon_tv_std_enum_list +ffffffff82a03100 r radeon_underscan_enum_list +ffffffff82a03130 r radeon_audio_enum_list +ffffffff82a03160 r radeon_dither_enum_list +ffffffff82a03180 r radeon_output_csc_enum_list +ffffffff82a031c0 r radeon_crtc_funcs +ffffffff82a03280 r hpd_names +ffffffff82a032b0 r encoder_names +ffffffff82a033e0 r radeon_afmt_init.eg_offsets +ffffffff82a04000 r aux_offset +ffffffff82a05000 R radeondrm_ca +ffffffff82a05030 r pciidlist +ffffffff82a091d0 r kms_driver +ffffffff82a092c0 r radeon_ioctls_kms +ffffffff82a0a000 r radeon_fb_helper_funcs +ffffffff82a0a008 r radeonfb_ops +ffffffff82a0b000 R radeon_fence_ops +ffffffff82a0d000 R radeon_gem_object_funcs +ffffffff82a0d060 r radeon_gem_vm_ops +ffffffff82a0e000 r radeon_i2c_algo +ffffffff82a0e010 r radeon_atom_i2c_algo +ffffffff82a0f000 r legacy_helper_funcs +ffffffff82a10000 r radeon_backlight_ops +ffffffff82a10018 r radeon_legacy_lvds_enc_funcs +ffffffff82a10038 r radeon_legacy_lvds_helper_funcs +ffffffff82a100a0 r radeon_legacy_tmds_int_enc_funcs +ffffffff82a100c0 r radeon_legacy_tmds_int_helper_funcs +ffffffff82a10128 r radeon_legacy_primary_dac_enc_funcs +ffffffff82a10148 r radeon_legacy_primary_dac_helper_funcs +ffffffff82a101b0 r radeon_legacy_tv_dac_enc_funcs +ffffffff82a101d0 r radeon_legacy_tv_dac_helper_funcs +ffffffff82a10238 r radeon_legacy_tmds_ext_enc_funcs +ffffffff82a10258 r radeon_legacy_tmds_ext_helper_funcs +ffffffff82a11000 r SLOPE_value +ffffffff82a11030 r YCOEF_EN_value +ffffffff82a11060 r YCOEF_value +ffffffff82a11090 r available_tv_modes +ffffffff82a11110 r hor_timing_NTSC +ffffffff82a11150 r vert_timing_NTSC +ffffffff82a11190 r hor_timing_PAL +ffffffff82a111d0 r vert_timing_PAL +ffffffff82a13000 r radeon_pm_state_type_name +ffffffff82a14000 r radeon_evict_flags.placements +ffffffff82a17000 r rs600_reg_safe_bm +ffffffff82a19000 r rv515_reg_safe_bm +ffffffff82a1a000 r dll_speed_table +ffffffff82a1b000 r r7xx_golden_registers +ffffffff82a1b090 r r7xx_golden_dyn_gpr_registers +ffffffff82a1b100 r rv770ce_golden_registers +ffffffff82a1b160 r rv770_golden_registers +ffffffff82a1b1b0 r rv770_mgcg_init +ffffffff82a1b8f0 r rv730_golden_registers +ffffffff82a1b950 r rv730_mgcg_init +ffffffff82a1bee0 r rv710_golden_registers +ffffffff82a1bf30 r rv710_mgcg_init +ffffffff82a1c1d0 r rv740_golden_registers +ffffffff82a1c360 r rv740_mgcg_init +ffffffff82a1e000 r rv730_smc_int_vectors +ffffffff82a1e040 r rv710_smc_int_vectors +ffffffff82a1e080 r rv740_smc_int_vectors +ffffffff82a1e0c0 r cypress_smc_int_vectors +ffffffff82a1e100 r caicos_smc_int_vectors +ffffffff82a1e140 r cayman_smc_int_vectors +ffffffff82a1f000 r tahiti_io_mc_regs +ffffffff82a1f120 r pitcairn_io_mc_regs +ffffffff82a1f240 r verde_io_mc_regs +ffffffff82a1f360 r oland_io_mc_regs +ffffffff82a1f480 r hainan_io_mc_regs +ffffffff82a1f5a0 r crtc_offsets +ffffffff82a1f5c0 r si_disp_int_status +ffffffff82a1f5e0 r tahiti_golden_registers +ffffffff82a1f760 r tahiti_golden_rlc_registers +ffffffff82a1f7b0 r tahiti_mgcg_cgcg_init +ffffffff82a1fd98 r tahiti_golden_registers2 +ffffffff82a1fdb0 r pitcairn_golden_registers +ffffffff82a1ff00 r pitcairn_golden_rlc_registers +ffffffff82a1ff40 r pitcairn_mgcg_cgcg_init +ffffffff82a203b0 r verde_golden_registers +ffffffff82a20620 r verde_golden_rlc_registers +ffffffff82a20660 r verde_mgcg_cgcg_init +ffffffff82a20ae0 r oland_golden_registers +ffffffff82a20c30 r oland_golden_rlc_registers +ffffffff82a20c70 r oland_mgcg_cgcg_init +ffffffff82a21000 r hainan_golden_registers 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lcac_cape_verde +ffffffff82a249d0 r cac_override_cape_verde +ffffffff82a249e4 r powertune_data_cape_verde +ffffffff82a24a20 r cac_weights_cape_verde_pro +ffffffff82a24ef0 r cac_weights_heathrow +ffffffff82a253c0 r cac_weights_chelsea_xt +ffffffff82a25890 r cac_weights_chelsea_pro +ffffffff82a25d60 r cac_weights_cape_verde +ffffffff82a26230 r cac_weights_mars_pro +ffffffff82a26700 r lcac_mars_pro +ffffffff82a26a60 r cac_override_oland +ffffffff82a26a74 r powertune_data_mars_pro +ffffffff82a26ab0 r cac_weights_mars_xt +ffffffff82a26f80 r cac_weights_oland_pro +ffffffff82a27450 r cac_weights_oland_xt +ffffffff82a27920 r lcac_oland +ffffffff82a27c7c r powertune_data_oland +ffffffff82a27cb8 r dte_data_oland +ffffffff82a27d90 r cac_weights_hainan +ffffffff82a28254 r powertune_data_hainan +ffffffff82a28290 r dte_data_aruba_pro +ffffffff82a28360 r dte_data_tahiti_pro +ffffffff82a28430 r dte_data_curacao_pro +ffffffff82a28500 r dte_data_neptune_xt +ffffffff82a285d0 r dte_data_sun_xt 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r opcode_table +ffffffff82a2fbd0 r atom_dst_to_src +ffffffff82a2fc50 r atom_io_names +ffffffff82a2fc80 r atom_table_names +ffffffff82a2fed0 r atom_iio_len +ffffffff82a30000 r object_connector_convert +ffffffff82a30058 R amdgpu_vbios_version_attr_group +ffffffff82a31000 r voltage_names +ffffffff82a31020 r pre_emph_names +ffffffff82a32000 r amdgpu_atombios_encoder_backlight_ops +ffffffff82a34000 r amdgpu_benchmark.common_modes +ffffffff82a35000 r amdgpu_cgs_ops +ffffffff82a36000 r amdgpu_connector_dp_helper_funcs +ffffffff82a36050 r amdgpu_connector_vga_helper_funcs +ffffffff82a360a0 r amdgpu_connector_dvi_helper_funcs +ffffffff82a360f0 r amdgpu_connector_lvds_helper_funcs +ffffffff82a36140 r amdgpu_connector_dp_funcs +ffffffff82a361c0 r amdgpu_connector_add_common_modes.common_modes +ffffffff82a36248 r amdgpu_connector_edp_funcs +ffffffff82a362c0 r amdgpu_connector_vga_funcs +ffffffff82a36338 r amdgpu_connector_dvi_funcs +ffffffff82a363b0 r amdgpu_connector_lvds_funcs +ffffffff82a38000 R amdgpu_ctx_num_entities +ffffffff82a39000 r amdgpu_kms_driver +ffffffff82a390f0 r amdgpu_device_ip_reinit_late_sriov.ip_order +ffffffff82a3a000 r hw_id_map +ffffffff82a3a090 r hw_id_names +ffffffff82a3b000 r hpd_names +ffffffff82a3b030 r encoder_names +ffffffff82a3b180 r dcc_retile_formats +ffffffff82a3b270 r dcc_formats +ffffffff82a3b360 R amdgpu_mode_funcs +ffffffff82a3b3b0 r amdgpu_underscan_enum_list +ffffffff82a3b3e0 r amdgpu_audio_enum_list +ffffffff82a3b410 r amdgpu_dither_enum_list +ffffffff82a3b430 r amdgpu_fb_funcs +ffffffff82a3c000 R amdgpu_dmabuf_ops +ffffffff82a3d000 R amdgpu_ioctls_kms +ffffffff82a3d210 R amdgpu_ca +ffffffff82a3d240 r pciidlist +ffffffff82a3e110 r amdgpu_unsupported_pciidlist +ffffffff82a3e690 r amdgpu_kms_driver +ffffffff82a3f000 r amdgpu_job_fence_ops +ffffffff82a3f038 r amdgpu_fence_ops +ffffffff82a40000 r amdgpu_gem_object_funcs +ffffffff82a40060 r amdgpu_gem_vm_ops +ffffffff82a42000 R amdgpu_gtt_mgr_attr_group +ffffffff82a42018 r amdgpu_gtt_mgr_func +ffffffff82a43000 r amdgpu_atombios_i2c_algo +ffffffff82a44000 R amdgpu_sched_ops +ffffffff82a47000 r amdgpu_vram_names +ffffffff82a48000 r amdgpu_preempt_mgr_func +ffffffff82a49000 R psp_ip_funcs +ffffffff82a490a0 R psp_v3_1_ip_block +ffffffff82a490b8 R psp_v10_0_ip_block +ffffffff82a490d0 R psp_v11_0_ip_block +ffffffff82a490e8 R psp_v11_0_8_ip_block +ffffffff82a49100 R psp_v12_0_ip_block +ffffffff82a49118 R psp_v13_0_ip_block +ffffffff82a49130 R psp_v13_0_4_ip_block +ffffffff82a4b000 r amdgpu_evict_flags.placements +ffffffff82a4f000 R amdgpu_vkms_ip_block +ffffffff82a51000 R amdgpu_vm_cpu_funcs +ffffffff82a53000 R amdgpu_vm_sdma_funcs +ffffffff82a54000 R amdgpu_vram_mgr_attr_group +ffffffff82a54018 r amdgpu_vram_mgr_func +ffffffff82a55000 r xgmi_pcs_err_status_reg_arct +ffffffff82a56000 r GC_BASE +ffffffff82a560c0 r HDP_BASE +ffffffff82a56180 r MMHUB_BASE +ffffffff82a56240 r ATHUB_BASE +ffffffff82a56300 r NBIF0_BASE +ffffffff82a563c0 r MP0_BASE +ffffffff82a56480 r MP1_BASE +ffffffff82a56540 r UVD_BASE +ffffffff82a56600 r DF_BASE +ffffffff82a566c0 r OSSSYS_BASE +ffffffff82a56780 r SDMA0_BASE +ffffffff82a56840 r SDMA1_BASE +ffffffff82a56900 r SDMA2_BASE +ffffffff82a569c0 r SDMA3_BASE +ffffffff82a56a80 r SDMA4_BASE +ffffffff82a56b40 r SDMA5_BASE +ffffffff82a56c00 r SDMA6_BASE +ffffffff82a56cc0 r SDMA7_BASE +ffffffff82a56d80 r SMUIO_BASE +ffffffff82a56e40 r THM_BASE +ffffffff82a56f00 r UMC_BASE +ffffffff82a56fc0 r RSMU_BASE +ffffffff82a58000 r cz_ih_ip_funcs +ffffffff82a580a0 R cz_ih_ip_block +ffffffff82a580b8 r cz_ih_funcs +ffffffff82a59000 r crtc_offsets +ffffffff82a59020 r dce_v10_0_ip_funcs +ffffffff82a590c0 R dce_v10_0_ip_block +ffffffff82a590d8 R dce_v10_1_ip_block +ffffffff82a590f0 r dce_v10_0_display_funcs +ffffffff82a59150 r hpd_offsets +ffffffff82a59168 r dce_v10_0_encoder_funcs +ffffffff82a59188 r dce_v10_0_dac_helper_funcs +ffffffff82a591f0 r dce_v10_0_dig_helper_funcs +ffffffff82a59258 r dce_v10_0_ext_helper_funcs +ffffffff82a592c0 r dce_v10_0_audio_write_sad_regs.eld_reg_to_type +ffffffff82a592f0 r dce_v10_0_crtc_irq_funcs +ffffffff82a59300 r dce_v10_0_pageflip_irq_funcs +ffffffff82a59310 r dce_v10_0_hpd_irq_funcs +ffffffff82a59320 r interrupt_status_offsets +ffffffff82a59380 r dce_v10_0_crtc_funcs +ffffffff82a59440 r dce_v10_0_crtc_helper_funcs +ffffffff82a594c0 r vga_control_regs +ffffffff82a594e0 r dig_offsets +ffffffff82a59500 r pin_offsets +ffffffff82a59520 r fiji_mgcg_cgcg_init +ffffffff82a59540 r golden_settings_fiji_a10 +ffffffff82a59570 r tonga_mgcg_cgcg_init +ffffffff82a59590 r golden_settings_tonga_a11 +ffffffff82a5a000 r crtc_offsets +ffffffff82a5a020 r dce_v11_0_ip_funcs +ffffffff82a5a0c0 R dce_v11_0_ip_block +ffffffff82a5a0d8 R dce_v11_2_ip_block +ffffffff82a5a0f0 r dce_v11_0_display_funcs +ffffffff82a5a150 r hpd_offsets +ffffffff82a5a168 r dce_v11_0_encoder_funcs +ffffffff82a5a188 r dce_v11_0_dac_helper_funcs +ffffffff82a5a1f0 r dce_v11_0_dig_helper_funcs +ffffffff82a5a258 r dce_v11_0_ext_helper_funcs +ffffffff82a5a2c0 r dce_v11_0_audio_write_sad_regs.eld_reg_to_type +ffffffff82a5a2f0 r dce_v11_0_crtc_irq_funcs +ffffffff82a5a300 r dce_v11_0_pageflip_irq_funcs +ffffffff82a5a310 r dce_v11_0_hpd_irq_funcs +ffffffff82a5a320 r interrupt_status_offsets +ffffffff82a5a380 r dce_v11_0_crtc_funcs +ffffffff82a5a440 r dce_v11_0_crtc_helper_funcs +ffffffff82a5a4c0 r vga_control_regs +ffffffff82a5a4e0 r dig_offsets +ffffffff82a5a510 r cz_mgcg_cgcg_init +ffffffff82a5a530 r cz_golden_settings_a11 +ffffffff82a5a550 r stoney_golden_settings_a11 +ffffffff82a5a570 r polaris11_golden_settings_a11 +ffffffff82a5a5b0 r polaris10_golden_settings_a11 +ffffffff82a5b000 R df_v1_7_funcs +ffffffff82a5b070 r df_v1_7_channel_number +ffffffff82a5c000 R df_v3_6_funcs +ffffffff82a5c070 r df_v3_6_channel_number +ffffffff82a5d000 r GC_BASE +ffffffff82a5d0a8 r HDP_BASE +ffffffff82a5d150 r MMHUB_BASE +ffffffff82a5d1f8 r ATHUB_BASE +ffffffff82a5d2a0 r NBIO_BASE +ffffffff82a5d348 r MP0_BASE +ffffffff82a5d3f0 r MP1_BASE +ffffffff82a5d498 r VCN0_BASE +ffffffff82a5d540 r DF_BASE +ffffffff82a5d5e8 r DCN_BASE +ffffffff82a5d690 r OSSSYS_BASE +ffffffff82a5d738 r SMUIO_BASE +ffffffff82a5d7e0 r THM_BASE +ffffffff82a5e000 r gfx_v10_0_ip_funcs +ffffffff82a5e0a0 R gfx_v10_0_ip_block +ffffffff82a5e0b8 r gfx_v10_0_kiq_pm4_funcs +ffffffff82a5e0f8 r gfx_v10_0_ring_funcs_kiq +ffffffff82a5e218 r gfx_v10_0_ring_funcs_gfx +ffffffff82a5e338 r gfx_v10_0_ring_funcs_compute +ffffffff82a5e458 r gfx_v10_0_eop_irq_funcs +ffffffff82a5e468 r gfx_v10_0_kiq_irq_funcs +ffffffff82a5e478 r gfx_v10_0_priv_reg_irq_funcs +ffffffff82a5e488 r gfx_v10_0_priv_inst_irq_funcs +ffffffff82a5e498 r gfx_v10_0_rlc_funcs +ffffffff82a5e500 r gfx_v10_0_rlc_funcs_sriov +ffffffff82a5e570 r gfx10_cs_data +ffffffff82a5e590 r gfx10_SECT_CONTEXT_defs +ffffffff82a5e620 r gfx10_SECT_CONTEXT_def_1 +ffffffff82a5e980 r gfx10_SECT_CONTEXT_def_3 +ffffffff82a5e990 r gfx10_SECT_CONTEXT_def_4 +ffffffff82a5ec08 r gfx10_SECT_CONTEXT_def_5 +ffffffff82a5ec10 r gfx10_SECT_CONTEXT_def_6 +ffffffff82a5ec20 r gfx10_SECT_CONTEXT_def_2 +ffffffff82a5f060 r gfx10_SECT_CONTEXT_def_7 +ffffffff82a5f170 r gfx10_SECT_CONTEXT_def_8 +ffffffff82a5f4a0 r gfx_v10_0_gfx_funcs +ffffffff82a5f4e0 r golden_settings_gc_rlc_spm_10_0_nv10 +ffffffff82a65780 r golden_settings_gc_rlc_spm_10_1_nv14 +ffffffff82a691a0 r golden_settings_gc_rlc_spm_10_1_2_nv12 +ffffffff82a6f440 r golden_settings_gc_10_1 +ffffffff82a6f800 r golden_settings_gc_10_0_nv10 +ffffffff82a6f800 r golden_settings_gc_10_1_1 +ffffffff82a6fb90 r golden_settings_gc_10_1_2 +ffffffff82a6fb90 r golden_settings_gc_10_1_nv14 +ffffffff82a6ff80 r golden_settings_gc_10_1_2_nv12 +ffffffff82a6ff80 r golden_settings_gc_10_3 +ffffffff82a70388 r golden_settings_gc_10_3_sienna_cichlid +ffffffff82a70390 r golden_settings_gc_10_3_2 +ffffffff82a70780 r golden_settings_gc_10_3_vangogh +ffffffff82a709e0 r golden_settings_gc_10_3_3 +ffffffff82a70bc0 r golden_settings_gc_10_3_4 +ffffffff82a70f20 r golden_settings_gc_10_3_5 +ffffffff82a71220 r golden_settings_gc_10_0_cyan_skillfish +ffffffff82a71550 r golden_settings_gc_10_3_6 +ffffffff82a71760 r golden_settings_gc_10_3_7 +ffffffff82a72000 r gfx_v11_0_ip_funcs +ffffffff82a720a0 R gfx_v11_0_ip_block +ffffffff82a720b8 r gfx_v11_0_kiq_pm4_funcs +ffffffff82a720f8 r gfx_v11_0_ring_funcs_kiq +ffffffff82a72218 r gfx_v11_0_ring_funcs_gfx +ffffffff82a72338 r gfx_v11_0_ring_funcs_compute +ffffffff82a72458 r gfx_v11_0_eop_irq_funcs +ffffffff82a72468 r gfx_v11_0_priv_reg_irq_funcs +ffffffff82a72478 r gfx_v11_0_priv_inst_irq_funcs +ffffffff82a72488 r gfx_v11_0_rlc_funcs +ffffffff82a724f0 r gfx11_cs_data +ffffffff82a72510 r gfx11_SECT_CONTEXT_defs +ffffffff82a72590 r gfx11_SECT_CONTEXT_def_1 +ffffffff82a728f0 r gfx11_SECT_CONTEXT_def_3 +ffffffff82a72900 r gfx11_SECT_CONTEXT_def_5 +ffffffff82a72908 r gfx11_SECT_CONTEXT_def_6 +ffffffff82a72910 r gfx11_SECT_CONTEXT_def_2 +ffffffff82a72d50 r gfx11_SECT_CONTEXT_def_4 +ffffffff82a72fd0 r gfx11_SECT_CONTEXT_def_7 +ffffffff82a73438 r gfx_v11_0_gfx_funcs +ffffffff82a73480 r golden_settings_gc_11_0_1 +ffffffff82a74000 r gfx_v8_0_ip_funcs +ffffffff82a740a0 R gfx_v8_0_ip_block +ffffffff82a740b8 R gfx_v8_1_ip_block +ffffffff82a740d0 r gfx_v8_0_gfx_funcs +ffffffff82a74110 r gfx_v8_0_ring_funcs_kiq +ffffffff82a74230 r gfx_v8_0_ring_funcs_gfx +ffffffff82a74350 r gfx_v8_0_ring_funcs_compute +ffffffff82a74470 r amdgpu_gds_reg_offset +ffffffff82a74570 r gfx_v8_0_eop_irq_funcs +ffffffff82a74580 r gfx_v8_0_priv_reg_irq_funcs +ffffffff82a74590 r gfx_v8_0_priv_inst_irq_funcs +ffffffff82a745a0 r gfx_v8_0_cp_ecc_error_irq_funcs +ffffffff82a745b0 r gfx_v8_0_sq_irq_funcs +ffffffff82a745c0 r sq_edc_source_names +ffffffff82a745f8 r iceland_rlc_funcs +ffffffff82a74660 r vi_cs_data +ffffffff82a74680 r vi_SECT_CONTEXT_defs +ffffffff82a74700 r vi_SECT_CONTEXT_def_1 +ffffffff82a74a50 r vi_SECT_CONTEXT_def_3 +ffffffff82a74a70 r vi_SECT_CONTEXT_def_4 +ffffffff82a74ce4 r vi_SECT_CONTEXT_def_5 +ffffffff82a74cec r vi_SECT_CONTEXT_def_6 +ffffffff82a74cf0 r vi_SECT_CONTEXT_def_2 +ffffffff82a75140 r vi_SECT_CONTEXT_def_7 +ffffffff82a754f0 r vgpr_init_compute_shader +ffffffff82a75600 r vgpr_init_regs +ffffffff82a75690 r sgpr1_init_regs +ffffffff82a75720 r sgpr2_init_regs +ffffffff82a757b0 r sec_ded_counter_registers +ffffffff82a75820 r iceland_mgcg_cgcg_init +ffffffff82a75b20 r golden_settings_iceland_a11 +ffffffff82a75be0 r iceland_golden_common_all +ffffffff82a75c40 r fiji_mgcg_cgcg_init +ffffffff82a75df0 r golden_settings_fiji_a10 +ffffffff82a75e80 r fiji_golden_common_all +ffffffff82a75f00 r tonga_mgcg_cgcg_init +ffffffff82a76290 r golden_settings_tonga_a11 +ffffffff82a76350 r tonga_golden_common_all +ffffffff82a763b0 r golden_settings_vegam_a11 +ffffffff82a76480 r vegam_golden_common_all +ffffffff82a764d0 r golden_settings_polaris11_a11 +ffffffff82a765a0 r polaris11_golden_common_all +ffffffff82a765f0 r golden_settings_polaris10_a11 +ffffffff82a766c0 r polaris10_golden_common_all +ffffffff82a76720 r cz_mgcg_cgcg_init +ffffffff82a76ab0 r cz_golden_settings_a11 +ffffffff82a76b40 r cz_golden_common_all +ffffffff82a76ba0 r stoney_mgcg_cgcg_init +ffffffff82a76be0 r stoney_golden_settings_a11 +ffffffff82a76c60 r stoney_golden_common_all +ffffffff82a77000 R gfx_v9_0_ras_ops +ffffffff82a77040 r gfx_v9_0_ip_funcs +ffffffff82a770e0 R gfx_v9_0_ip_block +ffffffff82a77100 r ras_gfx_subblocks +ffffffff82a77b80 r gfx_v9_0_edc_counter_regs +ffffffff82a77f20 r gfx_v9_0_ras_fields +ffffffff82a79000 r gfx_v9_0_kiq_pm4_funcs +ffffffff82a79040 r gfx_v9_0_ring_funcs_kiq +ffffffff82a79160 r gfx_v9_0_ring_funcs_gfx +ffffffff82a79280 r gfx_v9_0_ring_funcs_compute +ffffffff82a793a0 r gfx_v9_0_eop_irq_funcs +ffffffff82a793b0 r gfx_v9_0_priv_reg_irq_funcs +ffffffff82a793c0 r gfx_v9_0_priv_inst_irq_funcs +ffffffff82a793d0 r gfx_v9_0_cp_ecc_error_irq_funcs +ffffffff82a793e0 r gfx_v9_0_rlc_funcs +ffffffff82a79450 r gfx9_cs_data +ffffffff82a79470 r gfx9_SECT_CONTEXT_defs +ffffffff82a79500 r gfx9_SECT_CONTEXT_def_1 +ffffffff82a79850 r gfx9_SECT_CONTEXT_def_3 +ffffffff82a79860 r gfx9_SECT_CONTEXT_def_4 +ffffffff82a79ad4 r gfx9_SECT_CONTEXT_def_5 +ffffffff82a79adc r gfx9_SECT_CONTEXT_def_6 +ffffffff82a79ae0 r gfx9_SECT_CONTEXT_def_7 +ffffffff82a79bf0 r gfx9_SECT_CONTEXT_def_2 +ffffffff82a7a060 r gfx9_SECT_CONTEXT_def_8 +ffffffff82a7a2d0 r vgpr_init_compute_shader_arcturus +ffffffff82a7ab60 r vgpr_init_regs_arcturus +ffffffff82a7acf0 r vgpr_init_regs +ffffffff82a7ae80 r sgpr1_init_regs +ffffffff82a7b010 r sgpr2_init_regs +ffffffff82a7b198 r gfx_v9_0_gfx_funcs +ffffffff82a7b1e0 r golden_settings_gc_9_0 +ffffffff82a7b3c0 r golden_settings_gc_9_0_vg10 +ffffffff82a7b570 r golden_settings_gc_9_2_1 +ffffffff82a7b6f0 r golden_settings_gc_9_2_1_vg12 +ffffffff82a7b830 r golden_settings_gc_9_0_vg20 +ffffffff82a7b940 r golden_settings_gc_9_4_1_arct +ffffffff82a7ba50 r golden_settings_gc_9_1 +ffffffff82a7bc90 r golden_settings_gc_9_1_rv2 +ffffffff82a7be60 r golden_settings_gc_9_1_rv1 +ffffffff82a7bf10 r golden_settings_gc_9_1_rn +ffffffff82a7c030 r golden_settings_gc_9_x_common +ffffffff82a7d000 R gfx_v9_4_ras_ops +ffffffff82a7d040 r gfx_v9_4_edc_counter_regs +ffffffff82a7d420 r gfx_v9_4_ras_fields +ffffffff82a7f000 R vgpr_init_regs_aldebaran +ffffffff82a7f1b0 R sgpr112_init_regs_aldebaran +ffffffff82a7f360 R sgpr96_init_regs_aldebaran +ffffffff82a7f510 R sgpr64_init_regs_aldebaran +ffffffff82a7f6c0 r golden_settings_gc_9_4_2_alde +ffffffff82a7f720 r golden_settings_gc_9_4_2_alde_die_0 +ffffffff82a7f7b0 r golden_settings_gc_9_4_2_alde_die_1 +ffffffff82a7f840 r sgpr112_init_compute_shader_aldebaran +ffffffff82a7fa60 r sgpr96_init_compute_shader_aldebaran +ffffffff82a7fc50 r sgpr64_init_compute_shader_aldebaran +ffffffff82a7fdc0 r vgpr_init_compute_shader_aldebaran +ffffffff82a806a0 r gfx_v9_4_2_edc_counter_regs +ffffffff82a80a20 r gfx_v9_4_2_ras_fields +ffffffff82a823c0 r gfx_v9_4_2_utc_blocks +ffffffff82a83000 R gfxhub_v1_0_funcs +ffffffff82a84000 R gfxhub_v2_0_funcs +ffffffff82a84060 r gfxhub_v2_0_vmhub_funcs +ffffffff82a84070 r gfxhub_client_ids +ffffffff82a85000 R gfxhub_v2_1_funcs +ffffffff82a85060 r gfxhub_v2_1_vmhub_funcs +ffffffff82a85070 r gfxhub_client_ids +ffffffff82a86000 R gfxhub_v3_0_funcs +ffffffff82a86060 r gfxhub_v3_0_vmhub_funcs +ffffffff82a86070 r gfxhub_client_ids +ffffffff82a87000 R gfxhub_v3_0_3_funcs +ffffffff82a87060 r gfxhub_v3_0_3_vmhub_funcs +ffffffff82a87070 r gfxhub_client_ids +ffffffff82a88000 R gmc_v10_0_ip_funcs +ffffffff82a880a0 R gmc_v10_0_ip_block +ffffffff82a880b8 r gmc_v10_0_gmc_funcs +ffffffff82a88100 r gmc_v10_0_irq_funcs +ffffffff82a88110 r gmc_v10_0_ecc_funcs +ffffffff82a89000 R gmc_v11_0_ip_funcs +ffffffff82a890a0 R gmc_v11_0_ip_block +ffffffff82a890b8 r gmc_v11_0_gmc_funcs +ffffffff82a89100 r gmc_v11_0_irq_funcs +ffffffff82a89110 r gmc_v11_0_ecc_funcs +ffffffff82a8a000 r gmc_v7_0_ip_funcs +ffffffff82a8a0a0 R gmc_v7_0_ip_block +ffffffff82a8a0b8 R gmc_v7_4_ip_block +ffffffff82a8a0d0 r gmc_v7_0_gmc_funcs +ffffffff82a8a118 r gmc_v7_0_irq_funcs +ffffffff82a8a128 r iceland_mgcg_cgcg_init +ffffffff82a8a140 r golden_settings_iceland_a11 +ffffffff82a8a170 r mc_cg_registers +ffffffff82a8a1a0 r mc_cg_en +ffffffff82a8a1d0 r mc_cg_ls_en +ffffffff82a8b000 r gmc_v8_0_ip_funcs +ffffffff82a8b0a0 R gmc_v8_0_ip_block +ffffffff82a8b0b8 R gmc_v8_1_ip_block +ffffffff82a8b0d0 R gmc_v8_5_ip_block +ffffffff82a8b0e8 r gmc_v8_0_gmc_funcs +ffffffff82a8b130 r gmc_v8_0_irq_funcs +ffffffff82a8b140 r fiji_mgcg_cgcg_init +ffffffff82a8b150 r golden_settings_fiji_a10 +ffffffff82a8b180 r tonga_mgcg_cgcg_init +ffffffff82a8b190 r golden_settings_tonga_a11 +ffffffff82a8b1f0 r golden_settings_polaris11_a11 +ffffffff82a8b220 r golden_settings_polaris10_a11 +ffffffff82a8b25c r cz_mgcg_cgcg_init +ffffffff82a8b270 r stoney_mgcg_cgcg_init +ffffffff82a8b290 r golden_settings_stoney_common +ffffffff82a8c000 R gmc_v9_0_ip_funcs +ffffffff82a8c0a0 R gmc_v9_0_ip_block +ffffffff82a8c0b8 r gmc_v9_0_gmc_funcs +ffffffff82a8c100 r gmc_v9_0_irq_funcs +ffffffff82a8c110 r gmc_v9_0_ecc_funcs +ffffffff82a8c120 r gfxhub_client_ids +ffffffff82a8c190 r mmhub_client_ids_vega10 +ffffffff82a8c480 r mmhub_client_ids_vega12 +ffffffff82a8c780 r mmhub_client_ids_vega20 +ffffffff82a8ca70 r mmhub_client_ids_arcturus +ffffffff82a8e280 r mmhub_client_ids_raven +ffffffff82a8e440 r mmhub_client_ids_renoir +ffffffff82a8e630 r mmhub_client_ids_aldebaran +ffffffff82a8fe40 r ecc_umc_mcumc_ctrl_addrs +ffffffff82a8fec0 r ecc_umc_mcumc_ctrl_mask_addrs +ffffffff82a8ff40 r golden_settings_mmhub_1_0_0 +ffffffff82a8ff70 r golden_settings_athub_1_0_0 +ffffffff82a90000 R hdp_v4_0_funcs +ffffffff82a91000 R hdp_v5_0_funcs +ffffffff82a92000 R hdp_v5_2_funcs +ffffffff82a93000 R hdp_v6_0_funcs +ffffffff82a94000 r iceland_ih_ip_funcs +ffffffff82a940a0 R iceland_ih_ip_block +ffffffff82a940b8 r iceland_ih_funcs +ffffffff82a95000 r ih_v6_0_ip_funcs +ffffffff82a950a0 R ih_v6_0_ip_block +ffffffff82a950b8 r ih_v6_0_funcs +ffffffff82a950d8 r ih_v6_0_self_irq_funcs +ffffffff82a96000 R gfx_v11_0_imu_funcs +ffffffff82a96030 r imu_rlc_ram_golden_11 +ffffffff82a96680 r imu_rlc_ram_golden_11_0_2 +ffffffff82a97000 r imu_rlc_ram_golden_11_0_3 +ffffffff82a98000 r jpeg_v1_0_decode_ring_vm_funcs +ffffffff82a98120 r jpeg_v1_0_irq_funcs +ffffffff82a99000 r jpeg_v2_0_ip_funcs +ffffffff82a990a0 R jpeg_v2_0_ip_block +ffffffff82a990b8 r jpeg_v2_0_dec_ring_vm_funcs +ffffffff82a991d8 r jpeg_v2_0_irq_funcs +ffffffff82a9a000 r jpeg_v2_5_ip_funcs +ffffffff82a9a0a0 R jpeg_v2_5_ip_block +ffffffff82a9a0b8 r jpeg_v2_6_ip_funcs +ffffffff82a9a158 R jpeg_v2_6_ip_block +ffffffff82a9a170 R jpeg_v2_6_ras_hw_ops +ffffffff82a9a1b0 r jpeg_v2_5_dec_ring_vm_funcs +ffffffff82a9a2d0 r jpeg_v2_6_dec_ring_vm_funcs +ffffffff82a9a3f0 r jpeg_v2_5_irq_funcs +ffffffff82a9b000 r jpeg_v3_0_ip_funcs +ffffffff82a9b0a0 R jpeg_v3_0_ip_block +ffffffff82a9b0b8 r jpeg_v3_0_dec_ring_vm_funcs +ffffffff82a9b1d8 r jpeg_v3_0_irq_funcs +ffffffff82a9c000 r jpeg_v4_0_ip_funcs +ffffffff82a9c0a0 R jpeg_v4_0_ip_block +ffffffff82a9c0b8 r jpeg_v4_0_dec_ring_vm_funcs +ffffffff82a9c1d8 r jpeg_v4_0_irq_funcs +ffffffff82a9d000 R lsdma_v6_0_funcs +ffffffff82a9e000 R mca_v3_0_mp0_hw_ops +ffffffff82a9e040 R mca_v3_0_mp1_hw_ops +ffffffff82a9e080 R mca_v3_0_mpio_hw_ops +ffffffff82a9e0c0 R mca_v3_0_funcs +ffffffff82a9f000 r mes_v10_1_ip_funcs +ffffffff82a9f0a0 R mes_v10_1_ip_block +ffffffff82a9f0b8 r mes_v10_1_funcs +ffffffff82a9f0e8 r mes_v10_1_ring_funcs +ffffffff82aa0000 r mes_v11_0_ip_funcs +ffffffff82aa00a0 R mes_v11_0_ip_block +ffffffff82aa00b8 r mes_v11_0_funcs +ffffffff82aa00e8 r mes_v11_0_ring_funcs +ffffffff82aa1000 R mmhub_v1_0_funcs +ffffffff82aa1050 r mmhub_v1_0_edc_cnt_regs +ffffffff82aa10c0 r mmhub_v1_0_ras_fields +ffffffff82aa2000 R mmhub_v1_7_funcs +ffffffff82aa2050 r mmhub_v1_7_edc_cnt_regs +ffffffff82aa2250 r mmhub_v1_7_ras_fields +ffffffff82aa39c0 r mmhub_v1_7_ea_err_status_regs +ffffffff82aa4000 R mmhub_v2_0_funcs +ffffffff82aa4050 r mmhub_v2_0_vmhub_funcs +ffffffff82aa4060 r mmhub_client_ids_navi1x +ffffffff82aa4190 r mmhub_client_ids_sienna_cichlid +ffffffff82aa4450 r mmhub_client_ids_beige_goby +ffffffff82aa5000 R mmhub_v2_3_funcs +ffffffff82aa5050 r mmhub_v2_3_vmhub_funcs +ffffffff82aa5060 r mmhub_client_ids_vangogh +ffffffff82aa6000 R mmhub_v3_0_funcs +ffffffff82aa6050 r mmhub_v3_0_vmhub_funcs +ffffffff82aa6060 r mmhub_client_ids_v3_0_0 +ffffffff82aa7000 R mmhub_v3_0_1_funcs +ffffffff82aa7050 r mmhub_v3_0_1_vmhub_funcs +ffffffff82aa7060 r mmhub_client_ids_v3_0_1 +ffffffff82aa8000 R mmhub_v3_0_2_funcs +ffffffff82aa8050 r mmhub_v3_0_2_vmhub_funcs +ffffffff82aa8060 r mmhub_client_ids_v3_0_2 +ffffffff82aa9000 R mmhub_v9_4_ras_hw_ops +ffffffff82aa9040 R mmhub_v9_4_funcs +ffffffff82aa9090 r mmhub_v9_4_edc_cnt_regs +ffffffff82aa9330 r mmhub_v9_4_ras_fields +ffffffff82aab3b0 r mmhub_v9_4_err_status_regs +ffffffff82aac000 r xgpu_ai_mailbox_ack_irq_funcs +ffffffff82aac010 r xgpu_ai_mailbox_rcv_irq_funcs +ffffffff82aac020 R xgpu_ai_virt_ops +ffffffff82aad000 r xgpu_nv_mailbox_ack_irq_funcs +ffffffff82aad010 r xgpu_nv_mailbox_rcv_irq_funcs +ffffffff82aad020 R xgpu_nv_virt_ops +ffffffff82aae000 r xgpu_fiji_mgcg_cgcg_init +ffffffff82aae240 r xgpu_fiji_golden_settings_a10 +ffffffff82aae370 r xgpu_fiji_golden_common_all +ffffffff82aae3f0 r xgpu_tonga_mgcg_cgcg_init +ffffffff82aae810 r xgpu_tonga_golden_settings_a11 +ffffffff82aae9d0 r xgpu_tonga_golden_common_all +ffffffff82aaea28 r xgpu_vi_mailbox_ack_irq_funcs +ffffffff82aaea38 r xgpu_vi_mailbox_rcv_irq_funcs +ffffffff82aaea48 R xgpu_vi_virt_ops +ffffffff82aaf000 r navi10_ih_ip_funcs +ffffffff82aaf0a0 R navi10_ih_ip_block +ffffffff82aaf0b8 r navi10_ih_funcs +ffffffff82aaf0d8 r navi10_ih_self_irq_funcs +ffffffff82ab0000 R nbio_v2_3_hdp_flush_reg +ffffffff82ab0048 R nbio_v2_3_funcs +ffffffff82ab1000 R nbio_v4_3_hdp_flush_reg +ffffffff82ab1048 R nbio_v4_3_funcs +ffffffff82ab1130 R nbio_v4_3_sriov_funcs +ffffffff82ab2000 R nbio_v6_1_hdp_flush_reg +ffffffff82ab2048 R nbio_v6_1_funcs +ffffffff82ab3000 R nbio_v7_0_hdp_flush_reg +ffffffff82ab3048 R nbio_v7_0_funcs +ffffffff82ab4000 R nbio_v7_2_hdp_flush_reg +ffffffff82ab4048 R nbio_v7_2_funcs +ffffffff82ab5000 R nbio_v7_4_hdp_flush_reg +ffffffff82ab5048 R nbio_v7_4_ras_hw_ops +ffffffff82ab5088 R nbio_v7_4_funcs +ffffffff82ab5170 r nbio_v7_4_ras_controller_irq_funcs +ffffffff82ab5180 r nbio_v7_4_ras_err_event_athub_irq_funcs +ffffffff82ab6000 R nbio_v7_7_hdp_flush_reg +ffffffff82ab6048 R nbio_v7_7_funcs +ffffffff82ab7000 r nv_common_ip_funcs +ffffffff82ab70a0 R nv_common_ip_block +ffffffff82ab70b8 r nv_asic_funcs +ffffffff82ab7170 r nv_allowed_read_registers +ffffffff82ab72f0 r nv_video_codecs_encode +ffffffff82ab7300 r sc_video_codecs_decode +ffffffff82ab7310 r yc_video_codecs_decode +ffffffff82ab7320 r bg_video_codecs_encode +ffffffff82ab7330 r bg_video_codecs_decode +ffffffff82ab7340 r nv_video_codecs_decode +ffffffff82ab7350 r nv_video_codecs_encode_array +ffffffff82ab7380 r sc_video_codecs_decode_array +ffffffff82ab7420 r yc_video_codecs_decode_array +ffffffff82ab7490 r bg_video_codecs_decode_array +ffffffff82ab74d0 r nv_video_codecs_decode_array +ffffffff82ab8000 r psp_v10_0_funcs +ffffffff82ab9000 r psp_v11_0_funcs +ffffffff82aba000 r psp_v11_0_8_funcs +ffffffff82abb000 r psp_v12_0_funcs +ffffffff82abc000 r psp_v13_0_funcs +ffffffff82abd000 r psp_v13_0_4_funcs +ffffffff82abe000 r psp_v3_1_funcs +ffffffff82abf000 r sdma_v2_4_ip_funcs +ffffffff82abf0a0 R sdma_v2_4_ip_block +ffffffff82abf0b8 r sdma_v2_4_ring_funcs +ffffffff82abf1d8 r sdma_v2_4_buffer_funcs +ffffffff82abf1f8 r sdma_v2_4_vm_pte_funcs +ffffffff82abf218 r sdma_v2_4_trap_irq_funcs +ffffffff82abf228 r sdma_v2_4_illegal_inst_irq_funcs +ffffffff82abf240 r iceland_mgcg_cgcg_init +ffffffff82abf260 r golden_settings_iceland_a11 +ffffffff82ac0000 r sdma_v3_0_ip_funcs +ffffffff82ac00a0 R sdma_v3_0_ip_block +ffffffff82ac00b8 R sdma_v3_1_ip_block +ffffffff82ac00d0 r sdma_v3_0_ring_funcs +ffffffff82ac01f0 r sdma_v3_0_buffer_funcs +ffffffff82ac0210 r sdma_v3_0_vm_pte_funcs +ffffffff82ac0230 r sdma_v3_0_trap_irq_funcs +ffffffff82ac0240 r sdma_v3_0_illegal_inst_irq_funcs +ffffffff82ac0250 r fiji_mgcg_cgcg_init +ffffffff82ac0270 r golden_settings_fiji_a10 +ffffffff82ac02d0 r tonga_mgcg_cgcg_init +ffffffff82ac02f0 r golden_settings_tonga_a11 +ffffffff82ac0370 r golden_settings_polaris11_a11 +ffffffff82ac03f0 r golden_settings_polaris10_a11 +ffffffff82ac0470 r cz_mgcg_cgcg_init +ffffffff82ac0490 r cz_golden_settings_a11 +ffffffff82ac0520 r stoney_mgcg_cgcg_init +ffffffff82ac0530 r stoney_golden_settings_a11 +ffffffff82ac1000 R sdma_v4_0_ip_funcs +ffffffff82ac10a0 R sdma_v4_0_ras_hw_ops +ffffffff82ac10e0 R sdma_v4_0_ip_block +ffffffff82ac10f8 r sdma_v4_0_ring_funcs_2nd_mmhub +ffffffff82ac1218 r sdma_v4_0_ring_funcs +ffffffff82ac1338 r sdma_v4_0_page_ring_funcs_2nd_mmhub +ffffffff82ac1458 r sdma_v4_0_page_ring_funcs +ffffffff82ac1578 r sdma_v4_0_buffer_funcs +ffffffff82ac1598 r sdma_v4_0_vm_pte_funcs +ffffffff82ac15b8 r sdma_v4_0_trap_irq_funcs +ffffffff82ac15c8 r sdma_v4_0_illegal_inst_irq_funcs +ffffffff82ac15d8 r sdma_v4_0_ecc_irq_funcs +ffffffff82ac15e8 r sdma_v4_0_vm_hole_irq_funcs +ffffffff82ac15f8 r sdma_v4_0_doorbell_invalid_irq_funcs +ffffffff82ac1608 r sdma_v4_0_pool_timeout_irq_funcs +ffffffff82ac1618 r sdma_v4_0_srbm_write_irq_funcs +ffffffff82ac1630 r golden_settings_sdma_4 +ffffffff82ac1890 r golden_settings_sdma_vg10 +ffffffff82ac1940 r golden_settings_sdma_vg12 +ffffffff82ac19f0 r golden_settings_sdma0_4_2_init +ffffffff82ac1a10 r golden_settings_sdma0_4_2 +ffffffff82ac1ca0 r golden_settings_sdma1_4_2 +ffffffff82ac1f30 r golden_settings_sdma_arct +ffffffff82ac2230 r golden_settings_sdma_aldebaran +ffffffff82ac23a0 r golden_settings_sdma_4_1 +ffffffff82ac24b0 r golden_settings_sdma_rv2 +ffffffff82ac24e0 r golden_settings_sdma_rv1 +ffffffff82ac2510 r golden_settings_sdma_4_3 +ffffffff82ac2600 r sdma_v4_0_ras_fields +ffffffff82ac3000 R sdma_v4_4_ras_hw_ops +ffffffff82ac3040 r sdma_v4_4_ras_fields +ffffffff82ac4000 R sdma_v5_0_ip_funcs +ffffffff82ac40a0 R sdma_v5_0_ip_block +ffffffff82ac40b8 r sdma_v5_0_ring_funcs +ffffffff82ac41d8 r sdma_v5_0_buffer_funcs +ffffffff82ac41f8 r sdma_v5_0_vm_pte_funcs +ffffffff82ac4218 r sdma_v5_0_trap_irq_funcs +ffffffff82ac4228 r sdma_v5_0_illegal_inst_irq_funcs +ffffffff82ac4240 r golden_settings_sdma_5 +ffffffff82ac4480 r golden_settings_sdma_nv10 +ffffffff82ac44b0 r golden_settings_sdma_nv14 +ffffffff82ac44e0 r golden_settings_sdma_5_sriov +ffffffff82ac46c0 r golden_settings_sdma_nv12 +ffffffff82ac4750 r golden_settings_sdma_cyan_skillfish +ffffffff82ac5000 R sdma_v5_2_ip_funcs +ffffffff82ac50a0 R sdma_v5_2_ip_block +ffffffff82ac50b8 r sdma_v5_2_ring_funcs +ffffffff82ac51d8 r sdma_v5_2_buffer_funcs +ffffffff82ac51f8 r sdma_v5_2_vm_pte_funcs +ffffffff82ac5218 r sdma_v5_2_trap_irq_funcs +ffffffff82ac5228 r sdma_v5_2_illegal_inst_irq_funcs +ffffffff82ac6000 R sdma_v6_0_ip_funcs +ffffffff82ac60a0 R sdma_v6_0_ip_block +ffffffff82ac60b8 r sdma_v6_0_ring_funcs +ffffffff82ac61d8 r sdma_v6_0_buffer_funcs +ffffffff82ac61f8 r sdma_v6_0_vm_pte_funcs +ffffffff82ac6218 r sdma_v6_0_trap_irq_funcs +ffffffff82ac6228 r sdma_v6_0_illegal_inst_irq_funcs +ffffffff82ac7000 r smu_v11_0_i2c_algo +ffffffff82ac7010 r smu_v11_0_i2c_i2c_lock_ops +ffffffff82ac7028 r smu_v11_0_i2c_control_quirks +ffffffff82ac8000 R smuio_v11_0_funcs +ffffffff82ac9000 R smuio_v11_0_6_funcs +ffffffff82aca000 R smuio_v13_0_funcs +ffffffff82acb000 R smuio_v13_0_6_funcs +ffffffff82acc000 R smuio_v9_0_funcs +ffffffff82acd000 r soc15_common_ip_funcs +ffffffff82acd0a0 R vega10_common_ip_block +ffffffff82acd0b8 r soc15_asic_funcs +ffffffff82acd170 r vega20_asic_funcs +ffffffff82acd230 r soc15_allowed_read_registers +ffffffff82acd3c0 r vega_video_codecs_encode +ffffffff82acd3d0 r vega_video_codecs_decode +ffffffff82acd3e0 r rv_video_codecs_decode +ffffffff82acd3f0 r rn_video_codecs_decode +ffffffff82acd400 r vega_video_codecs_encode_array +ffffffff82acd430 r vega_video_codecs_decode_array +ffffffff82acd4b0 r rv_video_codecs_decode_array +ffffffff82acd540 r rn_video_codecs_decode_array +ffffffff82ace000 r soc21_common_ip_funcs +ffffffff82ace0a0 R soc21_common_ip_block +ffffffff82ace0b8 r soc21_asic_funcs +ffffffff82ace170 r soc21_allowed_read_registers +ffffffff82ace2f0 r vcn_4_0_0_video_codecs_encode_vcn1 +ffffffff82ace300 r vcn_4_0_0_video_codecs_decode_vcn1 +ffffffff82ace310 r vcn_4_0_0_video_codecs_encode_vcn0 +ffffffff82ace320 r vcn_4_0_0_video_codecs_decode_vcn0 +ffffffff82ace330 r vcn_4_0_0_video_codecs_encode_array_vcn1 +ffffffff82ace360 r vcn_4_0_0_video_codecs_decode_array_vcn1 +ffffffff82ace3b0 r vcn_4_0_0_video_codecs_encode_array_vcn0 +ffffffff82ace3e0 r vcn_4_0_0_video_codecs_decode_array_vcn0 +ffffffff82acf000 r tonga_ih_ip_funcs +ffffffff82acf0a0 R tonga_ih_ip_block +ffffffff82acf0b8 r tonga_ih_funcs +ffffffff82ad0000 R umc_v6_0_funcs +ffffffff82ad1000 R umc_v6_1_channel_idx_tbl +ffffffff82ad1080 R umc_v6_1_ras_hw_ops +ffffffff82ad2000 R umc_v6_7_channel_idx_tbl_second +ffffffff82ad2080 R umc_v6_7_channel_idx_tbl_first +ffffffff82ad2100 R umc_v6_7_ras_hw_ops +ffffffff82ad3000 R umc_v8_10_channelnum_map_colbit_table +ffffffff82ad3040 R umc_v8_10_channel_idx_tbl +ffffffff82ad30a0 R umc_v8_10_ras_hw_ops +ffffffff82ad4000 R umc_v8_7_channel_idx_tbl +ffffffff82ad4040 R umc_v8_7_ras_hw_ops +ffffffff82ad5000 r uvd_v5_0_ip_funcs +ffffffff82ad50a0 R uvd_v5_0_ip_block +ffffffff82ad50b8 r uvd_v5_0_ring_funcs +ffffffff82ad51d8 r uvd_v5_0_irq_funcs +ffffffff82ad6000 r uvd_v6_0_ip_funcs +ffffffff82ad60a0 R uvd_v6_0_ip_block +ffffffff82ad60b8 R uvd_v6_2_ip_block +ffffffff82ad60d0 R uvd_v6_3_ip_block +ffffffff82ad60e8 r uvd_v6_0_ring_vm_funcs +ffffffff82ad6208 r uvd_v6_0_ring_phys_funcs +ffffffff82ad6328 r uvd_v6_0_enc_ring_vm_funcs +ffffffff82ad6448 r uvd_v6_0_irq_funcs +ffffffff82ad7000 R uvd_v7_0_ip_funcs +ffffffff82ad70a0 R uvd_v7_0_ip_block +ffffffff82ad70b8 r uvd_v7_0_ring_vm_funcs +ffffffff82ad71d8 r uvd_v7_0_enc_ring_vm_funcs +ffffffff82ad72f8 r uvd_v7_0_irq_funcs +ffffffff82ad8000 r vce_v3_0_ip_funcs +ffffffff82ad80a0 R vce_v3_0_ip_block +ffffffff82ad80b8 R vce_v3_1_ip_block +ffffffff82ad80d0 R vce_v3_4_ip_block +ffffffff82ad80e8 r vce_v3_0_ring_vm_funcs +ffffffff82ad8208 r vce_v3_0_ring_phys_funcs +ffffffff82ad8328 r vce_v3_0_irq_funcs +ffffffff82ad9000 R vce_v4_0_ip_funcs +ffffffff82ad90a0 R vce_v4_0_ip_block +ffffffff82ad90b8 r vce_v4_0_ring_vm_funcs +ffffffff82ad91d8 r vce_v4_0_irq_funcs +ffffffff82ada000 r vcn_v1_0_ip_funcs +ffffffff82ada0a0 R vcn_v1_0_ip_block +ffffffff82ada0b8 r vcn_v1_0_dec_ring_vm_funcs +ffffffff82ada1d8 r vcn_v1_0_enc_ring_vm_funcs +ffffffff82ada2f8 r vcn_v1_0_irq_funcs +ffffffff82adb000 r vcn_v2_0_ip_funcs +ffffffff82adb0a0 R vcn_v2_0_ip_block +ffffffff82adb0b8 r vcn_v2_0_dec_ring_vm_funcs +ffffffff82adb1d8 r vcn_v2_0_enc_ring_vm_funcs +ffffffff82adb2f8 r vcn_v2_0_irq_funcs +ffffffff82adc000 r vcn_v2_5_ip_funcs +ffffffff82adc0a0 R vcn_v2_5_ip_block +ffffffff82adc0b8 r vcn_v2_6_ip_funcs +ffffffff82adc158 R vcn_v2_6_ip_block +ffffffff82adc170 R vcn_v2_6_ras_hw_ops +ffffffff82adc1b0 r vcn_v2_5_dec_ring_vm_funcs +ffffffff82adc2d0 r vcn_v2_6_dec_ring_vm_funcs +ffffffff82adc3f0 r vcn_v2_5_enc_ring_vm_funcs +ffffffff82adc510 r vcn_v2_6_enc_ring_vm_funcs +ffffffff82adc630 r vcn_v2_5_irq_funcs +ffffffff82add000 r vcn_v3_0_ip_funcs +ffffffff82add0a0 R vcn_v3_0_ip_block +ffffffff82add0b8 r vcn_v3_0_dec_ring_vm_funcs +ffffffff82add1d8 r vcn_v3_0_enc_ring_vm_funcs +ffffffff82add2f8 r vcn_v3_0_irq_funcs +ffffffff82ade000 r vcn_v4_0_ip_funcs +ffffffff82ade0a0 R vcn_v4_0_ip_block +ffffffff82ade0b8 r vcn_v4_0_unified_ring_vm_funcs +ffffffff82ade1d8 r vcn_v4_0_irq_funcs +ffffffff82adf000 R vega10_ih_ip_funcs +ffffffff82adf0a0 R vega10_ih_ip_block +ffffffff82adf0b8 r vega10_ih_funcs +ffffffff82adf0d8 r vega10_ih_self_irq_funcs +ffffffff82ae0000 r GC_BASE +ffffffff82ae0064 r HDP_BASE +ffffffff82ae00c8 r MMHUB_BASE +ffffffff82ae012c r ATHUB_BASE +ffffffff82ae0190 r NBIO_BASE +ffffffff82ae01f4 r MP0_BASE +ffffffff82ae0258 r MP1_BASE +ffffffff82ae02bc r VCE_BASE +ffffffff82ae0320 r VCN_BASE +ffffffff82ae0384 r DF_BASE +ffffffff82ae03e8 r DCE_BASE +ffffffff82ae044c r OSSSYS_BASE +ffffffff82ae04b0 r SDMA0_BASE +ffffffff82ae0514 r SDMA1_BASE +ffffffff82ae0578 r SMUIO_BASE +ffffffff82ae05dc r PWR_BASE +ffffffff82ae0640 r NBIF_BASE +ffffffff82ae06a4 r THM_BASE +ffffffff82ae0708 r CLK_BASE +ffffffff82ae1000 R vega20_ih_ip_funcs +ffffffff82ae10a0 R vega20_ih_ip_block +ffffffff82ae10b8 r vega20_ih_funcs +ffffffff82ae10d8 r vega20_ih_self_irq_funcs +ffffffff82ae2000 r GC_BASE +ffffffff82ae2090 r HDP_BASE +ffffffff82ae2120 r MMHUB_BASE +ffffffff82ae21b0 r ATHUB_BASE +ffffffff82ae2240 r NBIO_BASE +ffffffff82ae22d0 r MP0_BASE +ffffffff82ae2360 r MP1_BASE +ffffffff82ae23f0 r UVD_BASE +ffffffff82ae2480 r VCE_BASE +ffffffff82ae2510 r DF_BASE +ffffffff82ae25a0 r DCE_BASE +ffffffff82ae2630 r OSSSYS_BASE +ffffffff82ae26c0 r SDMA0_BASE +ffffffff82ae2750 r SDMA1_BASE +ffffffff82ae27e0 r SMUIO_BASE +ffffffff82ae2870 r THM_BASE +ffffffff82ae2900 r CLK_BASE +ffffffff82ae2990 r UMC_BASE +ffffffff82ae2a20 r RSMU_BASE +ffffffff82ae3000 r vi_common_ip_block +ffffffff82ae3018 r vi_common_ip_funcs +ffffffff82ae30b8 r vi_asic_funcs +ffffffff82ae3170 r vi_allowed_read_registers +ffffffff82ae33d0 r topaz_video_codecs_encode +ffffffff82ae33e0 r topaz_video_codecs_decode +ffffffff82ae33f0 r tonga_video_codecs_encode +ffffffff82ae3400 r tonga_video_codecs_decode +ffffffff82ae3410 r polaris_video_codecs_encode +ffffffff82ae3420 r cz_video_codecs_decode +ffffffff82ae3430 r tonga_video_codecs_encode_array +ffffffff82ae3450 r tonga_video_codecs_decode_array +ffffffff82ae34a0 r polaris_video_codecs_encode_array +ffffffff82ae34d0 r cz_video_codecs_decode_array +ffffffff82ae3550 r iceland_mgcg_cgcg_init +ffffffff82ae3590 r fiji_mgcg_cgcg_init +ffffffff82ae35f0 r tonga_mgcg_cgcg_init +ffffffff82ae3650 r cz_mgcg_cgcg_init +ffffffff82ae3690 r stoney_mgcg_cgcg_init +ffffffff82ae4000 r amdgpu_dm_funcs +ffffffff82ae40a0 R dm_ip_block +ffffffff82ae40b8 R amdgpu_dm_encoder_helper_funcs +ffffffff82ae4120 r dm_display_funcs +ffffffff82ae4180 r hpd_disconnect_quirk_table +ffffffff82ae4ef0 r amdgpu_dm_mode_funcs +ffffffff82ae4f38 r amdgpu_dm_encoder_funcs +ffffffff82ae4f58 r amdgpu_dm_connector_funcs +ffffffff82ae4fd0 r amdgpu_dm_connector_helper_funcs +ffffffff82ae5020 r amdgpu_dm_i2c_algo +ffffffff82ae51f0 r add_fs_modes.common_rates +ffffffff82ae5220 r amdgpu_dm_backlight_ops +ffffffff82ae6000 r amdgpu_dm_crtc_funcs +ffffffff82ae60c0 r amdgpu_dm_crtc_helper_funcs +ffffffff82ae7000 r dm_dtn_log_begin.msg +ffffffff82ae700d r dm_dtn_log_end.msg +ffffffff82ae7018 r SYNAPTICS_DEVICE_ID +ffffffff82ae8000 r dm_crtc_irq_funcs +ffffffff82ae8010 r dm_vline0_irq_funcs +ffffffff82ae8020 r dm_dmub_outbox_irq_funcs +ffffffff82ae8030 r dm_vupdate_irq_funcs +ffffffff82ae8040 r dm_dmub_trace_irq_funcs +ffffffff82ae8050 r dm_pageflip_irq_funcs +ffffffff82ae8060 r dm_hpd_irq_funcs +ffffffff82ae9000 r amdgpu_dm_encoder_funcs +ffffffff82ae9020 r dm_mst_cbs +ffffffff82ae9030 r dm_dp_mst_connector_funcs +ffffffff82ae90a8 r dm_dp_mst_connector_helper_funcs +ffffffff82aea000 r dm_plane_funcs +ffffffff82aea068 r dm_plane_helper_funcs +ffffffff82aec000 r vbios_funcs +ffffffff82aed000 r vbios_funcs +ffffffff82af2000 r command_table_helper_funcs +ffffffff82af3000 r command_table_helper_funcs +ffffffff82af4000 r command_table_helper_funcs +ffffffff82af5000 r command_table_helper_funcs +ffffffff82af6000 r dce80_max_clks_by_state +ffffffff82af6028 r disp_clk_regs +ffffffff82af607c r disp_clk_shift +ffffffff82af6088 r disp_clk_mask +ffffffff82af7000 r dce110_max_clks_by_state +ffffffff82af7028 r disp_clk_regs +ffffffff82af707c r disp_clk_shift +ffffffff82af7088 r disp_clk_mask +ffffffff82af8000 r dce112_max_clks_by_state +ffffffff82af8028 r disp_clk_regs +ffffffff82af807c r disp_clk_shift +ffffffff82af8088 r disp_clk_mask +ffffffff82af9000 r dce120_max_clks_by_state +ffffffff82afa000 r clk_mgr_regs +ffffffff82afa054 r clk_mgr_shift +ffffffff82afa060 r clk_mgr_mask +ffffffff82afb000 r clk_mgr_regs +ffffffff82afb054 r clk_mgr_shift +ffffffff82afb060 r clk_mgr_mask +ffffffff82afc000 r clk_mgr_regs +ffffffff82afc054 r clk_mgr_shift +ffffffff82afc060 r clk_mgr_mask +ffffffff82afd000 r lpddr5_wm_table +ffffffff82afd0c0 r ddr5_wm_table +ffffffff82afe000 r lpddr5_wm_table +ffffffff82afe0c0 r ddr5_wm_table +ffffffff82aff000 r lpddr5_wm_table +ffffffff82aff0c0 r ddr5_wm_table +ffffffff82b00000 r lpddr5_wm_table +ffffffff82b000c0 r ddr4_wm_table +ffffffff82b01000 r clk_mgr_regs_dcn321 +ffffffff82b01054 r clk_mgr_shift_dcn321 +ffffffff82b01060 r clk_mgr_mask_dcn321 +ffffffff82b01084 r clk_mgr_regs_dcn32 +ffffffff82b010d8 r clk_mgr_shift_dcn32 +ffffffff82b010e4 r clk_mgr_mask_dcn32 +ffffffff82b02000 r DC_BUILD_ID +ffffffff82b04000 r output_csc_matrix +ffffffff82b040e0 r black_color_format +ffffffff82b05000 r DP_SINK_BRANCH_DEV_NAME_7580 +ffffffff82b06000 r DP_VGA_DONGLE_BRANCH_DEV_NAME +ffffffff82b06006 r DP_DVI_CONVERTER_ID_4 +ffffffff82b0600d r DP_DVI_CONVERTER_ID_5 +ffffffff82b07000 r DP_VGA_LVDS_CONVERTER_ID_2 +ffffffff82b07007 r DP_VGA_LVDS_CONVERTER_ID_3 +ffffffff82b07010 r dp_lt_fallbacks +ffffffff82b08000 r mandatory_dpcd_partitions +ffffffff82b0a000 r dce_funcs +ffffffff82b0b000 r funcs +ffffffff82b0c000 R video_optimized_pixel_rates +ffffffff82b0c1b0 r dce110_clk_src_funcs +ffffffff82b0c1d8 r dce112_clk_src_funcs +ffffffff82b0c200 r dcn20_clk_src_funcs +ffffffff82b0c228 r dcn3_clk_src_funcs +ffffffff82b0c250 r dcn31_clk_src_funcs +ffffffff82b0d000 r dce_funcs +ffffffff82b0d068 r dcn10_funcs +ffffffff82b0d0d0 r dcn20_funcs +ffffffff82b0d138 r dcn21_funcs +ffffffff82b0e000 r dce_ipp_funcs +ffffffff82b0f000 r dce110_lnk_enc_funcs +ffffffff82b10000 r dce_mi_funcs +ffffffff82b10090 r dce112_mi_funcs +ffffffff82b10120 r dce120_mi_funcs +ffffffff82b101b0 r pte_settings +ffffffff82b11000 r funcs +ffffffff82b12000 r dce_link_panel_cntl_funcs +ffffffff82b13000 r filter_3tap_16p_upscale +ffffffff82b13040 r filter_3tap_16p_116 +ffffffff82b13080 r filter_3tap_16p_149 +ffffffff82b130c0 r filter_3tap_16p_183 +ffffffff82b13100 r filter_3tap_64p_upscale +ffffffff82b131d0 r filter_3tap_64p_116 +ffffffff82b132a0 r filter_3tap_64p_149 +ffffffff82b13370 r filter_3tap_64p_183 +ffffffff82b13440 r filter_4tap_16p_upscale +ffffffff82b13490 r filter_4tap_16p_116 +ffffffff82b134e0 r filter_4tap_16p_149 +ffffffff82b13530 r filter_4tap_16p_183 +ffffffff82b13580 r filter_4tap_64p_upscale +ffffffff82b13690 r filter_4tap_64p_116 +ffffffff82b137a0 r filter_4tap_64p_149 +ffffffff82b138b0 r filter_4tap_64p_183 +ffffffff82b139c0 r filter_5tap_64p_upscale +ffffffff82b13b10 r filter_5tap_64p_116 +ffffffff82b13c60 r filter_5tap_64p_149 +ffffffff82b13db0 r filter_5tap_64p_183 +ffffffff82b13f00 r filter_6tap_64p_upscale +ffffffff82b14090 r filter_6tap_64p_116 +ffffffff82b14220 r filter_6tap_64p_149 +ffffffff82b143b0 r filter_6tap_64p_183 +ffffffff82b14540 r filter_7tap_64p_upscale +ffffffff82b14710 r filter_7tap_64p_116 +ffffffff82b148e0 r filter_7tap_64p_149 +ffffffff82b14ab0 r filter_7tap_64p_183 +ffffffff82b14c80 r filter_8tap_64p_upscale +ffffffff82b14e90 r filter_8tap_64p_116 +ffffffff82b150a0 r filter_8tap_64p_149 +ffffffff82b152b0 r filter_8tap_64p_183 +ffffffff82b154c0 r filter_2tap_16p +ffffffff82b154f0 r filter_2tap_64p +ffffffff82b16000 r audio_clock_info_table_48bpc +ffffffff82b16190 r audio_clock_info_table_36bpc +ffffffff82b16320 r audio_clock_info_table +ffffffff82b164e0 r dce110_str_enc_funcs +ffffffff82b17000 r global_color_matrix +ffffffff82b170a8 r dce_transform_funcs +ffffffff82b18000 r abm_funcs +ffffffff82b19000 r psr_funcs +ffffffff82b19040 r DP_SINK_DEVICE_STR_ID_1 +ffffffff82b19045 r DP_SINK_DEVICE_STR_ID_2 +ffffffff82b1a000 r reg_offsets +ffffffff82b1b000 r bios_regs +ffffffff82b1b008 r res_cap +ffffffff82b1b050 r clk_src_regs +ffffffff82b1b14c r dmcu_regs +ffffffff82b1b1a8 r dmcu_shift +ffffffff82b1b1bc r dmcu_mask +ffffffff82b1b208 r abm_regs +ffffffff82b1b248 r abm_shift +ffffffff82b1b25c r abm_mask +ffffffff82b1b2b0 r dce100_tg_offsets +ffffffff82b1b2f8 r plane_cap +ffffffff82b1b328 r res_create_funcs +ffffffff82b1b358 r dce100_res_pool_funcs +ffffffff82b1b440 r panel_cntl_regs +ffffffff82b1b460 r panel_cntl_shift +ffffffff82b1b470 r panel_cntl_mask +ffffffff82b1b4b0 r link_enc_regs +ffffffff82b1b870 r link_enc_aux_regs +ffffffff82b1b8c0 r link_enc_hpd_regs +ffffffff82b1b8d8 r link_enc_feature +ffffffff82b1b8e8 r cs_shift +ffffffff82b1b8f4 r cs_mask +ffffffff82b1b920 r mi_regs +ffffffff82b1bc38 r mi_shifts +ffffffff82b1bc80 r mi_masks +ffffffff82b1bda0 r ipp_regs +ffffffff82b1bf98 r ipp_shift +ffffffff82b1bfc0 r ipp_mask +ffffffff82b1c060 r xfm_regs +ffffffff82b1c600 r xfm_shift +ffffffff82b1c660 r xfm_mask +ffffffff82b1c7e0 r opp_regs +ffffffff82b1c930 r opp_shift +ffffffff82b1c95c r opp_mask +ffffffff82b1ca10 r aux_engine_regs +ffffffff82b1cb00 r aux_mask +ffffffff82b1cb60 r aux_shift +ffffffff82b1cb80 r i2c_hw_regs +ffffffff82b1ccd0 r i2c_shifts +ffffffff82b1ccfc r i2c_masks +ffffffff82b1cda0 r audio_regs +ffffffff82b1ced4 r audio_shift +ffffffff82b1ceec r audio_mask +ffffffff82b1cf30 r stream_enc_regs +ffffffff82b1d5dc r se_shift +ffffffff82b1d660 r se_mask +ffffffff82b1d864 r hwseq_reg +ffffffff82b1da80 r hwseq_shift +ffffffff82b1db00 r hwseq_mask +ffffffff82b1e000 r reg_offsets +ffffffff82b1e018 r dce110_compressor_funcs +ffffffff82b1f000 r dce110_funcs +ffffffff82b1f2c0 r dce110_private_funcs +ffffffff82b20000 r dce110_mem_input_v_funcs +ffffffff82b20090 r dvmm_Hw_Setting_1DTiling +ffffffff82b20120 r dvmm_Hw_Setting_2DTiling +ffffffff82b201b0 r dvmm_Hw_Setting_Linear +ffffffff82b21000 r global_color_matrix +ffffffff82b210b0 r input_csc_matrix +ffffffff82b22000 r funcs +ffffffff82b23000 r bios_regs +ffffffff82b23008 r dce110_res_pool_funcs +ffffffff82b230f0 r clk_src_regs +ffffffff82b231ec r dmcu_regs +ffffffff82b23248 r dmcu_shift +ffffffff82b2325c r dmcu_mask +ffffffff82b232a8 r abm_regs +ffffffff82b232e8 r abm_shift +ffffffff82b232fc r abm_mask +ffffffff82b23350 r dce110_tg_offsets +ffffffff82b23398 r res_create_funcs +ffffffff82b233c8 r plane_cap +ffffffff82b233f4 r underlay_plane_cap +ffffffff82b23420 r stoney_resource_cap +ffffffff82b2345c r carrizo_resource_cap +ffffffff82b234a0 r panel_cntl_regs +ffffffff82b234c0 r panel_cntl_shift +ffffffff82b234d0 r panel_cntl_mask +ffffffff82b23510 r link_enc_regs +ffffffff82b238d0 r link_enc_aux_regs +ffffffff82b23920 r link_enc_hpd_regs +ffffffff82b23938 r link_enc_feature +ffffffff82b23948 r cs_shift +ffffffff82b23954 r cs_mask +ffffffff82b23980 r mi_regs +ffffffff82b23b0c r mi_shifts +ffffffff82b23b54 r mi_masks +ffffffff82b23c70 r ipp_regs +ffffffff82b23d6c r ipp_shift +ffffffff82b23d94 r ipp_mask +ffffffff82b23e30 r xfm_regs +ffffffff82b24100 r xfm_shift +ffffffff82b24160 r xfm_mask +ffffffff82b242e0 r opp_regs +ffffffff82b24430 r opp_shift +ffffffff82b2445c r opp_mask +ffffffff82b24510 r aux_engine_regs +ffffffff82b24600 r aux_mask +ffffffff82b24660 r aux_shift +ffffffff82b24680 r i2c_hw_regs +ffffffff82b247d0 r i2c_shifts +ffffffff82b247fc r i2c_masks +ffffffff82b248a0 r audio_regs +ffffffff82b249d4 r audio_shift +ffffffff82b249ec r audio_mask +ffffffff82b24a30 r stream_enc_regs +ffffffff82b24d0c r se_shift +ffffffff82b24d90 r se_mask +ffffffff82b24f94 r hwseq_stoney_reg +ffffffff82b251b0 r hwseq_cz_reg +ffffffff82b253cc r hwseq_shift +ffffffff82b2544c r hwseq_mask +ffffffff82b26000 r dce110_tg_funcs +ffffffff82b27000 r dce110_tg_v_funcs +ffffffff82b28000 r dce110_xfmv_funcs +ffffffff82b29000 r reg_offsets +ffffffff82b2a000 r reg_offsets +ffffffff82b2b000 r bios_regs +ffffffff82b2b010 r clk_src_regs +ffffffff82b2b208 r dmcu_regs +ffffffff82b2b264 r dmcu_shift +ffffffff82b2b278 r dmcu_mask +ffffffff82b2b2c4 r abm_regs +ffffffff82b2b304 r abm_shift +ffffffff82b2b318 r abm_mask +ffffffff82b2b360 r dce112_tg_offsets +ffffffff82b2b3a8 r res_create_funcs +ffffffff82b2b3d8 r plane_cap +ffffffff82b2b404 r polaris_11_resource_cap +ffffffff82b2b440 r polaris_10_resource_cap +ffffffff82b2b480 r dce112_res_pool_funcs +ffffffff82b2b560 r panel_cntl_regs +ffffffff82b2b580 r panel_cntl_shift +ffffffff82b2b590 r panel_cntl_mask +ffffffff82b2b5d0 r link_enc_regs +ffffffff82b2b990 r link_enc_aux_regs +ffffffff82b2b9e0 r link_enc_hpd_regs +ffffffff82b2b9f8 r link_enc_feature +ffffffff82b2ba08 r cs_shift +ffffffff82b2ba14 r cs_mask +ffffffff82b2ba40 r mi_regs +ffffffff82b2bd58 r mi_shifts +ffffffff82b2bda0 r mi_masks +ffffffff82b2bec0 r ipp_regs +ffffffff82b2c0b8 r ipp_shift +ffffffff82b2c0e0 r ipp_mask +ffffffff82b2c180 r xfm_regs +ffffffff82b2c720 r xfm_shift +ffffffff82b2c780 r xfm_mask +ffffffff82b2c900 r opp_regs +ffffffff82b2ca50 r opp_shift +ffffffff82b2ca7c r opp_mask +ffffffff82b2cb30 r aux_engine_regs +ffffffff82b2cc20 r aux_mask +ffffffff82b2cc80 r aux_shift +ffffffff82b2cca0 r i2c_hw_regs +ffffffff82b2cdf0 r i2c_shifts +ffffffff82b2ce1c r i2c_masks +ffffffff82b2cec0 r audio_regs +ffffffff82b2cfc8 r audio_shift +ffffffff82b2cfe0 r audio_mask +ffffffff82b2d020 r stream_enc_regs +ffffffff82b2d5d8 r se_shift +ffffffff82b2d65c r se_mask +ffffffff82b2d860 r hwseq_reg +ffffffff82b2da7c r hwseq_shift +ffffffff82b2dafc r hwseq_mask +ffffffff82b2e000 r bios_regs +ffffffff82b2e008 r res_cap +ffffffff82b2e048 r dce120_res_pool_funcs +ffffffff82b2e128 r debug_defaults +ffffffff82b2e2a0 r clk_src_regs +ffffffff82b2e498 r dmcu_regs +ffffffff82b2e4f4 r dmcu_shift +ffffffff82b2e508 r dmcu_mask +ffffffff82b2e554 r abm_regs +ffffffff82b2e594 r abm_shift +ffffffff82b2e5a8 r abm_mask +ffffffff82b2e5f0 r dce120_tg_offsets +ffffffff82b2e638 r dce121_res_create_funcs +ffffffff82b2e668 r res_create_funcs +ffffffff82b2e698 r plane_cap +ffffffff82b2e6d0 r panel_cntl_regs +ffffffff82b2e6f0 r panel_cntl_shift +ffffffff82b2e700 r panel_cntl_mask +ffffffff82b2e740 r link_enc_regs +ffffffff82b2eb00 r link_enc_aux_regs +ffffffff82b2eb50 r link_enc_hpd_regs +ffffffff82b2eb68 r link_enc_feature +ffffffff82b2eb78 r cs_shift +ffffffff82b2eb84 r cs_mask +ffffffff82b2ebb0 r mi_regs +ffffffff82b2eec8 r mi_shifts +ffffffff82b2ef10 r mi_masks +ffffffff82b2f030 r ipp_regs +ffffffff82b2f228 r ipp_shift +ffffffff82b2f250 r ipp_mask +ffffffff82b2f2f0 r xfm_regs +ffffffff82b2f890 r xfm_shift +ffffffff82b2f8f0 r xfm_mask +ffffffff82b2fa70 r opp_regs +ffffffff82b2fbc0 r opp_shift +ffffffff82b2fbec r opp_mask +ffffffff82b2fca0 r aux_engine_regs +ffffffff82b2fd90 r aux_mask +ffffffff82b2fdf0 r aux_shift +ffffffff82b2fe10 r i2c_hw_regs +ffffffff82b2ff60 r i2c_shifts +ffffffff82b2ff8c r i2c_masks +ffffffff82b30030 r audio_regs +ffffffff82b30164 r audio_shift +ffffffff82b3017c r audio_mask +ffffffff82b301c0 r stream_enc_regs +ffffffff82b30778 r se_shift +ffffffff82b307fc r se_mask +ffffffff82b30a00 r dce121_hwseq_reg +ffffffff82b30c1c r dce121_hwseq_shift +ffffffff82b30c9c r dce121_hwseq_mask +ffffffff82b30e90 r hwseq_reg +ffffffff82b310ac r hwseq_shift +ffffffff82b3112c r hwseq_mask +ffffffff82b32000 r dce120_tg_funcs +ffffffff82b33000 r bios_regs +ffffffff82b33008 r res_cap +ffffffff82b33048 r dce80_res_pool_funcs +ffffffff82b33130 r clk_src_regs +ffffffff82b3322c r dmcu_regs +ffffffff82b33288 r dmcu_shift +ffffffff82b3329c r dmcu_mask +ffffffff82b332e8 r abm_regs +ffffffff82b33328 r abm_shift +ffffffff82b3333c r abm_mask +ffffffff82b33390 r dce80_tg_offsets +ffffffff82b333d8 r plane_cap +ffffffff82b33408 r res_create_funcs +ffffffff82b33440 r panel_cntl_regs +ffffffff82b33460 r panel_cntl_shift +ffffffff82b33470 r panel_cntl_mask +ffffffff82b334b0 r link_enc_regs +ffffffff82b33870 r link_enc_aux_regs +ffffffff82b338c0 r link_enc_hpd_regs +ffffffff82b338d8 r link_enc_feature +ffffffff82b338e8 r cs_shift +ffffffff82b338f4 r cs_mask +ffffffff82b33920 r mi_regs +ffffffff82b33c38 r mi_shifts +ffffffff82b33c80 r mi_masks +ffffffff82b33da0 r ipp_regs +ffffffff82b33f98 r ipp_shift +ffffffff82b33fc0 r ipp_mask +ffffffff82b34060 r xfm_regs +ffffffff82b34600 r xfm_shift +ffffffff82b34660 r xfm_mask +ffffffff82b347e0 r opp_regs +ffffffff82b34930 r opp_shift +ffffffff82b3495c r opp_mask +ffffffff82b34a10 r aux_engine_regs +ffffffff82b34b00 r aux_mask +ffffffff82b34b60 r aux_shift +ffffffff82b34b80 r i2c_hw_regs +ffffffff82b34cd0 r i2c_shifts +ffffffff82b34cfc r i2c_masks +ffffffff82b34da0 r audio_regs +ffffffff82b34ed4 r audio_shift +ffffffff82b34eec r audio_mask +ffffffff82b34f30 r stream_enc_regs +ffffffff82b355dc r se_shift +ffffffff82b35660 r se_mask +ffffffff82b35864 r hwseq_reg +ffffffff82b35a80 r hwseq_shift +ffffffff82b35b00 r hwseq_mask +ffffffff82b35cf4 r res_cap_81 +ffffffff82b35d30 r res_cap_83 +ffffffff82b36000 r reg_offsets +ffffffff82b36048 r dce80_tg_funcs +ffffffff82b37000 r dcn10_dpp_funcs +ffffffff82b38000 r dpp_input_csc_matrix +ffffffff82b3a000 r hubbub1_funcs +ffffffff82b3b000 r dcn10_hubp_funcs +ffffffff82b3c000 r reduceSizeAndFraction.prime_numbers +ffffffff82b3e000 r dcn10_funcs +ffffffff82b3e2c0 r dcn10_private_funcs +ffffffff82b3f000 r dcn10_ipp_funcs +ffffffff82b3f048 r dcn20_ipp_funcs +ffffffff82b40000 r dcn10_lnk_enc_funcs +ffffffff82b41000 r dcn10_mpc_funcs +ffffffff82b42000 r dcn10_opp_funcs +ffffffff82b43000 r dcn10_tg_funcs +ffffffff82b44000 r bios_regs +ffffffff82b44008 r rv2_res_cap +ffffffff82b44044 r res_cap +ffffffff82b44080 r debug_defaults_drv +ffffffff82b441f8 r debug_defaults_diags +ffffffff82b44370 r clk_src_regs +ffffffff82b444c0 r dmcu_regs +ffffffff82b4451c r dmcu_shift +ffffffff82b44530 r dmcu_mask +ffffffff82b4457c r abm_regs +ffffffff82b445bc r abm_shift +ffffffff82b445d0 r abm_mask +ffffffff82b44618 r res_create_funcs +ffffffff82b44648 r res_create_maximus_funcs +ffffffff82b44678 r plane_cap +ffffffff82b446a8 r dcn10_res_pool_funcs +ffffffff82b44790 r panel_cntl_regs +ffffffff82b447b0 r panel_cntl_shift +ffffffff82b447c0 r panel_cntl_mask +ffffffff82b44800 r link_enc_regs +ffffffff82b44d10 r link_enc_aux_regs +ffffffff82b44d50 r link_enc_hpd_regs +ffffffff82b44d60 r le_shift +ffffffff82b44e50 r le_mask +ffffffff82b45208 r link_enc_feature +ffffffff82b45218 r cs_shift +ffffffff82b45224 r cs_mask +ffffffff82b45250 r hubp_regs +ffffffff82b45900 r hubp_shift +ffffffff82b459c4 r hubp_mask +ffffffff82b45cd0 r ipp_regs +ffffffff82b45db0 r ipp_shift +ffffffff82b45dcc r ipp_mask +ffffffff82b45e40 r tf_regs +ffffffff82b46da0 r tf_shift +ffffffff82b47008 r tf_mask +ffffffff82b479a0 r opp_regs +ffffffff82b47a70 r opp_shift +ffffffff82b47a90 r opp_mask +ffffffff82b47b10 r tg_regs +ffffffff82b48010 r tg_shift +ffffffff82b480d0 r tg_mask +ffffffff82b483d0 r aux_engine_regs +ffffffff82b484c0 r aux_mask +ffffffff82b48520 r aux_shift +ffffffff82b48540 r i2c_hw_regs +ffffffff82b48690 r i2c_shifts +ffffffff82b486bc r i2c_masks +ffffffff82b48760 r mpc_regs +ffffffff82b48880 r mpc_shift +ffffffff82b48898 r mpc_mask +ffffffff82b488f4 r hubbub_reg +ffffffff82b48a68 r hubbub_shift +ffffffff82b48af0 r hubbub_mask +ffffffff82b48d10 r audio_regs +ffffffff82b48dc0 r audio_shift +ffffffff82b48dd8 r audio_mask +ffffffff82b48e20 r stream_enc_regs +ffffffff82b49370 r se_shift +ffffffff82b4944c r se_mask +ffffffff82b497b8 r hwseq_reg +ffffffff82b499d4 r hwseq_shift +ffffffff82b49a54 r hwseq_mask +ffffffff82b4a000 r audio_clock_info_table_48bpc +ffffffff82b4a190 r audio_clock_info_table_36bpc +ffffffff82b4a320 r audio_clock_info_table +ffffffff82b4a4e0 r dcn10_str_enc_funcs +ffffffff82b4b000 r dccg2_funcs +ffffffff82b4d000 r dpp_input_csc_matrix +ffffffff82b4e000 R dcn20_dsc_funcs +ffffffff82b4f000 R dcn20_dwbc_funcs +ffffffff82b50000 r filter_12tap_16p_upscale +ffffffff82b500e0 r filter_12tap_16p_117 +ffffffff82b501c0 r filter_12tap_16p_150 +ffffffff82b502a0 r filter_12tap_16p_183 +ffffffff82b50380 r filter_11tap_16p_upscale +ffffffff82b50450 r filter_11tap_16p_117 +ffffffff82b50520 r filter_11tap_16p_150 +ffffffff82b505f0 r filter_11tap_16p_183 +ffffffff82b506c0 r filter_10tap_16p_upscale +ffffffff82b50780 r filter_10tap_16p_117 +ffffffff82b50840 r filter_10tap_16p_150 +ffffffff82b50900 r filter_10tap_16p_183 +ffffffff82b509c0 r filter_9tap_16p_upscale +ffffffff82b50a70 r filter_9tap_16p_117 +ffffffff82b50b20 r filter_9tap_16p_150 +ffffffff82b50bd0 r filter_9tap_16p_183 +ffffffff82b50c80 r filter_8tap_16p_upscale +ffffffff82b50d10 r filter_8tap_16p_117 +ffffffff82b50da0 r filter_8tap_16p_150 +ffffffff82b50e30 r filter_8tap_16p_183 +ffffffff82b50ec0 r filter_7tap_16p_upscale +ffffffff82b50f40 r filter_7tap_16p_117 +ffffffff82b50fc0 r filter_7tap_16p_150 +ffffffff82b51040 r filter_7tap_16p_183 +ffffffff82b510c0 r filter_6tap_16p_upscale +ffffffff82b51130 r filter_6tap_16p_117 +ffffffff82b511a0 r filter_6tap_16p_150 +ffffffff82b51210 r filter_6tap_16p_183 +ffffffff82b51280 r filter_5tap_16p_upscale +ffffffff82b512e0 r filter_5tap_16p_117 +ffffffff82b51340 r filter_5tap_16p_150 +ffffffff82b513a0 r filter_5tap_16p_183 +ffffffff82b51400 r filter_4tap_16p_upscale +ffffffff82b51450 r filter_4tap_16p_117 +ffffffff82b514a0 r filter_4tap_16p_150 +ffffffff82b514f0 r filter_4tap_16p_183 +ffffffff82b51540 r filter_3tap_16p_upscale +ffffffff82b51580 r filter_3tap_16p_117 +ffffffff82b515c0 r filter_3tap_16p_150 +ffffffff82b51600 r filter_3tap_16p_183 +ffffffff82b52000 r hubbub2_funcs +ffffffff82b53000 r dcn20_funcs +ffffffff82b532c0 r dcn20_private_funcs +ffffffff82b54000 r dcn2_mpll_cfg +ffffffff82b54190 r dcn20_link_enc_funcs +ffffffff82b55000 R dcn20_mmhubbub_funcs +ffffffff82b56000 R dcn20_mpc_funcs +ffffffff82b57000 r tf_regs +ffffffff82b58920 r tf_shift +ffffffff82b58ba4 r tf_mask +ffffffff82b595c0 r ipp_regs +ffffffff82b59710 r ipp_shift +ffffffff82b5972c r ipp_mask +ffffffff82b597a0 r opp_regs +ffffffff82b599b0 r opp_shift +ffffffff82b599e8 r opp_mask +ffffffff82b59ac0 r aux_engine_regs +ffffffff82b59bb0 r aux_mask +ffffffff82b59c10 r aux_shift +ffffffff82b59c30 r i2c_hw_regs +ffffffff82b59d80 r i2c_shifts +ffffffff82b59dac r i2c_masks +ffffffff82b59e50 r mpc_regs +ffffffff82b5a398 r mpc_shift +ffffffff82b5a3e0 r mpc_mask +ffffffff82b5a4f4 r hubbub_reg +ffffffff82b5a668 r hubbub_shift +ffffffff82b5a6f0 r hubbub_mask +ffffffff82b5a90c r res_cap_nv10 +ffffffff82b5a950 r vmid_regs +ffffffff82b5ab10 r vmid_shifts +ffffffff82b5ab18 r vmid_masks +ffffffff82b5ab40 r tg_regs +ffffffff82b5b2c0 r tg_shift +ffffffff82b5b380 r tg_mask +ffffffff82b5b680 r link_enc_regs +ffffffff82b5be20 r link_enc_aux_regs +ffffffff82b5be80 r link_enc_hpd_regs +ffffffff82b5be98 r le_shift +ffffffff82b5bf88 r le_mask +ffffffff82b5c340 r stream_enc_regs +ffffffff82b5cb38 r se_shift +ffffffff82b5cc14 r se_mask +ffffffff82b5cf80 r hwseq_reg +ffffffff82b5d19c r hwseq_shift +ffffffff82b5d21c r hwseq_mask +ffffffff82b5d410 r dsc_regs +ffffffff82b5d8a8 r dsc_shift +ffffffff82b5d960 r dsc_mask +ffffffff82b5dc40 r hubp_regs +ffffffff82b5e888 r hubp_shift +ffffffff82b5e984 r hubp_mask +ffffffff82b5ed80 r dwbc20_regs +ffffffff82b5ee38 r dwbc20_shift +ffffffff82b5eeb8 r dwbc20_mask +ffffffff82b5f0b0 r mcif_wb20_regs +ffffffff82b5f190 r mcif_wb20_shift +ffffffff82b5f230 r mcif_wb20_mask +ffffffff82b5f4b0 r link_enc_feature +ffffffff82b5f4c0 r bios_regs +ffffffff82b5f4c8 r dcn20_res_pool_funcs +ffffffff82b5f5a8 r res_cap_nv14 +ffffffff82b5f5e8 r debug_defaults_drv +ffffffff82b5f760 r debug_defaults_diags +ffffffff82b5f8e0 r clk_src_regs +ffffffff82b5fad8 r dccg_regs +ffffffff82b5fbc4 r dccg_shift +ffffffff82b5fc5c r dccg_mask +ffffffff82b5feb8 r dmcu_regs +ffffffff82b5ff14 r dmcu_shift +ffffffff82b5ff28 r dmcu_mask +ffffffff82b5ff74 r abm_regs +ffffffff82b5ffb4 r abm_shift +ffffffff82b5ffc8 r abm_mask +ffffffff82b60010 r res_create_funcs +ffffffff82b60040 r res_create_maximus_funcs +ffffffff82b60070 r plane_cap +ffffffff82b600a0 r panel_cntl_regs +ffffffff82b600c0 r panel_cntl_shift +ffffffff82b600d0 r panel_cntl_mask +ffffffff82b6010c r cs_shift +ffffffff82b60118 r cs_mask +ffffffff82b60140 r audio_regs +ffffffff82b60274 r audio_shift +ffffffff82b6028c r audio_mask +ffffffff82b61000 r dcn20_str_enc_funcs +ffffffff82b62000 r dccg201_funcs +ffffffff82b63000 r hubbub201_funcs +ffffffff82b64000 r dcn201_funcs +ffffffff82b642c0 r dcn201_private_funcs +ffffffff82b65000 r dcn201_link_enc_funcs +ffffffff82b66000 R dcn201_mpc_funcs +ffffffff82b67000 r bios_regs +ffffffff82b67008 r res_cap_dnc201 +ffffffff82b67048 r debug_defaults_drv +ffffffff82b671c0 r clk_src_regs +ffffffff82b67268 r dccg_regs +ffffffff82b67354 r dccg_shift +ffffffff82b673ec r dccg_mask +ffffffff82b67648 r res_create_funcs +ffffffff82b67678 r res_create_maximus_funcs +ffffffff82b676a8 r plane_cap +ffffffff82b676e0 r link_enc_regs +ffffffff82b67970 r link_enc_aux_regs +ffffffff82b67990 r link_enc_hpd_regs +ffffffff82b67998 r le_shift +ffffffff82b67a88 r le_mask +ffffffff82b67e40 r link_enc_feature +ffffffff82b67e50 r cs_shift +ffffffff82b67e5c r cs_mask +ffffffff82b67e90 r hubp_regs +ffffffff82b68620 r hubp_shift +ffffffff82b686f8 r hubp_mask +ffffffff82b68a60 r ipp_regs +ffffffff82b68b40 r ipp_shift +ffffffff82b68b5c r ipp_mask +ffffffff82b68bd0 r tf_regs +ffffffff82b69c10 r tf_shift +ffffffff82b69e94 r tf_mask +ffffffff82b6a8b0 r opp_regs +ffffffff82b6a960 r opp_shift +ffffffff82b6a998 r opp_mask +ffffffff82b6aa70 r aux_engine_regs +ffffffff82b6aac0 r aux_mask +ffffffff82b6ab20 r aux_shift +ffffffff82b6ab40 r i2c_hw_regs +ffffffff82b6abb0 r i2c_shifts +ffffffff82b6abdc r i2c_masks +ffffffff82b6ac80 r tg_regs +ffffffff82b6af00 r tg_shift +ffffffff82b6afc0 r tg_mask +ffffffff82b6b2c0 r mpc_regs +ffffffff82b6b808 r mpc_shift +ffffffff82b6b854 r mpc_mask +ffffffff82b6b97c r hubbub_reg +ffffffff82b6baf0 r hubbub_shift +ffffffff82b6bb78 r hubbub_mask +ffffffff82b6bda0 r audio_regs +ffffffff82b6bdf8 r audio_shift +ffffffff82b6be10 r audio_mask +ffffffff82b6be50 r stream_enc_regs +ffffffff82b6c0f8 r se_shift +ffffffff82b6c1d4 r se_mask +ffffffff82b6c540 r hwseq_reg +ffffffff82b6c75c r hwseq_shift +ffffffff82b6c7dc r hwseq_mask +ffffffff82b6d000 r dccg21_funcs +ffffffff82b6e000 r hubbub21_funcs +ffffffff82b6f000 r dcn21_funcs +ffffffff82b6f2c0 r dcn21_private_funcs +ffffffff82b70000 r dcn21_mpll_cfg_ref +ffffffff82b70190 r dcn21_link_enc_funcs +ffffffff82b71000 r bios_regs +ffffffff82b71008 r res_cap_rn +ffffffff82b71048 r dcn21_res_pool_funcs +ffffffff82b71128 r debug_defaults_drv +ffffffff82b712a0 r debug_defaults_diags +ffffffff82b71420 r clk_src_regs +ffffffff82b715c4 r dccg_regs +ffffffff82b716b0 r dccg_shift +ffffffff82b71748 r dccg_mask +ffffffff82b719a4 r dmcu_regs +ffffffff82b71a00 r dmcu_shift +ffffffff82b71a14 r dmcu_mask +ffffffff82b71a60 r abm_regs +ffffffff82b71aa0 r abm_shift +ffffffff82b71ab4 r abm_mask +ffffffff82b71b00 r res_create_funcs +ffffffff82b71b30 r res_create_maximus_funcs +ffffffff82b71b60 r plane_cap +ffffffff82b71b90 r panel_cntl_regs +ffffffff82b71bb0 r panel_cntl_shift +ffffffff82b71bc0 r panel_cntl_mask +ffffffff82b71c00 r link_enc_regs +ffffffff82b72260 r link_enc_aux_regs +ffffffff82b722b0 r link_enc_hpd_regs +ffffffff82b722c4 r le_shift +ffffffff82b723b4 r le_mask +ffffffff82b7276c r link_enc_feature +ffffffff82b7277c r panel_config_defaults +ffffffff82b727b0 r cs_shift +ffffffff82b727bc r cs_mask +ffffffff82b727f0 r hubp_regs +ffffffff82b73020 r hubp_shift +ffffffff82b7311c r hubp_mask +ffffffff82b73510 r ipp_regs +ffffffff82b735f0 r ipp_shift +ffffffff82b7360c r ipp_mask +ffffffff82b73680 r tf_regs +ffffffff82b74740 r tf_shift +ffffffff82b749c4 r tf_mask +ffffffff82b753e0 r opp_regs +ffffffff82b755f0 r opp_shift +ffffffff82b75628 r opp_mask +ffffffff82b75700 r tg_regs +ffffffff82b75c00 r tg_shift +ffffffff82b75cc0 r tg_mask +ffffffff82b75fc0 r aux_engine_regs +ffffffff82b76088 r aux_mask +ffffffff82b760e8 r aux_shift +ffffffff82b76100 r i2c_hw_regs +ffffffff82b76218 r i2c_shifts +ffffffff82b76244 r i2c_masks +ffffffff82b762e8 r mpc_regs +ffffffff82b76830 r mpc_shift +ffffffff82b76878 r mpc_mask +ffffffff82b7698c r hubbub_reg +ffffffff82b76b00 r hubbub_shift +ffffffff82b76b88 r hubbub_mask +ffffffff82b76db0 r vmid_regs +ffffffff82b76f70 r vmid_shifts +ffffffff82b76f78 r vmid_masks +ffffffff82b76fa0 r dsc_regs +ffffffff82b77438 r dsc_shift +ffffffff82b774f0 r dsc_mask +ffffffff82b777d0 r audio_regs +ffffffff82b778d8 r audio_shift +ffffffff82b778f0 r audio_mask +ffffffff82b77930 r stream_enc_regs +ffffffff82b77fd4 r se_shift +ffffffff82b780b0 r se_mask +ffffffff82b7841c r hwseq_reg +ffffffff82b78638 r hwseq_shift +ffffffff82b786b8 r hwseq_mask +ffffffff82b79000 r dccg3_funcs +ffffffff82b7a000 r dcn30_link_enc_funcs +ffffffff82b7b000 r dcn30_str_enc_funcs +ffffffff82b7c000 r dpp_input_csc_matrix +ffffffff82b7d000 R dcn30_dwbc_funcs +ffffffff82b7e000 r hubbub30_funcs +ffffffff82b80000 r dcn30_funcs +ffffffff82b802c0 r dcn30_private_funcs +ffffffff82b81000 R dcn30_mmhubbub_funcs +ffffffff82b82000 R dcn30_mpc_funcs +ffffffff82b83000 r bios_regs +ffffffff82b83008 r res_cap_dcn3 +ffffffff82b83048 r debug_defaults_drv +ffffffff82b831c0 r debug_defaults_diags +ffffffff82b83340 r clk_src_regs +ffffffff82b83538 r dccg_regs +ffffffff82b83624 r dccg_shift +ffffffff82b836bc r dccg_mask +ffffffff82b83920 r abm_regs +ffffffff82b83aa0 r abm_shift +ffffffff82b83ab4 r abm_mask +ffffffff82b83b00 r res_create_funcs +ffffffff82b83b30 r res_create_maximus_funcs +ffffffff82b83b60 r plane_cap +ffffffff82b83b90 r dcn30_res_pool_funcs +ffffffff82b83c70 r panel_cntl_regs +ffffffff82b83c90 r panel_cntl_shift +ffffffff82b83ca0 r panel_cntl_mask +ffffffff82b83ce0 r link_enc_regs +ffffffff82b84480 r link_enc_aux_regs +ffffffff82b844e0 r link_enc_hpd_regs +ffffffff82b844f8 r le_shift +ffffffff82b845e8 r le_mask +ffffffff82b849a0 r link_enc_feature +ffffffff82b849b0 r cs_shift +ffffffff82b849bc r cs_mask +ffffffff82b849e4 r hubbub_reg +ffffffff82b84b58 r hubbub_shift +ffffffff82b84be0 r hubbub_mask +ffffffff82b84e00 r vmid_regs +ffffffff82b84fc0 r vmid_shifts +ffffffff82b84fc8 r vmid_masks +ffffffff82b84ff0 r hubp_regs +ffffffff82b85c38 r hubp_shift +ffffffff82b85d34 r hubp_mask +ffffffff82b86130 r dpp_regs +ffffffff82b880b0 r tf_shift +ffffffff82b88380 r tf_mask +ffffffff82b88ec0 r opp_regs +ffffffff82b890d0 r opp_shift +ffffffff82b89108 r opp_mask +ffffffff82b891e0 r optc_regs +ffffffff82b89960 r optc_shift +ffffffff82b89a20 r optc_mask +ffffffff82b89d20 r mpc_regs +ffffffff82b8b50c r mpc_shift +ffffffff82b8b5e8 r mpc_mask +ffffffff82b8b960 r dsc_regs +ffffffff82b8bdf8 r dsc_shift +ffffffff82b8beb0 r dsc_mask +ffffffff82b8c190 r dwbc30_regs +ffffffff82b8c36c r dwbc30_shift +ffffffff82b8c4a0 r dwbc30_mask +ffffffff82b8c970 r mcif_wb30_regs +ffffffff82b8ca6c r mcif_wb30_shift +ffffffff82b8cb18 r mcif_wb30_mask +ffffffff82b8cdd0 r aux_engine_regs +ffffffff82b8cec0 r aux_mask +ffffffff82b8cf20 r aux_shift +ffffffff82b8cf40 r i2c_hw_regs +ffffffff82b8d090 r i2c_shifts +ffffffff82b8d0bc r i2c_masks +ffffffff82b8d160 r audio_regs +ffffffff82b8d294 r audio_shift +ffffffff82b8d2ac r audio_mask +ffffffff82b8d2f0 r stream_enc_regs +ffffffff82b8dae8 r se_shift +ffffffff82b8dbc4 r se_mask +ffffffff82b8df30 r vpg_regs +ffffffff82b8dfbc r vpg_shift +ffffffff82b8dfe4 r vpg_mask +ffffffff82b8e080 r afmt_regs +ffffffff82b8e17c r afmt_shift +ffffffff82b8e190 r afmt_mask +ffffffff82b8e1d4 r hwseq_reg +ffffffff82b8e3f0 r hwseq_shift +ffffffff82b8e470 r hwseq_mask +ffffffff82b8f000 r dccg301_funcs +ffffffff82b90000 r dcn301_link_enc_funcs +ffffffff82b91000 r hubbub301_funcs +ffffffff82b92000 r dcn301_funcs +ffffffff82b922c0 r dcn301_private_funcs +ffffffff82b93000 r dcn301_link_panel_cntl_funcs +ffffffff82b94000 r bios_regs +ffffffff82b94008 r debug_defaults_drv +ffffffff82b94180 r debug_defaults_diags +ffffffff82b94300 r clk_src_regs +ffffffff82b94450 r dccg_regs +ffffffff82b9453c r dccg_shift +ffffffff82b945d4 r dccg_mask +ffffffff82b94830 r abm_regs +ffffffff82b94930 r abm_shift +ffffffff82b94944 r abm_mask +ffffffff82b94990 r res_create_funcs +ffffffff82b949c0 r res_create_maximus_funcs +ffffffff82b949f0 r plane_cap +ffffffff82b94a20 r panel_cntl_regs +ffffffff82b94a60 r panel_cntl_shift +ffffffff82b94a70 r panel_cntl_mask +ffffffff82b94ab0 r link_enc_regs +ffffffff82b94fc0 r link_enc_aux_regs +ffffffff82b95000 r link_enc_hpd_regs +ffffffff82b95010 r le_shift +ffffffff82b95100 r le_mask +ffffffff82b954b8 r link_enc_feature +ffffffff82b954c8 r cs_shift +ffffffff82b954d4 r cs_mask +ffffffff82b954fc r hubbub_reg +ffffffff82b95670 r hubbub_shift +ffffffff82b956f8 r hubbub_mask +ffffffff82b95920 r vmid_regs +ffffffff82b95ae0 r vmid_shifts +ffffffff82b95ae8 r vmid_masks +ffffffff82b95b10 r hubp_regs +ffffffff82b96340 r hubp_shift +ffffffff82b9643c r hubp_mask +ffffffff82b96830 r dpp_regs +ffffffff82b97d30 r tf_shift +ffffffff82b98000 r tf_mask +ffffffff82b98b40 r opp_regs +ffffffff82b98ca0 r opp_shift +ffffffff82b98cd8 r opp_mask +ffffffff82b98db0 r optc_regs +ffffffff82b992b0 r optc_shift +ffffffff82b99370 r optc_mask +ffffffff82b99670 r mpc_regs +ffffffff82b9ae5c r mpc_shift +ffffffff82b9af38 r mpc_mask +ffffffff82b9b2b0 r dsc_regs +ffffffff82b9b4fc r dsc_shift +ffffffff82b9b5b4 r dsc_mask +ffffffff82b9b890 r dwbc30_regs +ffffffff82b9ba6c r dwbc30_shift +ffffffff82b9bba0 r dwbc30_mask +ffffffff82b9c070 r mcif_wb30_regs +ffffffff82b9c16c r mcif_wb30_shift +ffffffff82b9c218 r mcif_wb30_mask +ffffffff82b9c4d0 r aux_engine_regs +ffffffff82b9c570 r aux_mask +ffffffff82b9c5d0 r aux_shift +ffffffff82b9c5f0 r i2c_hw_regs +ffffffff82b9c6d0 r i2c_shifts +ffffffff82b9c6fc r i2c_masks +ffffffff82b9c7a0 r audio_regs +ffffffff82b9c8d4 r audio_shift +ffffffff82b9c8ec r audio_mask +ffffffff82b9c930 r stream_enc_regs +ffffffff82b9ce80 r se_shift +ffffffff82b9cf5c r se_mask +ffffffff82b9d2d0 r vpg_regs +ffffffff82b9d320 r vpg_shift +ffffffff82b9d348 r vpg_mask +ffffffff82b9d3e0 r afmt_regs +ffffffff82b9d470 r afmt_shift +ffffffff82b9d484 r afmt_mask +ffffffff82b9d4c8 r hwseq_reg +ffffffff82b9d6e4 r hwseq_shift +ffffffff82b9d764 r hwseq_mask +ffffffff82b9e000 r bios_regs +ffffffff82b9e008 r res_cap_dcn302 +ffffffff82b9e048 r debug_defaults_drv +ffffffff82b9e1c0 r debug_defaults_diags +ffffffff82b9e340 r clk_src_regs +ffffffff82b9e4e4 r dccg_regs +ffffffff82b9e5d0 r dccg_shift +ffffffff82b9e668 r dccg_mask +ffffffff82b9e8d0 r abm_regs +ffffffff82b9ea10 r abm_shift +ffffffff82b9ea24 r abm_mask +ffffffff82b9ea70 r res_create_funcs +ffffffff82b9eaa0 r res_create_maximus_funcs +ffffffff82b9ead0 r plane_cap +ffffffff82b9eb00 r panel_cntl_regs +ffffffff82b9eb20 r panel_cntl_shift +ffffffff82b9eb30 r panel_cntl_mask +ffffffff82b9eb70 r link_enc_regs +ffffffff82b9f1d0 r link_enc_aux_regs +ffffffff82b9f220 r link_enc_hpd_regs +ffffffff82b9f234 r le_shift +ffffffff82b9f324 r le_mask +ffffffff82b9f6dc r link_enc_feature +ffffffff82b9f6ec r cs_shift +ffffffff82b9f6f8 r cs_mask +ffffffff82b9f720 r hubbub_reg +ffffffff82b9f894 r hubbub_shift +ffffffff82b9f91c r hubbub_mask +ffffffff82b9fb40 r vmid_regs +ffffffff82b9fd00 r vmid_shifts +ffffffff82b9fd08 r vmid_masks +ffffffff82b9fd30 r hubp_regs +ffffffff82ba076c r hubp_shift +ffffffff82ba0868 r hubp_mask +ffffffff82ba0c60 r dpp_regs +ffffffff82ba26a0 r tf_shift +ffffffff82ba2970 r tf_mask +ffffffff82ba34b0 r opp_regs +ffffffff82ba3668 r opp_shift +ffffffff82ba36a0 r opp_mask +ffffffff82ba3780 r optc_regs +ffffffff82ba3dc0 r optc_shift +ffffffff82ba3e80 r optc_mask +ffffffff82ba4180 r mpc_regs +ffffffff82ba596c r mpc_shift +ffffffff82ba5a48 r mpc_mask +ffffffff82ba5dc0 r dsc_regs +ffffffff82ba6194 r dsc_shift +ffffffff82ba624c r dsc_mask +ffffffff82ba6530 r dwbc30_regs +ffffffff82ba670c r dwbc30_shift +ffffffff82ba6840 r dwbc30_mask +ffffffff82ba6d10 r mcif_wb30_regs +ffffffff82ba6e0c r mcif_wb30_shift +ffffffff82ba6eb8 r mcif_wb30_mask +ffffffff82ba7170 r aux_engine_regs +ffffffff82ba7238 r aux_mask +ffffffff82ba7298 r aux_shift +ffffffff82ba72b0 r i2c_hw_regs +ffffffff82ba73c8 r i2c_shifts +ffffffff82ba73f4 r i2c_masks +ffffffff82ba74a0 r audio_regs +ffffffff82ba75d4 r audio_shift +ffffffff82ba75ec r audio_mask +ffffffff82ba7630 r stream_enc_regs +ffffffff82ba7cd4 r se_shift +ffffffff82ba7db0 r se_mask +ffffffff82ba8120 r vpg_regs +ffffffff82ba8198 r vpg_shift +ffffffff82ba81c0 r vpg_mask +ffffffff82ba8260 r afmt_regs +ffffffff82ba8338 r afmt_shift +ffffffff82ba834c r afmt_mask +ffffffff82ba8390 r hwseq_reg +ffffffff82ba85ac r hwseq_shift +ffffffff82ba862c r hwseq_mask ffffffff82ba9000 r bios_regs -ffffffff82ba9008 r res_cap_dcn31 -ffffffff82ba9048 r debug_defaults_diags -ffffffff82ba91c0 r clk_src_regs -ffffffff82ba9370 r clk_src_regs_b0 -ffffffff82ba9514 r dccg_regs -ffffffff82ba9600 r dccg_shift -ffffffff82ba9698 r dccg_mask -ffffffff82ba9900 r abm_regs -ffffffff82ba9a00 r abm_shift -ffffffff82ba9a14 r abm_mask -ffffffff82ba9a60 r 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mpc_regs -ffffffff82bb01a8 r mpc_shift -ffffffff82bb0284 r mpc_mask -ffffffff82bb05f0 r dsc_regs -ffffffff82bb083c r dsc_shift -ffffffff82bb08f4 r dsc_mask -ffffffff82bb0bd0 r dwbc30_regs -ffffffff82bb0dac r dwbc30_shift -ffffffff82bb0ee0 r dwbc30_mask -ffffffff82bb13b0 r mcif_wb30_regs -ffffffff82bb14ac r mcif_wb30_shift -ffffffff82bb1558 r mcif_wb30_mask -ffffffff82bb1810 r aux_engine_regs -ffffffff82bb18d8 r aux_mask -ffffffff82bb1938 r aux_shift -ffffffff82bb1950 r i2c_hw_regs -ffffffff82bb1a68 r i2c_shifts -ffffffff82bb1a94 r i2c_masks -ffffffff82bb1b40 r audio_regs -ffffffff82bb1c74 r audio_shift -ffffffff82bb1c8c r audio_mask -ffffffff82bb1cc8 r se_shift -ffffffff82bb1da4 r se_mask -ffffffff82bb2110 r vpg_regs -ffffffff82bb2200 r vpg_shift -ffffffff82bb2228 r vpg_mask -ffffffff82bb22d0 r afmt_regs -ffffffff82bb23a8 r afmt_shift -ffffffff82bb23bc r afmt_mask -ffffffff82bb2410 r stream_enc_regs -ffffffff82bb3ab0 r hpo_dp_stream_enc_regs -ffffffff82bb3ce0 r hpo_dp_se_shift -ffffffff82bb3d08 r hpo_dp_se_mask -ffffffff82bb3db0 r apg_regs -ffffffff82bb3df0 r apg_shift -ffffffff82bb3df8 r apg_mask -ffffffff82bb3e10 r hpo_dp_link_enc_regs -ffffffff82bb3f20 r hpo_dp_le_shift -ffffffff82bb3f3c r hpo_dp_le_mask -ffffffff82bb3fa0 r hwseq_reg -ffffffff82bb41bc r hwseq_shift -ffffffff82bb423c r hwseq_mask -ffffffff82bb5000 r dccg314_funcs -ffffffff82bb6000 r dcn314_str_enc_funcs -ffffffff82bb7000 r dcn314_funcs -ffffffff82bb72c0 r dcn314_private_funcs -ffffffff82bb8000 r bios_regs -ffffffff82bb8008 r res_cap_dcn314 -ffffffff82bb8048 r debug_defaults_diags -ffffffff82bb81c0 r clk_src_regs -ffffffff82bb8364 r dccg_regs -ffffffff82bb8450 r dccg_shift -ffffffff82bb84e8 r dccg_mask -ffffffff82bb8750 r abm_regs -ffffffff82bb8850 r abm_shift -ffffffff82bb8864 r abm_mask -ffffffff82bb88b0 r res_create_funcs -ffffffff82bb88e0 r res_create_maximus_funcs -ffffffff82bb8910 r plane_cap -ffffffff82bb8940 r link_enc_regs -ffffffff82bb8fa0 r link_enc_aux_regs -ffffffff82bb8ff0 r link_enc_hpd_regs -ffffffff82bb9004 r le_shift -ffffffff82bb90f4 r le_mask -ffffffff82bb94ac r link_enc_feature -ffffffff82bb94bc r panel_config_defaults -ffffffff82bb94f0 r debug_defaults_drv -ffffffff82bb9668 r cs_shift -ffffffff82bb9674 r cs_mask -ffffffff82bb969c r hubbub_reg -ffffffff82bb9810 r hubbub_shift -ffffffff82bb9898 r hubbub_mask -ffffffff82bb9ac0 r vmid_regs -ffffffff82bb9c80 r vmid_shifts -ffffffff82bb9c88 r vmid_masks -ffffffff82bb9cb0 r hubp_regs -ffffffff82bba4e0 r hubp_shift -ffffffff82bba5dc r hubp_mask -ffffffff82bba9d0 r dpp_regs -ffffffff82bbbed0 r tf_shift -ffffffff82bbc1a0 r tf_mask -ffffffff82bbcce0 r opp_regs -ffffffff82bbce40 r opp_shift -ffffffff82bbce78 r opp_mask -ffffffff82bbcf50 r optc_regs -ffffffff82bbd450 r optc_shift -ffffffff82bbd510 r optc_mask -ffffffff82bbd80c r mpc_regs -ffffffff82bbeff8 r mpc_shift -ffffffff82bbf0d4 r mpc_mask -ffffffff82bbf440 r dsc_regs -ffffffff82bbf750 r dsc_shift -ffffffff82bbf808 r dsc_mask -ffffffff82bbfae0 r dwbc30_regs -ffffffff82bbfcbc r dwbc30_shift -ffffffff82bbfdf0 r dwbc30_mask -ffffffff82bc02c0 r mcif_wb30_regs -ffffffff82bc03bc r mcif_wb30_shift -ffffffff82bc0468 r mcif_wb30_mask -ffffffff82bc0720 r aux_engine_regs -ffffffff82bc07e8 r aux_mask -ffffffff82bc0848 r aux_shift -ffffffff82bc0860 r i2c_hw_regs -ffffffff82bc0978 r i2c_shifts -ffffffff82bc09a4 r i2c_masks -ffffffff82bc0a50 r audio_regs -ffffffff82bc0b84 r audio_shift -ffffffff82bc0b9c r audio_mask -ffffffff82bc0be0 r stream_enc_regs -ffffffff82bc1284 r se_shift -ffffffff82bc1360 r se_mask -ffffffff82bc16d0 r vpg_regs -ffffffff82bc17c0 r vpg_shift -ffffffff82bc17e8 r vpg_mask -ffffffff82bc1890 r afmt_regs -ffffffff82bc1968 r afmt_shift -ffffffff82bc197c r afmt_mask -ffffffff82bc19d0 r hpo_dp_stream_enc_regs -ffffffff82bc1c00 r hpo_dp_se_shift -ffffffff82bc1c28 r hpo_dp_se_mask -ffffffff82bc1cd0 r apg_regs -ffffffff82bc1d10 r apg_shift -ffffffff82bc1d18 r apg_mask -ffffffff82bc1d30 r hpo_dp_link_enc_regs -ffffffff82bc1e40 r hpo_dp_le_shift -ffffffff82bc1e5c r hpo_dp_le_mask -ffffffff82bc1ec0 r hwseq_reg -ffffffff82bc20dc r hwseq_shift -ffffffff82bc215c r hwseq_mask -ffffffff82bc3000 r bios_regs -ffffffff82bc3008 r res_cap_dcn31 -ffffffff82bc3048 r debug_defaults_diags -ffffffff82bc31c0 r clk_src_regs -ffffffff82bc3364 r dccg_regs -ffffffff82bc3450 r dccg_shift -ffffffff82bc34e8 r dccg_mask -ffffffff82bc3750 r abm_regs -ffffffff82bc3850 r abm_shift -ffffffff82bc3864 r abm_mask -ffffffff82bc38b0 r res_create_funcs -ffffffff82bc38e0 r res_create_maximus_funcs -ffffffff82bc3910 r plane_cap -ffffffff82bc3940 r link_enc_regs -ffffffff82bc3fa0 r link_enc_aux_regs -ffffffff82bc3ff0 r link_enc_hpd_regs -ffffffff82bc4004 r le_shift -ffffffff82bc40f4 r le_mask -ffffffff82bc44ac r link_enc_feature -ffffffff82bc44bc r panel_config_defaults -ffffffff82bc44f0 r debug_defaults_drv -ffffffff82bc4668 r cs_shift -ffffffff82bc4674 r cs_mask -ffffffff82bc469c r hubbub_reg -ffffffff82bc4810 r hubbub_shift -ffffffff82bc4898 r hubbub_mask -ffffffff82bc4ac0 r vmid_regs -ffffffff82bc4c80 r vmid_shifts -ffffffff82bc4c88 r vmid_masks -ffffffff82bc4cb0 r hubp_regs -ffffffff82bc54e0 r hubp_shift -ffffffff82bc55dc r hubp_mask -ffffffff82bc59d0 r dpp_regs -ffffffff82bc6ed0 r tf_shift -ffffffff82bc71a0 r tf_mask -ffffffff82bc7ce0 r opp_regs -ffffffff82bc7e40 r opp_shift -ffffffff82bc7e78 r opp_mask -ffffffff82bc7f50 r optc_regs -ffffffff82bc8450 r optc_shift -ffffffff82bc8510 r optc_mask -ffffffff82bc880c r mpc_regs -ffffffff82bc9ff8 r mpc_shift -ffffffff82bca0d4 r mpc_mask -ffffffff82bca440 r dsc_regs -ffffffff82bca68c r dsc_shift -ffffffff82bca744 r dsc_mask -ffffffff82bcaa20 r dwbc30_regs -ffffffff82bcabfc r dwbc30_shift -ffffffff82bcad30 r dwbc30_mask -ffffffff82bcb200 r mcif_wb30_regs -ffffffff82bcb2fc r mcif_wb30_shift -ffffffff82bcb3a8 r mcif_wb30_mask -ffffffff82bcb660 r aux_engine_regs -ffffffff82bcb728 r aux_mask -ffffffff82bcb788 r aux_shift -ffffffff82bcb7a0 r i2c_hw_regs -ffffffff82bcb8b8 r i2c_shifts -ffffffff82bcb8e4 r i2c_masks -ffffffff82bcb990 r audio_regs -ffffffff82bcbac4 r audio_shift -ffffffff82bcbadc r audio_mask -ffffffff82bcbb20 r stream_enc_regs -ffffffff82bcc1c4 r se_shift -ffffffff82bcc2a0 r se_mask -ffffffff82bcc610 r vpg_regs -ffffffff82bcc700 r vpg_shift -ffffffff82bcc728 r vpg_mask -ffffffff82bcc7d0 r afmt_regs -ffffffff82bcc8a8 r afmt_shift -ffffffff82bcc8bc r afmt_mask -ffffffff82bcc910 r hpo_dp_stream_enc_regs -ffffffff82bccb40 r hpo_dp_se_shift -ffffffff82bccb68 r hpo_dp_se_mask -ffffffff82bccc10 r apg_regs -ffffffff82bccc50 r apg_shift -ffffffff82bccc58 r apg_mask -ffffffff82bccc70 r hpo_dp_link_enc_regs -ffffffff82bccd80 r hpo_dp_le_shift -ffffffff82bccd9c r hpo_dp_le_mask -ffffffff82bcce00 r hwseq_reg -ffffffff82bcd01c r hwseq_shift -ffffffff82bcd09c r hwseq_mask -ffffffff82bce000 r bios_regs -ffffffff82bce008 r res_cap_dcn31 -ffffffff82bce048 r debug_defaults_diags -ffffffff82bce1c0 r clk_src_regs -ffffffff82bce364 r dccg_regs -ffffffff82bce450 r dccg_shift -ffffffff82bce4e8 r dccg_mask -ffffffff82bce750 r abm_regs -ffffffff82bce850 r abm_shift -ffffffff82bce864 r abm_mask -ffffffff82bce8b0 r res_create_funcs -ffffffff82bce8e0 r res_create_maximus_funcs -ffffffff82bce910 r plane_cap -ffffffff82bce940 r link_enc_regs -ffffffff82bcefa0 r link_enc_aux_regs -ffffffff82bceff0 r link_enc_hpd_regs -ffffffff82bcf004 r le_shift -ffffffff82bcf0f4 r le_mask -ffffffff82bcf4ac r link_enc_feature -ffffffff82bcf4bc r panel_config_defaults -ffffffff82bcf4f0 r debug_defaults_drv -ffffffff82bcf668 r cs_shift -ffffffff82bcf674 r cs_mask -ffffffff82bcf69c r hubbub_reg -ffffffff82bcf810 r hubbub_shift -ffffffff82bcf898 r hubbub_mask -ffffffff82bcfac0 r vmid_regs -ffffffff82bcfc80 r vmid_shifts -ffffffff82bcfc88 r vmid_masks -ffffffff82bcfcb0 r hubp_regs -ffffffff82bd04e0 r hubp_shift -ffffffff82bd05dc r hubp_mask -ffffffff82bd09d0 r dpp_regs -ffffffff82bd1ed0 r tf_shift -ffffffff82bd21a0 r tf_mask -ffffffff82bd2ce0 r opp_regs -ffffffff82bd2e40 r opp_shift -ffffffff82bd2e78 r opp_mask -ffffffff82bd2f50 r optc_regs -ffffffff82bd3450 r optc_shift -ffffffff82bd3510 r optc_mask -ffffffff82bd380c r mpc_regs -ffffffff82bd4ff8 r mpc_shift -ffffffff82bd50d4 r mpc_mask -ffffffff82bd5440 r dsc_regs -ffffffff82bd568c r dsc_shift -ffffffff82bd5744 r dsc_mask -ffffffff82bd5a20 r dwbc30_regs -ffffffff82bd5bfc r dwbc30_shift -ffffffff82bd5d30 r dwbc30_mask -ffffffff82bd6200 r mcif_wb30_regs -ffffffff82bd62fc r mcif_wb30_shift -ffffffff82bd63a8 r mcif_wb30_mask -ffffffff82bd6660 r aux_engine_regs -ffffffff82bd6728 r aux_mask -ffffffff82bd6788 r aux_shift -ffffffff82bd67a0 r i2c_hw_regs -ffffffff82bd68b8 r i2c_shifts -ffffffff82bd68e4 r i2c_masks -ffffffff82bd6990 r audio_regs -ffffffff82bd6ac4 r audio_shift -ffffffff82bd6adc r audio_mask -ffffffff82bd6b20 r stream_enc_regs -ffffffff82bd71c4 r se_shift -ffffffff82bd72a0 r se_mask -ffffffff82bd7610 r vpg_regs -ffffffff82bd7700 r vpg_shift -ffffffff82bd7728 r vpg_mask -ffffffff82bd77d0 r afmt_regs -ffffffff82bd78a8 r afmt_shift -ffffffff82bd78bc r afmt_mask -ffffffff82bd7910 r hpo_dp_stream_enc_regs -ffffffff82bd7b40 r hpo_dp_se_shift -ffffffff82bd7b68 r hpo_dp_se_mask -ffffffff82bd7c10 r apg_regs -ffffffff82bd7c50 r apg_shift -ffffffff82bd7c58 r apg_mask -ffffffff82bd7c70 r hpo_dp_link_enc_regs -ffffffff82bd7d80 r hpo_dp_le_shift -ffffffff82bd7d9c r hpo_dp_le_mask -ffffffff82bd7e00 r hwseq_reg -ffffffff82bd801c r hwseq_shift -ffffffff82bd809c r hwseq_mask -ffffffff82bd9000 r dccg32_funcs -ffffffff82bda000 r dcn32_link_enc_funcs -ffffffff82bdb000 r dcn32_str_enc_funcs -ffffffff82bdc000 r hubbub32_funcs -ffffffff82bdd000 r dcn32_funcs -ffffffff82bdd2c0 r dcn32_private_funcs -ffffffff82bde000 R dcn32_mmhubbub_funcs -ffffffff82bdf000 R dcn32_mpc_funcs -ffffffff82be0000 r res_cap_dcn32 -ffffffff82be0040 r debug_defaults_diags -ffffffff82be01b8 r dccg_shift -ffffffff82be0250 r dccg_mask -ffffffff82be04ac r abm_shift -ffffffff82be04c0 r abm_mask -ffffffff82be0508 r res_create_funcs -ffffffff82be0538 r res_create_maximus_funcs -ffffffff82be0568 r plane_cap -ffffffff82be0594 r le_shift -ffffffff82be0684 r le_mask -ffffffff82be0a3c r link_enc_feature -ffffffff82be0a50 r debug_defaults_drv -ffffffff82be0bc8 r cs_shift -ffffffff82be0bd4 r cs_mask -ffffffff82be0bfc r hubbub_shift -ffffffff82be0c84 r hubbub_mask -ffffffff82be0ea0 r vmid_shifts -ffffffff82be0ea8 r vmid_masks -ffffffff82be0ec8 r hubp_shift -ffffffff82be0fc4 r hubp_mask -ffffffff82be13b4 r tf_shift -ffffffff82be1684 r tf_mask -ffffffff82be21c4 r opp_shift -ffffffff82be21fc r opp_mask -ffffffff82be22d0 r optc_shift -ffffffff82be2390 r optc_mask -ffffffff82be268c r mpc_shift -ffffffff82be2768 r mpc_mask -ffffffff82be2ad4 r dsc_shift -ffffffff82be2b8c r dsc_mask -ffffffff82be2e64 r dwbc30_shift -ffffffff82be2f98 r dwbc30_mask -ffffffff82be3460 r mcif_wb30_shift -ffffffff82be350c r mcif_wb30_mask -ffffffff82be37b8 r aux_mask -ffffffff82be3818 r aux_shift -ffffffff82be3830 r i2c_shifts -ffffffff82be385c r i2c_masks -ffffffff82be3900 r audio_shift -ffffffff82be3918 r audio_mask -ffffffff82be3954 r se_shift -ffffffff82be3a30 r se_mask -ffffffff82be3d9c r vpg_shift -ffffffff82be3dc4 r vpg_mask -ffffffff82be3e58 r afmt_shift -ffffffff82be3e6c r afmt_mask -ffffffff82be3eb0 r hpo_dp_se_shift -ffffffff82be3ed8 r hpo_dp_se_mask -ffffffff82be3f78 r apg_shift -ffffffff82be3f80 r apg_mask -ffffffff82be3f98 r hpo_dp_le_shift -ffffffff82be3fb4 r hpo_dp_le_mask -ffffffff82be4018 r hwseq_shift -ffffffff82be4098 r hwseq_mask -ffffffff82be5000 r dcn321_link_enc_funcs -ffffffff82be6000 r res_cap_dcn321 -ffffffff82be6040 r debug_defaults_diags -ffffffff82be61b8 r dccg_shift -ffffffff82be6250 r dccg_mask -ffffffff82be64ac r abm_shift -ffffffff82be64c0 r abm_mask -ffffffff82be6508 r res_create_funcs -ffffffff82be6538 r res_create_maximus_funcs -ffffffff82be6568 r plane_cap -ffffffff82be6594 r le_shift -ffffffff82be6684 r le_mask -ffffffff82be6a3c r link_enc_feature -ffffffff82be6a50 r debug_defaults_drv -ffffffff82be6bc8 r cs_shift -ffffffff82be6bd4 r cs_mask -ffffffff82be6bfc r hubbub_shift -ffffffff82be6c84 r hubbub_mask -ffffffff82be6ea0 r vmid_shifts -ffffffff82be6ea8 r vmid_masks -ffffffff82be6ec8 r hubp_shift -ffffffff82be6fc4 r hubp_mask -ffffffff82be73b4 r tf_shift -ffffffff82be7684 r tf_mask -ffffffff82be81c4 r opp_shift -ffffffff82be81fc r opp_mask -ffffffff82be82d0 r optc_shift -ffffffff82be8390 r optc_mask -ffffffff82be868c r mpc_shift -ffffffff82be8768 r mpc_mask -ffffffff82be8ad4 r dsc_shift -ffffffff82be8b8c r dsc_mask -ffffffff82be8e64 r dwbc30_shift -ffffffff82be8f98 r dwbc30_mask -ffffffff82be9460 r mcif_wb30_shift -ffffffff82be950c r mcif_wb30_mask -ffffffff82be97b8 r aux_mask -ffffffff82be9818 r aux_shift -ffffffff82be9830 r i2c_shifts -ffffffff82be985c r i2c_masks -ffffffff82be9900 r audio_shift -ffffffff82be9918 r audio_mask -ffffffff82be9954 r se_shift -ffffffff82be9a30 r se_mask -ffffffff82be9d9c r vpg_shift -ffffffff82be9dc4 r vpg_mask -ffffffff82be9e58 r afmt_shift -ffffffff82be9e6c r afmt_mask -ffffffff82be9eb0 r hpo_dp_se_shift -ffffffff82be9ed8 r hpo_dp_se_mask -ffffffff82be9f78 r apg_shift -ffffffff82be9f80 r apg_mask -ffffffff82be9f98 r hpo_dp_le_shift -ffffffff82be9fb4 r hpo_dp_le_mask -ffffffff82bea018 r hwseq_shift -ffffffff82bea098 r hwseq_mask -ffffffff82bec000 R dcn10_soc_defaults -ffffffff82bec08c R dcn10_ip_defaults -ffffffff82bf7000 R dml20_funcs -ffffffff82bf7030 R dml20v2_funcs -ffffffff82bf7060 R dml21_funcs -ffffffff82bf7090 R dml30_funcs -ffffffff82bf70c0 R dml31_funcs -ffffffff82bf70f0 R dml314_funcs -ffffffff82bf7120 R dml32_funcs -ffffffff82bfa000 R qp_table_422_10bpc_min -ffffffff82bfa740 R qp_table_444_8bpc_max -ffffffff82bfb080 R qp_table_420_12bpc_max -ffffffff82bfb7c0 R qp_table_444_10bpc_min -ffffffff82bfc400 R qp_table_420_8bpc_max -ffffffff82bfc840 R qp_table_444_8bpc_min -ffffffff82bfd180 R qp_table_444_12bpc_min -ffffffff82bfe0c0 R qp_table_420_12bpc_min -ffffffff82bfe800 R qp_table_422_12bpc_min -ffffffff82bff140 R qp_table_422_12bpc_max -ffffffff82bffa80 R qp_table_444_12bpc_max -ffffffff82c009c0 R qp_table_420_8bpc_min -ffffffff82c00e00 R qp_table_422_8bpc_min -ffffffff82c01340 R qp_table_422_10bpc_max -ffffffff82c01a80 R qp_table_420_10bpc_max -ffffffff82c02040 R qp_table_420_10bpc_min -ffffffff82c02600 R qp_table_444_10bpc_max -ffffffff82c03240 R qp_table_422_8bpc_max -ffffffff82c05000 r funcs -ffffffff82c05050 r hpd_regs -ffffffff82c051a0 r hpd_shift -ffffffff82c051b0 r hpd_mask -ffffffff82c051c0 r ddc_data_regs -ffffffff82c053a0 r ddc_clk_regs -ffffffff82c05580 r ddc_shift -ffffffff82c055a8 r ddc_mask -ffffffff82c06000 r funcs -ffffffff82c07000 r funcs -ffffffff82c07050 r hpd_regs -ffffffff82c071a0 r hpd_shift -ffffffff82c071b0 r hpd_mask -ffffffff82c071c0 r ddc_data_regs -ffffffff82c073a0 r ddc_clk_regs -ffffffff82c07580 r ddc_shift -ffffffff82c075a8 r ddc_mask -ffffffff82c08000 r funcs -ffffffff82c09000 r funcs -ffffffff82c09050 r hpd_regs -ffffffff82c091a0 r hpd_shift -ffffffff82c091b0 r hpd_mask -ffffffff82c091c0 r ddc_data_regs -ffffffff82c093a0 r ddc_clk_regs -ffffffff82c09580 r ddc_shift -ffffffff82c095a8 r ddc_mask -ffffffff82c0a000 r funcs -ffffffff82c0b000 r funcs -ffffffff82c0b050 r hpd_regs -ffffffff82c0b1a0 r hpd_shift -ffffffff82c0b1b0 r hpd_mask -ffffffff82c0b1c0 r ddc_data_regs -ffffffff82c0b3a0 r ddc_clk_regs -ffffffff82c0b580 r ddc_shift -ffffffff82c0b5a8 r ddc_mask -ffffffff82c0b5d0 r generic_regs -ffffffff82c0b640 r generic_shift -ffffffff82c0b650 r generic_mask -ffffffff82c0c000 r funcs -ffffffff82c0d000 r funcs -ffffffff82c0d050 r hpd_regs -ffffffff82c0d1a0 r hpd_shift -ffffffff82c0d1b0 r hpd_mask -ffffffff82c0d1c0 r ddc_data_regs_dcn -ffffffff82c0d370 r ddc_clk_regs_dcn -ffffffff82c0d520 r ddc_shift -ffffffff82c0d610 r ddc_mask -ffffffff82c0d700 r generic_regs -ffffffff82c0d770 r generic_shift -ffffffff82c0d780 r generic_mask -ffffffff82c0e000 r funcs -ffffffff82c0f000 r funcs -ffffffff82c0f050 r hpd_regs -ffffffff82c0f168 r hpd_shift -ffffffff82c0f178 r hpd_mask -ffffffff82c0f190 r ddc_data_regs_dcn -ffffffff82c0f2c0 r ddc_clk_regs_dcn -ffffffff82c0f3f0 r ddc_shift -ffffffff82c0f4e0 r ddc_mask -ffffffff82c0f5d0 r generic_regs -ffffffff82c0f604 r generic_shift -ffffffff82c0f60c r generic_mask -ffffffff82c10000 r funcs -ffffffff82c11000 r funcs -ffffffff82c11050 r hpd_regs -ffffffff82c111a0 r hpd_shift -ffffffff82c111b0 r hpd_mask -ffffffff82c111c0 r ddc_data_regs_dcn -ffffffff82c11370 r ddc_clk_regs_dcn -ffffffff82c11520 r ddc_shift -ffffffff82c11610 r ddc_mask -ffffffff82c11700 r generic_regs -ffffffff82c11770 r generic_shift -ffffffff82c11780 r generic_mask -ffffffff82c12000 r funcs +ffffffff82ba9008 r res_cap_dcn303 +ffffffff82ba9048 r debug_defaults_drv +ffffffff82ba91c0 r debug_defaults_diags +ffffffff82ba9340 r clk_src_regs +ffffffff82ba93e8 r dccg_regs +ffffffff82ba94d4 r dccg_shift +ffffffff82ba956c r dccg_mask +ffffffff82ba97d0 r abm_regs +ffffffff82ba9850 r abm_shift +ffffffff82ba9864 r abm_mask +ffffffff82ba98b0 r res_create_funcs +ffffffff82ba98e0 r res_create_maximus_funcs +ffffffff82ba9910 r plane_cap +ffffffff82ba9940 r panel_cntl_regs +ffffffff82ba9960 r panel_cntl_shift +ffffffff82ba9970 r panel_cntl_mask +ffffffff82ba99b0 r link_enc_regs +ffffffff82ba9c40 r link_enc_aux_regs +ffffffff82ba9c60 r link_enc_hpd_regs +ffffffff82ba9c68 r le_shift +ffffffff82ba9d58 r le_mask +ffffffff82baa110 r link_enc_feature +ffffffff82baa120 r cs_shift +ffffffff82baa12c r cs_mask +ffffffff82baa154 r hubbub_reg +ffffffff82baa2c8 r hubbub_shift +ffffffff82baa350 r hubbub_mask +ffffffff82baa570 r vmid_regs +ffffffff82baa730 r vmid_shifts +ffffffff82baa738 r vmid_masks +ffffffff82baa760 r hubp_regs +ffffffff82baab78 r hubp_shift +ffffffff82baac74 r hubp_mask +ffffffff82bab070 r dpp_regs +ffffffff82babaf0 r tf_shift +ffffffff82babdc0 r tf_mask +ffffffff82bac900 r opp_regs +ffffffff82bac9b0 r opp_shift +ffffffff82bac9e8 r opp_mask +ffffffff82bacac0 r optc_regs +ffffffff82bacd40 r optc_shift +ffffffff82bace00 r optc_mask +ffffffff82bad100 r mpc_regs +ffffffff82bae8ec r mpc_shift +ffffffff82bae9c8 r mpc_mask +ffffffff82baed40 r dsc_regs +ffffffff82baeec8 r dsc_shift +ffffffff82baef80 r dsc_mask +ffffffff82baf260 r dwbc30_regs +ffffffff82baf43c r dwbc30_shift +ffffffff82baf570 r dwbc30_mask +ffffffff82bafa40 r mcif_wb30_regs +ffffffff82bafb3c r mcif_wb30_shift +ffffffff82bafbe8 r mcif_wb30_mask +ffffffff82bafea0 r aux_engine_regs +ffffffff82bafef0 r aux_mask +ffffffff82baff50 r aux_shift +ffffffff82baff70 r i2c_hw_regs +ffffffff82baffe0 r i2c_shifts +ffffffff82bb000c r i2c_masks +ffffffff82bb00b0 r audio_regs +ffffffff82bb01e4 r audio_shift +ffffffff82bb01fc r audio_mask +ffffffff82bb0240 r stream_enc_regs +ffffffff82bb04e8 r se_shift +ffffffff82bb05c4 r se_mask +ffffffff82bb0930 r vpg_regs +ffffffff82bb096c r vpg_shift +ffffffff82bb0994 r vpg_mask +ffffffff82bb0a30 r afmt_regs +ffffffff82bb0a9c r afmt_shift +ffffffff82bb0ab0 r afmt_mask +ffffffff82bb0af4 r hwseq_reg +ffffffff82bb0d10 r hwseq_shift +ffffffff82bb0d90 r hwseq_mask +ffffffff82bb1000 r dccg31_funcs +ffffffff82bb2000 r dcn31_link_enc_funcs +ffffffff82bb3000 r dcn30_str_enc_funcs +ffffffff82bb4000 r hubbub31_funcs +ffffffff82bb5000 r dcn31_funcs +ffffffff82bb52c0 r dcn31_private_funcs +ffffffff82bb6000 r dcn31_link_panel_cntl_funcs +ffffffff82bb7000 r bios_regs +ffffffff82bb7008 r res_cap_dcn31 +ffffffff82bb7048 r debug_defaults_diags +ffffffff82bb71c0 r clk_src_regs +ffffffff82bb7370 r clk_src_regs_b0 +ffffffff82bb7514 r dccg_regs +ffffffff82bb7600 r dccg_shift +ffffffff82bb7698 r dccg_mask +ffffffff82bb7900 r abm_regs +ffffffff82bb7a00 r abm_shift +ffffffff82bb7a14 r abm_mask +ffffffff82bb7a60 r res_create_funcs +ffffffff82bb7a90 r res_create_maximus_funcs +ffffffff82bb7ac0 r plane_cap +ffffffff82bb7af0 r link_enc_regs +ffffffff82bb8150 r link_enc_aux_regs +ffffffff82bb81a0 r link_enc_hpd_regs +ffffffff82bb81b4 r le_shift +ffffffff82bb82a4 r le_mask +ffffffff82bb865c r link_enc_feature +ffffffff82bb866c r panel_config_defaults +ffffffff82bb86a0 r debug_defaults_drv +ffffffff82bb8818 r cs_shift +ffffffff82bb8824 r cs_mask +ffffffff82bb884c r hubbub_reg +ffffffff82bb89c0 r hubbub_shift +ffffffff82bb8a48 r hubbub_mask +ffffffff82bb8c70 r vmid_regs +ffffffff82bb8e30 r vmid_shifts +ffffffff82bb8e38 r vmid_masks +ffffffff82bb8e60 r hubp_regs +ffffffff82bb9690 r hubp_shift +ffffffff82bb978c r hubp_mask +ffffffff82bb9b80 r dpp_regs +ffffffff82bbb080 r tf_shift +ffffffff82bbb350 r tf_mask +ffffffff82bbbe90 r opp_regs +ffffffff82bbbff0 r opp_shift +ffffffff82bbc028 r opp_mask +ffffffff82bbc100 r optc_regs +ffffffff82bbc600 r optc_shift +ffffffff82bbc6c0 r optc_mask +ffffffff82bbc9c0 r mpc_regs +ffffffff82bbe1ac r mpc_shift +ffffffff82bbe288 r mpc_mask +ffffffff82bbe600 r dsc_regs +ffffffff82bbe84c r dsc_shift +ffffffff82bbe904 r dsc_mask +ffffffff82bbebe0 r dwbc30_regs +ffffffff82bbedbc r dwbc30_shift +ffffffff82bbeef0 r dwbc30_mask +ffffffff82bbf3c0 r mcif_wb30_regs +ffffffff82bbf4bc r mcif_wb30_shift +ffffffff82bbf568 r mcif_wb30_mask +ffffffff82bbf820 r aux_engine_regs +ffffffff82bbf8e8 r aux_mask +ffffffff82bbf948 r aux_shift +ffffffff82bbf960 r i2c_hw_regs +ffffffff82bbfa78 r i2c_shifts +ffffffff82bbfaa4 r i2c_masks +ffffffff82bbfb50 r audio_regs +ffffffff82bbfc84 r audio_shift +ffffffff82bbfc9c r audio_mask +ffffffff82bbfcd8 r se_shift +ffffffff82bbfdb4 r se_mask +ffffffff82bc0120 r vpg_regs +ffffffff82bc0210 r vpg_shift +ffffffff82bc0238 r vpg_mask +ffffffff82bc02e0 r afmt_regs +ffffffff82bc03b8 r afmt_shift +ffffffff82bc03cc r afmt_mask +ffffffff82bc0420 r stream_enc_regs +ffffffff82bc1ac0 r hpo_dp_stream_enc_regs +ffffffff82bc1cf0 r hpo_dp_se_shift +ffffffff82bc1d18 r hpo_dp_se_mask +ffffffff82bc1dc0 r apg_regs +ffffffff82bc1e00 r apg_shift +ffffffff82bc1e08 r apg_mask +ffffffff82bc1e20 r hpo_dp_link_enc_regs +ffffffff82bc1f30 r hpo_dp_le_shift +ffffffff82bc1f4c r hpo_dp_le_mask +ffffffff82bc1fb0 r hwseq_reg +ffffffff82bc21cc r hwseq_shift +ffffffff82bc224c r hwseq_mask +ffffffff82bc3000 r dccg314_funcs +ffffffff82bc4000 r dcn314_str_enc_funcs +ffffffff82bc5000 r dcn314_funcs +ffffffff82bc52c0 r dcn314_private_funcs +ffffffff82bc6000 r bios_regs +ffffffff82bc6008 r res_cap_dcn314 +ffffffff82bc6048 r debug_defaults_diags +ffffffff82bc61c0 r clk_src_regs +ffffffff82bc6364 r dccg_regs +ffffffff82bc6450 r dccg_shift +ffffffff82bc64e8 r dccg_mask +ffffffff82bc6750 r abm_regs +ffffffff82bc6850 r abm_shift +ffffffff82bc6864 r abm_mask +ffffffff82bc68b0 r res_create_funcs +ffffffff82bc68e0 r res_create_maximus_funcs +ffffffff82bc6910 r plane_cap +ffffffff82bc6940 r link_enc_regs +ffffffff82bc6fa0 r link_enc_aux_regs +ffffffff82bc6ff0 r link_enc_hpd_regs +ffffffff82bc7004 r le_shift +ffffffff82bc70f4 r le_mask +ffffffff82bc74ac r link_enc_feature +ffffffff82bc74bc r panel_config_defaults +ffffffff82bc74f0 r debug_defaults_drv +ffffffff82bc7668 r cs_shift +ffffffff82bc7674 r cs_mask +ffffffff82bc769c r hubbub_reg +ffffffff82bc7810 r hubbub_shift +ffffffff82bc7898 r hubbub_mask +ffffffff82bc7ac0 r vmid_regs +ffffffff82bc7c80 r vmid_shifts +ffffffff82bc7c88 r vmid_masks +ffffffff82bc7cb0 r hubp_regs +ffffffff82bc84e0 r hubp_shift +ffffffff82bc85dc r hubp_mask +ffffffff82bc89d0 r dpp_regs +ffffffff82bc9ed0 r tf_shift +ffffffff82bca1a0 r tf_mask +ffffffff82bcace0 r opp_regs +ffffffff82bcae40 r opp_shift +ffffffff82bcae78 r opp_mask +ffffffff82bcaf50 r optc_regs +ffffffff82bcb450 r optc_shift +ffffffff82bcb510 r optc_mask +ffffffff82bcb810 r mpc_regs +ffffffff82bccffc r mpc_shift +ffffffff82bcd0d8 r mpc_mask +ffffffff82bcd450 r dsc_regs +ffffffff82bcd760 r dsc_shift +ffffffff82bcd818 r dsc_mask +ffffffff82bcdaf0 r dwbc30_regs +ffffffff82bcdccc r dwbc30_shift +ffffffff82bcde00 r dwbc30_mask +ffffffff82bce2d0 r mcif_wb30_regs +ffffffff82bce3cc r mcif_wb30_shift +ffffffff82bce478 r mcif_wb30_mask +ffffffff82bce730 r aux_engine_regs +ffffffff82bce7f8 r aux_mask +ffffffff82bce858 r aux_shift +ffffffff82bce870 r i2c_hw_regs +ffffffff82bce988 r i2c_shifts +ffffffff82bce9b4 r i2c_masks +ffffffff82bcea60 r audio_regs +ffffffff82bceb94 r audio_shift +ffffffff82bcebac r audio_mask +ffffffff82bcebf0 r stream_enc_regs +ffffffff82bcf294 r se_shift +ffffffff82bcf370 r se_mask +ffffffff82bcf6e0 r vpg_regs +ffffffff82bcf7d0 r vpg_shift +ffffffff82bcf7f8 r vpg_mask +ffffffff82bcf8a0 r afmt_regs +ffffffff82bcf978 r afmt_shift +ffffffff82bcf98c r afmt_mask +ffffffff82bcf9e0 r hpo_dp_stream_enc_regs +ffffffff82bcfc10 r hpo_dp_se_shift +ffffffff82bcfc38 r hpo_dp_se_mask +ffffffff82bcfce0 r apg_regs +ffffffff82bcfd20 r apg_shift +ffffffff82bcfd28 r apg_mask +ffffffff82bcfd40 r hpo_dp_link_enc_regs +ffffffff82bcfe50 r hpo_dp_le_shift +ffffffff82bcfe6c r hpo_dp_le_mask +ffffffff82bcfed0 r hwseq_reg +ffffffff82bd00ec r hwseq_shift +ffffffff82bd016c r hwseq_mask +ffffffff82bd1000 r bios_regs +ffffffff82bd1008 r res_cap_dcn31 +ffffffff82bd1048 r debug_defaults_diags +ffffffff82bd11c0 r clk_src_regs +ffffffff82bd1364 r dccg_regs +ffffffff82bd1450 r dccg_shift +ffffffff82bd14e8 r dccg_mask +ffffffff82bd1750 r abm_regs +ffffffff82bd1850 r abm_shift +ffffffff82bd1864 r abm_mask +ffffffff82bd18b0 r res_create_funcs +ffffffff82bd18e0 r res_create_maximus_funcs +ffffffff82bd1910 r plane_cap +ffffffff82bd1940 r link_enc_regs +ffffffff82bd1fa0 r link_enc_aux_regs +ffffffff82bd1ff0 r link_enc_hpd_regs +ffffffff82bd2004 r le_shift +ffffffff82bd20f4 r le_mask +ffffffff82bd24ac r link_enc_feature +ffffffff82bd24bc r panel_config_defaults +ffffffff82bd24f0 r debug_defaults_drv +ffffffff82bd2668 r cs_shift +ffffffff82bd2674 r cs_mask +ffffffff82bd269c r hubbub_reg +ffffffff82bd2810 r hubbub_shift +ffffffff82bd2898 r hubbub_mask +ffffffff82bd2ac0 r vmid_regs +ffffffff82bd2c80 r vmid_shifts +ffffffff82bd2c88 r vmid_masks +ffffffff82bd2cb0 r hubp_regs +ffffffff82bd34e0 r hubp_shift +ffffffff82bd35dc r hubp_mask +ffffffff82bd39d0 r dpp_regs +ffffffff82bd4ed0 r tf_shift +ffffffff82bd51a0 r tf_mask +ffffffff82bd5ce0 r opp_regs +ffffffff82bd5e40 r opp_shift +ffffffff82bd5e78 r opp_mask +ffffffff82bd5f50 r optc_regs +ffffffff82bd6450 r optc_shift +ffffffff82bd6510 r optc_mask +ffffffff82bd6810 r mpc_regs +ffffffff82bd7ffc r mpc_shift +ffffffff82bd80d8 r mpc_mask +ffffffff82bd8450 r dsc_regs +ffffffff82bd869c r dsc_shift +ffffffff82bd8754 r dsc_mask +ffffffff82bd8a30 r dwbc30_regs +ffffffff82bd8c0c r dwbc30_shift +ffffffff82bd8d40 r dwbc30_mask +ffffffff82bd9210 r mcif_wb30_regs +ffffffff82bd930c r mcif_wb30_shift +ffffffff82bd93b8 r mcif_wb30_mask +ffffffff82bd9670 r aux_engine_regs +ffffffff82bd9738 r aux_mask +ffffffff82bd9798 r aux_shift +ffffffff82bd97b0 r i2c_hw_regs +ffffffff82bd98c8 r i2c_shifts +ffffffff82bd98f4 r i2c_masks +ffffffff82bd99a0 r audio_regs +ffffffff82bd9ad4 r audio_shift +ffffffff82bd9aec r audio_mask +ffffffff82bd9b30 r stream_enc_regs +ffffffff82bda1d4 r se_shift +ffffffff82bda2b0 r se_mask +ffffffff82bda620 r vpg_regs +ffffffff82bda710 r vpg_shift +ffffffff82bda738 r vpg_mask +ffffffff82bda7e0 r afmt_regs +ffffffff82bda8b8 r afmt_shift +ffffffff82bda8cc r afmt_mask +ffffffff82bda920 r hpo_dp_stream_enc_regs +ffffffff82bdab50 r hpo_dp_se_shift +ffffffff82bdab78 r hpo_dp_se_mask +ffffffff82bdac20 r apg_regs +ffffffff82bdac60 r apg_shift +ffffffff82bdac68 r apg_mask +ffffffff82bdac80 r hpo_dp_link_enc_regs +ffffffff82bdad90 r hpo_dp_le_shift +ffffffff82bdadac r hpo_dp_le_mask +ffffffff82bdae10 r hwseq_reg +ffffffff82bdb02c r hwseq_shift +ffffffff82bdb0ac r hwseq_mask +ffffffff82bdc000 r bios_regs +ffffffff82bdc008 r res_cap_dcn31 +ffffffff82bdc048 r debug_defaults_diags +ffffffff82bdc1c0 r clk_src_regs +ffffffff82bdc364 r dccg_regs +ffffffff82bdc450 r dccg_shift +ffffffff82bdc4e8 r dccg_mask +ffffffff82bdc750 r abm_regs +ffffffff82bdc850 r abm_shift +ffffffff82bdc864 r abm_mask +ffffffff82bdc8b0 r res_create_funcs +ffffffff82bdc8e0 r res_create_maximus_funcs +ffffffff82bdc910 r plane_cap +ffffffff82bdc940 r link_enc_regs +ffffffff82bdcfa0 r link_enc_aux_regs +ffffffff82bdcff0 r link_enc_hpd_regs +ffffffff82bdd004 r le_shift +ffffffff82bdd0f4 r le_mask +ffffffff82bdd4ac r link_enc_feature +ffffffff82bdd4bc r panel_config_defaults +ffffffff82bdd4f0 r debug_defaults_drv +ffffffff82bdd668 r cs_shift +ffffffff82bdd674 r cs_mask +ffffffff82bdd69c r hubbub_reg +ffffffff82bdd810 r hubbub_shift +ffffffff82bdd898 r hubbub_mask +ffffffff82bddac0 r vmid_regs +ffffffff82bddc80 r vmid_shifts +ffffffff82bddc88 r vmid_masks +ffffffff82bddcb0 r hubp_regs +ffffffff82bde4e0 r hubp_shift +ffffffff82bde5dc r hubp_mask +ffffffff82bde9d0 r dpp_regs +ffffffff82bdfed0 r tf_shift +ffffffff82be01a0 r tf_mask +ffffffff82be0ce0 r opp_regs +ffffffff82be0e40 r opp_shift +ffffffff82be0e78 r opp_mask +ffffffff82be0f50 r optc_regs +ffffffff82be1450 r optc_shift +ffffffff82be1510 r optc_mask +ffffffff82be1810 r mpc_regs +ffffffff82be2ffc r mpc_shift +ffffffff82be30d8 r mpc_mask +ffffffff82be3450 r dsc_regs +ffffffff82be369c r dsc_shift +ffffffff82be3754 r dsc_mask +ffffffff82be3a30 r dwbc30_regs +ffffffff82be3c0c r dwbc30_shift +ffffffff82be3d40 r dwbc30_mask +ffffffff82be4210 r mcif_wb30_regs +ffffffff82be430c r mcif_wb30_shift +ffffffff82be43b8 r mcif_wb30_mask +ffffffff82be4670 r aux_engine_regs +ffffffff82be4738 r aux_mask +ffffffff82be4798 r aux_shift +ffffffff82be47b0 r i2c_hw_regs +ffffffff82be48c8 r i2c_shifts +ffffffff82be48f4 r i2c_masks +ffffffff82be49a0 r audio_regs +ffffffff82be4ad4 r audio_shift +ffffffff82be4aec r audio_mask +ffffffff82be4b30 r stream_enc_regs +ffffffff82be51d4 r se_shift +ffffffff82be52b0 r se_mask +ffffffff82be5620 r vpg_regs +ffffffff82be5710 r vpg_shift +ffffffff82be5738 r vpg_mask +ffffffff82be57e0 r afmt_regs +ffffffff82be58b8 r afmt_shift +ffffffff82be58cc r afmt_mask +ffffffff82be5920 r hpo_dp_stream_enc_regs +ffffffff82be5b50 r hpo_dp_se_shift +ffffffff82be5b78 r hpo_dp_se_mask +ffffffff82be5c20 r apg_regs +ffffffff82be5c60 r apg_shift +ffffffff82be5c68 r apg_mask +ffffffff82be5c80 r hpo_dp_link_enc_regs +ffffffff82be5d90 r hpo_dp_le_shift +ffffffff82be5dac r hpo_dp_le_mask +ffffffff82be5e10 r hwseq_reg +ffffffff82be602c r hwseq_shift +ffffffff82be60ac r hwseq_mask +ffffffff82be7000 r dccg32_funcs +ffffffff82be8000 r dcn32_link_enc_funcs +ffffffff82be9000 r dcn32_str_enc_funcs +ffffffff82bea000 r hubbub32_funcs +ffffffff82beb000 r dcn32_funcs +ffffffff82beb2c0 r dcn32_private_funcs +ffffffff82bec000 R dcn32_mmhubbub_funcs +ffffffff82bed000 R dcn32_mpc_funcs +ffffffff82bee000 r res_cap_dcn32 +ffffffff82bee040 r debug_defaults_diags +ffffffff82bee1b8 r dccg_shift +ffffffff82bee250 r dccg_mask +ffffffff82bee4ac r abm_shift +ffffffff82bee4c0 r abm_mask +ffffffff82bee508 r res_create_funcs +ffffffff82bee538 r res_create_maximus_funcs +ffffffff82bee568 r plane_cap +ffffffff82bee594 r le_shift +ffffffff82bee684 r le_mask +ffffffff82beea3c r link_enc_feature +ffffffff82beea50 r debug_defaults_drv +ffffffff82beebc8 r cs_shift +ffffffff82beebd4 r cs_mask +ffffffff82beebfc r hubbub_shift +ffffffff82beec84 r hubbub_mask +ffffffff82beeea0 r vmid_shifts +ffffffff82beeea8 r vmid_masks +ffffffff82beeec8 r hubp_shift +ffffffff82beefc4 r hubp_mask +ffffffff82bef3b4 r tf_shift +ffffffff82bef684 r tf_mask +ffffffff82bf01c4 r opp_shift +ffffffff82bf01fc r opp_mask +ffffffff82bf02d0 r optc_shift +ffffffff82bf0390 r optc_mask +ffffffff82bf0690 r mpc_shift +ffffffff82bf076c r mpc_mask +ffffffff82bf0ad8 r dsc_shift +ffffffff82bf0b90 r dsc_mask +ffffffff82bf0e68 r dwbc30_shift +ffffffff82bf0f9c r dwbc30_mask +ffffffff82bf1464 r mcif_wb30_shift +ffffffff82bf1510 r mcif_wb30_mask +ffffffff82bf17bc r aux_mask +ffffffff82bf181c r aux_shift +ffffffff82bf1834 r i2c_shifts +ffffffff82bf1860 r i2c_masks +ffffffff82bf1904 r audio_shift +ffffffff82bf191c r audio_mask +ffffffff82bf1958 r se_shift +ffffffff82bf1a34 r se_mask +ffffffff82bf1da0 r vpg_shift +ffffffff82bf1dc8 r vpg_mask +ffffffff82bf1e5c r afmt_shift +ffffffff82bf1e70 r afmt_mask +ffffffff82bf1eb4 r hpo_dp_se_shift +ffffffff82bf1edc r hpo_dp_se_mask +ffffffff82bf1f7c r apg_shift +ffffffff82bf1f84 r apg_mask +ffffffff82bf1f9c r hpo_dp_le_shift +ffffffff82bf1fb8 r hpo_dp_le_mask +ffffffff82bf201c r hwseq_shift +ffffffff82bf209c r hwseq_mask +ffffffff82bf3000 r dcn321_link_enc_funcs +ffffffff82bf4000 r res_cap_dcn321 +ffffffff82bf4040 r debug_defaults_diags +ffffffff82bf41b8 r dccg_shift +ffffffff82bf4250 r dccg_mask +ffffffff82bf44ac r abm_shift +ffffffff82bf44c0 r abm_mask +ffffffff82bf4508 r res_create_funcs +ffffffff82bf4538 r res_create_maximus_funcs +ffffffff82bf4568 r plane_cap +ffffffff82bf4594 r le_shift +ffffffff82bf4684 r le_mask +ffffffff82bf4a3c r link_enc_feature +ffffffff82bf4a50 r debug_defaults_drv +ffffffff82bf4bc8 r cs_shift +ffffffff82bf4bd4 r cs_mask +ffffffff82bf4bfc r hubbub_shift +ffffffff82bf4c84 r hubbub_mask +ffffffff82bf4ea0 r vmid_shifts +ffffffff82bf4ea8 r vmid_masks +ffffffff82bf4ec8 r hubp_shift +ffffffff82bf4fc4 r hubp_mask +ffffffff82bf53b4 r tf_shift +ffffffff82bf5684 r tf_mask +ffffffff82bf61c4 r opp_shift +ffffffff82bf61fc r opp_mask +ffffffff82bf62d0 r optc_shift +ffffffff82bf6390 r optc_mask +ffffffff82bf6690 r mpc_shift +ffffffff82bf676c r mpc_mask +ffffffff82bf6ad8 r dsc_shift +ffffffff82bf6b90 r dsc_mask +ffffffff82bf6e68 r dwbc30_shift +ffffffff82bf6f9c r dwbc30_mask +ffffffff82bf7464 r mcif_wb30_shift +ffffffff82bf7510 r mcif_wb30_mask +ffffffff82bf77bc r aux_mask +ffffffff82bf781c r aux_shift +ffffffff82bf7834 r i2c_shifts +ffffffff82bf7860 r i2c_masks +ffffffff82bf7904 r audio_shift +ffffffff82bf791c r audio_mask +ffffffff82bf7958 r se_shift +ffffffff82bf7a34 r se_mask +ffffffff82bf7da0 r vpg_shift +ffffffff82bf7dc8 r vpg_mask +ffffffff82bf7e5c r afmt_shift +ffffffff82bf7e70 r afmt_mask +ffffffff82bf7eb4 r hpo_dp_se_shift +ffffffff82bf7edc r hpo_dp_se_mask +ffffffff82bf7f7c r apg_shift +ffffffff82bf7f84 r apg_mask +ffffffff82bf7f9c r hpo_dp_le_shift +ffffffff82bf7fb8 r hpo_dp_le_mask +ffffffff82bf801c r hwseq_shift +ffffffff82bf809c r hwseq_mask +ffffffff82bfa000 R dcn10_soc_defaults +ffffffff82bfa08c R dcn10_ip_defaults +ffffffff82c05000 R dml20_funcs +ffffffff82c05030 R dml20v2_funcs +ffffffff82c05060 R dml21_funcs +ffffffff82c05090 R dml30_funcs +ffffffff82c050c0 R dml31_funcs +ffffffff82c050f0 R dml314_funcs +ffffffff82c05120 R dml32_funcs +ffffffff82c08000 R qp_table_422_10bpc_min +ffffffff82c08740 R qp_table_444_8bpc_max +ffffffff82c09080 R qp_table_420_12bpc_max +ffffffff82c097c0 R qp_table_444_10bpc_min +ffffffff82c0a400 R qp_table_420_8bpc_max +ffffffff82c0a840 R qp_table_444_8bpc_min +ffffffff82c0b180 R qp_table_444_12bpc_min +ffffffff82c0c0c0 R qp_table_420_12bpc_min +ffffffff82c0c800 R qp_table_422_12bpc_min +ffffffff82c0d140 R qp_table_422_12bpc_max +ffffffff82c0da80 R qp_table_444_12bpc_max +ffffffff82c0e9c0 R qp_table_420_8bpc_min +ffffffff82c0ee00 R qp_table_422_8bpc_min +ffffffff82c0f340 R qp_table_422_10bpc_max +ffffffff82c0fa80 R qp_table_420_10bpc_max +ffffffff82c10040 R qp_table_420_10bpc_min +ffffffff82c10600 R qp_table_444_10bpc_max +ffffffff82c11240 R qp_table_422_8bpc_max ffffffff82c13000 r funcs ffffffff82c13050 r hpd_regs -ffffffff82c13168 r hpd_shift -ffffffff82c13178 r hpd_mask -ffffffff82c13190 r ddc_data_regs_dcn -ffffffff82c13300 r ddc_clk_regs_dcn -ffffffff82c13470 r ddc_shift -ffffffff82c13560 r ddc_mask -ffffffff82c13650 r generic_regs -ffffffff82c136c0 r generic_shift -ffffffff82c136d0 r generic_mask +ffffffff82c131a0 r hpd_shift +ffffffff82c131b0 r hpd_mask +ffffffff82c131c0 r ddc_data_regs +ffffffff82c133a0 r ddc_clk_regs +ffffffff82c13580 r ddc_shift +ffffffff82c135a8 r ddc_mask ffffffff82c14000 r funcs ffffffff82c15000 r funcs ffffffff82c15050 r hpd_regs -ffffffff82c15168 r hpd_shift -ffffffff82c15178 r hpd_mask -ffffffff82c15190 r ddc_data_regs_dcn -ffffffff82c15340 r ddc_clk_regs_dcn -ffffffff82c154f0 r ddc_shift -ffffffff82c155e0 r ddc_mask -ffffffff82c156d0 r generic_regs -ffffffff82c15740 r generic_shift -ffffffff82c15750 r generic_mask +ffffffff82c151a0 r hpd_shift +ffffffff82c151b0 r hpd_mask +ffffffff82c151c0 r ddc_data_regs +ffffffff82c153a0 r ddc_clk_regs +ffffffff82c15580 r ddc_shift +ffffffff82c155a8 r ddc_mask ffffffff82c16000 r funcs ffffffff82c17000 r funcs +ffffffff82c17050 r hpd_regs +ffffffff82c171a0 r hpd_shift +ffffffff82c171b0 r hpd_mask +ffffffff82c171c0 r ddc_data_regs +ffffffff82c173a0 r ddc_clk_regs +ffffffff82c17580 r ddc_shift +ffffffff82c175a8 r ddc_mask ffffffff82c18000 r funcs ffffffff82c19000 r funcs -ffffffff82c1a000 r hdmi_14_protection -ffffffff82c1a010 r dp_11_protection -ffffffff82c1a020 r hdcp_i2c_offsets -ffffffff82c1a050 r hdcp_dpcd_addrs -ffffffff82c1b000 r irq_service_funcs_dce110 -ffffffff82c1b010 r irq_source_info_dce110 -ffffffff82c1c2a0 r dummy_irq_info_funcs -ffffffff82c1c2b0 r hpd_irq_info_funcs -ffffffff82c1c2c0 r hpd_rx_irq_info_funcs -ffffffff82c1c2d0 r pflip_irq_info_funcs -ffffffff82c1c2e0 r vupdate_irq_info_funcs -ffffffff82c1c2f0 r vblank_irq_info_funcs -ffffffff82c1d000 r irq_service_funcs_dce120 -ffffffff82c1d008 r dummy_irq_info_funcs -ffffffff82c1d018 r hpd_irq_info_funcs -ffffffff82c1d028 r hpd_rx_irq_info_funcs -ffffffff82c1d038 r pflip_irq_info_funcs -ffffffff82c1d048 r vupdate_irq_info_funcs -ffffffff82c1d058 r vblank_irq_info_funcs -ffffffff82c1d070 r irq_source_info_dce120 -ffffffff82c1f000 r irq_service_funcs_dce80 -ffffffff82c1f008 r dummy_irq_info_funcs -ffffffff82c1f018 r hpd_irq_info_funcs -ffffffff82c1f028 r hpd_rx_irq_info_funcs -ffffffff82c1f038 r pflip_irq_info_funcs -ffffffff82c1f048 r vupdate_irq_info_funcs -ffffffff82c1f058 r vblank_irq_info_funcs -ffffffff82c1f070 r irq_source_info_dce80 -ffffffff82c21000 r irq_service_funcs_dcn10 -ffffffff82c21008 r dummy_irq_info_funcs -ffffffff82c21018 r hpd_irq_info_funcs -ffffffff82c21028 r hpd_rx_irq_info_funcs -ffffffff82c21038 r pflip_irq_info_funcs -ffffffff82c21048 r vupdate_no_lock_irq_info_funcs -ffffffff82c21058 r vblank_irq_info_funcs -ffffffff82c21068 r vline0_irq_info_funcs -ffffffff82c21080 r irq_source_info_dcn10 -ffffffff82c23000 r irq_service_funcs_dcn20 -ffffffff82c23008 r dummy_irq_info_funcs -ffffffff82c23018 r hpd_irq_info_funcs -ffffffff82c23028 r hpd_rx_irq_info_funcs -ffffffff82c23038 r pflip_irq_info_funcs -ffffffff82c23048 r vupdate_no_lock_irq_info_funcs -ffffffff82c23058 r vblank_irq_info_funcs -ffffffff82c23068 r vline0_irq_info_funcs -ffffffff82c23080 r irq_source_info_dcn20 -ffffffff82c25000 r irq_service_funcs_dcn201 -ffffffff82c25008 r dummy_irq_info_funcs -ffffffff82c25018 r hpd_irq_info_funcs -ffffffff82c25028 r hpd_rx_irq_info_funcs -ffffffff82c25038 r pflip_irq_info_funcs -ffffffff82c25048 r vupdate_no_lock_irq_info_funcs -ffffffff82c25058 r vblank_irq_info_funcs -ffffffff82c25068 r vline0_irq_info_funcs -ffffffff82c25080 r irq_source_info_dcn201 -ffffffff82c27000 r irq_source_info_dcn21 -ffffffff82c28290 r irq_service_funcs_dcn21 -ffffffff82c28298 r dummy_irq_info_funcs -ffffffff82c282a8 r hpd_irq_info_funcs -ffffffff82c282b8 r hpd_rx_irq_info_funcs -ffffffff82c282c8 r pflip_irq_info_funcs -ffffffff82c282d8 r vupdate_no_lock_irq_info_funcs -ffffffff82c282e8 r vblank_irq_info_funcs -ffffffff82c282f8 r vline0_irq_info_funcs -ffffffff82c28308 r dmub_outbox_irq_info_funcs -ffffffff82c29000 r irq_source_info_dcn30 -ffffffff82c2a290 r irq_service_funcs_dcn30 -ffffffff82c2a298 r dummy_irq_info_funcs -ffffffff82c2a2a8 r hpd_irq_info_funcs -ffffffff82c2a2b8 r hpd_rx_irq_info_funcs -ffffffff82c2a2c8 r pflip_irq_info_funcs -ffffffff82c2a2d8 r vupdate_no_lock_irq_info_funcs -ffffffff82c2a2e8 r vblank_irq_info_funcs -ffffffff82c2a2f8 r vline0_irq_info_funcs -ffffffff82c2a308 r dmub_trace_irq_info_funcs -ffffffff82c2b000 r irq_source_info_dcn302 -ffffffff82c2c290 r irq_service_funcs_dcn302 -ffffffff82c2c298 r dummy_irq_info_funcs -ffffffff82c2c2a8 r hpd_irq_info_funcs -ffffffff82c2c2b8 r hpd_rx_irq_info_funcs -ffffffff82c2c2c8 r pflip_irq_info_funcs -ffffffff82c2c2d8 r vupdate_no_lock_irq_info_funcs -ffffffff82c2c2e8 r vblank_irq_info_funcs -ffffffff82c2c2f8 r vline0_irq_info_funcs -ffffffff82c2c308 r dmub_trace_irq_info_funcs -ffffffff82c2d000 r irq_service_funcs_dcn303 +ffffffff82c19050 r hpd_regs +ffffffff82c191a0 r hpd_shift +ffffffff82c191b0 r hpd_mask +ffffffff82c191c0 r ddc_data_regs +ffffffff82c193a0 r ddc_clk_regs +ffffffff82c19580 r ddc_shift +ffffffff82c195a8 r ddc_mask +ffffffff82c195d0 r generic_regs +ffffffff82c19640 r generic_shift +ffffffff82c19650 r generic_mask +ffffffff82c1a000 r funcs +ffffffff82c1b000 r funcs +ffffffff82c1b050 r hpd_regs +ffffffff82c1b1a0 r hpd_shift +ffffffff82c1b1b0 r hpd_mask +ffffffff82c1b1c0 r ddc_data_regs_dcn +ffffffff82c1b370 r ddc_clk_regs_dcn +ffffffff82c1b520 r ddc_shift +ffffffff82c1b640 r ddc_mask +ffffffff82c1b760 r generic_regs +ffffffff82c1b7d0 r generic_shift +ffffffff82c1b7e0 r generic_mask +ffffffff82c1c000 r funcs +ffffffff82c1d000 r funcs +ffffffff82c1d050 r hpd_regs +ffffffff82c1d168 r hpd_shift +ffffffff82c1d178 r hpd_mask +ffffffff82c1d190 r ddc_data_regs_dcn +ffffffff82c1d2c0 r ddc_clk_regs_dcn +ffffffff82c1d3f0 r ddc_shift +ffffffff82c1d4e0 r ddc_mask +ffffffff82c1d5d0 r generic_regs +ffffffff82c1d604 r generic_shift +ffffffff82c1d60c r generic_mask +ffffffff82c1e000 r funcs +ffffffff82c1f000 r funcs +ffffffff82c1f050 r hpd_regs +ffffffff82c1f1a0 r hpd_shift +ffffffff82c1f1b0 r hpd_mask +ffffffff82c1f1c0 r ddc_data_regs_dcn +ffffffff82c1f370 r ddc_clk_regs_dcn +ffffffff82c1f520 r ddc_shift +ffffffff82c1f640 r ddc_mask +ffffffff82c1f760 r generic_regs +ffffffff82c1f7d0 r generic_shift +ffffffff82c1f7e0 r generic_mask +ffffffff82c20000 r funcs +ffffffff82c21000 r funcs +ffffffff82c21050 r hpd_regs +ffffffff82c21168 r hpd_shift +ffffffff82c21178 r hpd_mask +ffffffff82c21190 r ddc_data_regs_dcn +ffffffff82c21300 r ddc_clk_regs_dcn +ffffffff82c21470 r ddc_shift +ffffffff82c21560 r ddc_mask +ffffffff82c21650 r generic_regs +ffffffff82c216c0 r generic_shift +ffffffff82c216d0 r generic_mask +ffffffff82c22000 r funcs +ffffffff82c23000 r funcs +ffffffff82c23050 r hpd_regs +ffffffff82c23168 r hpd_shift +ffffffff82c23178 r hpd_mask +ffffffff82c23190 r ddc_data_regs_dcn +ffffffff82c23340 r ddc_clk_regs_dcn +ffffffff82c234f0 r ddc_shift +ffffffff82c23610 r ddc_mask +ffffffff82c23730 r generic_regs +ffffffff82c237a0 r generic_shift +ffffffff82c237b0 r generic_mask +ffffffff82c24000 r funcs +ffffffff82c25000 r funcs +ffffffff82c26000 r funcs +ffffffff82c27000 r funcs +ffffffff82c28000 r hdmi_14_protection +ffffffff82c28010 r dp_11_protection +ffffffff82c28020 r hdcp_i2c_offsets +ffffffff82c28050 r hdcp_dpcd_addrs +ffffffff82c29000 r irq_service_funcs_dce110 +ffffffff82c29010 r irq_source_info_dce110 +ffffffff82c2a2a0 r dummy_irq_info_funcs +ffffffff82c2a2b0 r hpd_irq_info_funcs +ffffffff82c2a2c0 r hpd_rx_irq_info_funcs +ffffffff82c2a2d0 r pflip_irq_info_funcs +ffffffff82c2a2e0 r vupdate_irq_info_funcs +ffffffff82c2a2f0 r vblank_irq_info_funcs +ffffffff82c2b000 r irq_service_funcs_dce120 +ffffffff82c2b008 r dummy_irq_info_funcs +ffffffff82c2b018 r hpd_irq_info_funcs +ffffffff82c2b028 r hpd_rx_irq_info_funcs +ffffffff82c2b038 r pflip_irq_info_funcs +ffffffff82c2b048 r vupdate_irq_info_funcs +ffffffff82c2b058 r vblank_irq_info_funcs +ffffffff82c2b070 r irq_source_info_dce120 +ffffffff82c2d000 r irq_service_funcs_dce80 ffffffff82c2d008 r dummy_irq_info_funcs ffffffff82c2d018 r hpd_irq_info_funcs ffffffff82c2d028 r hpd_rx_irq_info_funcs ffffffff82c2d038 r pflip_irq_info_funcs -ffffffff82c2d048 r vupdate_no_lock_irq_info_funcs +ffffffff82c2d048 r vupdate_irq_info_funcs ffffffff82c2d058 r vblank_irq_info_funcs -ffffffff82c2d068 r vline0_irq_info_funcs -ffffffff82c2d080 r irq_source_info_dcn303 -ffffffff82c2f000 r irq_source_info_dcn31 -ffffffff82c30290 r irq_service_funcs_dcn31 -ffffffff82c30298 r dummy_irq_info_funcs -ffffffff82c302a8 r hpd_irq_info_funcs -ffffffff82c302b8 r hpd_rx_irq_info_funcs -ffffffff82c302c8 r pflip_irq_info_funcs -ffffffff82c302d8 r vupdate_no_lock_irq_info_funcs -ffffffff82c302e8 r vblank_irq_info_funcs -ffffffff82c302f8 r vline0_irq_info_funcs -ffffffff82c30308 r outbox_irq_info_funcs -ffffffff82c31000 r irq_source_info_dcn314 -ffffffff82c32290 r irq_service_funcs_dcn314 -ffffffff82c32298 r dummy_irq_info_funcs -ffffffff82c322a8 r hpd_irq_info_funcs -ffffffff82c322b8 r hpd_rx_irq_info_funcs -ffffffff82c322c8 r pflip_irq_info_funcs -ffffffff82c322d8 r vupdate_no_lock_irq_info_funcs -ffffffff82c322e8 r vblank_irq_info_funcs -ffffffff82c322f8 r vline0_irq_info_funcs -ffffffff82c32308 r outbox_irq_info_funcs -ffffffff82c33000 r irq_source_info_dcn315 -ffffffff82c34290 r irq_service_funcs_dcn315 -ffffffff82c34298 r dummy_irq_info_funcs -ffffffff82c342a8 r hpd_irq_info_funcs -ffffffff82c342b8 r hpd_rx_irq_info_funcs -ffffffff82c342c8 r pflip_irq_info_funcs -ffffffff82c342d8 r vupdate_no_lock_irq_info_funcs -ffffffff82c342e8 r vblank_irq_info_funcs -ffffffff82c342f8 r vline0_irq_info_funcs -ffffffff82c34308 r outbox_irq_info_funcs -ffffffff82c35000 r irq_source_info_dcn32 -ffffffff82c36290 r irq_service_funcs_dcn32 +ffffffff82c2d070 r irq_source_info_dce80 +ffffffff82c2f000 r irq_service_funcs_dcn10 +ffffffff82c2f008 r dummy_irq_info_funcs +ffffffff82c2f018 r hpd_irq_info_funcs +ffffffff82c2f028 r hpd_rx_irq_info_funcs +ffffffff82c2f038 r pflip_irq_info_funcs +ffffffff82c2f048 r vupdate_no_lock_irq_info_funcs +ffffffff82c2f058 r vblank_irq_info_funcs +ffffffff82c2f068 r vline0_irq_info_funcs +ffffffff82c2f080 r irq_source_info_dcn10 +ffffffff82c31000 r irq_service_funcs_dcn20 +ffffffff82c31008 r dummy_irq_info_funcs +ffffffff82c31018 r hpd_irq_info_funcs +ffffffff82c31028 r hpd_rx_irq_info_funcs +ffffffff82c31038 r pflip_irq_info_funcs +ffffffff82c31048 r vupdate_no_lock_irq_info_funcs +ffffffff82c31058 r vblank_irq_info_funcs +ffffffff82c31068 r vline0_irq_info_funcs +ffffffff82c31080 r irq_source_info_dcn20 +ffffffff82c33000 r irq_service_funcs_dcn201 +ffffffff82c33008 r dummy_irq_info_funcs +ffffffff82c33018 r hpd_irq_info_funcs +ffffffff82c33028 r hpd_rx_irq_info_funcs +ffffffff82c33038 r pflip_irq_info_funcs +ffffffff82c33048 r vupdate_no_lock_irq_info_funcs +ffffffff82c33058 r vblank_irq_info_funcs +ffffffff82c33068 r vline0_irq_info_funcs +ffffffff82c33080 r irq_source_info_dcn201 +ffffffff82c35000 r irq_source_info_dcn21 +ffffffff82c36290 r irq_service_funcs_dcn21 ffffffff82c36298 r dummy_irq_info_funcs ffffffff82c362a8 r hpd_irq_info_funcs ffffffff82c362b8 r hpd_rx_irq_info_funcs @@ -45166,9456 +45256,9525 @@ ffffffff82c362c8 r pflip_irq_info_funcs ffffffff82c362d8 r vupdate_no_lock_irq_info_funcs ffffffff82c362e8 r vblank_irq_info_funcs ffffffff82c362f8 r vline0_irq_info_funcs -ffffffff82c36308 r outbox_irq_info_funcs -ffffffff82c37000 r dio_link_hwss -ffffffff82c38000 r dpia_link_hwss -ffffffff82c39000 r hpo_dp_link_hwss -ffffffff82c3a000 r virtual_lnk_enc_funcs -ffffffff82c3b000 r virtual_link_hwss -ffffffff82c3c000 r virtual_str_enc_funcs -ffffffff82c3d000 R dmub_srv_dcn20_regs -ffffffff82c3e000 R dmub_srv_dcn21_regs -ffffffff82c3f000 R dmub_srv_dcn30_regs -ffffffff82c40000 R dmub_srv_dcn301_regs -ffffffff82c41000 R dmub_srv_dcn302_regs -ffffffff82c42000 R dmub_srv_dcn303_regs -ffffffff82c43000 R dmub_srv_dcn31_regs -ffffffff82c44000 R dmub_srv_dcn315_regs -ffffffff82c45000 R dmub_srv_dcn316_regs -ffffffff82c46000 R dmub_srv_dcn32_regs -ffffffff82c47000 r numerator01 -ffffffff82c47020 r numerator02 -ffffffff82c47040 r numerator04 -ffffffff82c47060 r numerator05 -ffffffff82c49000 r abm_settings -ffffffff82c49010 r abm_settings_config0 -ffffffff82c49050 r abm_settings_config1 -ffffffff82c49088 r min_reduction_table_v_2_2 -ffffffff82c49095 r max_reduction_table_v_2_2 -ffffffff82c490a2 r min_reduction_table -ffffffff82c490af r max_reduction_table -ffffffff82c4a000 R amdgpu_pp_profile_name -ffffffff82c4b000 r pp_lib_thermal_controller_names -ffffffff82c4c000 r pp_ip_funcs -ffffffff82c4c0a0 R pp_smu_ip_block -ffffffff82c4c0b8 r pp_dpm_funcs -ffffffff82c4d000 r gpio_tbl -ffffffff82c4d0f0 r enable_fb_req_rej_tbl -ffffffff82c4d140 r use_bclk_tbl -ffffffff82c4d310 r turn_off_plls_tbl -ffffffff82c4d640 r enter_baco_tbl -ffffffff82c4d730 r exit_baco_tbl -ffffffff82c4d850 r clean_baco_tbl -ffffffff82c4e000 r gpio_tbl -ffffffff82c4e0f0 r enable_fb_req_rej_tbl -ffffffff82c4e140 r use_bclk_tbl -ffffffff82c4e2e0 r turn_off_plls_tbl -ffffffff82c4e370 r clk_req_b_tbl -ffffffff82c4e490 r enter_baco_tbl -ffffffff82c4e5b0 r exit_baco_tbl -ffffffff82c4e6d0 r clean_baco_tbl -ffffffff82c4f000 r gpio_tbl -ffffffff82c4f0f0 r enable_fb_req_rej_tbl -ffffffff82c4f140 r use_bclk_tbl_vg -ffffffff82c4f200 r turn_off_plls_tbl_vg -ffffffff82c4f350 r use_bclk_tbl -ffffffff82c4f440 r turn_off_plls_tbl -ffffffff82c4f5f0 r clk_req_b_tbl -ffffffff82c4f710 r enter_baco_tbl -ffffffff82c4f830 r exit_baco_tbl -ffffffff82c4f950 r clean_baco_tbl -ffffffff82c50000 r vega10_fuses_default -ffffffff82c5f000 r pp_r600_encode_lanes -ffffffff82c60000 R pptable_v1_0_funcs -ffffffff82c61000 R pptable_funcs -ffffffff82c61020 r soft_dummy_pp_table -ffffffff82c62000 r smu10_hwmgr_funcs -ffffffff82c63000 r smu7_hwmgr_funcs -ffffffff82c632f8 r smu7_irq_funcs -ffffffff82c63310 r SMU7ThermalPolicy -ffffffff82c64000 r GCCACConfig_Polaris10 -ffffffff82c641b0 r DIDTConfig_Polaris10 -ffffffff82c64a50 r GCCACConfig_Polaris11 -ffffffff82c64c00 r DIDTConfig_Polaris11_Kicker -ffffffff82c654a0 r DIDTConfig_Polaris11 -ffffffff82c65d40 r DIDTConfig_Polaris12 -ffffffff82c665e0 r GCCACConfig_VegaM -ffffffff82c66790 r DIDTConfig_VegaM -ffffffff82c68000 r smu8_hwmgr_funcs -ffffffff82c682f0 r SMU7ThermalPolicy -ffffffff82c69000 r smu9_irq_funcs -ffffffff82c6a000 r gpio_tbl_iceland -ffffffff82c6a060 r gpio_tbl -ffffffff82c6a150 r enable_fb_req_rej_tbl -ffffffff82c6a1a0 r use_bclk_tbl -ffffffff82c6a370 r turn_off_plls_tbl -ffffffff82c6a610 r enter_baco_tbl -ffffffff82c6a730 r exit_baco_tbl_iceland -ffffffff82c6a870 r clean_baco_tbl_iceland -ffffffff82c6a890 r exit_baco_tbl -ffffffff82c6a9b0 r clean_baco_tbl -ffffffff82c6b000 r pre_baco_tbl -ffffffff82c6b090 r enter_baco_tbl -ffffffff82c6b2b0 r exit_baco_tbl -ffffffff82c6b520 r clean_baco_tbl -ffffffff82c6c000 r vega10_hwmgr_funcs -ffffffff82c6c2f0 r channel_number -ffffffff82c6c320 r SMU7ThermalWithDelayPolicy -ffffffff82c6d000 r SEDiDtStallCtrlConfig_vega10 -ffffffff82c6d110 r SEDiDtStallPatternConfig_vega10 -ffffffff82c6d2e0 r SEDiDtWeightConfig_Vega10 -ffffffff82c6d3b0 r SEDiDtCtrl1Config_Vega10 -ffffffff82c6d440 r SEDiDtCtrl2Config_Vega10 -ffffffff82c6d510 r SEDiDtCtrl3Config_vega10 -ffffffff82c6d820 r SEDiDtTuningCtrlConfig_Vega10 -ffffffff82c6d8b0 r SELCacConfig_Vega10 -ffffffff82c6da40 r SEDiDtCtrl0Config_Vega10 -ffffffff82c6dd10 r AvfsPSMInitConfig_vega10 -ffffffff82c6dd90 r SEEDCStallPatternConfig_Vega10 -ffffffff82c6dea0 r SEEDCStallDelayConfig_Vega10 -ffffffff82c6df80 r SEEDCCtrlConfig_Vega10 -ffffffff82c6e040 r PSMSEEDCStallPatternConfig_Vega10 -ffffffff82c6e0c0 r PSMSEEDCStallDelayConfig_Vega10 -ffffffff82c6e1d0 r PSMSEEDCCtrlResetConfig_Vega10 -ffffffff82c6e290 r PSMSEEDCCtrlConfig_Vega10 -ffffffff82c6e350 r SEEDCForceStallPatternConfig_Vega10 -ffffffff82c6e3e0 r SEEDCCtrlForceStallConfig_Vega10 -ffffffff82c6f000 R vega10_pptable_funcs -ffffffff82c70000 r pre_baco_tbl -ffffffff82c70090 r enter_baco_tbl -ffffffff82c702b0 r exit_baco_tbl -ffffffff82c70520 r clean_baco_tbl -ffffffff82c71000 r vega12_hwmgr_funcs -ffffffff82c712f0 r SMU7ThermalWithDelayPolicy -ffffffff82c71340 r link_width -ffffffff82c72000 R vega12_pptable_funcs -ffffffff82c73000 r clean_baco_tbl -ffffffff82c74000 r vega20_hwmgr_funcs -ffffffff82c742f0 r SMU7ThermalWithDelayPolicy -ffffffff82c74340 r link_width -ffffffff82c75000 R vega20_pptable_funcs -ffffffff82c76000 R ci_smu_funcs -ffffffff82c760e0 r defaults_hawaii_pro -ffffffff82c7612c r defaults_hawaii_xt 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ip6_defmcasthlim -ffffffff8317400c D ip6_maxfragpackets -ffffffff83174010 D ip6_maxfrags -ffffffff83174014 D ip6_log_interval -ffffffff83174018 D ip6_hdrnestlimit -ffffffff8317401c D ip6_dad_count -ffffffff83174020 D ip6_auto_flowlabel -ffffffff83174024 D ip6_use_deprecated -ffffffff83174028 D ip6_neighborgcthresh -ffffffff8317402c D ip6_maxdynroutes -ffffffff83174030 D rip6_sendspace -ffffffff83174038 D rip6_recvspace -ffffffff83174040 D icmp6_redirtimeout -ffffffff83174044 D icmp6errppslim -ffffffff83174048 D ip6_mtudisc_timeout -ffffffff83175000 D frag6_mutex -ffffffff83176000 d icmp6_mtudisc_hiwat -ffffffff83176004 d icmp6_mtudisc_lowat -ffffffff83177000 d randomtab_20 -ffffffff83178000 D ip6intrq -ffffffff83178038 d ip6send_task -ffffffff83179000 D nd6_timer_next -ffffffff83179008 D nd6_expire_next -ffffffff83179010 D nd6_delay -ffffffff83179014 D nd6_umaxtries -ffffffff83179018 D nd6_mmaxtries -ffffffff8317901c D nd6_gctimer -ffffffff83179020 D nd6_maxndopt -ffffffff8317a000 d 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amdgpu_pp_profile_name +ffffffff82c59000 r pp_lib_thermal_controller_names +ffffffff82c5a000 r pp_ip_funcs +ffffffff82c5a0a0 R pp_smu_ip_block +ffffffff82c5a0b8 r pp_dpm_funcs +ffffffff82c5b000 r gpio_tbl +ffffffff82c5b0f0 r enable_fb_req_rej_tbl +ffffffff82c5b140 r use_bclk_tbl +ffffffff82c5b310 r turn_off_plls_tbl +ffffffff82c5b640 r enter_baco_tbl +ffffffff82c5b730 r exit_baco_tbl +ffffffff82c5b850 r clean_baco_tbl +ffffffff82c5c000 r gpio_tbl +ffffffff82c5c0f0 r enable_fb_req_rej_tbl +ffffffff82c5c140 r use_bclk_tbl +ffffffff82c5c2e0 r turn_off_plls_tbl +ffffffff82c5c370 r clk_req_b_tbl +ffffffff82c5c490 r enter_baco_tbl +ffffffff82c5c5b0 r exit_baco_tbl +ffffffff82c5c6d0 r clean_baco_tbl +ffffffff82c5d000 r gpio_tbl +ffffffff82c5d0f0 r enable_fb_req_rej_tbl +ffffffff82c5d140 r use_bclk_tbl_vg +ffffffff82c5d200 r turn_off_plls_tbl_vg +ffffffff82c5d350 r use_bclk_tbl +ffffffff82c5d440 r turn_off_plls_tbl +ffffffff82c5d5f0 r clk_req_b_tbl +ffffffff82c5d710 r enter_baco_tbl +ffffffff82c5d830 r exit_baco_tbl +ffffffff82c5d950 r clean_baco_tbl +ffffffff82c5e000 r vega10_fuses_default +ffffffff82c6d000 r pp_r600_encode_lanes +ffffffff82c6e000 R pptable_v1_0_funcs +ffffffff82c6f000 R pptable_funcs +ffffffff82c6f020 r soft_dummy_pp_table +ffffffff82c70000 r smu10_hwmgr_funcs +ffffffff82c71000 r smu7_hwmgr_funcs +ffffffff82c712f8 r smu7_irq_funcs +ffffffff82c71310 r SMU7ThermalPolicy +ffffffff82c72000 r GCCACConfig_Polaris10 +ffffffff82c721b0 r DIDTConfig_Polaris10 +ffffffff82c72a50 r GCCACConfig_Polaris11 +ffffffff82c72c00 r DIDTConfig_Polaris11_Kicker +ffffffff82c734a0 r DIDTConfig_Polaris11 +ffffffff82c73d40 r DIDTConfig_Polaris12 +ffffffff82c745e0 r GCCACConfig_VegaM +ffffffff82c74790 r DIDTConfig_VegaM +ffffffff82c76000 r smu8_hwmgr_funcs +ffffffff82c762f0 r SMU7ThermalPolicy +ffffffff82c77000 r smu9_irq_funcs +ffffffff82c78000 r gpio_tbl_iceland +ffffffff82c78060 r gpio_tbl +ffffffff82c78150 r enable_fb_req_rej_tbl +ffffffff82c781a0 r use_bclk_tbl +ffffffff82c78370 r turn_off_plls_tbl +ffffffff82c78610 r enter_baco_tbl +ffffffff82c78730 r exit_baco_tbl_iceland +ffffffff82c78870 r clean_baco_tbl_iceland +ffffffff82c78890 r exit_baco_tbl +ffffffff82c789b0 r clean_baco_tbl +ffffffff82c79000 r pre_baco_tbl +ffffffff82c79090 r enter_baco_tbl +ffffffff82c792b0 r exit_baco_tbl +ffffffff82c79520 r clean_baco_tbl +ffffffff82c7a000 r vega10_hwmgr_funcs +ffffffff82c7a2f0 r channel_number +ffffffff82c7a320 r SMU7ThermalWithDelayPolicy +ffffffff82c7b000 r SEDiDtStallCtrlConfig_vega10 +ffffffff82c7b110 r SEDiDtStallPatternConfig_vega10 +ffffffff82c7b2e0 r SEDiDtWeightConfig_Vega10 +ffffffff82c7b3b0 r SEDiDtCtrl1Config_Vega10 +ffffffff82c7b440 r SEDiDtCtrl2Config_Vega10 +ffffffff82c7b510 r SEDiDtCtrl3Config_vega10 +ffffffff82c7b820 r SEDiDtTuningCtrlConfig_Vega10 +ffffffff82c7b8b0 r SELCacConfig_Vega10 +ffffffff82c7ba40 r SEDiDtCtrl0Config_Vega10 +ffffffff82c7bd10 r AvfsPSMInitConfig_vega10 +ffffffff82c7bd90 r SEEDCStallPatternConfig_Vega10 +ffffffff82c7bea0 r SEEDCStallDelayConfig_Vega10 +ffffffff82c7bf80 r SEEDCCtrlConfig_Vega10 +ffffffff82c7c040 r PSMSEEDCStallPatternConfig_Vega10 +ffffffff82c7c0c0 r PSMSEEDCStallDelayConfig_Vega10 +ffffffff82c7c1d0 r PSMSEEDCCtrlResetConfig_Vega10 +ffffffff82c7c290 r PSMSEEDCCtrlConfig_Vega10 +ffffffff82c7c350 r SEEDCForceStallPatternConfig_Vega10 +ffffffff82c7c3e0 r SEEDCCtrlForceStallConfig_Vega10 +ffffffff82c7d000 R vega10_pptable_funcs +ffffffff82c7e000 r pre_baco_tbl +ffffffff82c7e090 r enter_baco_tbl +ffffffff82c7e2b0 r exit_baco_tbl +ffffffff82c7e520 r clean_baco_tbl +ffffffff82c7f000 r vega12_hwmgr_funcs +ffffffff82c7f2f0 r SMU7ThermalWithDelayPolicy +ffffffff82c7f340 r link_width +ffffffff82c80000 R vega12_pptable_funcs +ffffffff82c81000 r clean_baco_tbl +ffffffff82c82000 r vega20_hwmgr_funcs +ffffffff82c822f0 r SMU7ThermalWithDelayPolicy +ffffffff82c82340 r link_width +ffffffff82c83000 R vega20_pptable_funcs +ffffffff82c84000 R ci_smu_funcs +ffffffff82c840e0 r defaults_hawaii_pro +ffffffff82c8412c r defaults_hawaii_xt +ffffffff82c84178 r defaults_saturn_xt +ffffffff82c841c4 r defaults_bonaire_xt +ffffffff82c84210 r ci_program_jump_on_start.data +ffffffff82c85000 R fiji_smu_funcs +ffffffff82c850e0 r avfs_graphics_level +ffffffff82c85240 r fiji_power_tune_data_set_array +ffffffff82c85246 r fiji_clock_stretch_amount_conversion +ffffffff82c85260 r fiji_clock_stretcher_ddt_table +ffffffff82c86000 R iceland_smu_funcs +ffffffff82c860e0 r defaults_icelandxt +ffffffff82c8612c r defaults_icelandpro +ffffffff82c86178 r defaults_iceland +ffffffff82c87000 R polaris10_smu_funcs +ffffffff82c870e0 r avfs_graphics_level_polaris10 +ffffffff82c872a0 r avfs_memory_level_polaris10 +ffffffff82c872c0 r polaris10_power_tune_data_set_array +ffffffff82c87310 r Range_Table +ffffffff82c88000 R smu10_smu_funcs +ffffffff82c89000 r smu7_program_jump_on_start.data +ffffffff82c89010 r pwr_virus_table_pre +ffffffff82c89680 r pwr_virus_table_post +ffffffff82c89f80 r pwr_virus_section1 +ffffffff82c8a610 r pwr_virus_section2 +ffffffff82c8a660 r pwr_virus_section3 +ffffffff82c91ab0 r pwr_virus_section4 +ffffffff82c91e80 r pwr_virus_section5 +ffffffff82c92490 r pwr_virus_section6 +ffffffff82c94000 R smu8_smu_funcs +ffffffff82c95000 R tonga_smu_funcs +ffffffff82c950e0 r tonga_power_tune_data_set_array +ffffffff82c9512c r tonga_clock_stretch_amount_conversion +ffffffff82c95140 r tonga_clock_stretcher_ddt_table +ffffffff82c96000 R vega10_smu_funcs +ffffffff82c97000 R vega12_smu_funcs +ffffffff82c98000 R vega20_smu_funcs +ffffffff82c99000 R vegam_smu_funcs +ffffffff82c990e0 r vegam_power_tune_data_set_array +ffffffff82c99130 r Range_Table +ffffffff82c9a000 R smu_ip_funcs +ffffffff82c9a0a0 R smu_v11_0_ip_block +ffffffff82c9a0b8 R smu_v12_0_ip_block +ffffffff82c9a0d0 R smu_v13_0_ip_block +ffffffff82c9a0e8 r swsmu_pm_funcs +ffffffff82c9b000 r arcturus_table_map +ffffffff82c9b080 r arcturus_pwr_src_map +ffffffff82c9b090 r arcturus_workload_map +ffffffff82c9b0d0 r arcturus_ppt_funcs +ffffffff82c9b4a0 r smu11_thermal_policy +ffffffff82c9b4f0 r arcturus_i2c_algo +ffffffff82c9b500 r arcturus_i2c_control_quirks +ffffffff82c9b510 r arcturus_throttler_map +ffffffff82c9b530 r arcturus_message_map +ffffffff82c9bf80 r arcturus_clk_map +ffffffff82c9c040 r arcturus_feature_mask_map +ffffffff82c9d000 r cyan_skillfish_ppt_funcs +ffffffff82c9e000 r navi10_ppt_funcs +ffffffff82c9e3d0 r smu11_thermal_policy +ffffffff82c9e420 r navi10_i2c_algo +ffffffff82c9e430 r navi10_i2c_control_quirks +ffffffff82c9e440 r navi1x_throttler_map +ffffffff82c9e460 r NoDbiPrbs7 +ffffffff82c9f460 r DbiPrbs7 +ffffffff82ca1000 r sienna_cichlid_ppt_funcs +ffffffff82ca13d0 r smu11_thermal_policy +ffffffff82ca1420 r sienna_cichlid_i2c_algo +ffffffff82ca1430 r sienna_cichlid_i2c_control_quirks +ffffffff82ca1440 r sienna_cichlid_throttler_map +ffffffff82ca2000 r smu_v11_0_irq_funcs +ffffffff82ca2010 r link_width +ffffffff82ca3000 r vangogh_ppt_funcs +ffffffff82ca33d0 r vangogh_throttler_map +ffffffff82ca4000 r renoir_ppt_funcs +ffffffff82ca43d0 r renoir_throttler_map +ffffffff82ca5000 r aldebaran_clk_map +ffffffff82ca50c0 r aldebaran_table_map +ffffffff82ca5140 r aldebaran_ppt_funcs +ffffffff82ca5510 r smu13_thermal_policy +ffffffff82ca5560 r aldebaran_i2c_algo +ffffffff82ca5570 r aldebaran_i2c_control_quirks +ffffffff82ca5580 r aldebaran_throttler_map +ffffffff82ca55a0 r aldebaran_message_map +ffffffff82ca5ff0 r aldebaran_feature_mask_map +ffffffff82ca7000 r smu_v13_0_irq_funcs +ffffffff82ca7010 r link_width +ffffffff82ca8000 r smu_v13_0_0_ppt_funcs +ffffffff82ca83d0 r smu13_thermal_policy +ffffffff82ca8420 r smu_v13_0_0_i2c_algo +ffffffff82ca8430 r smu_v13_0_0_i2c_control_quirks +ffffffff82ca8440 r smu_v13_0_0_throttler_map +ffffffff82ca9000 r smu_v13_0_4_ppt_funcs +ffffffff82caa000 r smu_v13_0_5_ppt_funcs +ffffffff82cab000 r smu_v13_0_7_ppt_funcs +ffffffff82cab3d0 r smu13_thermal_policy +ffffffff82cab420 r smu_v13_0_7_throttler_map +ffffffff82cac000 r yellow_carp_ppt_funcs +ffffffff82cad000 r __smu_message_names +ffffffff82cae000 R pchb_ca +ffffffff82caf000 R amas_ca +ffffffff82caf028 R amas_devices +ffffffff82caf040 r amas_feature +ffffffff82cb0000 R cardslot_ca +ffffffff82cb1000 R cardbus_ca +ffffffff82cb2000 R com_cardbus_ca +ffffffff82cb3000 R xl_cardbus_ca +ffffffff82cb3030 R xl_cardbus_products +ffffffff82cb4000 R dc_cardbus_ca +ffffffff82cb4030 R dc_cardbus_devices +ffffffff82cb5000 R fxp_cardbus_ca +ffffffff82cb5028 R fxp_cardbus_devices +ffffffff82cb6000 R rl_cardbus_devices +ffffffff82cb6028 R rl_cardbus_ca +ffffffff82cb7000 R re_cardbus_ca +ffffffff82cb7028 R re_cardbus_devices +ffffffff82cb8000 R ath_cardbus_ca +ffffffff82cb9000 R athn_cardbus_ca +ffffffff82cb9030 r athn_cardbus_devices +ffffffff82cba000 R atw_cardbus_ca +ffffffff82cba028 R atw_cardbus_devices +ffffffff82cbb000 R rtw_cardbus_ca +ffffffff82cbb028 R rtw_cardbus_devices +ffffffff82cbc000 R ral_cardbus_ca +ffffffff82cbc030 r ral_cardbus_devices +ffffffff82cbd000 R acx_cardbus_ca +ffffffff82cbd028 r acx_cardbus_devices +ffffffff82cbe000 R pgt_cardbus_ca +ffffffff82cbe028 R pgt_cardbus_devices +ffffffff82cbf000 R ehci_cardbus_ca +ffffffff82cc0000 R ohci_cardbus_ca +ffffffff82cc1000 R uhci_cardbus_ca +ffffffff82cc2000 R malo_cardbus_ca +ffffffff82cc2028 r malo_cardbus_devices +ffffffff82cc3000 R bwi_cardbus_ca +ffffffff82cc3030 r bwi_cardbus_devices +ffffffff82cc4000 R pcmcia_ca +ffffffff82cc5000 r pcmcia_parse_cis_tuple.init_cfe +ffffffff82cc6000 r pcmcia_cis_quirks +ffffffff82cc7000 R ep_pcmcia_ca +ffffffff82cc8000 R ne_pcmcia_ca +ffffffff82cc8030 R ne2000devs +ffffffff82cca000 R aic_pcmcia_ca +ffffffff82ccb000 R com_pcmcia_ca +ffffffff82ccc000 R wdc_pcmcia_ca +ffffffff82ccd000 R sm_pcmcia_ca +ffffffff82cce000 R xe_pcmcia_ca +ffffffff82ccf000 R wi_pcmcia_ca +ffffffff82ccf030 r wi_pcmcia_products +ffffffff82cd0000 R malo_pcmcia_ca +ffffffff82cd1000 R an_pcmcia_ca +ffffffff82cd2000 R pcib_ca +ffffffff82cd3000 R amdpcib_ca +ffffffff82cd3028 R amdpcib_devices +ffffffff82cd4000 R tcpcib_ca +ffffffff82cd4028 R tcpcib_devices +ffffffff82cd5000 R aapic_ca +ffffffff82cd6000 R hme_pci_ca +ffffffff82cd6028 r hme_promhdr +ffffffff82cd602a r hme_promdat +ffffffff82cd7000 R isa_ca +ffffffff82cd8000 R isadma_ca +ffffffff82cd9000 R fdc_ca +ffffffff82cda000 R fd_ca +ffffffff82cdb000 R com_isa_ca +ffffffff82cdc000 R pckbc_isa_ca +ffffffff82cdd000 R vga_isa_ca +ffffffff82cde000 R wdc_isa_ca +ffffffff82cdf000 R mpu_midi_hw_if +ffffffff82ce0000 R mpu_isa_ca +ffffffff82ce1000 R pcppi_ca +ffffffff82ce2000 R spkr_ca +ffffffff82ce2030 r pitchtab +ffffffff82ce3000 R lpt_isa_ca +ffffffff82ce4000 R wbsio_ca +ffffffff82ce5000 R schsio_ca +ffffffff82ce6000 R lm_isa_ca +ffffffff82ce6028 R lm_wbsio_ca +ffffffff82ce7000 R it_sensors +ffffffff82ce7110 R it_vrfact +ffffffff82ce7140 R it_fan_regs +ffffffff82ce7160 R it_fan_ext_regs +ffffffff82ce7178 R it_ca +ffffffff82ce8000 R abitkv_sensors +ffffffff82ce8200 R abitaa_sensors +ffffffff82ce8480 R abitav_sensors +ffffffff82ce8700 R abitas_sensors +ffffffff82ce8980 R abitax_sensors +ffffffff82ce8bc0 R abitm4_sensors +ffffffff82ce8e80 R abitan_sensors +ffffffff82ce9120 R abital_sensors +ffffffff82ce93a0 R abitaw_sensors +ffffffff82ce9700 R abitni_sensors +ffffffff82ce99a0 R abitat_sensors +ffffffff82ce9cc0 R abitan2_sensors +ffffffff82ce9f60 R abitab_sensors +ffffffff82cea220 R abitan3_sensors +ffffffff82cea500 R abitaw2_sensors +ffffffff82cea860 R abitat2_sensors +ffffffff82ceab60 R abitab2_sensors +ffffffff82ceaea0 R abitin_sensors +ffffffff82ceb1e0 R uguru_ca +ffffffff82cec000 R aps_ca +ffffffff82ced000 R wsdisplay_emul_ca +ffffffff82ced030 r charClass +ffffffff82cee000 r usl_syncops +ffffffff82cef000 R wsevent_filtops +ffffffff82cf0000 R wskbd_ca +ffffffff82cf1000 r latin1_to_upper +ffffffff82cf2000 R wsmouse_ca +ffffffff82cf3000 R cyrillic_to_koi8 +ffffffff82cf3060 R unicode_to_latin2 +ffffffff82cf30e0 R unicode_to_latin7 +ffffffff82cf4000 R wsemul_vt100_ops +ffffffff82cf5000 r decspcgr2uni +ffffffff82cf5100 r dectech2uni +ffffffff82cf5200 r nrctable +ffffffff82cf5320 r nrcovlpos +ffffffff82cf6000 r vt100_fkeys +ffffffff82cf60c0 r vt100_pfkeys +ffffffff82cf60e0 r vt100_numpad +ffffffff82cf7000 R pckbd_ca +ffffffff82cf7028 R pckbd_accessops +ffffffff82cf7040 R pckbd_consops +ffffffff82cf7060 R pckbd_keymapdata +ffffffff82cf7070 R pckbd_xtbl +ffffffff82cf7100 R pckbd_xtbl_ext +ffffffff82cf8000 r pckbd_keydesc_us +ffffffff82cf8250 r pckbd_keydesc_de +ffffffff82cf82f0 r pckbd_keydesc_de_nodead +ffffffff82cf8310 r pckbd_keydesc_fr +ffffffff82cf83d0 r pckbd_keydesc_fr_dvorak_bepo +ffffffff82cf8510 r pckbd_keydesc_dk +ffffffff82cf85a0 r pckbd_keydesc_dk_nodead +ffffffff82cf85b0 r pckbd_keydesc_it +ffffffff82cf8640 r pckbd_keydesc_uk +ffffffff82cf86e0 r pckbd_keydesc_jp +ffffffff82cf8750 r pckbd_keydesc_sv +ffffffff82cf8780 r pckbd_keydesc_sv_nodead +ffffffff82cf8790 r pckbd_keydesc_no +ffffffff82cf87c0 r pckbd_keydesc_no_nodead +ffffffff82cf87d0 r pckbd_keydesc_us_declk +ffffffff82cf8860 r pckbd_keydesc_us_dvorak +ffffffff82cf8900 r pckbd_keydesc_us_colemak +ffffffff82cf8948 r pckbd_keydesc_swapctrlcaps +ffffffff82cf8960 r pckbd_keydesc_iopener +ffffffff82cf89b0 r pckbd_keydesc_es +ffffffff82cf8a50 r pckbd_keydesc_be +ffffffff82cf8b10 r pckbd_keydesc_ru +ffffffff82cf8c80 r pckbd_keydesc_ua +ffffffff82cf8e10 r pckbd_keydesc_sg +ffffffff82cf8ec0 r pckbd_keydesc_sg_nodead +ffffffff82cf8ee0 r pckbd_keydesc_sf +ffffffff82cf8f00 r pckbd_keydesc_pt +ffffffff82cf8f90 r pckbd_keydesc_lt +ffffffff82cf9070 r pckbd_keydesc_la +ffffffff82cf9100 r pckbd_keydesc_br +ffffffff82cf9180 r pckbd_keydesc_tr +ffffffff82cf9230 r pckbd_keydesc_tr_nodead +ffffffff82cf9250 r pckbd_keydesc_pl +ffffffff82cf92b0 r pckbd_keydesc_hu +ffffffff82cf93c0 r pckbd_keydesc_si +ffffffff82cf94d0 r pckbd_keydesc_cf +ffffffff82cf95a0 r pckbd_keydesc_cf_nodead +ffffffff82cf95c0 r pckbd_keydesc_lv +ffffffff82cf9640 r pckbd_keydesc_nl +ffffffff82cf9720 r pckbd_keydesc_nl_nodead +ffffffff82cf9740 r pckbd_keydesc_is +ffffffff82cf97cc r pckbd_keydesc_is_nodead +ffffffff82cf97e0 r pckbd_keydesc_ee +ffffffff82cf9890 r pckbd_keydesc_ee_nodead +ffffffff82cf98b0 R pckbd_keydesctab +ffffffff82cfa000 R pms_ca +ffffffff82cfa028 R pms_accessops +ffffffff82cfa040 R pms_sec_accessops +ffffffff82cfa060 R pms_protocols +ffffffff82cfa1e0 r alps_models +ffffffff82cfb000 R skgpio_led_offset +ffffffff82cfb008 R skgpio_ca +ffffffff82cfc000 R hidkbd_trtab +ffffffff82cfc100 r apple_fn_trans +ffffffff82cfc120 r apple_tb_trans +ffffffff82cfc140 r apple_mba_trans +ffffffff82cfd000 r hidcc_attach_wskbd.accessops +ffffffff82cfd020 r hidcc_keysyms +ffffffff82cfe000 R usb_ca +ffffffff82cff000 R usb_known_products +ffffffff82d0ae60 R usb_known_vendors +ffffffff82d0d660 R usbd_error_strs +ffffffff82d0e000 R usb_quirks +ffffffff82d0e390 R usb_dev_quirks +ffffffff82d0e398 R usbd_no_quirk +ffffffff82d0f000 R uhub_ca +ffffffff82d0f028 R uhub_uhub_ca +ffffffff82d10000 R uaudio_ca +ffffffff82d10028 R uaudio_hw_if +ffffffff82d100e0 R uaudio_rates +ffffffff82d10120 r uaudio_clkname.names +ffffffff82d10140 r uaudio_feature_addent.features +ffffffff82d11000 R uvideo_ca +ffffffff82d11028 R uvideo_hw_if +ffffffff82d11100 R uvideo_devs +ffffffff82d12000 r utvfu_select_norm.pal +ffffffff82d12040 r utvfu_select_norm.ntsc +ffffffff82d12080 r utvfu_setup_capture.setup +ffffffff82d12180 r utvfu_audio_start_chip.setup +ffffffff82d121c8 r utvfu_audio_stop_chip.setup +ffffffff82d121d8 R utvfu_ca +ffffffff82d12200 R utvfu_vid_hw_if +ffffffff82d122d0 R utvfu_au_hw_if +ffffffff82d13000 R udl_ca +ffffffff82d13030 r udl_devs +ffffffff82d130b0 r udl_modes +ffffffff82d14000 R umidi_hw_if +ffffffff82d14030 R umidi_ca +ffffffff82d14060 r umidi_evlen +ffffffff82d14080 r packet_length +ffffffff82d15000 r quirk_name +ffffffff82d16000 R ucom_ca +ffffffff82d17000 R ugen_ca +ffffffff82d17028 R ugenread_intr_filtops +ffffffff82d17058 R ugenread_isoc_filtops +ffffffff82d18000 R uhidev_ca +ffffffff82d18030 r uhid_graphire_report_descr +ffffffff82d180b0 r uhid_graphire3_4x5_report_descr +ffffffff82d18160 r uhid_xb360gp_report_descr +ffffffff82d18210 r uhid_xbonegp_report_descr +ffffffff82d19000 R uhid_ca +ffffffff82d19028 R uhidread_filtops +ffffffff82d1a000 R fido_ca +ffffffff82d1b000 R ujoy_ca +ffffffff82d1c000 r ukbd_keydesc_us +ffffffff82d1c290 r ukbd_keydesc_de +ffffffff82d1c340 r ukbd_keydesc_de_nodead +ffffffff82d1c360 r ukbd_keydesc_fr +ffffffff82d1c420 r ukbd_keydesc_fr_apple +ffffffff82d1c560 r ukbd_keydesc_fr_dvorak_bepo +ffffffff82d1c6a0 r ukbd_keydesc_dk +ffffffff82d1c740 r ukbd_keydesc_dk_nodead +ffffffff82d1c750 r ukbd_keydesc_it +ffffffff82d1c7f0 r ukbd_keydesc_uk +ffffffff82d1c8a0 r ukbd_keydesc_jp +ffffffff82d1c910 r ukbd_keydesc_sv +ffffffff82d1c940 r ukbd_keydesc_sv_nodead +ffffffff82d1c950 r ukbd_keydesc_no +ffffffff82d1c980 r ukbd_keydesc_no_nodead +ffffffff82d1c990 r ukbd_keydesc_us_dvorak +ffffffff82d1ca30 r ukbd_keydesc_us_colemak +ffffffff82d1ca78 r ukbd_keydesc_swapctrlcaps +ffffffff82d1ca90 r ukbd_keydesc_iopener +ffffffff82d1cae0 r ukbd_keydesc_es +ffffffff82d1cb80 r ukbd_keydesc_be +ffffffff82d1cc40 r ukbd_keydesc_ru +ffffffff82d1cdb0 r ukbd_keydesc_ua +ffffffff82d1cf50 r ukbd_keydesc_sg +ffffffff82d1d010 r ukbd_keydesc_sg_nodead +ffffffff82d1d030 r ukbd_keydesc_sf +ffffffff82d1d050 r ukbd_keydesc_pt +ffffffff82d1d0e0 r ukbd_keydesc_pt_apple +ffffffff82d1d100 r ukbd_keydesc_lt +ffffffff82d1d1e0 r ukbd_keydesc_la +ffffffff82d1d280 r ukbd_keydesc_br +ffffffff82d1d310 r ukbd_keydesc_tr +ffffffff82d1d3d0 r ukbd_keydesc_tr_nodead +ffffffff82d1d3f0 r ukbd_keydesc_pl +ffffffff82d1d450 r ukbd_keydesc_hu +ffffffff82d1d560 r ukbd_keydesc_si +ffffffff82d1d680 r ukbd_keydesc_cf +ffffffff82d1d760 r ukbd_keydesc_cf_nodead +ffffffff82d1d780 r ukbd_keydesc_lv +ffffffff82d1d800 r ukbd_keydesc_nl +ffffffff82d1d8e0 r ukbd_keydesc_nl_nodead +ffffffff82d1d900 r ukbd_keydesc_is +ffffffff82d1d994 r ukbd_keydesc_is_nodead +ffffffff82d1d9a0 r ukbd_keydesc_ee +ffffffff82d1da50 r ukbd_keydesc_ee_nodead +ffffffff82d1da70 R ukbd_keydesctab +ffffffff82d1e000 R ukbd_countrylayout +ffffffff82d1e090 R ukbd_consops +ffffffff82d1e0b0 R ukbd_accessops +ffffffff82d1e0c8 R ukbd_ca +ffffffff82d1f000 R ums_accessops +ffffffff82d1f018 R ums_ca +ffffffff82d20000 R umt_accessops +ffffffff82d20018 R umt_ca +ffffffff82d21000 R uts_devs +ffffffff82d21010 R uts_accessops +ffffffff82d21028 R uts_ca +ffffffff82d22000 R ubcmtp_accessops +ffffffff82d22018 R ubcmtp_ca +ffffffff82d22040 r ubcmtp_devices +ffffffff82d23000 R ucycom_methods +ffffffff82d23040 R ucycom_devs +ffffffff82d23050 R ucycom_ca +ffffffff82d24000 R uslhcom_methods +ffffffff82d24040 R uslhcom_ca +ffffffff82d24068 r uslhcom_devs +ffffffff82d25000 R ulpt_ca +ffffffff82d26000 R umass_ca +ffffffff82d26028 R umass_bbb_methods +ffffffff82d26040 R umass_cbi_methods +ffffffff82d27000 R umass_quirks +ffffffff82d28000 R umass_scsi_switch +ffffffff82d29000 R uthum_devs +ffffffff82d29008 R uthum_ca +ffffffff82d29030 r uthum_sensor_type_s +ffffffff82d2a000 R ugold_devs +ffffffff82d2a010 R ugold_ca +ffffffff82d2b000 R utrh_devs +ffffffff82d2b008 R utrh_ca +ffffffff82d2c000 R uoakrh_devs +ffffffff82d2c008 R uoakrh_ca +ffffffff82d2c030 R uoakrh_methods +ffffffff82d2d000 R uoaklux_devs +ffffffff82d2d008 R uoaklux_ca +ffffffff82d2d030 R uoaklux_methods +ffffffff82d2e000 R uoakv_devs +ffffffff82d2e008 R uoakv_ca +ffffffff82d2e030 R uoakv_methods +ffffffff82d2f000 R uonerng_ca +ffffffff82d30000 R urng_ca +ffffffff82d30030 r urng_devs +ffffffff82d31000 R udcf_ca +ffffffff82d31028 r udcf_devs +ffffffff82d32000 R umbg_ca +ffffffff82d33000 R uvisor_methods +ffffffff82d33040 R uvisor_ca +ffffffff82d33070 r uvisor_devs +ffffffff82d34000 R udsbr_hw_if +ffffffff82d34028 R udsbr_ca +ffffffff82d35000 R utwitch_devs +ffffffff82d35008 R utwitch_ca +ffffffff82d36000 R aue_devs +ffffffff82d361b0 R aue_ca +ffffffff82d37000 R axe_devs +ffffffff82d370d0 R axe_ca +ffffffff82d38000 R axen_devs +ffffffff82d38020 R axen_ca +ffffffff82d39000 R smsc_ca +ffffffff82d39030 r smsc_devs +ffffffff82d3a000 R cue_ca +ffffffff82d3b000 R kue_devs +ffffffff82d3b088 R kue_ca +ffffffff82d3c000 R cdce_devs +ffffffff82d3c048 R cdce_ca +ffffffff82d3d000 R urndis_ca +ffffffff82d3d030 R urndis_class +ffffffff82d3e000 R mos_devs +ffffffff82d3e018 R mos_ca +ffffffff82d3f000 R mue_devs +ffffffff82d3f020 R mue_ca +ffffffff82d40000 R udav_ca +ffffffff82d40030 r udav_devs +ffffffff82d41000 R upl_ca +ffffffff82d42000 R ugl_ca +ffffffff82d43000 R url_ca +ffffffff82d43030 r url_devs +ffffffff82d44000 R ure_devs +ffffffff82d440f0 R ure_ca +ffffffff82d45000 R uaq_devs +ffffffff82d45018 R uaq_ca +ffffffff82d46000 R umodem_methods +ffffffff82d46040 R umodem_ca +ffffffff82d47000 R uftdi_methods +ffffffff82d47040 R uftdi_ca +ffffffff82d47070 r uftdi_devs +ffffffff82d48000 R uplcom_methods +ffffffff82d48040 R uplcom_ca +ffffffff82d48070 r uplcom_devs +ffffffff82d49000 R umct_methods +ffffffff82d49040 R umct_ca +ffffffff82d49070 r umct_devs +ffffffff82d4a000 R uvscom_methods +ffffffff82d4a040 R uvscom_ca +ffffffff82d4a070 r uvscom_devs +ffffffff82d4b000 R ubsa_methods +ffffffff82d4b040 R ubsa_devs +ffffffff82d4b060 R ubsa_ca +ffffffff82d4c000 R ukspan_ca +ffffffff82d4c028 r ukspan_devs +ffffffff82d4c030 r ukspan_methods +ffffffff82d4d000 R uslcom_methods +ffffffff82d4d040 R uslcom_ca +ffffffff82d4d070 r uslcom_devs +ffffffff82d4e000 R uark_methods +ffffffff82d4e040 R uark_ca +ffffffff82d4e068 r uark_devs +ffffffff82d4f000 R moscom_methods +ffffffff82d4f040 R moscom_ca +ffffffff82d4f068 r moscom_devs +ffffffff82d50000 R umcs_methods +ffffffff82d50040 R umcs_devs +ffffffff82d50050 R umcs_ca +ffffffff82d51000 R uscom_methods +ffffffff82d51040 R uscom_ca +ffffffff82d51068 r uscom_devs +ffffffff82d52000 R ucrcom_methods +ffffffff82d52040 R ucrcom_ca +ffffffff82d53000 R uxrcom_methods +ffffffff82d53040 R uxrcom_ca +ffffffff82d53068 r uxrcom_devs +ffffffff82d54000 R uipaq_methods +ffffffff82d54040 R uipaq_ca +ffffffff82d54070 r uipaq_devs +ffffffff82d55000 R umsm_methods +ffffffff82d55040 R umsm_ca +ffffffff82d55070 r umsm_devs +ffffffff82d56000 R uchcom_methods +ffffffff82d56040 R uchcom_ca +ffffffff82d56068 r uchcom_devs +ffffffff82d56080 r dividers +ffffffff82d57000 R uticom_methods +ffffffff82d57040 R uticom_ca +ffffffff82d57070 r uticom_devs +ffffffff82d58000 R wi_usb_devs +ffffffff82d580f0 R wi_usb_ca +ffffffff82d59000 R atu_ca +ffffffff82d5a000 R ural_ca +ffffffff82d5a030 r ural_devs +ffffffff82d5a0a0 r ural_rf2522_r2 +ffffffff82d5a0e0 r ural_rf2524_r2 +ffffffff82d5a120 r ural_rf2525_hi_r2 +ffffffff82d5a160 r ural_rf2525_r2 +ffffffff82d5a1a0 r ural_rf2525e_r2 +ffffffff82d5a1e0 r ural_rf2526_hi_r2 +ffffffff82d5a220 r ural_rf2526_r2 +ffffffff82d5a260 r ural_def_bbp +ffffffff82d5a2a0 r ural_def_mac +ffffffff82d5b000 R rum_ca +ffffffff82d5b030 r rum_devs +ffffffff82d5b110 r rum_rf5225 +ffffffff82d5b460 r rum_rf5226 +ffffffff82d5b7b0 r rum_def_bbp +ffffffff82d5b7f0 r rum_def_mac +ffffffff82d5c000 R run_ca +ffffffff82d5c030 r run_devs +ffffffff82d5c430 r rt2860_rf2850 +ffffffff82d5c860 r rt2860_rates +ffffffff82d5c920 r rt5592_freqs_40mhz +ffffffff82d5ca60 r rt5592_freqs_20mhz +ffffffff82d5cba0 r rt5592_2ghz_def_rf +ffffffff82d5cbe0 r rt5592_chan_5ghz +ffffffff82d5ce30 r rt5592_def_bbp +ffffffff82d5ce70 r rt5592_bbp_r196 +ffffffff82d5ced0 r rt5390_def_bbp +ffffffff82d5cf00 r rt3572_def_rf +ffffffff82d5cf40 r rt3070_def_rf +ffffffff82d5cf70 r rt3593_def_rf +ffffffff82d5cfb0 r rt5592_def_rf +ffffffff82d5cfe0 r rt5392_def_rf +ffffffff82d5d060 r rt5390_def_rf +ffffffff82d5d0e0 r rt2870_def_mac +ffffffff82d5e000 R mtw_ca +ffffffff82d5e030 r mtw_devs +ffffffff82d5e070 r rt2860_rates +ffffffff82d5e130 r mt7601_rf_chan +ffffffff82d5e1a0 r mt7601_def_bbp +ffffffff82d5e2d0 r mt7601_rf_bank0 +ffffffff82d5e330 r mt7601_rf_bank4 +ffffffff82d5e3b0 r mt7601_rf_bank5 +ffffffff82d5e430 r mt7601_def_mac +ffffffff82d5f000 R zyd_ca +ffffffff82d5f030 r zyd_devs +ffffffff82d5f1b0 r zyd_rfmd_init.phyini +ffffffff82d5f2e0 r zyd_rfmd_init.rfini +ffffffff82d5f330 r zyd_rfmd_set_channel.rfprog +ffffffff82d5f3a0 r zyd_al2230_init.phyini +ffffffff82d5f480 r zyd_al2230_init.rfini +ffffffff82d5f4e0 r zyd_al2230_init_b.phyini +ffffffff82d5f5d0 r zyd_al2230_init_b.rfini +ffffffff82d5f620 r zyd_al2230_set_channel.rfprog +ffffffff82d5f6d0 r zyd_al7230B_init.phyini_1 +ffffffff82d5f7b0 r zyd_al7230B_init.rfini_1 +ffffffff82d5f7f0 r zyd_al7230B_set_channel.rfprog +ffffffff82d5f860 r zyd_al7230B_set_channel.rfsc +ffffffff82d5f890 r zyd_al2210_init.phyini +ffffffff82d5f8f0 r zyd_al2210_init.rfini +ffffffff82d5f920 r zyd_al2210_set_channel.rfprog +ffffffff82d5f960 r zyd_gct_init.phyini +ffffffff82d5f9b0 r zyd_gct_init.rfini +ffffffff82d5fa50 r zyd_gct_set_channel.rfprog +ffffffff82d5fa90 r zyd_maxim_set_channel.phyini +ffffffff82d5fba0 r zyd_maxim_set_channel.rfini +ffffffff82d5fbe0 r zyd_maxim_set_channel.rfprog +ffffffff82d5fc50 r zyd_maxim2_set_channel.phyini +ffffffff82d5fd70 r zyd_maxim2_set_channel.rfini +ffffffff82d5fdb0 r zyd_maxim2_set_channel.rfprog +ffffffff82d5fe20 r zyd_rf_name.zyd_rfs +ffffffff82d5fea0 r zyd_def_phyB +ffffffff82d600d0 r zyd_def_phy +ffffffff82d61000 R upgt_ca +ffffffff82d61028 r upgt_devs_1 +ffffffff82d61030 r upgt_devs_2 +ffffffff82d62000 R urtw_ca +ffffffff82d62030 r urtw_devs +ffffffff82d62090 r urtw_ratetable +ffffffff82d620f0 r urtw_8225_gain +ffffffff82d62110 r urtw_8225_txpwr_cck_ch14 +ffffffff82d62140 r urtw_8225_txpwr_cck +ffffffff82d62170 r urtw_8225_tx_gain_cck_ofdm +ffffffff82d62176 r urtw_8225_txpwr_ofdm +ffffffff82d62180 r urtw_8225_rf_part1 +ffffffff82d62200 r urtw_8225_rxgain +ffffffff82d622c0 r urtw_8225_agc +ffffffff82d62340 r urtw_8225_rf_part2 +ffffffff82d62470 r urtw_8225_rf_part3 +ffffffff82d62550 r urtw_8225_channel +ffffffff82d6258c r urtw_8225_threshold +ffffffff82d625a0 r urtw_8225v2_gain_bg +ffffffff82d625c0 r urtw_8225v2_tx_gain_cck_ofdm +ffffffff82d625f0 r urtw_8225v2_rf_part1 +ffffffff82d62670 r urtw_8225v2_rxgain +ffffffff82d62730 r urtw_8225v2_rf_part2 +ffffffff82d62870 r urtw_8225v2_rf_part3 +ffffffff82d62970 r urtw_8187b_regtbl +ffffffff82d62a90 r urtw_8225v2_b_rf +ffffffff82d62b20 r urtw_8225v2_agc +ffffffff82d62ba0 r urtw_8225v2_ofdm +ffffffff82d63000 R urtwn_ca +ffffffff82d63030 r urtwn_devs +ffffffff82d63330 r rtl8188eu_mac +ffffffff82d634a0 r rtl8192eu_mac +ffffffff82d63640 r rtl8192cu_mac +ffffffff82d63798 r rtl8188eu_bb_prog +ffffffff82d637c0 r rtl8192eu_bb_prog +ffffffff82d637e8 r rtl8188ce_bb_prog +ffffffff82d63810 r rtl8188ru_bb_prog +ffffffff82d63838 r rtl8188cu_bb_prog +ffffffff82d63860 r rtl8192ce_bb_prog +ffffffff82d63888 r rtl8192cu_bb_prog +ffffffff82d638b0 r rtl8188eu_bb_regs +ffffffff82d63a30 r rtl8188eu_bb_vals +ffffffff82d63d30 r rtl8188eu_agc_vals +ffffffff82d63f30 r rtl8192e_bb_regs +ffffffff82d640d0 r rtl8192e_bb_vals +ffffffff82d64410 r rtl8192eu_agc_vals +ffffffff82d64610 r rtl8192ce_bb_regs +ffffffff82d64790 r rtl8188ce_bb_vals +ffffffff82d64a80 r rtl8188ce_agc_vals +ffffffff82d64d00 r rtl8188ru_bb_regs +ffffffff82d64e80 r rtl8188ru_bb_vals +ffffffff82d65180 r rtl8188ru_agc_vals +ffffffff82d65400 r rtl8188cu_bb_vals +ffffffff82d656f0 r rtl8192ce_bb_vals +ffffffff82d659e0 r rtl8192ce_agc_vals +ffffffff82d65c60 r rtl8192cu_bb_vals +ffffffff82d66000 R rsu_ca +ffffffff82d66030 r rsu_devs +ffffffff82d660c8 r rsu_devs_noht +ffffffff82d660d0 r rsu_qid2idx_4ep +ffffffff82d660da r rsu_qid2idx_6ep +ffffffff82d660e4 r rsu_qid2idx_11ep +ffffffff82d660ee r r92s_epaddr +ffffffff82d67000 R otus_ca +ffffffff82d67030 r otus_devs +ffffffff82d67090 r ar_chans +ffffffff82d670c0 r otus_rates +ffffffff82d670e0 r ar5416_phy_regs +ffffffff82d67380 r ar5416_phy_vals_2ghz_20mhz +ffffffff82d678b0 r ar5416_phy_vals_5ghz_20mhz +ffffffff82d67de0 r ar5416_banks_vals_5ghz +ffffffff82d67ef0 r ar5416_banks_vals_2ghz +ffffffff82d68000 r ar5416_banks_regs +ffffffff82d69000 R umb_regstates +ffffffff82d69080 R umb_dataclasses +ffffffff82d69190 R umb_simstate +ffffffff82d69210 R umb_messages +ffffffff82d692b0 R umb_status +ffffffff82d69570 R umb_cids +ffffffff82d696e0 R umb_pktstate +ffffffff82d69740 R umb_actstate +ffffffff82d697a0 R umb_error +ffffffff82d69830 R umb_pintype +ffffffff82d69960 R umb_istate +ffffffff82d699f0 R umb_ca +ffffffff82d69a20 R umb_quirks +ffffffff82d6a000 R uath_ca +ffffffff82d6a030 r uath_devs +ffffffff82d6b000 R athn_usb_ca +ffffffff82d6b030 r athn_usb_devs +ffffffff82d6c000 R uow_ca +ffffffff82d6c028 r uow_devs +ffffffff82d6d000 R uberry_devices +ffffffff82d6d008 R uberry_ca +ffffffff82d6e000 R upd_ca +ffffffff82d6f000 R uwacom_devs +ffffffff82d6f010 R uwacom_ca +ffffffff82d6f038 R uwacom_accessops +ffffffff82d70000 R bwfm_usb_ca +ffffffff82d70030 r bwfm_usbdevs +ffffffff82d71000 R umstc_ca +ffffffff82d71028 r umstc_devs +ffffffff82d72000 R uhidpp_ca +ffffffff82d72028 r uhidpp_devs +ffffffff82d73000 R ucc_ca +ffffffff82d74000 R iic_ca +ffffffff82d75000 r probes +ffffffff82d76000 R lmtemp_ca +ffffffff82d77000 R lmn_ca +ffffffff82d78000 R lmenv_ca +ffffffff82d79000 R maxtmp_ca +ffffffff82d7a000 R adc_ca +ffffffff82d7b000 R admtemp_ca +ffffffff82d7c000 R admlc_ca +ffffffff82d7d000 R admtm_ca +ffffffff82d7e000 R admtmp_ca +ffffffff82d7f000 R admtt_ca +ffffffff82d80000 R maxds_ca +ffffffff82d81000 R adt_ca +ffffffff82d82000 R lm_i2c_ca +ffffffff82d83000 R admcts_ca +ffffffff82d84000 R wbng_ca +ffffffff82d85000 R nvt_ca +ffffffff82d85030 r nvt_volt_desc +ffffffff82d86000 R adl_ca +ffffffff82d87000 R andl_ca +ffffffff82d87030 r andl_temp +ffffffff82d88000 R spdmem_iic_ca +ffffffff82d89000 R sdtemp_ca +ffffffff82d8a000 R lisa_ca +ffffffff82d8b000 R ihidev_ca +ffffffff82d8c000 R ikbd_consops +ffffffff82d8c020 R ikbd_accessops +ffffffff82d8c038 R ikbd_ca +ffffffff82d8d000 R ims_accessops +ffffffff82d8d018 R ims_ca +ffffffff82d8e000 R imt_accessops +ffffffff82d8e018 R imt_ca +ffffffff82d8f000 R iatp_accessops +ffffffff82d8f018 R iatp_ca +ffffffff82d8f040 r mxt_t19_button_map_devs +ffffffff82d90000 R bgw_ca +ffffffff82d91000 R icc_ca +ffffffff82d92000 R gpio_ca +ffffffff82d93000 r sbtn_pnp +ffffffff82d93108 R acpiread_filtops +ffffffff82d94000 R hext +ffffffff82d96000 R acpitimer_ca +ffffffff82d97000 R acpiac_ca +ffffffff82d98000 R acpibat_ca +ffffffff82d99000 R acpibtn_ca +ffffffff82d9a000 R acpicmos_ca +ffffffff82d9b000 R acpicpu_ca +ffffffff82d9c000 R acpihpet_ca +ffffffff82d9d000 R acpiec_ca +ffffffff82d9e000 R acpitz_ca +ffffffff82d9f000 R acpimadt_ca +ffffffff82da0000 R acpimcfg_ca +ffffffff82da1000 R acpiprt_ca +ffffffff82da2000 R acpidmar_ca +ffffffff82da3000 R acpidock_ca +ffffffff82da4000 R abl_ca +ffffffff82da5000 R asmc_ca +ffffffff82da5030 r asmc_prods +ffffffff82da66c0 r asmc_temp_desc +ffffffff82da6c60 r asmc_fan_loc +ffffffff82da6cf0 r asmc_light_desc +ffffffff82da7000 R acpiasus_ca +ffffffff82da8000 R acpithinkpad_ca +ffffffff82da9000 R acpitoshiba_ca +ffffffff82daa000 R acpisony_ca +ffffffff82dab000 R acpivideo_ca +ffffffff82dac000 R acpivout_ca +ffffffff82dad000 R acpipwrres_ca +ffffffff82dae000 R aibs_ca +ffffffff82daf000 R aplgpio_ca +ffffffff82db0000 R bytgpio_ca +ffffffff82db0030 R byt_score_pins +ffffffff82db01d0 R byt_ncore_pins +ffffffff82db0240 R byt_sus_pins +ffffffff82db1000 R chvgpio_ca +ffffffff82db1030 R chv_southwest_pins +ffffffff82db1050 R chv_north_pins +ffffffff82db1068 R chv_east_pins +ffffffff82db1080 R chv_southeast_pins +ffffffff82db2000 R glkgpio_ca +ffffffff82db3000 R pchgpio_ca +ffffffff82db3030 R spt_lp_groups +ffffffff82db3068 R spt_lp_device +ffffffff82db3080 R spt_h_groups +ffffffff82db30c8 R spt_h_device +ffffffff82db30e0 R cnl_h_groups +ffffffff82db3138 R cnl_h_device +ffffffff82db3150 R cnl_lp_groups +ffffffff82db3190 R cnl_lp_device +ffffffff82db31b0 R tgl_lp_groups +ffffffff82db3208 R tgl_lp_device +ffffffff82db3220 R tgl_h_groups +ffffffff82db3288 R tgl_h_device +ffffffff82db4000 R tipmic_ca +ffffffff82db5000 R ccpmic_ca +ffffffff82db6000 R com_acpi_ca +ffffffff82db7000 R sdhc_acpi_ca +ffffffff82db8000 R dwiic_acpi_ca +ffffffff82db9000 R acpicbkbd_ca +ffffffff82dba000 R acpials_ca +ffffffff82dbb000 R tpm_devs +ffffffff82dbb148 R tpm_ca +ffffffff82dbc000 R acpihve_ca +ffffffff82dbd000 R acpisbs_battery_checks +ffffffff82dbd420 R acpisbs_ca +ffffffff82dbe000 R acpisurface_ca +ffffffff82dbf000 R ipmi_acpi_ca +ffffffff82dc0000 R amdgpio_ca +ffffffff82dc1000 R acpihid_ca +ffffffff82dc1030 r acpihid_dsm_funcs +ffffffff82dc2000 R acpi_ca +ffffffff82dc3000 ? acpi_real_mode_resume +ffffffff82dc32fb R acpi_resume_end +ffffffff82dc32fb R acpi_tramp_data_start +ffffffff82dc34a8 R acpi_tramp_data_end +ffffffff82dc4000 R acpipci_ca +ffffffff82dc5000 R efi_ca +ffffffff82dc6000 R vmm_kp_contig +ffffffff82dc6028 R vmm_ca +ffffffff82dc6050 R vmm_vmx_sreg_vmcs_fields +ffffffff82dc7000 R sdmmc_ca +ffffffff82dc8000 R switch_group0_functions +ffffffff82dc8050 R sdmmc_mmc_timings +ffffffff82dc9000 R sdmmc_switch +ffffffff82dca000 R bwfm_sdio_ca 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E_abs_script_sched_slot0_Used +ffffffff830b70a0 D E_abs_targ0_Used +ffffffff830b70dc D E_abs_msgin_Used +ffffffff830b70e8 D E_abs_lunsw_return_Used +ffffffff830b70f0 D E_abs_tag0_Used +ffffffff830b7130 D E_ldsa_abs_reselected_Used +ffffffff830b7134 D E_ldsa_abs_reselect_Used +ffffffff830b7138 D E_ldsa_abs_selected_Used +ffffffff830b713c D E_ldsa_abs_data_Used +ffffffff830b7140 D E_ldsa_abs_slot_Used +ffffffff830b7148 D siop_cd +ffffffff830b8000 D ep_isa_media +ffffffff830b8060 D ep_cd +ffffffff830b9000 D wi_cd +ffffffff830b9020 D wi_func_io +ffffffff830ba000 D an_cd +ffffffff830bb000 D xl_cd +ffffffff830bc000 D fxp_int_delay +ffffffff830bc004 D fxp_bundle_max +ffffffff830bc008 D fxp_min_size_mask +ffffffff830bc010 D fxp_cd +ffffffff830bc030 d tx_threshold +ffffffff830bc040 d fxp_cb_config_template +ffffffff830bd000 D rl_cd +ffffffff830be000 D re_cd +ffffffff830bf000 D dc_cd +ffffffff830c0000 D smc91cxx_idstrs +ffffffff830c0080 D sm_cd +ffffffff830c1000 D epic_cd +ffffffff830c2000 D ne_cd +ffffffff830c2020 d ne2000_detect.test_pattern +ffffffff830c3000 D gem_cd +ffffffff830c4000 D ti_cd +ffffffff830c5000 D com_cd +ffffffff830c5020 D comdefaultrate +ffffffff830c5024 D comconsrate +ffffffff830c5028 D comconscflag +ffffffff830c5030 d comcnattach.comcons +ffffffff830c6000 D pckbc_slot_names +ffffffff830c6010 D pckbc_cd +ffffffff830c7000 D ac97civ +ffffffff830c8000 D cy_cd +ffffffff830c9000 D lpt_cd +ffffffff830ca000 D lm_cd +ffffffff830cb000 D ath_dwelltime +ffffffff830cb004 D ath_calinterval +ffffffff830cb008 D ath_outdoor +ffffffff830cb00c D ath_xchanmode +ffffffff830cb010 D ath_softcrypto +ffffffff830cb018 D ath_cd +ffffffff830cc000 D athn_cd +ffffffff830cd000 D bwfm_2ghz_channels +ffffffff830cd010 D bwfm_5ghz_channels +ffffffff830cd030 D bwfm_proto_bcdc_ops +ffffffff830cd050 D bwfm_cd +ffffffff830ce000 D atw_bbp_io_enable_delay +ffffffff830ce004 D atw_bbp_io_disable_delay +ffffffff830ce008 D atw_writewep_delay +ffffffff830ce00c D atw_beacon_len_adjust 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dt_static_smr_call +ffffffff830f0a40 D dt_static_smr_called +ffffffff830f0ab0 D dt_static_smr_barrier_enter +ffffffff830f0b20 D dt_static_smr_barrier_exit +ffffffff830f0b90 D dt_static_smr_wakeup +ffffffff830f0c00 D dt_static_smr_thread +ffffffff830f0c70 D dt_static_refcnt_none +ffffffff830f0ce0 D dt_static_refcnt_ifaddr +ffffffff830f0d50 D dt_static_refcnt_inpcb +ffffffff830f0dc0 D dt_static_refcnt_tdb +ffffffff830f1000 D db_next_free_breakpoint +ffffffff830f1008 D db_breakpoints_inserted +ffffffff830f2000 D db_ed_style +ffffffff830f3000 D db_examine_format +ffffffff830f3078 D db_print_format +ffffffff830f4000 D db_history_size +ffffffff830f4008 D db_history_curr +ffffffff830f4010 D db_history_last +ffffffff830f5000 D db_tab_stop_width +ffffffff830f5004 D db_max_line +ffffffff830f5008 D db_max_width +ffffffff830f500c D db_radix +ffffffff830f6000 D db_lastsym +ffffffff830f6008 D db_maxoff +ffffffff830f7000 D db_vars +ffffffff830f7090 D db_evars +ffffffff830f8000 D db_watchpoints_inserted +ffffffff830f8008 D db_next_free_watchpoint +ffffffff830f9000 D db_log +ffffffff830fa000 D audio_cd +ffffffff830fa020 D audio_lock +ffffffff830fb000 D midi_cd +ffffffff830fc000 D rnd_cold +ffffffff830fc004 D rnd_slowextract +ffffffff830fc008 D rnd_timeout +ffffffff830fc050 D rndlock +ffffffff830fc060 D rndreinit_timeout +ffffffff830fc0a8 D rnd_task +ffffffff830fd000 D video_cd +ffffffff830fe000 d rrip_table_analyze +ffffffff830fe0e0 d rrip_table_getname +ffffffff830fe1e0 d rrip_table_getsymname +ffffffff830fe280 d rrip_table_extref +ffffffff830ff000 D nexecs +ffffffff83100000 D elf_note_names +ffffffff83101000 D ncpus +ffffffff83101004 D ncpusfound +ffffffff83102000 D acct_lock +ffffffff83102010 D acctsuspend +ffffffff83102014 D acctresume +ffffffff83102018 D acctrate +ffffffff83103000 D ticks +ffffffff83103008 D jiffies +ffffffff83104000 D clockintr_mtx +ffffffff83104010 D statclock_gen +ffffffff83105000 D fhdlk +ffffffff83106000 D kqueue_klist_lock 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evcount_list +ffffffff8311a010 d evcount_percpu_init_list +ffffffff8311b000 D syslogf_rwlock +ffffffff8311b010 D log_mtx +ffffffff8311b020 D logstash_in +ffffffff8311b028 D logstash_out +ffffffff8311b030 D logstash_rwlock +ffffffff8311c000 D pool_head +ffffffff8311c010 D pool_lock +ffffffff8311c020 D pool_debug +ffffffff8311c028 D pool_allocator_single +ffffffff8311c040 D pool_allocator_multi +ffffffff8311c058 D pool_allocator_multi_ni +ffffffff8311c070 D pool_gc_tick +ffffffff8311c0b8 D pool_gc_task +ffffffff8311d000 D kprintf_mutex +ffffffff8311d010 D db_panic +ffffffff8311d014 D splassert_ctl +ffffffff8311d018 D v_putc +ffffffff8311d020 D printf_flags +ffffffff8311e000 D userconf_base +ffffffff8311e004 D userconf_maxdev +ffffffff8311e008 D userconf_totdev +ffffffff8311e00c D userconf_maxlocnames +ffffffff8311e010 D userconf_cnt +ffffffff8311e014 D userconf_lines +ffffffff8311e018 D userconf_histsz +ffffffff8311e020 D userconf_cmds +ffffffff8311f000 D ftlock +ffffffff83120000 d ppollcollect.poll_errintvl +ffffffff83121000 D ttydefchars +ffffffff83121014 D ttclos +ffffffff8312101b D ttopen +ffffffff83121022 D ttybg +ffffffff83121028 D ttyin +ffffffff8312102e D ttyout +ffffffff83121038 D ttylist_lock +ffffffff83122000 D linesw +ffffffff83122280 D nlinesw +ffffffff83123000 D pt_softc_lock +ffffffff83124000 d mbstat_boot_boot_cpumem +ffffffff83124080 D mbstat +ffffffff83124090 D mclsizes +ffffffff831240b0 D m_extref_mtx +ffffffff831240c0 D m_pool_allocator +ffffffff83125000 D somaxconn +ffffffff83125004 D sominconn +ffffffff83125008 D sosplice_lock +ffffffff83126000 D sb_max +ffffffff83127000 D unp_df_lock +ffffffff83127010 D unp_gc_lock +ffffffff83127020 D unp_rights_mtx +ffffffff83127030 D unp_ino_mtx +ffffffff83127040 D unp_gc_task +ffffffff83127070 D unpst_sendspace +ffffffff83127074 D unpst_recvspace +ffffffff83127078 D unpsq_sendspace +ffffffff8312707c D unpsq_recvspace +ffffffff83127080 D unpdg_sendspace +ffffffff83127084 D unpdg_recvspace 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SHAPad2 +ffffffff83141000 D rtmap_gc +ffffffff83141018 D rt_rc +ffffffff83142000 D rt_labels +ffffffff83143000 D enc_cloner +ffffffff83144000 D gre_cloner +ffffffff83144030 D gre_list +ffffffff83144040 D mgre_cloner +ffffffff83144070 D egre_cloner +ffffffff831440a0 D nvgre_cloner +ffffffff831440d0 D eoip_cloner +ffffffff83145000 D trunk_cloner +ffffffff83146000 d aggr_cloner +ffffffff83147000 d tpmr_cloner +ffffffff83148000 D mpe_cloner +ffffffff83149000 D mpw_cloner +ffffffff8314a000 D mpip_cloner +ffffffff8314b000 d bpe_cloner +ffffffff8314b030 d bpe_lock +ffffffff8314c000 D vether_cloner +ffffffff8314d000 D pair_cloner +ffffffff8314e000 d vxlan_cloner +ffffffff8314e030 d vxlan_lock +ffffffff8314e040 d vxlan_teps +ffffffff8314f000 D underload_interval +ffffffff8314f010 D wg_cloner +ffffffff83150000 d stoeplitz_keyseed +ffffffff83151000 D ieee80211_cache_size +ffffffff83152000 D arpt_prune +ffffffff83152004 D arpt_keep +ffffffff83152008 D arpt_down +ffffffff83152010 D arpinq +ffffffff83152048 D arp_mtx +ffffffff83152058 D arp_maxtries +ffffffff83153000 D ipport_firstauto +ffffffff83153004 D ipport_lastauto +ffffffff83153008 D ipport_hifirstauto +ffffffff8315300c D ipport_hilastauto +ffffffff83154000 D divert_sendspace +ffffffff83154004 D divert_recvspace +ffffffff83154008 D divbhashsize +ffffffff83155000 D icmptstamprepl +ffffffff83155004 D icmperrppslim +ffffffff83155008 D icmp_redirtimeout +ffffffff83156000 D ipsendredirects +ffffffff83156004 D ip_defttl +ffffffff83156008 D ip_mtudisc +ffffffff8315600c D ip_mtudisc_timeout +ffffffff83156010 D ipq_mutex +ffffffff83156020 D ip_maxqueue +ffffffff83156028 D ipintrq +ffffffff83156060 d ipsend_task +ffffffff83156090 d ipsendraw_task +ffffffff83157000 D ip_mrtproto +ffffffff83157004 d sin +ffffffff83158000 D rip_sendspace +ffffffff83158008 D rip_recvspace +ffffffff83159000 D tcprexmtthresh +ffffffff83159004 D tcptv_keep_init +ffffffff83159008 D tcp_rst_ppslim +ffffffff8315900c D tcp_ackdrop_ppslim +ffffffff83159010 D tcp_syn_hash_size +ffffffff83159014 D tcp_syn_cache_limit +ffffffff83159018 D tcp_syn_bucket_limit +ffffffff8315901c D tcp_syn_use_limit +ffffffff8315a000 D tcp_outflags +ffffffff8315b000 D tcp_timer_mtx +ffffffff8315b010 D tcp_mssdflt +ffffffff8315b014 D tcp_rttdflt +ffffffff8315b018 D tcp_do_rfc1323 +ffffffff8315b01c D tcp_do_sack +ffffffff8315b020 D tcp_do_rfc3390 +ffffffff8315b024 D tcp_reass_limit +ffffffff8315b028 D tcp_sackhole_limit +ffffffff8315c000 D tcp_backoff +ffffffff8315c034 D tcp_totbackoff +ffffffff8315d000 D tcp_sendspace +ffffffff8315d004 D tcp_recvspace +ffffffff8315d008 D tcp_autorcvbuf_inc +ffffffff8315e000 D udpcksum +ffffffff8315e004 D udp_sendspace +ffffffff8315e008 D udp_recvspace +ffffffff8315f000 D ipsec_flows_mtx +ffffffff8315f010 D ipsec_ids_idle +ffffffff8315f014 D ipsec_ids_next_flow +ffffffff8315f018 D ipsec_policy_head +ffffffff8315f028 D ipsp_ids_gc_timeout +ffffffff8315f070 D tdb_sadb_mtx +ffffffff8315f080 d tdb_hashmask +ffffffff83160000 D ipo_tdb_mtx +ffffffff83160010 D ipsec_acquire_mtx +ffffffff83160020 D ipsec_acquire_head +ffffffff83161000 D ipsec_keep_invalid +ffffffff83161004 D ipsec_require_pfs +ffffffff83161008 D ipsec_soft_timeout +ffffffff8316100c D ipsec_exp_timeout +ffffffff83161010 D ipsec_soft_first_use +ffffffff83161014 D ipsec_exp_first_use +ffffffff83161018 D ipsec_expire_acquire +ffffffff8316101c D esp_enable +ffffffff83161020 D ah_enable +ffffffff83162000 D udpencap_enable +ffffffff83162004 D udpencap_port +ffffffff83163000 D carp_vh_rc +ffffffff83163020 D carp_sc_rc +ffffffff83163040 D carp_opts +ffffffff83163058 D carp_cloner +ffffffff83163088 d carp_send_na.mcast +ffffffff83164000 d PADDING +ffffffff83165000 d PADDING +ffffffff83166000 d weak_keys +ffffffff83167000 D swcr_id +ffffffff83168000 D window_inflate +ffffffff83168004 D window_deflate +ffffffff83169000 D ghash_update +ffffffff8316a000 D mpls_defttl +ffffffff8316a004 D mpls_mapttl_ip +ffffffff8316b000 D nfskevq_lock +ffffffff8316c000 D nfs_backoff +ffffffff8316c020 D nfs_ptimers +ffffffff8316d000 D desirednfsrvcache +ffffffff8316d010 D nonidempotent +ffffffff8316d070 D nfsv2_repstat +ffffffff8316e000 D nfsv2_type +ffffffff8316e030 D nfsv3_type +ffffffff8316e060 D nv2tov_type +ffffffff8316e080 D nv3tov_type +ffffffff8316e0a0 D nfsv3_procid +ffffffff8316e100 D nfsv2_procid +ffffffff8316e15c d nfsv3err_getattr +ffffffff8316e170 d nfsv3err_setattr +ffffffff8316e190 d nfsv3err_lookup +ffffffff8316e1a4 d nfsv3err_access +ffffffff8316e1b0 d nfsv3err_readlink +ffffffff8316e1d0 d nfsv3err_read +ffffffff8316e1f0 d nfsv3err_write +ffffffff8316e210 d nfsv3err_create +ffffffff8316e230 d nfsv3err_mkdir +ffffffff8316e250 d nfsv3err_symlink +ffffffff8316e270 d nfsv3err_mknod +ffffffff8316e290 d nfsv3err_remove +ffffffff8316e2b0 d nfsv3err_rmdir +ffffffff8316e2d0 d nfsv3err_rename +ffffffff8316e300 d nfsv3err_link +ffffffff8316e330 d nfsv3err_readdir +ffffffff8316e350 d nfsv3err_readdirplus +ffffffff8316e366 d nfsv3err_fsstat +ffffffff8316e372 d nfsv3err_fsinfo +ffffffff8316e37c d nfsv3err_pathconf +ffffffff8316e386 d nfsv3err_commit +ffffffff8316f000 D nfsrv3_procs +ffffffff8316f0b8 D nfs_niothreads +ffffffff83170000 D fragtbl +ffffffff83171000 D ffs_vtbl +ffffffff83172000 D softdep_typenames +ffffffff83172070 D tickdelay +ffffffff83173000 D dirchk +ffffffff83174000 D desireddquot +ffffffff83175000 D amap_list_lock +ffffffff83176000 d uao_list_lock +ffffffff83177000 d uvmexp_countersboot_boot_cpumem +ffffffff831770c0 D uvmexp_counters +ffffffff831770c8 D vm_min_kernel_address +ffffffff83178000 D no_constraint +ffffffff83179000 d uvm_kmapent_warn_rate +ffffffff8317a000 D maxslp +ffffffff8317b000 D uvmpagerops +ffffffff8317c000 D uvm_swap_data_lock +ffffffff8317c010 D swap_syscall_lock +ffffffff8317c020 D oommtx +ffffffff8317d000 D uvm_doswapencrypt +ffffffff8317e000 D gif_list +ffffffff8317e010 D gif_cloner +ffffffff8317f000 D divert6_sendspace +ffffffff8317f004 D divert6_recvspace +ffffffff8317f008 D divb6hashsize +ffffffff83180000 d in6_get_hw_ifid.allone +ffffffff83181000 D ip6_sendredirects +ffffffff83181004 D ip6_defhlim +ffffffff83181008 D ip6_defmcasthlim +ffffffff8318100c D ip6_maxfragpackets +ffffffff83181010 D ip6_maxfrags +ffffffff83181014 D ip6_log_interval +ffffffff83181018 D ip6_hdrnestlimit +ffffffff8318101c D ip6_dad_count +ffffffff83181020 D ip6_auto_flowlabel +ffffffff83181024 D ip6_use_deprecated +ffffffff83181028 D ip6_neighborgcthresh +ffffffff8318102c D ip6_maxdynroutes +ffffffff83181030 D rip6_sendspace +ffffffff83181038 D rip6_recvspace +ffffffff83181040 D icmp6_redirtimeout +ffffffff83181044 D icmp6errppslim +ffffffff83181048 D ip6_mtudisc_timeout +ffffffff83182000 D frag6_mutex +ffffffff83183000 d icmp6_mtudisc_hiwat +ffffffff83183004 d icmp6_mtudisc_lowat +ffffffff83184000 d randomtab_20 +ffffffff83185000 D ip6intrq +ffffffff83185038 d ip6send_task +ffffffff83186000 D nd6_timer_next +ffffffff83186008 D nd6_expire_next +ffffffff83186010 D nd6_delay +ffffffff83186014 D nd6_umaxtries +ffffffff83186018 D nd6_mmaxtries +ffffffff8318601c D nd6_gctimer +ffffffff83186020 D nd6_maxndopt +ffffffff83187000 d dadq +ffffffff83188000 D pfkeyv2_mtx +ffffffff83188010 d pfkeyv2_seq +ffffffff83189000 D sadb_exts_allowed_in +ffffffff83189090 D sadb_exts_required_in +ffffffff8318a000 D cold +ffffffff8318b000 D bdevsw +ffffffff8318b460 D nblkdev +ffffffff8318b470 D cdevsw +ffffffff8318d400 D nchrdev +ffffffff8318d404 D mem_no +ffffffff8318d408 D swapdev +ffffffff8318d410 D constab +ffffffff8318e000 D machine +ffffffff8318e008 D lid_action +ffffffff8318e00c D pwr_action +ffffffff8318e010 D isa_constraint +ffffffff8318e020 D dma_constraint +ffffffff8318e030 D uvm_md_constraints +ffffffff8318e048 D delay_func +ffffffff8318e050 D initclock_func +ffffffff8318e058 D bootinfo_size +ffffffff8318e05c D waittime +ffffffff8318e060 D dumpmag +ffffffff8318f000 D tsc_rdtsc +ffffffff8318f008 D tsc_timecounter +ffffffff8318f058 D tsc_is_synchronized +ffffffff83190000 D local_apic +ffffffff83190020 D lapic_id +ffffffff83190080 D lapic_tpr +ffffffff831900a0 d lapic_ppr +ffffffff83190100 d lapic_isr +ffffffff83191000 D warn_once +ffffffff83192000 d errata +ffffffff83193000 D cpu_ucode_intel_mtx +ffffffff83194000 D mem_owner_bios +ffffffff83194008 D mrops +ffffffff83194028 D mtrrmask +ffffffff83194030 D mtrrtomrt +ffffffff83195000 D pmap_pg_wc +ffffffff83195008 D pmaps_lock +ffffffff83195018 d pmap_maxkvaddr +ffffffff83196000 D kv_physwait +ffffffff83197000 D fpu_save_len +ffffffff83198000 D i8259_pic +ffffffff83199000 D softintr_pic +ffffffff8319a000 D ipifunc +ffffffff8319b000 D setperf_mp_mutex +ffffffff8319c000 D db_Grp6 +ffffffff8319c040 D db_Grp7 +ffffffff8319c100 D db_Grp8 +ffffffff8319c140 D db_Grp9 +ffffffff8319c200 D db_GrpA +ffffffff8319c240 D db_GrpB +ffffffff8319c280 D db_GrpC +ffffffff8319c2c0 D db_inst_0f0x +ffffffff8319c440 D db_inst_0f2x +ffffffff8319c5c0 D db_inst_0f3x +ffffffff8319c740 D db_inst_0f8x +ffffffff8319c8c0 D db_inst_0f9x +ffffffff8319ca40 D db_inst_0fax +ffffffff8319cbc0 D db_inst_0fbx +ffffffff8319cd40 D db_inst_0fcx +ffffffff8319cec0 D db_inst_0f +ffffffff8319cf40 D db_Esc92 +ffffffff8319cf80 D db_Esc94 +ffffffff8319cfc0 D db_Esc95 +ffffffff8319d000 D db_Esc96 +ffffffff8319d040 D db_Esc97 +ffffffff8319d080 D db_Esca5 +ffffffff8319d0c0 D db_Escb4 +ffffffff8319d100 D db_Esce3 +ffffffff8319d140 D db_Escf4 +ffffffff8319d180 D db_Esc8 +ffffffff8319d240 D db_Esc9 +ffffffff8319d300 D db_Esca +ffffffff8319d3c0 D db_Escb +ffffffff8319d480 D db_Escc +ffffffff8319d540 D db_Escd +ffffffff8319d600 D db_Esce +ffffffff8319d6c0 D db_Escf +ffffffff8319d780 D db_Esc_inst +ffffffff8319d7c0 D db_Grp1 +ffffffff8319d800 D db_Grp2 +ffffffff8319d840 D db_Grp3 +ffffffff8319d900 D db_Grp4 +ffffffff8319d9c0 D db_Grp5 +ffffffff8319da80 D db_inst_table +ffffffff8319f280 D db_bad_inst +ffffffff8319f2a0 D db_index_reg_16 +ffffffff8319f2e0 D db_reg +ffffffff8319f4e0 D db_seg_reg +ffffffff8319f520 D db_lengths +ffffffff831a0000 D db_regs +ffffffff831a01e0 D db_eregs +ffffffff831a01f0 D db_reg_args +ffffffff831a1000 D timer_mutex +ffffffff831a1010 d i8254_timecounter +ffffffff831a2000 D spleen8x16 +ffffffff831a2058 D spleen12x24 +ffffffff831a20b0 D spleen16x32 +ffffffff831a2108 D spleen32x64 +ffffffff831a2160 d builtin_fonts +ffffffff831a21e0 d wsfont_add.cookiegen +ffffffff831a21f0 d spleen8x16_data +ffffffff831a2ff0 d spleen12x24_data +ffffffff831a59f0 d spleen16x32_data +ffffffff831a91f0 d spleen32x64_data +ffffffff831b8000 D nsphy_cd +ffffffff831b9000 D nsphyter_cd +ffffffff831ba000 D gentbi_cd +ffffffff831bb000 D qsphy_cd +ffffffff831bc000 D inphy_cd +ffffffff831bd000 D iophy_cd +ffffffff831be000 D eephy_cd +ffffffff831bf000 D exphy_cd +ffffffff831c0000 D rlphy_cd +ffffffff831c1000 D lxtphy_cd +ffffffff831c2000 D luphy_cd +ffffffff831c3000 D mtdphy_cd +ffffffff831c4000 D icsphy_cd +ffffffff831c5000 D sqphy_cd +ffffffff831c6000 D tqphy_cd +ffffffff831c7000 D ukphy_cd +ffffffff831c8000 D dcphy_cd +ffffffff831c9000 D bmtphy_cd +ffffffff831ca000 D brgphy_cd +ffffffff831cb000 D xmphy_cd +ffffffff831cc000 D amphy_cd +ffffffff831cd000 D acphy_cd +ffffffff831ce000 D nsgphy_cd +ffffffff831cf000 D urlphy_cd +ffffffff831d0000 D rgephy_cd +ffffffff831d1000 D ciphy_cd +ffffffff831d2000 D ipgphy_cd +ffffffff831d3000 D etphy_cd +ffffffff831d4000 D jmphy_cd +ffffffff831d5000 D atphy_cd +ffffffff831d6000 D scsi_autoconf +ffffffff831d6008 D scsibus_cd +ffffffff831d7000 D cd_cd +ffffffff831d8000 D ch_cd +ffffffff831d8020 D chquirks +ffffffff831d9000 D sd_cd +ffffffff831da000 D st_cd +ffffffff831db000 D uk_cd +ffffffff831dc000 D safte_cd +ffffffff831dd000 D ses_cd +ffffffff831de000 D sym_cd +ffffffff831de020 D sym_devices +ffffffff831de070 D asym_devices +ffffffff831df000 D rdac_cd +ffffffff831df020 D rdac_devices +ffffffff831e0000 D emc_cd +ffffffff831e0020 D emc_devices +ffffffff831e1000 D hds_cd +ffffffff831e1020 D hds_devices +ffffffff831e2000 D atapiscsi_cd +ffffffff831e3000 D wd_cd +ffffffff831e3020 d wddumpmulti +ffffffff831e4000 D mainbus_cd +ffffffff831e4020 D mba_iba +ffffffff831e5000 D bios_cd +ffffffff831e5020 D smbios_uninfo +ffffffff831e6000 D mpbios_cd +ffffffff831e6020 d mp_conf +ffffffff831e6070 d extint_bus +ffffffff831e60a0 d smi_bus +ffffffff831e60d0 d nmi_bus +ffffffff831e7000 D cpu_info_full_primary +ffffffff831ea000 D cpu_info_list +ffffffff831ea008 D mp_cpu_funcs +ffffffff831ea020 D cpu_cd +ffffffff831ea040 D cpu_info +ffffffff831eb000 D local_pic +ffffffff831eb090 D lapic_readreg +ffffffff831eb098 D lapic_writereg +ffffffff831eb0a0 D x86_ipi +ffffffff831ec000 D ioapic_cold +ffffffff831ec008 D ioapic_cd +ffffffff831ed000 D efifb_std_descr +ffffffff831ed030 D efifb_descrs +ffffffff831ed038 D efifb_accessops +ffffffff831ed098 D efifb_cd +ffffffff831ee000 D pvbus_cd +ffffffff831ee020 D pvbus_types +ffffffff831ee0e0 D pvbus_dma_tag +ffffffff831ef000 D pvclock_cd +ffffffff831ef020 D pvclock_timecounter +ffffffff831f0000 D vmt_tclo_rpc +ffffffff831f00d0 D vmt_cd +ffffffff831f1000 D xen_cd +ffffffff831f1020 D xen_bus_dma_tag +ffffffff831f2000 D xnf_cd +ffffffff831f3000 D xbf_cd +ffffffff831f4000 D hv_msg_dispatch +ffffffff831f4110 D hv_timecounter +ffffffff831f4160 D hyperv_cd +ffffffff831f5000 d hv_ic_devs +ffffffff831f6000 D hvn_cd +ffffffff831f7000 D hvs_cd +ffffffff831f8000 D virtio_cd +ffffffff831f9000 D vio_cd +ffffffff831fa000 D vioblk_cd +ffffffff831fb000 D viomb_cd +ffffffff831fc000 D viornd_cd +ffffffff831fd000 D vioscsi_cd +ffffffff831fe000 D vmmci_cd +ffffffff831ff000 D pci_cd +ffffffff83200000 D arc_fw_hdr +ffffffff83200008 D arc_cd +ffffffff83201000 D jmb_cd +ffffffff83202000 D mfii_cd +ffffffff83203000 D ips_cd +ffffffff83204000 D eap_cd +ffffffff83205000 D auacer_cd +ffffffff83206000 D auich_cd +ffffffff83207000 D azalia_cd +ffffffff83208000 D envy_cd +ffffffff83208020 D envy_matchids +ffffffff83208030 D envy_rates +ffffffff832080b0 D ak4524_dac +ffffffff832080d8 D ak4524_adc +ffffffff83208100 D ak4358_dac +ffffffff83208128 D ak5365_adc +ffffffff83208150 D unkenvy_codec +ffffffff83208180 D envy_cards +ffffffff832083f0 D envy_cards_ht +ffffffff83208600 d julia_eeprom +ffffffff83209000 D emu_cd +ffffffff8320a000 D auixp_cd +ffffffff8320b000 D clcs_cd +ffffffff8320c000 D yds_cd +ffffffff8320d000 D auvia_cd +ffffffff8320e000 D qle_cd +ffffffff8320f000 D mpii_cd +ffffffff83210000 D aq_cd +ffffffff83211000 D de_cd +ffffffff83212000 D pcn_cd +ffffffff83213000 D wdc_sii3114_vtbl +ffffffff83213038 D wdc_pdc203xx_vtbl +ffffffff83213070 D wdc_svwsata_vtbl +ffffffff832130a8 D pciide_cd +ffffffff832130d0 d sis_hostbr_type +ffffffff83214000 D ppb_cd +ffffffff83215000 D vr_cd +ffffffff83215020 D vr_devices +ffffffff83216000 D txp_cd +ffffffff83217000 D bt848_card_signature +ffffffff83218000 D bktr_cd +ffffffff83219000 D em_cd +ffffffff8321a000 D ixgb_cd +ffffffff8321b000 D ix_cd +ffffffff8321b020 D ixgbe_smart_speed +ffffffff8321b024 D ixgbe_enable_msix +ffffffff8321c000 D ixl_cd +ffffffff8321c020 d ixl_sff_lock +ffffffff8321d000 D xge_cd +ffffffff8321e000 D thtc_cd +ffffffff8321e020 D tht_cd +ffffffff8321e040 D tht_txt_desc +ffffffff8321e068 D tht_rxf_desc +ffffffff8321e090 D tht_rxd_desc +ffffffff8321e0b8 D tht_txf_desc +ffffffff8321f000 D myx_cd +ffffffff83220000 D oce_cd +ffffffff83221000 D dc_devs +ffffffff83222000 D cas_cd +ffffffff83223000 D sis_cd +ffffffff83224000 D se_cd +ffffffff83225000 D cbb_cd +ffffffff83225020 D yc_chipsets +ffffffff832251b0 d pccbb_funcs +ffffffff832251e0 d pccbb_pcmcia_funcs +ffffffff83226000 D skc_cd +ffffffff83226020 D sk_cd +ffffffff83227000 D mskc_cd +ffffffff83227020 D msk_cd +ffffffff83228000 D puc_cd +ffffffff83229000 D puc_ndevs +ffffffff8322a000 D iwi_cd +ffffffff8322b000 D wpi_cd +ffffffff8322c000 D iwn_cd +ffffffff8322d000 D iwm_cd +ffffffff8322e000 D iwx_cd +ffffffff8322f000 D cmpci_cd +ffffffff83230000 D iha_cd +ffffffff83231000 D pcscp_cd +ffffffff83231020 D pcscp_glue +ffffffff83232000 D bge_cd +ffffffff83233000 D bnx_firmwares +ffffffff83233160 D bnx_rv2ps +ffffffff832331c0 D bnx_cd +ffffffff832331e0 d flash_5709 +ffffffff83233210 d flash_table +ffffffff83234000 D vge_cd +ffffffff83235000 D stge_cd +ffffffff83236000 D nfe_cd +ffffffff83237000 D et_cd +ffffffff83238000 D jme_cd +ffffffff83239000 D age_cd +ffffffff8323a000 D alc_dma_burst +ffffffff8323a020 D alc_cd +ffffffff8323b000 D ale_cd +ffffffff8323c000 D amdpm_cd +ffffffff8323c020 d amdpm_timecounter +ffffffff8323d000 D bce_cd +ffffffff8323e000 D rtwn_cd +ffffffff8323f000 d ral_rt2560_opns +ffffffff8323f028 d ral_rt2661_opns +ffffffff8323f050 d ral_rt2860_opns +ffffffff83240000 D piixpm_cd +ffffffff83241000 D vic_cd +ffffffff83242000 D vmx_cd +ffffffff83243000 D vmwpvs_cd +ffffffff83244000 D lii_cd +ffffffff83245000 D ichiic_cd +ffffffff83246000 D viapm_cd +ffffffff83246020 d viapm_timecounter +ffffffff83247000 D amdiic_cd +ffffffff83248000 D nviic_cd +ffffffff83249000 D kate_cd +ffffffff8324a000 D km_cd +ffffffff8324b000 D cpu_model_offsets +ffffffff8324b070 D ksmn_cd +ffffffff8324c000 D itherm_cd +ffffffff8324d000 D pchtemp_cd +ffffffff8324e000 D xspd_cd +ffffffff8324f000 D virtio_pci_ops +ffffffff83250000 D bwfm_pci_buscore_ops +ffffffff83250030 D bwfm_pci_bus_ops +ffffffff83250058 D bwfm_pci_msgbuf_ops +ffffffff83251000 D bnxt_cd +ffffffff83252000 D mcx_cd +ffffffff83253000 D iavf_cd +ffffffff83254000 D rge_cd +ffffffff83255000 D igc_cd +ffffffff83256000 D ngbe_cd +ffffffff83257000 D agp_cd +ffffffff83258000 D intagp_cd +ffffffff83258020 D agp_i810_methods +ffffffff83259000 D reservation_ww_class +ffffffff8325a000 d bridge_lock +ffffffff8325a010 d bridge_list +ffffffff8325b000 d drm_connector_enum_list +ffffffff8325b1f8 d connector_list_lock +ffffffff8325b208 d connector_list +ffffffff8325c000 d kernel_fb_helper_list +ffffffff8325c010 d kernel_fb_helper_lock +ffffffff8325d000 D drm_global_mutex +ffffffff8325e000 D sch_mtx +ffffffff8325e010 D i2c_bit_algo +ffffffff8325e020 d drm_fence_context_count +ffffffff8325e028 d dma_fence_stub_mtx +ffffffff8325e038 D wait_bit_mtx +ffffffff8325e048 D shrinkers +ffffffff8325f000 d crtc_ww_class +ffffffff83260000 d panel_lock +ffffffff83260010 d panel_list +ffffffff83261000 d ttm_global_mutex +ffffffff83262000 D intel_bbops +ffffffff83263000 d i915_sys_placement +ffffffff83263020 d i915_ttm_bo_driver +ffffffff83264000 d mchdev_lock +ffffffff83265000 D inteldrm_stdscreen +ffffffff83265030 D inteldrm_scrlist +ffffffff83265038 D inteldrm_screenlist +ffffffff83265048 D inteldrm_accessops +ffffffff832650a8 D inteldrm_cd +ffffffff83266000 d capture_mutex +ffffffff83267000 d mitigations +ffffffff83268000 D i915_modparams +ffffffff83269000 d schedule_lock +ffffffff8326a000 d unbind_fence_ops +ffffffff8326b000 D intel_graphics_stolen_res +ffffffff8326c000 D btc_valid_sclk +ffffffff8326d000 d evergreen_cs_packet_parse_vline.vline_start_end +ffffffff8326d020 d evergreen_cs_packet_parse_vline.vline_status +ffffffff8326e000 d r600_cs_packet_parse_vline.vline_start_end +ffffffff8326e008 d r600_cs_packet_parse_vline.vline_status +ffffffff8326f000 d r100_asic +ffffffff8326f2e0 d r200_asic +ffffffff8326f5c0 d r300_asic_pcie +ffffffff8326f8a0 d r300_asic +ffffffff8326fb80 d r420_asic +ffffffff8326fe60 d rs400_asic +ffffffff83270140 d rs600_asic +ffffffff83270420 d rs690_asic +ffffffff83270700 d rv515_asic +ffffffff832709e0 d r520_asic +ffffffff83270cc0 d r600_asic +ffffffff83270fa0 d rv6xx_asic +ffffffff83271280 d rs780_asic +ffffffff83271560 d rv770_asic +ffffffff83271840 d evergreen_asic +ffffffff83271b20 d sumo_asic +ffffffff83271e00 d btc_asic +ffffffff832720e0 d cayman_asic +ffffffff832723c0 d trinity_asic +ffffffff832726a0 d si_asic +ffffffff83272980 d ci_asic +ffffffff83272c60 d kv_asic +ffffffff83273000 d dce6_funcs +ffffffff83273018 d dce6_hdmi_funcs +ffffffff83273088 d dce6_dp_funcs +ffffffff832730f8 d dce4_funcs +ffffffff83273110 d dce4_hdmi_funcs +ffffffff83273180 d dce4_dp_funcs +ffffffff832731f0 d dce32_funcs +ffffffff83273208 d dce32_hdmi_funcs +ffffffff83273278 d dce32_dp_funcs +ffffffff832732e8 d r600_funcs +ffffffff83273300 d r600_hdmi_funcs +ffffffff83274000 D radeon_modeset +ffffffff83274004 D radeon_dynclks +ffffffff83274008 D radeon_agpmode +ffffffff8327400c D radeon_gart_size +ffffffff83274010 D radeon_tv +ffffffff83274014 D radeon_audio +ffffffff83274018 D radeon_pcie_gen2 +ffffffff8327401c D radeon_msi +ffffffff83274020 D radeon_lockup_timeout +ffffffff83274024 D radeon_dpm +ffffffff83274028 D radeon_aspm +ffffffff8327402c D radeon_runtime_pm +ffffffff83274030 D radeon_vm_size +ffffffff83274034 D radeon_vm_block_size +ffffffff83274038 D radeon_use_pflipirq +ffffffff8327403c D radeon_bapm +ffffffff83274040 D radeon_backlight +ffffffff83274044 D radeon_auxch +ffffffff83274048 D radeon_uvd +ffffffff8327404c D radeon_vce +ffffffff83274050 D radeon_si_support +ffffffff83274054 D radeon_cik_support +ffffffff83274058 D radeondrm_cd +ffffffff83274078 D radeondrm_stdscreen +ffffffff832740a8 D radeondrm_scrlist +ffffffff832740b0 D radeondrm_screenlist +ffffffff832740c0 D radeondrm_accessops +ffffffff83275000 D radeon_bbops +ffffffff83276000 d radeon_bo_driver +ffffffff83277000 d verde_pg_init +ffffffff83278000 d cac_weights_pitcairn +ffffffff832784d0 d cac_weights_oland +ffffffff83279000 d aldebaran_mode2_handler +ffffffff8327a000 d amdgpu_vbios_version_attrs +ffffffff8327b000 D amdgpu_asic_name +ffffffff8327c000 D amdgpu_gart_size +ffffffff8327c004 D amdgpu_gtt_size +ffffffff8327c008 D amdgpu_moverate +ffffffff8327c00c D amdgpu_audio +ffffffff8327c010 D amdgpu_pcie_gen2 +ffffffff8327c014 D amdgpu_msi +ffffffff8327c018 D amdgpu_dpm +ffffffff8327c01c D amdgpu_fw_load_type +ffffffff8327c020 D amdgpu_aspm +ffffffff8327c024 D amdgpu_runtime_pm +ffffffff8327c028 D amdgpu_ip_block_mask +ffffffff8327c02c D amdgpu_bapm +ffffffff8327c030 D amdgpu_vm_size +ffffffff8327c034 D amdgpu_vm_fragment_size +ffffffff8327c038 D amdgpu_vm_block_size +ffffffff8327c03c D amdgpu_vm_update_mode +ffffffff8327c040 D amdgpu_dc +ffffffff8327c044 D amdgpu_sched_jobs +ffffffff8327c048 D amdgpu_sched_hw_submission +ffffffff8327c050 D amdgpu_cg_mask +ffffffff8327c058 D amdgpu_pg_mask +ffffffff8327c05c D amdgpu_sdma_phase_quantum +ffffffff8327c060 D amdgpu_pp_feature_mask +ffffffff8327c064 D amdgpu_lbpw +ffffffff8327c068 D amdgpu_compute_multipipe +ffffffff8327c06c D amdgpu_gpu_recovery +ffffffff8327c070 D amdgpu_smu_pptable_id +ffffffff8327c074 D amdgpu_dc_feature_mask +ffffffff8327c078 D amdgpu_async_gfx_ring +ffffffff8327c07c D amdgpu_discovery +ffffffff8327c080 D amdgpu_noretry +ffffffff8327c084 D amdgpu_force_asic_type +ffffffff8327c088 D amdgpu_tmz +ffffffff8327c08c D amdgpu_reset_method +ffffffff8327c090 D amdgpu_num_kcq +ffffffff8327c094 D amdgpu_use_xgmi_p2p +ffffffff8327c098 D mgpu_info +ffffffff8327c248 D amdgpu_ras_enable +ffffffff8327c24c D amdgpu_ras_mask +ffffffff8327c250 D amdgpu_bad_page_threshold +ffffffff8327c254 D amdgpu_backlight +ffffffff8327c258 D amdgpu_cd +ffffffff8327c278 D amdgpu_stdscreen +ffffffff8327c2a8 D amdgpu_scrlist +ffffffff8327c2b0 D amdgpu_screenlist +ffffffff8327c2c0 D amdgpu_accessops +ffffffff8327d000 d amdgpu_gtt_mgr_attributes +ffffffff8327e000 D amdgpu_bbops +ffffffff8327f000 D soc15_ih_clientid_name +ffffffff83280000 D ras_error_string +ffffffff83280030 D ras_block_string +ffffffff832800c0 D ras_mca_block_string +ffffffff83281000 d amdgpu_bo_driver +ffffffff83282000 d amdgpu_vram_mgr_attributes +ffffffff83283000 D amdgpu_xgmi_hive_type +ffffffff83283008 d xgmi_mutex +ffffffff83283018 D xgmi_ras_hw_ops +ffffffff83283058 D xgmi_ras +ffffffff83284000 d gfx_v9_0_ras +ffffffff83285000 D gfx_v9_4_ras +ffffffff83286000 D gfx_v9_4_2_ras_ops +ffffffff83286040 D gfx_v9_4_2_ras +ffffffff83287000 D hdp_v4_0_ras_hw_ops +ffffffff83287040 D hdp_v4_0_ras +ffffffff83288000 d jpeg_v2_6_ras +ffffffff83289000 D mca_v3_0_mp0_ras +ffffffff83289058 D mca_v3_0_mp1_ras +ffffffff832890b0 D mca_v3_0_mpio_ras +ffffffff8328a000 D mmhub_v1_0_ras_hw_ops +ffffffff8328a040 D mmhub_v1_0_ras +ffffffff8328b000 D mmhub_v1_7_ras_hw_ops +ffffffff8328b040 D mmhub_v1_7_ras +ffffffff8328c000 D mmhub_v9_4_ras +ffffffff8328d000 D nbio_v7_4_ras +ffffffff8328e000 d sriov_sc_video_codecs_encode +ffffffff8328e010 d sriov_sc_video_codecs_decode +ffffffff8328e020 d sriov_sc_video_codecs_encode_array +ffffffff8328e050 d sriov_sc_video_codecs_decode_array +ffffffff8328f000 d sdma_v4_0_ras +ffffffff83290000 D sdma_v4_4_ras +ffffffff83291000 d sienna_cichlid_mode2_handler +ffffffff83292000 D umc_v6_1_ras +ffffffff83293000 D umc_v6_7_ras +ffffffff83294000 D umc_v8_10_ras +ffffffff83295000 D umc_v8_7_ras +ffffffff83296000 d vcn_v2_6_ras +ffffffff83297000 d amdgpu_dm_mode_config_helperfuncs +ffffffff83297010 d dm_atomic_state_funcs +ffffffff83298000 d construct_integrated_info.result +ffffffff83298004 d bios_parser_get_firmware_info.result +ffffffff83299000 d dce_funcs +ffffffff8329a000 d dce110_funcs +ffffffff8329b000 d dce112_funcs +ffffffff8329c000 d dce120_funcs +ffffffff8329d000 d rv1_clk_funcs +ffffffff8329d088 d rv1_clk_internal_funcs +ffffffff8329e000 d rv2_clk_internal_funcs +ffffffff8329f000 d dcn2_funcs +ffffffff832a0000 D dcn201_funcs +ffffffff832a1000 d dcn21_funcs +ffffffff832a1088 d rn_bw_params +ffffffff832a2000 D dcn3_fpga_funcs +ffffffff832a2088 d dcn3_funcs +ffffffff832a3000 d vg_funcs +ffffffff832a3088 d dummy_clocks +ffffffff832a31b8 d vg_bw_params +ffffffff832a4000 d dcn31_bw_params +ffffffff832a42a0 d dcn31_funcs +ffffffff832a5000 d dcn314_bw_params +ffffffff832a52a0 d dcn314_funcs +ffffffff832a6000 d dcn315_funcs +ffffffff832a6088 d dcn315_bw_params +ffffffff832a7000 d dcn316_funcs +ffffffff832a7088 d dcn316_bw_params +ffffffff832a8000 d dcn32_funcs +ffffffff832a9000 d dcn10_dpp_cap +ffffffff832aa000 D aperture_default_system +ffffffff832ab000 d dcn20_dpp_cap +ffffffff832ab010 d dcn20_dpp_funcs +ffffffff832ac000 d dcn20_hubp_funcs +ffffffff832ad000 d dcn20_opp_funcs +ffffffff832ae000 d dcn20_tg_funcs +ffffffff832af000 d dcn201_dpp_funcs +ffffffff832af110 d dcn201_dpp_cap +ffffffff832b0000 d dcn201_hubp_funcs +ffffffff832b1000 d dcn201_opp_funcs +ffffffff832b2000 d dcn201_tg_funcs +ffffffff832b3000 D dcn201_ip +ffffffff832b31b8 D dcn201_soc +ffffffff832b3b88 d dcn201_res_pool_funcs +ffffffff832b4000 d dcn21_hubp_funcs +ffffffff832b5000 d dcn30_afmt_funcs +ffffffff832b6000 d dcn30_dpp_cap +ffffffff832b6010 d dcn30_dpp_funcs +ffffffff832b7000 d dcn30_hubp_funcs +ffffffff832b8000 d dcn30_tg_funcs +ffffffff832b9000 d dcn30_vpg_funcs +ffffffff832ba000 d res_cap_dcn301 +ffffffff832ba040 d dcn301_res_pool_funcs +ffffffff832bb000 d dcn302_res_pool_funcs +ffffffff832bc000 d dcn303_res_pool_funcs +ffffffff832bd000 d dcn31_afmt_funcs +ffffffff832be000 d dcn31_apg_funcs +ffffffff832bf000 d dcn31_hpo_dp_link_encoder_funcs +ffffffff832c0000 d dcn31_hubp_funcs +ffffffff832c1000 d dcn31_tg_funcs +ffffffff832c2000 d dcn31_res_pool_funcs +ffffffff832c3000 d dcn31_vpg_funcs +ffffffff832c4000 d dcn314_tg_funcs +ffffffff832c5000 d dcn314_res_pool_funcs +ffffffff832c6000 d dcn315_res_pool_funcs +ffffffff832c7000 d dcn316_res_pool_funcs +ffffffff832c8000 d dcn32_dpp_funcs +ffffffff832c8110 d dcn32_dpp_cap +ffffffff832c9000 d dcn32_hpo_dp_link_encoder_funcs +ffffffff832ca000 d dcn32_hubp_funcs +ffffffff832cb000 d dcn32_tg_funcs +ffffffff832cc000 d dcn32_res_pool_funcs +ffffffff832cd000 d dcn321_res_pool_funcs +ffffffff832ce000 D dcn1_0_ip +ffffffff832ce1b8 D dcn1_0_soc +ffffffff832cf000 D dcn2_0_ip +ffffffff832cf1b8 D dcn2_0_nv14_ip +ffffffff832cf370 D dcn2_0_soc +ffffffff832cfd40 D dcn2_0_nv14_soc +ffffffff832d0710 D dcn2_1_ip +ffffffff832d08c8 D dcn2_1_soc +ffffffff832d1298 D ddr4_wm_table_gs +ffffffff832d1358 D lpddr4_wm_table_gs +ffffffff832d1418 D lpddr4_wm_table_with_disabled_ppt +ffffffff832d14d8 D ddr4_wm_table_rn +ffffffff832d1598 D ddr4_1R_wm_table_rn +ffffffff832d1658 D lpddr4_wm_table_rn +ffffffff832d2000 D dcn3_0_ip +ffffffff832d21b8 D dcn3_0_soc +ffffffff832d3000 D dcn3_01_ip +ffffffff832d31b8 D dcn3_01_soc +ffffffff832d3b88 D ddr4_wm_table +ffffffff832d3c48 D lpddr5_wm_table +ffffffff832d4000 D dcn3_02_ip +ffffffff832d41b8 D dcn3_02_soc +ffffffff832d5000 D dcn3_03_ip +ffffffff832d51b8 D dcn3_03_soc +ffffffff832d6000 D dcn3_1_ip +ffffffff832d61b8 D dcn3_15_ip +ffffffff832d6370 D dcn3_16_ip +ffffffff832d6528 d dcn3_15_soc +ffffffff832d6ef8 d dcn3_1_soc +ffffffff832d78c8 d dcn3_16_soc +ffffffff832d9000 D dcn3_14_ip +ffffffff832d91b8 D dcn3_14_soc +ffffffff832da000 D dcn3_2_ip +ffffffff832da1b8 D dcn3_2_soc +ffffffff832db000 D dcn3_21_ip +ffffffff832db1b8 D dcn3_21_soc +ffffffff832dc000 d dsc_policy_max_target_bpp_limit +ffffffff832dd000 D DIDTEDCConfig_P12 +ffffffff832dd070 d smu7_profiling +ffffffff832de000 d cyan_skillfish_table_map +ffffffff832de080 d cyan_skillfish_message_map +ffffffff832df000 d navi10_table_map +ffffffff832df080 d navi10_pwr_src_map +ffffffff832df090 d navi10_workload_map +ffffffff832df0d0 d navi10_message_map +ffffffff832dfb20 d navi10_clk_map +ffffffff832dfbe0 d navi10_feature_mask_map +ffffffff832e0000 d sienna_cichlid_message_map +ffffffff832e0a50 d sienna_cichlid_table_map +ffffffff832e0ad0 d sienna_cichlid_pwr_src_map +ffffffff832e0ae0 d sienna_cichlid_workload_map +ffffffff832e0b20 d sienna_cichlid_clk_map +ffffffff832e0be0 d sienna_cichlid_feature_mask_map +ffffffff832e1000 d vangogh_message_map +ffffffff832e1a50 d vangogh_table_map +ffffffff832e1ad0 d vangogh_workload_map +ffffffff832e1b10 d vangogh_feature_mask_map +ffffffff832e2000 d renoir_table_map +ffffffff832e2080 d renoir_workload_map +ffffffff832e20c0 d renoir_message_map +ffffffff832e2b10 d renoir_clk_map +ffffffff832e3000 d smu_v13_0_0_message_map +ffffffff832e3a50 d smu_v13_0_0_feature_mask_map +ffffffff832e3e20 d smu_v13_0_0_table_map +ffffffff832e3ea0 d smu_v13_0_0_pwr_src_map +ffffffff832e3eb0 d smu_v13_0_0_workload_map +ffffffff832e3ef0 d smu_v13_0_0_clk_map +ffffffff832e4000 d smu_v13_0_4_message_map +ffffffff832e4a50 d smu_v13_0_4_table_map +ffffffff832e4ad0 d smu_v13_0_4_feature_mask_map +ffffffff832e5000 d smu_v13_0_5_table_map +ffffffff832e5080 d smu_v13_0_5_message_map +ffffffff832e5ad0 d smu_v13_0_5_feature_mask_map +ffffffff832e6000 d smu_v13_0_7_message_map +ffffffff832e6a50 d smu_v13_0_7_feature_mask_map +ffffffff832e6e20 d smu_v13_0_7_table_map +ffffffff832e6ea0 d smu_v13_0_7_pwr_src_map +ffffffff832e6eb0 d smu_v13_0_7_workload_map +ffffffff832e6ef0 d smu_v13_0_7_clk_map +ffffffff832e7000 d yellow_carp_table_map +ffffffff832e7080 d yellow_carp_message_map +ffffffff832e7ad0 d yellow_carp_feature_mask_map +ffffffff832e8000 D pci_conf_lock +ffffffff832e8010 D pci_bus_dma_tag +ffffffff832e8088 D msi_pic +ffffffff832e8118 D msix_pic +ffffffff832e9000 D pchb_cd +ffffffff832ea000 D amas_cd +ffffffff832eb000 D cardslot_cd +ffffffff832ec000 D cardbus_cd +ffffffff832ed000 d csdevs +ffffffff832ee000 d ral_rt2560_opns +ffffffff832ee028 d ral_rt2661_opns +ffffffff832ee050 d ral_rt2860_opns +ffffffff832ef000 D pcmcia_cd +ffffffff832f0000 D pcmcia_3cxem556_func0 +ffffffff832f00b8 D pcmcia_3cxem556_func0_cfe0 +ffffffff832f0158 D pcmcia_megahertz_xjem1144_func0 +ffffffff832f0210 D pcmcia_megahertz_xjem1144_func0_cfe0 +ffffffff832f02b0 d pcmcia_3cxem556_func1 +ffffffff832f0368 d pcmcia_3cxem556_func1_cfe0 +ffffffff832f0408 d pcmcia_megahertz_xjem1144_func1 +ffffffff832f04c0 d pcmcia_megahertz_xjem1144_func1_cfe0 +ffffffff832f0560 d pcmcia_sierra_a555_func1 +ffffffff832f0618 d pcmcia_sierra_a555_func1_cfe0 +ffffffff832f06b8 d pcmcia_sveclancard_func0 +ffffffff832f0770 d pcmcia_sveclancard_func0_cfe0 +ffffffff832f1000 D ep_pcmcia_prod +ffffffff832f2000 D aic_pcmcia_prod +ffffffff832f3000 D com_pcmcia_prod +ffffffff832f4000 D wdc_pcmcia_pr +ffffffff832f5000 D sm_pcmcia_prod +ffffffff832f6000 D xe_cd +ffffffff832f7000 D pcib_cd +ffffffff832f8000 D amdpcib_cd +ffffffff832f9000 D tcpcib_cd +ffffffff832fa000 D aapic_cd +ffffffff832fb000 D hme_cd +ffffffff832fc000 D isa_cd +ffffffff832fd000 D isadma_cd +ffffffff832fe000 D fdc_cd +ffffffff832ff000 D fd_types +ffffffff832ff1f8 D fd_cd +ffffffff83300000 D mpu_cd +ffffffff83301000 D pcppi_cd +ffffffff83302000 D spkr_cd +ffffffff83303000 D wbsio_cd +ffffffff83304000 D schsio_cd +ffffffff83305000 D it_cd +ffffffff83306000 D uguru_cd +ffffffff83307000 D aps_cd +ffffffff83308000 D isa_bus_dma_tag +ffffffff83309000 D wsdisplay_cd +ffffffff83309020 D wsdisplay_cons +ffffffff83309058 D wsdisplay_defaultscreens +ffffffff8330a000 D wskbd_cd +ffffffff8330a020 D wskbd_default_bell_data +ffffffff8330a030 D wskbd_default_keyrepeat_data +ffffffff8330a040 D wskbd_srcops +ffffffff8330b000 d compose_tab +ffffffff8330c000 D wsmouse_cd +ffffffff8330c020 D wsmouse_srcops +ffffffff8330d000 D wsmux_srcops +ffffffff8330d030 D wsmux_tree_lock +ffffffff8330e000 D vt100_output +ffffffff8330f000 D pckbd_cd +ffffffff83310000 D pms_cd +ffffffff83310020 d synaptics_params +ffffffff83310030 d alps_params +ffffffff83311000 D skgpio_cd +ffffffff83312000 D pctr_conf_lock +ffffffff83313000 D ukbd_keymapdata +ffffffff83314000 D usbrev_str +ffffffff83314030 D usb_cd +ffffffff83315000 d usbd_ratecheck.errinterval +ffffffff83316000 D uhub_cd +ffffffff83317000 D uaudio_cd +ffffffff83318000 D uvideo_ctrls +ffffffff833182d8 D uvideo_cd +ffffffff83319000 D utvfu_norm_params +ffffffff83319030 D utvfu_cd +ffffffff8331a000 D udl_reg_vals_640x480_60 +ffffffff8331a020 D udl_reg_vals_640x480_67 +ffffffff8331a040 D udl_reg_vals_640x480_72 +ffffffff8331a060 D udl_reg_vals_640x480_75 +ffffffff8331a080 D udl_reg_vals_800x480_61 +ffffffff8331a0a0 D udl_reg_vals_800x600_56 +ffffffff8331a0c0 D udl_reg_vals_800x600_60 +ffffffff8331a0e0 D udl_reg_vals_800x600_72 +ffffffff8331a100 D udl_reg_vals_800x600_74 +ffffffff8331a120 D udl_reg_vals_800x600_75 +ffffffff8331a140 D udl_reg_vals_1024x768_60 +ffffffff8331a160 D udl_reg_vals_1024x768_70 +ffffffff8331a180 D udl_reg_vals_1024x768_75 +ffffffff8331a1a0 D udl_reg_vals_1280x800_60 +ffffffff8331a1c0 D udl_reg_vals_1280x960_60 +ffffffff8331a1e0 D udl_reg_vals_1280x1024_60 +ffffffff8331a200 D udl_reg_vals_1280x1024_75 +ffffffff8331a220 D udl_reg_vals_1366x768_60 +ffffffff8331a240 D udl_reg_vals_1440x900_60 +ffffffff8331a260 D udl_reg_vals_1440x900_59 +ffffffff8331a280 D udl_reg_vals_1440x900_75 +ffffffff8331a2a0 D udl_reg_vals_1680x1050_60 +ffffffff8331a2c0 D udl_reg_vals_1600x1200_60 +ffffffff8331a2e0 D udl_reg_vals_1920x1080_60 +ffffffff8331a300 D udl_null_key_1 +ffffffff8331a310 D udl_decomp_table +ffffffff8331b510 D udl_cd +ffffffff8331b530 D udl_stdscreen +ffffffff8331b560 D udl_scrlist +ffffffff8331b568 D udl_screenlist +ffffffff8331b578 D udl_accessops +ffffffff8331c000 D umidi_cd +ffffffff8331d000 d umq_YAMAHA_YAMAHA_UX256_ANYIFACE +ffffffff8331d020 d umq_ROLAND_ROLAND_UM1_2 +ffffffff8331d040 d umq_ROLAND_ROLAND_SC8850_2 +ffffffff8331d060 d umq_ROLAND_ROLAND_SD90_2 +ffffffff8331d080 d umq_ROLAND_ROLAND_UM880N_0 +ffffffff8331d0a0 d umq_ROLAND_ROLAND_UA100_2 +ffffffff8331d0c0 d umq_ROLAND_ROLAND_UM4_2 +ffffffff8331d0e0 d umq_ROLAND_ROLAND_U8_2 +ffffffff8331d100 d umq_ROLAND_ROLAND_UM2_2 +ffffffff8331d120 d umq_ROLAND_ROLAND_SC8820_2 +ffffffff8331d140 d umq_ROLAND_ROLAND_PC300_2 +ffffffff8331d160 d umq_ROLAND_ROLAND_SK500_2 +ffffffff8331d180 d umq_ROLAND_ROLAND_SCD70_2 +ffffffff8331d1a0 d umq_ROLAND_ROLAND_UM550_0 +ffffffff8331d1c0 d umq_ROLAND_ROLAND_SD20_0 +ffffffff8331d1e0 d umq_ROLAND_ROLAND_SD80_0 +ffffffff8331d200 d umq_ROLAND_ROLAND_UA700_3 +ffffffff8331d220 d umq_ROLAND_ROLAND_UMONE_ANYIFACE +ffffffff8331d240 D umidi_quirklist +ffffffff8331d4a0 d umq_YAMAHA_YAMAHA_UX256_ANYIFACE_fixed_ep_desc +ffffffff8331d4c0 d umq_YAMAHA_YAMAHA_UX256_ANYIFACE_fixed_ep_endpoints +ffffffff8331d4d0 d umq_ROLAND_ROLAND_UM1_2_fixed_ep_desc +ffffffff8331d4f0 d umq_ROLAND_ROLAND_UM1_2_fixed_ep_endpoints +ffffffff8331d500 d umq_ROLAND_ROLAND_SC8850_2_fixed_ep_desc +ffffffff8331d520 d umq_ROLAND_ROLAND_SC8850_2_fixed_ep_endpoints +ffffffff8331d530 d umq_ROLAND_ROLAND_SD90_2_fixed_ep_desc +ffffffff8331d550 d umq_ROLAND_ROLAND_SD90_2_fixed_ep_endpoints +ffffffff8331d560 d umq_ROLAND_ROLAND_UM880N_0_fixed_ep_desc +ffffffff8331d580 d umq_ROLAND_ROLAND_UM880N_0_fixed_ep_endpoints +ffffffff8331d590 d umq_ROLAND_ROLAND_UA100_2_fixed_ep_desc +ffffffff8331d5b0 d umq_ROLAND_ROLAND_UA100_2_fixed_ep_endpoints +ffffffff8331d5c0 d umq_ROLAND_ROLAND_UM4_2_fixed_ep_desc +ffffffff8331d5e0 d umq_ROLAND_ROLAND_UM4_2_fixed_ep_endpoints +ffffffff8331d5f0 d umq_ROLAND_ROLAND_U8_2_fixed_ep_desc +ffffffff8331d610 d umq_ROLAND_ROLAND_U8_2_fixed_ep_endpoints +ffffffff8331d620 d umq_ROLAND_ROLAND_UM2_2_fixed_ep_desc +ffffffff8331d640 d umq_ROLAND_ROLAND_UM2_2_fixed_ep_endpoints +ffffffff8331d650 d umq_ROLAND_ROLAND_SC8820_2_fixed_ep_desc +ffffffff8331d670 d umq_ROLAND_ROLAND_SC8820_2_fixed_ep_endpoints +ffffffff8331d680 d umq_ROLAND_ROLAND_PC300_2_fixed_ep_desc +ffffffff8331d6a0 d umq_ROLAND_ROLAND_PC300_2_fixed_ep_endpoints +ffffffff8331d6b0 d umq_ROLAND_ROLAND_SK500_2_fixed_ep_desc +ffffffff8331d6d0 d umq_ROLAND_ROLAND_SK500_2_fixed_ep_endpoints +ffffffff8331d6e0 d umq_ROLAND_ROLAND_SCD70_2_fixed_ep_desc +ffffffff8331d700 d umq_ROLAND_ROLAND_SCD70_2_fixed_ep_endpoints +ffffffff8331d710 d umq_ROLAND_ROLAND_UM550_0_fixed_ep_desc +ffffffff8331d730 d umq_ROLAND_ROLAND_UM550_0_fixed_ep_endpoints +ffffffff8331d740 d umq_ROLAND_ROLAND_SD20_0_fixed_ep_desc +ffffffff8331d760 d umq_ROLAND_ROLAND_SD20_0_fixed_ep_endpoints +ffffffff8331d770 d umq_ROLAND_ROLAND_SD80_0_fixed_ep_desc +ffffffff8331d790 d umq_ROLAND_ROLAND_SD80_0_fixed_ep_endpoints +ffffffff8331d7a0 d umq_ROLAND_ROLAND_UA700_3_fixed_ep_desc +ffffffff8331d7c0 d umq_ROLAND_ROLAND_UA700_3_fixed_ep_endpoints +ffffffff8331d7d0 d umq_ROLAND_ROLAND_UMONE_ANYIFACE_fixed_ep_desc +ffffffff8331d7f0 d umq_ROLAND_ROLAND_UMONE_ANYIFACE_fixed_ep_endpoints +ffffffff8331e000 D ucom_cd +ffffffff8331f000 D ugen_cd +ffffffff83320000 D uhidev_cd +ffffffff83320020 d uhidev_use_rdesc.reportbuf +ffffffff83321000 D uhid_cd +ffffffff83322000 D fido_cd +ffffffff83323000 D ujoy_cd +ffffffff83324000 D ukbd_cd +ffffffff83325000 D ums_cd +ffffffff83325020 d ums_fix_elecom_descriptor.match +ffffffff83326000 D umt_cd +ffffffff83327000 D def_scale +ffffffff83327020 D uts_cd +ffffffff83328000 D ubcmtp_cd +ffffffff83329000 D ucycom_cd +ffffffff8332a000 D uslhcom_cd +ffffffff8332b000 D ulpt_fwdevs +ffffffff8332b060 D ulpt_cd +ffffffff8332b080 D ulptusein +ffffffff8332c000 D umass_cd +ffffffff8332c020 d umass_bbb_transfer.dCBWtag +ffffffff8332d000 D uthum_cd +ffffffff8332e000 D ugold_cd +ffffffff8332e020 d cmd_init +ffffffff8332e028 d cmd_type +ffffffff8332e030 d cmd_data +ffffffff8332f000 D utrh_cd +ffffffff83330000 D uoakrh_cd +ffffffff83331000 D uoaklux_cd +ffffffff83332000 D uoakv_cd +ffffffff83333000 D uonerng_cd +ffffffff83334000 D urng_cd +ffffffff83335000 D udcf_cd +ffffffff83336000 D umbg_cd +ffffffff83337000 D uvisor_cd +ffffffff83338000 D udsbr_cd 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sr_bootkey +ffffffff833e6030 B softraid0 +ffffffff833e6038 B sr_hotplug_callbacks +ffffffff833e7000 B gf_pow +ffffffff833e7300 B gf_map +ffffffff833e7b00 B gf_log +ffffffff833e8000 b ksym_syms +ffffffff833e8008 b ksym_syms_size +ffffffff833e9000 B kstat_version +ffffffff833e9008 B kstat_id_tree +ffffffff833e9010 B kstat_pv_tree +ffffffff833e9018 B kstat_nm_tree +ffffffff833e9020 b kstat_init.initialized +ffffffff833e9028 B kstat_pool +ffffffff833ea000 B stat_fbufs_in +ffffffff833ea004 B stat_fbufs_wait +ffffffff833ea008 B stat_opened_fusedev +ffffffff833ea010 B fuse_d_list +ffffffff833eb000 B fusefs_fbuf_pool +ffffffff833ec000 B pf_npurge +ffffffff833ec008 B pf_state_pl +ffffffff833ec1b0 B pf_src_tree_pl +ffffffff833ec358 B pf_pktdelay_pl +ffffffff833ec500 B pf_status +ffffffff833ec6e8 B tree_id +ffffffff833ec6f0 B tree_src_tracking +ffffffff833ec6f8 B pf_sn_item_pl +ffffffff833ec8a0 B pf_statetbl +ffffffff833ec8a8 B pf_state_item_pl +ffffffff833eca50 B pf_state_key_pl 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audio_record_enable +ffffffff8340e000 B constty +ffffffff8340e008 B cn_devvp +ffffffff8340e010 b cnpollc.refcount +ffffffff8340f000 B numvnd +ffffffff8340f008 B vnd_softc +ffffffff83410000 B rnd_event_prod +ffffffff83410010 B rnd_event_space +ffffffff83410410 B rnd_event_cons +ffffffff83410414 b add_entropy_words.entropy_add_ptr +ffffffff83410418 b add_entropy_words.entropy_input_rotate +ffffffff83410420 b entropy_pool +ffffffff83412420 b extract_entropy.extract_pool +ffffffff83414420 b rs_count +ffffffff83414428 b rs_have +ffffffff83414430 b rs_buf +ffffffff83414830 b rs +ffffffff83414870 b _rs_stir_if_needed.rs_initialized +ffffffff83415000 B video_record_enable +ffffffff83416000 B iso_nchstats +ffffffff83417000 B isohash +ffffffff83417008 B isohashtbl +ffffffff83417010 B isohashkey +ffffffff83418000 B cd9660_wchar2char +ffffffff83419000 B udf_trans_pool +ffffffff834191a8 B unode_pool +ffffffff83419350 B udf_ds_pool +ffffffff8341a000 B exec_maxhdrsz +ffffffff8341b000 B db_active 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