--- 7.2/2023-04-09T08:07:27Z/2023-03-27T00:00:00Z/nm-bsd-ot14.txt	Tue Apr 11 11:18:27 2023
+++ 7.2/2023-04-09T08:07:27Z/2023-03-28T00:00:00Z/nm-bsd-ot14.txt	Tue Apr 11 14:15:41 2023
@@ -7,9 +7,9 @@
 0251d000 C __kernel_rodata_phys
 02dce000 R __kernel_kutext_page_phys
 02dd0000 C __kernel_randomdata_phys
-03093000 R __kernel_data_phys
-033c3000 D __kernel_kudata_phys
-033c4000 C __kernel_bss_phys
+03092000 R __kernel_data_phys
+033c2000 D __kernel_kudata_phys
+033c3000 C __kernel_bss_phys
 03800000 B __kernel_phys_end
 80000000 A __kernel_virt_to_phys
 ffffffff80000000 A __kernel_base
@@ -18531,29 +18531,29 @@ ffffffff81922d10 T drm_detect_monitor_audio
 ffffffff81922f10 T drm_default_rgb_quant_range
 ffffffff81922f50 T drm_edid_connector_update
 ffffffff81922fb0 t _drm_edid_connector_update
-ffffffff81924880 t _drm_update_tile_info
-ffffffff81924b10 t _drm_edid_connector_property_update
-ffffffff81924cc0 T drm_add_modes_noedid
-ffffffff81924da0 T drm_set_preferred_mode
-ffffffff81924e00 T drm_hdmi_avi_infoframe_from_display_mode
-ffffffff81925070 T drm_hdmi_avi_infoframe_quant_range
-ffffffff81925110 T drm_hdmi_vendor_infoframe_from_display_mode
-ffffffff819251d0 t connector_bad_edid
-ffffffff81925390 t drm_for_each_detailed_block
-ffffffff819255e0 t __cea_db_iter_next
-ffffffff81925880 t update_display_info
-ffffffff81926700 t get_monitor_range
-ffffffff819267a0 t do_detailed_mode
-ffffffff819270c0 t hdmi_mode_alternate_clock
-ffffffff81927170 t do_cvt_mode
-ffffffff819273c0 t drm_mode_std
-ffffffff819280d0 t do_standard_modes
-ffffffff81928210 t drm_monitor_supports_rb
-ffffffff81928500 t drm_gtf2_hbreak
-ffffffff81928790 t do_established_modes
-ffffffff81928990 t drm_match_hdmi_mode
-ffffffff81928bd0 t do_inferred_modes
-ffffffff81929140 t mode_in_range
+ffffffff81924e60 t _drm_update_tile_info
+ffffffff819250f0 t _drm_edid_connector_property_update
+ffffffff819252a0 T drm_add_modes_noedid
+ffffffff81925380 T drm_set_preferred_mode
+ffffffff819253e0 T drm_hdmi_avi_infoframe_from_display_mode
+ffffffff81925660 T drm_hdmi_avi_infoframe_quant_range
+ffffffff81925700 T drm_hdmi_vendor_infoframe_from_display_mode
+ffffffff819257c0 t connector_bad_edid
+ffffffff81925980 t drm_for_each_detailed_block
+ffffffff81925bd0 t __cea_db_iter_next
+ffffffff81925e70 t update_display_info
+ffffffff81926cf0 t get_monitor_range
+ffffffff81926d90 t do_detailed_mode
+ffffffff819276b0 t hdmi_mode_alternate_clock
+ffffffff81927760 t do_cvt_mode
+ffffffff819279b0 t drm_mode_std
+ffffffff819286c0 t do_standard_modes
+ffffffff81928800 t drm_monitor_supports_rb
+ffffffff81928af0 t drm_gtf2_hbreak
+ffffffff81928d80 t do_established_modes
+ffffffff81928f80 t drm_match_hdmi_mode
+ffffffff819291c0 t do_inferred_modes
+ffffffff81929730 t mode_in_range
 ffffffff8192a000 T drm_encoder_register_all
 ffffffff8192a080 T drm_encoder_unregister_all
 ffffffff8192a0f0 T drm_encoder_init
@@ -19015,9 +19015,9 @@ ffffffff8194a0a0 T drm_modeset_unregister_all
 ffffffff8194a0d0 T drm_mode_getresources
 ffffffff8194a380 T drm_mode_config_reset
 ffffffff8194a4d0 T drmm_mode_config_init
-ffffffff8194ab00 t drm_mode_config_init_release
-ffffffff8194ab10 T drm_mode_config_cleanup
-ffffffff8194ae50 T drm_mode_config_validate
+ffffffff8194ab50 T drm_mode_config_cleanup
+ffffffff8194ae90 t drm_mode_config_init_release
+ffffffff8194aea0 T drm_mode_config_validate
 ffffffff8194c000 T __drm_mode_object_add
 ffffffff8194c100 T drm_mode_object_add
 ffffffff8194c1d0 T drm_mode_object_register
@@ -19478,63 +19478,64 @@ ffffffff8197a710 t drm_dp_mst_topology_put_port
 ffffffff8197a840 t drm_dp_mst_wait_tx_reply
 ffffffff8197ab90 T drm_dp_send_query_stream_enc_status
 ffffffff8197ae50 T drm_dp_add_payload_part1
-ffffffff8197afd0 T drm_dp_remove_payload
-ffffffff8197b160 T drm_dp_add_payload_part2
-ffffffff8197b310 T drm_dp_get_vc_payload_bw
-ffffffff8197b3a0 T drm_dp_read_mst_cap
-ffffffff8197b400 T drm_dp_mst_topology_mgr_set_mst
-ffffffff8197b690 t drm_dp_dpcd_write_payload
-ffffffff8197b820 t drm_dp_mst_topology_put_mstb
-ffffffff8197b920 T drm_dp_mst_topology_mgr_suspend
-ffffffff8197b9e0 t drm_dp_mst_topology_mgr_invalidate_mstb
-ffffffff8197ba50 T drm_dp_mst_topology_mgr_resume
-ffffffff8197bc90 T drm_dp_mst_hpd_irq
-ffffffff8197cb10 T drm_dp_mst_detect_port
-ffffffff8197cc80 T drm_dp_mst_get_edid
-ffffffff8197cd80 T drm_dp_atomic_find_time_slots
-ffffffff8197d050 T drm_atomic_get_mst_topology_state
-ffffffff8197d060 T drm_dp_atomic_release_time_slots
-ffffffff8197d280 T drm_dp_mst_atomic_setup_commit
-ffffffff8197d410 T drm_dp_mst_atomic_wait_for_dependencies
-ffffffff8197d590 T drm_dp_mst_root_conn_atomic_check
-ffffffff8197d6a0 T drm_dp_mst_update_slots
-ffffffff8197d6f0 T drm_dp_check_act_status
-ffffffff8197d8a0 T drm_dp_calc_pbn_mode
-ffffffff8197d910 T drm_dp_mst_dump_topology
-ffffffff8197db60 t drm_dp_mst_dump_mstb
-ffffffff8197dbd0 T drm_dp_mst_add_affected_dsc_crtcs
-ffffffff8197dd00 T drm_dp_mst_dsc_aux_for_port
-ffffffff8197df20 T drm_dp_mst_atomic_enable_dsc
-ffffffff8197e0c0 T drm_dp_mst_atomic_check
-ffffffff8197e3a0 t drm_dp_mst_atomic_check_mstb_bw_limit
-ffffffff8197e670 t drm_dp_mst_duplicate_state
-ffffffff8197e840 t drm_dp_mst_destroy_state
-ffffffff8197e900 T drm_atomic_get_new_mst_topology_state
-ffffffff8197e910 T drm_dp_mst_topology_mgr_init
-ffffffff8197eb70 t drm_dp_mst_link_probe_work
-ffffffff8197ee10 t drm_dp_tx_work
-ffffffff8197ee50 t drm_dp_delayed_destroy_work
-ffffffff8197f270 t drm_dp_mst_up_req_work
-ffffffff8197f770 T drm_dp_mst_topology_mgr_destroy
-ffffffff8197f7f0 t drm_dp_mst_is_virtual_dpcd
-ffffffff8197f8d0 t drm_dp_free_mst_branch_device
-ffffffff8197f910 t drm_dp_mst_topology_get_port_validated_locked
-ffffffff8197f990 t drm_dp_mst_dump_sideband_msg_tx
-ffffffff8197fba0 t process_single_down_tx_qlock
-ffffffff8197fd10 t process_single_tx_qlock
-ffffffff819801f0 t drm_dp_msg_data_crc4
-ffffffff81980310 t drm_dp_payload_send_msg
-ffffffff81980760 t drm_dp_mst_topology_get_mstb_validated_locked
-ffffffff819807e0 t drm_dp_get_one_sb_msg
-ffffffff81980f00 t drm_dp_get_mst_branch_device
-ffffffff81981070 t drm_dp_check_and_send_link_address
-ffffffff81981140 t drm_dp_send_link_address
-ffffffff81981df0 t drm_dp_send_enum_path_resources
-ffffffff81982050 t drm_dp_port_set_pdt
-ffffffff81982330 t drm_dp_mst_port_add_connector
-ffffffff81982510 t drm_dp_mst_i2c_xfer
-ffffffff81982c00 t drm_dp_mst_i2c_functionality
-ffffffff81982c30 t get_mst_branch_device_by_guid_helper
+ffffffff8197b000 T drm_dp_remove_payload
+ffffffff8197b190 T drm_dp_add_payload_part2
+ffffffff8197b340 T drm_dp_get_vc_payload_bw
+ffffffff8197b3d0 T drm_dp_read_mst_cap
+ffffffff8197b430 T drm_dp_mst_topology_mgr_set_mst
+ffffffff8197b6f0 t drm_dp_dpcd_write_payload
+ffffffff8197b880 t drm_dp_mst_topology_put_mstb
+ffffffff8197b980 T drm_dp_mst_topology_mgr_suspend
+ffffffff8197ba40 t drm_dp_mst_topology_mgr_invalidate_mstb
+ffffffff8197bab0 T drm_dp_mst_topology_mgr_resume
+ffffffff8197bcf0 T drm_dp_mst_hpd_irq
+ffffffff8197cb60 T drm_dp_mst_detect_port
+ffffffff8197ccd0 T drm_dp_mst_get_edid
+ffffffff8197cdd0 T drm_dp_atomic_find_time_slots
+ffffffff8197d0a0 T drm_atomic_get_mst_topology_state
+ffffffff8197d0b0 T drm_dp_atomic_release_time_slots
+ffffffff8197d2d0 T drm_dp_mst_atomic_setup_commit
+ffffffff8197d460 T drm_dp_mst_atomic_wait_for_dependencies
+ffffffff8197d5e0 T drm_dp_mst_root_conn_atomic_check
+ffffffff8197d6f0 T drm_dp_mst_update_slots
+ffffffff8197d740 T drm_dp_check_act_status
+ffffffff8197d8f0 T drm_dp_calc_pbn_mode
+ffffffff8197d960 T drm_dp_mst_dump_topology
+ffffffff8197dbb0 t drm_dp_mst_dump_mstb
+ffffffff8197dc20 T drm_dp_mst_add_affected_dsc_crtcs
+ffffffff8197dd50 T drm_dp_mst_dsc_aux_for_port
+ffffffff8197df70 T drm_dp_mst_atomic_enable_dsc
+ffffffff8197e110 T drm_dp_mst_atomic_check
+ffffffff8197e3f0 t drm_dp_mst_atomic_check_mstb_bw_limit
+ffffffff8197e6c0 t drm_dp_mst_duplicate_state
+ffffffff8197e890 t drm_dp_mst_destroy_state
+ffffffff8197e950 T drm_atomic_get_old_mst_topology_state
+ffffffff8197e960 T drm_atomic_get_new_mst_topology_state
+ffffffff8197e970 T drm_dp_mst_topology_mgr_init
+ffffffff8197ebd0 t drm_dp_mst_link_probe_work
+ffffffff8197ee70 t drm_dp_tx_work
+ffffffff8197eeb0 t drm_dp_delayed_destroy_work
+ffffffff8197f2d0 t drm_dp_mst_up_req_work
+ffffffff8197f7d0 T drm_dp_mst_topology_mgr_destroy
+ffffffff8197f850 t drm_dp_mst_is_virtual_dpcd
+ffffffff8197f930 t drm_dp_free_mst_branch_device
+ffffffff8197f970 t drm_dp_mst_topology_get_port_validated_locked
+ffffffff8197f9f0 t drm_dp_mst_dump_sideband_msg_tx
+ffffffff8197fc00 t process_single_down_tx_qlock
+ffffffff8197fd70 t process_single_tx_qlock
+ffffffff81980250 t drm_dp_msg_data_crc4
+ffffffff81980370 t drm_dp_payload_send_msg
+ffffffff819807c0 t drm_dp_mst_topology_get_mstb_validated_locked
+ffffffff81980840 t drm_dp_get_one_sb_msg
+ffffffff81980f60 t drm_dp_get_mst_branch_device
+ffffffff819810d0 t drm_dp_check_and_send_link_address
+ffffffff819811a0 t drm_dp_send_link_address
+ffffffff81981e50 t drm_dp_send_enum_path_resources
+ffffffff819820b0 t drm_dp_port_set_pdt
+ffffffff81982390 t drm_dp_mst_port_add_connector
+ffffffff81982570 t drm_dp_mst_i2c_xfer
+ffffffff81982c60 t drm_dp_mst_i2c_functionality
+ffffffff81982c90 t get_mst_branch_device_by_guid_helper
 ffffffff81983000 T drm_dsc_dp_pps_header_init
 ffffffff81983030 T drm_dsc_dp_rc_buffer_size
 ffffffff81983090 T drm_dsc_pps_payload_pack
@@ -20410,59 +20411,59 @@ ffffffff819eefd0 T intel_pipe_config_compare
 ffffffff819f1ac0 t pipe_config_mismatch
 ffffffff819f1bb0 t pipe_config_infoframe_mismatch
 ffffffff819f1d60 T intel_modeset_all_pipes
-ffffffff819f1ef0 T intel_atomic_add_affected_planes
-ffffffff819f1fc0 T intel_crtc_update_active_timings
-ffffffff819f20c0 T intel_calc_active_pipes
-ffffffff819f2140 T intel_crtc_arm_fifo_underrun
-ffffffff819f21e0 T intel_plane_destroy
-ffffffff819f2210 T intel_get_pipe_from_crtc_id_ioctl
-ffffffff819f2280 T intel_mode_valid_max_plane_size
-ffffffff819f2300 T intel_init_display_hooks
-ffffffff819f23e0 T intel_modeset_init_noirq
-ffffffff819f2690 t intel_atomic_helper_free_state_worker
-ffffffff819f2700 T intel_modeset_init_nogem
-ffffffff819f3830 T intel_modeset_init
-ffffffff819f3a50 T i830_enable_pipe
-ffffffff819f4080 T i830_disable_pipe
-ffffffff819f43a0 T intel_display_resume
-ffffffff819f44e0 T intel_modeset_driver_remove
-ffffffff819f4590 T intel_modeset_driver_remove_noirq
-ffffffff819f4700 T intel_modeset_driver_remove_nogem
-ffffffff819f4730 T intel_modeset_probe_defer
-ffffffff819f4760 T intel_display_driver_register
-ffffffff819f47c0 T intel_display_driver_unregister
-ffffffff819f4840 T intel_scanout_needs_vtd_wa
-ffffffff819f4880 t wait_for_pipe_scanline_moving
-ffffffff819f4ae0 t hsw_get_pipe_config
-ffffffff819f58d0 t hsw_crtc_enable
-ffffffff819f6300 t hsw_crtc_disable
-ffffffff819f64b0 t skl_commit_modeset_enables
-ffffffff819f6a70 t intel_get_transcoder_timings
-ffffffff819f6d40 t ilk_get_pfit_config
-ffffffff819f6ec0 t enabled_bigjoiner_pipes
-ffffffff819f70d0 t bdw_set_pipemisc
-ffffffff819f7210 t ilk_pfit_enable
-ffffffff819f7320 t intel_set_transcoder_timings
-ffffffff819f76e0 t intel_update_crtc
-ffffffff819f7cd0 t intel_pre_plane_update
-ffffffff819f81e0 t intel_commit_modeset_enables
-ffffffff819f82f0 t ilk_get_pipe_config
-ffffffff819f8630 t ilk_crtc_enable
-ffffffff819f8ce0 t ilk_crtc_disable
-ffffffff819f8f70 t i9xx_get_pipe_config
-ffffffff819f98a0 t valleyview_crtc_enable
-ffffffff819f9cb0 t i9xx_crtc_disable
-ffffffff819fa030 t i9xx_pfit_enable
-ffffffff819fa190 t i9xx_crtc_enable
-ffffffff819fa510 t intel_mode_valid
-ffffffff819fa6c0 t intel_atomic_check
-ffffffff819fd9c0 t intel_atomic_commit
-ffffffff819fdd30 t copy_bigjoiner_crtc_state_nomodeset
-ffffffff819fde30 t intel_crtc_copy_uapi_to_hw_state_modeset
-ffffffff819fdf90 t intel_atomic_commit_ready
-ffffffff819fe020 t intel_atomic_commit_work
-ffffffff819fe030 t intel_atomic_commit_tail
-ffffffff819ff410 t intel_atomic_cleanup_work
+ffffffff819f1f00 T intel_atomic_add_affected_planes
+ffffffff819f1fd0 T intel_crtc_update_active_timings
+ffffffff819f20d0 T intel_calc_active_pipes
+ffffffff819f2150 T intel_crtc_arm_fifo_underrun
+ffffffff819f21f0 T intel_plane_destroy
+ffffffff819f2220 T intel_get_pipe_from_crtc_id_ioctl
+ffffffff819f2290 T intel_mode_valid_max_plane_size
+ffffffff819f2310 T intel_init_display_hooks
+ffffffff819f23f0 T intel_modeset_init_noirq
+ffffffff819f26a0 t intel_atomic_helper_free_state_worker
+ffffffff819f2710 T intel_modeset_init_nogem
+ffffffff819f3840 T intel_modeset_init
+ffffffff819f3a60 T i830_enable_pipe
+ffffffff819f4090 T i830_disable_pipe
+ffffffff819f43b0 T intel_display_resume
+ffffffff819f44f0 T intel_modeset_driver_remove
+ffffffff819f45a0 T intel_modeset_driver_remove_noirq
+ffffffff819f4710 T intel_modeset_driver_remove_nogem
+ffffffff819f4740 T intel_modeset_probe_defer
+ffffffff819f4770 T intel_display_driver_register
+ffffffff819f47d0 T intel_display_driver_unregister
+ffffffff819f4850 T intel_scanout_needs_vtd_wa
+ffffffff819f4890 t wait_for_pipe_scanline_moving
+ffffffff819f4af0 t hsw_get_pipe_config
+ffffffff819f58e0 t hsw_crtc_enable
+ffffffff819f6310 t hsw_crtc_disable
+ffffffff819f64c0 t skl_commit_modeset_enables
+ffffffff819f6a80 t intel_get_transcoder_timings
+ffffffff819f6d50 t ilk_get_pfit_config
+ffffffff819f6ed0 t enabled_bigjoiner_pipes
+ffffffff819f70e0 t bdw_set_pipemisc
+ffffffff819f7220 t ilk_pfit_enable
+ffffffff819f7330 t intel_set_transcoder_timings
+ffffffff819f76f0 t intel_update_crtc
+ffffffff819f7ce0 t intel_pre_plane_update
+ffffffff819f81f0 t intel_commit_modeset_enables
+ffffffff819f8300 t ilk_get_pipe_config
+ffffffff819f8640 t ilk_crtc_enable
+ffffffff819f8cf0 t ilk_crtc_disable
+ffffffff819f8f80 t i9xx_get_pipe_config
+ffffffff819f98b0 t valleyview_crtc_enable
+ffffffff819f9cc0 t i9xx_crtc_disable
+ffffffff819fa040 t i9xx_pfit_enable
+ffffffff819fa1a0 t i9xx_crtc_enable
+ffffffff819fa520 t intel_mode_valid
+ffffffff819fa6d0 t intel_atomic_check
+ffffffff819fd9d0 t intel_atomic_commit
+ffffffff819fdd40 t copy_bigjoiner_crtc_state_nomodeset
+ffffffff819fde40 t intel_crtc_copy_uapi_to_hw_state_modeset
+ffffffff819fdfa0 t intel_atomic_commit_ready
+ffffffff819fe030 t intel_atomic_commit_work
+ffffffff819fe040 t intel_atomic_commit_tail
+ffffffff819ff420 t intel_atomic_cleanup_work
 ffffffff81a00000 T intel_display_power_domain_str
 ffffffff81a00060 T __intel_display_power_is_enabled
 ffffffff81a00130 T intel_display_power_is_enabled
@@ -20726,27 +20727,28 @@ ffffffff81a21270 T intel_dp_mst_source_support
 ffffffff81a212a0 T intel_dp_mst_encoder_cleanup
 ffffffff81a212f0 T intel_dp_mst_is_master_trans
 ffffffff81a21330 T intel_dp_mst_is_slave_trans
-ffffffff81a21370 t intel_dp_add_mst_connector
-ffffffff81a21580 t intel_dp_mst_poll_hpd_irq
-ffffffff81a215a0 t intel_dp_mst_get_hw_state
-ffffffff81a21600 t intel_dp_mst_connector_late_register
-ffffffff81a21670 t intel_dp_mst_connector_early_unregister
-ffffffff81a216a0 t intel_dp_mst_get_modes
-ffffffff81a21740 t intel_dp_mst_detect
-ffffffff81a21830 t intel_dp_mst_mode_valid_ctx
-ffffffff81a21980 t intel_mst_atomic_best_encoder
-ffffffff81a219d0 t intel_dp_mst_atomic_check
-ffffffff81a21b50 t intel_dp_mst_compute_config
-ffffffff81a21e60 t intel_dp_mst_compute_config_late
-ffffffff81a21f50 t intel_mst_disable_dp
-ffffffff81a22000 t intel_mst_post_disable_dp
-ffffffff81a222c0 t intel_mst_pre_pll_enable_dp
-ffffffff81a22310 t intel_mst_pre_enable_dp
-ffffffff81a22530 t intel_mst_enable_dp
-ffffffff81a22920 t intel_dp_mst_enc_get_hw_state
-ffffffff81a22960 t intel_dp_mst_enc_get_config
-ffffffff81a22980 t intel_dp_mst_initial_fastset_check
-ffffffff81a229a0 t intel_dp_mst_encoder_destroy
+ffffffff81a21370 T intel_dp_mst_add_topology_state_for_crtc
+ffffffff81a21440 t intel_dp_add_mst_connector
+ffffffff81a21650 t intel_dp_mst_poll_hpd_irq
+ffffffff81a21670 t intel_dp_mst_get_hw_state
+ffffffff81a216d0 t intel_dp_mst_connector_late_register
+ffffffff81a21740 t intel_dp_mst_connector_early_unregister
+ffffffff81a21770 t intel_dp_mst_get_modes
+ffffffff81a21810 t intel_dp_mst_detect
+ffffffff81a21900 t intel_dp_mst_mode_valid_ctx
+ffffffff81a21a50 t intel_mst_atomic_best_encoder
+ffffffff81a21aa0 t intel_dp_mst_atomic_check
+ffffffff81a21c20 t intel_dp_mst_compute_config
+ffffffff81a21f30 t intel_dp_mst_compute_config_late
+ffffffff81a22020 t intel_mst_disable_dp
+ffffffff81a220d0 t intel_mst_post_disable_dp
+ffffffff81a22390 t intel_mst_pre_pll_enable_dp
+ffffffff81a223e0 t intel_mst_pre_enable_dp
+ffffffff81a22600 t intel_mst_enable_dp
+ffffffff81a229f0 t intel_dp_mst_enc_get_hw_state
+ffffffff81a22a30 t intel_dp_mst_enc_get_config
+ffffffff81a22a50 t intel_dp_mst_initial_fastset_check
+ffffffff81a22a70 t intel_dp_mst_encoder_destroy
 ffffffff81a23000 T bxt_port_to_phy_channel
 ffffffff81a23130 T bxt_ddi_phy_set_signal_levels
 ffffffff81a23650 T bxt_ddi_phy_is_enabled
@@ -22442,13 +22444,13 @@ ffffffff81b19fb0 t __delayed_work_tick
 ffffffff81b1a000 T intel_ring_update_space
 ffffffff81b1a040 T __intel_ring_pin
 ffffffff81b1a070 T intel_ring_pin
-ffffffff81b1a1c0 T intel_ring_reset
-ffffffff81b1a200 T intel_ring_unpin
-ffffffff81b1a280 T intel_engine_create_ring
-ffffffff81b1a400 T intel_ring_free
-ffffffff81b1a450 T intel_ring_begin
-ffffffff81b1a5d0 t wait_for_space
-ffffffff81b1a6d0 T intel_ring_cacheline_align
+ffffffff81b1a1d0 T intel_ring_reset
+ffffffff81b1a210 T intel_ring_unpin
+ffffffff81b1a2b0 T intel_engine_create_ring
+ffffffff81b1a440 T intel_ring_free
+ffffffff81b1a490 T intel_ring_begin
+ffffffff81b1a610 t wait_for_space
+ffffffff81b1a710 T intel_ring_cacheline_align
 ffffffff81b1b000 T intel_ring_submission_setup
 ffffffff81b1b700 t i915_gem_object_lock
 ffffffff81b1b910 t ring_release
@@ -23622,27 +23624,27 @@ ffffffff81bc8fb0 T atombios_dig_transmitter_setup2
 ffffffff81bc9910 T atombios_set_edp_panel_power
 ffffffff81bc9a30 T radeon_atom_release_dig_encoder
 ffffffff81bc9a70 T radeon_atom_pick_dig_encoder
-ffffffff81bc9c90 T radeon_atom_encoder_init
-ffffffff81bc9d60 t atombios_external_encoder_setup
-ffffffff81bc9fc0 T radeon_atom_ext_encoder_setup_ddc
-ffffffff81bca010 T radeon_enc_destroy
-ffffffff81bca0c0 T radeon_add_atom_encoder
-ffffffff81bca500 t radeon_atom_backlight_update_status
-ffffffff81bca560 t radeon_atom_encoder_dpms
-ffffffff81bca870 t radeon_atom_mode_fixup
-ffffffff81bca9b0 t radeon_atom_encoder_prepare
-ffffffff81bcae80 t radeon_atom_encoder_commit
-ffffffff81bcaeb0 t radeon_atom_encoder_mode_set
-ffffffff81bcb460 t radeon_atom_dig_detect
-ffffffff81bcb570 t radeon_atom_encoder_disable
-ffffffff81bcb820 t radeon_atom_encoder_dpms_avivo
-ffffffff81bcba50 t radeon_atom_encoder_dpms_dig
-ffffffff81bcbf50 t radeon_atom_dac_detect
-ffffffff81bcc140 t radeon_atom_ext_dpms
-ffffffff81bcc170 t radeon_atom_ext_prepare
-ffffffff81bcc1a0 t radeon_atom_ext_commit
-ffffffff81bcc1d0 t radeon_atom_ext_mode_set
-ffffffff81bcc200 t radeon_atom_ext_disable
+ffffffff81bc9cb0 T radeon_atom_encoder_init
+ffffffff81bc9d80 t atombios_external_encoder_setup
+ffffffff81bc9fe0 T radeon_atom_ext_encoder_setup_ddc
+ffffffff81bca030 T radeon_enc_destroy
+ffffffff81bca0e0 T radeon_add_atom_encoder
+ffffffff81bca520 t radeon_atom_backlight_update_status
+ffffffff81bca580 t radeon_atom_encoder_dpms
+ffffffff81bca890 t radeon_atom_mode_fixup
+ffffffff81bca9d0 t radeon_atom_encoder_prepare
+ffffffff81bcaea0 t radeon_atom_encoder_commit
+ffffffff81bcaed0 t radeon_atom_encoder_mode_set
+ffffffff81bcb480 t radeon_atom_dig_detect
+ffffffff81bcb590 t radeon_atom_encoder_disable
+ffffffff81bcb840 t radeon_atom_encoder_dpms_avivo
+ffffffff81bcba70 t radeon_atom_encoder_dpms_dig
+ffffffff81bcbf70 t radeon_atom_dac_detect
+ffffffff81bcc160 t radeon_atom_ext_dpms
+ffffffff81bcc190 t radeon_atom_ext_prepare
+ffffffff81bcc1c0 t radeon_atom_ext_commit
+ffffffff81bcc1f0 t radeon_atom_ext_mode_set
+ffffffff81bcc220 t radeon_atom_ext_disable
 ffffffff81bcd000 T radeon_atom_hw_i2c_xfer
 ffffffff81bcd160 t radeon_process_i2c_ch
 ffffffff81bcd330 T radeon_atom_hw_i2c_func
@@ -24569,13 +24571,13 @@ ffffffff81c74540 t cail_mc_write
 ffffffff81c74560 t cail_pll_read
 ffffffff81c74580 t cail_pll_write
 ffffffff81c745a0 T radeon_atombios_fini
-ffffffff81c74630 T radeon_combios_init
-ffffffff81c74670 T radeon_combios_fini
-ffffffff81c746a0 T radeon_device_init
-ffffffff81c75180 T radeon_device_fini
-ffffffff81c75280 T radeon_suspend_kms
-ffffffff81c755f0 T radeon_resume_kms
-ffffffff81c75840 T radeon_gpu_reset
+ffffffff81c74640 T radeon_combios_init
+ffffffff81c74680 T radeon_combios_fini
+ffffffff81c746b0 T radeon_device_init
+ffffffff81c75190 T radeon_device_fini
+ffffffff81c75290 T radeon_suspend_kms
+ffffffff81c75600 T radeon_resume_kms
+ffffffff81c75850 T radeon_gpu_reset
 ffffffff81c76000 T radeon_crtc_load_lut
 ffffffff81c76dc0 T radeon_crtc_handle_vblank
 ffffffff81c76f30 T radeon_get_crtc_scanoutpos
@@ -25730,36 +25732,36 @@ ffffffff81d28330 t amdgpu_device_xgmi_reset_func
 ffffffff81d28630 t amdgpu_device_ip_late_init
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 ffffffff81d28a90 T amdgpu_device_fini_hw
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-ffffffff81d29040 T amdgpu_device_fini_sw
-ffffffff81d29420 T amdgpu_device_suspend
-ffffffff81d295c0 T amdgpu_device_resume
-ffffffff81d298e0 T amdgpu_device_has_job_running
-ffffffff81d299b0 T amdgpu_device_should_recover_gpu
-ffffffff81d29ae0 T amdgpu_device_mode1_reset
-ffffffff81d29be0 T amdgpu_device_load_pci_state
-ffffffff81d29c30 T amdgpu_device_pre_asic_reset
-ffffffff81d2a020 T amdgpu_do_asic_reset
-ffffffff81d2a5f0 t amdgpu_device_ip_resume_phase1
-ffffffff81d2a6f0 t amdgpu_device_fw_loading
-ffffffff81d2a850 t amdgpu_device_ip_resume_phase2
-ffffffff81d2a970 t amdgpu_device_recover_vram
-ffffffff81d2ab50 T amdgpu_device_gpu_recover
-ffffffff81d2b690 t amdgpu_device_reset_sriov
-ffffffff81d2bb70 T amdgpu_device_is_peer_accessible
-ffffffff81d2bba0 T amdgpu_device_baco_enter
-ffffffff81d2bc50 T amdgpu_device_baco_exit
-ffffffff81d2bd20 T amdgpu_pci_error_detected
-ffffffff81d2bd70 T amdgpu_pci_mmio_enabled
-ffffffff81d2bdb0 T amdgpu_pci_slot_reset
-ffffffff81d2be00 T amdgpu_pci_resume
-ffffffff81d2be20 T amdgpu_in_reset
-ffffffff81d2be50 T amdgpu_device_halt
-ffffffff81d2be90 T amdgpu_device_pcie_port_rreg
-ffffffff81d2c0d0 T amdgpu_device_pcie_port_wreg
-ffffffff81d2c390 T amdgpu_device_switch_gang
-ffffffff81d2c420 T amdgpu_device_has_display_hardware
-ffffffff81d2c480 t __delayed_work_tick
+ffffffff81d28f80 t amdgpu_device_unmap_mmio
+ffffffff81d29080 T amdgpu_device_fini_sw
+ffffffff81d29460 T amdgpu_device_suspend
+ffffffff81d29600 T amdgpu_device_resume
+ffffffff81d29920 T amdgpu_device_has_job_running
+ffffffff81d299f0 T amdgpu_device_should_recover_gpu
+ffffffff81d29b20 T amdgpu_device_mode1_reset
+ffffffff81d29c20 T amdgpu_device_load_pci_state
+ffffffff81d29c70 T amdgpu_device_pre_asic_reset
+ffffffff81d2a060 T amdgpu_do_asic_reset
+ffffffff81d2a630 t amdgpu_device_ip_resume_phase1
+ffffffff81d2a730 t amdgpu_device_fw_loading
+ffffffff81d2a890 t amdgpu_device_ip_resume_phase2
+ffffffff81d2a9b0 t amdgpu_device_recover_vram
+ffffffff81d2ab90 T amdgpu_device_gpu_recover
+ffffffff81d2b6d0 t amdgpu_device_reset_sriov
+ffffffff81d2bbb0 T amdgpu_device_is_peer_accessible
+ffffffff81d2bbe0 T amdgpu_device_baco_enter
+ffffffff81d2bc90 T amdgpu_device_baco_exit
+ffffffff81d2bd60 T amdgpu_pci_error_detected
+ffffffff81d2bdb0 T amdgpu_pci_mmio_enabled
+ffffffff81d2bdf0 T amdgpu_pci_slot_reset
+ffffffff81d2be40 T amdgpu_pci_resume
+ffffffff81d2be60 T amdgpu_in_reset
+ffffffff81d2be90 T amdgpu_device_halt
+ffffffff81d2bed0 T amdgpu_device_pcie_port_rreg
+ffffffff81d2c110 T amdgpu_device_pcie_port_wreg
+ffffffff81d2c3d0 T amdgpu_device_switch_gang
+ffffffff81d2c460 T amdgpu_device_has_display_hardware
+ffffffff81d2c4c0 t __delayed_work_tick
 ffffffff81d2d000 T amdgpu_discovery_fini
 ffffffff81d2d050 T amdgpu_discovery_get_ip_version
 ffffffff81d2d170 T amdgpu_discovery_set_ip_blocks
@@ -27757,7 +27759,7 @@ ffffffff81e54840 t nbio_v7_2_update_medium_grain_light
 ffffffff81e549d0 t nbio_v7_2_get_clockgating_state
 ffffffff81e54a60 t nbio_v7_2_ih_control
 ffffffff81e54bb0 t nbio_v7_2_init_registers
-ffffffff81e54c90 t nbio_v7_2_remap_hdp_registers
+ffffffff81e54d70 t nbio_v7_2_remap_hdp_registers
 ffffffff81e55000 t nbio_v7_4_query_ras_error_count
 ffffffff81e551a0 t nbio_v7_4_handle_ras_controller_intr_no_bifring
 ffffffff81e553d0 t nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring
@@ -28846,19 +28848,19 @@ ffffffff81f03000 T dm_crtc_handle_vblank
 ffffffff81f03070 T modeset_required
 ffffffff81f030b0 T amdgpu_dm_vrr_active_irq
 ffffffff81f030f0 T dm_set_vupdate_irq
-ffffffff81f03190 T amdgpu_dm_vrr_active
-ffffffff81f031d0 T dm_enable_vblank
-ffffffff81f031e0 t dm_set_vblank
-ffffffff81f033d0 T dm_disable_vblank
-ffffffff81f033e0 T amdgpu_dm_crtc_init
-ffffffff81f035b0 t vblank_control_worker
-ffffffff81f036c0 t dm_crtc_reset_state
-ffffffff81f03760 t amdgpu_dm_crtc_destroy
-ffffffff81f03790 t dm_crtc_duplicate_state
-ffffffff81f03930 t dm_crtc_destroy_state
-ffffffff81f03970 t dm_crtc_helper_mode_fixup
-ffffffff81f039a0 t dm_crtc_helper_disable
-ffffffff81f039d0 t dm_crtc_helper_atomic_check
+ffffffff81f031a0 T amdgpu_dm_vrr_active
+ffffffff81f031e0 T dm_enable_vblank
+ffffffff81f031f0 t dm_set_vblank
+ffffffff81f033e0 T dm_disable_vblank
+ffffffff81f033f0 T amdgpu_dm_crtc_init
+ffffffff81f035c0 t vblank_control_worker
+ffffffff81f036d0 t dm_crtc_reset_state
+ffffffff81f03770 t amdgpu_dm_crtc_destroy
+ffffffff81f037a0 t dm_crtc_duplicate_state
+ffffffff81f03940 t dm_crtc_destroy_state
+ffffffff81f03980 t dm_crtc_helper_mode_fixup
+ffffffff81f039b0 t dm_crtc_helper_disable
+ffffffff81f039e0 t dm_crtc_helper_atomic_check
 ffffffff81f04000 T dm_helpers_parse_edid_caps
 ffffffff81f04190 T dm_helpers_dp_update_branch_info
 ffffffff81f041c0 T dm_helpers_dp_mst_write_payload_allocation_table
@@ -29363,20 +29365,20 @@ ffffffff81f46480 t dcn314_enable_pme_wa
 ffffffff81f46490 t dcn314_notify_wm_ranges
 ffffffff81f47000 T dcn314_smu_get_smu_version
 ffffffff81f47010 t dcn314_smu_send_msg_with_param
-ffffffff81f47210 T dcn314_smu_set_dispclk
-ffffffff81f47280 T dcn314_smu_set_dprefclk
-ffffffff81f472f0 T dcn314_smu_set_hard_min_dcfclk
-ffffffff81f47370 T dcn314_smu_set_min_deep_sleep_dcfclk
-ffffffff81f473f0 T dcn314_smu_set_dppclk
-ffffffff81f47460 T dcn314_smu_set_display_idle_optimization
-ffffffff81f474b0 T dcn314_smu_enable_phy_refclk_pwrdwn
-ffffffff81f474f0 T dcn314_smu_enable_pme_wa
-ffffffff81f47530 T dcn314_smu_set_dram_addr_high
-ffffffff81f47570 T dcn314_smu_set_dram_addr_low
-ffffffff81f475b0 T dcn314_smu_transfer_dpm_table_smu_2_dram
-ffffffff81f475f0 T dcn314_smu_transfer_wm_table_dram_2_smu
-ffffffff81f47630 T dcn314_smu_set_zstate_support
-ffffffff81f47680 T dcn314_smu_set_dtbclk
+ffffffff81f47230 T dcn314_smu_set_dispclk
+ffffffff81f472a0 T dcn314_smu_set_dprefclk
+ffffffff81f47310 T dcn314_smu_set_hard_min_dcfclk
+ffffffff81f47390 T dcn314_smu_set_min_deep_sleep_dcfclk
+ffffffff81f47410 T dcn314_smu_set_dppclk
+ffffffff81f47480 T dcn314_smu_set_display_idle_optimization
+ffffffff81f474d0 T dcn314_smu_enable_phy_refclk_pwrdwn
+ffffffff81f47510 T dcn314_smu_enable_pme_wa
+ffffffff81f47550 T dcn314_smu_set_dram_addr_high
+ffffffff81f47590 T dcn314_smu_set_dram_addr_low
+ffffffff81f475d0 T dcn314_smu_transfer_dpm_table_smu_2_dram
+ffffffff81f47610 T dcn314_smu_transfer_wm_table_dram_2_smu
+ffffffff81f47650 T dcn314_smu_set_zstate_support
+ffffffff81f476a0 T dcn314_smu_set_dtbclk
 ffffffff81f48000 T dcn315_clk_mgr_construct
 ffffffff81f489c0 T dcn315_clk_mgr_destroy
 ffffffff81f48a10 t dcn315_update_clocks
@@ -29474,46 +29476,46 @@ ffffffff81f56710 T dc_dmub_update_dirty_rect
 ffffffff81f569a0 T dc_update_planes_and_stream
 ffffffff81f570f0 t commit_minimal_transition_state
 ffffffff81f57480 t commit_planes_for_stream
-ffffffff81f58b30 T dc_commit_updates_for_stream
-ffffffff81f58f20 t copy_surface_update_to_plane
-ffffffff81f59320 t copy_stream_update_to_stream
-ffffffff81f59950 T dc_get_current_stream_count
-ffffffff81f59980 T dc_get_stream_at_index
-ffffffff81f599c0 T dc_interrupt_to_irq_source
-ffffffff81f599e0 T dc_interrupt_set
-ffffffff81f59a30 T dc_interrupt_ack
-ffffffff81f59a50 T dc_power_down_on_boot
-ffffffff81f59aa0 T dc_set_power_state
-ffffffff81f59c90 T dc_resume
-ffffffff81f59d00 T dc_is_dmcu_initialized
-ffffffff81f59d50 T dc_is_oem_i2c_device_present
-ffffffff81f59d90 T dc_submit_i2c
-ffffffff81f59dc0 T dc_submit_i2c_oem
-ffffffff81f59e10 T dc_link_add_remote_sink
-ffffffff81f59fa0 T dc_link_remove_remote_sink
-ffffffff81f5a090 T get_clock_requirements_for_state
-ffffffff81f5a110 T dc_set_clock
-ffffffff81f5a150 T dc_get_clock
-ffffffff81f5a190 T dc_set_psr_allow_active
-ffffffff81f5a290 T dc_allow_idle_optimizations
-ffffffff81f5a330 T dc_unlock_memory_clock_frequency
-ffffffff81f5a3a0 T dc_lock_memory_clock_frequency
-ffffffff81f5a430 T dc_enable_dcmode_clk_limit
-ffffffff81f5a530 t blank_and_force_memclk
-ffffffff81f5a710 T dc_is_plane_eligible_for_idle_optimizations
-ffffffff81f5a760 T dc_hardware_release
-ffffffff81f5a7b0 T dc_mclk_switch_using_fw_based_vblank_stretch_shut_down
-ffffffff81f5a7f0 T dc_is_dmub_outbox_supported
-ffffffff81f5a850 T dc_enable_dmub_notifications
-ffffffff81f5a8b0 T dc_enable_dmub_outbox
-ffffffff81f5a8f0 T dc_process_dmub_aux_transfer_async
-ffffffff81f5aa90 T get_link_index_from_dpia_port_index
-ffffffff81f5ab40 T dc_process_dmub_set_config_async
-ffffffff81f5ac20 T dc_process_dmub_set_mst_slots
-ffffffff81f5ad10 T dc_process_dmub_dpia_hpd_int_enable
-ffffffff81f5ade0 T dc_disable_accelerated_mode
-ffffffff81f5ae00 T dc_notify_vsync_int_state
-ffffffff81f5b030 T dc_extended_blank_supported
+ffffffff81f58b70 T dc_commit_updates_for_stream
+ffffffff81f58f60 t copy_surface_update_to_plane
+ffffffff81f59360 t copy_stream_update_to_stream
+ffffffff81f59990 T dc_get_current_stream_count
+ffffffff81f599c0 T dc_get_stream_at_index
+ffffffff81f59a00 T dc_interrupt_to_irq_source
+ffffffff81f59a20 T dc_interrupt_set
+ffffffff81f59a70 T dc_interrupt_ack
+ffffffff81f59a90 T dc_power_down_on_boot
+ffffffff81f59ae0 T dc_set_power_state
+ffffffff81f59cd0 T dc_resume
+ffffffff81f59d40 T dc_is_dmcu_initialized
+ffffffff81f59d90 T dc_is_oem_i2c_device_present
+ffffffff81f59dd0 T dc_submit_i2c
+ffffffff81f59e00 T dc_submit_i2c_oem
+ffffffff81f59e50 T dc_link_add_remote_sink
+ffffffff81f59fe0 T dc_link_remove_remote_sink
+ffffffff81f5a0d0 T get_clock_requirements_for_state
+ffffffff81f5a150 T dc_set_clock
+ffffffff81f5a190 T dc_get_clock
+ffffffff81f5a1d0 T dc_set_psr_allow_active
+ffffffff81f5a2d0 T dc_allow_idle_optimizations
+ffffffff81f5a370 T dc_unlock_memory_clock_frequency
+ffffffff81f5a3e0 T dc_lock_memory_clock_frequency
+ffffffff81f5a470 T dc_enable_dcmode_clk_limit
+ffffffff81f5a570 t blank_and_force_memclk
+ffffffff81f5a750 T dc_is_plane_eligible_for_idle_optimizations
+ffffffff81f5a7a0 T dc_hardware_release
+ffffffff81f5a7f0 T dc_mclk_switch_using_fw_based_vblank_stretch_shut_down
+ffffffff81f5a830 T dc_is_dmub_outbox_supported
+ffffffff81f5a890 T dc_enable_dmub_notifications
+ffffffff81f5a8f0 T dc_enable_dmub_outbox
+ffffffff81f5a930 T dc_process_dmub_aux_transfer_async
+ffffffff81f5aad0 T get_link_index_from_dpia_port_index
+ffffffff81f5ab80 T dc_process_dmub_set_config_async
+ffffffff81f5ac60 T dc_process_dmub_set_mst_slots
+ffffffff81f5ad50 T dc_process_dmub_dpia_hpd_int_enable
+ffffffff81f5ae20 T dc_disable_accelerated_mode
+ffffffff81f5ae40 T dc_notify_vsync_int_state
+ffffffff81f5b070 T dc_extended_blank_supported
 ffffffff81f5c000 T pre_surface_trace
 ffffffff81f5c030 T update_surface_trace
 ffffffff81f5c060 T post_surface_trace
@@ -29681,32 +29683,32 @@ ffffffff81f75170 t set_crtc_test_pattern
 ffffffff81f75600 T dp_enable_mst_on_sink
 ffffffff81f75680 T dp_set_fec_enable
 ffffffff81f75790 T dpcd_set_source_specific_data
-ffffffff81f75900 T dpcd_write_cable_id_to_dprx
-ffffffff81f75970 T dc_link_set_backlight_level_nits
-ffffffff81f75a10 T dc_link_get_backlight_level_nits
-ffffffff81f75aa0 T dc_link_backlight_enable_aux
-ffffffff81f75b00 T dc_link_read_default_bl_aux
-ffffffff81f75b60 T is_edp_ilr_optimization_required
-ffffffff81f75dd0 T dc_link_dp_mst_decide_link_encoding_format
-ffffffff81f75e50 T dpcd_write_128b_132b_sst_payload_allocation_table
-ffffffff81f76130 T calculate_sst_avg_time_slots_per_mtp
-ffffffff81f76190 T dpcd_poll_for_allocation_change_trigger
-ffffffff81f76540 T is_dp_128b_132b_signal
-ffffffff81f76600 T edp_panel_backlight_power_on
-ffffffff81f766b0 T dc_link_clear_dprx_states
-ffffffff81f766e0 T dp_receiver_power_ctrl
-ffffffff81f76730 T dp_source_sequence_trace
-ffffffff81f76790 T edp_add_delay_for_T9
-ffffffff81f767e0 T edp_receiver_ready_T9
-ffffffff81f768b0 T edp_receiver_ready_T7
-ffffffff81f76a50 T dp_disable_link_phy_mst
-ffffffff81f76b50 T dp_retrain_link_dp_test
-ffffffff81f76d60 T dp_set_dsc_on_rx
-ffffffff81f76dc0 T dp_set_dsc_on_stream
-ffffffff81f77390 T dp_set_dsc_enable
-ffffffff81f77440 T dp_set_dsc_pps_sdp
-ffffffff81f778e0 T dp_update_dsc_config
-ffffffff81f77950 t dpcd_set_lt_pattern_and_lane_settings
+ffffffff81f758d0 T dpcd_write_cable_id_to_dprx
+ffffffff81f75940 T dc_link_set_backlight_level_nits
+ffffffff81f759e0 T dc_link_get_backlight_level_nits
+ffffffff81f75a70 T dc_link_backlight_enable_aux
+ffffffff81f75ad0 T dc_link_read_default_bl_aux
+ffffffff81f75b30 T is_edp_ilr_optimization_required
+ffffffff81f75da0 T dc_link_dp_mst_decide_link_encoding_format
+ffffffff81f75e20 T dpcd_write_128b_132b_sst_payload_allocation_table
+ffffffff81f76100 T calculate_sst_avg_time_slots_per_mtp
+ffffffff81f76160 T dpcd_poll_for_allocation_change_trigger
+ffffffff81f76510 T is_dp_128b_132b_signal
+ffffffff81f765d0 T edp_panel_backlight_power_on
+ffffffff81f76680 T dc_link_clear_dprx_states
+ffffffff81f766b0 T dp_receiver_power_ctrl
+ffffffff81f76700 T dp_source_sequence_trace
+ffffffff81f76760 T edp_add_delay_for_T9
+ffffffff81f767b0 T edp_receiver_ready_T9
+ffffffff81f76880 T edp_receiver_ready_T7
+ffffffff81f76a20 T dp_disable_link_phy_mst
+ffffffff81f76b20 T dp_retrain_link_dp_test
+ffffffff81f76d30 T dp_set_dsc_on_rx
+ffffffff81f76d90 T dp_set_dsc_on_stream
+ffffffff81f77360 T dp_set_dsc_enable
+ffffffff81f77410 T dp_set_dsc_pps_sdp
+ffffffff81f778b0 T dp_update_dsc_config
+ffffffff81f77920 t dpcd_set_lt_pattern_and_lane_settings
 ffffffff81f78000 T core_link_read_dpcd
 ffffffff81f781a0 T core_link_write_dpcd
 ffffffff81f79000 T dpcd_get_tunneling_device_data
@@ -31160,10 +31162,11 @@ ffffffff82067700 T optc3_set_drr_trigger_window
 ffffffff82067790 T optc3_set_vtotal_change_limit
 ffffffff82067800 T optc3_set_dsc_config
 ffffffff82067850 T optc3_set_odm_bypass
-ffffffff820679c0 T optc3_set_vtotal_min_max
-ffffffff820679d0 T optc3_tg_init
-ffffffff82067a20 T dcn30_timing_generator_init
-ffffffff82067a90 t optc3_set_odm_combine
+ffffffff820679c0 T optc3_wait_drr_doublebuffer_pending_clear
+ffffffff82067a30 T optc3_set_vtotal_min_max
+ffffffff82067a40 T optc3_tg_init
+ffffffff82067a90 T dcn30_timing_generator_init
+ffffffff82067b00 t optc3_set_odm_combine
 ffffffff82068000 T dcn30_add_stream_to_ctx
 ffffffff82068010 T dcn30_populate_dml_pipes_from_context
 ffffffff82068100 T dcn30_populate_dml_writeback_from_context
@@ -31370,14 +31373,14 @@ ffffffff82096000 T dcn314_dio_stream_encoder_construct
 ffffffff82096070 t enc314_stream_encoder_hdmi_set_stream_attribute
 ffffffff82096660 t enc314_stream_encoder_dvi_set_stream_attribute
 ffffffff82096860 t enc314_stream_encoder_dp_blank
-ffffffff820968c0 t enc314_stream_encoder_dp_unblank
-ffffffff82096c00 t enc314_read_state
-ffffffff82096d60 t enc314_dp_set_dsc_config
-ffffffff82096db0 t enc314_dp_set_odm_combine
-ffffffff82096df0 t enc314_set_dig_input_mode
-ffffffff82096e40 t enc314_enable_fifo
-ffffffff82096ee0 t enc314_disable_fifo
-ffffffff82096f20 t enc314_reset_fifo
+ffffffff820968b0 t enc314_stream_encoder_dp_unblank
+ffffffff82096bf0 t enc314_read_state
+ffffffff82096d50 t enc314_dp_set_dsc_config
+ffffffff82096da0 t enc314_dp_set_odm_combine
+ffffffff82096de0 t enc314_set_dig_input_mode
+ffffffff82096e30 t enc314_enable_fifo
+ffffffff82096ed0 t enc314_disable_fifo
+ffffffff82096f10 t enc314_reset_fifo
 ffffffff82098000 T dcn314_update_odm
 ffffffff82098610 T dcn314_dsc_pg_control
 ffffffff820989d0 T dcn314_enable_power_gating_plane
@@ -31777,10 +31780,10 @@ ffffffff8219b620 T insert_entry_into_table_sorted
 ffffffff8219ba50 T dcn32_set_phantom_stream_timing
 ffffffff8219bcf0 t dcn32_split_stream_for_mpc_or_odm
 ffffffff8219c080 T dcn32_calculate_wm_and_dlg_fpu
-ffffffff8219d570 T dcn32_patch_dpm_table
-ffffffff8219d780 T dcn32_update_bw_bounding_box_fpu
-ffffffff8219f150 T dcn32_zero_pipe_dcc_fraction
-ffffffff8219f1b0 t subvp_drr_schedulable
+ffffffff8219d590 T dcn32_patch_dpm_table
+ffffffff8219d7a0 T dcn32_update_bw_bounding_box_fpu
+ffffffff8219f170 T dcn32_zero_pipe_dcc_fraction
+ffffffff8219f1d0 t subvp_drr_schedulable
 ffffffff821a0000 T dml32_recalculate
 ffffffff821a4320 T dml32_ModeSupportAndSystemConfigurationFull
 ffffffff821ac000 T dml32_dscceComputeDelay
@@ -38986,18 +38989,18 @@ ffffffff8251f000 r isomappings
 ffffffff8251f080 r unimappings
 ffffffff8251f230 r replacements
 ffffffff82522aff r cmd0646_9_tim_udma
-ffffffff8257611d r pp_r600_decoded_lanes
-ffffffff82591355 r cmd680_setup_channel.udma_tbl
-ffffffff82598f54 r apollo_udma33_tim
-ffffffff8259eff7 r substchar
-ffffffff825a109d r apollo_udma100_tim
-ffffffff825c88b2 r apollo_udma66_tim
-ffffffff825cfd0a r apollo_pio_rec
-ffffffff825defc0 r cy_pio_rec
-ffffffff8260e2a7 r apollo_udma133_tim
-ffffffff8261ad78 R drm_ca
-ffffffff8261ada0 R drm_filtops
-ffffffff8261add0 R drmread_filtops
+ffffffff8257615c r pp_r600_decoded_lanes
+ffffffff82591394 r cmd680_setup_channel.udma_tbl
+ffffffff82598f93 r apollo_udma33_tim
+ffffffff8259f036 r substchar
+ffffffff825a10dc r apollo_udma100_tim
+ffffffff825c88ab r apollo_udma66_tim
+ffffffff825cfd03 r apollo_pio_rec
+ffffffff825defb9 r cy_pio_rec
+ffffffff8260e2ca r apollo_udma133_tim
+ffffffff8261ada0 R drm_ca
+ffffffff8261adc8 R drm_filtops
+ffffffff8261adf8 R drmread_filtops
 ffffffff8261b000 r vga_emulops
 ffffffff8261b048 R vga_stdscreen
 ffffffff8261b078 R vga_stdscreen_mono
@@ -40991,27 +40994,28 @@ ffffffff82926000 r drm_mode_status_names
 ffffffff82927000 r primary_plane_funcs
 ffffffff82927068 r safe_modeset_formats
 ffffffff82928000 r orientation_data
-ffffffff8292b060 r lcd800x1280_rightside_up
-ffffffff8292b078 r lcd720x1280_rightside_up
-ffffffff8292b090 r asus_t100ha
-ffffffff8292b0a8 r lcd1080x1920_leftside_up
-ffffffff8292b0c0 r lcd1200x1920_rightside_up
-ffffffff8292b0d8 r gpd_micropc
-ffffffff8292b0f0 r gpd_pocket
-ffffffff8292b108 r gpd_pocket2
-ffffffff8292b120 r gpd_win
-ffffffff8292b138 r gpd_win2
-ffffffff8292b150 r itworks_tw891
-ffffffff8292b168 r onegx1_pro
-ffffffff8292b180 r lcd1600x2560_leftside_up
-ffffffff8292b198 r lcd1280x1920_rightside_up
-ffffffff8292b1b0 r .compoundliteral
-ffffffff8292b1c0 r .compoundliteral.5
-ffffffff8292b1e8 r .compoundliteral.9
-ffffffff8292b208 r .compoundliteral.17
-ffffffff8292b248 r .compoundliteral.21
-ffffffff8292b268 r .compoundliteral.23
-ffffffff8292b278 r .compoundliteral.25
+ffffffff8292b468 r lcd800x1280_rightside_up
+ffffffff8292b480 r lcd720x1280_rightside_up
+ffffffff8292b498 r lcd800x1280_leftside_up
+ffffffff8292b4b0 r lcd1080x1920_leftside_up
+ffffffff8292b4c8 r lcd1200x1920_rightside_up
+ffffffff8292b4e0 r gpd_micropc
+ffffffff8292b4f8 r gpd_pocket
+ffffffff8292b510 r gpd_pocket2
+ffffffff8292b528 r gpd_win
+ffffffff8292b540 r gpd_win2
+ffffffff8292b558 r itworks_tw891
+ffffffff8292b570 r lcd1600x2560_rightside_up
+ffffffff8292b588 r onegx1_pro
+ffffffff8292b5a0 r lcd1600x2560_leftside_up
+ffffffff8292b5b8 r lcd1280x1920_rightside_up
+ffffffff8292b5d0 r .compoundliteral
+ffffffff8292b5e0 r .compoundliteral.5
+ffffffff8292b608 r .compoundliteral.9
+ffffffff8292b628 r .compoundliteral.17
+ffffffff8292b668 r .compoundliteral.21
+ffffffff8292b688 r .compoundliteral.23
+ffffffff8292b698 r .compoundliteral.25
 ffffffff8292c000 r drm_gem_prime_dmabuf_ops
 ffffffff8292e000 r is_hdmi_adaptor.dp_dual_mode_hdmi_id
 ffffffff8292f000 r drm_dp_phy_name.phy_names
@@ -41786,8 +41790,8 @@ ffffffff829748b0 r rc_range_maxqp444_8bpc
 ffffffff82974ae0 r rc_range_maxqp444_10bpc
 ffffffff82974dc0 r rc_range_maxqp444_12bpc
 ffffffff82976000 r intel_quirks
-ffffffff82976228 r .compoundliteral
-ffffffff82976630 r .compoundliteral.4
+ffffffff82976240 r .compoundliteral
+ffffffff82976648 r .compoundliteral.4
 ffffffff82977000 r intel_sdvo_enc_funcs
 ffffffff82977020 r intel_sdvo_ddc_proxy
 ffffffff82977030 r proxy_lock_ops
@@ -44028,21 +44032,21 @@ ffffffff82b5cbdc r i2c_masks
 ffffffff82b5cc80 r tg_regs
 ffffffff82b5cf00 r tg_shift
 ffffffff82b5cfc0 r tg_mask
-ffffffff82b5d2bc r mpc_regs
-ffffffff82b5d804 r mpc_shift
-ffffffff82b5d850 r mpc_mask
-ffffffff82b5d978 r hubbub_reg
-ffffffff82b5daec r hubbub_shift
-ffffffff82b5db74 r hubbub_mask
-ffffffff82b5dd90 r audio_regs
-ffffffff82b5dde8 r audio_shift
-ffffffff82b5de00 r audio_mask
-ffffffff82b5de40 r stream_enc_regs
-ffffffff82b5e0e8 r se_shift
-ffffffff82b5e1c4 r se_mask
-ffffffff82b5e530 r hwseq_reg
-ffffffff82b5e74c r hwseq_shift
-ffffffff82b5e7cc r hwseq_mask
+ffffffff82b5d2c0 r mpc_regs
+ffffffff82b5d808 r mpc_shift
+ffffffff82b5d854 r mpc_mask
+ffffffff82b5d97c r hubbub_reg
+ffffffff82b5daf0 r hubbub_shift
+ffffffff82b5db78 r hubbub_mask
+ffffffff82b5dda0 r audio_regs
+ffffffff82b5ddf8 r audio_shift
+ffffffff82b5de10 r audio_mask
+ffffffff82b5de50 r stream_enc_regs
+ffffffff82b5e0f8 r se_shift
+ffffffff82b5e1d4 r se_mask
+ffffffff82b5e540 r hwseq_reg
+ffffffff82b5e75c r hwseq_shift
+ffffffff82b5e7dc r hwseq_mask
 ffffffff82b5f000 r dccg21_funcs
 ffffffff82b60000 r hubbub21_funcs
 ffffffff82b61000 r dcn21_funcs
@@ -44175,39 +44179,39 @@ ffffffff82b7b108 r opp_mask
 ffffffff82b7b1e0 r optc_regs
 ffffffff82b7b960 r optc_shift
 ffffffff82b7ba20 r optc_mask
-ffffffff82b7bd1c r mpc_regs
-ffffffff82b7d508 r mpc_shift
-ffffffff82b7d5e4 r mpc_mask
-ffffffff82b7d950 r dsc_regs
-ffffffff82b7dde8 r dsc_shift
-ffffffff82b7dea0 r dsc_mask
-ffffffff82b7e180 r dwbc30_regs
-ffffffff82b7e35c r dwbc30_shift
-ffffffff82b7e490 r dwbc30_mask
-ffffffff82b7e960 r mcif_wb30_regs
-ffffffff82b7ea5c r mcif_wb30_shift
-ffffffff82b7eb08 r mcif_wb30_mask
-ffffffff82b7edc0 r aux_engine_regs
-ffffffff82b7eeb0 r aux_mask
-ffffffff82b7ef10 r aux_shift
-ffffffff82b7ef30 r i2c_hw_regs
-ffffffff82b7f080 r i2c_shifts
-ffffffff82b7f0ac r i2c_masks
-ffffffff82b7f150 r audio_regs
-ffffffff82b7f284 r audio_shift
-ffffffff82b7f29c r audio_mask
-ffffffff82b7f2e0 r stream_enc_regs
-ffffffff82b7fad8 r se_shift
-ffffffff82b7fbb4 r se_mask
-ffffffff82b7ff20 r vpg_regs
-ffffffff82b7ffac r vpg_shift
-ffffffff82b7ffd4 r vpg_mask
-ffffffff82b80070 r afmt_regs
-ffffffff82b8016c r afmt_shift
-ffffffff82b80180 r afmt_mask
-ffffffff82b801c4 r hwseq_reg
-ffffffff82b803e0 r hwseq_shift
-ffffffff82b80460 r hwseq_mask
+ffffffff82b7bd20 r mpc_regs
+ffffffff82b7d50c r mpc_shift
+ffffffff82b7d5e8 r mpc_mask
+ffffffff82b7d960 r dsc_regs
+ffffffff82b7ddf8 r dsc_shift
+ffffffff82b7deb0 r dsc_mask
+ffffffff82b7e190 r dwbc30_regs
+ffffffff82b7e36c r dwbc30_shift
+ffffffff82b7e4a0 r dwbc30_mask
+ffffffff82b7e970 r mcif_wb30_regs
+ffffffff82b7ea6c r mcif_wb30_shift
+ffffffff82b7eb18 r mcif_wb30_mask
+ffffffff82b7edd0 r aux_engine_regs
+ffffffff82b7eec0 r aux_mask
+ffffffff82b7ef20 r aux_shift
+ffffffff82b7ef40 r i2c_hw_regs
+ffffffff82b7f090 r i2c_shifts
+ffffffff82b7f0bc r i2c_masks
+ffffffff82b7f160 r audio_regs
+ffffffff82b7f294 r audio_shift
+ffffffff82b7f2ac r audio_mask
+ffffffff82b7f2f0 r stream_enc_regs
+ffffffff82b7fae8 r se_shift
+ffffffff82b7fbc4 r se_mask
+ffffffff82b7ff30 r vpg_regs
+ffffffff82b7ffbc r vpg_shift
+ffffffff82b7ffe4 r vpg_mask
+ffffffff82b80080 r afmt_regs
+ffffffff82b8017c r afmt_shift
+ffffffff82b80190 r afmt_mask
+ffffffff82b801d4 r hwseq_reg
+ffffffff82b803f0 r hwseq_shift
+ffffffff82b80470 r hwseq_mask
 ffffffff82b81000 r dccg301_funcs
 ffffffff82b82000 r dcn301_link_enc_funcs
 ffffffff82b83000 r hubbub301_funcs
@@ -44256,39 +44260,39 @@ ffffffff82b8acd8 r opp_mask
 ffffffff82b8adb0 r optc_regs
 ffffffff82b8b2b0 r optc_shift
 ffffffff82b8b370 r optc_mask
-ffffffff82b8b66c r mpc_regs
-ffffffff82b8ce58 r mpc_shift
-ffffffff82b8cf34 r mpc_mask
-ffffffff82b8d2a0 r dsc_regs
-ffffffff82b8d4ec r dsc_shift
-ffffffff82b8d5a4 r dsc_mask
-ffffffff82b8d880 r dwbc30_regs
-ffffffff82b8da5c r dwbc30_shift
-ffffffff82b8db90 r dwbc30_mask
-ffffffff82b8e060 r mcif_wb30_regs
-ffffffff82b8e15c r mcif_wb30_shift
-ffffffff82b8e208 r mcif_wb30_mask
-ffffffff82b8e4c0 r aux_engine_regs
-ffffffff82b8e560 r aux_mask
-ffffffff82b8e5c0 r aux_shift
-ffffffff82b8e5e0 r i2c_hw_regs
-ffffffff82b8e6c0 r i2c_shifts
-ffffffff82b8e6ec r i2c_masks
-ffffffff82b8e790 r audio_regs
-ffffffff82b8e8c4 r audio_shift
-ffffffff82b8e8dc r audio_mask
-ffffffff82b8e920 r stream_enc_regs
-ffffffff82b8ee70 r se_shift
-ffffffff82b8ef4c r se_mask
-ffffffff82b8f2c0 r vpg_regs
-ffffffff82b8f310 r vpg_shift
-ffffffff82b8f338 r vpg_mask
-ffffffff82b8f3d0 r afmt_regs
-ffffffff82b8f460 r afmt_shift
-ffffffff82b8f474 r afmt_mask
-ffffffff82b8f4b8 r hwseq_reg
-ffffffff82b8f6d4 r hwseq_shift
-ffffffff82b8f754 r hwseq_mask
+ffffffff82b8b670 r mpc_regs
+ffffffff82b8ce5c r mpc_shift
+ffffffff82b8cf38 r mpc_mask
+ffffffff82b8d2b0 r dsc_regs
+ffffffff82b8d4fc r dsc_shift
+ffffffff82b8d5b4 r dsc_mask
+ffffffff82b8d890 r dwbc30_regs
+ffffffff82b8da6c r dwbc30_shift
+ffffffff82b8dba0 r dwbc30_mask
+ffffffff82b8e070 r mcif_wb30_regs
+ffffffff82b8e16c r mcif_wb30_shift
+ffffffff82b8e218 r mcif_wb30_mask
+ffffffff82b8e4d0 r aux_engine_regs
+ffffffff82b8e570 r aux_mask
+ffffffff82b8e5d0 r aux_shift
+ffffffff82b8e5f0 r i2c_hw_regs
+ffffffff82b8e6d0 r i2c_shifts
+ffffffff82b8e6fc r i2c_masks
+ffffffff82b8e7a0 r audio_regs
+ffffffff82b8e8d4 r audio_shift
+ffffffff82b8e8ec r audio_mask
+ffffffff82b8e930 r stream_enc_regs
+ffffffff82b8ee80 r se_shift
+ffffffff82b8ef5c r se_mask
+ffffffff82b8f2d0 r vpg_regs
+ffffffff82b8f320 r vpg_shift
+ffffffff82b8f348 r vpg_mask
+ffffffff82b8f3e0 r afmt_regs
+ffffffff82b8f470 r afmt_shift
+ffffffff82b8f484 r afmt_mask
+ffffffff82b8f4c8 r hwseq_reg
+ffffffff82b8f6e4 r hwseq_shift
+ffffffff82b8f764 r hwseq_mask
 ffffffff82b90000 r bios_regs
 ffffffff82b90008 r res_cap_dcn302
 ffffffff82b90048 r debug_defaults_drv
@@ -44332,39 +44336,39 @@ ffffffff82b956a0 r opp_mask
 ffffffff82b95780 r optc_regs
 ffffffff82b95dc0 r optc_shift
 ffffffff82b95e80 r optc_mask
-ffffffff82b9617c r mpc_regs
-ffffffff82b97968 r mpc_shift
-ffffffff82b97a44 r mpc_mask
-ffffffff82b97db0 r dsc_regs
-ffffffff82b98184 r dsc_shift
-ffffffff82b9823c r dsc_mask
-ffffffff82b98520 r dwbc30_regs
-ffffffff82b986fc r dwbc30_shift
-ffffffff82b98830 r dwbc30_mask
-ffffffff82b98d00 r mcif_wb30_regs
-ffffffff82b98dfc r mcif_wb30_shift
-ffffffff82b98ea8 r mcif_wb30_mask
-ffffffff82b99160 r aux_engine_regs
-ffffffff82b99228 r aux_mask
-ffffffff82b99288 r aux_shift
-ffffffff82b992a0 r i2c_hw_regs
-ffffffff82b993b8 r i2c_shifts
-ffffffff82b993e4 r i2c_masks
-ffffffff82b99490 r audio_regs
-ffffffff82b995c4 r audio_shift
-ffffffff82b995dc r audio_mask
-ffffffff82b99620 r stream_enc_regs
-ffffffff82b99cc4 r se_shift
-ffffffff82b99da0 r se_mask
-ffffffff82b9a110 r vpg_regs
-ffffffff82b9a188 r vpg_shift
-ffffffff82b9a1b0 r vpg_mask
-ffffffff82b9a250 r afmt_regs
-ffffffff82b9a328 r afmt_shift
-ffffffff82b9a33c r afmt_mask
-ffffffff82b9a380 r hwseq_reg
-ffffffff82b9a59c r hwseq_shift
-ffffffff82b9a61c r hwseq_mask
+ffffffff82b96180 r mpc_regs
+ffffffff82b9796c r mpc_shift
+ffffffff82b97a48 r mpc_mask
+ffffffff82b97dc0 r dsc_regs
+ffffffff82b98194 r dsc_shift
+ffffffff82b9824c r dsc_mask
+ffffffff82b98530 r dwbc30_regs
+ffffffff82b9870c r dwbc30_shift
+ffffffff82b98840 r dwbc30_mask
+ffffffff82b98d10 r mcif_wb30_regs
+ffffffff82b98e0c r mcif_wb30_shift
+ffffffff82b98eb8 r mcif_wb30_mask
+ffffffff82b99170 r aux_engine_regs
+ffffffff82b99238 r aux_mask
+ffffffff82b99298 r aux_shift
+ffffffff82b992b0 r i2c_hw_regs
+ffffffff82b993c8 r i2c_shifts
+ffffffff82b993f4 r i2c_masks
+ffffffff82b994a0 r audio_regs
+ffffffff82b995d4 r audio_shift
+ffffffff82b995ec r audio_mask
+ffffffff82b99630 r stream_enc_regs
+ffffffff82b99cd4 r se_shift
+ffffffff82b99db0 r se_mask
+ffffffff82b9a120 r vpg_regs
+ffffffff82b9a198 r vpg_shift
+ffffffff82b9a1c0 r vpg_mask
+ffffffff82b9a260 r afmt_regs
+ffffffff82b9a338 r afmt_shift
+ffffffff82b9a34c r afmt_mask
+ffffffff82b9a390 r hwseq_reg
+ffffffff82b9a5ac r hwseq_shift
+ffffffff82b9a62c r hwseq_mask
 ffffffff82b9b000 r bios_regs
 ffffffff82b9b008 r res_cap_dcn303
 ffffffff82b9b048 r debug_defaults_drv
@@ -44408,39 +44412,39 @@ ffffffff82b9e9e8 r opp_mask
 ffffffff82b9eac0 r optc_regs
 ffffffff82b9ed40 r optc_shift
 ffffffff82b9ee00 r optc_mask
-ffffffff82b9f0fc r mpc_regs
-ffffffff82ba08e8 r mpc_shift
-ffffffff82ba09c4 r mpc_mask
-ffffffff82ba0d30 r dsc_regs
-ffffffff82ba0eb8 r dsc_shift
-ffffffff82ba0f70 r dsc_mask
-ffffffff82ba1250 r dwbc30_regs
-ffffffff82ba142c r dwbc30_shift
-ffffffff82ba1560 r dwbc30_mask
-ffffffff82ba1a30 r mcif_wb30_regs
-ffffffff82ba1b2c r mcif_wb30_shift
-ffffffff82ba1bd8 r mcif_wb30_mask
-ffffffff82ba1e90 r aux_engine_regs
-ffffffff82ba1ee0 r aux_mask
-ffffffff82ba1f40 r aux_shift
-ffffffff82ba1f60 r i2c_hw_regs
-ffffffff82ba1fd0 r i2c_shifts
-ffffffff82ba1ffc r i2c_masks
-ffffffff82ba20a0 r audio_regs
-ffffffff82ba21d4 r audio_shift
-ffffffff82ba21ec r audio_mask
-ffffffff82ba2230 r stream_enc_regs
-ffffffff82ba24d8 r se_shift
-ffffffff82ba25b4 r se_mask
-ffffffff82ba2920 r vpg_regs
-ffffffff82ba295c r vpg_shift
-ffffffff82ba2984 r vpg_mask
-ffffffff82ba2a20 r afmt_regs
-ffffffff82ba2a8c r afmt_shift
-ffffffff82ba2aa0 r afmt_mask
-ffffffff82ba2ae4 r hwseq_reg
-ffffffff82ba2d00 r hwseq_shift
-ffffffff82ba2d80 r hwseq_mask
+ffffffff82b9f100 r mpc_regs
+ffffffff82ba08ec r mpc_shift
+ffffffff82ba09c8 r mpc_mask
+ffffffff82ba0d40 r dsc_regs
+ffffffff82ba0ec8 r dsc_shift
+ffffffff82ba0f80 r dsc_mask
+ffffffff82ba1260 r dwbc30_regs
+ffffffff82ba143c r dwbc30_shift
+ffffffff82ba1570 r dwbc30_mask
+ffffffff82ba1a40 r mcif_wb30_regs
+ffffffff82ba1b3c r mcif_wb30_shift
+ffffffff82ba1be8 r mcif_wb30_mask
+ffffffff82ba1ea0 r aux_engine_regs
+ffffffff82ba1ef0 r aux_mask
+ffffffff82ba1f50 r aux_shift
+ffffffff82ba1f70 r i2c_hw_regs
+ffffffff82ba1fe0 r i2c_shifts
+ffffffff82ba200c r i2c_masks
+ffffffff82ba20b0 r audio_regs
+ffffffff82ba21e4 r audio_shift
+ffffffff82ba21fc r audio_mask
+ffffffff82ba2240 r stream_enc_regs
+ffffffff82ba24e8 r se_shift
+ffffffff82ba25c4 r se_mask
+ffffffff82ba2930 r vpg_regs
+ffffffff82ba296c r vpg_shift
+ffffffff82ba2994 r vpg_mask
+ffffffff82ba2a30 r afmt_regs
+ffffffff82ba2a9c r afmt_shift
+ffffffff82ba2ab0 r afmt_mask
+ffffffff82ba2af4 r hwseq_reg
+ffffffff82ba2d10 r hwseq_shift
+ffffffff82ba2d90 r hwseq_mask
 ffffffff82ba3000 r dccg31_funcs
 ffffffff82ba4000 r dcn31_link_enc_funcs
 ffffffff82ba5000 r dcn30_str_enc_funcs
@@ -44490,48 +44494,48 @@ ffffffff82bae028 r opp_mask
 ffffffff82bae100 r optc_regs
 ffffffff82bae600 r optc_shift
 ffffffff82bae6c0 r optc_mask
-ffffffff82bae9bc r mpc_regs
-ffffffff82bb01a8 r mpc_shift
-ffffffff82bb0284 r mpc_mask
-ffffffff82bb05f0 r dsc_regs
-ffffffff82bb083c r dsc_shift
-ffffffff82bb08f4 r dsc_mask
-ffffffff82bb0bd0 r dwbc30_regs
-ffffffff82bb0dac r dwbc30_shift
-ffffffff82bb0ee0 r dwbc30_mask
-ffffffff82bb13b0 r mcif_wb30_regs
-ffffffff82bb14ac r mcif_wb30_shift
-ffffffff82bb1558 r mcif_wb30_mask
-ffffffff82bb1810 r aux_engine_regs
-ffffffff82bb18d8 r aux_mask
-ffffffff82bb1938 r aux_shift
-ffffffff82bb1950 r i2c_hw_regs
-ffffffff82bb1a68 r i2c_shifts
-ffffffff82bb1a94 r i2c_masks
-ffffffff82bb1b40 r audio_regs
-ffffffff82bb1c74 r audio_shift
-ffffffff82bb1c8c r audio_mask
-ffffffff82bb1cc8 r se_shift
-ffffffff82bb1da4 r se_mask
-ffffffff82bb2110 r vpg_regs
-ffffffff82bb2200 r vpg_shift
-ffffffff82bb2228 r vpg_mask
-ffffffff82bb22d0 r afmt_regs
-ffffffff82bb23a8 r afmt_shift
-ffffffff82bb23bc r afmt_mask
-ffffffff82bb2410 r stream_enc_regs
-ffffffff82bb3ab0 r hpo_dp_stream_enc_regs
-ffffffff82bb3ce0 r hpo_dp_se_shift
-ffffffff82bb3d08 r hpo_dp_se_mask
-ffffffff82bb3db0 r apg_regs
-ffffffff82bb3df0 r apg_shift
-ffffffff82bb3df8 r apg_mask
-ffffffff82bb3e10 r hpo_dp_link_enc_regs
-ffffffff82bb3f20 r hpo_dp_le_shift
-ffffffff82bb3f3c r hpo_dp_le_mask
-ffffffff82bb3fa0 r hwseq_reg
-ffffffff82bb41bc r hwseq_shift
-ffffffff82bb423c r hwseq_mask
+ffffffff82bae9c0 r mpc_regs
+ffffffff82bb01ac r mpc_shift
+ffffffff82bb0288 r mpc_mask
+ffffffff82bb0600 r dsc_regs
+ffffffff82bb084c r dsc_shift
+ffffffff82bb0904 r dsc_mask
+ffffffff82bb0be0 r dwbc30_regs
+ffffffff82bb0dbc r dwbc30_shift
+ffffffff82bb0ef0 r dwbc30_mask
+ffffffff82bb13c0 r mcif_wb30_regs
+ffffffff82bb14bc r mcif_wb30_shift
+ffffffff82bb1568 r mcif_wb30_mask
+ffffffff82bb1820 r aux_engine_regs
+ffffffff82bb18e8 r aux_mask
+ffffffff82bb1948 r aux_shift
+ffffffff82bb1960 r i2c_hw_regs
+ffffffff82bb1a78 r i2c_shifts
+ffffffff82bb1aa4 r i2c_masks
+ffffffff82bb1b50 r audio_regs
+ffffffff82bb1c84 r audio_shift
+ffffffff82bb1c9c r audio_mask
+ffffffff82bb1cd8 r se_shift
+ffffffff82bb1db4 r se_mask
+ffffffff82bb2120 r vpg_regs
+ffffffff82bb2210 r vpg_shift
+ffffffff82bb2238 r vpg_mask
+ffffffff82bb22e0 r afmt_regs
+ffffffff82bb23b8 r afmt_shift
+ffffffff82bb23cc r afmt_mask
+ffffffff82bb2420 r stream_enc_regs
+ffffffff82bb3ac0 r hpo_dp_stream_enc_regs
+ffffffff82bb3cf0 r hpo_dp_se_shift
+ffffffff82bb3d18 r hpo_dp_se_mask
+ffffffff82bb3dc0 r apg_regs
+ffffffff82bb3e00 r apg_shift
+ffffffff82bb3e08 r apg_mask
+ffffffff82bb3e20 r hpo_dp_link_enc_regs
+ffffffff82bb3f30 r hpo_dp_le_shift
+ffffffff82bb3f4c r hpo_dp_le_mask
+ffffffff82bb3fb0 r hwseq_reg
+ffffffff82bb41cc r hwseq_shift
+ffffffff82bb424c r hwseq_mask
 ffffffff82bb5000 r dccg314_funcs
 ffffffff82bb6000 r dcn314_str_enc_funcs
 ffffffff82bb7000 r dcn314_funcs
@@ -44577,48 +44581,48 @@ ffffffff82bbce78 r opp_mask
 ffffffff82bbcf50 r optc_regs
 ffffffff82bbd450 r optc_shift
 ffffffff82bbd510 r optc_mask
-ffffffff82bbd80c r mpc_regs
-ffffffff82bbeff8 r mpc_shift
-ffffffff82bbf0d4 r mpc_mask
-ffffffff82bbf440 r dsc_regs
-ffffffff82bbf750 r dsc_shift
-ffffffff82bbf808 r dsc_mask
-ffffffff82bbfae0 r dwbc30_regs
-ffffffff82bbfcbc r dwbc30_shift
-ffffffff82bbfdf0 r dwbc30_mask
-ffffffff82bc02c0 r mcif_wb30_regs
-ffffffff82bc03bc r mcif_wb30_shift
-ffffffff82bc0468 r mcif_wb30_mask
-ffffffff82bc0720 r aux_engine_regs
-ffffffff82bc07e8 r aux_mask
-ffffffff82bc0848 r aux_shift
-ffffffff82bc0860 r i2c_hw_regs
-ffffffff82bc0978 r i2c_shifts
-ffffffff82bc09a4 r i2c_masks
-ffffffff82bc0a50 r audio_regs
-ffffffff82bc0b84 r audio_shift
-ffffffff82bc0b9c r audio_mask
-ffffffff82bc0be0 r stream_enc_regs
-ffffffff82bc1284 r se_shift
-ffffffff82bc1360 r se_mask
-ffffffff82bc16d0 r vpg_regs
-ffffffff82bc17c0 r vpg_shift
-ffffffff82bc17e8 r vpg_mask
-ffffffff82bc1890 r afmt_regs
-ffffffff82bc1968 r afmt_shift
-ffffffff82bc197c r afmt_mask
-ffffffff82bc19d0 r hpo_dp_stream_enc_regs
-ffffffff82bc1c00 r hpo_dp_se_shift
-ffffffff82bc1c28 r hpo_dp_se_mask
-ffffffff82bc1cd0 r apg_regs
-ffffffff82bc1d10 r apg_shift
-ffffffff82bc1d18 r apg_mask
-ffffffff82bc1d30 r hpo_dp_link_enc_regs
-ffffffff82bc1e40 r hpo_dp_le_shift
-ffffffff82bc1e5c r hpo_dp_le_mask
-ffffffff82bc1ec0 r hwseq_reg
-ffffffff82bc20dc r hwseq_shift
-ffffffff82bc215c r hwseq_mask
+ffffffff82bbd810 r mpc_regs
+ffffffff82bbeffc r mpc_shift
+ffffffff82bbf0d8 r mpc_mask
+ffffffff82bbf450 r dsc_regs
+ffffffff82bbf760 r dsc_shift
+ffffffff82bbf818 r dsc_mask
+ffffffff82bbfaf0 r dwbc30_regs
+ffffffff82bbfccc r dwbc30_shift
+ffffffff82bbfe00 r dwbc30_mask
+ffffffff82bc02d0 r mcif_wb30_regs
+ffffffff82bc03cc r mcif_wb30_shift
+ffffffff82bc0478 r mcif_wb30_mask
+ffffffff82bc0730 r aux_engine_regs
+ffffffff82bc07f8 r aux_mask
+ffffffff82bc0858 r aux_shift
+ffffffff82bc0870 r i2c_hw_regs
+ffffffff82bc0988 r i2c_shifts
+ffffffff82bc09b4 r i2c_masks
+ffffffff82bc0a60 r audio_regs
+ffffffff82bc0b94 r audio_shift
+ffffffff82bc0bac r audio_mask
+ffffffff82bc0bf0 r stream_enc_regs
+ffffffff82bc1294 r se_shift
+ffffffff82bc1370 r se_mask
+ffffffff82bc16e0 r vpg_regs
+ffffffff82bc17d0 r vpg_shift
+ffffffff82bc17f8 r vpg_mask
+ffffffff82bc18a0 r afmt_regs
+ffffffff82bc1978 r afmt_shift
+ffffffff82bc198c r afmt_mask
+ffffffff82bc19e0 r hpo_dp_stream_enc_regs
+ffffffff82bc1c10 r hpo_dp_se_shift
+ffffffff82bc1c38 r hpo_dp_se_mask
+ffffffff82bc1ce0 r apg_regs
+ffffffff82bc1d20 r apg_shift
+ffffffff82bc1d28 r apg_mask
+ffffffff82bc1d40 r hpo_dp_link_enc_regs
+ffffffff82bc1e50 r hpo_dp_le_shift
+ffffffff82bc1e6c r hpo_dp_le_mask
+ffffffff82bc1ed0 r hwseq_reg
+ffffffff82bc20ec r hwseq_shift
+ffffffff82bc216c r hwseq_mask
 ffffffff82bc3000 r bios_regs
 ffffffff82bc3008 r res_cap_dcn31
 ffffffff82bc3048 r debug_defaults_diags
@@ -44660,48 +44664,48 @@ ffffffff82bc7e78 r opp_mask
 ffffffff82bc7f50 r optc_regs
 ffffffff82bc8450 r optc_shift
 ffffffff82bc8510 r optc_mask
-ffffffff82bc880c r mpc_regs
-ffffffff82bc9ff8 r mpc_shift
-ffffffff82bca0d4 r mpc_mask
-ffffffff82bca440 r dsc_regs
-ffffffff82bca68c r dsc_shift
-ffffffff82bca744 r dsc_mask
-ffffffff82bcaa20 r dwbc30_regs
-ffffffff82bcabfc r dwbc30_shift
-ffffffff82bcad30 r dwbc30_mask
-ffffffff82bcb200 r mcif_wb30_regs
-ffffffff82bcb2fc r mcif_wb30_shift
-ffffffff82bcb3a8 r mcif_wb30_mask
-ffffffff82bcb660 r aux_engine_regs
-ffffffff82bcb728 r aux_mask
-ffffffff82bcb788 r aux_shift
-ffffffff82bcb7a0 r i2c_hw_regs
-ffffffff82bcb8b8 r i2c_shifts
-ffffffff82bcb8e4 r i2c_masks
-ffffffff82bcb990 r audio_regs
-ffffffff82bcbac4 r audio_shift
-ffffffff82bcbadc r audio_mask
-ffffffff82bcbb20 r stream_enc_regs
-ffffffff82bcc1c4 r se_shift
-ffffffff82bcc2a0 r se_mask
-ffffffff82bcc610 r vpg_regs
-ffffffff82bcc700 r vpg_shift
-ffffffff82bcc728 r vpg_mask
-ffffffff82bcc7d0 r afmt_regs
-ffffffff82bcc8a8 r afmt_shift
-ffffffff82bcc8bc r afmt_mask
-ffffffff82bcc910 r hpo_dp_stream_enc_regs
-ffffffff82bccb40 r hpo_dp_se_shift
-ffffffff82bccb68 r hpo_dp_se_mask
-ffffffff82bccc10 r apg_regs
-ffffffff82bccc50 r apg_shift
-ffffffff82bccc58 r apg_mask
-ffffffff82bccc70 r hpo_dp_link_enc_regs
-ffffffff82bccd80 r hpo_dp_le_shift
-ffffffff82bccd9c r hpo_dp_le_mask
-ffffffff82bcce00 r hwseq_reg
-ffffffff82bcd01c r hwseq_shift
-ffffffff82bcd09c r hwseq_mask
+ffffffff82bc8810 r mpc_regs
+ffffffff82bc9ffc r mpc_shift
+ffffffff82bca0d8 r mpc_mask
+ffffffff82bca450 r dsc_regs
+ffffffff82bca69c r dsc_shift
+ffffffff82bca754 r dsc_mask
+ffffffff82bcaa30 r dwbc30_regs
+ffffffff82bcac0c r dwbc30_shift
+ffffffff82bcad40 r dwbc30_mask
+ffffffff82bcb210 r mcif_wb30_regs
+ffffffff82bcb30c r mcif_wb30_shift
+ffffffff82bcb3b8 r mcif_wb30_mask
+ffffffff82bcb670 r aux_engine_regs
+ffffffff82bcb738 r aux_mask
+ffffffff82bcb798 r aux_shift
+ffffffff82bcb7b0 r i2c_hw_regs
+ffffffff82bcb8c8 r i2c_shifts
+ffffffff82bcb8f4 r i2c_masks
+ffffffff82bcb9a0 r audio_regs
+ffffffff82bcbad4 r audio_shift
+ffffffff82bcbaec r audio_mask
+ffffffff82bcbb30 r stream_enc_regs
+ffffffff82bcc1d4 r se_shift
+ffffffff82bcc2b0 r se_mask
+ffffffff82bcc620 r vpg_regs
+ffffffff82bcc710 r vpg_shift
+ffffffff82bcc738 r vpg_mask
+ffffffff82bcc7e0 r afmt_regs
+ffffffff82bcc8b8 r afmt_shift
+ffffffff82bcc8cc r afmt_mask
+ffffffff82bcc920 r hpo_dp_stream_enc_regs
+ffffffff82bccb50 r hpo_dp_se_shift
+ffffffff82bccb78 r hpo_dp_se_mask
+ffffffff82bccc20 r apg_regs
+ffffffff82bccc60 r apg_shift
+ffffffff82bccc68 r apg_mask
+ffffffff82bccc80 r hpo_dp_link_enc_regs
+ffffffff82bccd90 r hpo_dp_le_shift
+ffffffff82bccdac r hpo_dp_le_mask
+ffffffff82bcce10 r hwseq_reg
+ffffffff82bcd02c r hwseq_shift
+ffffffff82bcd0ac r hwseq_mask
 ffffffff82bce000 r bios_regs
 ffffffff82bce008 r res_cap_dcn31
 ffffffff82bce048 r debug_defaults_diags
@@ -44743,48 +44747,48 @@ ffffffff82bd2e78 r opp_mask
 ffffffff82bd2f50 r optc_regs
 ffffffff82bd3450 r optc_shift
 ffffffff82bd3510 r optc_mask
-ffffffff82bd380c r mpc_regs
-ffffffff82bd4ff8 r mpc_shift
-ffffffff82bd50d4 r mpc_mask
-ffffffff82bd5440 r dsc_regs
-ffffffff82bd568c r dsc_shift
-ffffffff82bd5744 r dsc_mask
-ffffffff82bd5a20 r dwbc30_regs
-ffffffff82bd5bfc r dwbc30_shift
-ffffffff82bd5d30 r dwbc30_mask
-ffffffff82bd6200 r mcif_wb30_regs
-ffffffff82bd62fc r mcif_wb30_shift
-ffffffff82bd63a8 r mcif_wb30_mask
-ffffffff82bd6660 r aux_engine_regs
-ffffffff82bd6728 r aux_mask
-ffffffff82bd6788 r aux_shift
-ffffffff82bd67a0 r i2c_hw_regs
-ffffffff82bd68b8 r i2c_shifts
-ffffffff82bd68e4 r i2c_masks
-ffffffff82bd6990 r audio_regs
-ffffffff82bd6ac4 r audio_shift
-ffffffff82bd6adc r audio_mask
-ffffffff82bd6b20 r stream_enc_regs
-ffffffff82bd71c4 r se_shift
-ffffffff82bd72a0 r se_mask
-ffffffff82bd7610 r vpg_regs
-ffffffff82bd7700 r vpg_shift
-ffffffff82bd7728 r vpg_mask
-ffffffff82bd77d0 r afmt_regs
-ffffffff82bd78a8 r afmt_shift
-ffffffff82bd78bc r afmt_mask
-ffffffff82bd7910 r hpo_dp_stream_enc_regs
-ffffffff82bd7b40 r hpo_dp_se_shift
-ffffffff82bd7b68 r hpo_dp_se_mask
-ffffffff82bd7c10 r apg_regs
-ffffffff82bd7c50 r apg_shift
-ffffffff82bd7c58 r apg_mask
-ffffffff82bd7c70 r hpo_dp_link_enc_regs
-ffffffff82bd7d80 r hpo_dp_le_shift
-ffffffff82bd7d9c r hpo_dp_le_mask
-ffffffff82bd7e00 r hwseq_reg
-ffffffff82bd801c r hwseq_shift
-ffffffff82bd809c r hwseq_mask
+ffffffff82bd3810 r mpc_regs
+ffffffff82bd4ffc r mpc_shift
+ffffffff82bd50d8 r mpc_mask
+ffffffff82bd5450 r dsc_regs
+ffffffff82bd569c r dsc_shift
+ffffffff82bd5754 r dsc_mask
+ffffffff82bd5a30 r dwbc30_regs
+ffffffff82bd5c0c r dwbc30_shift
+ffffffff82bd5d40 r dwbc30_mask
+ffffffff82bd6210 r mcif_wb30_regs
+ffffffff82bd630c r mcif_wb30_shift
+ffffffff82bd63b8 r mcif_wb30_mask
+ffffffff82bd6670 r aux_engine_regs
+ffffffff82bd6738 r aux_mask
+ffffffff82bd6798 r aux_shift
+ffffffff82bd67b0 r i2c_hw_regs
+ffffffff82bd68c8 r i2c_shifts
+ffffffff82bd68f4 r i2c_masks
+ffffffff82bd69a0 r audio_regs
+ffffffff82bd6ad4 r audio_shift
+ffffffff82bd6aec r audio_mask
+ffffffff82bd6b30 r stream_enc_regs
+ffffffff82bd71d4 r se_shift
+ffffffff82bd72b0 r se_mask
+ffffffff82bd7620 r vpg_regs
+ffffffff82bd7710 r vpg_shift
+ffffffff82bd7738 r vpg_mask
+ffffffff82bd77e0 r afmt_regs
+ffffffff82bd78b8 r afmt_shift
+ffffffff82bd78cc r afmt_mask
+ffffffff82bd7920 r hpo_dp_stream_enc_regs
+ffffffff82bd7b50 r hpo_dp_se_shift
+ffffffff82bd7b78 r hpo_dp_se_mask
+ffffffff82bd7c20 r apg_regs
+ffffffff82bd7c60 r apg_shift
+ffffffff82bd7c68 r apg_mask
+ffffffff82bd7c80 r hpo_dp_link_enc_regs
+ffffffff82bd7d90 r hpo_dp_le_shift
+ffffffff82bd7dac r hpo_dp_le_mask
+ffffffff82bd7e10 r hwseq_reg
+ffffffff82bd802c r hwseq_shift
+ffffffff82bd80ac r hwseq_mask
 ffffffff82bd9000 r dccg32_funcs
 ffffffff82bda000 r dcn32_link_enc_funcs
 ffffffff82bdb000 r dcn32_str_enc_funcs
@@ -44820,34 +44824,34 @@ ffffffff82be21c4 r opp_shift
 ffffffff82be21fc r opp_mask
 ffffffff82be22d0 r optc_shift
 ffffffff82be2390 r optc_mask
-ffffffff82be268c r mpc_shift
-ffffffff82be2768 r mpc_mask
-ffffffff82be2ad4 r dsc_shift
-ffffffff82be2b8c r dsc_mask
-ffffffff82be2e64 r dwbc30_shift
-ffffffff82be2f98 r dwbc30_mask
-ffffffff82be3460 r mcif_wb30_shift
-ffffffff82be350c r mcif_wb30_mask
-ffffffff82be37b8 r aux_mask
-ffffffff82be3818 r aux_shift
-ffffffff82be3830 r i2c_shifts
-ffffffff82be385c r i2c_masks
-ffffffff82be3900 r audio_shift
-ffffffff82be3918 r audio_mask
-ffffffff82be3954 r se_shift
-ffffffff82be3a30 r se_mask
-ffffffff82be3d9c r vpg_shift
-ffffffff82be3dc4 r vpg_mask
-ffffffff82be3e58 r afmt_shift
-ffffffff82be3e6c r afmt_mask
-ffffffff82be3eb0 r hpo_dp_se_shift
-ffffffff82be3ed8 r hpo_dp_se_mask
-ffffffff82be3f78 r apg_shift
-ffffffff82be3f80 r apg_mask
-ffffffff82be3f98 r hpo_dp_le_shift
-ffffffff82be3fb4 r hpo_dp_le_mask
-ffffffff82be4018 r hwseq_shift
-ffffffff82be4098 r hwseq_mask
+ffffffff82be2690 r mpc_shift
+ffffffff82be276c r mpc_mask
+ffffffff82be2ad8 r dsc_shift
+ffffffff82be2b90 r dsc_mask
+ffffffff82be2e68 r dwbc30_shift
+ffffffff82be2f9c r dwbc30_mask
+ffffffff82be3464 r mcif_wb30_shift
+ffffffff82be3510 r mcif_wb30_mask
+ffffffff82be37bc r aux_mask
+ffffffff82be381c r aux_shift
+ffffffff82be3834 r i2c_shifts
+ffffffff82be3860 r i2c_masks
+ffffffff82be3904 r audio_shift
+ffffffff82be391c r audio_mask
+ffffffff82be3958 r se_shift
+ffffffff82be3a34 r se_mask
+ffffffff82be3da0 r vpg_shift
+ffffffff82be3dc8 r vpg_mask
+ffffffff82be3e5c r afmt_shift
+ffffffff82be3e70 r afmt_mask
+ffffffff82be3eb4 r hpo_dp_se_shift
+ffffffff82be3edc r hpo_dp_se_mask
+ffffffff82be3f7c r apg_shift
+ffffffff82be3f84 r apg_mask
+ffffffff82be3f9c r hpo_dp_le_shift
+ffffffff82be3fb8 r hpo_dp_le_mask
+ffffffff82be401c r hwseq_shift
+ffffffff82be409c r hwseq_mask
 ffffffff82be5000 r dcn321_link_enc_funcs
 ffffffff82be6000 r res_cap_dcn321
 ffffffff82be6040 r debug_defaults_diags
@@ -44876,34 +44880,34 @@ ffffffff82be81c4 r opp_shift
 ffffffff82be81fc r opp_mask
 ffffffff82be82d0 r optc_shift
 ffffffff82be8390 r optc_mask
-ffffffff82be868c r mpc_shift
-ffffffff82be8768 r mpc_mask
-ffffffff82be8ad4 r dsc_shift
-ffffffff82be8b8c r dsc_mask
-ffffffff82be8e64 r dwbc30_shift
-ffffffff82be8f98 r dwbc30_mask
-ffffffff82be9460 r mcif_wb30_shift
-ffffffff82be950c r mcif_wb30_mask
-ffffffff82be97b8 r aux_mask
-ffffffff82be9818 r aux_shift
-ffffffff82be9830 r i2c_shifts
-ffffffff82be985c r i2c_masks
-ffffffff82be9900 r audio_shift
-ffffffff82be9918 r audio_mask
-ffffffff82be9954 r se_shift
-ffffffff82be9a30 r se_mask
-ffffffff82be9d9c r vpg_shift
-ffffffff82be9dc4 r vpg_mask
-ffffffff82be9e58 r afmt_shift
-ffffffff82be9e6c r afmt_mask
-ffffffff82be9eb0 r hpo_dp_se_shift
-ffffffff82be9ed8 r hpo_dp_se_mask
-ffffffff82be9f78 r apg_shift
-ffffffff82be9f80 r apg_mask
-ffffffff82be9f98 r hpo_dp_le_shift
-ffffffff82be9fb4 r hpo_dp_le_mask
-ffffffff82bea018 r hwseq_shift
-ffffffff82bea098 r hwseq_mask
+ffffffff82be8690 r mpc_shift
+ffffffff82be876c r mpc_mask
+ffffffff82be8ad8 r dsc_shift
+ffffffff82be8b90 r dsc_mask
+ffffffff82be8e68 r dwbc30_shift
+ffffffff82be8f9c r dwbc30_mask
+ffffffff82be9464 r mcif_wb30_shift
+ffffffff82be9510 r mcif_wb30_mask
+ffffffff82be97bc r aux_mask
+ffffffff82be981c r aux_shift
+ffffffff82be9834 r i2c_shifts
+ffffffff82be9860 r i2c_masks
+ffffffff82be9904 r audio_shift
+ffffffff82be991c r audio_mask
+ffffffff82be9958 r se_shift
+ffffffff82be9a34 r se_mask
+ffffffff82be9da0 r vpg_shift
+ffffffff82be9dc8 r vpg_mask
+ffffffff82be9e5c r afmt_shift
+ffffffff82be9e70 r afmt_mask
+ffffffff82be9eb4 r hpo_dp_se_shift
+ffffffff82be9edc r hpo_dp_se_mask
+ffffffff82be9f7c r apg_shift
+ffffffff82be9f84 r apg_mask
+ffffffff82be9f9c r hpo_dp_le_shift
+ffffffff82be9fb8 r hpo_dp_le_mask
+ffffffff82bea01c r hwseq_shift
+ffffffff82bea09c r hwseq_mask
 ffffffff82bec000 R dcn10_soc_defaults
 ffffffff82bec08c R dcn10_ip_defaults
 ffffffff82bf7000 R dml20_funcs
@@ -44977,10 +44981,10 @@ ffffffff82c0d1b0 r hpd_mask
 ffffffff82c0d1c0 r ddc_data_regs_dcn
 ffffffff82c0d370 r ddc_clk_regs_dcn
 ffffffff82c0d520 r ddc_shift
-ffffffff82c0d610 r ddc_mask
-ffffffff82c0d700 r generic_regs
-ffffffff82c0d770 r generic_shift
-ffffffff82c0d780 r generic_mask
+ffffffff82c0d640 r ddc_mask
+ffffffff82c0d760 r generic_regs
+ffffffff82c0d7d0 r generic_shift
+ffffffff82c0d7e0 r generic_mask
 ffffffff82c0e000 r funcs
 ffffffff82c0f000 r funcs
 ffffffff82c0f050 r hpd_regs
@@ -45001,10 +45005,10 @@ ffffffff82c111b0 r hpd_mask
 ffffffff82c111c0 r ddc_data_regs_dcn
 ffffffff82c11370 r ddc_clk_regs_dcn
 ffffffff82c11520 r ddc_shift
-ffffffff82c11610 r ddc_mask
-ffffffff82c11700 r generic_regs
-ffffffff82c11770 r generic_shift
-ffffffff82c11780 r generic_mask
+ffffffff82c11640 r ddc_mask
+ffffffff82c11760 r generic_regs
+ffffffff82c117d0 r generic_shift
+ffffffff82c117e0 r generic_mask
 ffffffff82c12000 r funcs
 ffffffff82c13000 r funcs
 ffffffff82c13050 r hpd_regs
@@ -45025,10 +45029,10 @@ ffffffff82c15178 r hpd_mask
 ffffffff82c15190 r ddc_data_regs_dcn
 ffffffff82c15340 r ddc_clk_regs_dcn
 ffffffff82c154f0 r ddc_shift
-ffffffff82c155e0 r ddc_mask
-ffffffff82c156d0 r generic_regs
-ffffffff82c15740 r generic_shift
-ffffffff82c15750 r generic_mask
+ffffffff82c15610 r ddc_mask
+ffffffff82c15730 r generic_regs
+ffffffff82c157a0 r generic_shift
+ffffffff82c157b0 r generic_mask
 ffffffff82c16000 r funcs
 ffffffff82c17000 r funcs
 ffffffff82c18000 r funcs
@@ -46559,8063 +46563,8063 @@ ffffffff82de1000 r __retguard_3488
 ffffffff82de1008 r __retguard_3506
 ffffffff82de1010 r __retguard_686
 ffffffff82de1018 r __retguard_974
-ffffffff82de2000 r __retguard_62
-ffffffff82de3000 r __retguard_2097
-ffffffff82de3008 r __retguard_160
-ffffffff82de3010 r __retguard_2997
-ffffffff82de3018 r __retguard_538
-ffffffff82de3020 r __retguard_3144
-ffffffff82de4000 r __retguard_2784
-ffffffff82de4008 r __retguard_1551
-ffffffff82de4010 r __retguard_3223
-ffffffff82de4018 r __retguard_3206
-ffffffff82de4020 r __retguard_2583
-ffffffff82de4028 r __retguard_3752
-ffffffff82de4030 r __retguard_2781
-ffffffff82de4038 r __retguard_441
-ffffffff82de4040 r __retguard_2950
-ffffffff82de4048 r __retguard_3069
-ffffffff82de4050 r __retguard_2553
-ffffffff82de4058 r __retguard_3626
-ffffffff82de4060 r __retguard_2899
-ffffffff82de4068 r __retguard_116
-ffffffff82de4070 r __retguard_2943
-ffffffff82de4078 r __retguard_3766
-ffffffff82de4080 r __retguard_1200
-ffffffff82de4088 r __retguard_2852
-ffffffff82de4090 r __retguard_2019
-ffffffff82de4098 r __retguard_3827
-ffffffff82de40a0 r __retguard_2872
-ffffffff82de40a8 r __retguard_1537
-ffffffff82de40b0 r __retguard_1028
-ffffffff82de40b8 r __retguard_2058
-ffffffff82de5000 r __retguard_562
-ffffffff82de5008 r __retguard_167
-ffffffff82de5010 r __retguard_3643
-ffffffff82de5018 r __retguard_3866
-ffffffff82de6000 r __retguard_2149
-ffffffff82de6008 r __retguard_2407
-ffffffff82de6010 r __retguard_437
-ffffffff82de6018 r __retguard_791
-ffffffff82de6020 r __retguard_776
-ffffffff82de6028 r __retguard_2571
-ffffffff82de6030 r __retguard_245
-ffffffff82de6038 r __retguard_3633
-ffffffff82de6040 r __retguard_2183
-ffffffff82de6048 r __retguard_2841
-ffffffff82de6050 r __retguard_781
-ffffffff82de6058 r __retguard_430
-ffffffff82de6060 r __retguard_3913
-ffffffff82de6068 r __retguard_2788
-ffffffff82de6070 r __retguard_1879
-ffffffff82de6078 r __retguard_1700
-ffffffff82de6080 r __retguard_278
-ffffffff82de6088 r __retguard_2344
-ffffffff82de7000 r __retguard_1318
-ffffffff82de7008 r __retguard_2566
-ffffffff82de7010 r __retguard_3360
-ffffffff82de7018 r __retguard_1302
-ffffffff82de7020 r __retguard_1796
-ffffffff82de7028 r __retguard_3824
-ffffffff82de7030 r __retguard_1044
-ffffffff82de7038 r __retguard_3125
-ffffffff82de7040 r __retguard_3085
-ffffffff82de7048 r __retguard_1637
-ffffffff82de7050 r __retguard_23
-ffffffff82de7058 r __retguard_3111
-ffffffff82de7060 r __retguard_3639
-ffffffff82de7068 r __retguard_9
-ffffffff82de7070 r __retguard_818
-ffffffff82de7078 r __retguard_2345
-ffffffff82de7080 r __retguard_3964
-ffffffff82de7088 r __retguard_1821
-ffffffff82de7090 r __retguard_770
-ffffffff82de7098 r __retguard_3017
-ffffffff82de70a0 r __retguard_2329
-ffffffff82de70a8 r __retguard_823
-ffffffff82de70b0 r __retguard_1589
-ffffffff82de70b8 r __retguard_3889
-ffffffff82de70c0 r __retguard_109
-ffffffff82de70c8 r __retguard_514
-ffffffff82de70d0 r __retguard_3163
-ffffffff82de70d8 r __retguard_1438
-ffffffff82de70e0 r __retguard_2152
-ffffffff82de70e8 r __retguard_241
-ffffffff82de70f0 r __retguard_2848
-ffffffff82de70f8 r __retguard_3336
-ffffffff82de7100 r __retguard_2343
-ffffffff82de7108 r __retguard_354
-ffffffff82de7110 r __retguard_2966
-ffffffff82de7118 r __retguard_2664
-ffffffff82de7120 r __retguard_3767
-ffffffff82de7128 r __retguard_2688
-ffffffff82de7130 r __retguard_382
-ffffffff82de7138 r __retguard_3867
-ffffffff82de7140 r __retguard_137
-ffffffff82de7148 r __retguard_3361
-ffffffff82de7150 r __retguard_1194
-ffffffff82de7158 r __retguard_833
-ffffffff82de7160 r __retguard_1356
-ffffffff82de7168 r __retguard_2349
-ffffffff82de7170 r __retguard_1933
-ffffffff82de8000 r __retguard_3010
-ffffffff82de8008 r __retguard_2902
-ffffffff82de8010 r __retguard_2213
-ffffffff82de8018 r __retguard_298
-ffffffff82de8020 r __retguard_1344
-ffffffff82de8028 r __retguard_983
-ffffffff82de8030 r __retguard_3000
-ffffffff82de8038 r __retguard_1948
-ffffffff82de8040 r __retguard_2200
-ffffffff82de8048 r __retguard_2720
-ffffffff82de8050 r __retguard_949
-ffffffff82de8058 r __retguard_3820
-ffffffff82de8060 r __retguard_1539
-ffffffff82de8068 r __retguard_3119
-ffffffff82de8070 r __retguard_1685
-ffffffff82de8078 r __retguard_2724
-ffffffff82de8080 r __retguard_214
-ffffffff82de8088 r __retguard_2590
-ffffffff82de8090 r __retguard_2168
-ffffffff82de8098 r __retguard_2013
-ffffffff82de80a0 r __retguard_3801
-ffffffff82de80a8 r __retguard_1058
-ffffffff82de80b0 r __retguard_3354
-ffffffff82de80b8 r __retguard_2114
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-ffffffff8325f000 d evergreen_cs_packet_parse_vline.vline_start_end
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-ffffffff83266018 D radeon_pcie_gen2
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-ffffffff8326603c D radeon_bapm
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-ffffffff8326e00c D amdgpu_audio
-ffffffff8326e010 D amdgpu_pcie_gen2
-ffffffff8326e014 D amdgpu_msi
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-ffffffff8326e01c D amdgpu_fw_load_type
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-ffffffff8326e024 D amdgpu_runtime_pm
-ffffffff8326e028 D amdgpu_ip_block_mask
-ffffffff8326e02c D amdgpu_bapm
-ffffffff8326e030 D amdgpu_vm_size
-ffffffff8326e034 D amdgpu_vm_fragment_size
-ffffffff8326e038 D amdgpu_vm_block_size
-ffffffff8326e03c D amdgpu_vm_update_mode
-ffffffff8326e040 D amdgpu_dc
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-ffffffff8326e050 D amdgpu_cg_mask
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-ffffffff8326e06c D amdgpu_gpu_recovery
-ffffffff8326e070 D amdgpu_smu_pptable_id
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-ffffffff832da088 D msi_pic
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-ffffffff832e20b8 D pcmcia_3cxem556_func0_cfe0
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-ffffffff832ef000 D isadma_cd
-ffffffff832f0000 D fdc_cd
-ffffffff832f1000 D fd_types
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-ffffffff832f2000 D mpu_cd
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-ffffffff832f4000 D spkr_cd
-ffffffff832f5000 D wbsio_cd
-ffffffff832f6000 D schsio_cd
-ffffffff832f7000 D it_cd
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-ffffffff832fb000 D wsdisplay_cd
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-ffffffff832fb058 D wsdisplay_defaultscreens
-ffffffff832fc000 D wskbd_cd
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-ffffffff832fc040 D wskbd_srcops
-ffffffff832fd000 d compose_tab
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-ffffffff832ff000 D wsmux_srcops
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-ffffffff83305000 D ukbd_keymapdata
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-ffffffff83308000 D uhub_cd
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-ffffffff8330a000 D uvideo_ctrls
-ffffffff8330a2d8 D uvideo_cd
-ffffffff8330b000 D utvfu_norm_params
-ffffffff8330b030 D utvfu_cd
-ffffffff8330c000 D udl_reg_vals_640x480_60
-ffffffff8330c020 D udl_reg_vals_640x480_67
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-ffffffff8330c060 D udl_reg_vals_640x480_75
-ffffffff8330c080 D udl_reg_vals_800x480_61
-ffffffff8330c0a0 D udl_reg_vals_800x600_56
-ffffffff8330c0c0 D udl_reg_vals_800x600_60
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-ffffffff8330c120 D udl_reg_vals_800x600_75
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-ffffffff8330c160 D udl_reg_vals_1024x768_70
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-ffffffff8330c1a0 D udl_reg_vals_1280x800_60
-ffffffff8330c1c0 D udl_reg_vals_1280x960_60
-ffffffff8330c1e0 D udl_reg_vals_1280x1024_60
-ffffffff8330c200 D udl_reg_vals_1280x1024_75
-ffffffff8330c220 D udl_reg_vals_1366x768_60
-ffffffff8330c240 D udl_reg_vals_1440x900_60
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-ffffffff8330c2a0 D udl_reg_vals_1680x1050_60
-ffffffff8330c2c0 D udl_reg_vals_1600x1200_60
-ffffffff8330c2e0 D udl_reg_vals_1920x1080_60
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-ffffffff8330d510 D udl_cd
-ffffffff8330d530 D udl_stdscreen
-ffffffff8330d560 D udl_scrlist
-ffffffff8330d568 D udl_screenlist
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-ffffffff8330f200 d umq_ROLAND_ROLAND_UA700_3
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-ffffffff8330f560 d umq_ROLAND_ROLAND_UM880N_0_fixed_ep_desc
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-ffffffff8330f5c0 d umq_ROLAND_ROLAND_UM4_2_fixed_ep_desc
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-ffffffff8330f680 d umq_ROLAND_ROLAND_PC300_2_fixed_ep_desc
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-ffffffff8330f6d0 d umq_ROLAND_ROLAND_SK500_2_fixed_ep_endpoints
-ffffffff8330f6e0 d umq_ROLAND_ROLAND_SCD70_2_fixed_ep_desc
-ffffffff8330f700 d umq_ROLAND_ROLAND_SCD70_2_fixed_ep_endpoints
-ffffffff8330f710 d umq_ROLAND_ROLAND_UM550_0_fixed_ep_desc
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-ffffffff8330f740 d umq_ROLAND_ROLAND_SD20_0_fixed_ep_desc
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-ffffffff8330f7a0 d umq_ROLAND_ROLAND_UA700_3_fixed_ep_desc
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-ffffffff83311000 D ugen_cd
-ffffffff83312000 D uhidev_cd
-ffffffff83312020 d uhidev_use_rdesc.reportbuf
-ffffffff83313000 D uhid_cd
-ffffffff83314000 D fido_cd
-ffffffff83315000 D ujoy_cd
-ffffffff83316000 D ukbd_cd
-ffffffff83317000 D ums_cd
-ffffffff83317020 d ums_fix_elecom_descriptor.match
-ffffffff83318000 D umt_cd
-ffffffff83319000 D def_scale
-ffffffff83319020 D uts_cd
-ffffffff8331a000 D ubcmtp_cd
-ffffffff8331b000 D ucycom_cd
-ffffffff8331c000 D uslhcom_cd
-ffffffff8331d000 D ulpt_fwdevs
-ffffffff8331d060 D ulpt_cd
-ffffffff8331d080 D ulptusein
-ffffffff8331e000 D umass_cd
-ffffffff8331e020 d umass_bbb_transfer.dCBWtag
-ffffffff8331f000 D uthum_cd
-ffffffff83320000 D ugold_cd
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-ffffffff83321000 D utrh_cd
-ffffffff83322000 D uoakrh_cd
-ffffffff83323000 D uoaklux_cd
-ffffffff83324000 D uoakv_cd
-ffffffff83325000 D uonerng_cd
-ffffffff83326000 D urng_cd
-ffffffff83327000 D udcf_cd
-ffffffff83328000 D umbg_cd
-ffffffff83329000 D uvisor_cd
-ffffffff8332a000 D udsbr_cd
-ffffffff8332b000 D utwitch_cd
-ffffffff8332c000 D aue_cd
-ffffffff8332d000 D axe_cd
-ffffffff8332e000 D axen_cd
-ffffffff8332f000 D smsc_cd
-ffffffff83330000 D cue_devs
-ffffffff83330010 D cue_cd
-ffffffff83331000 D kue_cd
-ffffffff83332000 D cdce_cd
-ffffffff83333000 D urndis_cd
-ffffffff83334000 D mos_cd
-ffffffff83335000 D mue_cd
-ffffffff83336000 D udav_cd
-ffffffff83337000 D upl_devs
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-ffffffff83338000 D ugl_devs
-ffffffff83338008 D ugl_cd
-ffffffff83339000 D url_cd
-ffffffff8333a000 D ure_cd
-ffffffff8333b000 D uaq_cd
-ffffffff8333c000 D umodem_cd
-ffffffff8333d000 D uftdi_cd
-ffffffff8333e000 D uplcom_cd
-ffffffff8333f000 D umct_cd
-ffffffff83340000 D uvscom_cd
-ffffffff83341000 D ubsa_cd
-ffffffff83342000 D ukspan_cd
-ffffffff83343000 D uslcom_cd
-ffffffff83344000 D uark_cd
-ffffffff83345000 D moscom_cd
-ffffffff83346000 D umcs_cd
-ffffffff83347000 D uscom_cd
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-ffffffff83349000 D uxrcom_cd
-ffffffff8334a000 D uipaq_cd
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+ffffffff836b6088 b dml1_rq_dlg_get_row_heights.__warned
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+ffffffff836d2040 B wsdisplay_cons_kbd_pollc
+ffffffff836d2048 B ws_get_param
+ffffffff836d2050 B ws_set_param
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+ffffffff836d4000 b compose_tab_inorder
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+ffffffff836d6000 B wsemul_vt100_console_emuldata
+ffffffff836d7000 B pckbd_consdata
+ffffffff836d7038 B pckbd_bell_fn
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+ffffffff836d8000 b wscninit.initted
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+ffffffff836dc010 b usb_nbuses
+ffffffff836dc018 B usbpalock
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+ffffffff836de008 b usb_delay_ms.usb_delay_wchan
+ffffffff836de010 b usbd_probe_and_attach.cookie
+ffffffff836df000 b t_wait
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+ffffffff836e3314 B odp
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+ffffffff836e4000 B scope
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+ffffffff836e9000 B acpitz_cpu_setperf
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+ffffffff83732008 B vm_pool
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+ffffffff83733000 B sdmmc_verbose
+ffffffff83734000 B utc_offset
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+ffffffff83735000 B mountroot
+ffffffff83736000 B __kernel_bss_end
 ffffffff83800000 B _end
 ffffffff83800000 B end