--- 7.2/2023-03-03T14:25:27Z/2023-02-26T00:00:00Z/nm-bsd-ot14.txt	Sun Mar  5 05:28:30 2023
+++ 7.2/2023-03-03T14:25:27Z/2023-02-27T00:00:00Z/nm-bsd-ot14.txt	Sun Mar  5 08:02:39 2023
@@ -5466,13 +5466,21 @@ ffffffff81290000 T clockintr_init
 ffffffff81290300 T clockintr_statvar_init
 ffffffff812903c0 T clockintr_setstatclockrate
 ffffffff812904c0 T clockintr_cpu_init
-ffffffff812906e0 T nsec_advance
-ffffffff81290760 T clockintr_trigger
-ffffffff812907f0 T clockintr_dispatch
-ffffffff81290d00 T sysctl_clockintr
-ffffffff81290e70 T db_show_all_clockintr
-ffffffff81291060 T db_show_clockintr_cpu
-ffffffff812911b0 T db_show_clockintr
+ffffffff81290810 T clockintr_establish
+ffffffff81290870 T clockintr_hardclock
+ffffffff81290920 T clockintr_statclock
+ffffffff81290a60 T clockintr_schedclock
+ffffffff81290b20 T clockintr_schedule
+ffffffff81290b50 T clockintr_advance
+ffffffff81290bd0 T clockintr_trigger
+ffffffff81290c60 T clockintr_dispatch
+ffffffff81290f60 T nsec_advance
+ffffffff81290fe0 T clockintr_expiration
+ffffffff81291010 T clockintr_nsecuptime
+ffffffff81291040 T sysctl_clockintr
+ffffffff812911b0 T db_show_all_clockintr
+ffffffff81291280 T db_show_clockintr_cpu
+ffffffff81291460 T db_show_clockintr
 ffffffff81292000 T filedesc_init
 ffffffff81292090 T find_last_set
 ffffffff81292130 T fd_iterfile
@@ -34754,33 +34762,33 @@ ffffffff8234a490 T wsemul_vt100_output
 ffffffff8234a750 T wsemul_vt100_detach
 ffffffff8234a880 T wsemul_vt100_resetop
 ffffffff8234aa10 T wsemul_vt100_output_esc
-ffffffff8234b020 T wsemul_vt100_output_csi
-ffffffff8234b140 T wsemul_vt100_output_scs94
-ffffffff8234b1f0 T wsemul_vt100_output_scs94_percent
-ffffffff8234b240 T wsemul_vt100_output_scs96
-ffffffff8234b390 T wsemul_vt100_output_scs96_percent
-ffffffff8234b3e0 T wsemul_vt100_output_esc_hash
-ffffffff8234b740 T wsemul_vt100_output_esc_spc
-ffffffff8234b770 T wsemul_vt100_output_string
-ffffffff8234b7d0 T wsemul_vt100_output_string_esc
-ffffffff8234b820 T wsemul_vt100_output_dcs
-ffffffff8234b8c0 T wsemul_vt100_output_dcs_dollar
-ffffffff8234b910 T wsemul_vt100_output_esc_percent
-ffffffff8234b970 T wsemul_vt100_init
-ffffffff8234b9d0 T wsemul_vt100_reset
-ffffffff8234bad0 T wsemul_vt100_nextline
-ffffffff8234bb60 T wsemul_vt100_output_normal
-ffffffff8234bda0 T wsemul_vt100_output_c0c1
-ffffffff8234c020 T wsemul_vt100_jump_scroll
+ffffffff8234b070 T wsemul_vt100_output_csi
+ffffffff8234b190 T wsemul_vt100_output_scs94
+ffffffff8234b240 T wsemul_vt100_output_scs94_percent
+ffffffff8234b290 T wsemul_vt100_output_scs96
+ffffffff8234b3e0 T wsemul_vt100_output_scs96_percent
+ffffffff8234b430 T wsemul_vt100_output_esc_hash
+ffffffff8234b790 T wsemul_vt100_output_esc_spc
+ffffffff8234b7c0 T wsemul_vt100_output_string
+ffffffff8234b830 T wsemul_vt100_output_string_esc
+ffffffff8234b880 T wsemul_vt100_output_dcs
+ffffffff8234b920 T wsemul_vt100_output_dcs_dollar
+ffffffff8234b970 T wsemul_vt100_output_esc_percent
+ffffffff8234b9d0 T wsemul_vt100_init
+ffffffff8234ba30 T wsemul_vt100_reset
+ffffffff8234bb30 T wsemul_vt100_nextline
+ffffffff8234bbc0 T wsemul_vt100_output_normal
+ffffffff8234be00 T wsemul_vt100_output_c0c1
+ffffffff8234c080 T wsemul_vt100_jump_scroll
 ffffffff8234d000 T wsemul_vt100_scrollup
 ffffffff8234d150 T wsemul_vt100_scrolldown
 ffffffff8234d290 T wsemul_vt100_ed
 ffffffff8234d500 T wsemul_vt100_el
 ffffffff8234d5f0 T wsemul_vt100_handle_csi
-ffffffff8234e560 T vt100_ansimode
-ffffffff8234e5d0 T vt100_decmode
-ffffffff8234e700 T vt100_selectattribute
-ffffffff8234e840 T wsemul_vt100_handle_dcs
+ffffffff8234e580 T vt100_ansimode
+ffffffff8234e5f0 T vt100_decmode
+ffffffff8234e720 T vt100_selectattribute
+ffffffff8234e860 T wsemul_vt100_handle_dcs
 ffffffff8234f000 T vt100_initchartables
 ffffffff8234f200 T vt100_setnrc
 ffffffff82350000 T wsemul_vt100_translate
@@ -38964,19 +38972,19 @@ ffffffff8251b124 r gen9_edram_size_mb.sets
 ffffffff8251c000 r isomappings
 ffffffff8251c080 r unimappings
 ffffffff8251c230 r replacements
-ffffffff8251fb09 r cmd0646_9_tim_udma
-ffffffff82573092 r pp_r600_decoded_lanes
-ffffffff8258e2f5 r cmd680_setup_channel.udma_tbl
-ffffffff82595edc r apollo_udma33_tim
-ffffffff8259bf7f r substchar
-ffffffff8259e025 r apollo_udma100_tim
-ffffffff825c5870 r apollo_udma66_tim
-ffffffff825ccc98 r apollo_pio_rec
-ffffffff825dbf3b r cy_pio_rec
-ffffffff8260b236 r apollo_udma133_tim
-ffffffff82617cc8 R drm_ca
-ffffffff82617cf0 R drm_filtops
-ffffffff82617d20 R drmread_filtops
+ffffffff8251faff r cmd0646_9_tim_udma
+ffffffff825730aa r pp_r600_decoded_lanes
+ffffffff8258e30d r cmd680_setup_channel.udma_tbl
+ffffffff82595ef4 r apollo_udma33_tim
+ffffffff8259bf97 r substchar
+ffffffff8259e03d r apollo_udma100_tim
+ffffffff825c587a r apollo_udma66_tim
+ffffffff825ccca2 r apollo_pio_rec
+ffffffff825dbf45 r cy_pio_rec
+ffffffff8260b258 r apollo_udma133_tim
+ffffffff82617d28 R drm_ca
+ffffffff82617d50 R drm_filtops
+ffffffff82617d80 R drmread_filtops
 ffffffff82618000 r vga_emulops
 ffffffff82618048 R vga_stdscreen
 ffffffff82618078 R vga_stdscreen_mono
@@ -52244,9 +52252,9 @@ ffffffff8340c014 B prof_avg
 ffffffff8340c018 B prof_min
 ffffffff8340c01c B prof_mask
 ffffffff8340c020 B schedclock_period
-ffffffff8340c024 B statclock_min
-ffffffff8340c028 B statclock_mask
-ffffffff8340c02c B statclock_avg
+ffffffff8340c024 B statclock_avg
+ffffffff8340c028 B statclock_min
+ffffffff8340c02c B statclock_mask
 ffffffff8340d000 B file_pool
 ffffffff8340d1a8 B fdesc_pool
 ffffffff8340d350 B filehead