--- 7.1/2022-05-03T22:03:08Z/2022-04-28T00:00:00Z/nm-bsd-ot14.txt	Wed May  4 00:15:29 2022
+++ 7.1/2022-05-03T22:03:08Z/2022-04-28T05:11:48Z/nm-bsd-ot14.txt	Wed May  4 01:37:40 2022
@@ -20956,30 +20956,30 @@ ffffffff81a55c10 t __delayed_work_tick
 ffffffff81a56000 T intel_psr_irq_handler
 ffffffff81a56690 T intel_psr_init_dpcd
 ffffffff81a56940 T intel_psr_compute_config
-ffffffff81a570a0 T intel_psr_get_config
-ffffffff81a57260 T intel_psr_enable
-ffffffff81a57350 t intel_psr_enable_locked
-ffffffff81a57b90 T intel_psr_disable
-ffffffff81a57ca0 t intel_psr_disable_locked
-ffffffff81a57fe0 T intel_psr_pause
-ffffffff81a58190 t intel_psr_exit
-ffffffff81a584f0 T intel_psr_resume
-ffffffff81a58580 t intel_psr_activate
-ffffffff81a58c20 T intel_psr2_program_plane_sel_fetch
-ffffffff81a58df0 T intel_psr2_program_trans_man_trk_ctl
-ffffffff81a58e80 T intel_psr2_sel_fetch_update
-ffffffff81a59460 T intel_psr_update
-ffffffff81a59620 T intel_psr_wait_for_idle
-ffffffff81a59810 T intel_psr_debug_set
-ffffffff81a59b20 T intel_psr_invalidate
-ffffffff81a59ca0 T intel_psr_flush
-ffffffff81a59ff0 T intel_psr_init
-ffffffff81a5a170 t intel_psr_work
-ffffffff81a5a320 t tgl_dc3co_disable_work
-ffffffff81a5a370 T intel_psr_short_pulse
-ffffffff81a5a750 T intel_psr_enabled
-ffffffff81a5a7d0 t tgl_psr2_disable_dc3co
-ffffffff81a5a900 t __delayed_work_tick
+ffffffff81a57050 T intel_psr_get_config
+ffffffff81a57210 T intel_psr_enable
+ffffffff81a57300 t intel_psr_enable_locked
+ffffffff81a57b40 T intel_psr_disable
+ffffffff81a57c50 t intel_psr_disable_locked
+ffffffff81a57f90 T intel_psr_pause
+ffffffff81a58140 t intel_psr_exit
+ffffffff81a584a0 T intel_psr_resume
+ffffffff81a58530 t intel_psr_activate
+ffffffff81a58bd0 T intel_psr2_program_plane_sel_fetch
+ffffffff81a58da0 T intel_psr2_program_trans_man_trk_ctl
+ffffffff81a58e30 T intel_psr2_sel_fetch_update
+ffffffff81a59410 T intel_psr_update
+ffffffff81a595d0 T intel_psr_wait_for_idle
+ffffffff81a597c0 T intel_psr_debug_set
+ffffffff81a59ad0 T intel_psr_invalidate
+ffffffff81a59c50 T intel_psr_flush
+ffffffff81a59fa0 T intel_psr_init
+ffffffff81a5a120 t intel_psr_work
+ffffffff81a5a2d0 t tgl_dc3co_disable_work
+ffffffff81a5a320 T intel_psr_short_pulse
+ffffffff81a5a700 T intel_psr_enabled
+ffffffff81a5a780 t tgl_psr2_disable_dc3co
+ffffffff81a5a8b0 t __delayed_work_tick
 ffffffff81a5b000 T intel_lookup_range_min_qp
 ffffffff81a5b0b0 T intel_lookup_range_max_qp
 ffffffff81a5c000 T intel_init_quirks
@@ -36843,17 +36843,17 @@ ffffffff82396080 r unimappings
 ffffffff82396230 r replacements
 ffffffff82399aa2 r cmd0646_9_tim_udma
 ffffffff823e8473 r pp_r600_decoded_lanes
-ffffffff82401f96 r cmd680_setup_channel.udma_tbl
-ffffffff8240938d r apollo_udma33_tim
-ffffffff8240ece5 r substchar
-ffffffff82410cc6 r apollo_udma100_tim
-ffffffff824359a3 r apollo_udma66_tim
-ffffffff8243c727 r apollo_pio_rec
-ffffffff8244b059 r cy_pio_rec
-ffffffff82477ad3 r apollo_udma133_tim
-ffffffff82483ab8 R drm_ca
-ffffffff82483ae0 R drm_filtops
-ffffffff82483b10 R drmread_filtops
+ffffffff82401f5d r cmd680_setup_channel.udma_tbl
+ffffffff82409354 r apollo_udma33_tim
+ffffffff8240ecac r substchar
+ffffffff82410c8d r apollo_udma100_tim
+ffffffff8243596a r apollo_udma66_tim
+ffffffff8243c6ee r apollo_pio_rec
+ffffffff8244b020 r cy_pio_rec
+ffffffff82477a9a r apollo_udma133_tim
+ffffffff82483a80 R drm_ca
+ffffffff82483aa8 R drm_filtops
+ffffffff82483ad8 R drmread_filtops
 ffffffff82484000 r vga_emulops
 ffffffff82484048 R vga_stdscreen
 ffffffff82484078 R vga_stdscreen_mono