--- 2021-08-07T06:17:03Z/2021-08-04T00:00:00Z/nm-bsd-ot14.txt	Sat Aug  7 19:37:07 2021
+++ 2021-08-07T06:17:03Z/2021-08-05T00:00:00Z/nm-bsd-ot14.txt	Sat Aug  7 21:28:12 2021
@@ -26107,15 +26107,15 @@ ffffffff81d6fe80 t psp_v11_0_read_usbc_pd_fw
 ffffffff81d6ff20 t psp_v11_0_memory_training_send_msg
 ffffffff81d71000 T psp_v12_0_set_psp_funcs
 ffffffff81d71030 t psp_v12_0_init_microcode
-ffffffff81d71270 t psp_v12_0_bootloader_load_sysdrv
-ffffffff81d714e0 t psp_v12_0_bootloader_load_sos
-ffffffff81d71770 t psp_v12_0_ring_init
-ffffffff81d71ba0 t psp_v12_0_ring_create
-ffffffff81d71f70 t psp_v12_0_ring_stop
-ffffffff81d72150 t psp_v12_0_ring_destroy
-ffffffff81d721c0 t psp_v12_0_mode1_reset
-ffffffff81d722b0 t psp_v12_0_ring_get_wptr
-ffffffff81d722e0 t psp_v12_0_ring_set_wptr
+ffffffff81d71260 t psp_v12_0_bootloader_load_sysdrv
+ffffffff81d714d0 t psp_v12_0_bootloader_load_sos
+ffffffff81d71760 t psp_v12_0_ring_init
+ffffffff81d71b90 t psp_v12_0_ring_create
+ffffffff81d71f60 t psp_v12_0_ring_stop
+ffffffff81d72140 t psp_v12_0_ring_destroy
+ffffffff81d721b0 t psp_v12_0_mode1_reset
+ffffffff81d722a0 t psp_v12_0_ring_get_wptr
+ffffffff81d722d0 t psp_v12_0_ring_set_wptr
 ffffffff81d73000 T psp_v3_1_set_psp_funcs
 ffffffff81d73030 t psp_v3_1_init_microcode
 ffffffff81d730e0 t psp_v3_1_bootloader_load_sysdrv
@@ -27226,15 +27226,15 @@ ffffffff81e25000 T rv2_clk_mgr_construct
 ffffffff81e26000 T dentist_get_did_from_divider
 ffffffff81e260a0 T dcn20_update_clocks_update_dpp_dto
 ffffffff81e26160 T dcn20_update_clocks_update_dentist
-ffffffff81e26380 T dcn2_update_clocks
-ffffffff81e268e0 T dcn2_read_clocks_from_hw_dentist
-ffffffff81e269b0 T dcn2_update_clocks_fpga
-ffffffff81e26af0 T dcn2_init_clocks
-ffffffff81e26b70 T dcn2_enable_pme_wa
-ffffffff81e26bc0 T dcn2_get_clock
-ffffffff81e26c30 T dcn20_clk_mgr_construct
-ffffffff81e26d80 t dcn2_are_clock_states_equal
-ffffffff81e26df0 t dcn2_notify_link_rate_change
+ffffffff81e263c0 T dcn2_update_clocks
+ffffffff81e26920 T dcn2_read_clocks_from_hw_dentist
+ffffffff81e269f0 T dcn2_update_clocks_fpga
+ffffffff81e26b30 T dcn2_init_clocks
+ffffffff81e26bb0 T dcn2_enable_pme_wa
+ffffffff81e26c00 T dcn2_get_clock
+ffffffff81e26c70 T dcn20_clk_mgr_construct
+ffffffff81e26dc0 t dcn2_are_clock_states_equal
+ffffffff81e26e30 t dcn2_notify_link_rate_change
 ffffffff81e27000 T rn_get_active_display_cnt_wa
 ffffffff81e271c0 T rn_set_low_power_state
 ffffffff81e27200 T rn_update_clocks