--- 2021-08-02T18:57:01Z/2021-07-19T00:00:00Z/nm-bsd-ot14.txt	Wed Aug  4 15:54:42 2021
+++ 2021-08-02T18:57:01Z/2021-07-20T00:00:00Z/nm-bsd-ot14.txt	Wed Aug  4 17:47:58 2021
@@ -4821,10 +4821,10 @@ ffffffff812468e0 t pppoe_tls
 ffffffff812469a0 t pppoe_tlf
 ffffffff812469f0 t pppoe_timeout
 ffffffff81246e30 T pppoe_disc_input
-ffffffff81247760 T pppoe_data_input
-ffffffff81247900 t pppoe_send_padr
-ffffffff81247ba0 t pppoe_output
-ffffffff81247d10 t pppoe_send_padi
+ffffffff81247780 T pppoe_data_input
+ffffffff81247920 t pppoe_send_padr
+ffffffff81247bc0 t pppoe_output
+ffffffff81247d30 t pppoe_send_padi
 ffffffff81248000 T dtattach
 ffffffff81248070 T dtopen
 ffffffff81248220 T dtlookup
@@ -9529,9 +9529,9 @@ ffffffff81451d10 T tdb_reaper
 ffffffff81451d30 T tdb_init
 ffffffff81451d90 T ipsp_is_unspecified
 ffffffff81451df0 T ipsp_ids_insert
-ffffffff81451f40 T ipsp_ids_lookup
-ffffffff81451fd0 t ipsec_ids_tree_RBT_COMPARE
-ffffffff814520c0 t ipsec_ids_flows_RBT_COMPARE
+ffffffff81451f70 T ipsp_ids_lookup
+ffffffff81452000 t ipsec_ids_tree_RBT_COMPARE
+ffffffff814520f0 t ipsec_ids_flows_RBT_COMPARE
 ffffffff81453000 T spd_table_get
 ffffffff81453090 T spd_table_add
 ffffffff814531e0 T spd_table_walk
@@ -18198,42 +18198,42 @@ ffffffff8190b640 T drm_dp_downstream_is_tmds
 ffffffff8190b6b0 T drm_dp_send_real_edid_checksum
 ffffffff8190b840 T drm_dp_read_dpcd_caps
 ffffffff8190b9b0 T drm_dp_read_downstream_info
-ffffffff8190ba80 T drm_dp_downstream_max_dotclock
-ffffffff8190bad0 T drm_dp_downstream_max_tmds_clock
-ffffffff8190bb70 T drm_dp_downstream_min_tmds_clock
-ffffffff8190bbf0 T drm_dp_downstream_max_bpc
-ffffffff8190bc90 T drm_dp_downstream_420_passthrough
-ffffffff8190bcf0 T drm_dp_downstream_444_to_420_conversion
-ffffffff8190bd50 T drm_dp_downstream_mode
-ffffffff8190bdd0 T drm_dp_downstream_id
-ffffffff8190bdf0 T drm_dp_downstream_debug
-ffffffff8190be90 T drm_dp_subconnector_type
-ffffffff8190bef0 T drm_dp_set_subconnector_property
-ffffffff8190bf60 T drm_dp_read_sink_count_cap
-ffffffff8190bfb0 T drm_dp_read_sink_count
-ffffffff8190c010 T drm_dp_remote_aux_init
-ffffffff8190c040 t drm_dp_aux_crc_work
-ffffffff8190c160 T drm_dp_aux_init
-ffffffff8190c210 T drm_dp_aux_register
-ffffffff8190c2f0 T drm_dp_aux_unregister
-ffffffff8190c320 T drm_dp_psr_setup_time
-ffffffff8190c360 T drm_dp_start_crc
-ffffffff8190c400 T drm_dp_stop_crc
-ffffffff8190c490 T drm_dp_get_edid_quirks
-ffffffff8190c660 T drm_dp_read_desc
-ffffffff8190c810 T drm_dp_dsc_sink_max_slice_count
-ffffffff8190c8a0 T drm_dp_dsc_sink_line_buf_depth
-ffffffff8190c8e0 T drm_dp_dsc_sink_supported_input_bpcs
-ffffffff8190c950 T drm_dp_get_phy_test_pattern
-ffffffff8190ca50 T drm_dp_set_phy_test_pattern
-ffffffff8190cb70 T drm_dp_vsc_sdp_log
-ffffffff8190cea0 t drm_dp_aux_get_crc
-ffffffff8190cf70 t drm_dp_i2c_xfer
-ffffffff8190d1b0 t drm_dp_i2c_functionality
-ffffffff8190d1e0 t drm_dp_i2c_do_msg
-ffffffff8190d490 t lock_bus
-ffffffff8190d4b0 t trylock_bus
-ffffffff8190d500 t unlock_bus
+ffffffff8190ba90 T drm_dp_downstream_max_dotclock
+ffffffff8190bae0 T drm_dp_downstream_max_tmds_clock
+ffffffff8190bb80 T drm_dp_downstream_min_tmds_clock
+ffffffff8190bc00 T drm_dp_downstream_max_bpc
+ffffffff8190bca0 T drm_dp_downstream_420_passthrough
+ffffffff8190bd00 T drm_dp_downstream_444_to_420_conversion
+ffffffff8190bd60 T drm_dp_downstream_mode
+ffffffff8190bde0 T drm_dp_downstream_id
+ffffffff8190be00 T drm_dp_downstream_debug
+ffffffff8190bea0 T drm_dp_subconnector_type
+ffffffff8190bf00 T drm_dp_set_subconnector_property
+ffffffff8190bf70 T drm_dp_read_sink_count_cap
+ffffffff8190bfc0 T drm_dp_read_sink_count
+ffffffff8190c020 T drm_dp_remote_aux_init
+ffffffff8190c050 t drm_dp_aux_crc_work
+ffffffff8190c170 T drm_dp_aux_init
+ffffffff8190c220 T drm_dp_aux_register
+ffffffff8190c300 T drm_dp_aux_unregister
+ffffffff8190c330 T drm_dp_psr_setup_time
+ffffffff8190c370 T drm_dp_start_crc
+ffffffff8190c410 T drm_dp_stop_crc
+ffffffff8190c4a0 T drm_dp_get_edid_quirks
+ffffffff8190c670 T drm_dp_read_desc
+ffffffff8190c820 T drm_dp_dsc_sink_max_slice_count
+ffffffff8190c8b0 T drm_dp_dsc_sink_line_buf_depth
+ffffffff8190c8f0 T drm_dp_dsc_sink_supported_input_bpcs
+ffffffff8190c960 T drm_dp_get_phy_test_pattern
+ffffffff8190ca60 T drm_dp_set_phy_test_pattern
+ffffffff8190cb80 T drm_dp_vsc_sdp_log
+ffffffff8190ceb0 t drm_dp_aux_get_crc
+ffffffff8190cf80 t drm_dp_i2c_xfer
+ffffffff8190d1c0 t drm_dp_i2c_functionality
+ffffffff8190d1f0 t drm_dp_i2c_do_msg
+ffffffff8190d4a0 t lock_bus
+ffffffff8190d4c0 t trylock_bus
+ffffffff8190d510 t unlock_bus
 ffffffff8190e000 T drm_dp_encode_sideband_req
 ffffffff8190e420 T drm_dp_decode_sideband_req
 ffffffff8190e980 T drm_dp_dump_sideband_msg_req_body
@@ -19190,15 +19190,15 @@ ffffffff8197a000 T drm_sched_entity_init
 ffffffff8197a150 T drm_sched_entity_modify_sched
 ffffffff8197a1d0 T drm_sched_entity_is_ready
 ffffffff8197a210 T drm_sched_entity_flush
-ffffffff8197a520 T drm_sched_entity_fini
-ffffffff8197a750 T drm_sched_entity_destroy
-ffffffff8197a7a0 T drm_sched_entity_set_priority
-ffffffff8197a7e0 T drm_sched_entity_pop_job
-ffffffff8197a9e0 T drm_sched_entity_select_rq
-ffffffff8197aaa0 T drm_sched_entity_push_job
-ffffffff8197ab90 t drm_sched_entity_kill_jobs_cb
-ffffffff8197ac00 t drm_sched_entity_clear_dep
-ffffffff8197ac20 t drm_sched_entity_wakeup
+ffffffff8197a580 T drm_sched_entity_fini
+ffffffff8197a7f0 T drm_sched_entity_destroy
+ffffffff8197a840 T drm_sched_entity_set_priority
+ffffffff8197a880 T drm_sched_entity_pop_job
+ffffffff8197aa80 T drm_sched_entity_select_rq
+ffffffff8197ab40 T drm_sched_entity_push_job
+ffffffff8197ac30 t drm_sched_entity_kill_jobs_cb
+ffffffff8197aca0 t drm_sched_entity_clear_dep
+ffffffff8197acc0 t drm_sched_entity_wakeup
 ffffffff8197b000 T drm_sched_fence_slab_init
 ffffffff8197b060 T drm_sched_fence_slab_fini
 ffffffff8197b080 T drm_sched_fence_scheduled
@@ -19228,9 +19228,9 @@ ffffffff8197cbc0 T drm_sched_init
 ffffffff8197cdf0 t drm_sched_job_timedout
 ffffffff8197cef0 t drm_sched_main
 ffffffff8197d300 T drm_sched_fini
-ffffffff8197d380 t __delayed_work_tick
-ffffffff8197d3a0 t drm_sched_get_cleanup_job
-ffffffff8197d4d0 t drm_sched_select_entity
+ffffffff8197d520 t __delayed_work_tick
+ffffffff8197d540 t drm_sched_get_cleanup_job
+ffffffff8197d670 t drm_sched_select_entity
 ffffffff8197e000 t ch7017_init
 ffffffff8197e130 t ch7017_dpms
 ffffffff8197e370 t ch7017_mode_valid
@@ -19906,104 +19906,104 @@ ffffffff819ea5b0 T intel_write_dp_vsc_sdp
 ffffffff819ea740 T intel_dp_set_infoframes
 ffffffff819ea8a0 t intel_write_dp_sdp
 ffffffff819eabb0 T intel_read_dp_sdp
-ffffffff819eaea0 T intel_dp_process_phy_request
-ffffffff819eb5a0 T intel_dp_retrain_link
-ffffffff819ebad0 T intel_digital_port_connected
-ffffffff819ebb70 T intel_dp_encoder_flush_work
-ffffffff819ebc80 t edp_panel_vdd_off_sync
-ffffffff819ebf60 T intel_dp_encoder_suspend
-ffffffff819ec070 T intel_dp_encoder_reset
-ffffffff819ec2d0 t intel_dp_pps_init
-ffffffff819ec560 T intel_dp_hpd_pulse
-ffffffff819ecb00 T intel_dp_is_port_edp
-ffffffff819ecb50 T intel_edp_drrs_enable
-ffffffff819ecc40 T intel_edp_drrs_disable
-ffffffff819ecd60 T intel_edp_drrs_update
-ffffffff819ece60 T intel_edp_drrs_invalidate
-ffffffff819ecf80 t intel_dp_set_drrs_state
-ffffffff819ed1b0 T intel_edp_drrs_flush
-ffffffff819ed320 T intel_dp_init_connector
-ffffffff819ee4f0 t intel_dp_modeset_retry_work_fn
-ffffffff819ee570 T intel_dp_init
-ffffffff819ee9f0 t intel_dp_hotplug
-ffffffff819eeaf0 t intel_dp_get_hw_state
-ffffffff819eeba0 t intel_dp_get_config
-ffffffff819eede0 t chv_dp_pre_pll_enable
-ffffffff819eee10 t chv_pre_enable_dp
-ffffffff819eee60 t vlv_enable_dp
-ffffffff819eef20 t vlv_disable_dp
-ffffffff819ef0d0 t chv_post_disable_dp
-ffffffff819ef130 t chv_dp_post_pll_disable
-ffffffff819ef150 t vlv_dp_pre_pll_enable
-ffffffff819ef180 t vlv_pre_enable_dp
-ffffffff819ef1c0 t vlv_post_disable_dp
-ffffffff819ef1e0 t g4x_pre_enable_dp
-ffffffff819ef530 t g4x_enable_dp
-ffffffff819ef600 t g4x_disable_dp
-ffffffff819ef7b0 t g4x_post_disable_dp
-ffffffff819ef9c0 t cpt_set_link_train
-ffffffff819efa80 t g4x_set_link_train
-ffffffff819efb50 t chv_set_signal_levels
-ffffffff819efc30 t vlv_set_signal_levels
-ffffffff819efd00 t ivb_cpu_edp_set_signal_levels
-ffffffff819efdd0 t snb_cpu_edp_set_signal_levels
-ffffffff819efea0 t g4x_set_signal_levels
-ffffffff819eff70 t intel_dp_pre_empemph_max_3
-ffffffff819effa0 t intel_dp_voltage_max_3
-ffffffff819effd0 t intel_dp_pre_empemph_max_2
-ffffffff819f0000 t intel_dp_voltage_max_2
-ffffffff819f0030 t gm45_digital_port_connected
-ffffffff819f00c0 t g4x_digital_port_connected
-ffffffff819f0150 t ilk_digital_port_connected
-ffffffff819f01c0 t ibx_digital_port_connected
-ffffffff819f0230 T intel_dp_mst_suspend
-ffffffff819f02b0 T intel_dp_mst_resume
-ffffffff819f0350 t intel_dp_dsc_get_output_bpp
-ffffffff819f0490 t intel_dp_dsc_get_slice_count
-ffffffff819f05d0 t wait_panel_status
-ffffffff819f0860 t intel_pps_readout_hw_state
-ffffffff819f0a20 t intel_pps_get_registers
-ffffffff819f0bb0 t vlv_power_sequencer_pipe
-ffffffff819f1120 t intel_dp_init_panel_power_sequencer_registers
-ffffffff819f14b0 t vlv_steal_power_sequencer
-ffffffff819f15e0 t intel_dp_init_panel_power_sequencer
-ffffffff819f18d0 t vlv_detach_power_sequencer
-ffffffff819f1a30 t intel_dp_get_dpcd
-ffffffff819f1b90 t intel_dp_check_service_irq
-ffffffff819f2150 t intel_dp_set_common_rates
-ffffffff819f22c0 t intel_dp_force
-ffffffff819f2400 t intel_dp_connector_register
-ffffffff819f24a0 t intel_dp_connector_unregister
-ffffffff819f24f0 t intel_dp_set_edid
-ffffffff819f27d0 t intel_dp_get_modes
-ffffffff819f28e0 t intel_dp_detect
-ffffffff819f31c0 t intel_dp_mode_valid
-ffffffff819f3540 t intel_dp_connector_atomic_check
-ffffffff819f3800 t intel_dp_get_dsc_sink_cap
-ffffffff819f3980 t skl_aux_ctl_reg
-ffffffff819f3a00 t skl_aux_data_reg
-ffffffff819f3a80 t ilk_aux_ctl_reg
-ffffffff819f3b00 t ilk_aux_data_reg
-ffffffff819f3b80 t g4x_aux_ctl_reg
-ffffffff819f3c00 t g4x_aux_data_reg
-ffffffff819f3c80 t skl_get_aux_clock_divider
-ffffffff819f3cb0 t hsw_get_aux_clock_divider
-ffffffff819f3d40 t ilk_get_aux_clock_divider
-ffffffff819f3da0 t g4x_get_aux_clock_divider
-ffffffff819f3df0 t skl_get_aux_send_ctl
-ffffffff819f3e80 t g4x_get_aux_send_ctl
-ffffffff819f3ee0 t kasprintf
-ffffffff819f3fc0 t intel_dp_aux_transfer
-ffffffff819f4210 t intel_dp_aux_xfer
-ffffffff819f4de0 t edp_panel_vdd_work
-ffffffff819f4eb0 t edp_notify_handler
-ffffffff819f5040 t intel_edp_backlight_power
-ffffffff819f5240 t __delayed_work_tick
-ffffffff819f5260 t intel_edp_drrs_downclock_work
-ffffffff819f52f0 t intel_dp_encoder_destroy
-ffffffff819f5350 t intel_dp_prepare
-ffffffff819f5650 t intel_enable_dp
-ffffffff819f5b10 t intel_dp_link_down
+ffffffff819eae80 T intel_dp_process_phy_request
+ffffffff819eb580 T intel_dp_retrain_link
+ffffffff819ebab0 T intel_digital_port_connected
+ffffffff819ebb50 T intel_dp_encoder_flush_work
+ffffffff819ebc60 t edp_panel_vdd_off_sync
+ffffffff819ebf40 T intel_dp_encoder_suspend
+ffffffff819ec050 T intel_dp_encoder_reset
+ffffffff819ec2b0 t intel_dp_pps_init
+ffffffff819ec540 T intel_dp_hpd_pulse
+ffffffff819ecae0 T intel_dp_is_port_edp
+ffffffff819ecb30 T intel_edp_drrs_enable
+ffffffff819ecc20 T intel_edp_drrs_disable
+ffffffff819ecd40 T intel_edp_drrs_update
+ffffffff819ece40 T intel_edp_drrs_invalidate
+ffffffff819ecf60 t intel_dp_set_drrs_state
+ffffffff819ed190 T intel_edp_drrs_flush
+ffffffff819ed300 T intel_dp_init_connector
+ffffffff819ee4d0 t intel_dp_modeset_retry_work_fn
+ffffffff819ee550 T intel_dp_init
+ffffffff819ee9d0 t intel_dp_hotplug
+ffffffff819eead0 t intel_dp_get_hw_state
+ffffffff819eeb80 t intel_dp_get_config
+ffffffff819eedc0 t chv_dp_pre_pll_enable
+ffffffff819eedf0 t chv_pre_enable_dp
+ffffffff819eee40 t vlv_enable_dp
+ffffffff819eef00 t vlv_disable_dp
+ffffffff819ef0b0 t chv_post_disable_dp
+ffffffff819ef110 t chv_dp_post_pll_disable
+ffffffff819ef130 t vlv_dp_pre_pll_enable
+ffffffff819ef160 t vlv_pre_enable_dp
+ffffffff819ef1a0 t vlv_post_disable_dp
+ffffffff819ef1c0 t g4x_pre_enable_dp
+ffffffff819ef510 t g4x_enable_dp
+ffffffff819ef5e0 t g4x_disable_dp
+ffffffff819ef790 t g4x_post_disable_dp
+ffffffff819ef9a0 t cpt_set_link_train
+ffffffff819efa60 t g4x_set_link_train
+ffffffff819efb30 t chv_set_signal_levels
+ffffffff819efc10 t vlv_set_signal_levels
+ffffffff819efce0 t ivb_cpu_edp_set_signal_levels
+ffffffff819efdb0 t snb_cpu_edp_set_signal_levels
+ffffffff819efe80 t g4x_set_signal_levels
+ffffffff819eff50 t intel_dp_pre_empemph_max_3
+ffffffff819eff80 t intel_dp_voltage_max_3
+ffffffff819effb0 t intel_dp_pre_empemph_max_2
+ffffffff819effe0 t intel_dp_voltage_max_2
+ffffffff819f0010 t gm45_digital_port_connected
+ffffffff819f00a0 t g4x_digital_port_connected
+ffffffff819f0130 t ilk_digital_port_connected
+ffffffff819f01a0 t ibx_digital_port_connected
+ffffffff819f0210 T intel_dp_mst_suspend
+ffffffff819f0290 T intel_dp_mst_resume
+ffffffff819f0330 t intel_dp_dsc_get_output_bpp
+ffffffff819f0470 t intel_dp_dsc_get_slice_count
+ffffffff819f05b0 t wait_panel_status
+ffffffff819f0840 t intel_pps_readout_hw_state
+ffffffff819f0a00 t intel_pps_get_registers
+ffffffff819f0b90 t vlv_power_sequencer_pipe
+ffffffff819f1100 t intel_dp_init_panel_power_sequencer_registers
+ffffffff819f1490 t vlv_steal_power_sequencer
+ffffffff819f15c0 t intel_dp_init_panel_power_sequencer
+ffffffff819f18b0 t vlv_detach_power_sequencer
+ffffffff819f1a10 t intel_dp_get_dpcd
+ffffffff819f1b70 t intel_dp_check_service_irq
+ffffffff819f2130 t intel_dp_set_common_rates
+ffffffff819f22a0 t intel_dp_force
+ffffffff819f23e0 t intel_dp_connector_register
+ffffffff819f2480 t intel_dp_connector_unregister
+ffffffff819f24d0 t intel_dp_set_edid
+ffffffff819f27b0 t intel_dp_get_modes
+ffffffff819f28c0 t intel_dp_detect
+ffffffff819f31a0 t intel_dp_mode_valid
+ffffffff819f3520 t intel_dp_connector_atomic_check
+ffffffff819f37e0 t intel_dp_get_dsc_sink_cap
+ffffffff819f3960 t skl_aux_ctl_reg
+ffffffff819f39e0 t skl_aux_data_reg
+ffffffff819f3a60 t ilk_aux_ctl_reg
+ffffffff819f3ae0 t ilk_aux_data_reg
+ffffffff819f3b60 t g4x_aux_ctl_reg
+ffffffff819f3be0 t g4x_aux_data_reg
+ffffffff819f3c60 t skl_get_aux_clock_divider
+ffffffff819f3c90 t hsw_get_aux_clock_divider
+ffffffff819f3d20 t ilk_get_aux_clock_divider
+ffffffff819f3d80 t g4x_get_aux_clock_divider
+ffffffff819f3dd0 t skl_get_aux_send_ctl
+ffffffff819f3e60 t g4x_get_aux_send_ctl
+ffffffff819f3ec0 t kasprintf
+ffffffff819f3fa0 t intel_dp_aux_transfer
+ffffffff819f41f0 t intel_dp_aux_xfer
+ffffffff819f4dc0 t edp_panel_vdd_work
+ffffffff819f4e90 t edp_notify_handler
+ffffffff819f5020 t intel_edp_backlight_power
+ffffffff819f5220 t __delayed_work_tick
+ffffffff819f5240 t intel_edp_drrs_downclock_work
+ffffffff819f52d0 t intel_dp_encoder_destroy
+ffffffff819f5330 t intel_dp_prepare
+ffffffff819f5630 t intel_enable_dp
+ffffffff819f5af0 t intel_dp_link_down
 ffffffff819f6000 T intel_dp_aux_init_backlight_funcs
 ffffffff819f6160 t intel_dp_aux_setup_backlight
 ffffffff819f64e0 t intel_dp_aux_enable_backlight
@@ -23306,14 +23306,14 @@ ffffffff81bf4f50 T radeon_modeset_fini
 ffffffff81bf50a0 T radeon_crtc_scaling_mode_fixup
 ffffffff81bf53f0 T radeon_get_crtc_scanout_position
 ffffffff81bf5450 t radeon_user_framebuffer_create
-ffffffff81bf55e0 t radeon_crtc_gamma_set
-ffffffff81bf5620 t radeon_crtc_destroy
-ffffffff81bf5660 t radeon_crtc_set_config
-ffffffff81bf5730 t radeon_crtc_page_flip_target
-ffffffff81bf5b90 t radeon_flip_work_func
-ffffffff81bf5db0 t radeon_unpin_work_func
-ffffffff81bf5e40 t radeon_bo_reserve
-ffffffff81bf5fc0 t radeon_bo_unreserve
+ffffffff81bf55f0 t radeon_crtc_gamma_set
+ffffffff81bf5630 t radeon_crtc_destroy
+ffffffff81bf5670 t radeon_crtc_set_config
+ffffffff81bf5740 t radeon_crtc_page_flip_target
+ffffffff81bf5ba0 t radeon_flip_work_func
+ffffffff81bf5dc0 t radeon_unpin_work_func
+ffffffff81bf5e50 t radeon_bo_reserve
+ffffffff81bf5fd0 t radeon_bo_unreserve
 ffffffff81bf7000 T radeon_dp_aux_transfer_native
 ffffffff81bf8000 T radeon_dp_mst_prepare_pll
 ffffffff81bf8150 T radeon_dp_mst_init
@@ -24563,10 +24563,10 @@ ffffffff81ca9d80 T amdgpu_i2c_router_select_cd_port
 ffffffff81caa000 T amdgpu_ib_get
 ffffffff81caa0f0 T amdgpu_ib_free
 ffffffff81caa100 T amdgpu_ib_schedule
-ffffffff81caa710 T amdgpu_ib_pool_init
-ffffffff81caa830 T amdgpu_ib_pool_fini
-ffffffff81caa8a0 T amdgpu_ib_ring_tests
-ffffffff81caaa60 T amdgpu_debugfs_sa_init
+ffffffff81caa6d0 T amdgpu_ib_pool_init
+ffffffff81caa7f0 T amdgpu_ib_pool_fini
+ffffffff81caa860 T amdgpu_ib_ring_tests
+ffffffff81caaa20 T amdgpu_debugfs_sa_init
 ffffffff81cab000 T amdgpu_pasid_alloc
 ffffffff81cab090 T amdgpu_pasid_free
 ffffffff81cab0b0 T amdgpu_pasid_free_delayed
@@ -26785,59 +26785,60 @@ ffffffff81dd16c0 t dm_dmub_hw_init
 ffffffff81dd1a30 t amdgpu_dm_fini
 ffffffff81dd1b90 t emulated_link_detect
 ffffffff81dd1c80 t amdgpu_dm_atomic_check
-ffffffff81dd2bb0 t amdgpu_dm_atomic_commit
-ffffffff81dd2bc0 t dm_update_plane_state
-ffffffff81dd3430 t dm_update_crtc_state
-ffffffff81dd3af0 t dm_atomic_destroy_state
-ffffffff81dd3b30 t amdgpu_bo_reserve
-ffffffff81dd3cb0 t amdgpu_bo_unreserve
-ffffffff81dd3d80 t fill_dc_plane_info_and_addr
-ffffffff81dd40d0 t fill_plane_buffer_attributes
-ffffffff81dd4580 t fill_hdr_info_packet
-ffffffff81dd46e0 t update_stream_scaling_settings
-ffffffff81dd4820 t amdgpu_dm_atomic_commit_tail
-ffffffff81dd6a70 t handle_cursor_update
-ffffffff81dd6d20 t dm_atomic_duplicate_state
-ffffffff81dd6dc0 t amdgpu_dm_plane_init
-ffffffff81dd7030 t dm_drm_plane_reset
-ffffffff81dd70c0 t dm_drm_plane_duplicate_state
-ffffffff81dd7170 t dm_drm_plane_destroy_state
-ffffffff81dd71b0 t dm_plane_helper_prepare_fb
-ffffffff81dd7410 t dm_plane_helper_cleanup_fb
-ffffffff81dd7490 t dm_plane_atomic_check
-ffffffff81dd75d0 t dm_plane_atomic_async_check
-ffffffff81dd7610 t dm_plane_atomic_async_update
-ffffffff81dd76c0 t dm_crtc_reset_state
-ffffffff81dd7760 t amdgpu_dm_crtc_destroy
-ffffffff81dd7790 t dm_crtc_duplicate_state
-ffffffff81dd7920 t dm_crtc_destroy_state
-ffffffff81dd7960 t dm_enable_vblank
-ffffffff81dd7a30 t dm_disable_vblank
-ffffffff81dd7ae0 t dm_crtc_helper_mode_fixup
-ffffffff81dd7b10 t dm_crtc_helper_disable
-ffffffff81dd7b40 t dm_crtc_helper_atomic_check
-ffffffff81dd7cb0 t amdgpu_dm_encoder_destroy
-ffffffff81dd7ce0 t amdgpu_dm_i2c_xfer
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+ffffffff81dd8820 t dm_crtc_high_irq
+ffffffff81dd89f0 t dm_vupdate_high_irq
+ffffffff81dd8b60 t dm_pflip_high_irq
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+ffffffff81dd8fa0 t handle_hpd_rx_irq
+ffffffff81dd9250 t dm_gpureset_toggle_interrupts
+ffffffff81dd9530 t s3_handle_mst
+ffffffff81dd9620 t fill_stream_properties_from_drm_display_mode
 ffffffff81dda000 T amdgpu_dm_init_color_mod
-ffffffff81dda010 T amdgpu_dm_update_crtc_color_mgmt
-ffffffff81dda5c0 T amdgpu_dm_update_plane_color_mgmt
+ffffffff81dda010 T amdgpu_dm_verify_lut_sizes
+ffffffff81dda0d0 T amdgpu_dm_update_crtc_color_mgmt
+ffffffff81dda690 T amdgpu_dm_update_plane_color_mgmt
 ffffffff81ddb000 T dm_helpers_parse_edid_caps
 ffffffff81ddb3e0 T dm_helpers_dp_update_branch_info
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@@ -27407,36 +27408,36 @@ ffffffff81e3cad0 T dp_get_panel_mode
 ffffffff81e3cb60 T dp_set_panel_mode
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-ffffffff81e3d0c0 T dp_verify_link_cap
-ffffffff81e3d570 t hpd_rx_irq_check_link_loss_status
-ffffffff81e3d660 T dp_verify_link_cap_with_retries
-ffffffff81e3d7f0 T dp_verify_mst_link_cap
-ffffffff81e3d940 T dp_validate_mode_timing
-ffffffff81e3d9d0 T decide_link_settings
-ffffffff81e3dc60 T dc_link_handle_hpd_rx_irq
-ffffffff81e3e960 T is_mst_supported
-ffffffff81e3ea00 T is_dp_active_dongle
-ffffffff81e3ea30 T dp_overwrite_extended_receiver_cap
-ffffffff81e3eb20 t get_active_converter_info
-ffffffff81e3ed50 T detect_dp_sink_caps
-ffffffff81e3ed60 t retrieve_link_cap
-ffffffff81e3f5c0 T linkRateInKHzToLinkRateMultiplier
-ffffffff81e3f680 T detect_edp_sink_caps
-ffffffff81e3f830 T dc_link_set_default_brightness_aux
-ffffffff81e3f930 T dc_link_dp_enable_hpd
-ffffffff81e3f970 T dc_link_dp_disable_hpd
-ffffffff81e3f9c0 T dc_link_dp_set_test_pattern
-ffffffff81e3fff0 t set_crtc_test_pattern
-ffffffff81e40430 T dp_enable_mst_on_sink
-ffffffff81e404b0 T dp_set_fec_enable
-ffffffff81e405a0 T dpcd_set_source_specific_data
-ffffffff81e40640 T dc_link_set_backlight_level_nits
-ffffffff81e406e0 T dc_link_get_backlight_level_nits
-ffffffff81e40770 T dc_link_backlight_enable_aux
-ffffffff81e407d0 T dc_link_read_default_bl_aux
-ffffffff81e40830 t dpcd_set_lt_pattern_and_lane_settings
-ffffffff81e40a20 t get_lane_status_and_drive_settings
+ffffffff81e3cff0 T dc_link_dp_sync_lt_end
+ffffffff81e3d0e0 T dp_verify_link_cap
+ffffffff81e3d590 t hpd_rx_irq_check_link_loss_status
+ffffffff81e3d680 T dp_verify_link_cap_with_retries
+ffffffff81e3d810 T dp_verify_mst_link_cap
+ffffffff81e3d960 T dp_validate_mode_timing
+ffffffff81e3d9f0 T decide_link_settings
+ffffffff81e3dc90 T dc_link_handle_hpd_rx_irq
+ffffffff81e3e990 T is_mst_supported
+ffffffff81e3ea30 T is_dp_active_dongle
+ffffffff81e3ea60 T dp_overwrite_extended_receiver_cap
+ffffffff81e3eb50 t get_active_converter_info
+ffffffff81e3ed80 T detect_dp_sink_caps
+ffffffff81e3ed90 t retrieve_link_cap
+ffffffff81e3f5f0 T linkRateInKHzToLinkRateMultiplier
+ffffffff81e3f6b0 T detect_edp_sink_caps
+ffffffff81e3f860 T dc_link_set_default_brightness_aux
+ffffffff81e3f960 T dc_link_dp_enable_hpd
+ffffffff81e3f9a0 T dc_link_dp_disable_hpd
+ffffffff81e3f9f0 T dc_link_dp_set_test_pattern
+ffffffff81e40020 t set_crtc_test_pattern
+ffffffff81e40460 T dp_enable_mst_on_sink
+ffffffff81e404e0 T dp_set_fec_enable
+ffffffff81e405d0 T dpcd_set_source_specific_data
+ffffffff81e40670 T dc_link_set_backlight_level_nits
+ffffffff81e40710 T dc_link_get_backlight_level_nits
+ffffffff81e407a0 T dc_link_backlight_enable_aux
+ffffffff81e40800 T dc_link_read_default_bl_aux
+ffffffff81e40860 t dpcd_set_lt_pattern_and_lane_settings
+ffffffff81e40a50 t get_lane_status_and_drive_settings
 ffffffff81e41000 T core_link_read_dpcd
 ffffffff81e41060 T core_link_write_dpcd
 ffffffff81e410c0 T dp_receiver_power_ctrl
@@ -28121,11 +28122,11 @@ ffffffff81e9f000 T dpp1_dscl_calc_lb_num_partitions
 ffffffff81e9f1e0 T dpp1_dscl_is_lb_conf_valid
 ffffffff81e9f220 T dpp1_dscl_set_scaler_auto_scale
 ffffffff81e9f6f0 t dpp1_dscl_find_lb_memory_config
-ffffffff81e9f9e0 t dpp1_dscl_set_lb
-ffffffff81e9fc60 t dpp1_dscl_set_scl_filter
-ffffffff81ea0060 T dpp1_dscl_set_scaler_manual_scale
-ffffffff81ea0a10 t dpp1_dscl_get_filter_coeffs_64p
-ffffffff81ea0ae0 t dpp1_dscl_set_scaler_filter
+ffffffff81e9fa00 t dpp1_dscl_set_lb
+ffffffff81e9fc80 t dpp1_dscl_set_scl_filter
+ffffffff81ea0080 T dpp1_dscl_set_scaler_manual_scale
+ffffffff81ea0a30 t dpp1_dscl_get_filter_coeffs_64p
+ffffffff81ea0b00 t dpp1_dscl_set_scaler_filter
 ffffffff81ea1000 T hubbub1_wm_read_state
 ffffffff81ea1360 T hubbub1_allow_self_refresh_control
 ffffffff81ea13e0 T hubbub1_is_allow_self_refresh_enabled
@@ -28906,20 +28907,20 @@ ffffffff81f5cd40 t get_surf_rq_param
 ffffffff81f5d680 t calculate_ttu_cursor
 ffffffff81f5e000 T dml30_recalculate
 ffffffff81f5e600 t DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
-ffffffff81f64cd0 T dml30_CalculateWriteBackDISPCLK
-ffffffff81f64e50 T dml30_ModeSupportAndSystemConfigurationFull
-ffffffff81f6d4a0 t CalculateBytePerPixelAnd256BBlockSizes
-ffffffff81f6d720 t CalculateSwathAndDETConfiguration
-ffffffff81f6ddf0 t TruncToValidBPP
-ffffffff81f6e090 t dscceComputeDelay
-ffffffff81f6e230 t CalculateVMAndRowBytes
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-ffffffff81f6ecd0 t CalculateDCFCLKDeepSleep
-ffffffff81f6f000 t CalculatePrefetchSchedule
-ffffffff81f704f0 t CalculateFlipSchedule
-ffffffff81f709e0 t CalculateWatermarksAndDRAMSpeedChangeSupport
-ffffffff81f717f0 t CalculateSwathWidth
+ffffffff81f64ce0 T dml30_CalculateWriteBackDISPCLK
+ffffffff81f64e60 T dml30_ModeSupportAndSystemConfigurationFull
+ffffffff81f6d420 t CalculateBytePerPixelAnd256BBlockSizes
+ffffffff81f6d6a0 t CalculateSwathAndDETConfiguration
+ffffffff81f6dd70 t TruncToValidBPP
+ffffffff81f6e010 t dscceComputeDelay
+ffffffff81f6e1b0 t CalculateVMAndRowBytes
+ffffffff81f6e800 t CalculatePrefetchSourceLines
+ffffffff81f6e9c0 t CalculateUrgentBurstFactor
+ffffffff81f6ec50 t CalculateDCFCLKDeepSleep
+ffffffff81f6ef80 t CalculatePrefetchSchedule
+ffffffff81f70470 t CalculateFlipSchedule
+ffffffff81f70960 t CalculateWatermarksAndDRAMSpeedChangeSupport
+ffffffff81f71770 t CalculateSwathWidth
 ffffffff81f72000 T dml30_rq_dlg_get_rq_reg
 ffffffff81f72620 t dml_rq_dlg_get_rq_params
 ffffffff81f72920 T dml30_rq_dlg_get_dlg_reg
@@ -35267,16 +35268,16 @@ ffffffff82283080 r unimappings
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-ffffffff82358191 r apollo_udma133_tim
-ffffffff82363598 R drm_filtops
-ffffffff823635c8 R drmread_filtops
+ffffffff822e8b9b r cmd680_setup_channel.udma_tbl
+ffffffff822efa53 r apollo_udma33_tim
+ffffffff822f4c7e r substchar
+ffffffff822f6c0b r apollo_udma100_tim
+ffffffff82319e33 r apollo_udma66_tim
+ffffffff82320792 r apollo_pio_rec
+ffffffff8232e149 r cy_pio_rec
+ffffffff8235820a r apollo_udma133_tim
+ffffffff82363610 R drm_filtops
+ffffffff82363640 R drmread_filtops
 ffffffff82364000 r vga_emulops
 ffffffff82364048 R vga_stdscreen
 ffffffff82364078 R vga_stdscreen_mono
@@ -42345,18 +42346,17 @@ ffffffff82ae8010 r __retguard_430
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 ffffffff82ae9000 r __retguard_2889
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@@ -42879,8 +42879,9 @@ ffffffff82b2c168 r __retguard_2635
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