--- 2021-08-01T20:16:54Z/2021-07-29T03:09:17Z/nm-bsd-ot14.txt	Sun Aug  1 23:46:20 2021
+++ 2021-08-01T20:16:54Z/2021-07-29T03:12:14Z/nm-bsd-ot14.txt	Mon Aug  2 01:05:56 2021
@@ -25381,57 +25381,57 @@ ffffffff81d17f40 t gfx_v10_0_ring_get_wptr_gfx
 ffffffff81d17fd0 t gfx_v10_0_ring_set_wptr_gfx
 ffffffff81d18060 t gfx_v10_0_ring_emit_ib_gfx
 ffffffff81d186d0 t gfx_v10_0_ring_emit_fence
-ffffffff81d18a80 t gfx_v10_0_ring_emit_pipeline_sync
-ffffffff81d18ae0 t gfx_v10_0_ring_emit_vm_flush
-ffffffff81d18bf0 t gfx_v10_0_ring_emit_hdp_flush
-ffffffff81d18cc0 t gfx_v10_0_ring_emit_gds_switch
-ffffffff81d18da0 t gfx_v10_0_ring_emit_init_cond_exec
-ffffffff81d18fd0 t gfx_v10_0_ring_emit_patch_cond_exec
-ffffffff81d19090 t gfx_v10_0_ring_emit_sb
-ffffffff81d19170 t gfx_v10_0_ring_emit_cntxcntl
-ffffffff81d19620 t gfx_v10_0_ring_emit_frame_cntl
-ffffffff81d19730 t gfx_v10_0_ring_soft_recovery
-ffffffff81d19760 t gfx_v10_0_ring_preempt_ib
-ffffffff81d198d0 t gfx_v10_0_emit_mem_sync
-ffffffff81d19c10 t gfx_v10_0_write_data_to_reg
-ffffffff81d19e20 t gfx_v10_0_set_eop_interrupt_state
-ffffffff81d19f80 t gfx_v10_0_eop_irq
-ffffffff81d1a0a0 t gfx_v10_0_kiq_set_interrupt_state
-ffffffff81d1a1d0 t gfx_v10_0_kiq_irq
-ffffffff81d1a250 t gfx_v10_0_set_priv_reg_fault_state
-ffffffff81d1a2e0 t gfx_v10_0_priv_reg_irq
-ffffffff81d1a340 t gfx_v10_0_handle_priv_fault
-ffffffff81d1a4b0 t gfx_v10_0_set_priv_inst_fault_state
-ffffffff81d1a540 t gfx_v10_0_priv_inst_irq
-ffffffff81d1a5a0 t gfx_v10_0_is_rlc_enabled
-ffffffff81d1a5f0 t gfx_v10_0_set_safe_mode
-ffffffff81d1a720 t gfx_v10_0_unset_safe_mode
-ffffffff81d1a760 t gfx_v10_0_rlc_init
-ffffffff81d1a7d0 t gfx_v10_0_get_csb_size
-ffffffff81d1a820 t gfx_v10_0_get_csb_buffer
-ffffffff81d1a9a0 t gfx_v10_0_rlc_resume
-ffffffff81d1b0f0 t gfx_v10_0_rlc_reset
-ffffffff81d1b1a0 t gfx_v10_0_rlc_start
-ffffffff81d1b250 t gfx_v10_0_update_spm_vmid
-ffffffff81d1b2c0 t gfx_v10_0_wait_for_rlc_autoload_complete
-ffffffff81d1b850 t gfx_v10_0_init_csb
-ffffffff81d1bbd0 t gfx_v10_rlcg_wreg
-ffffffff81d1bd20 t gfx_v10_0_is_rlcg_access_range
-ffffffff81d1bd50 t amdgpu_bo_unreserve
-ffffffff81d1be20 t gfx_v10_0_get_gpu_clock_counter
-ffffffff81d1bed0 t gfx_v10_0_select_se_sh
-ffffffff81d1bf30 t gfx_v10_0_read_wave_data
-ffffffff81d1c430 t gfx_v10_0_read_wave_vgprs
-ffffffff81d1c4f0 t gfx_v10_0_read_wave_sgprs
-ffffffff81d1c5e0 t gfx_v10_0_select_me_pipe_q
-ffffffff81d1c600 t gfx_v10_0_init_spm_golden_registers
-ffffffff81d1c670 t gfx_v10_0_cp_gfx_enable
-ffffffff81d1c870 t amdgpu_bo_reserve
-ffffffff81d1c9f0 t gfx_v10_0_kiq_init_register
-ffffffff81d1cec0 t gfx_v10_0_compute_mqd_init
-ffffffff81d1d210 t gfx_v10_0_cp_gfx_set_doorbell
-ffffffff81d1d2e0 t gfx_v10_0_cp_gfx_start
-ffffffff81d1dc20 t gfx_v10_0_update_medium_grain_clock_gating
+ffffffff81d18a90 t gfx_v10_0_ring_emit_pipeline_sync
+ffffffff81d18af0 t gfx_v10_0_ring_emit_vm_flush
+ffffffff81d18c00 t gfx_v10_0_ring_emit_hdp_flush
+ffffffff81d18cd0 t gfx_v10_0_ring_emit_gds_switch
+ffffffff81d18db0 t gfx_v10_0_ring_emit_init_cond_exec
+ffffffff81d18fe0 t gfx_v10_0_ring_emit_patch_cond_exec
+ffffffff81d190a0 t gfx_v10_0_ring_emit_sb
+ffffffff81d19180 t gfx_v10_0_ring_emit_cntxcntl
+ffffffff81d19630 t gfx_v10_0_ring_emit_frame_cntl
+ffffffff81d19740 t gfx_v10_0_ring_soft_recovery
+ffffffff81d19770 t gfx_v10_0_ring_preempt_ib
+ffffffff81d198e0 t gfx_v10_0_emit_mem_sync
+ffffffff81d19c20 t gfx_v10_0_write_data_to_reg
+ffffffff81d19e30 t gfx_v10_0_set_eop_interrupt_state
+ffffffff81d19f90 t gfx_v10_0_eop_irq
+ffffffff81d1a0b0 t gfx_v10_0_kiq_set_interrupt_state
+ffffffff81d1a1e0 t gfx_v10_0_kiq_irq
+ffffffff81d1a260 t gfx_v10_0_set_priv_reg_fault_state
+ffffffff81d1a2f0 t gfx_v10_0_priv_reg_irq
+ffffffff81d1a350 t gfx_v10_0_handle_priv_fault
+ffffffff81d1a4c0 t gfx_v10_0_set_priv_inst_fault_state
+ffffffff81d1a550 t gfx_v10_0_priv_inst_irq
+ffffffff81d1a5b0 t gfx_v10_0_is_rlc_enabled
+ffffffff81d1a600 t gfx_v10_0_set_safe_mode
+ffffffff81d1a730 t gfx_v10_0_unset_safe_mode
+ffffffff81d1a770 t gfx_v10_0_rlc_init
+ffffffff81d1a7e0 t gfx_v10_0_get_csb_size
+ffffffff81d1a830 t gfx_v10_0_get_csb_buffer
+ffffffff81d1a9b0 t gfx_v10_0_rlc_resume
+ffffffff81d1b100 t gfx_v10_0_rlc_reset
+ffffffff81d1b1b0 t gfx_v10_0_rlc_start
+ffffffff81d1b260 t gfx_v10_0_update_spm_vmid
+ffffffff81d1b2d0 t gfx_v10_0_wait_for_rlc_autoload_complete
+ffffffff81d1b860 t gfx_v10_0_init_csb
+ffffffff81d1bbe0 t gfx_v10_rlcg_wreg
+ffffffff81d1bd30 t gfx_v10_0_is_rlcg_access_range
+ffffffff81d1bd60 t amdgpu_bo_unreserve
+ffffffff81d1be30 t gfx_v10_0_get_gpu_clock_counter
+ffffffff81d1bee0 t gfx_v10_0_select_se_sh
+ffffffff81d1bf40 t gfx_v10_0_read_wave_data
+ffffffff81d1c440 t gfx_v10_0_read_wave_vgprs
+ffffffff81d1c500 t gfx_v10_0_read_wave_sgprs
+ffffffff81d1c5f0 t gfx_v10_0_select_me_pipe_q
+ffffffff81d1c610 t gfx_v10_0_init_spm_golden_registers
+ffffffff81d1c680 t gfx_v10_0_cp_gfx_enable
+ffffffff81d1c880 t amdgpu_bo_reserve
+ffffffff81d1ca00 t gfx_v10_0_kiq_init_register
+ffffffff81d1ced0 t gfx_v10_0_compute_mqd_init
+ffffffff81d1d220 t gfx_v10_0_cp_gfx_set_doorbell
+ffffffff81d1d2f0 t gfx_v10_0_cp_gfx_start
+ffffffff81d1dc30 t gfx_v10_0_update_medium_grain_clock_gating
 ffffffff81d1e000 t gfx_v8_0_early_init
 ffffffff81d1e1e0 t gfx_v8_0_late_init
 ffffffff81d1e8d0 t gfx_v8_0_sw_init
@@ -37894,8 +37894,8 @@ ffffffff82746ba0 r golden_settings_gc_10_1_2
 ffffffff82746ba0 r golden_settings_gc_10_1_nv14
 ffffffff82746f90 r golden_settings_gc_10_1_2_nv12
 ffffffff82746f90 r golden_settings_gc_10_3
-ffffffff82747350 r golden_settings_gc_10_3_2
-ffffffff82747350 r golden_settings_gc_10_3_sienna_cichlid
+ffffffff82747368 r golden_settings_gc_10_3_sienna_cichlid
+ffffffff82747370 r golden_settings_gc_10_3_2
 ffffffff82748000 r gfx_v8_0_ip_funcs
 ffffffff827480a0 R gfx_v8_0_ip_block
 ffffffff827480b8 R gfx_v8_1_ip_block