--- 2020-11-15T23:05:31Z/2020-06-09T00:00:00Z/nm-bsd-ot14.txt	Wed Nov 18 11:48:53 2020
+++ 2020-11-15T23:05:31Z/2020-06-10T00:00:00Z/nm-bsd-ot14.txt	Wed Nov 18 13:37:12 2020
@@ -14434,58 +14434,58 @@ ffffffff81726f10 T em_allocate_pci_resources
 ffffffff81727320 T em_allocate_desc_rings
 ffffffff81727430 T em_hardware_init
 ffffffff817276e0 T em_update_stats_counters
-ffffffff81727a40 T em_start
-ffffffff81727d40 T em_encap
-ffffffff81728190 T em_82547_move_tail_locked
-ffffffff817283b0 T em_82547_update_fifo_head
-ffffffff81728400 T em_ioctl
-ffffffff81728610 T em_init
-ffffffff81728970 T em_disable_intr
-ffffffff81728a70 T em_iff
-ffffffff81728d90 T em_initialize_receive_unit
-ffffffff817293d0 T em_enable_intr
-ffffffff81729530 T em_watchdog
-ffffffff817296e0 T em_enable_hw_vlans
-ffffffff81729770 T em_setup_transmit_structures
-ffffffff81729960 T em_initialize_transmit_unit
-ffffffff81729ef0 T em_setup_receive_structures
-ffffffff8172a020 T em_setup_queues_msix
-ffffffff8172a6d0 T em_intr
-ffffffff8172a870 T em_txeof
-ffffffff8172aa40 T em_rxeof
-ffffffff8172af20 T em_rxrefill
-ffffffff8172b020 T em_media_status
-ffffffff8172b250 T em_flowstatus
-ffffffff8172b360 T em_media_change
-ffffffff8172b4c0 T em_transmit_checksum_setup
-ffffffff8172b5a0 T em_fill_descriptors
-ffffffff8172b620 T em_82547_fifo_workaround
-ffffffff8172b680 T em_82547_tx_fifo_reset
-ffffffff8172bad0 T em_pci_clear_mwi
-ffffffff8172bb00 T em_pci_set_mwi
-ffffffff8172bb30 T em_smartspeed
-ffffffff8172bd20 T em_flush_desc_rings
-ffffffff8172be50 T em_free_transmit_structures
-ffffffff8172c030 T em_free_receive_structures
-ffffffff8172c220 T em_legacy_irq_quirk_spt
-ffffffff8172c300 T em_allocate_msix
-ffffffff8172c510 T em_allocate_legacy
-ffffffff8172c630 T em_dma_free
-ffffffff8172c6a0 T em_disable_aspm
-ffffffff8172c770 T em_dma_malloc
-ffffffff8172c910 T em_allocate_transmit_structures
-ffffffff8172c9f0 T em_get_buf
-ffffffff8172cb50 T em_allocate_receive_structures
-ffffffff8172cd10 T em_rxfill
-ffffffff8172ce60 T em_receive_checksum
-ffffffff8172ced0 T em_write_pci_cfg
-ffffffff8172cf40 T em_read_pci_cfg
-ffffffff8172cfb0 T em_read_pcie_cap_reg
-ffffffff8172cfe0 T em_flush_tx_ring
-ffffffff8172d160 T em_flush_rx_ring
-ffffffff8172d320 T em_queue_intr_msix
-ffffffff8172d470 T em_link_intr_msix
-ffffffff8172d590 T em_enable_queue_intr_msix
+ffffffff81727a60 T em_start
+ffffffff81727d60 T em_encap
+ffffffff817281b0 T em_82547_move_tail_locked
+ffffffff817283d0 T em_82547_update_fifo_head
+ffffffff81728420 T em_ioctl
+ffffffff81728630 T em_init
+ffffffff81728990 T em_disable_intr
+ffffffff81728a90 T em_iff
+ffffffff81728db0 T em_initialize_receive_unit
+ffffffff817294c0 T em_enable_intr
+ffffffff81729620 T em_watchdog
+ffffffff817297d0 T em_enable_hw_vlans
+ffffffff81729860 T em_setup_transmit_structures
+ffffffff81729a50 T em_initialize_transmit_unit
+ffffffff81729fe0 T em_setup_receive_structures
+ffffffff8172a120 T em_setup_queues_msix
+ffffffff8172a7d0 T em_intr
+ffffffff8172a970 T em_txeof
+ffffffff8172ab40 T em_rxeof
+ffffffff8172b020 T em_rxrefill
+ffffffff8172b120 T em_media_status
+ffffffff8172b350 T em_flowstatus
+ffffffff8172b460 T em_media_change
+ffffffff8172b5c0 T em_transmit_checksum_setup
+ffffffff8172b6a0 T em_fill_descriptors
+ffffffff8172b720 T em_82547_fifo_workaround
+ffffffff8172b780 T em_82547_tx_fifo_reset
+ffffffff8172bbd0 T em_pci_clear_mwi
+ffffffff8172bc00 T em_pci_set_mwi
+ffffffff8172bc30 T em_smartspeed
+ffffffff8172be20 T em_flush_desc_rings
+ffffffff8172bf50 T em_free_transmit_structures
+ffffffff8172c130 T em_free_receive_structures
+ffffffff8172c320 T em_legacy_irq_quirk_spt
+ffffffff8172c400 T em_allocate_msix
+ffffffff8172c610 T em_allocate_legacy
+ffffffff8172c730 T em_dma_free
+ffffffff8172c7a0 T em_disable_aspm
+ffffffff8172c870 T em_dma_malloc
+ffffffff8172ca10 T em_allocate_transmit_structures
+ffffffff8172caf0 T em_get_buf
+ffffffff8172cc50 T em_allocate_receive_structures
+ffffffff8172ce10 T em_rxfill
+ffffffff8172cf60 T em_receive_checksum
+ffffffff8172cfd0 T em_write_pci_cfg
+ffffffff8172d040 T em_read_pci_cfg
+ffffffff8172d0b0 T em_read_pcie_cap_reg
+ffffffff8172d0e0 T em_flush_tx_ring
+ffffffff8172d250 T em_flush_rx_ring
+ffffffff8172d410 T em_queue_intr_msix
+ffffffff8172d560 T em_link_intr_msix
+ffffffff8172d680 T em_enable_queue_intr_msix
 ffffffff8172e000 T em_set_mac_type
 ffffffff8172e980 T em_set_media_type
 ffffffff8172eb50 T em_translate_82542_register
@@ -17175,60 +17175,60 @@ ffffffff8188a1a0 T bnxt_hwrm_func_drv_rgtr
 ffffffff8188a2c0 T bnxt_hwrm_func_rgtr_async_events
 ffffffff8188a3e0 T bnxt_hwrm_func_qcaps
 ffffffff8188a4c0 T bnxt_intr
-ffffffff8188a950 T bnxt_hwrm_func_qcfg
-ffffffff8188aa00 T bnxt_hwrm_queue_qportcfg
-ffffffff8188abe0 T bnxt_hwrm_func_reset
-ffffffff8188ac90 T bnxt_mark_cpr_invalid
-ffffffff8188acf0 T bnxt_hwrm_ring_alloc
-ffffffff8188aea0 T bnxt_cfg_async_cr
-ffffffff8188afa0 T bnxt_write_cp_doorbell
-ffffffff8188afe0 T bnxt_hwrm_cmd_hdr_init
-ffffffff8188b030 T hwrm_send_message
-ffffffff8188b0b0 T bnxt_ioctl
-ffffffff8188b310 T bnxt_start
-ffffffff8188b710 T bnxt_watchdog
-ffffffff8188b740 T bnxt_media_change
-ffffffff8188b8a0 T bnxt_media_status
-ffffffff8188b8b0 T bnxt_refill
-ffffffff8188b910 T bnxt_media_autonegotiate
-ffffffff8188ba00 T bnxt_hwrm_port_phy_qcfg
-ffffffff8188bf30 T bnxt_free_slots
-ffffffff8188bfc0 T bnxt_up
-ffffffff8188d1c0 T bnxt_hwrm_stat_ctx_alloc
-ffffffff8188d2c0 T bnxt_write_tx_doorbell
-ffffffff8188d330 T bnxt_write_rx_doorbell
-ffffffff8188d3a0 T bnxt_hwrm_ring_grp_alloc
-ffffffff8188d4b0 T bnxt_hwrm_vnic_ctx_alloc
-ffffffff8188d590 T bnxt_hwrm_vnic_alloc
-ffffffff8188d680 T bnxt_hwrm_vnic_cfg
-ffffffff8188d7c0 T bnxt_hwrm_vnic_cfg_placement
-ffffffff8188d890 T bnxt_hwrm_set_filter
-ffffffff8188da10 T bnxt_iff
-ffffffff8188db80 T bnxt_rx_fill
-ffffffff8188dc80 T bnxt_hwrm_free_filter
-ffffffff8188dd70 T bnxt_hwrm_vnic_free
-ffffffff8188de50 T bnxt_hwrm_vnic_ctx_free
-ffffffff8188df30 T bnxt_hwrm_ring_grp_free
-ffffffff8188e010 T bnxt_hwrm_ring_free
-ffffffff8188e100 T bnxt_hwrm_stat_ctx_free
-ffffffff8188e1f0 T bnxt_down
-ffffffff8188ea30 T bnxt_hwrm_cfa_l2_set_rx_mask
-ffffffff8188eb00 T bnxt_rxrinfo
-ffffffff8188ebe0 T bnxt_get_sffpage
-ffffffff8188eef0 T bnxt_load_mbuf
-ffffffff8188efa0 T bnxt_handle_async_event
-ffffffff8188efe0 T bnxt_cpr_next_cmpl
-ffffffff8188f060 T bnxt_cpr_commit
-ffffffff8188f090 T bnxt_cpr_rollback
-ffffffff8188f0c0 T bnxt_rx
-ffffffff8188f2d0 T bnxt_txeof
-ffffffff8188f3f0 T bnxt_write_cp_doorbell_index
-ffffffff8188f460 T bnxt_get_media_type
-ffffffff8188f9b0 T bnxt_add_media_type
-ffffffff8188fb80 T _hwrm_send_message
-ffffffff818929c0 T bnxt_rx_fill_slots
-ffffffff81892b70 T bnxt_hwrm_err_map
-ffffffff81892bb0 T _bnxt_hwrm_set_async_event_bit
+ffffffff8188a960 T bnxt_hwrm_func_qcfg
+ffffffff8188aa10 T bnxt_hwrm_queue_qportcfg
+ffffffff8188abf0 T bnxt_hwrm_func_reset
+ffffffff8188aca0 T bnxt_mark_cpr_invalid
+ffffffff8188ad00 T bnxt_hwrm_ring_alloc
+ffffffff8188aeb0 T bnxt_cfg_async_cr
+ffffffff8188afb0 T bnxt_write_cp_doorbell
+ffffffff8188aff0 T bnxt_hwrm_cmd_hdr_init
+ffffffff8188b040 T hwrm_send_message
+ffffffff8188b0c0 T bnxt_ioctl
+ffffffff8188b320 T bnxt_start
+ffffffff8188b740 T bnxt_watchdog
+ffffffff8188b770 T bnxt_media_change
+ffffffff8188b8d0 T bnxt_media_status
+ffffffff8188b8e0 T bnxt_refill
+ffffffff8188b940 T bnxt_media_autonegotiate
+ffffffff8188ba30 T bnxt_hwrm_port_phy_qcfg
+ffffffff8188bf60 T bnxt_free_slots
+ffffffff8188bff0 T bnxt_up
+ffffffff8188d1f0 T bnxt_hwrm_stat_ctx_alloc
+ffffffff8188d2f0 T bnxt_write_tx_doorbell
+ffffffff8188d360 T bnxt_write_rx_doorbell
+ffffffff8188d3d0 T bnxt_hwrm_ring_grp_alloc
+ffffffff8188d4e0 T bnxt_hwrm_vnic_ctx_alloc
+ffffffff8188d5c0 T bnxt_hwrm_vnic_alloc
+ffffffff8188d6b0 T bnxt_hwrm_vnic_cfg
+ffffffff8188d7f0 T bnxt_hwrm_vnic_cfg_placement
+ffffffff8188d8c0 T bnxt_hwrm_set_filter
+ffffffff8188da40 T bnxt_iff
+ffffffff8188dbb0 T bnxt_rx_fill
+ffffffff8188dcb0 T bnxt_hwrm_free_filter
+ffffffff8188dda0 T bnxt_hwrm_vnic_free
+ffffffff8188de80 T bnxt_hwrm_vnic_ctx_free
+ffffffff8188df60 T bnxt_hwrm_ring_grp_free
+ffffffff8188e040 T bnxt_hwrm_ring_free
+ffffffff8188e130 T bnxt_hwrm_stat_ctx_free
+ffffffff8188e220 T bnxt_down
+ffffffff8188ea60 T bnxt_hwrm_cfa_l2_set_rx_mask
+ffffffff8188eb30 T bnxt_rxrinfo
+ffffffff8188ec10 T bnxt_get_sffpage
+ffffffff8188ef20 T bnxt_load_mbuf
+ffffffff8188efd0 T bnxt_handle_async_event
+ffffffff8188f010 T bnxt_cpr_next_cmpl
+ffffffff8188f090 T bnxt_cpr_commit
+ffffffff8188f0c0 T bnxt_cpr_rollback
+ffffffff8188f0f0 T bnxt_rx
+ffffffff8188f370 T bnxt_txeof
+ffffffff8188f4a0 T bnxt_write_cp_doorbell_index
+ffffffff8188f510 T bnxt_get_media_type
+ffffffff8188fa60 T bnxt_add_media_type
+ffffffff8188fc30 T _hwrm_send_message
+ffffffff81892a70 T bnxt_rx_fill_slots
+ffffffff81892c20 T bnxt_hwrm_err_map
+ffffffff81892c60 T _bnxt_hwrm_set_async_event_bit
 ffffffff81893000 t mcx_match
 ffffffff81893020 t mcx_attach
 ffffffff81895cb0 T mcx_rx_fill_slots
@@ -24651,72 +24651,72 @@ ffffffff81ce0ad0 t dm_late_init
 ffffffff81ce0cc0 t dm_sw_init
 ffffffff81ce1260 t dm_sw_fini
 ffffffff81ce1350 t dm_hw_init
-ffffffff81ce27d0 t dm_hw_fini
-ffffffff81ce2820 t dm_suspend
-ffffffff81ce28c0 t dm_resume
-ffffffff81ce2cf0 t dm_is_idle
-ffffffff81ce2d20 t dm_wait_for_idle
-ffffffff81ce2d50 t dm_check_soft_reset
-ffffffff81ce2d80 t dm_soft_reset
-ffffffff81ce2db0 t dm_set_clockgating_state
-ffffffff81ce2de0 t dm_set_powergating_state
-ffffffff81ce2e10 t dm_bandwidth_update
-ffffffff81ce2e40 t dm_vblank_get_counter
-ffffffff81ce2eb0 t dm_crtc_get_scanoutpos
-ffffffff81ce2f70 t amdgpu_dm_dmub_reg_read
-ffffffff81ce2fa0 t amdgpu_dm_dmub_reg_write
-ffffffff81ce2fd0 t dm_dmub_hw_init
-ffffffff81ce3310 t amdgpu_dm_fini
-ffffffff81ce3430 t emulated_link_detect
-ffffffff81ce3520 t amdgpu_dm_atomic_check
-ffffffff81ce4820 t amdgpu_dm_atomic_commit
-ffffffff81ce4910 t dm_update_plane_state
-ffffffff81ce5110 t dm_update_crtc_state
-ffffffff81ce58c0 t fill_dc_plane_info_and_addr
-ffffffff81ce5bb0 t amdgpu_bo_reserve
-ffffffff81ce5db0 t amdgpu_bo_unreserve
-ffffffff81ce5e80 t fill_plane_buffer_attributes
-ffffffff81ce62d0 t fill_hdr_info_packet
-ffffffff81ce6430 t update_stream_scaling_settings
-ffffffff81ce6570 t amdgpu_dm_atomic_commit_tail
-ffffffff81ce86e0 t handle_cursor_update
-ffffffff81ce89a0 t dm_atomic_duplicate_state
-ffffffff81ce8a40 t dm_atomic_destroy_state
-ffffffff81ce8a80 t amdgpu_dm_plane_init
-ffffffff81ce8c90 t dm_drm_plane_reset
-ffffffff81ce8d20 t dm_drm_plane_duplicate_state
-ffffffff81ce8db0 t dm_plane_helper_prepare_fb
-ffffffff81ce9020 t dm_plane_helper_cleanup_fb
-ffffffff81ce90b0 t dm_plane_atomic_check
-ffffffff81ce9190 t dm_plane_atomic_async_check
-ffffffff81ce91d0 t dm_plane_atomic_async_update
-ffffffff81ce9280 t dm_crtc_reset_state
-ffffffff81ce9350 t amdgpu_dm_crtc_destroy
-ffffffff81ce9380 t dm_crtc_duplicate_state
-ffffffff81ce9530 t dm_crtc_destroy_state
-ffffffff81ce9570 t dm_enable_vblank
-ffffffff81ce9640 t dm_disable_vblank
-ffffffff81ce96f0 t dm_crtc_helper_mode_fixup
-ffffffff81ce9720 t dm_crtc_helper_disable
-ffffffff81ce9750 t dm_crtc_helper_atomic_check
-ffffffff81ce9930 t amdgpu_dm_encoder_destroy
-ffffffff81ce9960 t amdgpu_dm_i2c_xfer
-ffffffff81ce9aa0 t amdgpu_dm_i2c_func
-ffffffff81ce9ad0 t amdgpu_dm_connector_detect
-ffffffff81ce9b30 t amdgpu_dm_connector_late_register
-ffffffff81ce9b90 t amdgpu_dm_connector_unregister
-ffffffff81ce9bb0 t amdgpu_dm_connector_destroy
-ffffffff81ce9c80 t get_modes
-ffffffff81ce9ff0 t amdgpu_dm_connector_atomic_check
-ffffffff81cea100 t amdgpu_dm_backlight_update_status
-ffffffff81cea270 t amdgpu_dm_backlight_get_brightness
-ffffffff81cea2c0 t dm_crtc_high_irq
-ffffffff81cea4b0 t dm_vupdate_high_irq
-ffffffff81cea640 t dm_pflip_high_irq
-ffffffff81cea8d0 t handle_hpd_irq
-ffffffff81cea9d0 t handle_hpd_rx_irq
-ffffffff81ceac70 t s3_handle_mst
-ffffffff81cead70 t fill_stream_properties_from_drm_display_mode
+ffffffff81ce2850 t dm_hw_fini
+ffffffff81ce28a0 t dm_suspend
+ffffffff81ce2940 t dm_resume
+ffffffff81ce2d70 t dm_is_idle
+ffffffff81ce2da0 t dm_wait_for_idle
+ffffffff81ce2dd0 t dm_check_soft_reset
+ffffffff81ce2e00 t dm_soft_reset
+ffffffff81ce2e30 t dm_set_clockgating_state
+ffffffff81ce2e60 t dm_set_powergating_state
+ffffffff81ce2e90 t dm_bandwidth_update
+ffffffff81ce2ec0 t dm_vblank_get_counter
+ffffffff81ce2f30 t dm_crtc_get_scanoutpos
+ffffffff81ce2ff0 t amdgpu_dm_dmub_reg_read
+ffffffff81ce3020 t amdgpu_dm_dmub_reg_write
+ffffffff81ce3050 t dm_dmub_hw_init
+ffffffff81ce3390 t amdgpu_dm_fini
+ffffffff81ce34c0 t emulated_link_detect
+ffffffff81ce35b0 t amdgpu_dm_atomic_check
+ffffffff81ce48b0 t amdgpu_dm_atomic_commit
+ffffffff81ce49a0 t dm_update_plane_state
+ffffffff81ce51a0 t dm_update_crtc_state
+ffffffff81ce5950 t fill_dc_plane_info_and_addr
+ffffffff81ce5c40 t amdgpu_bo_reserve
+ffffffff81ce5e40 t amdgpu_bo_unreserve
+ffffffff81ce5f10 t fill_plane_buffer_attributes
+ffffffff81ce6360 t fill_hdr_info_packet
+ffffffff81ce64c0 t update_stream_scaling_settings
+ffffffff81ce6600 t amdgpu_dm_atomic_commit_tail
+ffffffff81ce8770 t handle_cursor_update
+ffffffff81ce8a30 t dm_atomic_duplicate_state
+ffffffff81ce8ad0 t dm_atomic_destroy_state
+ffffffff81ce8b10 t amdgpu_dm_plane_init
+ffffffff81ce8d20 t dm_drm_plane_reset
+ffffffff81ce8db0 t dm_drm_plane_duplicate_state
+ffffffff81ce8e40 t dm_plane_helper_prepare_fb
+ffffffff81ce90b0 t dm_plane_helper_cleanup_fb
+ffffffff81ce9140 t dm_plane_atomic_check
+ffffffff81ce9220 t dm_plane_atomic_async_check
+ffffffff81ce9260 t dm_plane_atomic_async_update
+ffffffff81ce9310 t dm_crtc_reset_state
+ffffffff81ce93e0 t amdgpu_dm_crtc_destroy
+ffffffff81ce9410 t dm_crtc_duplicate_state
+ffffffff81ce95c0 t dm_crtc_destroy_state
+ffffffff81ce9600 t dm_enable_vblank
+ffffffff81ce96d0 t dm_disable_vblank
+ffffffff81ce9780 t dm_crtc_helper_mode_fixup
+ffffffff81ce97b0 t dm_crtc_helper_disable
+ffffffff81ce97e0 t dm_crtc_helper_atomic_check
+ffffffff81ce99c0 t amdgpu_dm_encoder_destroy
+ffffffff81ce99f0 t amdgpu_dm_i2c_xfer
+ffffffff81ce9b30 t amdgpu_dm_i2c_func
+ffffffff81ce9b60 t amdgpu_dm_connector_detect
+ffffffff81ce9bc0 t amdgpu_dm_connector_late_register
+ffffffff81ce9c20 t amdgpu_dm_connector_unregister
+ffffffff81ce9c40 t amdgpu_dm_connector_destroy
+ffffffff81ce9d10 t get_modes
+ffffffff81cea080 t amdgpu_dm_connector_atomic_check
+ffffffff81cea190 t amdgpu_dm_backlight_update_status
+ffffffff81cea300 t amdgpu_dm_backlight_get_brightness
+ffffffff81cea350 t dm_crtc_high_irq
+ffffffff81cea540 t dm_vupdate_high_irq
+ffffffff81cea6d0 t dm_pflip_high_irq
+ffffffff81cea960 t handle_hpd_irq
+ffffffff81ceaa60 t handle_hpd_rx_irq
+ffffffff81cead00 t s3_handle_mst
+ffffffff81ceae00 t fill_stream_properties_from_drm_display_mode
 ffffffff81cec000 T amdgpu_dm_init_color_mod
 ffffffff81cec010 T amdgpu_dm_update_crtc_color_mgmt
 ffffffff81cec5a0 T amdgpu_dm_update_plane_color_mgmt
@@ -31252,15 +31252,15 @@ ffffffff820aa6f0 T axe_tick_task
 ffffffff820aa7a0 T axe_stop
 ffffffff820aa9a0 T axe_ioctl
 ffffffff820aaaf0 T axe_start
-ffffffff820aabd0 T axe_watchdog
-ffffffff820aac80 T axe_tick
-ffffffff820aacf0 T axe_newbuf
-ffffffff820aad80 T axe_rx_list_init
-ffffffff820aae30 T axe_tx_list_init
-ffffffff820aaee0 T axe_rxeof
-ffffffff820ab180 T axe_txeof
-ffffffff820ab2a0 T axe_encap
-ffffffff820ab400 T axe_init
+ffffffff820aabb0 T axe_watchdog
+ffffffff820aace0 T axe_tick
+ffffffff820aad50 T axe_newbuf
+ffffffff820aade0 T axe_rx_list_init
+ffffffff820aae90 T axe_tx_list_init
+ffffffff820aaf40 T axe_rxeof
+ffffffff820ab1e0 T axe_txeof
+ffffffff820ab380 T axe_encap
+ffffffff820ab4f0 T axe_init
 ffffffff820ac000 T axen_match
 ffffffff820ac070 T axen_attach
 ffffffff820ac490 T axen_detach
@@ -31279,15 +31279,15 @@ ffffffff820ad4a0 T axen_tick_task
 ffffffff820ad550 T axen_stop
 ffffffff820ad750 T axen_ioctl
 ffffffff820ad8a0 T axen_start
-ffffffff820ad980 T axen_watchdog
-ffffffff820ada30 T axen_tick
-ffffffff820adaa0 T axen_newbuf
-ffffffff820adb30 T axen_rx_list_init
-ffffffff820adbe0 T axen_tx_list_init
-ffffffff820adc90 T axen_rxeof
-ffffffff820adff0 T axen_txeof
-ffffffff820ae110 T axen_encap
-ffffffff820ae260 T axen_init
+ffffffff820ad960 T axen_watchdog
+ffffffff820ada90 T axen_tick
+ffffffff820adb00 T axen_newbuf
+ffffffff820adb90 T axen_rx_list_init
+ffffffff820adc40 T axen_tx_list_init
+ffffffff820adcf0 T axen_rxeof
+ffffffff820ae050 T axen_txeof
+ffffffff820ae1f0 T axen_encap
+ffffffff820ae350 T axen_init
 ffffffff820af000 T smsc_match
 ffffffff820af070 T smsc_attach
 ffffffff820af440 T smsc_detach
@@ -31312,11 +31312,11 @@ ffffffff820b0fb0 T smsc_rx_list_init
 ffffffff820b1060 T smsc_tx_list_init
 ffffffff820b1110 T smsc_rxeof
 ffffffff820b1310 T smsc_start
-ffffffff820b13d0 T smsc_encap
-ffffffff820b14e0 T smsc_tick
-ffffffff820b1540 T smsc_ioctl
-ffffffff820b1690 T smsc_tick_task
-ffffffff820b1740 T smsc_txeof
+ffffffff820b13b0 T smsc_encap
+ffffffff820b14d0 T smsc_tick
+ffffffff820b1530 T smsc_ioctl
+ffffffff820b1680 T smsc_tick_task
+ffffffff820b1730 T smsc_txeof
 ffffffff820b2000 T cue_match
 ffffffff820b2070 T cue_attach
 ffffffff820b2300 T cue_detach
@@ -31352,14 +31352,14 @@ ffffffff820b45d0 T kue_setmulti
 ffffffff820b4790 T kue_attachhook
 ffffffff820b4a60 T kue_ioctl
 ffffffff820b4c50 T kue_start
-ffffffff820b4d30 T kue_watchdog
-ffffffff820b4df0 T kue_stop
-ffffffff820b4fb0 T kue_newbuf
-ffffffff820b50a0 T kue_rx_list_init
-ffffffff820b51c0 T kue_tx_list_init
-ffffffff820b5260 T kue_rxeof
-ffffffff820b54c0 T kue_txeof
-ffffffff820b55e0 T kue_send
+ffffffff820b4d20 T kue_watchdog
+ffffffff820b4de0 T kue_stop
+ffffffff820b4fa0 T kue_newbuf
+ffffffff820b5090 T kue_rx_list_init
+ffffffff820b51b0 T kue_tx_list_init
+ffffffff820b5250 T kue_rxeof
+ffffffff820b54b0 T kue_txeof
+ffffffff820b55d0 T kue_send
 ffffffff820b5720 T kue_init
 ffffffff820b58d0 T kue_open_pipes
 ffffffff820b6000 T cdce_match
@@ -31367,9 +31367,9 @@ ffffffff820b60a0 T cdce_attach
 ffffffff820b6650 T cdce_detach
 ffffffff820b66e0 T cdce_ioctl
 ffffffff820b67f0 T cdce_start
-ffffffff820b68d0 T cdce_watchdog
-ffffffff820b6950 T cdce_stop
-ffffffff820b6b10 T cdce_encap
+ffffffff820b68c0 T cdce_watchdog
+ffffffff820b6940 T cdce_stop
+ffffffff820b6b00 T cdce_encap
 ffffffff820b6c30 T cdce_txeof
 ffffffff820b6d60 T cdce_init
 ffffffff820b6ff0 T cdce_intr
@@ -31394,16 +31394,16 @@ ffffffff820b9030 T urndis_ctrl_halt
 ffffffff820b9170 T urndis_ctrl_query
 ffffffff820b9330 T urndis_ctrl_set_param
 ffffffff820b94a0 T urndis_encap
-ffffffff820b95e0 T urndis_txeof
-ffffffff820b96f0 T urndis_stop
-ffffffff820b9860 T urndis_decap
-ffffffff820b9a80 T urndis_newbuf
-ffffffff820b9b50 T urndis_rx_list_init
-ffffffff820b9c00 T urndis_tx_list_init
-ffffffff820b9ca0 T urndis_ioctl
-ffffffff820b9db0 T urndis_init
-ffffffff820b9ff0 T urndis_rxeof
-ffffffff820ba100 T urndis_start
+ffffffff820b95f0 T urndis_txeof
+ffffffff820b9700 T urndis_stop
+ffffffff820b9870 T urndis_decap
+ffffffff820b9a90 T urndis_newbuf
+ffffffff820b9b60 T urndis_rx_list_init
+ffffffff820b9c10 T urndis_tx_list_init
+ffffffff820b9cb0 T urndis_ioctl
+ffffffff820b9dc0 T urndis_init
+ffffffff820ba000 T urndis_rxeof
+ffffffff820ba110 T urndis_start
 ffffffff820ba1e0 T urndis_lookup
 ffffffff820bb000 T mos_match
 ffffffff820bb070 T mos_attach
@@ -31437,7 +31437,7 @@ ffffffff820bcc90 T mos_tx_list_init
 ffffffff820bcd40 T mos_rxeof
 ffffffff820bcf70 T mos_txeof
 ffffffff820bd090 T mos_encap
-ffffffff820bd170 T mos_init
+ffffffff820bd180 T mos_init
 ffffffff820be000 T mue_match
 ffffffff820be070 T mue_attach
 ffffffff820be470 T mue_detach
@@ -31463,17 +31463,17 @@ ffffffff820c0a50 T mue_tick_task
 ffffffff820c0b00 T mue_stop
 ffffffff820c0cd0 T mue_ioctl
 ffffffff820c0e20 T mue_start
-ffffffff820c0f00 T mue_watchdog
-ffffffff820c0fb0 T mue_tick
-ffffffff820c1020 T mue_rx_list_init
-ffffffff820c10d0 T mue_tx_list_init
-ffffffff820c1180 T mue_open_pipes
-ffffffff820c1290 T mue_rxeof
-ffffffff820c1490 T mue_encap
-ffffffff820c15a0 T mue_txeof
-ffffffff820c16c0 T mue_iff
-ffffffff820c18f0 T mue_init
-ffffffff820c1aa0 T mue_reset
+ffffffff820c0ee0 T mue_watchdog
+ffffffff820c1010 T mue_tick
+ffffffff820c1080 T mue_rx_list_init
+ffffffff820c1130 T mue_tx_list_init
+ffffffff820c11e0 T mue_open_pipes
+ffffffff820c12f0 T mue_rxeof
+ffffffff820c14f0 T mue_encap
+ffffffff820c1610 T mue_txeof
+ffffffff820c17b0 T mue_iff
+ffffffff820c19e0 T mue_init
+ffffffff820c1b90 T mue_reset
 ffffffff820c2000 T udav_match
 ffffffff820c2070 T udav_attach
 ffffffff820c2450 T udav_detach
@@ -31510,15 +31510,15 @@ ffffffff820c5070 T upl_attach
 ffffffff820c5280 T upl_detach
 ffffffff820c5330 T upl_ioctl
 ffffffff820c5450 T upl_start
-ffffffff820c5530 T upl_watchdog
-ffffffff820c55d0 T upl_output
-ffffffff820c55e0 T upl_stop
-ffffffff820c57a0 T upl_newbuf
-ffffffff820c5890 T upl_rx_list_init
-ffffffff820c59c0 T upl_tx_list_init
-ffffffff820c5a70 T upl_rxeof
-ffffffff820c5ca0 T upl_txeof
-ffffffff820c5dc0 T upl_send
+ffffffff820c5520 T upl_watchdog
+ffffffff820c55c0 T upl_output
+ffffffff820c55d0 T upl_stop
+ffffffff820c5790 T upl_newbuf
+ffffffff820c5880 T upl_rx_list_init
+ffffffff820c59b0 T upl_tx_list_init
+ffffffff820c5a60 T upl_rxeof
+ffffffff820c5c90 T upl_txeof
+ffffffff820c5db0 T upl_send
 ffffffff820c5ed0 T upl_init
 ffffffff820c6010 T upl_openpipes
 ffffffff820c6170 T upl_intr
@@ -31527,14 +31527,14 @@ ffffffff820c7070 T ugl_attach
 ffffffff820c7230 T ugl_detach
 ffffffff820c72e0 T ugl_ioctl
 ffffffff820c73f0 T ugl_start
-ffffffff820c74d0 T ugl_watchdog
-ffffffff820c7550 T ugl_stop
-ffffffff820c7680 T ugl_newbuf
-ffffffff820c7770 T ugl_rx_list_init
-ffffffff820c78a0 T ugl_tx_list_init
-ffffffff820c7950 T ugl_rxeof
-ffffffff820c7c00 T ugl_txeof
-ffffffff820c7d20 T ugl_send
+ffffffff820c74c0 T ugl_watchdog
+ffffffff820c7540 T ugl_stop
+ffffffff820c7670 T ugl_newbuf
+ffffffff820c7760 T ugl_rx_list_init
+ffffffff820c7890 T ugl_tx_list_init
+ffffffff820c7940 T ugl_rxeof
+ffffffff820c7bf0 T ugl_txeof
+ffffffff820c7d10 T ugl_send
 ffffffff820c7e50 T ugl_init
 ffffffff820c7f90 T ugl_openpipes
 ffffffff820c80f0 T ugl_intr
@@ -31607,7 +31607,7 @@ ffffffff820cf790 T ure_rx_list_init
 ffffffff820cf840 T ure_tx_list_init
 ffffffff820cf920 T ure_rxeof
 ffffffff820cfbc0 T ure_start
-ffffffff820cfcd0 T ure_encap
+ffffffff820cfcc0 T ure_encap
 ffffffff820cfe30 T ure_tick
 ffffffff820cfe90 T ure_rtl8152_init
 ffffffff820d0230 T ure_rtl8153_init
@@ -38392,47 +38392,47 @@ ffffffff827900b0 R version
 ffffffff82791000 R codepatch_begin
 ffffffff82799000 R codepatch_end
 ffffffff8279d8e2 r cmd0646_9_tim_udma
-ffffffff827e139c r pp_r600_decoded_lanes
-ffffffff827fb396 r cmd680_setup_channel.udma_tbl
-ffffffff8280216e r apollo_udma33_tim
-ffffffff82804fae r substchar
-ffffffff82808e51 r apollo_udma100_tim
-ffffffff8282a27c r apollo_udma66_tim
-ffffffff828306cc r apollo_pio_rec
-ffffffff8283d6e2 r cy_pio_rec
-ffffffff8286665f r apollo_udma133_tim
-ffffffff8286f1b0 r acx100_txpower_maxim
-ffffffff8286f1d0 r hangpic
-ffffffff8286f210 r digits
-ffffffff8286f210 r pppdumpb.digits
-ffffffff8286f210 r pppdumpm.digits
-ffffffff8286f260 r bwi_rf_calc_nrssi_slope_11b.save_phy_regs
-ffffffff8286f280 r fiji_clock_stretcher_lookup_table
-ffffffff8286f280 r tonga_clock_stretcher_lookup_table
-ffffffff8286f300 r amdgpu_device_ip_reinit_early_sriov.ip_order
-ffffffff8286f360 r rtwn_iq_calib_run.adda_92e
-ffffffff8286f400 r bwi_phy_noise_11g_rev1
-ffffffff8286f410 r cardslot_process_event.antonym_ev
-ffffffff8286f500 r arcturus_pwr_src_map
-ffffffff8286f500 r navi10_pwr_src_map
-ffffffff8286f500 r vega20_pwr_src_map
-ffffffff8286f5f0 r rtwn_iq_calib_run.adda_92c
-ffffffff8286f600 r ddr2_cycle_tenths
-ffffffff8286f660 r rtw_intr_rx.ratetbl
-ffffffff8286f680 r abm_config
-ffffffff8286f6e0 r reg_offsets
-ffffffff8286f720 r getbootinfo.ports
-ffffffff8286f730 r bwi_rf_lo_measure_11g.rf_lo_adjust
-ffffffff8286f740 r init_non_clock_fields.look_up
-ffffffff8286f750 r uftdi_8u232am_getrate.roundoff
-ffffffff8286f780 r zyd_rx_data.rates
-ffffffff8286f7c0 r ieee80211_mira_valid_tx_mcs.max_mcs
-ffffffff8286f7f0 r bwi_phy_noise_11g
-ffffffff8286f830 r hpt366_pio
-ffffffff8286f860 r bwi_rf_calc_nrssi_slope_11g.save_phy3_regs
-ffffffff8286f890 r ether_crc32_be_update.rev
-ffffffff8286f890 r rtw_grf5101_mac_crypt.caesar
-ffffffff8286f8e0 r snb_b_fdi_train_param
+ffffffff827e1387 r pp_r600_decoded_lanes
+ffffffff827fb381 r cmd680_setup_channel.udma_tbl
+ffffffff82802159 r apollo_udma33_tim
+ffffffff82804f99 r substchar
+ffffffff82808e3c r apollo_udma100_tim
+ffffffff8282a273 r apollo_udma66_tim
+ffffffff828306c3 r apollo_pio_rec
+ffffffff8283d6c4 r cy_pio_rec
+ffffffff82866641 r apollo_udma133_tim
+ffffffff8286f1a0 r acx100_txpower_maxim
+ffffffff8286f1c0 r hangpic
+ffffffff8286f200 r digits
+ffffffff8286f200 r pppdumpb.digits
+ffffffff8286f200 r pppdumpm.digits
+ffffffff8286f250 r bwi_rf_calc_nrssi_slope_11b.save_phy_regs
+ffffffff8286f270 r fiji_clock_stretcher_lookup_table
+ffffffff8286f270 r tonga_clock_stretcher_lookup_table
+ffffffff8286f2f0 r amdgpu_device_ip_reinit_early_sriov.ip_order
+ffffffff8286f350 r rtwn_iq_calib_run.adda_92e
+ffffffff8286f3f0 r bwi_phy_noise_11g_rev1
+ffffffff8286f400 r cardslot_process_event.antonym_ev
+ffffffff8286f4f0 r arcturus_pwr_src_map
+ffffffff8286f4f0 r navi10_pwr_src_map
+ffffffff8286f4f0 r vega20_pwr_src_map
+ffffffff8286f5e0 r rtwn_iq_calib_run.adda_92c
+ffffffff8286f5f0 r ddr2_cycle_tenths
+ffffffff8286f650 r rtw_intr_rx.ratetbl
+ffffffff8286f670 r abm_config
+ffffffff8286f6d0 r reg_offsets
+ffffffff8286f710 r getbootinfo.ports
+ffffffff8286f720 r bwi_rf_lo_measure_11g.rf_lo_adjust
+ffffffff8286f730 r init_non_clock_fields.look_up
+ffffffff8286f740 r uftdi_8u232am_getrate.roundoff
+ffffffff8286f770 r zyd_rx_data.rates
+ffffffff8286f7b0 r ieee80211_mira_valid_tx_mcs.max_mcs
+ffffffff8286f7e0 r bwi_phy_noise_11g
+ffffffff8286f820 r hpt366_pio
+ffffffff8286f850 r bwi_rf_calc_nrssi_slope_11g.save_phy3_regs
+ffffffff8286f880 r ether_crc32_be_update.rev
+ffffffff8286f880 r rtw_grf5101_mac_crypt.caesar
+ffffffff8286f8d0 r snb_b_fdi_train_param
 ffffffff8286f940 r pin_offsets
 ffffffff8286f9a0 r intel_hpll_vco.elk_vco
 ffffffff8286fa00 r atom_arg_shift